JP2004501517A5 - - Google Patents
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- JP2004501517A5 JP2004501517A5 JP2002504502A JP2002504502A JP2004501517A5 JP 2004501517 A5 JP2004501517 A5 JP 2004501517A5 JP 2002504502 A JP2002504502 A JP 2002504502A JP 2002504502 A JP2002504502 A JP 2002504502A JP 2004501517 A5 JP2004501517 A5 JP 2004501517A5
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Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US21292300P | 2000-06-20 | 2000-06-20 | |
US21372900P | 2000-06-22 | 2000-06-22 | |
PCT/US2001/019792 WO2001098793A2 (en) | 2000-06-20 | 2001-06-20 | Systems for testing integraged circuits during burn-in |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2004501517A JP2004501517A (ja) | 2004-01-15 |
JP2004501517A5 true JP2004501517A5 (ja) | 2008-07-24 |
Family
ID=26907616
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2002504502A Pending JP2004501517A (ja) | 2000-06-20 | 2001-06-20 | 集積回路をテスト及びパッケージングするためのシステム |
Country Status (8)
Country | Link |
---|---|
US (1) | US6791171B2 (ja) |
EP (1) | EP1292834B1 (ja) |
JP (1) | JP2004501517A (ja) |
KR (1) | KR20020026585A (ja) |
AT (1) | ATE311604T1 (ja) |
AU (1) | AU2001268630A1 (ja) |
DE (1) | DE60115437T2 (ja) |
WO (1) | WO2001098793A2 (ja) |
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2001
- 2001-06-20 JP JP2002504502A patent/JP2004501517A/ja active Pending
- 2001-06-20 DE DE60115437T patent/DE60115437T2/de not_active Expired - Fee Related
- 2001-06-20 WO PCT/US2001/019792 patent/WO2001098793A2/en active IP Right Grant
- 2001-06-20 US US10/069,902 patent/US6791171B2/en not_active Expired - Fee Related
- 2001-06-20 KR KR1020027002170A patent/KR20020026585A/ko not_active Application Discontinuation
- 2001-06-20 EP EP01946604A patent/EP1292834B1/en not_active Expired - Lifetime
- 2001-06-20 AT AT01946604T patent/ATE311604T1/de not_active IP Right Cessation
- 2001-06-20 AU AU2001268630A patent/AU2001268630A1/en not_active Abandoned