JP2004111479A - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
JP2004111479A
JP2004111479A JP2002268970A JP2002268970A JP2004111479A JP 2004111479 A JP2004111479 A JP 2004111479A JP 2002268970 A JP2002268970 A JP 2002268970A JP 2002268970 A JP2002268970 A JP 2002268970A JP 2004111479 A JP2004111479 A JP 2004111479A
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JP
Japan
Prior art keywords
film
forming
gate electrode
semiconductor device
insulating film
Prior art date
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Pending
Application number
JP2002268970A
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English (en)
Japanese (ja)
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JP2004111479A5 (enExample
Inventor
Mitsuaki Dewa
出羽　光明
Toshihiko Iinuma
飯沼　俊彦
Kyoichi Suguro
須黒　恭一
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Toshiba Corp
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Toshiba Corp
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Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2002268970A priority Critical patent/JP2004111479A/ja
Priority to CNB031567274A priority patent/CN1252834C/zh
Priority to KR10-2003-0062948A priority patent/KR100508840B1/ko
Priority to TW092125040A priority patent/TW200406849A/zh
Priority to US10/660,555 priority patent/US20040113209A1/en
Publication of JP2004111479A publication Critical patent/JP2004111479A/ja
Publication of JP2004111479A5 publication Critical patent/JP2004111479A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H10P10/00—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H10D64/01314—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2002268970A 2002-09-13 2002-09-13 半導体装置及びその製造方法 Pending JP2004111479A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2002268970A JP2004111479A (ja) 2002-09-13 2002-09-13 半導体装置及びその製造方法
CNB031567274A CN1252834C (zh) 2002-09-13 2003-09-08 用自对准硅化物工艺形成的mosfet及其制造方法
KR10-2003-0062948A KR100508840B1 (ko) 2002-09-13 2003-09-09 살리사이드 프로세스를 이용하여 형성된 ｍｏｓｆｅｔ 및그 제조 방법
TW092125040A TW200406849A (en) 2002-09-13 2003-09-10 MOSFET formed by self-aligned silicide process and method for producing the same
US10/660,555 US20040113209A1 (en) 2002-09-13 2003-09-12 MOSFET formed by using salicide process and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002268970A JP2004111479A (ja) 2002-09-13 2002-09-13 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
JP2004111479A true JP2004111479A (ja) 2004-04-08
JP2004111479A5 JP2004111479A5 (enExample) 2005-02-10

Family

ID=32267040

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002268970A Pending JP2004111479A (ja) 2002-09-13 2002-09-13 半導体装置及びその製造方法

Country Status (5)

Country Link
US (1) US20040113209A1 (enExample)
JP (1) JP2004111479A (enExample)
KR (1) KR100508840B1 (enExample)
CN (1) CN1252834C (enExample)
TW (1) TW200406849A (enExample)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005112089A1 (ja) * 2004-05-17 2005-11-24 Fujitsu Limited 半導体装置及びその製造方法
KR100731096B1 (ko) 2005-12-28 2007-06-22 동부일렉트로닉스 주식회사 반도체 소자 및 이의 제조방법
JP2007291485A (ja) * 2006-04-27 2007-11-08 Fujitsu Ltd 成膜方法、半導体装置の製造方法、コンピュータ可読記録媒体、スパッタ処理装置
JP2009529803A (ja) * 2006-03-31 2009-08-20 インテル コーポレイション 電界効果型トランジスタにおけるコンタクト抵抗を減少させるエピタキシャルシリコンゲルマニウム
CN110571190A (zh) * 2018-06-05 2019-12-13 中芯国际集成电路制造(上海)有限公司 接触插塞的形成方法和刻蚀方法

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1700478A (zh) * 2004-05-17 2005-11-23 富士通株式会社 半导体器件及其制造方法
KR100678314B1 (ko) * 2004-12-15 2007-02-02 동부일렉트로닉스 주식회사 저접촉저항을 갖는 반도체 소자의 제조방법
US8258057B2 (en) * 2006-03-30 2012-09-04 Intel Corporation Copper-filled trench contact for transistor performance improvement
JP2008071890A (ja) * 2006-09-13 2008-03-27 Toshiba Corp 半導体装置及びその製造方法
JP5309454B2 (ja) * 2006-10-11 2013-10-09 富士通セミコンダクター株式会社 半導体装置の製造方法
JP2008141003A (ja) * 2006-12-01 2008-06-19 Toshiba Corp 半導体装置の製造方法
JP5211503B2 (ja) * 2007-02-16 2013-06-12 富士通セミコンダクター株式会社 半導体装置の製造方法
TW200910526A (en) * 2007-07-03 2009-03-01 Renesas Tech Corp Method of manufacturing semiconductor device
CN102446970B (zh) * 2011-08-29 2014-05-28 上海华力微电子有限公司 一种防止酸槽清洗空洞形成的半导体器件及其制备方法
US11222820B2 (en) * 2018-06-27 2022-01-11 International Business Machines Corporation Self-aligned gate cap including an etch-stop layer

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2740087B2 (ja) * 1992-08-15 1998-04-15 株式会社東芝 半導体集積回路装置の製造方法
US5427964A (en) * 1994-04-04 1995-06-27 Motorola, Inc. Insulated gate field effect transistor and method for fabricating
JP3219996B2 (ja) * 1995-03-27 2001-10-15 株式会社東芝 半導体装置及びその製造方法
JP3199015B2 (ja) * 1998-02-04 2001-08-13 日本電気株式会社 半導体装置及びその製造方法
US6063680A (en) * 1998-02-19 2000-05-16 Texas Instruments - Acer Incorporated MOSFETS with a recessed self-aligned silicide contact and an extended source/drain junction
JP3547419B2 (ja) * 2001-03-13 2004-07-28 株式会社東芝 半導体装置及びその製造方法
US6506637B2 (en) * 2001-03-23 2003-01-14 Sharp Laboratories Of America, Inc. Method to form thermally stable nickel germanosilicide on SiGe
TWI284348B (en) * 2002-07-01 2007-07-21 Macronix Int Co Ltd Method for fabricating raised source/drain of semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005112089A1 (ja) * 2004-05-17 2005-11-24 Fujitsu Limited 半導体装置及びその製造方法
JPWO2005112089A1 (ja) * 2004-05-17 2008-03-27 富士通株式会社 半導体装置及びその製造方法
KR100731096B1 (ko) 2005-12-28 2007-06-22 동부일렉트로닉스 주식회사 반도체 소자 및 이의 제조방법
JP2009529803A (ja) * 2006-03-31 2009-08-20 インテル コーポレイション 電界効果型トランジスタにおけるコンタクト抵抗を減少させるエピタキシャルシリコンゲルマニウム
JP2007291485A (ja) * 2006-04-27 2007-11-08 Fujitsu Ltd 成膜方法、半導体装置の製造方法、コンピュータ可読記録媒体、スパッタ処理装置
CN110571190A (zh) * 2018-06-05 2019-12-13 中芯国际集成电路制造(上海)有限公司 接触插塞的形成方法和刻蚀方法

Also Published As

Publication number Publication date
KR100508840B1 (ko) 2005-08-18
TW200406849A (en) 2004-05-01
US20040113209A1 (en) 2004-06-17
CN1252834C (zh) 2006-04-19
KR20040024501A (ko) 2004-03-20
CN1495911A (zh) 2004-05-12

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