KR100508840B1 - 살리사이드 프로세스를 이용하여 형성된 ｍｏｓｆｅｔ 및그 제조 방법 - Google Patents

살리사이드 프로세스를 이용하여 형성된 ｍｏｓｆｅｔ 및그 제조 방법 Download PDF

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Publication number
KR100508840B1
KR100508840B1 KR10-2003-0062948A KR20030062948A KR100508840B1 KR 100508840 B1 KR100508840 B1 KR 100508840B1 KR 20030062948 A KR20030062948 A KR 20030062948A KR 100508840 B1 KR100508840 B1 KR 100508840B1
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South Korea
Prior art keywords
film
gate electrode
source
insulating film
forming
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Expired - Fee Related
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KR10-2003-0062948A
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English (en)
Korean (ko)
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KR20040024501A (ko
Inventor
이즈하미쯔아끼
이이누마도시히꼬
스구로교이찌
Original Assignee
가부시끼가이샤 도시바
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Publication of KR20040024501A publication Critical patent/KR20040024501A/ko
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Publication of KR100508840B1 publication Critical patent/KR100508840B1/ko
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01314—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of Ge, C or of compounds of Si, Ge or C contacting the insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
KR10-2003-0062948A 2002-09-13 2003-09-09 살리사이드 프로세스를 이용하여 형성된 ｍｏｓｆｅｔ 및그 제조 방법 Expired - Fee Related KR100508840B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2002-00268970 2002-09-13
JP2002268970A JP2004111479A (ja) 2002-09-13 2002-09-13 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
KR20040024501A KR20040024501A (ko) 2004-03-20
KR100508840B1 true KR100508840B1 (ko) 2005-08-18

Family

ID=32267040

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2003-0062948A Expired - Fee Related KR100508840B1 (ko) 2002-09-13 2003-09-09 살리사이드 프로세스를 이용하여 형성된 ｍｏｓｆｅｔ 및그 제조 방법

Country Status (5)

Country Link
US (1) US20040113209A1 (enExample)
JP (1) JP2004111479A (enExample)
KR (1) KR100508840B1 (enExample)
CN (1) CN1252834C (enExample)
TW (1) TW200406849A (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1700478A (zh) * 2004-05-17 2005-11-23 富士通株式会社 半导体器件及其制造方法
US20050253205A1 (en) * 2004-05-17 2005-11-17 Fujitsu Limited Semiconductor device and method for fabricating the same
KR100678314B1 (ko) * 2004-12-15 2007-02-02 동부일렉트로닉스 주식회사 저접촉저항을 갖는 반도체 소자의 제조방법
KR100731096B1 (ko) 2005-12-28 2007-06-22 동부일렉트로닉스 주식회사 반도체 소자 및 이의 제조방법
US8258057B2 (en) * 2006-03-30 2012-09-04 Intel Corporation Copper-filled trench contact for transistor performance improvement
US7566605B2 (en) * 2006-03-31 2009-07-28 Intel Corporation Epitaxial silicon germanium for reduced contact resistance in field-effect transistors
JP4983087B2 (ja) * 2006-04-27 2012-07-25 富士通セミコンダクター株式会社 成膜方法、半導体装置の製造方法、コンピュータ可読記録媒体、スパッタ処理装置
JP2008071890A (ja) * 2006-09-13 2008-03-27 Toshiba Corp 半導体装置及びその製造方法
JP5309454B2 (ja) * 2006-10-11 2013-10-09 富士通セミコンダクター株式会社 半導体装置の製造方法
JP2008141003A (ja) * 2006-12-01 2008-06-19 Toshiba Corp 半導体装置の製造方法
JP5211503B2 (ja) * 2007-02-16 2013-06-12 富士通セミコンダクター株式会社 半導体装置の製造方法
TW200910526A (en) 2007-07-03 2009-03-01 Renesas Tech Corp Method of manufacturing semiconductor device
CN102446970B (zh) * 2011-08-29 2014-05-28 上海华力微电子有限公司 一种防止酸槽清洗空洞形成的半导体器件及其制备方法
CN110571190B (zh) * 2018-06-05 2022-02-08 中芯国际集成电路制造(上海)有限公司 接触插塞的形成方法和刻蚀方法
US11222820B2 (en) * 2018-06-27 2022-01-11 International Business Machines Corporation Self-aligned gate cap including an etch-stop layer

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2740087B2 (ja) * 1992-08-15 1998-04-15 株式会社東芝 半導体集積回路装置の製造方法
US5427964A (en) * 1994-04-04 1995-06-27 Motorola, Inc. Insulated gate field effect transistor and method for fabricating
JP3219996B2 (ja) * 1995-03-27 2001-10-15 株式会社東芝 半導体装置及びその製造方法
JP3199015B2 (ja) * 1998-02-04 2001-08-13 日本電気株式会社 半導体装置及びその製造方法
US6063680A (en) * 1998-02-19 2000-05-16 Texas Instruments - Acer Incorporated MOSFETS with a recessed self-aligned silicide contact and an extended source/drain junction
JP3547419B2 (ja) * 2001-03-13 2004-07-28 株式会社東芝 半導体装置及びその製造方法
US6506637B2 (en) * 2001-03-23 2003-01-14 Sharp Laboratories Of America, Inc. Method to form thermally stable nickel germanosilicide on SiGe
TWI284348B (en) * 2002-07-01 2007-07-21 Macronix Int Co Ltd Method for fabricating raised source/drain of semiconductor device

Also Published As

Publication number Publication date
CN1495911A (zh) 2004-05-12
TW200406849A (en) 2004-05-01
CN1252834C (zh) 2006-04-19
JP2004111479A (ja) 2004-04-08
US20040113209A1 (en) 2004-06-17
KR20040024501A (ko) 2004-03-20

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