JP2003503847A5 - - Google Patents

Download PDF

Info

Publication number
JP2003503847A5
JP2003503847A5 JP2001506596A JP2001506596A JP2003503847A5 JP 2003503847 A5 JP2003503847 A5 JP 2003503847A5 JP 2001506596 A JP2001506596 A JP 2001506596A JP 2001506596 A JP2001506596 A JP 2001506596A JP 2003503847 A5 JP2003503847 A5 JP 2003503847A5
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001506596A
Other versions
JP2003503847A (ja
JP5249483B2 (ja
Filing date
Publication date
Priority claimed from US09/340,697 external-priority patent/US6396158B1/en
Application filed filed Critical
Publication of JP2003503847A publication Critical patent/JP2003503847A/ja
Publication of JP2003503847A5 publication Critical patent/JP2003503847A5/ja
Application granted granted Critical
Publication of JP5249483B2 publication Critical patent/JP5249483B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

JP2001506596A 1999-06-29 2000-05-24 半導体デバイス及びマスク設計方法 Expired - Lifetime JP5249483B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/340,697 1999-06-29
US09/340,697 US6396158B1 (en) 1999-06-29 1999-06-29 Semiconductor device and a process for designing a mask
PCT/US2000/014293 WO2001001469A2 (en) 1999-06-29 2000-05-24 Process for designing a mask

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2011174607A Division JP2011228750A (ja) 1999-06-29 2011-08-10 半導体デバイス及びマスク設計方法

Publications (3)

Publication Number Publication Date
JP2003503847A JP2003503847A (ja) 2003-01-28
JP2003503847A5 true JP2003503847A5 (ja) 2007-09-13
JP5249483B2 JP5249483B2 (ja) 2013-07-31

Family

ID=23334550

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2001506596A Expired - Lifetime JP5249483B2 (ja) 1999-06-29 2000-05-24 半導体デバイス及びマスク設計方法
JP2011174607A Pending JP2011228750A (ja) 1999-06-29 2011-08-10 半導体デバイス及びマスク設計方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2011174607A Pending JP2011228750A (ja) 1999-06-29 2011-08-10 半導体デバイス及びマスク設計方法

Country Status (7)

Country Link
US (2) US6396158B1 (ja)
EP (1) EP1196948A2 (ja)
JP (2) JP5249483B2 (ja)
KR (1) KR100722177B1 (ja)
CN (1) CN1274013C (ja)
TW (1) TW523831B (ja)
WO (1) WO2001001469A2 (ja)

Families Citing this family (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100530296B1 (ko) * 2000-03-07 2005-11-22 마이크론 테크놀로지, 인크. 집적 회로 내에 거의 평탄한 유전체막을 제조하는 방법
JP4843129B2 (ja) * 2000-06-30 2011-12-21 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP3806016B2 (ja) * 2000-11-30 2006-08-09 富士通株式会社 半導体集積回路
US6486066B2 (en) * 2001-02-02 2002-11-26 Matrix Semiconductor, Inc. Method of generating integrated circuit feature layout for improved chemical mechanical polishing
KR100378195B1 (ko) * 2001-02-21 2003-03-29 삼성전자주식회사 패턴의 밀도에 연속적으로 조절되는 밀도를 갖는 더미패턴군들을 포함하는 마스크용 데이터 생성 방법 및그러한 생성 방법이 저장된 기록매체
US6611045B2 (en) 2001-06-04 2003-08-26 Motorola, Inc. Method of forming an integrated circuit device using dummy features and structure thereof
US7014955B2 (en) * 2001-08-28 2006-03-21 Synopsys, Inc. System and method for indentifying dummy features on a mask layer
US6875682B1 (en) * 2001-09-04 2005-04-05 Taiwan Semiconductor Manufacturing Company Mesh pad structure to eliminate IMD crack on pad
JP2003218244A (ja) * 2002-01-24 2003-07-31 Seiko Epson Corp 半導体装置の製造方法
US6613688B1 (en) * 2002-04-26 2003-09-02 Motorola, Inc. Semiconductor device and process for generating an etch pattern
US20030229875A1 (en) * 2002-06-07 2003-12-11 Smith Taber H. Use of models in integrated circuit fabrication
US7363099B2 (en) * 2002-06-07 2008-04-22 Cadence Design Systems, Inc. Integrated circuit metrology
US7712056B2 (en) * 2002-06-07 2010-05-04 Cadence Design Systems, Inc. Characterization and verification for integrated circuit designs
US7774726B2 (en) * 2002-06-07 2010-08-10 Cadence Design Systems, Inc. Dummy fill for integrated circuits
US7853904B2 (en) * 2002-06-07 2010-12-14 Cadence Design Systems, Inc. Method and system for handling process related variations for integrated circuits based upon reflections
EP1532670A4 (en) * 2002-06-07 2007-09-12 Praesagus Inc CHARACTERIZATION AND REDUCTION OF VARIATION FOR INTEGRATED CIRCUITS
US7393755B2 (en) 2002-06-07 2008-07-01 Cadence Design Systems, Inc. Dummy fill for integrated circuits
US7152215B2 (en) * 2002-06-07 2006-12-19 Praesagus, Inc. Dummy fill for integrated circuits
US7124386B2 (en) * 2002-06-07 2006-10-17 Praesagus, Inc. Dummy fill for integrated circuits
US7128803B2 (en) * 2002-06-28 2006-10-31 Lam Research Corporation Integration of sensor based metrology into semiconductor processing tools
US7309618B2 (en) * 2002-06-28 2007-12-18 Lam Research Corporation Method and apparatus for real time metal film thickness measurement
US20040011462A1 (en) * 2002-06-28 2004-01-22 Lam Research Corporation Method and apparatus for applying differential removal rates to a surface of a substrate
FR2843232B1 (fr) * 2002-07-31 2004-11-05 Xyalis Procede d'homogeneisation de l'epaisseur d'un depot sur une couche comportant des motifs
US6748579B2 (en) * 2002-08-30 2004-06-08 Lsi Logic Corporation Method of using filler metal for implementing changes in an integrated circuit design
FR2844096A1 (fr) * 2002-08-30 2004-03-05 St Microelectronics Sa Procede de fabrication d'un circuit electrique comprenant une etape de polissage
US6812069B2 (en) * 2002-12-17 2004-11-02 Taiwan Semiconductor Manufacturing Co., Ltd Method for improving semiconductor process wafer CMP uniformity while avoiding fracture
US6730950B1 (en) 2003-01-07 2004-05-04 Texas Instruments Incorporated Local interconnect using the electrode of a ferroelectric
US6989229B2 (en) 2003-03-27 2006-01-24 Freescale Semiconductor, Inc. Non-resolving mask tiling method for flare reduction
US6905967B1 (en) * 2003-03-31 2005-06-14 Amd, Inc. Method for improving planarity of shallow trench isolation using multiple simultaneous tiling systems
US7089522B2 (en) 2003-06-11 2006-08-08 Chartered Semiconductor Manufacturing, Ltd. Device, design and method for a slot in a conductive area
US7175941B2 (en) * 2003-09-08 2007-02-13 Taiwan Semiconductor Manufacturing Co., Ltd. Phase shift assignments for alternate PSM
US20050066739A1 (en) * 2003-09-26 2005-03-31 Lam Research Corporation Method and apparatus for wafer mechanical stress monitoring and wafer thermal stress monitoring
US7481818B2 (en) * 2003-10-20 2009-01-27 Lifescan Lancing device with a floating probe for control of penetration depth
US20050096686A1 (en) * 2003-10-31 2005-05-05 Allen John J. Lancing device with trigger mechanism for penetration depth control
US7226839B1 (en) * 2004-06-04 2007-06-05 Spansion Llc Method and system for improving the topography of a memory array
JP4401874B2 (ja) * 2004-06-21 2010-01-20 株式会社ルネサステクノロジ 半導体装置
US7226857B2 (en) 2004-07-30 2007-06-05 Micron Technology, Inc. Front-end processing of nickel plated bond pads
US7476920B2 (en) 2004-12-15 2009-01-13 Infineon Technologies Ag 6F2 access transistor arrangement and semiconductor memory device
US7475382B2 (en) * 2005-02-24 2009-01-06 Synopsys, Inc. Method and apparatus for determining an improved assist feature configuration in a mask layout
JP5147167B2 (ja) * 2005-07-29 2013-02-20 キヤノン株式会社 決定方法及びプログラム
CN101341595A (zh) * 2005-12-14 2009-01-07 飞思卡尔半导体公司 形成具有伪特征的半导体器件的方法
US7741221B2 (en) * 2005-12-14 2010-06-22 Freescale Semiconductor, Inc. Method of forming a semiconductor device having dummy features
US7475368B2 (en) * 2006-01-20 2009-01-06 International Business Machines Corporation Deflection analysis system and method for circuit design
US7767570B2 (en) * 2006-03-22 2010-08-03 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy vias for damascene process
JP2007287928A (ja) * 2006-04-17 2007-11-01 Nec Electronics Corp 半導体集積回路およびその製造方法ならびにマスク
US7565639B2 (en) * 2007-01-04 2009-07-21 Freescale Semiconductor, Inc. Integrated assist features for epitaxial growth bulk tiles with compensation
US8003539B2 (en) 2007-01-04 2011-08-23 Freescale Semiconductor, Inc. Integrated assist features for epitaxial growth
US8741743B2 (en) * 2007-01-05 2014-06-03 Freescale Semiconductor, Inc. Integrated assist features for epitaxial growth
US7470624B2 (en) * 2007-01-08 2008-12-30 Freescale Semiconductor, Inc. Integrated assist features for epitaxial growth bulk/SOI hybrid tiles with compensation
DE102007004953A1 (de) * 2007-01-26 2008-07-31 Tesa Ag Heizelement
US7988794B2 (en) * 2007-02-07 2011-08-02 Infineon Technologies Ag Semiconductor device and method
US7926006B2 (en) * 2007-02-23 2011-04-12 International Business Machines Corporation Variable fill and cheese for mitigation of BEOL topography
US20090191468A1 (en) * 2008-01-29 2009-07-30 International Business Machines Corporation Contact Level Mask Layouts By Introducing Anisotropic Sub-Resolution Assist Features
US20090250760A1 (en) * 2008-04-02 2009-10-08 International Business Machines Corporation Methods of forming high-k/metal gates for nfets and pfets
JP5309728B2 (ja) * 2008-06-27 2013-10-09 富士通セミコンダクター株式会社 レチクルデータ作成方法及びレチクルデータ作成装置
US7975246B2 (en) * 2008-08-14 2011-07-05 International Business Machines Corporation MEEF reduction by elongation of square shapes
US9768182B2 (en) 2015-10-20 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method for forming the same
US10386714B2 (en) * 2017-01-09 2019-08-20 Globalfoundries Inc. Creating knowledge base for optical proximity correction to reduce sub-resolution assist feature printing
US11257816B2 (en) * 2019-08-20 2022-02-22 Taiwan Semiconductor Manufacturing Co., Ltd. Method for manufacturing semiconductor device including dummy gate electrodes
US11658103B2 (en) * 2020-09-11 2023-05-23 Qualcomm Incorporated Capacitor interposer layer (CIL) chiplet design with conformal die edge pattern around bumps

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59186342A (ja) 1983-04-06 1984-10-23 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPS6474547A (en) 1987-09-14 1989-03-20 Motorola Inc Manufacture of semiconductor for compensating strain between pattern on semiconductor body and mask for obtaining pattern
US5285017A (en) 1991-12-31 1994-02-08 Intel Corporation Embedded ground plane and shielding structures using sidewall insulators in high frequency circuits having vias
US5278105A (en) 1992-08-19 1994-01-11 Intel Corporation Semiconductor device with dummy features in active layers
TW272310B (en) 1994-11-09 1996-03-11 At & T Corp Process for producing multi-level metallization in an integrated circuit
TW299458B (ja) 1994-11-10 1997-03-01 Intel Corp
US5665633A (en) 1995-04-06 1997-09-09 Motorola, Inc. Process for forming a semiconductor device having field isolation
US5981384A (en) * 1995-08-14 1999-11-09 Micron Technology, Inc. Method of intermetal dielectric planarization by metal features layout modification
US5747380A (en) * 1996-02-26 1998-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. Robust end-point detection for contact and via etching
JPH1027799A (ja) * 1996-04-22 1998-01-27 Toshiba Corp 半導体装置及びその製造方法
US5885856A (en) 1996-08-21 1999-03-23 Motorola, Inc. Integrated circuit having a dummy structure and method of making
JPH10144635A (ja) 1996-11-11 1998-05-29 Sony Corp 平坦化研磨における研磨後の段差予測方法およびダミーパターン配置方法
KR100243272B1 (ko) * 1996-12-20 2000-03-02 윤종용 반도체 소자의 콘택 플러그 형성방법
US5923563A (en) * 1996-12-20 1999-07-13 International Business Machines Corporation Variable density fill shape generation
JP3743120B2 (ja) 1997-02-21 2006-02-08 ソニー株式会社 露光用マスクのマスクパターン設計方法、並びに半導体集積回路の作製方法
US5959320A (en) * 1997-03-18 1999-09-28 Lsi Logic Corporation Semiconductor die having on-die de-coupling capacitance
KR100230421B1 (ko) * 1997-04-22 1999-11-15 윤종용 반도체장치의 더미패턴 형성방법
JP3767154B2 (ja) * 1997-06-17 2006-04-19 セイコーエプソン株式会社 電気光学装置用基板、電気光学装置、電子機器及び投写型表示装置
JP3299486B2 (ja) 1997-10-08 2002-07-08 松下電器産業株式会社 半導体装置およびその製造方法
JP3488606B2 (ja) 1997-10-22 2004-01-19 株式会社東芝 半導体装置の設計方法
US6087733A (en) * 1998-06-12 2000-07-11 Intel Corporation Sacrificial erosion control features for chemical-mechanical polishing process
US6232231B1 (en) * 1998-08-31 2001-05-15 Cypress Semiconductor Corporation Planarized semiconductor interconnect topography and method for polishing a metal layer to form interconnect

Similar Documents

Publication Publication Date Title
BE2015C062I2 (ja)
BE2013C048I2 (ja)
BE2012C026I2 (ja)
BE2011C041I2 (ja)
BE2010C018I2 (ja)
BE2010C008I2 (ja)
BRPI0113420B8 (ja)
AR028236A3 (ja)
CH694022C1 (ja)
BR0112866A2 (ja)
CN300955183S (zh) 连接件
IN192980B (ja)
CN3135639S (ja)
CN3139851S (ja)
AU2000274567A8 (ja)
AU2000271150A8 (ja)
BY5592C1 (ja)
AU2000270908A8 (ja)
AU2000264849A8 (ja)
CN3133795S (ja)
CN3133951S (ja)
CN3135513S (ja)
CN3135584S (ja)
CN3135585S (ja)
CN3142120S (ja)