FR2843232B1 - Procede d'homogeneisation de l'epaisseur d'un depot sur une couche comportant des motifs - Google Patents

Procede d'homogeneisation de l'epaisseur d'un depot sur une couche comportant des motifs

Info

Publication number
FR2843232B1
FR2843232B1 FR0209764A FR0209764A FR2843232B1 FR 2843232 B1 FR2843232 B1 FR 2843232B1 FR 0209764 A FR0209764 A FR 0209764A FR 0209764 A FR0209764 A FR 0209764A FR 2843232 B1 FR2843232 B1 FR 2843232B1
Authority
FR
France
Prior art keywords
homogeneizing
deposit
patterns
thickness
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
FR0209764A
Other languages
English (en)
Other versions
FR2843232A1 (fr
Inventor
Chaisemartin Philippe Morey
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xyalis
Original Assignee
Xyalis
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xyalis filed Critical Xyalis
Priority to FR0209764A priority Critical patent/FR2843232B1/fr
Priority to US10/631,582 priority patent/US7157289B2/en
Publication of FR2843232A1 publication Critical patent/FR2843232A1/fr
Application granted granted Critical
Publication of FR2843232B1 publication Critical patent/FR2843232B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/926—Dummy metallization

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
FR0209764A 2002-07-31 2002-07-31 Procede d'homogeneisation de l'epaisseur d'un depot sur une couche comportant des motifs Expired - Lifetime FR2843232B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR0209764A FR2843232B1 (fr) 2002-07-31 2002-07-31 Procede d'homogeneisation de l'epaisseur d'un depot sur une couche comportant des motifs
US10/631,582 US7157289B2 (en) 2002-07-31 2003-07-31 Method for homogenizing the thickness of a coating on a patterned layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0209764A FR2843232B1 (fr) 2002-07-31 2002-07-31 Procede d'homogeneisation de l'epaisseur d'un depot sur une couche comportant des motifs

Publications (2)

Publication Number Publication Date
FR2843232A1 FR2843232A1 (fr) 2004-02-06
FR2843232B1 true FR2843232B1 (fr) 2004-11-05

Family

ID=30129593

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0209764A Expired - Lifetime FR2843232B1 (fr) 2002-07-31 2002-07-31 Procede d'homogeneisation de l'epaisseur d'un depot sur une couche comportant des motifs

Country Status (2)

Country Link
US (1) US7157289B2 (fr)
FR (1) FR2843232B1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070210453A1 (en) * 2006-03-13 2007-09-13 Texas Instruments Inc. Dummy-fill-structure placement for improved device feature location and access for integrated circuit failure analysis
US9436787B2 (en) * 2014-04-14 2016-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating an integrated circuit with optimized pattern density uniformity
US9640438B2 (en) * 2014-12-30 2017-05-02 Globalfoundries Singapore Pte. Ltd. Integrated circuits with inactive gates and methods of manufacturing the same

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5923563A (en) * 1996-12-20 1999-07-13 International Business Machines Corporation Variable density fill shape generation
JP3488606B2 (ja) * 1997-10-22 2004-01-19 株式会社東芝 半導体装置の設計方法
TW449900B (en) * 1998-05-26 2001-08-11 United Microelectronics Corp Method to define dummy patterns
US6396158B1 (en) * 1999-06-29 2002-05-28 Motorola Inc. Semiconductor device and a process for designing a mask
US6436807B1 (en) * 2000-01-18 2002-08-20 Agere Systems Guardian Corp. Method for making an interconnect layer and a semiconductor device including the same

Also Published As

Publication number Publication date
US20040069744A1 (en) 2004-04-15
FR2843232A1 (fr) 2004-02-06
US7157289B2 (en) 2007-01-02

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