JP2007287928A - 半導体集積回路およびその製造方法ならびにマスク - Google Patents
半導体集積回路およびその製造方法ならびにマスク Download PDFInfo
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- JP2007287928A JP2007287928A JP2006113609A JP2006113609A JP2007287928A JP 2007287928 A JP2007287928 A JP 2007287928A JP 2006113609 A JP2006113609 A JP 2006113609A JP 2006113609 A JP2006113609 A JP 2006113609A JP 2007287928 A JP2007287928 A JP 2007287928A
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- wiring
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70458—Mix-and-match, i.e. multiple exposures of the same area using a similar type of exposure apparatus, e.g. multiple exposures using a UV apparatus
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
【解決手段】半導体集積回路1は、基板上の領域11(第1の領域)に設けられた第1の配線と、基板上の領域12(第2の領域)に設けられた第2の配線と、を備えている。領域12は、領域11を取り囲む領域である。第1の配線の配線幅の最小設計寸法は、第2の配線の配線幅の最小設計寸法よりも小さい。
【選択図】図1
Description
3 マスク
11 領域(第1の領域)
12 領域(第2の領域)
13 領域(パターン禁止領域)
21 中央領域
22 外周領域
23 禁止領域
26 サブチップ
31 部分(第1の部分)
32 部分(第2の部分)
33 部分(パターン禁止部分)
61 I/Oブロック
62 RAMブロック
63 高性能ロジックブロック
64 PLLブロック
Claims (8)
- 基板上の第1の領域に設けられた第1の配線と、
前記基板上の前記第1の領域を取り囲む第2の領域に設けられた第2の配線と、を備え、
前記第1の配線の配線幅の最小設計寸法は、前記第2の配線の配線幅の最小設計寸法よりも小さいことを特徴とする半導体集積回路。 - 請求項1に記載の半導体集積回路において、
前記第1および第2の領域は、互いに離間しており、
前記第1の領域と前記第2の領域との間の領域には、配線パターンが存在しない半導体集積回路。 - 請求項1または2に記載の半導体集積回路において、
前記第2の領域は、当該半導体集積回路の入出力回路領域である半導体集積回路。 - 請求項1乃至3いずれかに記載の半導体集積回路において、
前記第1の配線の配線幅の最小設計寸法は、0.1μm以下である半導体集積回路。 - 請求項1乃至4いずれかに記載の半導体集積回路において、
前記第1の領域は、1辺が20mmの正方形の領域内に納まる領域である半導体集積回路。 - 請求項1乃至5いずれかに記載の半導体集積回路の製造に用いられるマスクであって、
当該マスクの第1の部分に形成され、前記第1の配線の配線パターンに対応し、第1の波長の光によるリソグラフィによって前記基板上の前記第1の領域に転写される第1のマスクパターンと、
当該マスクの前記第1の部分を取り囲む第2の部分に形成され、前記第2の配線の配線パターンに対応し、前記第1の波長よりも長い第2の波長の光によるリソグラフィによって前記基板上の前記第2の領域に転写される第2のマスクパターンと、
を備えることを特徴とするマスク。 - 請求項6に記載のマスクにおいて、
前記第1および第2の波長の光は、共にエキシマレーザ光であるマスク。 - 請求項6または7に記載のマスクを用いて半導体集積回路を製造する方法であって、
前記第1の波長の光によるリソグラフィによって、前記基板上の前記第1の領域に前記第1のマスクパターンを転写する工程と、
前記第2の波長の光によるリソグラフィによって、前記基板上の前記第2の領域に前記第2のマスクパターンを転写する工程と、
を含むことを特徴とする半導体集積回路の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006113609A JP2007287928A (ja) | 2006-04-17 | 2006-04-17 | 半導体集積回路およびその製造方法ならびにマスク |
US11/783,962 US8278760B2 (en) | 2006-04-17 | 2007-04-13 | Semiconductor integrated circuit and method for manufacturing same, and mask |
CN200710105317.1A CN100481434C (zh) | 2006-04-17 | 2007-04-17 | 半导体集成电路及其制造方法以及掩模 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006113609A JP2007287928A (ja) | 2006-04-17 | 2006-04-17 | 半導体集積回路およびその製造方法ならびにマスク |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012055355A Division JP5475818B2 (ja) | 2012-03-13 | 2012-03-13 | 半導体集積回路の製造方法 |
Publications (1)
Publication Number | Publication Date |
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JP2007287928A true JP2007287928A (ja) | 2007-11-01 |
Family
ID=38603993
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2006113609A Pending JP2007287928A (ja) | 2006-04-17 | 2006-04-17 | 半導体集積回路およびその製造方法ならびにマスク |
Country Status (3)
Country | Link |
---|---|
US (1) | US8278760B2 (ja) |
JP (1) | JP2007287928A (ja) |
CN (1) | CN100481434C (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010039192A (ja) * | 2008-08-05 | 2010-02-18 | Oki Semiconductor Co Ltd | フォトマスク、及びフォトレジストパターンの形成方法 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7763396B2 (en) * | 2006-02-16 | 2010-07-27 | Oracle America, Inc. | Method and apparatus for fabricating semiconductor chips using varying areas of precision |
JP2008300715A (ja) * | 2007-06-01 | 2008-12-11 | Toshiba Corp | 半導体集積回路及びその製造方法 |
US20150303145A1 (en) * | 2014-04-17 | 2015-10-22 | Qualcomm Incorporated | Back end of line (beol) local optimization to improve product performance |
CN105182679B (zh) | 2015-10-19 | 2020-04-21 | 京东方科技集团股份有限公司 | 掩膜板及其制作方法、利用掩膜板构图的方法、滤光片 |
CN115480443A (zh) * | 2021-05-31 | 2022-12-16 | 长鑫存储技术有限公司 | 掩膜版图形的修正方法、装置以及半导体器件的制作方法 |
Citations (3)
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JPH04287908A (ja) * | 1990-10-03 | 1992-10-13 | Fujitsu Ltd | 露光装置および露光方法 |
JPH06181164A (ja) * | 1992-12-15 | 1994-06-28 | Hitachi Ltd | 露光方法及び露光装置 |
JP2007227454A (ja) * | 2006-02-21 | 2007-09-06 | Toshiba Corp | 半導体装置の製造方法 |
Family Cites Families (18)
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JPH0689839A (ja) | 1992-09-09 | 1994-03-29 | Fujitsu Ltd | 微細パターン形成方法および微細パターン露光装置 |
CA2253635C (en) | 1996-05-03 | 2006-01-03 | Gruppo Lepetit S.P.A. | Use of aspirochlorine or derivatives thereof as immunosuppressive agents |
US5838050A (en) * | 1996-06-19 | 1998-11-17 | Winbond Electronics Corp. | Hexagon CMOS device |
JP3352405B2 (ja) * | 1998-09-10 | 2002-12-03 | キヤノン株式会社 | 露光方法及びそれを用いたデバイス製造方法並びに半導体デバイス |
US6157067A (en) * | 1999-01-04 | 2000-12-05 | International Business Machines Corporation | Metal oxide semiconductor capacitor utilizing dummy lithographic patterns |
US6396158B1 (en) * | 1999-06-29 | 2002-05-28 | Motorola Inc. | Semiconductor device and a process for designing a mask |
US6894341B2 (en) * | 2001-12-25 | 2005-05-17 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method |
US6764808B2 (en) * | 2002-02-27 | 2004-07-20 | Advanced Micro Devices, Inc. | Self-aligned pattern formation using wavelenghts |
US6995412B2 (en) * | 2002-04-12 | 2006-02-07 | International Business Machines Corporation | Integrated circuit with capacitors having a fin structure |
DE10309266B3 (de) * | 2003-03-04 | 2005-01-13 | Infineon Technologies Ag | Verfahren zum Bilden einer Öffnung einer Licht absorbierenden Schicht auf einer Maske |
US6693357B1 (en) * | 2003-03-13 | 2004-02-17 | Texas Instruments Incorporated | Methods and semiconductor devices with wiring layer fill structures to improve planarization uniformity |
JP4519411B2 (ja) * | 2003-04-01 | 2010-08-04 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US7208404B2 (en) * | 2003-10-16 | 2007-04-24 | Taiwan Semiconductor Manufacturing Company | Method to reduce Rs pattern dependence effect |
US7541652B1 (en) * | 2004-05-05 | 2009-06-02 | Xilinx, Inc. | Substrate coupled noise isolation for integrated circuits |
JP2006044072A (ja) | 2004-08-04 | 2006-02-16 | Yokohama Rubber Co Ltd:The | タイヤモールド |
JP4963349B2 (ja) * | 2005-01-14 | 2012-06-27 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US7304497B2 (en) * | 2005-04-29 | 2007-12-04 | Altera Corporation | Methods and apparatus for programmably powering down structured application-specific integrated circuits |
JP4949733B2 (ja) * | 2006-05-11 | 2012-06-13 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
-
2006
- 2006-04-17 JP JP2006113609A patent/JP2007287928A/ja active Pending
-
2007
- 2007-04-13 US US11/783,962 patent/US8278760B2/en not_active Expired - Fee Related
- 2007-04-17 CN CN200710105317.1A patent/CN100481434C/zh not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04287908A (ja) * | 1990-10-03 | 1992-10-13 | Fujitsu Ltd | 露光装置および露光方法 |
JPH06181164A (ja) * | 1992-12-15 | 1994-06-28 | Hitachi Ltd | 露光方法及び露光装置 |
JP2007227454A (ja) * | 2006-02-21 | 2007-09-06 | Toshiba Corp | 半導体装置の製造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010039192A (ja) * | 2008-08-05 | 2010-02-18 | Oki Semiconductor Co Ltd | フォトマスク、及びフォトレジストパターンの形成方法 |
Also Published As
Publication number | Publication date |
---|---|
CN100481434C (zh) | 2009-04-22 |
CN101060110A (zh) | 2007-10-24 |
US8278760B2 (en) | 2012-10-02 |
US20070241329A1 (en) | 2007-10-18 |
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