JP2003133417A - 半導体集積回路装置及びその設計方法 - Google Patents

半導体集積回路装置及びその設計方法

Info

Publication number
JP2003133417A
JP2003133417A JP2001329582A JP2001329582A JP2003133417A JP 2003133417 A JP2003133417 A JP 2003133417A JP 2001329582 A JP2001329582 A JP 2001329582A JP 2001329582 A JP2001329582 A JP 2001329582A JP 2003133417 A JP2003133417 A JP 2003133417A
Authority
JP
Japan
Prior art keywords
design
semiconductor integrated
integrated circuit
circuit device
bit cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001329582A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003133417A5 (enExample
Inventor
Hiroyuki Yamauchi
寛行 山内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2001329582A priority Critical patent/JP2003133417A/ja
Priority to US10/252,563 priority patent/US6791128B1/en
Publication of JP2003133417A publication Critical patent/JP2003133417A/ja
Priority to US10/935,094 priority patent/US7356795B2/en
Publication of JP2003133417A5 publication Critical patent/JP2003133417A5/ja
Priority to US11/980,589 priority patent/US20080074913A1/en
Priority to US11/980,461 priority patent/US20080084726A1/en
Priority to US11/980,562 priority patent/US20080067552A1/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/06—Multi-objective optimisation, e.g. Pareto optimisation using simulated annealing [SA], ant colony algorithms or genetic algorithms [GA]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2001329582A 2001-10-26 2001-10-26 半導体集積回路装置及びその設計方法 Pending JP2003133417A (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2001329582A JP2003133417A (ja) 2001-10-26 2001-10-26 半導体集積回路装置及びその設計方法
US10/252,563 US6791128B1 (en) 2001-10-26 2002-09-24 Semiconductor integrated circuit device and method for designing the same
US10/935,094 US7356795B2 (en) 2001-10-26 2004-09-08 Semiconductor integrated circuit device and method for designing the same
US11/980,589 US20080074913A1 (en) 2001-10-26 2007-10-31 Semiconductor integrated circuit device and method for designing the same
US11/980,461 US20080084726A1 (en) 2001-10-26 2007-10-31 Semiconductor integrated circuit device and method for designing the same
US11/980,562 US20080067552A1 (en) 2001-10-26 2007-10-31 Semiconductor integrated circuit device and method for desiging the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001329582A JP2003133417A (ja) 2001-10-26 2001-10-26 半導体集積回路装置及びその設計方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2008297010A Division JP2009081455A (ja) 2008-11-20 2008-11-20 半導体集積回路装置

Publications (2)

Publication Number Publication Date
JP2003133417A true JP2003133417A (ja) 2003-05-09
JP2003133417A5 JP2003133417A5 (enExample) 2005-04-07

Family

ID=19145464

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001329582A Pending JP2003133417A (ja) 2001-10-26 2001-10-26 半導体集積回路装置及びその設計方法

Country Status (2)

Country Link
US (5) US6791128B1 (enExample)
JP (1) JP2003133417A (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006209837A (ja) * 2005-01-26 2006-08-10 Nec Electronics Corp スタティック半導体記憶装置
JP2012156229A (ja) * 2011-01-25 2012-08-16 Renesas Electronics Corp 半導体装置およびその製造方法
JP2014157965A (ja) * 2013-02-18 2014-08-28 Renesas Electronics Corp 半導体装置

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004317718A (ja) * 2003-04-15 2004-11-11 Toshiba Corp パターン作成方法、パターン作成システム、および半導体装置の製造方法
US7087943B2 (en) * 2003-05-08 2006-08-08 Intel Corporation Direct alignment scheme between multiple lithography layers
JP4397210B2 (ja) 2003-10-20 2010-01-13 ローム株式会社 半導体装置
US7448012B1 (en) 2004-04-21 2008-11-04 Qi-De Qian Methods and system for improving integrated circuit layout
JP4309369B2 (ja) * 2005-03-30 2009-08-05 エルピーダメモリ株式会社 半導体装置
KR20070013557A (ko) * 2005-07-26 2007-01-31 삼성전자주식회사 마스크와, 이를 이용한 표시 기판의 제조 방법 및 표시기판
JP4949734B2 (ja) * 2006-05-17 2012-06-13 ルネサスエレクトロニクス株式会社 半導体装置及びその設計方法
JP5580981B2 (ja) * 2008-11-21 2014-08-27 ラピスセミコンダクタ株式会社 半導体素子及び半導体装置
US8359558B2 (en) 2010-03-16 2013-01-22 Synopsys, Inc. Modeling of cell delay change for electronic design automation
US9646958B2 (en) * 2010-03-17 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuits including dummy structures and methods of forming the same
US8595682B2 (en) * 2011-12-19 2013-11-26 International Business Machines Corporation Phase compensation in a differential pair of transmission lines
US11545495B2 (en) * 2017-06-29 2023-01-03 Taiwan Semiconductor Manufacturing Co., Ltd. Preventing gate-to-contact bridging by reducing contact dimensions in FinFET SRAM
CN108549750A (zh) * 2018-03-28 2018-09-18 湖南融创微电子有限公司 大容量sram的布局布线方法
CN108710710B (zh) * 2018-08-09 2023-08-29 广东电网有限责任公司广州供电局 用于配电房快速换柜的方法及装置

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SE358755B (enExample) * 1972-06-09 1973-08-06 Ericsson Telefon Ab L M
US4593383A (en) * 1983-11-02 1986-06-03 Raytheon Company Integated circuit memory
JPH04218944A (ja) 1990-06-04 1992-08-10 Ricoh Co Ltd 集積回路マスクのレイアウト方法および装置
US5264385A (en) * 1991-12-09 1993-11-23 Texas Instruments Incorporated SRAM design with no moat-to-moat spacing
KR950011636B1 (ko) * 1992-03-04 1995-10-07 금성일렉트론주식회사 개선된 레이아웃을 갖는 다이내믹 랜덤 액세스 메모리와 그것의 메모리셀 배치방법
JP3110262B2 (ja) * 1993-11-15 2000-11-20 松下電器産業株式会社 半導体装置及び半導体装置のオペレーティング方法
US5640342A (en) * 1995-11-20 1997-06-17 Micron Technology, Inc. Structure for cross coupled thin film transistors and static random access memory cell
JP3579205B2 (ja) * 1996-08-06 2004-10-20 株式会社ルネサステクノロジ 半導体記憶装置、半導体装置、データ処理装置及びコンピュータシステム
US5901103A (en) * 1997-04-07 1999-05-04 Motorola, Inc. Integrated circuit having standby control for memory and method thereof
US5932900A (en) 1997-06-20 1999-08-03 Faraday Technology Corporation Flexible cell for gate array
JP3351716B2 (ja) 1997-09-11 2002-12-03 株式会社東芝 半導体装置及びその製造方法
US6470489B1 (en) * 1997-09-17 2002-10-22 Numerical Technologies, Inc. Design rule checking system and method
JP4039532B2 (ja) * 1997-10-02 2008-01-30 株式会社ルネサステクノロジ 半導体集積回路装置
JP2000030441A (ja) * 1998-07-15 2000-01-28 Mitsubishi Electric Corp 半導体記憶装置及び半導体記憶装置のリフレッシュ方法
US6107108A (en) 1998-08-14 2000-08-22 Taiwan Semiconductor Manufacturing Company Dosage micro uniformity measurement in ion implantation
US6381166B1 (en) * 1998-09-28 2002-04-30 Texas Instruments Incorporated Semiconductor memory device having variable pitch array
JP2000114480A (ja) 1998-10-02 2000-04-21 Oki Electric Ind Co Ltd 半導体装置
JP3852729B2 (ja) * 1998-10-27 2006-12-06 富士通株式会社 半導体記憶装置
JP3209972B2 (ja) * 1999-01-14 2001-09-17 沖電気工業株式会社 半導体集積回路装置
JP3538108B2 (ja) 2000-03-14 2004-06-14 松下電器産業株式会社 半導体装置及びその製造方法
US7225423B2 (en) * 2000-06-30 2007-05-29 Zenasis Technologies, Inc. Method for automated design of integrated circuits with targeted quality objectives using dynamically generated building blocks
US6483739B2 (en) * 2000-12-31 2002-11-19 Texas Instruments Incorporated 4T memory with boost of stored voltage between standby and active

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006209837A (ja) * 2005-01-26 2006-08-10 Nec Electronics Corp スタティック半導体記憶装置
JP2012156229A (ja) * 2011-01-25 2012-08-16 Renesas Electronics Corp 半導体装置およびその製造方法
JP2014157965A (ja) * 2013-02-18 2014-08-28 Renesas Electronics Corp 半導体装置

Also Published As

Publication number Publication date
US7356795B2 (en) 2008-04-08
US20080084726A1 (en) 2008-04-10
US20050034093A1 (en) 2005-02-10
US20080067552A1 (en) 2008-03-20
US20080074913A1 (en) 2008-03-27
US6791128B1 (en) 2004-09-14

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