JP2003060509A - ディジタル信号のエラー補償装置及び方法 - Google Patents

ディジタル信号のエラー補償装置及び方法

Info

Publication number
JP2003060509A
JP2003060509A JP2001244735A JP2001244735A JP2003060509A JP 2003060509 A JP2003060509 A JP 2003060509A JP 2001244735 A JP2001244735 A JP 2001244735A JP 2001244735 A JP2001244735 A JP 2001244735A JP 2003060509 A JP2003060509 A JP 2003060509A
Authority
JP
Japan
Prior art keywords
error
digital signal
signal
interpolation data
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001244735A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003060509A5 (cg-RX-API-DMAC7.html
Inventor
Kazuo Watanabe
和夫 渡邊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Teac Corp
Original Assignee
Teac Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Teac Corp filed Critical Teac Corp
Priority to JP2001244735A priority Critical patent/JP2003060509A/ja
Priority to TW091114902A priority patent/TWI233596B/zh
Priority to CN021413649A priority patent/CN1217337C/zh
Priority to US10/215,624 priority patent/US6646582B2/en
Publication of JP2003060509A publication Critical patent/JP2003060509A/ja
Publication of JP2003060509A5 publication Critical patent/JP2003060509A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/3002—Conversion to or from differential modulation
    • H03M7/3004—Digital delta-sigma modulation
    • H03M7/3006—Compensating for, or preventing of, undesired influence of physical parameters

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Error Detection And Correction (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
JP2001244735A 2001-08-10 2001-08-10 ディジタル信号のエラー補償装置及び方法 Pending JP2003060509A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2001244735A JP2003060509A (ja) 2001-08-10 2001-08-10 ディジタル信号のエラー補償装置及び方法
TW091114902A TWI233596B (en) 2001-08-10 2002-07-04 Apparatus and method for compensating error of digital signal
CN021413649A CN1217337C (zh) 2001-08-10 2002-07-10 数字信号的误差补偿装置及方法
US10/215,624 US6646582B2 (en) 2001-08-10 2002-08-09 Error compensation for sigma-delta modulated digital signals or the like

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001244735A JP2003060509A (ja) 2001-08-10 2001-08-10 ディジタル信号のエラー補償装置及び方法

Publications (2)

Publication Number Publication Date
JP2003060509A true JP2003060509A (ja) 2003-02-28
JP2003060509A5 JP2003060509A5 (cg-RX-API-DMAC7.html) 2005-02-03

Family

ID=19074620

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001244735A Pending JP2003060509A (ja) 2001-08-10 2001-08-10 ディジタル信号のエラー補償装置及び方法

Country Status (4)

Country Link
US (1) US6646582B2 (cg-RX-API-DMAC7.html)
JP (1) JP2003060509A (cg-RX-API-DMAC7.html)
CN (1) CN1217337C (cg-RX-API-DMAC7.html)
TW (1) TWI233596B (cg-RX-API-DMAC7.html)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6956919B2 (en) * 2002-11-12 2005-10-18 Cirrus Logic, Inc. Single clock data communication in direct stream digital system
US6975258B2 (en) * 2003-01-23 2005-12-13 Corporation For National Research Initiatives Circuit for direct digital delta-sigma conversion of variable electrical capacitance
CA2454983A1 (en) * 2004-01-07 2005-07-07 Jean Beaucage System for high-speed applications over serial multi-drop communication networks
KR20080017392A (ko) * 2005-05-30 2008-02-26 코닌클리케 필립스 일렉트로닉스 엔.브이. 최소의 저장 요구를 갖는 디렉트 스트림 디지털 오디오
US7900116B2 (en) * 2006-08-07 2011-03-01 Broadcom Corporation Switch with error checking and correcting
EP2477418B1 (en) * 2011-01-12 2014-06-04 Nxp B.V. Signal processing method
US9520886B2 (en) * 2013-11-28 2016-12-13 Smart Energy Instruments Inc. Methods and devices for error correction of a signal using delta sigma modulation
CN107615379B (zh) * 2015-06-10 2021-12-24 索尼公司 信号处理装置、信号处理方法和程序

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0823971B2 (ja) * 1988-04-08 1996-03-06 日本ビクター株式会社 符号訂正装置
US5774481A (en) * 1995-03-31 1998-06-30 International Business Machines Corporation Reduced gate error detection and correction circuit
KR0157123B1 (ko) * 1995-12-23 1999-02-18 김광호 디지탈 보상형 멀티 비트 시그마 델타 아날로그 디지탈 변환기
JP2000114971A (ja) 1998-10-05 2000-04-21 Nippon Columbia Co Ltd ディジタル信号発生装置

Also Published As

Publication number Publication date
CN1217337C (zh) 2005-08-31
TWI233596B (en) 2005-06-01
US6646582B2 (en) 2003-11-11
US20030030577A1 (en) 2003-02-13
CN1402238A (zh) 2003-03-12

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