JP2003031611A - 複数の金属化レベル及び接続パッドを含む集積回路 - Google Patents
複数の金属化レベル及び接続パッドを含む集積回路Info
- Publication number
- JP2003031611A JP2003031611A JP2002142521A JP2002142521A JP2003031611A JP 2003031611 A JP2003031611 A JP 2003031611A JP 2002142521 A JP2002142521 A JP 2002142521A JP 2002142521 A JP2002142521 A JP 2002142521A JP 2003031611 A JP2003031611 A JP 2003031611A
- Authority
- JP
- Japan
- Prior art keywords
- metal layer
- integrated circuit
- metal
- discontinuous
- peripheral
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/019—Manufacture or treatment of bond pads
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07511—Treating the bonding area before connecting, e.g. by applying flux or cleaning
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5434—Dispositions of bond wires the connected ends being on auxiliary connecting means on bond pads, e.g. on other bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/59—Bond pads specially adapted therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/921—Structures or relative sizes of bond pads
- H10W72/923—Bond pads having multiple stacked layers
- H10W72/9232—Bond pads having multiple stacked layers with additional elements interposed between layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/951—Materials of bond pads
- H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/981—Auxiliary members, e.g. spacers
- H10W72/983—Reinforcing structures, e.g. collars
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/92—Conductor layers on different levels connected in parallel, e.g. to reduce resistance
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR0106591A FR2824954A1 (fr) | 2001-05-18 | 2001-05-18 | Plot de connexion d'un circuit integre |
| FR0106591 | 2001-05-18 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003031611A true JP2003031611A (ja) | 2003-01-31 |
| JP2003031611A5 JP2003031611A5 (https=) | 2005-09-29 |
Family
ID=8863445
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002142521A Pending JP2003031611A (ja) | 2001-05-18 | 2002-05-17 | 複数の金属化レベル及び接続パッドを含む集積回路 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US6822329B2 (https=) |
| EP (1) | EP1261030A1 (https=) |
| JP (1) | JP2003031611A (https=) |
| FR (1) | FR2824954A1 (https=) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005142553A (ja) * | 2003-10-15 | 2005-06-02 | Toshiba Corp | 半導体装置 |
| US7199042B2 (en) | 2003-11-06 | 2007-04-03 | Nec Electronics Corporation | Semiconductor device with multi-layered wiring arrangement including reinforcing patterns, and production method for manufacturing such semiconductor device |
| JP2011066459A (ja) * | 2010-12-28 | 2011-03-31 | Panasonic Corp | 半導体装置 |
Families Citing this family (43)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6104761A (en) | 1998-08-28 | 2000-08-15 | Sicom, Inc. | Constrained-envelope digital-communications transmission system and method therefor |
| JP3779243B2 (ja) * | 2002-07-31 | 2006-05-24 | 富士通株式会社 | 半導体装置及びその製造方法 |
| US7692315B2 (en) * | 2002-08-30 | 2010-04-06 | Fujitsu Microelectronics Limited | Semiconductor device and method for manufacturing the same |
| US6864578B2 (en) * | 2003-04-03 | 2005-03-08 | International Business Machines Corporation | Internally reinforced bond pads |
| US7005369B2 (en) * | 2003-08-21 | 2006-02-28 | Intersil American Inc. | Active area bonding compatible high current structures |
| US8274160B2 (en) | 2003-08-21 | 2012-09-25 | Intersil Americas Inc. | Active area bonding compatible high current structures |
| WO2005024912A2 (en) * | 2003-09-09 | 2005-03-17 | Intel Corporation | Methods of processing thick ild layers using spray coating or lamination for c4 wafer level thick metal integrated flow |
| US6977435B2 (en) * | 2003-09-09 | 2005-12-20 | Intel Corporation | Thick metal layer integrated process flow to improve power delivery and mechanical buffering |
| US7629689B2 (en) * | 2004-01-22 | 2009-12-08 | Kawasaki Microelectronics, Inc. | Semiconductor integrated circuit having connection pads over active elements |
| JP4242336B2 (ja) * | 2004-02-05 | 2009-03-25 | パナソニック株式会社 | 半導体装置 |
| JP4517843B2 (ja) * | 2004-12-10 | 2010-08-04 | エルピーダメモリ株式会社 | 半導体装置 |
| JP2006245076A (ja) * | 2005-03-01 | 2006-09-14 | Matsushita Electric Ind Co Ltd | 半導体装置 |
| US7323784B2 (en) * | 2005-03-17 | 2008-01-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Top via pattern for bond pad structure |
| US20060244156A1 (en) * | 2005-04-18 | 2006-11-02 | Tao Cheng | Bond pad structures and semiconductor devices using the same |
| JP4671814B2 (ja) | 2005-09-02 | 2011-04-20 | パナソニック株式会社 | 半導体装置 |
| US7626268B2 (en) | 2005-10-12 | 2009-12-01 | Infineon Technologies Ag | Support structures for semiconductor devices |
| FR2894716A1 (fr) * | 2005-12-09 | 2007-06-15 | St Microelectronics Sa | Puce de circuits integres a plots externes et procede de fabrication d'une telle puce |
| US7456479B2 (en) * | 2005-12-15 | 2008-11-25 | United Microelectronics Corp. | Method for fabricating a probing pad of an integrated circuit chip |
| US7592710B2 (en) * | 2006-03-03 | 2009-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bond pad structure for wire bonding |
| US7459792B2 (en) * | 2006-06-19 | 2008-12-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Via layout with via groups placed in interlocked arrangement |
| DE102006046182B4 (de) * | 2006-09-29 | 2010-11-11 | Infineon Technologies Ag | Halbleiterelement mit einer Stützstruktur sowie Herstellungsverfahren |
| US7573115B2 (en) * | 2006-11-13 | 2009-08-11 | International Business Machines Corporation | Structure and method for enhancing resistance to fracture of bonding pads |
| US7749885B2 (en) | 2006-12-15 | 2010-07-06 | Micron Technology, Inc. | Semiconductor processing methods, methods of forming contact pads, and methods of forming electrical connections between metal-containing layers |
| DE102007011126B4 (de) * | 2007-03-07 | 2009-08-27 | Austriamicrosystems Ag | Halbleiterbauelement mit Anschlusskontaktfläche |
| US9103884B2 (en) * | 2008-03-05 | 2015-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | De-embedding on-wafer devices |
| US8148797B2 (en) | 2008-06-26 | 2012-04-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Chip pad resistant to antenna effect and method |
| US8581423B2 (en) | 2008-11-17 | 2013-11-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Double solid metal pad with reduced area |
| JP2011146563A (ja) * | 2010-01-15 | 2011-07-28 | Panasonic Corp | 半導体装置 |
| US8381139B2 (en) | 2010-11-30 | 2013-02-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for metal correlated via split for double patterning |
| IT1404587B1 (it) | 2010-12-20 | 2013-11-22 | St Microelectronics Srl | Struttura di connessione induttiva per uso in un circuito integrato |
| IT1403475B1 (it) | 2010-12-20 | 2013-10-17 | St Microelectronics Srl | Struttura di connessione per un circuito integrato con funzione capacitiva |
| CN102593069A (zh) * | 2011-01-13 | 2012-07-18 | 奇景光电股份有限公司 | 接合垫结构以及集成电路芯片 |
| US8923357B2 (en) | 2011-09-13 | 2014-12-30 | Seagate Technology Llc | Semiconductor laser with cathode metal layer disposed in trench region |
| US8532156B2 (en) | 2011-09-13 | 2013-09-10 | Seagate Technology Llc | Semiconductor laser with test pads |
| CN102869189B (zh) * | 2012-09-18 | 2016-03-30 | 上海华勤通讯技术有限公司 | 焊盘加固pcb板 |
| CN103857181A (zh) * | 2012-12-06 | 2014-06-11 | 华为终端有限公司 | Pcb板以及具有该pcb板的电子设备 |
| US9773732B2 (en) * | 2013-03-06 | 2017-09-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for packaging pad structure |
| US9768221B2 (en) * | 2013-06-27 | 2017-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pad structure layout for semiconductor device |
| CN104952822A (zh) * | 2014-03-25 | 2015-09-30 | 中芯国际集成电路制造(上海)有限公司 | 一种焊盘结构 |
| US9269723B2 (en) * | 2014-04-09 | 2016-02-23 | Eastman Kodak Company | Printing electronic circuitry logic |
| JP2016139711A (ja) * | 2015-01-28 | 2016-08-04 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
| TWI559465B (zh) * | 2015-08-14 | 2016-11-21 | 恆勁科技股份有限公司 | 封裝基板及其製作方法 |
| US9922947B2 (en) * | 2016-04-28 | 2018-03-20 | Stmicroelectronics S.R.L. | Bonding pad structure over active circuitry |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08213422A (ja) * | 1995-02-07 | 1996-08-20 | Mitsubishi Electric Corp | 半導体装置およびそのボンディングパッド構造 |
| JP3482779B2 (ja) * | 1996-08-20 | 2004-01-06 | セイコーエプソン株式会社 | 半導体装置およびその製造方法 |
| US6143396A (en) * | 1997-05-01 | 2000-11-07 | Texas Instruments Incorporated | System and method for reinforcing a bond pad |
| JP2974022B1 (ja) * | 1998-10-01 | 1999-11-08 | ヤマハ株式会社 | 半導体装置のボンディングパッド構造 |
| JP2000195896A (ja) * | 1998-12-25 | 2000-07-14 | Nec Corp | 半導体装置 |
| TW430935B (en) * | 1999-03-19 | 2001-04-21 | Ind Tech Res Inst | Frame type bonding pad structure having a low parasitic capacitance |
| US6198170B1 (en) * | 1999-12-16 | 2001-03-06 | Conexant Systems, Inc. | Bonding pad and support structure and method for their fabrication |
-
2001
- 2001-05-18 FR FR0106591A patent/FR2824954A1/fr active Pending
-
2002
- 2002-05-06 EP EP02291127A patent/EP1261030A1/fr not_active Withdrawn
- 2002-05-14 US US10/145,388 patent/US6822329B2/en not_active Expired - Lifetime
- 2002-05-17 JP JP2002142521A patent/JP2003031611A/ja active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005142553A (ja) * | 2003-10-15 | 2005-06-02 | Toshiba Corp | 半導体装置 |
| US7199042B2 (en) | 2003-11-06 | 2007-04-03 | Nec Electronics Corporation | Semiconductor device with multi-layered wiring arrangement including reinforcing patterns, and production method for manufacturing such semiconductor device |
| JP2011066459A (ja) * | 2010-12-28 | 2011-03-31 | Panasonic Corp | 半導体装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| EP1261030A1 (fr) | 2002-11-27 |
| US6822329B2 (en) | 2004-11-23 |
| FR2824954A1 (fr) | 2002-11-22 |
| US20020179991A1 (en) | 2002-12-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2003031611A (ja) | 複数の金属化レベル及び接続パッドを含む集積回路 | |
| US6545366B2 (en) | Multiple chip package semiconductor device | |
| US6313540B1 (en) | Electrode structure of semiconductor element | |
| JP4808408B2 (ja) | マルチチップパッケージ、これに使われる半導体装置及びその製造方法 | |
| TW445557B (en) | Semiconductor device and method for producing the same | |
| KR100789874B1 (ko) | 반도체 장치 및 그 제조 방법 | |
| JP3903214B2 (ja) | 積層型半導体チップパッケージ及びその製造方法 | |
| EP1743369A2 (en) | Micropede stacked die component assembly | |
| KR101925951B1 (ko) | 다중 적층에 대한 전체 패키지 크기 감소를 위한 스티치 범프 적층 설계 | |
| US20090278251A1 (en) | Pad Structure for 3D Integrated Circuit | |
| JP2008527710A (ja) | 信号導電効率を上げながら配線パッド用構造支持体を実現する方法及び装置 | |
| US6215184B1 (en) | Optimized circuit design layout for high performance ball grid array packages | |
| JP4703938B2 (ja) | ウェーハレベルパッケージの空気パッドハンダ接合構造及びその製造方法 | |
| JP2000101016A (ja) | 半導体集積回路装置 | |
| TW200805620A (en) | Method of packaging a plurality of integrated circuit devices and semiconductor package so formed | |
| US5463255A (en) | Semiconductor integrated circuit device having an electrode pad including an extended wire bonding portion | |
| JP3833136B2 (ja) | 半導体構造およびボンディング方法 | |
| CN113314510B (zh) | 一种堆叠芯片及制备方法 | |
| US5880529A (en) | Silicon metal-pillar conductors under stagger bond pads | |
| US6020631A (en) | Method and apparatus for connecting a bondwire to a bondring near a via | |
| TW558810B (en) | Semiconductor package with lead frame as chip carrier and fabrication method thereof | |
| US20050263482A1 (en) | Method of manufacturing circuit device | |
| JP4062722B2 (ja) | 積層型半導体装置及びその製造方法 | |
| JP4168494B2 (ja) | 半導体装置の製造方法 | |
| KR20050027384A (ko) | 재배선 패드를 갖는 칩 사이즈 패키지 및 그 적층체 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20050426 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20050426 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20080319 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20080415 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20080711 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20080805 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20090106 |