JP2002305437A5 - - Google Patents
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- Publication number
- JP2002305437A5 JP2002305437A5 JP2002022435A JP2002022435A JP2002305437A5 JP 2002305437 A5 JP2002305437 A5 JP 2002305437A5 JP 2002022435 A JP2002022435 A JP 2002022435A JP 2002022435 A JP2002022435 A JP 2002022435A JP 2002305437 A5 JP2002305437 A5 JP 2002305437A5
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- JP
- Japan
- Prior art keywords
- address
- instruction
- synchronous dram
- signal
- access
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 230000001360 synchronised effect Effects 0.000 claims 30
- 238000000034 method Methods 0.000 claims 14
- 238000001514 detection method Methods 0.000 claims 3
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 claims 1
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US26598901P | 2001-02-02 | 2001-02-02 | |
| US60/265989 | 2001-02-02 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2002305437A JP2002305437A (ja) | 2002-10-18 |
| JP2002305437A5 true JP2002305437A5 (enExample) | 2005-08-04 |
| JP4313537B2 JP4313537B2 (ja) | 2009-08-12 |
Family
ID=23012704
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002022435A Expired - Fee Related JP4313537B2 (ja) | 2001-02-02 | 2002-01-30 | 低振幅電荷再利用型低電力cmos回路装置、加算器回路及び加算器モジュール |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US6803793B2 (enExample) |
| JP (1) | JP4313537B2 (enExample) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2868181B1 (fr) * | 2004-03-29 | 2006-05-26 | Soisic Sa | Procede de simulation d'un circuit a l'etat stationnaire |
| DE102005001484A1 (de) * | 2005-01-12 | 2006-03-23 | Infineon Technologies Ag | Schaltungsanordnung zur Verarbeitung eines Dual-Rail-Signals |
| FR2880217A1 (fr) * | 2004-11-03 | 2006-06-30 | Infineon Technologies Ag | Montage a mode de securite et a mode d'economie d'energie. |
| JP2006157321A (ja) * | 2004-11-29 | 2006-06-15 | Fujitsu Ltd | 差動クロック伝送装置、差動クロック送信装置、差動クロック受信装置、差動クロック伝送方法 |
| DE102005008367B3 (de) * | 2005-02-23 | 2006-10-19 | Infineon Technologies Ag | XOR-Schaltung |
| US20070008004A1 (en) * | 2005-07-11 | 2007-01-11 | Vikram Santurkar | Apparatus and methods for low-power routing circuitry in programmable logic devices |
| KR100744640B1 (ko) | 2005-11-02 | 2007-08-01 | 주식회사 하이닉스반도체 | 클럭 드라이버 |
| JP4984759B2 (ja) * | 2006-09-05 | 2012-07-25 | 富士通セミコンダクター株式会社 | 半導体記憶装置 |
| US7580304B2 (en) * | 2007-06-15 | 2009-08-25 | United Memories, Inc. | Multiple bus charge sharing |
| US7649406B2 (en) * | 2007-09-13 | 2010-01-19 | United Memories, Inc. | Short-circuit charge-sharing technique for integrated circuit devices |
| US8022729B2 (en) | 2008-04-11 | 2011-09-20 | Micron Technology, Inc. | Signal driver circuit having adjustable output voltage for a high logic level output signal |
| US7714617B2 (en) * | 2008-09-11 | 2010-05-11 | Micron Technology, Inc. | Signal driver circuit having an adjustable output voltage |
| US8482314B2 (en) * | 2011-11-08 | 2013-07-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method and apparatus for improved multiplexing using tri-state inverter |
| KR101844848B1 (ko) * | 2016-08-31 | 2018-04-03 | (주)멜파스 | 터치 검출 방법 및 이를 이용하는 터치 검출 장치 |
| US11068237B1 (en) | 2018-07-11 | 2021-07-20 | Rambus Inc. | Dual-domain combinational logic circuitry |
| JP2021068930A (ja) | 2019-10-17 | 2021-04-30 | キオクシア株式会社 | 半導体集積回路およびコントローラ |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2573392B2 (ja) * | 1990-03-30 | 1997-01-22 | 株式会社東芝 | 半導体記憶装置 |
| US5206544A (en) | 1991-04-08 | 1993-04-27 | International Business Machines Corporation | CMOS off-chip driver with reduced signal swing and reduced power supply disturbance |
| US5254883A (en) | 1992-04-22 | 1993-10-19 | Rambus, Inc. | Electrical current source circuitry for a bus |
| KR0137105B1 (ko) * | 1993-06-17 | 1998-04-29 | 모리시다 요이치 | 데이터 전송회로, 데이터선 구동회로, 증폭회로, 반도체 집적회로 및 반도체 기억장치 |
| US5903169A (en) | 1996-07-24 | 1999-05-11 | Lg Semicon Co., Ltd. | Charge recycling differential logic (CRDL) circuit and storage elements and devices using the same |
| US5859548A (en) | 1996-07-24 | 1999-01-12 | Lg Semicon Co., Ltd. | Charge recycling differential logic (CRDL) circuit and devices using the same |
| US5907251A (en) | 1996-11-22 | 1999-05-25 | International Business Machines Corp. | Low voltage swing capacitive bus driver device |
| US6097220A (en) | 1997-06-11 | 2000-08-01 | Intel Corporation | Method and circuit for recycling charge |
| JP2001118388A (ja) * | 1999-10-18 | 2001-04-27 | Nec Ic Microcomput Syst Ltd | バッファ回路 |
-
2002
- 2002-01-30 JP JP2002022435A patent/JP4313537B2/ja not_active Expired - Fee Related
- 2002-02-01 US US10/061,379 patent/US6803793B2/en not_active Expired - Fee Related
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