JP2002217377A - 半導体集積回路装置およびその製造方法 - Google Patents

半導体集積回路装置およびその製造方法

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Publication number
JP2002217377A
JP2002217377A JP2001010821A JP2001010821A JP2002217377A JP 2002217377 A JP2002217377 A JP 2002217377A JP 2001010821 A JP2001010821 A JP 2001010821A JP 2001010821 A JP2001010821 A JP 2001010821A JP 2002217377 A JP2002217377 A JP 2002217377A
Authority
JP
Japan
Prior art keywords
integrated circuit
semiconductor integrated
circuit device
wiring
connection terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001010821A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002217377A5 (enExample
Inventor
Toshio Miyamoto
俊夫 宮本
Ichiro Anjo
一郎 安生
Asao Nishimura
朝雄 西村
Mitsuaki Katagiri
光昭 片桐
Masayuki Shirai
優之 白井
Yoshihide Yamaguchi
欣秀 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2001010821A priority Critical patent/JP2002217377A/ja
Priority to US10/046,446 priority patent/US6861742B2/en
Priority to KR1020020002722A priority patent/KR20020062197A/ko
Publication of JP2002217377A publication Critical patent/JP2002217377A/ja
Priority to US10/771,471 priority patent/US6946327B2/en
Publication of JP2002217377A5 publication Critical patent/JP2002217377A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/22—Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Formation Of Insulating Films (AREA)
JP2001010821A 2001-01-18 2001-01-18 半導体集積回路装置およびその製造方法 Pending JP2002217377A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2001010821A JP2002217377A (ja) 2001-01-18 2001-01-18 半導体集積回路装置およびその製造方法
US10/046,446 US6861742B2 (en) 2001-01-18 2002-01-16 Wafer level chip size package having rerouting layers
KR1020020002722A KR20020062197A (ko) 2001-01-18 2002-01-17 반도체직접회로장치 및 그 제조방법
US10/771,471 US6946327B2 (en) 2001-01-18 2004-02-05 Semiconductor device and manufacturing method of that

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001010821A JP2002217377A (ja) 2001-01-18 2001-01-18 半導体集積回路装置およびその製造方法

Publications (2)

Publication Number Publication Date
JP2002217377A true JP2002217377A (ja) 2002-08-02
JP2002217377A5 JP2002217377A5 (enExample) 2006-03-09

Family

ID=18878068

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001010821A Pending JP2002217377A (ja) 2001-01-18 2001-01-18 半導体集積回路装置およびその製造方法

Country Status (3)

Country Link
US (2) US6861742B2 (enExample)
JP (1) JP2002217377A (enExample)
KR (1) KR20020062197A (enExample)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005229118A (ja) * 2004-02-10 2005-08-25 Samsung Electronics Co Ltd マルチ・ローパッド構造を有する半導体装置、及びそれを製造する方法
JP2006114595A (ja) * 2004-10-13 2006-04-27 Hitachi Ltd 半導体装置
JP2009266862A (ja) * 2008-04-22 2009-11-12 Oki Semiconductor Co Ltd 半導体装置
JP2012054712A (ja) * 2010-08-31 2012-03-15 Nikon Corp 撮像素子、及び撮像装置
JP2012160763A (ja) * 2012-05-28 2012-08-23 Renesas Electronics Corp 半導体装置
JP2013168491A (ja) * 2012-02-15 2013-08-29 Semiconductor Components Industries Llc 半導体装置の製造方法
US8558391B2 (en) 2008-02-14 2013-10-15 Renesas Electronics Corporation Semiconductor device and a method of manufacturing the same
JP2015053716A (ja) * 2014-10-27 2015-03-19 株式会社ニコン 撮像素子、及び撮像装置
WO2017146153A1 (ja) * 2016-02-26 2017-08-31 富士フイルム株式会社 積層体の製造方法および半導体デバイスの製造方法
JP2018042583A (ja) * 2016-09-12 2018-03-22 株式会社三共 遊技機

Families Citing this family (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6642136B1 (en) * 2001-09-17 2003-11-04 Megic Corporation Method of making a low fabrication cost, high performance, high reliability chip scale package
US8021976B2 (en) * 2002-10-15 2011-09-20 Megica Corporation Method of wire bonding over active area of a semiconductor circuit
US6815324B2 (en) * 2001-02-15 2004-11-09 Megic Corporation Reliable metal bumps on top of I/O pads after removal of test probe marks
TWI313507B (en) * 2002-10-25 2009-08-11 Megica Corporatio Method for assembling chips
US7902679B2 (en) * 2001-03-05 2011-03-08 Megica Corporation Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US7099293B2 (en) * 2002-05-01 2006-08-29 Stmicroelectronics, Inc. Buffer-less de-skewing for symbol combination in a CDMA demodulator
TWI245402B (en) * 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
JP3871609B2 (ja) * 2002-05-27 2007-01-24 松下電器産業株式会社 半導体装置及びその製造方法
DE10258094B4 (de) * 2002-12-11 2009-06-18 Qimonda Ag Verfahren zur Ausbildung von 3-D Strukturen auf Wafern
US7470997B2 (en) * 2003-07-23 2008-12-30 Megica Corporation Wirebond pad for semiconductor chip or wafer
US7394161B2 (en) * 2003-12-08 2008-07-01 Megica Corporation Chip structure with pads having bumps or wirebonded wires formed thereover or used to be tested thereto
US7422930B2 (en) * 2004-03-02 2008-09-09 Infineon Technologies Ag Integrated circuit with re-route layer and stacked die assembly
US8067837B2 (en) 2004-09-20 2011-11-29 Megica Corporation Metallization structure over passivation layer for IC chip
USD523403S1 (en) * 2004-09-09 2006-06-20 Kabushiki Kaisha Toshiba Substrate for a semiconductor device
USD522470S1 (en) * 2004-09-09 2006-06-06 Kabushiki Kaisha Toshiba Portion of a semiconductor device
USD522976S1 (en) * 2004-09-09 2006-06-13 Kabushiki Kaisha Toshiba Semiconductor device
US7342312B2 (en) * 2004-09-29 2008-03-11 Rohm Co., Ltd. Semiconductor device
US8294279B2 (en) * 2005-01-25 2012-10-23 Megica Corporation Chip package with dam bar restricting flow of underfill
KR100674970B1 (ko) * 2005-04-21 2007-01-26 삼성전자주식회사 이중 스페이서들을 이용한 미세 피치의 패턴 형성 방법
JP4289335B2 (ja) * 2005-08-10 2009-07-01 セイコーエプソン株式会社 電子部品、回路基板及び電子機器
US7932615B2 (en) * 2006-02-08 2011-04-26 Amkor Technology, Inc. Electronic devices including solder bumps on compliant dielectric layers
US7674701B2 (en) * 2006-02-08 2010-03-09 Amkor Technology, Inc. Methods of forming metal layers using multi-layer lift-off patterns
US7863737B2 (en) * 2006-04-01 2011-01-04 Stats Chippac Ltd. Integrated circuit package system with wire bond pattern
US7902885B2 (en) * 2006-12-28 2011-03-08 Stmicroelectronics Pvt. Ltd. Compensated output buffer for improving slew control rate
US8476735B2 (en) * 2007-05-29 2013-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Programmable semiconductor interposer for electronic package and method of forming
US7898088B2 (en) * 2007-10-09 2011-03-01 National Semiconductor Corporation I/O pad structures for integrated circuit devices
US11131431B2 (en) 2014-09-28 2021-09-28 Jiaxing Super Lighting Electric Appliance Co., Ltd LED tube lamp
CN102484101A (zh) 2009-08-13 2012-05-30 SKLink株式会社 电路基板及其制造方法
TWI464857B (zh) * 2011-05-20 2014-12-11 精材科技股份有限公司 晶片封裝體、其形成方法、及封裝晶圓
KR20130054769A (ko) * 2011-11-17 2013-05-27 삼성전기주식회사 반도체 패키지 및 이를 포함하는 반도체 패키지 모듈
TWI506570B (zh) * 2013-08-16 2015-11-01 Nat Univ Tsing Hua 分級產品資源規劃系統及其方法
KR102081684B1 (ko) * 2014-08-26 2020-04-28 데카 테크놀로지 잉크 고유 식별자를 포함하는 패키지에 대한 프론트사이드 패키지 레벨 직렬화
CN106796892B (zh) * 2014-08-26 2020-06-30 德卡技术股份有限公司 用于包括唯一标识符的封装体的正面封装级别序列化
US11480305B2 (en) 2014-09-25 2022-10-25 Jiaxing Super Lighting Electric Appliance Co., Ltd. LED tube lamp
CN112377825B (zh) 2014-09-28 2022-12-02 嘉兴山蒲照明电器有限公司 一种led直管灯
US10560989B2 (en) 2014-09-28 2020-02-11 Jiaxing Super Lighting Electric Appliance Co., Ltd LED tube lamp
US10514134B2 (en) 2014-12-05 2019-12-24 Jiaxing Super Lighting Electric Appliance Co., Ltd LED tube lamp
US12264789B2 (en) 2014-12-05 2025-04-01 Jiaxing Super Lighting Electric Appliance Co., Ltd LED tube lamp
US11028973B2 (en) 2015-03-10 2021-06-08 Jiaxing Super Lighting Electric Appliance Co., Ltd. Led tube lamp
US11519565B2 (en) 2015-03-10 2022-12-06 Jiaxing Super Lighting Electric Appliance Co., Ltd LED lamp and its power source module
US9897265B2 (en) 2015-03-10 2018-02-20 Jiaxing Super Lighting Electric Appliance Co., Ltd. LED tube lamp having LED light strip
US9589946B2 (en) * 2015-04-28 2017-03-07 Kabushiki Kaisha Toshiba Chip with a bump connected to a plurality of wirings
US9607681B2 (en) * 2015-08-26 2017-03-28 Everam Technology Inc. Memory device that supports multiple memory configurations
US11035526B2 (en) 2015-12-09 2021-06-15 Jiaxing Super Lighting Electric Appliance Co., Ltd. LED tube lamp
TWM592597U (zh) * 2019-03-26 2020-03-21 新加坡商Ｐｅｐ創新私人有限公司 面板組件、晶圓封裝體以及晶片封裝體
US11803686B2 (en) 2021-08-16 2023-10-31 International Business Machines Corporation Selective exposure of standard cell output nets for improved routing solutions

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07161761A (ja) 1993-12-13 1995-06-23 Fujitsu Ltd 半導体装置
JPH1140563A (ja) 1997-07-15 1999-02-12 Mitsubishi Electric Corp 半導体装置およびその電気特性変更方法
AU4726397A (en) 1997-10-30 1999-05-24 Hitachi Limited Semiconductor device and method for manufacturing the same
JPH11297889A (ja) * 1998-04-16 1999-10-29 Sony Corp 半導体パッケージおよび実装基板、ならびにこれらを用いた実装方法
US6103552A (en) * 1998-08-10 2000-08-15 Lin; Mou-Shiung Wafer scale packaging scheme
KR100301052B1 (ko) * 1998-12-28 2001-11-02 윤종용 소프트에러를감소하기위한반도체소자의제조방법
KR100306842B1 (ko) * 1999-09-30 2001-11-02 윤종용 범프 패드에 오목 패턴이 형성된 재배치 웨이퍼 레벨 칩 사이즈 패키지 및 그 제조방법
US20020125568A1 (en) * 2000-01-14 2002-09-12 Tongbi Jiang Method Of Fabricating Chip-Scale Packages And Resulting Structures
US6710456B1 (en) * 2000-08-31 2004-03-23 Micron Technology, Inc. Composite interposer for BGA packages
US6867123B2 (en) * 2001-02-08 2005-03-15 Renesas Technology Corp. Semiconductor integrated circuit device and its manufacturing method

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005229118A (ja) * 2004-02-10 2005-08-25 Samsung Electronics Co Ltd マルチ・ローパッド構造を有する半導体装置、及びそれを製造する方法
JP2006114595A (ja) * 2004-10-13 2006-04-27 Hitachi Ltd 半導体装置
US8558391B2 (en) 2008-02-14 2013-10-15 Renesas Electronics Corporation Semiconductor device and a method of manufacturing the same
JP2009266862A (ja) * 2008-04-22 2009-11-12 Oki Semiconductor Co Ltd 半導体装置
JP2012054712A (ja) * 2010-08-31 2012-03-15 Nikon Corp 撮像素子、及び撮像装置
JP2013168491A (ja) * 2012-02-15 2013-08-29 Semiconductor Components Industries Llc 半導体装置の製造方法
JP2012160763A (ja) * 2012-05-28 2012-08-23 Renesas Electronics Corp 半導体装置
JP2015053716A (ja) * 2014-10-27 2015-03-19 株式会社ニコン 撮像素子、及び撮像装置
WO2017146153A1 (ja) * 2016-02-26 2017-08-31 富士フイルム株式会社 積層体の製造方法および半導体デバイスの製造方法
JPWO2017146153A1 (ja) * 2016-02-26 2019-01-17 富士フイルム株式会社 積層体の製造方法および半導体デバイスの製造方法
JP2018042583A (ja) * 2016-09-12 2018-03-22 株式会社三共 遊技機

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