JP2001513946A - 垂直相互接続電子集成体とこれに有用な組成物 - Google Patents
垂直相互接続電子集成体とこれに有用な組成物Info
- Publication number
- JP2001513946A JP2001513946A JP53850598A JP53850598A JP2001513946A JP 2001513946 A JP2001513946 A JP 2001513946A JP 53850598 A JP53850598 A JP 53850598A JP 53850598 A JP53850598 A JP 53850598A JP 2001513946 A JP2001513946 A JP 2001513946A
- Authority
- JP
- Japan
- Prior art keywords
- printed wiring
- wiring board
- volume
- via hole
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
- H05K3/462—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar double-sided circuit boards
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
- H01B1/00—Conductors or conductive bodies characterised by the conductive materials; Selection of materials as conductors
- H01B1/02—Conductors or conductive bodies characterised by the conductive materials; Selection of materials as conductors mainly consisting of metals or alloys
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/02—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
- B23K35/0222—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape for use in soldering, brazing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49883—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials the conductive materials containing organic materials or pastes, e.g. for thick films
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
- H05K1/092—Dispersed materials, e.g. conductive pastes or inks
- H05K1/095—Dispersed materials, e.g. conductive pastes or inks for polymer thick films, i.e. having a permanent organic polymeric binder
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
- H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
- H05K2201/0203—Fillers and particles
- H05K2201/0263—Details about a collection of particles
- H05K2201/0272—Mixed conductive particles, i.e. using different conductive particles, e.g. differing in shape
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/10378—Interposers
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/04—Soldering or other types of metallurgic bonding
- H05K2203/0425—Solder powder or solder coated metal powder
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1105—Heating or thermal processing not related to soldering, firing, curing or laminating, e.g. for shaping the substrate or during finish plating
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3489—Composition of fluxes; Methods of application thereof; Other methods of activating the contact surfaces
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4623—Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S428/00—Stock material or miscellaneous articles
- Y10S428/901—Printed circuit
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/31504—Composite [nonstructural laminate]
- Y10T428/31511—Of epoxy ether
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/31504—Composite [nonstructural laminate]
- Y10T428/31511—Of epoxy ether
- Y10T428/31529—Next to metal
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/31504—Composite [nonstructural laminate]
- Y10T428/31678—Of metal
- Y10T428/31681—Next to polyester, polyamide or polyimide [e.g., alkyd, glue, or nylon, etc.]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Dispersion Chemistry (AREA)
- Mechanical Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1. 特製の垂直相互接続集成体(ビア・ホール)構造体であって、その構造体 は下記のものから成る: (i)所望の形状とパターンに穿孔されていて垂直相互接続通路を形成した透 電材と、 (ii)上記の穿孔透電体中に充填した電導性の過渡的液相焼結(TLPS)組 成物で、上記の電導性TLPS組成物は下記のものから成る: 高融点金属が5〜65容積%、 低融点金属又は金属合金が5〜60容積%、 バインダーが0〜35容積%、 潜在的又は化学的に保護された架橋剤が2〜60容量%、 反応性モノマー又はポリマーが0〜35容積%、および金属添加物が0〜10 容積%、 但し、上記組成物は必ず上記のバインダー及び/又は上記の反応性モノマー又 はポリマーを含有するか、または上記のバインダー及び/又は上記の反応性モノ マー又はポリマーは上記の化学的に保護された架橋剤と組合せて上記組成物の単 一成分とすることができるものとする。 2. 上記穿孔透電体の片面がメタリゼーション処理されている、請求項1に記 載の構造体。 3. 上記の穿孔透電体の両面がメタリゼーション処理されている、請求項1に 記載の構造体。 4. 上記の特製のビア・ホール構造体のいずれかの片面上にラミネートした2 枚の2面印刷配線板を更に含むことで1枚の多層回路を形成する、請求項1に記 載の構造体。 5. 上記の特製のビア・ホール構造体のいずれかの片面にラミネートした2枚 の多層印刷配線板を更に含むことで1枚の多層印刷配線板を形成する、請求項1 に記載の構造体。 6. エリア・アレイ素子実装体と印刷配線板基板を更に含み、上記のエリア・ アレー素子実装体と上記の印刷配線板基板とを上記の特製のビア・ホール構造体 のいずれかの片面上で整合、接続させて、1枚の集成印刷配線板を形成する、請 求項1に記載の構造体。 7. むき出しのダイと印刷配線板基板を更に含み、上記のダイと上記の印刷配 線板基板とを上記の特製のビア・ホール構造体のいずれかの片面上で整合、接続 して、1枚の集成印刷配線板を形成する、請求項1に記載の構造体。 8. むき出しのダイと素子実装体を更に含み、上記のダイと上記の素子実装体 を上記の特製のビア・ホール構造体のいずれかの片面上で整合、接続して、1枚 の実装素子を形成する、請求項1に記載の構造体。 9. 下記のものから成る特製のビア・ホール相互接続構造体: (i)カプセル化したメタリゼーション処理の透電体であって、封止剤は所望 のパターンのメタリゼーション処理面から選択的除去されたものであり、 (ii)上記の封止剤内の電導性組成物で形成したビア・ホール柱であり、これ により上記の組成物は上記のメタリゼーション処理面と電気的相互接続し、上記 の電導性組成物は下記のものから成る: 高融点金属が5〜65容積%、 低融点金属又は金属合金が5〜60容積%、 バインダーが0〜35容積%、 潜在的又は化学的に保護された架橋剤が2〜60容積%、 反応性モノマー又はポリマーが0〜35容積%、および 金属添加物が0〜10容積%、 但し、上記組成物は必ず上記のバインダー及び/又は上記の反応性モノマー又 はポリマーを含有するものとし、または、上記のバインダー及び/又は上記の反 応性モノマー又はポリマーは上記の化学的に保護された架橋剤と組合せて、上記 組成物の単一成分とすることができるものとする。 10.上記のメタリゼーション処理面は印刷配線板の回路パッドである、請求項 9に記載の構造体。 11.上記のメタリゼーション処理面がエリア・アレイ素子実装体上の回路パッ ドである、請求項9に記載の構造体。 12.上記のメタリゼーション処理面がむき出しダイ上の回路パッドである、請 求項9に記載の構造体。 13.印刷配線板を更に含み、上記の印刷配線板は上記のビア・ホール構造体の 頂部にラミネートして、上記の印刷配線板上の回路パッドが上記のビア・ホール 構造体中のビア・ホールと接続して1枚の印刷配線板を形成する、請求項9に記 載の構造体。 14.エリア・アレイ素子実装体を更に含み、上記のエリア・アレイ素子実装体 を上記の特製のビア・ホール構造体の頂部に付着して上記の実装体上の回路パッ ドを上記のビア・ホール構造体中のビア・ホールと接続して1つの印刷配線板集 成体を形成する、請求項9に記載の構造体。 15.むき出しのダイを更に含み、上記のダイは上記の特製のビア・ホール構造 体の頂部に付着させて上記のダイ上の回路パッドを上記のビア・ホール構造体中 のビア・ホールと接続して1つの印刷配線板集成体を形成する、請求項9に記載 の構造体。 16.むき出しのダイを更に含み、上記のダイは上記の特製のビア・ホール構造 体の頂部に付着させて上記のダイ上の回路パッドを上記のビア・ホール構造体中 のビア・ホールと接続して1つの集成素子実装体を形成する、請求項9に記載の 構造体。 17.下記のものから成る特製のビア・ホール構造体: (i)メタリゼーション処理透電体、および (ii)電導性接着組成物で形成した電導性接着剤柱であって、所望のビア・ホ ール形で上記のメタリゼーション透電体と接触しており、上記の電導性接着組成 物は下記のものから成る: 高融点金属が5〜65容積%、 低融点金属又は金属合金が5〜60容積%、 樹脂が0〜35容積%、 化学的に保護した架橋剤が2〜60容積%、 反応性モノマー又はポリマーが0〜35容積%、および 金属添加物が0〜10容積%、 但し、上記組成物は必ず上記バインダー及び/又は反応性モノマー又はポリマ ーを含むものとし、または上記のバインダー及び/又は上記の反応性モノマー又 はポリマーは上記の化学的に保護された架橋剤と組合せて上記組成分の単一成分 とすることができるものとする。 18.上記のメタリゼーション処理透電体がPWB回路パッドである、請求項1 7に記載の構造体。 19.上記のメタリゼーション処理透電体がエリア・アレイ素子実装体上の回路 パッドである、請求項17に記載の構造体。 20.上記のメタリゼーション処理透電体がむき出しのダイ上の回路パッドであ る、請求項17に記載の構造体。 21.更に下記のものを含む、請求項17に記載の構造体。 (i)上記のビア・ホール柱が貫通している透電性接着剤、および (ii)印刷配線板、上記の接着剤と上記の印刷配線板は上記の特製のビア・ホ ール構造体頂部にラミネートされていて上記の印刷配線板上の回路パッドが上記 のビア・ホール構造体中のビア・ホールと接続して1つの多層回路を形成する。 22.更に下記のものを含む、請求項17に記載の構造体。 (i)上記のビア・ホール柱が貫通した透電性接着剤、および (ii)エリア・アレイ素子実装体、上記の接着剤と上記のエリア・アレイ素子 実装体は上記の特製の特製のビア・ホール構造体の頂部に付着していて上記の回 路パッドが上記のビア・ホール構造体中のビア・ホールと接続して1つの印刷配 線板集成体を形成する。 23.更に下記のものを含む、請求項17に記載の構造体: (i)上記のビア・ホール柱が貫通した透電性接着剤、および (ii)むき出しのダイ、上記の接着剤と上記のダイは上記の特製のビア・ホー ル構造体頂部に付着していて、上記のダイ上の回路パッドが上記のビア・ホール 構造体中のビア・ホールと接続して1つの印刷配線板集成体を形成する。 24.更に下記のものを含む、請求項17に記載の構造体: (i)上記のビア・ホール柱が貫通した透電性接着剤、および (ii)むき出しのダイ、上記の接着剤と上記のダイは上記の特製のビア・ホー ル構造体頂部に付着していて、上記のダイ上の回路パッドが上記のビア・ホール 構造体中のビア・ホールと接続して1つの実装素子を形成する。
Applications Claiming Priority (3)
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US08/813,809 US5948533A (en) | 1990-02-09 | 1997-03-06 | Vertically interconnected electronic assemblies and compositions useful therefor |
US08/813,809 | 1997-03-06 | ||
PCT/US1998/001078 WO1998039781A1 (en) | 1997-03-06 | 1998-01-27 | Vertically interconnected electronic assemblies and compositions useful therefor |
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JP2001513946A true JP2001513946A (ja) | 2001-09-04 |
JP3869859B2 JP3869859B2 (ja) | 2007-01-17 |
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JP53850598A Expired - Lifetime JP3869859B2 (ja) | 1997-03-06 | 1998-01-27 | 垂直相互接続電子集成体とこれに有用な組成物 |
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US (1) | US5948533A (ja) |
EP (1) | EP0970480A4 (ja) |
JP (1) | JP3869859B2 (ja) |
KR (1) | KR100546533B1 (ja) |
WO (1) | WO1998039781A1 (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005112961A (ja) * | 2003-10-07 | 2005-04-28 | Shin Etsu Chem Co Ltd | 硬化性オルガノポリシロキサン組成物および半導体装置 |
JP2010095730A (ja) * | 2010-01-18 | 2010-04-30 | Shin-Etsu Chemical Co Ltd | 硬化性オルガノポリシロキサン組成物および半導体装置 |
JP2010515281A (ja) * | 2007-01-02 | 2010-05-06 | オルメット サーキッツ、インコーポレイテッド | 並列加工された回路および充填ビアから高密度の多層プリント配線基板を作成する方法 |
JP2019054105A (ja) * | 2017-09-14 | 2019-04-04 | 株式会社タムラ製作所 | 電極の接続方法および電子基板の製造方法 |
Families Citing this family (96)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2353528A (en) * | 1998-04-22 | 2001-02-28 | Multicore Solders Ltd | Adhesive and encapsulating material with fluxing properties |
GB9828656D0 (en) * | 1998-12-23 | 1999-02-17 | Northern Telecom Ltd | High density printed wiring board having in-via surface mounting pads |
US6344157B1 (en) | 1999-02-12 | 2002-02-05 | National Starch And Chemical Investment Holding Corporation | Conductive and resistive materials with electrical stability for use in electronics devices |
JP3973340B2 (ja) * | 1999-10-05 | 2007-09-12 | Necエレクトロニクス株式会社 | 半導体装置、配線基板、及び、それらの製造方法 |
TW512467B (en) * | 1999-10-12 | 2002-12-01 | North Kk | Wiring circuit substrate and manufacturing method therefor |
US6198170B1 (en) * | 1999-12-16 | 2001-03-06 | Conexant Systems, Inc. | Bonding pad and support structure and method for their fabrication |
JP2003518743A (ja) * | 1999-12-21 | 2003-06-10 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | 信頼性のあるフリップチップ接続のためのはんだによる有機パッケージ |
JP2001230551A (ja) * | 2000-02-14 | 2001-08-24 | Ibiden Co Ltd | プリント配線板並びに多層プリント配線板及びその製造方法 |
JP3633422B2 (ja) * | 2000-02-22 | 2005-03-30 | ソニーケミカル株式会社 | 接続材料 |
US6319811B1 (en) * | 2000-02-22 | 2001-11-20 | Scott Zimmerman | Bond ply structure and associated process for interconnection of circuit layer pairs with conductive inks |
US6387507B1 (en) * | 2000-03-31 | 2002-05-14 | Polese Company, Inc. | High temperature co-fired ceramic and low temperature co-fired ceramic combination electronic package device and method |
WO2002058108A2 (en) * | 2000-11-14 | 2002-07-25 | Henkel Loctite Corporation | Wafer applied fluxing and underfill material, and layered electronic assemblies manufactured therewith |
JP3473601B2 (ja) * | 2000-12-26 | 2003-12-08 | 株式会社デンソー | プリント基板およびその製造方法 |
US6884313B2 (en) * | 2001-01-08 | 2005-04-26 | Fujitsu Limited | Method and system for joining and an ultra-high density interconnect |
US6800169B2 (en) * | 2001-01-08 | 2004-10-05 | Fujitsu Limited | Method for joining conductive structures and an electrical conductive article |
US6534179B2 (en) | 2001-03-27 | 2003-03-18 | International Business Machines Corporation | Halogen free triazines, bismaleimide/epoxy polymers, prepregs made therefrom for circuit boards and resin coated articles, and use |
US6583201B2 (en) | 2001-04-25 | 2003-06-24 | National Starch And Chemical Investment Holding Corporation | Conductive materials with electrical stability for use in electronics devices |
US20030066679A1 (en) * | 2001-10-09 | 2003-04-10 | Castro Abram M. | Electrical circuit and method of formation |
US6660945B2 (en) | 2001-10-16 | 2003-12-09 | International Business Machines Corporation | Interconnect structure and method of making same |
US6926922B2 (en) * | 2002-04-09 | 2005-08-09 | Shipley Company, L.L.C. | PWB manufacture |
JP3925283B2 (ja) * | 2002-04-16 | 2007-06-06 | セイコーエプソン株式会社 | 電子デバイスの製造方法、電子機器の製造方法 |
US7230318B2 (en) | 2003-12-24 | 2007-06-12 | Agency For Science, Technology And Research | RF and MMIC stackable micro-modules |
CN101053079A (zh) | 2004-11-03 | 2007-10-10 | 德塞拉股份有限公司 | 堆叠式封装的改进 |
KR100601483B1 (ko) * | 2004-12-06 | 2006-07-18 | 삼성전기주식회사 | 비아포스트에 의해 층간 전도성이 부여된 병렬적 다층인쇄회로기판 및 그 제조 방법 |
US7452568B2 (en) * | 2005-02-04 | 2008-11-18 | International Business Machines Corporation | Centrifugal method for filing high aspect ratio blind micro vias with powdered materials for circuit formation |
JP2007076327A (ja) * | 2005-09-16 | 2007-03-29 | Fujifilm Corp | 電気接続構造、液体吐出ヘッド及びその製造方法並びに画像形成装置 |
US8063315B2 (en) | 2005-10-06 | 2011-11-22 | Endicott Interconnect Technologies, Inc. | Circuitized substrate with conductive paste, electrical assembly including said circuitized substrate and method of making said substrate |
US8058101B2 (en) | 2005-12-23 | 2011-11-15 | Tessera, Inc. | Microelectronic packages and methods therefor |
US7696016B2 (en) * | 2006-11-17 | 2010-04-13 | Freescale Semiconductor, Inc. | Method of packaging a device having a tangible element and device thereof |
US7807511B2 (en) * | 2006-11-17 | 2010-10-05 | Freescale Semiconductor, Inc. | Method of packaging a device having a multi-contact elastomer connector contact area and device thereof |
US7588951B2 (en) * | 2006-11-17 | 2009-09-15 | Freescale Semiconductor, Inc. | Method of packaging a semiconductor device and a prefabricated connector |
WO2008118947A1 (en) * | 2007-03-26 | 2008-10-02 | Lord Corporation | Method for producing heterogeneous composites |
US7858513B2 (en) * | 2007-06-18 | 2010-12-28 | Organicid, Inc. | Fabrication of self-aligned via holes in polymer thin films |
US20090032493A1 (en) * | 2007-08-03 | 2009-02-05 | Tsung Kuei Chang | Method For Manufacturing Predetermined Pattern |
WO2009031262A1 (ja) * | 2007-09-03 | 2009-03-12 | Panasonic Corporation | 配線基板 |
KR20120032463A (ko) * | 2009-04-02 | 2012-04-05 | 오르멧 서키츠 인코퍼레이티드 | 혼합된 합금 충전재를 함유하는 전도성 조성물 |
WO2010144770A1 (en) * | 2009-06-12 | 2010-12-16 | Lord Corporation | Method for shielding a substrate from electromagnetic interference |
US8840700B2 (en) * | 2009-11-05 | 2014-09-23 | Ormet Circuits, Inc. | Preparation of metallurgic network compositions and methods of use thereof |
JP4616927B1 (ja) * | 2010-02-25 | 2011-01-19 | パナソニック株式会社 | 配線基板、配線基板の製造方法、及びビアペースト |
JP4713682B1 (ja) * | 2010-02-25 | 2011-06-29 | パナソニック株式会社 | 多層配線基板、及び多層配線基板の製造方法 |
US8809690B2 (en) * | 2010-03-04 | 2014-08-19 | Rogers Corporation | Dielectric bond plies for circuits and multilayer circuits, and methods of manufacture thereof |
US8348139B2 (en) | 2010-03-09 | 2013-01-08 | Indium Corporation | Composite solder alloy preform |
US10366836B2 (en) * | 2010-05-26 | 2019-07-30 | Kemet Electronics Corporation | Electronic component structures with reduced microphonic noise |
US8482111B2 (en) | 2010-07-19 | 2013-07-09 | Tessera, Inc. | Stackable molded microelectronic packages |
JP4859999B1 (ja) * | 2010-12-21 | 2012-01-25 | パナソニック株式会社 | 多層配線基板、多層配線基板の製造方法、及びビアペースト |
JP4917668B1 (ja) * | 2010-12-29 | 2012-04-18 | パナソニック株式会社 | 多層配線基板、多層配線基板の製造方法 |
JP4795488B1 (ja) * | 2011-01-18 | 2011-10-19 | パナソニック株式会社 | 配線基板、配線基板の製造方法、及びビアペースト |
KR101128063B1 (ko) | 2011-05-03 | 2012-04-23 | 테세라, 인코포레이티드 | 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리 |
US8525338B2 (en) | 2011-06-07 | 2013-09-03 | Tessera, Inc. | Chip with sintered connections to package |
US9117811B2 (en) | 2011-06-13 | 2015-08-25 | Tessera, Inc. | Flip chip assembly and process with sintering material on metal bumps |
DE102011080729A1 (de) | 2011-08-10 | 2013-02-14 | Tesa Se | Elektrisch leitfähige Haftklebemasse und Haftklebeband |
DE102011080724A1 (de) * | 2011-08-10 | 2013-02-14 | Tesa Se | Elektrisch leitfähige hitzeaktivierbare Klebemasse |
US8836136B2 (en) | 2011-10-17 | 2014-09-16 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US8946757B2 (en) | 2012-02-17 | 2015-02-03 | Invensas Corporation | Heat spreading substrate with embedded interconnects |
US8372741B1 (en) | 2012-02-24 | 2013-02-12 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
US9056438B2 (en) | 2012-05-02 | 2015-06-16 | 3M Innovative Properties Company | Curable composition, articles comprising the curable composition, and method of making the same |
US8835228B2 (en) | 2012-05-22 | 2014-09-16 | Invensas Corporation | Substrate-less stackable package with wire-bond interconnect |
US9583453B2 (en) | 2012-05-30 | 2017-02-28 | Ormet Circuits, Inc. | Semiconductor packaging containing sintering die-attach material |
US9391008B2 (en) | 2012-07-31 | 2016-07-12 | Invensas Corporation | Reconstituted wafer-level package DRAM |
US9502390B2 (en) | 2012-08-03 | 2016-11-22 | Invensas Corporation | BVA interposer |
US9005330B2 (en) | 2012-08-09 | 2015-04-14 | Ormet Circuits, Inc. | Electrically conductive compositions comprising non-eutectic solder alloys |
JP5599497B2 (ja) | 2012-08-29 | 2014-10-01 | 有限会社 ナプラ | 機能性材料 |
WO2014082100A1 (en) * | 2012-11-16 | 2014-05-30 | Ormet Circuits Inc. | Alternative compositions for high temperature soldering applications |
US8878353B2 (en) | 2012-12-20 | 2014-11-04 | Invensas Corporation | Structure for microelectronic packaging with bond elements to encapsulation surface |
US9136254B2 (en) | 2013-02-01 | 2015-09-15 | Invensas Corporation | Microelectronic package having wire bond vias and stiffening layer |
KR102099878B1 (ko) | 2013-07-11 | 2020-04-10 | 삼성전자 주식회사 | 반도체 패키지 |
US9167710B2 (en) | 2013-08-07 | 2015-10-20 | Invensas Corporation | Embedded packaging with preformed vias |
US9685365B2 (en) | 2013-08-08 | 2017-06-20 | Invensas Corporation | Method of forming a wire bond having a free end |
EP2839904B1 (en) | 2013-08-21 | 2020-12-16 | Napra Co., Ltd. | Functional material |
US20150076714A1 (en) | 2013-09-16 | 2015-03-19 | Invensas Corporation | Microelectronic element with bond elements to encapsulation surface |
US9365947B2 (en) | 2013-10-04 | 2016-06-14 | Invensas Corporation | Method for preparing low cost substrates |
JP5885351B2 (ja) | 2013-10-09 | 2016-03-15 | 有限会社 ナプラ | 接合部及び電気配線 |
US9583456B2 (en) | 2013-11-22 | 2017-02-28 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US9263394B2 (en) | 2013-11-22 | 2016-02-16 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US9379074B2 (en) | 2013-11-22 | 2016-06-28 | Invensas Corporation | Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects |
US9583411B2 (en) | 2014-01-17 | 2017-02-28 | Invensas Corporation | Fine pitch BVA using reconstituted wafer with area array accessible for testing |
US10381326B2 (en) | 2014-05-28 | 2019-08-13 | Invensas Corporation | Structure and method for integrated circuits packaging with increased density |
US9826630B2 (en) * | 2014-09-04 | 2017-11-21 | Nxp Usa, Inc. | Fan-out wafer level packages having preformed embedded ground plane connections and methods for the fabrication thereof |
US9735084B2 (en) | 2014-12-11 | 2017-08-15 | Invensas Corporation | Bond via array for thermal conductivity |
US9888579B2 (en) | 2015-03-05 | 2018-02-06 | Invensas Corporation | Pressing of wire bond wire tips to provide bent-over tips |
US9502372B1 (en) | 2015-04-30 | 2016-11-22 | Invensas Corporation | Wafer-level packaging using wire bond wires in place of a redistribution layer |
US9761554B2 (en) | 2015-05-07 | 2017-09-12 | Invensas Corporation | Ball bonding metal wire bond wires to metal pads |
US9490222B1 (en) | 2015-10-12 | 2016-11-08 | Invensas Corporation | Wire bond wires for interference shielding |
US10490528B2 (en) | 2015-10-12 | 2019-11-26 | Invensas Corporation | Embedded wire bond wires |
US9515044B1 (en) * | 2015-10-14 | 2016-12-06 | Napra Co., Ltd. | Electronic device, method of manufacturing the same, metal particle, and electroconductive paste |
US10332854B2 (en) | 2015-10-23 | 2019-06-25 | Invensas Corporation | Anchoring structure of fine pitch bva |
US10181457B2 (en) | 2015-10-26 | 2019-01-15 | Invensas Corporation | Microelectronic package for wafer-level chip scale packaging with fan-out |
CN106658967B (zh) * | 2015-10-30 | 2019-12-20 | 奥特斯(中国)有限公司 | 具有不同电荷密度的交替垂直堆叠层结构的元件载体 |
US9911718B2 (en) | 2015-11-17 | 2018-03-06 | Invensas Corporation | ‘RDL-First’ packaged microelectronic device for a package-on-package device |
US9659848B1 (en) | 2015-11-18 | 2017-05-23 | Invensas Corporation | Stiffened wires for offset BVA |
US9984992B2 (en) | 2015-12-30 | 2018-05-29 | Invensas Corporation | Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces |
US9935075B2 (en) | 2016-07-29 | 2018-04-03 | Invensas Corporation | Wire bonding method and apparatus for electromagnetic interference shielding |
US20180063967A1 (en) * | 2016-08-26 | 2018-03-01 | Tyco Electronics Corporation | Interconnections Formed with Conductive Traces Applied onto Substrates Having Low Softening Temperatures |
US10299368B2 (en) | 2016-12-21 | 2019-05-21 | Invensas Corporation | Surface integrated waveguides and circuit structures therefor |
US11217554B2 (en) | 2017-06-12 | 2022-01-04 | Ormet Circuits, Inc. | Metallic adhesive compositions having good work lives and thermal conductivity, methods of making same and uses thereof |
EP4029052A1 (en) * | 2019-09-12 | 2022-07-20 | Ormet Circuits, Inc. | Lithographically defined electrical interconnects from conductive pastes |
Family Cites Families (76)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3541222A (en) * | 1969-01-13 | 1970-11-17 | Bunker Ramo | Connector screen for interconnecting adjacent surfaces of laminar circuits and method of making |
GB1353671A (en) * | 1971-06-10 | 1974-05-22 | Int Computers Ltd | Methods of forming circuit interconnections |
US3791858A (en) * | 1971-12-13 | 1974-02-12 | Ibm | Method of forming multi-layer circuit panels |
US3939559A (en) * | 1972-10-03 | 1976-02-24 | Western Electric Company, Inc. | Methods of solid-phase bonding mating members through an interposed pre-shaped compliant medium |
US3971610A (en) * | 1974-05-10 | 1976-07-27 | Technical Wire Products, Inc. | Conductive elastomeric contacts and connectors |
US3953924A (en) * | 1975-06-30 | 1976-05-04 | Rockwell International Corporation | Process for making a multilayer interconnect system |
SE404863B (sv) * | 1975-12-17 | 1978-10-30 | Perstorp Ab | Forfarande vid framstellning av ett flerlagerkort |
US4306925A (en) * | 1977-01-11 | 1981-12-22 | Pactel Corporation | Method of manufacturing high density printed circuit |
US4159222A (en) * | 1977-01-11 | 1979-06-26 | Pactel Corporation | Method of manufacturing high density fine line printed circuitry |
US4383363A (en) * | 1977-09-01 | 1983-05-17 | Sharp Kabushiki Kaisha | Method of making a through-hole connector |
JPS54133450A (en) * | 1978-04-10 | 1979-10-17 | Hitachi Ltd | Diffusion bonding method for different kind metal |
US4285780A (en) * | 1978-11-02 | 1981-08-25 | Schachter Herbert I | Method of making a multi-level circuit board |
US4273593A (en) * | 1979-06-25 | 1981-06-16 | Scm Corporation | Metal-joining paste and vehicle therefor |
US4332341A (en) * | 1979-12-26 | 1982-06-01 | Bell Telephone Laboratories, Incorporated | Fabrication of circuit packages using solid phase solder bonding |
US4446477A (en) * | 1981-08-21 | 1984-05-01 | Sperry Corporation | Multichip thin film module |
US4478882A (en) * | 1982-06-03 | 1984-10-23 | Italtel Societa Italiana Telecomunicazioni S.P.A. | Method for conductively interconnecting circuit components on opposite surfaces of a dielectric layer |
US4645733A (en) * | 1983-11-10 | 1987-02-24 | Sullivan Donald F | High resolution printed circuits formed in photopolymer pattern indentations overlaying printed wiring board substrates |
US4519760A (en) * | 1984-04-02 | 1985-05-28 | Burroughs Corporation | Machine for filling via holes in an integrated circuit package with conductive ink |
JPS60214941A (ja) * | 1984-04-10 | 1985-10-28 | 株式会社 潤工社 | プリント基板 |
US4667220A (en) * | 1984-04-27 | 1987-05-19 | Trilogy Computer Development Partners, Ltd. | Semiconductor chip module interconnection system |
US4647508A (en) * | 1984-07-09 | 1987-03-03 | Rogers Corporation | Flexible circuit laminate |
US4685210A (en) * | 1985-03-13 | 1987-08-11 | The Boeing Company | Multi-layer circuit board bonding method utilizing noble metal coated surfaces |
US4915983A (en) * | 1985-06-10 | 1990-04-10 | The Foxboro Company | Multilayer circuit board fabrication process |
US4692839A (en) * | 1985-06-24 | 1987-09-08 | Digital Equipment Corporation | Multiple chip interconnection system and package |
US4634631A (en) * | 1985-07-15 | 1987-01-06 | Rogers Corporation | Flexible circuit laminate and method of making the same |
US4642160A (en) * | 1985-08-12 | 1987-02-10 | Interconnect Technology Inc. | Multilayer circuit board manufacturing |
US4661204A (en) * | 1985-10-25 | 1987-04-28 | Tandem Computers Inc. | Method for forming vertical interconnects in polyimide insulating layers |
US4702792A (en) * | 1985-10-28 | 1987-10-27 | International Business Machines Corporation | Method of forming fine conductive lines, patterns and connectors |
US4874721A (en) * | 1985-11-11 | 1989-10-17 | Nec Corporation | Method of manufacturing a multichip package with increased adhesive strength |
US4902606A (en) * | 1985-12-20 | 1990-02-20 | Hughes Aircraft Company | Compressive pedestal for microminiature connections |
JPS6366993A (ja) * | 1986-09-08 | 1988-03-25 | 日本電気株式会社 | 多層配線基板 |
JPH07112041B2 (ja) * | 1986-12-03 | 1995-11-29 | シャープ株式会社 | 半導体装置の製造方法 |
US4875617A (en) * | 1987-01-20 | 1989-10-24 | Citowsky Elya L | Gold-tin eutectic lead bonding method and structure |
US5061548A (en) * | 1987-02-17 | 1991-10-29 | Rogers Corporation | Ceramic filled fluoropolymeric composite material |
US4849284A (en) * | 1987-02-17 | 1989-07-18 | Rogers Corporation | Electrical substrate material |
US4755911A (en) * | 1987-04-28 | 1988-07-05 | Junkosha Co., Ltd. | Multilayer printed circuit board |
US4788766A (en) * | 1987-05-20 | 1988-12-06 | Loral Corporation | Method of fabricating a multilayer circuit board assembly |
JPH0754872B2 (ja) * | 1987-06-22 | 1995-06-07 | 古河電気工業株式会社 | 二層印刷回路シ−トの製造方法 |
US4897338A (en) * | 1987-08-03 | 1990-01-30 | Allied-Signal Inc. | Method for the manufacture of multilayer printed circuit boards |
US4921777A (en) * | 1987-08-03 | 1990-05-01 | Allied-Signal Inc. | Method for manufacture of multilayer printed circuit boards |
US4922377A (en) * | 1987-11-16 | 1990-05-01 | Hitachi, Ltd. | Module and a substrate for the module |
FR2625042B1 (fr) * | 1987-12-22 | 1990-04-20 | Thomson Csf | Structure microelectronique hybride modulaire a haute densite d'integration |
US4841355A (en) * | 1988-02-10 | 1989-06-20 | Amdahl Corporation | Three-dimensional microelectronic package for semiconductor chips |
US4926241A (en) * | 1988-02-19 | 1990-05-15 | Microelectronics And Computer Technology Corporation | Flip substrate for chip mount |
US4868350A (en) * | 1988-03-07 | 1989-09-19 | International Business Machines Corporation | High performance circuit boards |
US4864722A (en) * | 1988-03-16 | 1989-09-12 | International Business Machines Corporation | Low dielectric printed circuit boards |
US4967314A (en) * | 1988-03-28 | 1990-10-30 | Prime Computer Inc. | Circuit board construction |
LU87259A1 (fr) * | 1988-06-27 | 1990-02-28 | Ceca Comm Europ Charbon Acier | Procede et dispositif de traitement de signaux electriques provenant de l'analyse d'une ligne d'une image |
US4810332A (en) * | 1988-07-21 | 1989-03-07 | Microelectronics And Computer Technology Corporation | Method of making an electrical multilayer copper interconnect |
US5008997A (en) * | 1988-09-16 | 1991-04-23 | National Semiconductor | Gold/tin eutectic bonding for tape automated bonding process |
US5031308A (en) * | 1988-12-29 | 1991-07-16 | Japan Radio Co., Ltd. | Method of manufacturing multilayered printed-wiring-board |
US4954313A (en) * | 1989-02-03 | 1990-09-04 | Amdahl Corporation | Method and apparatus for filling high density vias |
US4995941A (en) * | 1989-05-15 | 1991-02-26 | Rogers Corporation | Method of manufacture interconnect device |
US5049974A (en) * | 1989-05-15 | 1991-09-17 | Roger Corporation | Interconnect device and method of manufacture thereof |
US5097393A (en) * | 1989-05-15 | 1992-03-17 | Rogers Corporation | Multilayer interconnect device and method of manufacture thereof |
US5055425A (en) * | 1989-06-01 | 1991-10-08 | Hewlett-Packard Company | Stacked solid via formation in integrated circuit systems |
US5072075A (en) * | 1989-06-28 | 1991-12-10 | Digital Equipment Corporation | Double-sided hybrid high density circuit board and method of making same |
US5010641A (en) * | 1989-06-30 | 1991-04-30 | Unisys Corp. | Method of making multilayer printed circuit board |
US5030499A (en) * | 1989-12-08 | 1991-07-09 | Rockwell International Corporation | Hermetic organic/inorganic interconnection substrate for hybrid circuit manufacture |
US5716663A (en) * | 1990-02-09 | 1998-02-10 | Toranaga Technologies | Multilayer printed circuit |
US5376403A (en) * | 1990-02-09 | 1994-12-27 | Capote; Miguel A. | Electrically conductive compositions and methods for the preparation and use thereof |
US5538789A (en) * | 1990-02-09 | 1996-07-23 | Toranaga Technologies, Inc. | Composite substrates for preparation of printed circuits |
US5046238A (en) * | 1990-03-15 | 1991-09-10 | Rogers Corporation | Method of manufacturing a multilayer circuit board |
US5129142A (en) * | 1990-10-30 | 1992-07-14 | International Business Machines Corporation | Encapsulated circuitized power core alignment and lamination |
US5440805A (en) * | 1992-03-09 | 1995-08-15 | Rogers Corporation | Method of manufacturing a multilayer circuit |
US5276955A (en) * | 1992-04-14 | 1994-01-11 | Supercomputer Systems Limited Partnership | Multilayer interconnect system for an area array interconnection using solid state diffusion |
US5329695A (en) * | 1992-09-01 | 1994-07-19 | Rogers Corporation | Method of manufacturing a multilayer circuit board |
US5309629A (en) * | 1992-09-01 | 1994-05-10 | Rogers Corporation | Method of manufacturing a multilayer circuit board |
US5274912A (en) * | 1992-09-01 | 1994-01-04 | Rogers Corporation | Method of manufacturing a multilayer circuit board |
US5703405A (en) * | 1993-03-15 | 1997-12-30 | Motorola, Inc. | Integrated circuit chip formed from processing two opposing surfaces of a wafer |
WO1995013901A1 (en) * | 1993-11-19 | 1995-05-26 | Cts Corporation | Metallurgically bonded polymer vias |
US5456004A (en) * | 1994-01-04 | 1995-10-10 | Dell Usa, L.P. | Anisotropic interconnect methodology for cost effective manufacture of high density printed circuit boards |
US5498467A (en) * | 1994-07-26 | 1996-03-12 | W. L. Gore & Associates, Inc. | Process for preparing selectively conductive materials by electroless metal deposition and product made therefrom |
TW340132B (en) * | 1994-10-20 | 1998-09-11 | Ibm | Structure for use as an electrical interconnection means and process for preparing the same |
DE19511553C2 (de) * | 1995-03-29 | 1997-02-20 | Litton Precision Prod Int | Verfahren zur Erzeugung elektrisch leitfähiger Strukturen, eine nach dem Verfahren erhaltene elektrisch leitfähige Struktur sowie Kombination zur Erzeugung elektrisch leitfähiger Strukturen |
KR970010170A (ko) * | 1995-08-31 | 1997-03-27 | 한승준 | 상대변위 조절용 쇽 업소버 |
-
1997
- 1997-03-06 US US08/813,809 patent/US5948533A/en not_active Expired - Lifetime
-
1998
- 1998-01-27 EP EP98902647A patent/EP0970480A4/en not_active Ceased
- 1998-01-27 KR KR1019997008080A patent/KR100546533B1/ko active IP Right Grant
- 1998-01-27 WO PCT/US1998/001078 patent/WO1998039781A1/en active IP Right Grant
- 1998-01-27 JP JP53850598A patent/JP3869859B2/ja not_active Expired - Lifetime
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JP2005112961A (ja) * | 2003-10-07 | 2005-04-28 | Shin Etsu Chem Co Ltd | 硬化性オルガノポリシロキサン組成物および半導体装置 |
JP4551074B2 (ja) * | 2003-10-07 | 2010-09-22 | 信越化学工業株式会社 | 硬化性オルガノポリシロキサン組成物および半導体装置 |
JP2010515281A (ja) * | 2007-01-02 | 2010-05-06 | オルメット サーキッツ、インコーポレイテッド | 並列加工された回路および充填ビアから高密度の多層プリント配線基板を作成する方法 |
JP2010095730A (ja) * | 2010-01-18 | 2010-04-30 | Shin-Etsu Chemical Co Ltd | 硬化性オルガノポリシロキサン組成物および半導体装置 |
JP2019054105A (ja) * | 2017-09-14 | 2019-04-04 | 株式会社タムラ製作所 | 電極の接続方法および電子基板の製造方法 |
Also Published As
Publication number | Publication date |
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JP3869859B2 (ja) | 2007-01-17 |
US5948533A (en) | 1999-09-07 |
EP0970480A4 (en) | 2005-07-20 |
KR100546533B1 (ko) | 2006-01-26 |
WO1998039781A1 (en) | 1998-09-11 |
KR20000075994A (ko) | 2000-12-26 |
EP0970480A1 (en) | 2000-01-12 |
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