JP2001508218A - 複数デジタル・ビットのための安定化回路 - Google Patents
複数デジタル・ビットのための安定化回路Info
- Publication number
- JP2001508218A JP2001508218A JP53914497A JP53914497A JP2001508218A JP 2001508218 A JP2001508218 A JP 2001508218A JP 53914497 A JP53914497 A JP 53914497A JP 53914497 A JP53914497 A JP 53914497A JP 2001508218 A JP2001508218 A JP 2001508218A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- charge
- cell
- erase
- memory cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5657—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using ferroelectric storage elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
- G11C11/5635—Erasing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/565—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using capacitive charge storage elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
- G11C16/3431—Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Read Only Memory (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Plural Heterocyclic Compounds (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.情報ビットに対応する複数の離散状態のいずれかをそれぞれ格納することが できる複数のメモリ・セルと、 前記の一離散状態にある前記メモリ・セルによるドリフトを検出する手段とを 含む集積回路メモリ・システム。 2.前記検出手段が前記メモリ・セルのドリフトに起こりうる第1方向または第 2方向を検出することを特徴とする請求項1に記載のメモリ・システム。 3.前記の一離散状態にある前記メモリ・セルを復元する手段をさらに含み、前 記復元手段が前記検出手段と、前記の一離散状態に対応する前期情報ビットを維 持する前記の検出された第1方向または第2方向とに応答する請求項2に記載の メモリ・システム。 4.各メモリ・セルが前記情報ビットに対応する浮遊ゲート上の電荷量を蓄積す る不揮発性メモリ・セルを具備し、 前記電荷量に応答して前記の複数のメモリ・セルの各浮遊ゲート内の前記電荷 量を維持する回路手段をさらに含み、 それによって各メモリ・セル内の前記情報ビットの喪失を回避する請求項1に 記載のメモリ・システム。 5.前記維持回路手段が各不揮発性メモリ・セルとの間で電荷を加減することに より、前記不揮発性メモリ・セルからほぼすべての電荷を最初に消去することな く前記電荷量を調整することを特徴とする請求項4に記載のメモリ・システム。 6.各メモリ・セル内の前記情報ビットが少なくとも2ビットを含むことを特徴 とする請求項4に記載のメモリ・システム。 7.2N個以上の基準値を生成する手段をさらに含み、 各メモリ・セルがNビットの情報に対応する2N個の離散状態のいずれかを格 納することができ、前記検出手段が前記基準値との比較によって前記メモリ・セ ル内の前記の一離散状態を検出し、前記基準値を基準として前記の一離散状態に おけるドリフトを決定する請求項1に記載のメモリ・システム。 8.前記検出手段と前記基準値生成手段が協働して決められた順序で前記の一離 散状態と前記基準値とを順次比較することにより、前記の一離散状態を決定する こと、および前記基準値を基準にして前記の一離散状態におけるドリフトを決定 することを特徴とする請求項7に記載のメモリ・システム。 9.前記基準値が第1の組と第2の組を具備すること、前記検出手段が前記第1 の組の基準値に応答して前記の一離散状態を検出すること、前記検出手段が前記 第2の組の基準値に応答して前記メモリ・セル内の前記の一離散状態におけるド リフトを決定すること、および前記第2の組の基準値が第1の組の基準値と所定 の関係を有することを特徴とする請求項7に記載のメモリ・システム。 10.前記検出手段に応答して前記の一離散状態にある前記メモリ・セルを復元 する手段をさらに含み、それによって前記の一離散状態に対応する情報を前記の 複数のメモリ・セルのいずれかに保持できるようにする請求項9に記載のメモリ ・システム。 11.各メモリ・セルが前記の一離散状態を表す電荷量を蓄積し、前記検出手段 が前記の一離散状態を表す電荷を保持するために前記メモリ・セルとの間で電荷 の加減を行うべきかどうかを判定し、 さらに前記検出手段による判定に応答して少なくとも1つの状況フラグを設定 する手段を含む請求項7に記載のメモリ・システム。 12.前記メモリ・セルに関係する記憶域に前記の少なくとも1つの状況フラグ を保存する手段をさらに含む請求項11に記載のメモリ・システム。 13.前記検出手段が前記の一離散状態を少なくとも2つの基準値と比較して、 前記メモリ・セルに付加した電荷が前記の一離散状態を復元するのに十分か不十 分かを判定することを特徴とする請求項11に記載のメモリ・システム。 14.前記の複数のメモリ・セルがアレイ内に配置され、各メモリ・セルが前記 情報ビットに対応する電荷量を蓄積するメモリ・システムであって、 前記メモリ・セル・アレイに結合され、前記メモリ・セル・アレイに信号を供 給して前記メモリ・セルとの間で電荷を移動させ、それによって前記メモリ・セ ルに蓄積した電荷を前記情報ビットに対応させるプログラミング回路と、 さらに複数の基準電圧を生成することができる基準電圧回路と、 前記メモリ・セル・アレイと前記基準電圧回路とに結合されたコンパレータと 、 前記メモリ・セル・アレイ、前記基準電圧回路、および前記コンパレータに結 合された制御回路とを含み、前記制御回路が電荷量を検出することならびに前記 の選択された複数の各メモリ・セル内の情報ビットに対応する前期電荷量におけ るドリフトを決定することを目的として、前記メモリ・セル・アレイ内の選択さ れた複数のメモリ・セルと前記基準電圧回路を前記コンパレータに接続する請求 項1に記載のメモリ・システム。 15.前記制御回路がドリフト決定に応答して前記の選択された複数のメモリ・ セル内の電荷の調整を前記プログラミング回路に行わせ、それによって各メモリ ・セル内の情報ビットの喪失を回避できるようにすることを特徴とする請求項1 4に記載の集積回路。 16.前記プログラミング回路が前記の複数のメモリ・セルからほぼすべての電 荷を最初に消去することなく前記電荷を調整することを特徴とする請求項15に 記載の集積回路。 17.前記コンパレータが前記の選択された複数の各メモリ・セル内の前記電荷 に応答した電圧を前記の複数の基準電圧のうちの第1の組の基準電圧と比較して 、前記の選択された複数の各メモリ・セル内の前記デジタル情報を決定すること 、 前記コンパレータが前記の選択された複数の各メモリ・セル内の前記電荷に応 答した前記電圧を前記の複数の基準電圧のうちの第2の組の基準電圧と比較して 、前記デジタル情報に対応する前記電荷の前記電荷量における前記ドリフトを決 定すること、および 前記制御回路が前記情報ビットに対応する前記電荷の前記電荷量における前記 ドリフトの前記決定を表す状況フラグを設定することを特徴とする請求項14に 記載の集積回路。 18.複数のメモリ・セルを有する集積回路メモリ・システムを動作させる方法 であって、 それぞれ情報ビットに対応する複数の離散量のいずれかで各メモリ・セル内に 電荷を蓄積する段階と、 前記の一離散量におけるドリフトに応答して前記メモリ・セル内の電荷を復元 する段階とを含み、 それによって前記メモリ・セル内の情報ビットの喪失を回避する方法。 19.第1シーケンスの基準値に対して各メモリ・セル内の電荷量を検出して各 メモリ・セルごとに前記の対応する情報ビットを決定する段階をさらに含む請求 項18に記載の方法。 20.前記検出段階が前記電荷量に対応する値と前記第1シーケンスの基準値と を反復して比較する段階を含み、ある比較段階での基準値が前の比較段階の結果 によって決まり、 さらに第2シーケンスの基準値に対して各メモリ・セル内の前記電荷量におけ るドリフトを決定する段階と、 そうしたドリフト決定段階がドリフトの存在を肯定した場合にドリフトの方向 を表す少なくとも1つの状況フラグを設定する段階とを含むことを特徴とする請 求項19に記載の方法。 21.前記メモリ・セルに関係する記憶域に前記の少なくとも1つの状況フラグ を保存する段階をさらに含む請求項20に記載の方法。 22.前記ドリフト決定段階が前記電荷量に対応する値と前記第2シーケンスの 基準値とを反復して比較する段階を含み、ある比較段階での基準値が前の比較段 階の結果によって決まることを特徴とする請求項20に記載の方法。 23.前記第2シーケンスの基準値との前記反復比較段階がそれぞれ、前記第1 シーケンスの基準値との前記反復比較段階のいずれかに続いて行われることを特 徴とする請求項22に記載の方法。 24.前記検出段階が前記の対応する情報ビットがすべて論理「1」とすべて論 理「0」のどちらと判定したかに応じて、前記電荷量に対応する前記値と前記シ ーケンスの基準値のどれよりも大きいまたは小さい基準値とを比較する段階をさ らに含む請求項20に記載の方法。 25.各メモリ・セル内に電荷を蓄積するための前記の複数の離散量が2N個か らなること、および前記比較手段を少なくともN回だけ繰り返すことを特徴とす る請求項20に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/640,367 US5815439A (en) | 1996-04-30 | 1996-04-30 | Stabilization circuits and techniques for storage and retrieval of single or multiple digital bits per memory cell |
US08/640,367 | 1996-04-30 | ||
PCT/US1997/007152 WO1997041640A1 (en) | 1996-04-30 | 1997-04-28 | Stabilization circuits for multiple digital bits |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2001508218A true JP2001508218A (ja) | 2001-06-19 |
JP3706146B2 JP3706146B2 (ja) | 2005-10-12 |
Family
ID=24567961
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53914497A Expired - Lifetime JP3706146B2 (ja) | 1996-04-30 | 1997-04-28 | 複数デジタル・ビットのための安定化回路 |
Country Status (9)
Country | Link |
---|---|
US (2) | US5815439A (ja) |
EP (1) | EP0896763B1 (ja) |
JP (1) | JP3706146B2 (ja) |
KR (1) | KR100522561B1 (ja) |
CN (1) | CN1126256C (ja) |
AT (1) | ATE235094T1 (ja) |
DE (1) | DE69719968T2 (ja) |
TW (1) | TW345660B (ja) |
WO (1) | WO1997041640A1 (ja) |
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JP2012109012A (ja) * | 2006-08-05 | 2012-06-07 | Benhov Gmbh Llc | 固体記憶素子及び方法 |
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JP2009524176A (ja) * | 2006-01-20 | 2009-06-25 | マーベル ワールド トレード リミテッド | フラッシュメモリにおける誤り訂正のための方法およびシステム |
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JP2012109012A (ja) * | 2006-08-05 | 2012-06-07 | Benhov Gmbh Llc | 固体記憶素子及び方法 |
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US5815439A (en) | 1998-09-29 |
KR100522561B1 (ko) | 2006-01-27 |
DE69719968T2 (de) | 2004-01-08 |
US5901089A (en) | 1999-05-04 |
EP0896763B1 (en) | 2003-03-19 |
WO1997041640A1 (en) | 1997-11-06 |
ATE235094T1 (de) | 2003-04-15 |
DE69719968D1 (de) | 2003-04-24 |
CN1126256C (zh) | 2003-10-29 |
KR20000065145A (ko) | 2000-11-06 |
JP3706146B2 (ja) | 2005-10-12 |
TW345660B (en) | 1998-11-21 |
CN1268261A (zh) | 2000-09-27 |
EP0896763A4 (en) | 2000-08-16 |
EP0896763A1 (en) | 1999-02-17 |
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