JP2000299337A - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法

Info

Publication number
JP2000299337A
JP2000299337A JP11105586A JP10558699A JP2000299337A JP 2000299337 A JP2000299337 A JP 2000299337A JP 11105586 A JP11105586 A JP 11105586A JP 10558699 A JP10558699 A JP 10558699A JP 2000299337 A JP2000299337 A JP 2000299337A
Authority
JP
Japan
Prior art keywords
conductive metal
metal layer
electrode
semiconductor device
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11105586A
Other languages
English (en)
Japanese (ja)
Other versions
JP2000299337A5 (https=
Inventor
Eiji Watanabe
英二 渡辺
Koichi Murata
浩一 村田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11105586A priority Critical patent/JP2000299337A/ja
Priority to US09/515,515 priority patent/US6614113B2/en
Priority to TW089103776A priority patent/TW533519B/zh
Priority to KR10-2000-0011551A priority patent/KR100536036B1/ko
Publication of JP2000299337A publication Critical patent/JP2000299337A/ja
Publication of JP2000299337A5 publication Critical patent/JP2000299337A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/934—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
JP11105586A 1999-04-13 1999-04-13 半導体装置及びその製造方法 Pending JP2000299337A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP11105586A JP2000299337A (ja) 1999-04-13 1999-04-13 半導体装置及びその製造方法
US09/515,515 US6614113B2 (en) 1999-04-13 2000-02-29 Semiconductor device and method for producing the same
TW089103776A TW533519B (en) 1999-04-13 2000-03-03 Semiconductor device and method for producing the same
KR10-2000-0011551A KR100536036B1 (ko) 1999-04-13 2000-03-08 반도체 장치

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11105586A JP2000299337A (ja) 1999-04-13 1999-04-13 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
JP2000299337A true JP2000299337A (ja) 2000-10-24
JP2000299337A5 JP2000299337A5 (https=) 2006-06-01

Family

ID=14411614

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11105586A Pending JP2000299337A (ja) 1999-04-13 1999-04-13 半導体装置及びその製造方法

Country Status (4)

Country Link
US (1) US6614113B2 (https=)
JP (1) JP2000299337A (https=)
KR (1) KR100536036B1 (https=)
TW (1) TW533519B (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003045875A (ja) * 2001-07-30 2003-02-14 Nec Kagobutsu Device Kk 半導体装置およびその製造方法
US6528881B1 (en) 1999-08-27 2003-03-04 Nec Corporation Semiconductor device utilizing a side wall to prevent deterioration between electrode pad and barrier layer
KR100519893B1 (ko) * 2001-11-15 2005-10-13 인피니온 테크놀로지스 아게 기판상의 상호접속부 제조 방법

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6768210B2 (en) * 2001-11-01 2004-07-27 Texas Instruments Incorporated Bumpless wafer scale device and board assembly
JP2003140347A (ja) * 2001-11-02 2003-05-14 Tokyo Ohka Kogyo Co Ltd 厚膜ホトレジスト層積層体、厚膜レジストパターンの製造方法、および接続端子の製造方法
JP2003188313A (ja) * 2001-12-20 2003-07-04 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US6762503B2 (en) * 2002-08-29 2004-07-13 Micron Technology, Inc. Innovative solder ball pad structure to ease design rule, methods of fabricating same and substrates, electronic device assemblies and systems employing same
US6995475B2 (en) * 2003-09-18 2006-02-07 International Business Machines Corporation I/C chip suitable for wire bonding
US20050167837A1 (en) * 2004-01-21 2005-08-04 International Business Machines Corporation Device with area array pads for test probing
US7910471B2 (en) * 2004-02-02 2011-03-22 Texas Instruments Incorporated Bumpless wafer scale device and board assembly
JP3981089B2 (ja) * 2004-02-18 2007-09-26 株式会社東芝 半導体装置とその製造方法
TWI278946B (en) * 2004-07-23 2007-04-11 Advanced Semiconductor Eng Structure and formation method for conductive bump
US20060087039A1 (en) * 2004-10-22 2006-04-27 Taiwan Semiconductor Manufacturing Company, Ltd. Ubm structure for improving reliability and performance
US7416980B2 (en) * 2005-03-11 2008-08-26 Intel Corporation Forming a barrier layer in interconnect joints and structures formed thereby
KR100762354B1 (ko) * 2006-09-11 2007-10-12 주식회사 네패스 플립칩 반도체 패키지 및 그 제조방법
JP5101169B2 (ja) * 2007-05-30 2012-12-19 新光電気工業株式会社 配線基板とその製造方法
CN101765913B (zh) * 2007-07-30 2012-10-03 Nxp股份有限公司 底部粗糙度减小的半导体部件的应力缓冲元件
US8349721B2 (en) * 2008-03-19 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming insulating layer on conductive traces for electrical isolation in fine pitch bonding
JP5350022B2 (ja) * 2009-03-04 2013-11-27 パナソニック株式会社 半導体装置、及び該半導体装置を備えた実装体
US9607936B2 (en) * 2009-10-29 2017-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Copper bump joint structures with improved crack resistance
US8847387B2 (en) * 2009-10-29 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Robust joint structure for flip-chip bonding
KR101187977B1 (ko) * 2009-12-08 2012-10-05 삼성전기주식회사 패키지 기판 및 그의 제조방법
US9159652B2 (en) * 2013-02-25 2015-10-13 Stmicroelectronics S.R.L. Electronic device comprising at least a chip enclosed in a package and a corresponding assembly process
US9666550B2 (en) * 2014-12-16 2017-05-30 Tongfu Microelectronics Co., Ltd. Method and structure for wafer-level packaging

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63161649A (ja) * 1986-12-25 1988-07-05 Casio Comput Co Ltd 半導体装置の製造方法
EP0308971B1 (en) * 1987-09-24 1993-11-24 Kabushiki Kaisha Toshiba Bump and method of manufacturing the same
JP3361881B2 (ja) * 1994-04-28 2003-01-07 株式会社東芝 半導体装置とその製造方法
JP3238011B2 (ja) * 1994-07-27 2001-12-10 株式会社東芝 半導体装置
JPH10150249A (ja) * 1996-11-20 1998-06-02 Ibiden Co Ltd プリント配線板
US5977632A (en) * 1998-02-02 1999-11-02 Motorola, Inc. Flip chip bump structure and method of making

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6528881B1 (en) 1999-08-27 2003-03-04 Nec Corporation Semiconductor device utilizing a side wall to prevent deterioration between electrode pad and barrier layer
JP3387083B2 (ja) 1999-08-27 2003-03-17 日本電気株式会社 半導体装置及びその製造方法
JP2003045875A (ja) * 2001-07-30 2003-02-14 Nec Kagobutsu Device Kk 半導体装置およびその製造方法
KR100519893B1 (ko) * 2001-11-15 2005-10-13 인피니온 테크놀로지스 아게 기판상의 상호접속부 제조 방법

Also Published As

Publication number Publication date
KR100536036B1 (ko) 2005-12-12
US6614113B2 (en) 2003-09-02
US20020003302A1 (en) 2002-01-10
KR20000076789A (ko) 2000-12-26
TW533519B (en) 2003-05-21

Similar Documents

Publication Publication Date Title
JP2000299337A (ja) 半導体装置及びその製造方法
US5648686A (en) Connecting electrode portion in semiconductor device
US7445958B2 (en) Semiconductor device having a leading wiring layer
JP2001093928A (ja) 半導体装置及びその製造方法
US6774495B2 (en) Solder terminal and fabricating method thereof
US6784557B2 (en) Semiconductor device including a diffusion layer formed between electrode portions
TW200404344A (en) Connection terminals and manufacturing method of the same, semiconductor device and manufacturing method of the same
TWI307152B (en) Under bump metallurgy
JP3648585B2 (ja) 半導体装置及びその製造方法
TWI338344B (en) Semiconductor chip with solder bump suppressing growth of inter-metallic compound and method of frabricating the same
US6897141B2 (en) Solder terminal and fabricating method thereof
JP3860028B2 (ja) 半導体装置
JP2002280407A (ja) 半導体チップ及び半導体装置、回路基板並びに電子機器
JP2000150518A (ja) 半導体装置の製造方法
US20060017171A1 (en) Formation method and structure of conductive bumps
WO2006070808A1 (ja) 半導体チップおよびその製造方法、半導体チップの電極構造およびその形成方法、ならびに半導体装置
JP2004014854A (ja) 半導体装置
JP2006108284A (ja) 半導体パッケージ
JPH11145174A (ja) 半導体装置およびその製造方法
TWI284969B (en) Apparatus to reduce occurrences of delamination between flip-chip underfill and UBM structure
JP6836615B2 (ja) 半導体装置および半導体装置の製造方法
JP4270788B2 (ja) 半導体装置およびその製造方法
CN1503328A (zh) 具有焊块底部金属化结构的半导体装置及其制程
TWI244187B (en) Method of forming conductive connection structure on multilayer board and structure thereof
JP2022071925A (ja) 半導体装置および半導体装置の製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060412

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20060412

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20080526

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080603

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20081014