TWI338344B - Semiconductor chip with solder bump suppressing growth of inter-metallic compound and method of frabricating the same - Google Patents

Semiconductor chip with solder bump suppressing growth of inter-metallic compound and method of frabricating the same Download PDF

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Publication number
TWI338344B
TWI338344B TW095140824A TW95140824A TWI338344B TW I338344 B TWI338344 B TW I338344B TW 095140824 A TW095140824 A TW 095140824A TW 95140824 A TW95140824 A TW 95140824A TW I338344 B TWI338344 B TW I338344B
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Taiwan
Prior art keywords
layer
alloy
solder bump
metal adhesion
solder
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TW095140824A
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Chinese (zh)
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TW200733273A (en
Inventor
In Soo Kang
Joon Young Choi
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Nepes Corp
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Publication of TW200733273A publication Critical patent/TW200733273A/en
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Publication of TWI338344B publication Critical patent/TWI338344B/en

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Description

1338344 九、發明說明： 【發明所屬之技術領域】 本發明與具有銲料凸塊之半導體晶片及其製造方法有 關’更明確而言為與具有銲料凸塊以抑制介金屬化合物成 長之半導趙晶片及其製造方法。 【先前技術】1338344 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor wafer having solder bumps and a method of fabricating the same, and more specifically to a semiconductor wafer having a solder bump to suppress growth of a metal compound And its manufacturing method. [Prior Art]

大體上，以打線接合技術所製造的半導體封裝具有利 用導線來電連接半導體晶片墊的印刷電路板電極终端。因 此’半導艘封裝相較於半導體晶片具較大尺寸，且因其需 花費太多時間方能完成打線接合，因此具有必須縮減尺寸 與不易量產的缺點。 由於半導艘晶片的高集積度、高效能、與高速性吾 人嘗試各式方法企圖降低尺寸並量產該半導體封裝。最近 有關於此半導趙封裝的試驗結果建議，可將印刷電路板電 極終端經由金屬銲料（如，形成於半導體晶片的電極墊上的 鲜料凸塊）而直接電連結半導體晶片的電極墊。 此經由銲料凸塊製造的傳統半導體封裝 JiS ^ _ 少 w、第 1 圖 .1《 η π嘢面圖。 =&之，第1圖為於在半導體晶片上使用短& 裝前，形成於傳统本娄艚沾 吏用#料完成封 t烕於傳統+導體曰曰片的銲料凸& 3〇 如第1圖所示，丰導俨面圖° 所不手導體日曰片10具電極墊1 1飛士认盆 上。同時，半專目入 七成於/、 體日0片10具電層21形成於其上，使得 5 1338344 電極塾 11的上表面可以外露。一或多 UBM(under bump metal, UBM)層，通常為三UBM層22、23與24形成於電 極塾上11，其上表面藉介電層21而外露。在此，該三UBM 層包含黏著層22、擴散阻障層23與可濕層24。銲料凸塊 30最終形成於該ubM層22、23與24的最上層24»在此， 當形成時’銲料凸塊3〇與該UB Μ層22、23與24反應， 以使介於銲料凸塊3〇與UBM層22、23與24間之界面產In general, semiconductor packages fabricated by wire bonding techniques have printed circuit board electrode terminations that electrically connect the semiconductor wafer pads with wires. Therefore, the semi-conductor package has a larger size than the semiconductor wafer, and since it takes too much time to complete the wire bonding, it has the disadvantage of being downsized and not easily mass-produced. Due to the high degree of integration, high performance, and high speed of semi-conducting wafers, we have tried various methods to reduce the size and mass-produce the semiconductor package. Recent experimental results regarding this semiconductor package suggest that the printed circuit board electrode terminals can be directly electrically bonded to the electrode pads of the semiconductor wafer via metal solder (e.g., fresh bumps formed on the electrode pads of the semiconductor wafer). This is a conventional semiconductor package fabricated by solder bumps, JiS ^ _ less w, 1 1 .1 "η π 嘢 。. =&, Fig. 1 is a solder bump formed on a semiconductor wafer using a short & pre-fabricated, formed in a conventional 娄艚 娄艚 吏 # # 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 焊料 焊料 焊料 焊料 焊料 焊料 焊料 焊料 焊料 焊料 焊料 焊料 焊料As shown in Figure 1, the 俨 俨 ° ° 所 所 所 所 导体 导体 导体 导体 导体 导体 导体 导体 导体 10 10 10 10 10 10 10 10 10 10 10 At the same time, a semi-specialized 70% of the 10 electric layers 21 are formed on the body, so that the upper surface of the 5 1338344 electrode 塾 11 can be exposed. One or more layers of UBM (UBM), usually three UBM layers 22, 23 and 24 are formed on the electrode stack 11, and the upper surface thereof is exposed by the dielectric layer 21. Here, the three UBM layers include an adhesive layer 22, a diffusion barrier layer 23, and a wettable layer 24. Solder bumps 30 are ultimately formed in the uppermost layer 24 of the ubM layers 22, 23 and 24. Here, when formed, the solder bumps 3〇 react with the UB layer 22, 23 and 24 to cause solder bumps. Interface between block 3〇 and UBM layer 22, 23 and 24

生於介金屬化合物（intermetallic compound, IMC)。IMC 之 產生帶來介於銲料凸塊30與UBM層22、23與24間的濕 满效應’從而完成實際上的物理連結。 然而’當實際應用藉銲料凸塊3〇連結半導體封裝時， 將從銲料凸塊產生熱。該熱會導致IMC具易脆的機械特 性，因此會在銲料凸塊30與UBM層22、23與24間的界 面出現預期外的成長，因Λ IMC可能比預期更厚。此現象 可導致半導敢封袭的機械性質變弱，纟對半導艘封裝 靠度具極大影響。Born from intermetallic compounds (IMC). The generation of IMC brings about a wet-out effect between the solder bumps 30 and the UBM layers 22, 23 and 24 to complete the actual physical connection. However, when the actual application is to bond the semiconductor package by solder bumps, heat is generated from the solder bumps. This heat causes the IMC to have fragile mechanical properties and therefore an unexpected growth in the interface between the solder bumps 30 and the UBM layers 22, 23 and 24, since the IMC may be thicker than expected. This phenomenon can lead to weaker mechanical properties of the semi-conductor, and it has a great influence on the packaging of the semi-guided ship.

。’，亦可能有其他界面現象影響半導體封装的 度其中一現象為，銲料凸塊30溶入^^^層22、 β 24。因此失去UBM層22、23與24，使得焊料3亩 接與半導體晶片丨Λ 视30直 日曰片10内的金屬墊U接觸，因而在銲 30與半導雜ay1A 丹凸塊 差。 Ba片10的金屬墊II間發生失誤，使可濕性變 【發明内容】 6 1338344 因此，本發明鑑於上述問題且本發明目的在於提供具 銲料凸塊的半導體晶片，其中一層間分隔層、與一穿透層 (其之材料可滲入銲料凸塊中），係形成於至少一 UBM層與 銲料凸塊間，由此改變銲料凸塊之組成並從而抑制位於銲 料凸塊界面間的介金屬化合物（inter-metallic compound, IMC)之成長。. </ RTI> There may be other interface phenomena that affect the degree of semiconductor package. One of the phenomena is that the solder bumps 30 dissolve into the layers 22 and β 24 . Therefore, the UBM layers 22, 23, and 24 are lost, so that the solder 3 abuts the metal pad U in the semiconductor wafer 30, and thus the solder 30 is inferior to the semi-conductive ay1A. The error occurs between the metal pads II of the Ba sheet 10 to change the wettability. [Inventive] 6 1338344 Accordingly, the present invention has been made in view of the above problems and an object of the present invention is to provide a semiconductor wafer having solder bumps, wherein a layer of interlayers is a penetrating layer (the material of which can penetrate into the solder bumps) is formed between at least one of the UBM layers and the solder bumps, thereby changing the composition of the solder bumps and thereby suppressing the intermetallic compound located between the solder bump interfaces (inter-metallic compound, IMC) growth.

根據本發明一態樣，提供具銲料凸塊的半導體晶片。 半導體晶片包含至少一金屬黏著層係形成於半導體晶片的 電極墊上；一層間分隔層係形成於該金屬黏著層上；至少 一穿透層係形成於該層間分隔層上且滲入該銲料凸塊中； 以及該銲料凸塊係形成於該穿透層上。 由此結構，該金屬黏著層係經由該層間分隔層而與該 銲料凸塊隔離，且經由該穿透層改變該銲料凸塊之組成以 抑制IMC的成長。-According to one aspect of the invention, a semiconductor wafer with solder bumps is provided. The semiconductor wafer comprises at least one metal adhesion layer formed on the electrode pad of the semiconductor wafer; an interlayer separation layer is formed on the metal adhesion layer; at least one penetration layer is formed on the interlayer separation layer and penetrates into the solder bump And the solder bump is formed on the penetrating layer. With this structure, the metal adhesion layer is isolated from the solder bump via the interlayer spacer layer, and the composition of the solder bump is changed via the penetration layer to suppress the growth of the IMC. -

此時在該些金屬黏著層中，可由鈦、致合金、铭、铭 合金、錄、錄合金、銅、銅合金、鉻、絡合金、金、與金 合金之至少一者來形成一第一金屬黏著層。 再者，於該些金屬黏著層中，可由錄、鎳合金、銅、 銅合金、纪、與把合金之至少一者來形成一第二金屬黏著 層。由此，該第一金屬黏著層可與該層間分隔層更加牢固 地接合。 同時，可由鎳、鎳合金、鈀、與鈀合金之一來形成該 層間分隔層。 可由銅、銅合金、錄、錄合金、銦、銦合金、錫、錫 7 丄桃344 ^金、鉍、Μ合金、鉑、鉑合金、金與金合金之至少—者 來形成該穿透層。 再者’銲料凸塊可由金、共晶鉛銲料（Sn/37Pb )、高 釓薛料（Sn/95Pb)、與選自錫/銀、錫/銅、錫/鋅、踢/鋅/ 级、踢/銀/銅、與錫/銀/鉍之一的無鉛銲料來形成。 根據本發明一態樣，提供製造具銲料凸塊的半導想晶 片之方法。該方法包含步驟：形成至少一金屬黏著層於誃At this time, in the metal adhesive layer, a first one may be formed by at least one of titanium, alloy, Ming, Ming alloy, recorded alloy, copper, copper alloy, chromium, complex alloy, gold, and gold alloy. Metal adhesion layer. Further, in the metal adhesion layer, a second metal adhesion layer may be formed by at least one of a nickel alloy, a copper alloy, a copper alloy, a copper alloy, and a metal alloy. Thereby, the first metal adhesion layer can be more firmly bonded to the interlayer separation layer. Meanwhile, the interlayer separation layer may be formed of one of nickel, a nickel alloy, palladium, and a palladium alloy. The penetrating layer may be formed of at least copper, copper alloy, recorded, recorded alloy, indium, indium alloy, tin, tin, 7 丄 344 ^ gold, tantalum, niobium alloy, platinum, platinum alloy, gold and gold alloy. . Furthermore, the solder bumps can be made of gold, eutectic lead solder (Sn/37Pb), sorghum (Sn/95Pb), and selected from tin/silver, tin/copper, tin/zinc, kick/zinc/grade, Kick/silver/copper, formed with lead-free solder of one of tin/silver/铋. According to one aspect of the invention, a method of fabricating a semiconductor wafer with solder bumps is provided. The method comprises the steps of: forming at least one metal adhesion layer on the crucible

半導體晶片的雷炼執人 妁電極墊上，形成一層間分隔層於該金屬黏著 層上；形成至少一穿捸甩μ 芽边廣於該層間分隔層上以於形成該銲 料'凸塊時渗入該錄料&amp; , -¾辞料凸塊中；以及形成該銲料凸塊於該穿 X々汝更包含步驟：在形成金屬黏著層後，形 成光阻圖樣於金屈垄荽 屬黏著層上表面的相對端。其中層間分隔 、》成於金屬黏著層上的光阻圖樣之間。形成層間分隔 步驟係藉錢鍍製程或電鍵製程施行。形成穿透層之步A semiconductor wafer is mounted on the electrode pad to form an interlayer spacer layer on the metal adhesion layer; and at least one via bud is formed on the interlayer spacer layer to penetrate the interlayer solder layer to form the solder bump. Recording &amp;, -3⁄4 lexem bumps; and forming the solder bumps in the X-rays further comprising the steps of: forming a photoresist pattern on the upper surface of the adhesive layer of the genus The opposite end. The interlayer separation, "between the photoresist patterns on the metal adhesion layer." The step of forming the interlayer separation is performed by a money plating process or a key switch process. Step of forming a penetrating layer

驟係藉機鍵製@ 戰製程或電鍍製程施行。 再者，該，r 、、+ ^ .. 更包3步驟：重流（re flowing)銲料凸塊。 由此，該穿读 層可經由重流製程而滲入以抑制imc的成 長。 【實施方式】 本發明示箱普：&amp; 4 把貫施例參照、將詳盡說明如下。 第2圖為根 ^ 艰本發明具銲料凸塊以抑制IM C成長的半 導體晶片的斷^ 圖。如第2圖所示，本發明半導體晶片1〇〇 8 1338344Suddenly take advantage of the @key process or electroplating process. Furthermore, r, , + ^ .. further includes 3 steps: reflowing the solder bumps. Thereby, the transmissive layer can be infiltrated through the reflow process to suppress the growth of imc. [Embodiment] The present invention is described with reference to the following examples, which will be described in detail below. Fig. 2 is a diagram showing a semiconductor wafer with solder bumps for suppressing the growth of IM C. As shown in FIG. 2, the semiconductor wafer of the present invention 1 〇〇 8 1338344

具至少一電極墊110形成於其上，且半導體晶片 份形成於其上的介電層 210使得電極墊 110的 露。一或多金屬黏著層220與230形成於電極墊 該電極墊110的上表面藉部份形成的介電層210 外。層間分隔層240形成於金屬黏著層230上。 透層250形成於層間分隔層240上，使得當形成 時可滲入該銲料凸塊中。最後銲料凸塊300形成 250 上。 更明確而言，電極墊110可由金屬組成並形 體晶片100上。電極墊110可電連結半導體晶片 外部電路板。介電層210形成於半導體晶片100 極墊110的上表面暴露於外。 於金屬黏著層220與230間，第一金屬黏著 由欽、鈦合金、銘、铭合金、錄、錄合金、銅、 鉻、鉻合金、金、與金合金之至少一者來組成， 成於部份形成的介電層210上與電極墊110(其 介電層210而暴露於外）&quot;UBM層220與230較 厚度可為200埃至20000埃。 第二金屬黏著層 230可形成於第一金屬黏 上。此時第二金屬黏著層230可由適於接合第一 層220與層間分隔層240之物質組成，較佳為鎳 銅、銅合金、纪、與把合金之任一者組成。 層間分隔層 240可由適於接合金屬黏著層 與穿透層250之物質組成，較佳為鎳、鎳合金、 1 0 0具部 上表面外 1 1 0 上， 而暴露於 至少一穿 銲料凸塊 於穿透層 成於半導 100 與一 上以使電 層220可 銅合金、 且同時形 上表面藉 佳之形成 著層 220 金屬黏著 、鎮合金、 220 ' 230 纪、與把 9 1338344At least one electrode pad 110 is formed thereon, and a dielectric layer 210 on which the semiconductor wafer is formed causes the electrode pad 110 to be exposed. One or more metal adhesion layers 220 and 230 are formed on the electrode pad. The upper surface of the electrode pad 110 is external to the dielectric layer 210 formed by a portion. An interlayer spacer 240 is formed on the metal adhesion layer 230. The transmissive layer 250 is formed on the interlayer spacer layer 240 so as to penetrate into the solder bumps when formed. Finally, solder bumps 300 are formed on 250. More specifically, the electrode pad 110 may be composed of a metal and formed on the wafer 100. The electrode pad 110 can electrically connect the semiconductor chip external circuit board. The dielectric layer 210 is formed on the upper surface of the semiconductor wafer 100 pad 110 and exposed to the outside. Between the metal adhesion layers 220 and 230, the first metal adhesion is composed of at least one of Qin, titanium alloy, Ming, Ming alloy, recorded alloy, copper, chromium, chromium alloy, gold, and gold alloy. The partially formed dielectric layer 210 and the electrode pad 110 (the dielectric layer 210 is exposed to the outside) &quot;UBM layers 220 and 230 may have a thickness of 200 angstroms to 20,000 angstroms. The second metal adhesion layer 230 may be formed on the first metal paste. At this time, the second metal adhesion layer 230 may be composed of a material suitable for bonding the first layer 220 and the interlayer separation layer 240, preferably nickel copper, copper alloy, and any of the alloys. The interlayer spacer layer 240 may be composed of a material suitable for bonding the metal adhesion layer and the penetration layer 250, preferably nickel, nickel alloy, and the top surface of the 1000 surface, and exposed to at least one solder bump. The penetrating layer is formed on the semiconducting layer 100 and the upper layer so that the electric layer 220 can be made of a copper alloy, and at the same time, the surface is formed by a layer 220. The metal bonding, the town alloy, the 220' 230, and the 9 1338344

合金之至少一者組成，層間分隔層240係形成在 黏著層220之上，因此可將金屬黏著層220、230 250和銲料凸塊300彼此隔離。 穿透層250可由銅、銅合金、銻、銻合金、 金、锡、錫合金、Μ、祕合金、翻、始合金、金 之至少一者組成，且形成於層間分隔層240上。穿 可依銲料凸塊300尺寸而具各式厚度，且可為銲 量之0.1至10%。於形成穿透層250的物質中， 塊3 00以富含錫之無鉛銲料形成時，銅可對IMC 成長做出極大改變。更明確而言，添加少量銅至 料凸塊300，可改善銲料凸塊300之特性。然而 塊3 00内之銅過飽合時，可能會使銲料凸塊300 高。為此，於銲料凸塊300與層間分隔層240間 層250。因此當銲料凸塊300經由重流製程形成 層250可滲入銲料凸塊300中。 銲料凸塊 300可由金、不含鉛銲料與鉛銲 成。在此，不含錯的銲料較佳可由錫/銀、錫/銅 錫/鋅/鉍、錫/銀/銅、與錫/銀/鉍至少一者組成。 選自高鉛銲料與共晶鉛銲料之任一者。 第3圖為根據本發明形成銲料凸塊於半導體 抑制IMC成長之製程流程圖，且第4圖至第12 3圖所示製程之斷面圖。 形成銲料凸塊於半導體晶片上的製程將參照 第二金屬 與穿透層 銦、銦合 與金合金 透層250 料凸塊重 當銲料凸 之形狀與 錫銀的銲 當銲料凸 的熔點升 形成穿透 時，穿透 料之一組 、錫/鋅、 鉛銲料可 晶片上以 圖為如第 第3圖、 10 1338344 與第4至12圖而描述於下。 首先，如第4圖所示，電極墊110係形成於半導體晶 片100(S101)上，並接著形成介電層210橫過半導體晶 片100以使電極墊110的上表面外露在半導體晶片100上 (S102 ) 〇At least one of the alloys is formed, and an interlayer spacer 240 is formed over the adhesive layer 220, so that the metal adhesive layers 220, 230 250 and the solder bumps 300 can be isolated from each other. The penetrating layer 250 may be composed of at least one of copper, a copper alloy, tantalum, niobium alloy, gold, tin, tin alloy, niobium, a secret alloy, a turning alloy, and gold, and is formed on the interlayer separating layer 240. The wear may be of various thicknesses depending on the size of the solder bump 300, and may be 0.1 to 10% of the amount of solder. In the formation of the penetrating layer 250, when the block 300 is formed of tin-free lead-free solder, copper can greatly change the IMC growth. More specifically, the addition of a small amount of copper bumps 300 improves the characteristics of the solder bumps 300. However, when the copper in block 300 is saturated, the solder bumps 300 may be high. To this end, a layer 250 is interposed between the solder bumps 300 and the interlayer spacer layer 240. Therefore, the solder bumps 300 can penetrate into the solder bumps 300 via the reflow process forming layer 250. Solder bumps 300 can be soldered with gold, lead-free solder and lead. Here, the solder containing no defects may preferably be composed of at least one of tin/silver, tin/copper tin/zinc/bismuth, tin/silver/copper, and tin/silver/iridium. It is selected from any of high lead solder and eutectic lead solder. Fig. 3 is a flow chart showing a process flow for forming a solder bump in a semiconductor suppressing IMC growth according to the present invention, and a process view of the process shown in Figs. 4 to 23; The process of forming the solder bump on the semiconductor wafer will be described with reference to the second metal and the penetrating layer of indium, indium and gold alloy through layer. The bumps of the gold alloy are as thick as the shape of the solder bump and the solder of tin silver is formed as the melting point of the solder bump. When penetrating, a group of penetrating materials, tin/zinc, and lead solder can be described on the wafer as shown in Fig. 3, 10 1338344 and Figs. 4 to 12. First, as shown in FIG. 4, an electrode pad 110 is formed on the semiconductor wafer 100 (S101), and then a dielectric layer 210 is formed across the semiconductor wafer 100 to expose the upper surface of the electrode pad 110 on the semiconductor wafer 100 ( S102) 〇

接著，如第5圖與第6圖所示，經由濺鍍或電鍍而使 一或多金屬黏著層220與23 0形成於該部份形成的介電層 210與電極墊110上（其上表面藉介電層210外露）。金屬 黏著層220與230可具單由第一金屬黏著層220所組成之 結構，或由第一金屬黏著層22 0/第二金屬黏著層230組成 之結構。 接著，如第7圖所示，形成於第二金屬黏著層230上 的光阻圖樣301係為了形成層間分隔層240、穿透層250、 與銲料凸塊300 ( S104 )。Next, as shown in FIGS. 5 and 6, the one or more metal adhesion layers 220 and 230 are formed on the dielectric layer 210 and the electrode pad 110 formed by the sputtering or electroplating (the upper surface thereof) Exposed by the dielectric layer 210). The metal adhesive layers 220 and 230 may have a structure consisting of the first metal adhesion layer 220 alone or a first metal adhesion layer 22 / a second metal adhesion layer 230. Next, as shown in Fig. 7, the photoresist pattern 301 formed on the second metal adhesion layer 230 is formed to form the interlayer spacer layer 240, the penetration layer 250, and the solder bump 300 (S104).

接著，藉電鍍或濺鍍製程與使用光阻圖樣301(S1 05) 來形成層間分隔層240於第二金屬黏著層230上。此時如 上述，層間分隔層240可由金屬（如，鎳）組成。 如第8圖所示，藉電鍍或濺鍍製程與使用光阻圖樣301 (S106 )形成至少一穿透層250於層間分隔層240上。此 時如上述，穿透層250可由金屬（如，銅）組成。可調整穿 透層250的厚度或體積比以控制穿透層250於重流時滲入 銲料凸塊300之組成數量，因此穿透層250可為銲料凸塊 300重量之0.1至10%。 當使用始、始合金、金、或金合金作為穿透層時，可 11 1338344 強化 金屬 擴散 料凸 製程 如上 者組Next, an interlayer spacer layer 240 is formed on the second metal adhesion layer 230 by a plating or sputtering process and using a photoresist pattern 301 (S1 05). At this time, as described above, the interlayer spacer 240 may be composed of a metal such as nickel. As shown in FIG. 8, at least one penetration layer 250 is formed on the interlayer spacer layer 240 by a plating or sputtering process and using a photoresist pattern 301 (S106). At this time, as described above, the penetrating layer 250 may be composed of a metal such as copper. The thickness or volume ratio of the transmissive layer 250 can be adjusted to control the amount of penetration of the penetrating layer 250 into the solder bump 300 during reflow, and thus the penetrating layer 250 can be 0.1 to 10% by weight of the solder bump 300. When using the initial and initial alloys, gold, or gold alloys as the penetrating layer, 11 1338344 can be used to strengthen the metal diffusion material.

圖所 重流 使用 穿透 300 順序 穿透 之銲 亦可 為本 在不 與變 銲料凸塊300的可濕性並防止任何氧化UBM層（如， 黏著層或絕緣層）的作用。這些物質於重流製程時繪 進入銲料凸塊時，也因此預防了 IMC的成長。 如第9圖所示，藉使用光阻圖樣301 (S107)形成銲 塊3 00。此時銲料凸塊3 00可藉無電電鍍製程、蒸發 、附球製程、網印製程、喷銲製程、及其類似形成。 述，銲料凸塊300可由金、鉛銲料、與無鉛銲料之一 成。。 接著，如第10圖所示，移除光阻圖樣301，如第11 示，蝕刻金屬黏著層220與230,以及如第12圖所示， 銲料凸塊300。此時欲蝕刻金屬黏著層220與230，可 化學物濕蝕刻或使用物理方法乾蝕刻。重流的同時， 層250溶入銲料凸塊300因而消失。因此，銲料凸塊 組成改變。傳統技術之IM C成長問題因而獲得抑制。 如前述可知，根據本發明層間分隔層與穿透層以特定 形成，且銲料凸塊接著形成於穿透層上。由此，組成 層之物質滲入銲料凸塊，使得銲料凸塊轉變為多組成 料凸塊。從而抑制IMC成長，且半導體晶片的可靠度 獲得改善。 當本發明描述到關於考量為最佳實施例時，其應理解 發明並不受限於揭露之實施例與圖示；但相對地，其 悖離申請專利範圍之精神與範圍下意欲包含各式修正 型 。 12 1338344 【圖式簡單說明】 本發明前述與其他目的、特徵與優勢將藉下列詳細描 述與伴隨之圖示更加顯明： 第1圖為具銲料凸塊的傳統半導體晶片的斷面圖； 第2圖為根據本發明之具銲料凸塊以抑制IMC成長的 半導體晶片的斷面圖； 第3圖為根據本發明形成銲料凸塊於半導體晶片上以 抑制IMC成長的製程的流程圖；以及 Φ 第4圖至第12圖為第3圖製程的斷面圖。 U金屬墊 22黏著層 24可濕層 100半導體晶片 2 1 0介電層 230金屬黏著層 250穿透層 3 0 1光阻圖樣The reflow of the pattern using a through 300 sequential penetration soldering may also be used to protect the wettability of the solder bump 300 and prevent any oxidized UBM layer (e.g., an adhesive layer or an insulating layer). These materials prevent the growth of IMC when they are drawn into the solder bumps during the reflow process. As shown in Fig. 9, the solder bumps 00 are formed by using the photoresist pattern 301 (S107). At this time, the solder bumps 00 can be formed by an electroless plating process, an evaporation process, an attached ball process, a screen printing process, a spray welding process, and the like. As described, the solder bumps 300 may be formed of one of gold, lead solder, and lead-free solder. . Next, as shown in Fig. 10, the photoresist pattern 301 is removed, as shown in Fig. 11, the metal adhesion layers 220 and 230 are etched, and as shown in Fig. 12, the solder bumps 300. At this time, the metal adhesion layers 220 and 230 are etched, and the chemical may be wet etched or dry etched using a physical method. At the same time as the reflow, the layer 250 dissolves into the solder bumps 300 and thus disappears. Therefore, the solder bump composition changes. The IM C growth problem of the conventional technology is thus suppressed. As described above, the interlayer spacer layer and the penetration layer are specifically formed according to the present invention, and the solder bumps are then formed on the penetration layer. Thereby, the substance constituting the layer penetrates into the solder bump, so that the solder bump is converted into a multi-component bump. Thereby, the growth of the IMC is suppressed, and the reliability of the semiconductor wafer is improved. While the invention has been described with respect to the preferred embodiments, it is understood that the invention is not to be construed as Modified type. BRIEF DESCRIPTION OF THE DRAWINGS The foregoing and other objects, features and advantages of the present invention will become more apparent from the accompanying description and the accompanying drawings. FIG. 1 is a cross-sectional view of a conventional semiconductor wafer with solder bumps; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 3 is a cross-sectional view of a semiconductor wafer having solder bumps for suppressing IMC growth according to the present invention; FIG. 3 is a flow chart showing a process for forming solder bumps on a semiconductor wafer to suppress IMC growth according to the present invention; 4 to 12 are cross-sectional views of the process of Fig. 3. U metal pad 22 adhesive layer 24 wettable layer 100 semiconductor wafer 2 1 0 dielectric layer 230 metal adhesion layer 250 penetration layer 3 0 1 photoresist pattern

【主要元件符號說明】 10半導體晶片 21介電層 23擴散阻障層 30銲料凸塊 110電極墊 220金屬黏著層 240層間分隔層 3 00銲料凸塊 13[Main component symbol description] 10 semiconductor wafer 21 dielectric layer 23 diffusion barrier layer 30 solder bump 110 electrode pad 220 metal adhesion layer 240 interlayer separation layer 3 00 solder bump 13

Claims (1)

1338344 第w丨午小t號專f膝π年ί月修正 十、申請專利範圍： 丨舰 J 1. 一種具有銲料凸塊的半導體晶片，其至少包含： 至少一金屬黏著層，係形成於該半導體晶片的一電極墊 —層間分隔層，係形成於該金屬黏著層上； 至少一穿透層，係形成於該層間分隔層上且滲入該銲料 凸塊中，以將該銲料凸塊改變成一多成分之銲料凸塊，從 而抑制一介金屬化合物的成長；以及 該銲料凸塊，係形成於該穿透層上， 其中該層間分隔層係適於結合該至少一金屬黏著層與 該至少一穿透層，並結構上地分隔該至少一金屬黏著層與 該該至少一穿透層及該銲料凸塊，且其中該穿透層藉控制 該穿透層的厚度或體積比來形成，且其量為銲料凸塊重量 的0.1至10%間。1338344 The first w/ no small t-special f knee π-year ί 月 Amendment 10, the scope of application patent: J. J 1. A semiconductor wafer with solder bumps, comprising at least: at least one metal adhesive layer formed in the An electrode pad-interlayer spacer layer of the semiconductor wafer is formed on the metal adhesion layer; at least one penetration layer is formed on the interlayer separation layer and penetrates into the solder bump to change the solder bump into a multi-component solder bump to inhibit growth of a metal compound; and the solder bump is formed on the penetration layer, wherein the interlayer spacer is adapted to bond the at least one metal adhesion layer to the at least one Penetrating layer and structurally separating the at least one metal adhesion layer from the at least one penetration layer and the solder bump, and wherein the penetration layer is formed by controlling a thickness or volume ratio of the penetration layer, and The amount is between 0.1 and 10% of the weight of the solder bump. 2. 如申請專利範圍第1項所述之半導體晶片，其中在 該些金屬黏著層中，一第一金屬黏著層係由鈦、鈦合金、 銘、铭合金、錄、錄合金、銅、銅合金、絡、鉻合金、金、 與金合金之至少一者來形成。 3. 如申請專利範圍第1項所述之半導體晶片，其中在 該些金屬黏著層中，一第二金屬黏著層係有需要時由鎳、 錄合金、銅、銅合金、把、與纪合金之至少一者來形成。 [S} 14 1338344 4. 如申請專利範圍第1項所述之半導體晶片，其中該 層間分隔層係由錄、錄合金、奶、與紐合金之一者來形成。2. The semiconductor wafer according to claim 1, wherein in the metal adhesion layer, a first metal adhesion layer is made of titanium, titanium alloy, Ming, Ming alloy, recorded, recorded alloy, copper, copper. At least one of an alloy, a complex, a chromium alloy, gold, and a gold alloy is formed. 3. The semiconductor wafer of claim 1, wherein in the metal adhesion layer, a second metal adhesion layer is made of nickel, alloy, copper, copper alloy, and alloy. At least one of them is formed. [S} 14 1338344. The semiconductor wafer of claim 1, wherein the interlayer separation layer is formed by one of a recording and recording alloy, a milk, and a new alloy. 5. 如申請專利範圍第1項所述之半導體晶片，其中該 穿透層係由銅、銅合金、錄、錄合金、銦、銦合金、錫、 錫合金、叙、祕合金、钻、始合金、金與金合金之至少一 者來形成。 6. 如申請專利範圍第1項所述之半導體晶片，其中該 銲料凸塊係由下列之一者所組成：金、一無鉛銲料（其係選 自錫、錫/銀、錫/銅、錫/鋅、錫/鋅/鉍、錫/銀/銅與錫/銀/ 鉍之一）、以及一鉛銲料（其係選自高鉛銲料與共晶鉛銲料 之一者）。5. The semiconductor wafer according to claim 1, wherein the penetrating layer is made of copper, a copper alloy, a recording and recording alloy, an indium alloy, an indium alloy, a tin alloy, a tin alloy, a quartz alloy, a diamond alloy, a drill, and a spinner. At least one of an alloy, a gold, and a gold alloy is formed. 6. The semiconductor wafer of claim 1, wherein the solder bump is composed of one of: gold, a lead-free solder (which is selected from the group consisting of tin, tin/silver, tin/copper, tin). /Zinc, tin/zinc/bismuth, tin/silver/copper and tin/silver/铋 one), and a lead solder (which is selected from one of high lead solder and eutectic lead solder). 7. 一種製造具有一銲料凸塊的一半導體晶片的方 法，該方法包含如下步驟： 形成至少一金屬黏著層於該半導體晶片的一電極墊上； 形成一層間分隔層於該金屬黏著層上； 形成至少一穿透層於該層間分隔層上，以於當形成該銲 料凸塊時，可使該穿透層滲入該銲料凸塊中並將該銲料凸 塊改變成一多成分之銲料凸塊，從而抑制一介金屬化合物 的成長；以及 15 1338344 形成該銲料凸塊於該穿透層上， 其中該層間分隔層係適於結合該至少一金屬黏著層與 該至少一穿透層，並結構上地分隔該至少一金屬黏著層與 該該至少一穿透層及該銲料凸塊，且其中該穿透層藉控制 該穿透層的厚度或體積比來形成，且其量為銲料凸塊重量 的0.1至10%間。7. A method of fabricating a semiconductor wafer having a solder bump, the method comprising the steps of: forming at least one metal adhesion layer on an electrode pad of the semiconductor wafer; forming an interlayer spacer layer on the metal adhesion layer; forming At least one penetrating layer is disposed on the interlayer spacer layer, so that when the solder bump is formed, the penetrating layer may be infiltrated into the solder bump and the solder bump is changed into a multi-component solder bump. Thereby inhibiting the growth of a metal compound; and 15 1338344 forming the solder bump on the penetrating layer, wherein the interlayer insulating layer is adapted to bond the at least one metal adhesive layer and the at least one penetrating layer, and structurally Separating the at least one metal adhesion layer from the at least one penetration layer and the solder bump, and wherein the penetration layer is formed by controlling a thickness or volume ratio of the penetration layer, and the amount is the weight of the solder bump Between 0.1 and 10%. 8. 如申請專利範圍第7項所述之方法，更包含步驟： 在形成該金屬黏著層後，形成光阻圖樣於該金屬黏著層上 表面的相對端，其中該層間分隔層係形成於該金屬黏著層 上的該光阻圖樣之間。 9. 如申請專利範圍第7或第8項所述之方法，其中該 形成層間分隔層之步驟係藉濺鍍製程或電鍍製程施行。8. The method of claim 7, further comprising the steps of: forming a photoresist pattern on the opposite end of the upper surface of the metal adhesion layer after forming the metal adhesion layer, wherein the interlayer separation layer is formed on the metal adhesion layer Between the photoresist patterns on the metal adhesion layer. 9. The method of claim 7 or 8, wherein the step of forming the interlayer separation layer is performed by a sputtering process or an electroplating process. 10.如申請專利範圍第7項所述之方法，其中該形成穿 透層之步驟係藉濺鍍製程或電鍍製程施行。 11.如申請專利範圍第7項所述之方法，其更包含如下 步驟：重流該銲料凸塊。 16 [S.110. The method of claim 7, wherein the step of forming the permeation layer is performed by a sputtering process or an electroplating process. 11. The method of claim 7, further comprising the step of reflowing the solder bumps. 16 [S.1
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