JP2000189585A - Display driving circuit for game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate flicker of dynamic lighting display of a game machine. SOLUTION: The display driving circuit of the game machine is provided with a display driver 6 including a memory 6a storing the segment signal of display data outputted from a game control part 2 having a CPU executing game control at the interrupting period of a prescribed period and a matrix display 10 driven by the driver 6 and reads a segment signal stored in the memory 6a with the common signal of a period shorter than the interruption period of the CPU to dynamically drive the display 10. In addition, a common signal for reading and displaying display data is generated from a second oscillation circuit 6c which does not synchronize with a first oscillation circuit 2 deciding the interruption period of the CPU. In addition, a part excepting for the oscillator 7 of the circuit 6c in the driver 6 is formed of a one-chip integrated circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display driving circuit for a game machine, and more particularly to a technique for making display flicker less noticeable in dynamic driving of the display.

[0002]

2. Description of the Related Art A dynamic drive system is used for driving a display device in which LEDs used in a game machine such as a pachinko machine are arranged in a matrix. The CPU of the main control board that controls the display unit controls the various functions of the gaming machine in a time-division manner by performing "interrupt control" in order to generally control all the functions of the gaming machine.
The interrupt cycle of the CPU is currently 4 ms. In this case, the common signals COM0 to COM of the display unit
Assuming that n of n is 7, one character is displayed at a period of 32 ms (8 × 4 ms).

[0003]

However, when the display is dynamically driven in the interrupt cycle, there is a problem that the intervals between the lighting of each LED of the display are too long and the display contents of the display appear to flicker. . To make the flicker less noticeable, set the interrupt cycle to 1 ms to 2 ms.
However, since the CPU controls many functions of the gaming machine in a time-sharing manner by interrupt control as described above, it is very difficult to set the interrupt cycle to 1 ms to 2 ms. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a dynamic display driving circuit which eliminates the above-mentioned disadvantages of the conventional example and makes the flicker of the gaming machine less noticeable.

[0004]

Means for Solving the Problems In order to solve the above problems, the structure of the first invention according to the present application is as defined in claim 1.

According to the configuration of the first aspect of the present invention, a data signal (segment signal) for dynamically driving the display is stored in the display driver, and the stored data signal is used as an interrupt cycle of the game control unit having the CPU of the game machine. Since the display is driven by a common signal generated by a clock pulse having a shorter cycle, flicker of the display can be made inconspicuous.

Further, the structure of the second invention is as described in claim 2.

According to the configuration of the second invention, in addition to the operation of the configuration of the first invention, a first oscillation circuit for determining an interrupt cycle of the CPU and a common signal for generating a common signal when the display driver reads data are generated. Since the two oscillation circuits are asynchronously configured, even if the operation cycle of the dynamic drive of the display is measured, the interrupt cycle of the game control unit having the CPU cannot be measured. Can not be detected.

[0008] Further, the structure of the third invention is as described in claim 3.

According to the configuration of the third aspect of the invention, in addition to the operation of the configuration of the second aspect of the invention, the display driver includes at least the memory and the second oscillation circuit. Since the parts of the circuit other than the oscillator are constituted by one-chip integrated circuits, the components of the entire display drive circuit of the gaming machine can be simplified, and the space efficiency can be improved. Further, the reliability of the display driver circuit of the gaming machine is improved.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a display driving circuit block according to an embodiment of the present invention, and FIG.
3 shows a segment signal data setting area of the memory of the circuit block shown in FIG.
4 shows a time chart of a CPU output signal of the circuit block shown in FIG. 1, and FIG. 5 shows a time chart of an output signal of a display driver of the circuit block shown in FIG. ing. In FIGS. 4 and 5, the horizontal axis is the time axis.

In FIG. 1 to FIG. 5, a main control board 1 is a board for controlling the entire game machine such as a pachinko machine.
Oscillation circuit 2, game control unit 3 having CPU (central processing unit), ROM 4, RAM
5, a display driver 6, a crystal oscillator 7, an input processing circuit 8, and an output processing circuit 9. The display driver 6 includes a memory 6a, an address decoder 6b, a second oscillation circuit 6c,
A frequency dividing circuit 6d, a driving circuit 6e, an output circuit 6f, and a crystal oscillator 7 are provided. The first oscillation circuit 2 is a crystal oscillation circuit and outputs a clock signal to a game control unit 3 having a CPU.
To supply. The game control unit 3 having a CPU sends a data signal (an arrow 3a indicates a data signal supply path) and R / W.
A signal (write / read signal) (the arrow 3 b indicates a supply path of the R / W signal) is supplied to the display driver 6.

The output signals of the gate sensor 21, the starting port sensor 22 and the winning port sensor 23 are connected so as to be applied to the input processing circuit 8. The gate sensor 21 is a sensor that detects that a game ball has passed through a gate provided on a game board surface (not shown), and the starting port sensor 22 detects that a game ball has entered a starting port provided on the game board surface. Sensor. When a game ball enters the starting port, a special symbol displayed on a symbol display device provided on the game board surface changes. The winning port sensor 23 is a sensor that detects that a game ball has entered a winning port provided on the game board surface.

The output processing circuit 9 controlled by the game control unit 3 having a CPU includes a speaker 24 and a solenoid 25.
Control. The speaker 24 is for obtaining a sound effect such as a big hit, and the solenoid 25 is for opening a big winning hole provided on the game board surface at the time of the big hit of the special symbol, for example. When the special winning opening is opened, it becomes easier for game balls to win.

FIG. 4 shows the data signal (corresponding to a segment signal) and the R / W signal. The data signals are “D0 to Dm”. In the R / W signal, tc indicates a writing time of each byte in the memory 6a, and tco indicates an n-byte writing time in the memory 6a. tc is 0.1 to 0.5 μs, and tco is 1
0 to 30 μs. The data signal is synchronized with the R / W signal. The second oscillation circuit 6c is an oscillation circuit using the crystal oscillator 7, and supplies a pulse signal to the frequency dividing circuit 6d. Note that the oscillation frequency of the second oscillation circuit 6c is not synchronized with the oscillation frequency of the first oscillation circuit 2. The frequency dividing circuit 6d divides the pulse signal oscillated by the second oscillating circuit 6c to form a common signal.
a and the output circuit 6f.

The memory 6a is a game control unit 3 having a CPU.
Is stored as described above at the timing of the R / W signal. Note that the portion of the display driver 6 other than the crystal oscillator 7 is constituted by a dedicated one-chip integrated circuit. FIG. 2 shows a segment data setting area in the memory 6a. Address decoder 6
b denotes a chip select signal obtained by decoding an address signal output from the game control unit 3 having a CPU,
To supply. The chip select signal determines an address (segment data setting area) to be stored in the memory 6a.

As described above, the common signal of the display driver 6 is not synchronized with the clock signal transmitted by the first transmission circuit 2. For this reason, even if the period of the common signal of the display driver 6 is measured, the clock signal (CPU
Since the period of the clock signal of the game control unit 3 having the above cannot be determined, it is not possible to know the jackpot period of the gaming machine, so that it is possible to prevent illegal gaming of the gaming machine.

The drive circuit 6e amplifies the segment signal received from the memory 6a and supplies it to the LED display 10, and the output circuit 6f amplifies the common signal and supplies it to the LED display 10.

The LED display 10 is of an LED dynamic lighting type in which LEDs (light emitting diodes) are arranged in a matrix.
M0 to n, and the horizontal wiring shown is a segment wiring SE.
G0 to n. Note that the LED display 10 is used as a design display of a game machine or the like.

FIG. 3 shows a part 1 of the LED display 10 of FIG.
1 shows a detailed circuit. In FIG. 3, the LED 12 is connected between one of the common wirings, the common i wiring, and one of the segment wirings, the segment j wiring. Note that 0 <i ≦ n 0 <j ≦ m. In this case, when the common signal of the common i wiring is at a high level and the segment signal of the segment j wiring is at a low level, the light emitting diode 12 in FIG. 3 is turned on.

In FIG. 5, t0, t1 to tn (in this case, n = 7) are the ON times of the signals for the LED commons COM0 to COMn, which are 1 to 2 ms. t is the LED off time, which is 100 to 500 μs. The segment signal is stored in synchronization with the common signal.

For this reason, the period of the LED common signal is 2 m
s, if n = 7, about 16 ms (8 ×
One character is displayed at a period of 2 ms), and flickering can be prevented. Note that the data output from the game control unit 3 having a CPU has a period of 4 ms, and the next data may be interrupted. At that time, the same content as before can be repeatedly displayed. For this reason,
The flickering of the display contents of the LED display 10 is made inconspicuous, and the interruption period of the game control unit 3 having the CPU can be maintained at 4 ms, which is convenient. In the above embodiment, a liquid crystal display having the same performance can be used instead of the LED display 10.

[0022]

According to the first aspect of the present invention, a common signal generated by a clock pulse having a cycle shorter than an interrupt cycle of a game control section having a CPU of a game machine and a synchronous signal generated by the display drive circuit of the game machine according to the first invention of the present application. Since the display is dynamically driven by the data signal read out and read, the flicker of the display can be made inconspicuous.

Further, according to the second invention, in addition to the effect of the first invention, even if the cycle of the dynamic drive signal of the display is measured, the interrupt cycle of the CPU cannot be measured. Jackpot cycle cannot be detected. For this reason, it is possible to prevent illegal gaming of the gaming machine by measuring the dynamic drive signal of the display.

Further, according to the third aspect of the present invention, together with the effect of the second aspect of the present invention, the second aspect of the display driver comprises:
Since the parts of the oscillation circuit other than the oscillator are constituted by one-chip integrated circuits, the components of the entire display drive circuit of the gaming machine can be simplified, and the space efficiency can be improved. Further, the reliability of the display driver circuit of the gaming machine is improved, and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a display driver circuit of a gaming machine according to an embodiment of the present invention.

FIG. 2 is a table showing a segment data setting area of the memory of the block diagram shown in FIG. 1;

FIG. 3 is a circuit diagram showing details of a part of the LED display of the block diagram shown in FIG. 1;

FIG. 4 is a time chart showing output signals of a game control unit having the CPU shown in the block diagram of FIG. 1;

FIG. 5 is a time chart showing output signals of the display driver shown in FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Main control board 2 2nd oscillation circuit 3 Game control part which has CPU 6 Display driver 6a Memory 6c 2nd oscillation circuit 7 Oscillator 10 LED display

Claims (3)

[Claims] 1. A display driver including a memory for storing a segment signal of display data output from a game control unit having a CPU for executing a game control at a predetermined interrupt cycle, and a matrix display driven by the display driver. A display device driving circuit for a game machine, comprising: reading out a segment signal stored in the memory with a common signal having a cycle shorter than an interrupt cycle of the CPU to dynamically drive the matrix display. 2. A method according to claim 1, wherein a common signal for reading and displaying the display data is generated from a second oscillation circuit that is not synchronized with a first oscillation circuit that determines an interrupt cycle of the CPU. 2. A display driving circuit for a gaming machine according to claim 1. 3. The display driver according to claim 1, wherein the display driver includes at least the memory and the second oscillation circuit, and a portion of the display driver other than the oscillator of the second oscillation circuit is configured by a one-chip integrated circuit. 3. The display driving circuit of a gaming machine according to claim 2, wherein