JP2005052422A - Display controller for game machine, and the game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display controller for achieving versatility in the combination of a VDP (Video Display Processor) with a display driver and simplifying a game machine system, and to provide a game machine. <P>SOLUTION: A display controller 30 includes: a display control processor 310 for selecting the display state of a moving image; a VDP 320 for generating the image data of the selected display state; and a timing circuit 321 which is provided with a register part 322 for storing setting data for determining the condition of generating a timing signal to drive a gate driver 352 and a data driver 353 and which generates the timing signal based on the setting data. The display control processor 310 rewrites the setting data of the register part 322. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a display control device for a gaming machine and a gaming machine.

  Some gaming machines, such as pachinko machines and slot machines, display moving images on an image display unit according to the progress of the game in order to enhance the interest of the game. These gaming machines include a display driver that displays image data as an image on an image display unit, and a display control device that supplies image data according to the progress of the game to the display driver. The display control device displays a selected display mode on the image display unit and a display control processor that selects a display mode of a moving image on the image display unit based on an instruction from the main control device that controls the progress of the game. An image display processor (Video Display Processor, hereinafter referred to as VDP) for generating image data for the purpose.

  In a display control device of a gaming machine, a high-speed processing performance corresponding to the display rewriting speed of the image display unit is required for the VDP. Therefore, a processor that performs processing based on hardware combined with a logic circuit is used. On the other hand, as the display control processor, a processor that performs processing based on software is used because the degree of freedom in the development of display mode selection processing is required rather than the necessity of high-speed processing performance as that of VDP.

  The VDP sequentially supplies image data to the display driver together with a synchronization signal for display. The display driver that receives the supply of the synchronization signal and the image data displays the images one after another on the image display unit. A moving image is displayed on the image display unit by the continuous image display.

  Conventionally, the VDP and the display driver have separately mounted timing circuits for driving these circuits. The VDP timing circuit generates a unique timing signal for driving the mounted VDP, and the display driver timing circuit generates a unique timing signal for driving the mounted display driver. This realizes versatility in the combination of the VDP and the display driver.

Japanese Patent Laid-Open No. 11-282430

  These timing circuits have many circuit configurations that can be shared, and the gaming machine system as a whole has a redundant circuit configuration. Therefore, in order to simplify the gaming machine system, it is conceivable to integrate these timing circuits. In this integration, integration on the VDP side including an oscillator or the like is effective in terms of development. However, when the timing circuit is integrated on the VDP side, there is a problem that versatility in combination with the display driver is impaired. For this reason, when combining display drivers having different timing signal specifications due to differences in resolution of the image display unit, it is necessary to re-develop and redesign the timing circuit on the VDP side.

  The present invention has been made to solve the above-described problems, and realizes versatility in a combination of a VDP and a display driver, and can simplify a gaming machine system and a game. The purpose is to provide a machine.

  In order to solve the above-described problems, a display control device according to the present invention is mounted on a gaming machine having a display driver for displaying image data as an image on an image display unit, and the display driver displays image data according to the progress of the game. A display control processor for selecting a display mode of a moving image in the image display unit based on an instruction from a main control device that controls the progress of the game, and the selected display mode An image display processor for generating image data for displaying the image data on the image display unit, and a setting register for storing setting data for defining a generation condition of a timing signal for driving the display driver. A timing circuit for generating a timing signal based on the display control processor, wherein the display control processor rewrites the setting data in the setting register. Characterized in that it is a power sale processor.

  According to such a display control device and a gaming machine using the display control device, the display control processor drives not only a specific display driver but also various display drivers by rewriting the setting data in the setting register. be able to. As a result, even when a timing circuit for driving the display driver is provided in the display control device, versatility in the combination of the VDP and the display driver can be realized. Therefore, versatility in the combination of the VDP and the display driver can be realized, and the gaming machine system can be simplified. In addition, the setting data to be written can be changed by changing the software of the display control processor without developing and designing the timing circuit again. As a result, it is possible to suppress an increase in development man-hours due to changing the display driver, compared to hardware development / design.

  The display control device of the present invention having the above-described configuration and a gaming machine using the display control device can also take the following modes. The timing circuit may generate a timing signal for driving the display driver and a timing signal for driving the image display processor. Therefore, versatility in the combination of the VDP and the display driver can be realized, and the gaming machine system can be simplified.

  The display control device of the present invention includes a first oscillator that oscillates a first reference signal, and a second oscillator that oscillates a second reference signal having a frequency different from that of the first reference signal. The timing circuit is a circuit that generates a timing signal for driving the image display processor using the first reference signal, and generates a timing signal for driving the display driver using the second reference signal. There may be.

  According to such a display control device and a gaming machine using the display control device, timing signals based on independent clock frequencies can be generated for the VDP and the display driver. As a result, even if the clock frequency is finely adjusted according to one circuit characteristic, the clock frequency suitable for each circuit characteristic can be set without affecting the other clock frequency. Further, in the case of reducing electromagnetic interference (hereinafter referred to as EMI) in the gaming machine by spectrum spreading of the clock signal, the display of the display is performed by spectrum spreading by performing spectrum spreading only on the first oscillator. EMI in a gaming machine can be reduced without reducing image quality.

  The display control processor may be a processor that, when activated, starts selection of the display mode after writing setting data in the setting register. According to such a display control device and a gaming machine using this display control device, even if the setting register setting at the time of activation is abnormal setting data, the setting is made before starting the selection of the display mode. By writing normal setting data in the register, it is possible to prevent an abnormal moving image from being displayed when the gaming machine is activated.

  The display control processor may be a processor that periodically writes setting data in the setting register. According to such a display control device and a gaming machine using this display control device, even if the setting data of the setting register is erroneously written due to the influence of noise or the like and an abnormal moving image is displayed, it is periodically By writing the normal setting data, it is possible to resume normal moving image display.

  The image display unit may be a liquid crystal panel, and the display driver may include a gate driver and a data driver. Therefore, the present invention can also be applied to a liquid crystal display widely used as an image display device in gaming machines.

  In order to further clarify the configuration and operation of the present invention described above, a display control apparatus for a pachinko machine will be described below as one of display control apparatuses for a gaming machine to which the present invention is applied.

Table of Contents A. Example A- (1). Configuration of pachinko machine 10 A- (2). Configuration of Display Control Device 30 and LCD 35 A- (3). Configuration of timing circuit 321 of VDP 320 A- (4). Operation of CPU 311 of display control processor 310 A- (5). Operation of timing circuit 321 of VDP 320 Other Embodiments In this specification, a signal name prefixed with “#” means negative logic. “High level” means the “1” level of the two levels of the binary signal, and “Low level” means the “0” level.

A. Example:
A- (1). Configuration of the pachinko machine 10:
First, the external configuration of the pachinko machine 10 that is one embodiment of the present invention will be described. FIG. 1 is a front view of a pachinko machine 10 which is an embodiment of the present invention. The pachinko machine 10 includes an outer frame 11 that is fixed to an island facility of a pachinko store, an inner frame 12 that is fitted into the outer frame 11, a game board 13 that is arranged near the center of the inner frame 12 and plays a game ball, A glass frame 14 disposed in front of the game board 13 and having a glass plate in the center, a handle 15 for receiving an instruction for a player to launch a game ball on the game board 13, a card unit 90 for processing the rental of the game ball, etc. Prepare.

  A liquid crystal display (hereinafter referred to as “LCD”) 35 that is an image display device is provided at the center of the game board 13. Below the LCD 35, a winning opening 61 for receiving a winning game ball is provided. The winning opening 61 includes a switch 65 that detects a winning game ball and a solenoid 66 that expands and contracts the introduction path of the gaming ball in a predetermined case. The pachinko machine 10 includes electric decorations 55, 56, 57, 58, and 59 that incorporate a light emitting diode (LED) and emit light. The electrical decorations 55 and 56 are provided on the left and right ends of the game board 13, the electrical decoration 57 is provided on the upper part of the LCD 35, and the electrical decorations 58 and 59 are provided on the left and right of the upper part of the glass frame 14, respectively. A speaker 45 for outputting sound is built in the front center of the inner frame 12.

  Next, an electrical schematic configuration of the pachinko machine 10 will be described. FIG. 2 is a block diagram showing an electrical schematic configuration of the pachinko machine 10. The pachinko machine 10 includes a main control device 20 that controls the progress of a game. The main control device 20 includes a display control device 30, a sound control device 40, a lamp control device 50, a panel input / output device 60, and a payout control device 70. Etc. are electrically connected. The main control device 20, display control device 30, voice control device 40, lamp control device 50, panel input / output device 60, and payout control device 70 are provided on the back surface (not shown) of the inner frame 12.

  The display control device 30 controls the moving image display on the LCD 35 based on the control signal of the main control device 20. The sound control device 40 controls the output of sound in the speaker 45 based on the control signal of the main control device 20. The lamp control device 50 controls the light emission of the electric decorations 55, 56, 57, 58 and 59 based on the control signal of the main control device 20. Panel input / output device 60 transmits an input signal of switch 65 to main control device 20 and drives solenoid 66 based on the control signal of main control device 20. The payout control device 70 pays out a game ball as a prize ball based on a control signal from the main control device 20, and pays out a game ball as a rental ball based on a control signal from the card unit 90. 1 and 2 do not show all of the electrical decorations, switches, and solenoids, the pachinko machine 10 includes a plurality of each. Moreover, it is good also as a structure provided with multiple LCD35 and the speaker 45. FIG.

A- (2). Configurations of the display control device 30 and the LCD 35:
Next, the configuration of the display control device 30 and the LCD 35 will be described. FIG. 3 is a block diagram showing the internal configuration of the display control device 30 and the LCD 35. The display control device 30 and the LCD 35 are each housed in separate housings. The display control device 30 outputs image data corresponding to the progress of the game to the LCD 35 and outputs various timing signals to the LCD 35. This image data is image data (RGB data) in which the image is information based on luminance and color.

  The LCD 35 is a TFT (Thin Film Transistor) type active matrix drive LCD, a liquid crystal panel 351 which is an image display unit in which a plurality of pixels are formed in a matrix (m columns × n rows), and RGB data is a liquid crystal panel. A gate driver 352 and a data driver 353 which are display drivers to be displayed as an image on the 351, a backlight unit 354 which is a light source of the liquid crystal panel 351, a power supply circuit 355 which supplies power to various circuits in the LCD 35, and the like. Each pixel of the liquid crystal panel 351 is electrically connected to the data driver 353 by the data lines D1 to Dm in the column direction unit, and is electrically connected to the gate driver 352 by the gate lines G1 to Gn in the row direction unit. In each pixel at the matrix intersection of the data line and the gate line, a switching element and a capacitor element are integrated.

  The gate driver 352 turns on the switching elements of the pixels in the row connected to a predetermined gate line (hereinafter referred to as gate-on). The gate driver 352 outputs a gate-on pulse, and this pulse width is a gate-on period. In synchronization with the gate-on, the data driver 353 supplies the capacitor elements connected to the conductive switching elements by applying data voltages based on the RGB data to the data lines D1 to Dm. When charges are supplied to the capacitor elements, the pixels of the liquid crystal panel 351 change the polarization of the liquid crystal layer and transmit light from the backlight unit 354 to light up. By this operation, one line on the gate line is displayed. By performing this operation once for all the gate lines, one frame is displayed on the liquid crystal panel 351.

  The display control device 30 includes a display control processor 310 that selects a moving image display mode on the LCD 35 based on a control signal from the main control device 20, a VDP 320 that generates RGB data for displaying the selected display mode on the LCD 35, A character ROM (Read Only Memory) 330 that stores character image data used for generating image data in a nonvolatile manner is provided. Various circuits constituting the display control device 30 are provided on a single substrate having six wiring layers.

  The display control processor 310 of the display control device 30 includes a CPU (Central Processing Unit) 311 that performs various control processes in the display control device 30, a RAM (Random Access Memory) 312 that is a main memory of the CPU 311, and a control program executed by the CPU 311. A ROM 313 for storing data such as non-volatile data is provided. The CPU 311 and the RAM 312 are made into an MCM (Multi Chip Module) and sealed in a single package.

  The VDP 320 of the display control device 30 includes a data generation circuit 324 that generates RGB data, a timing circuit 321 that generates timing signals for driving various circuits in the display control device 30 and the LCD 35, and a reference for generating timing signals. An oscillator 323 that oscillates a signal is provided. Various circuits constituting the VDP 320 are sealed in a single package.

  The timing circuit 321 generates and outputs to the data generation circuit 324 a system clock signal (SC) for driving the data generation circuit 324 and a read signal for instructing timing for outputting RGB data. The data generation circuit 324 operates based on the system clock signal (SC), and outputs RGB data to the data driver 353 of the LCD 35 in synchronization with the read signal. In this embodiment, the signal is not used. However, when other peripheral devices such as a processor and a memory are connected in addition to the display control device 30, the timing circuit 321 drives these peripheral devices. A peripheral device clock signal (PC) can be generated and output.

  The timing circuit 321 instructs the gate driver 352 of the LCD 35 to start outputting a gate-on pulse, a gate start pulse signal (GS) that instructs the gate line to be turned on, a gate shift clock signal (GC), and a gate-on A gate-on enable signal (#GE) indicating the pulse width is generated and output. For the data driver 353, a horizontal clock signal (HC) for driving the data driver 353, a data start pulse signal (DS) for instructing start of output of RGB data, and a data latch for instructing application of RGB data to the data line An enable signal (DE) and a polarity inversion signal (INV) that indicates the timing of polarity inversion of the voltage applied to the pixel are generated. In this embodiment, the signal is not used, but when connected to another display that requires more timing signals than the LCD 35, the timing circuit 321 adds a spare signal ( X1 and X2) can be generated and output.

A- (3). Configuration of the timing circuit 321 of the VDP 320:
Next, the configuration of the timing circuit 321 of the VDP 320 will be described. FIG. 4 is a block diagram showing an internal configuration of the VDP 320. As shown in FIG. The timing circuit 321 of the VDP 320 includes a programmable clock generator (hereinafter referred to as PCG) 325 and 326 that generates various clock signals based on a reference signal from the oscillator 323, and a generation unit 327 that generates various timing signals. , 328, and a register unit 322 for storing setting data defining conditions for generating various timing signals. The PCGs 325 and 326 are circuits that generate a clock signal having a frequency corresponding to the setting data stored in the register unit 322. The generation units 327 and 328 are circuits composed of various PCG, PLL (Phase Lock Loop) circuits and oscillators, and are circuits that generate timing signals according to setting data stored in the register unit 322. The setting data stored in the register unit 322 is written by the CPU 311 of the display control processor 310 based on the program stored in the ROM 313 when the pachinko machine 10 is activated.

  The PCG 325 generates and outputs a system clock signal (SC) and a peripheral device clock signal (PC) based on the reference signal from the oscillator 323. The PCG 326 generates and outputs a dot clock signal (VC) which is a reference synchronization signal for displaying a moving image on the LCD 35 based on the reference signal from the oscillator 323.

  Based on the dot clock signal (VC), the generation unit 327 generates a vertical synchronization signal (#VSYNC) which is a vertical display timing for developing RGB data, and a horizontal synchronization signal (#HSYNC) which is a horizontal display timing. ) Is generated. The generation unit 328 generates various timing signals for driving the gate driver 352 and the data driver 353 in addition to the read signal based on the dot clock signal (VC), the vertical synchronization signal (#VSYNC), and the horizontal synchronization signal (#HSYNC). Is generated.

  Next, the configuration of the register unit 322 of the timing circuit 321 will be described. FIG. 5 is an explanatory diagram illustrating an example of the configuration and setting of the register unit 322 of the timing circuit 321. The register unit 322 includes a plurality of registers that store setting data of various signal generation conditions generated by the PCGs 325 and 326 and the generation units 327 and 328. FIG. 3 shows an example of setting of each register when the LCD 35 is an LCD module A having pixels of 400 columns × 234 rows and an LCD module B having pixels of 640 columns × 480 rows. Is represented.

  As registers related to the synchronization signal, there are provided a register (VTOTAL) for defining the fall timing of the vertical synchronization signal (#VSYNC) and a register (HTOTAL) for defining the fall timing of the horizontal synchronization signal (#HSYNC). As a register relating to the read signal, a register (VBACK) that defines a vertical output waiting period of RGB data, a register (VDSP) that defines a vertical output period of RGB data, and a horizontal output waiting period of RGB data A register (HBACK) for defining and a register (HDSP) for defining a horizontal output period of RGB data are provided.

  The registers related to the gate driver 352 include a register (GS_J) that defines the vertical timing of the rise of the gate start pulse signal (GS), a register (GS_K) that defines the vertical timing of the fall of the gate start pulse signal (GS), a gate A register (GS_H) that defines the horizontal timing of the start pulse signal (GS), a register (GC_J) that defines the rising timing of the gate shift clock signal (GC), and the falling timing of the gate shift clock signal (GC) Register (GC_K), a register (#GE_J) that defines the rising timing of the gate-on enable signal (#GE), and a register (#GE_K) that defines the falling timing of the gate-on enable signal (#GE) Equipped with a.

  The registers related to the data driver 353 include a register (DS_J) that defines the rising timing of the data start pulse signal (DS), a register (DS_K) that defines the falling timing of the data start pulse signal (DS), and a data latch enable. A register (DE_J) that defines the rising timing of the signal (DE) and a register (DE_K) that defines the falling timing of the data latch enable signal (DE) are provided.

  The registers related to the spare signals (X1, X2) include a register (X1_J) that defines the rising timing of the spare signal (X1), a register (X1_K) that defines the falling timing of the spare signal (X1), and a spare signal ( A register (X2_J) for defining the rising timing of X2) and a register (X2_K) for defining the falling timing of the spare signal (X2). In the case of the present embodiment shown in FIG. 3, the registers relating to these spare timing signals are blank, and no spare timing signal is generated.

  Although not shown in FIG. 5, the register unit 322 is a register for setting the frequencies of the system clock signal (SC), the peripheral device clock signal (PC), the dot clock signal (VC), and the horizontal clock signal (HC). Prepare. When the value of the setting register of the horizontal clock signal (HC) is “0”, the horizontal clock signal (HC) is the same signal as the dot clock signal (VC). In the case of “1”, the frequency of the dot clock signal (VC) is divided by two. In the case of “2”, the dot clock signal (VC) is divided by four. In addition, a polarity inversion mode register for setting the mode of the polarity inversion signal (INV) is also provided. When the value of the polarity inversion mode register is “0”, the timing circuit outputs a frame inversion mode polarity inversion signal (INV) that inverts the polarity in units of all pixels. In the case of “1”, the polarity inversion signal (INV) in the vertical line inversion mode for inverting the polarity in units of pixels on the data line is output. In the case of “2”, the polarity inversion signal (INV) in the horizontal line inversion mode for inverting the polarity in pixel units of the gate line is output. In the case of “3”, a polarity inversion signal (INV) in a dod inversion mode for inverting the polarity in units of one pixel is output. The horizontal clock signal (HC) setting register and the polarity inversion mode register are selected according to the specifications of the liquid crystal panel 351 and the like.

A- (4). Operation of CPU 311 of display control processor 310:
Next, a startup process that is one of the operations of the CPU 311 of the display control processor 310 will be described. FIG. 6 is a flowchart showing a startup process of the CPU 311 of the display control processor 310. This activation process is a process that is executed immediately after power is supplied to the CPU 311 when the display control device 30 is activated.

  When the power is supplied, the CPU 311 performs a startup process. When the start process is started, an initial setting process is performed (step S110). In the initial setting process, after the RAM 312 is checked, a control program is read from the ROM 313 and executed, and various system settings relating to the display control processor 310 are performed. Thereafter, the timing signal generation condition setting data stored in the ROM 313 is written to the register unit 322 of the timing circuit 321 (step S120). Thereafter, the activation process is terminated, and the display mode selection process for selecting the display mode of the moving image is started. Note that the timing signal generation condition setting data may be periodically written between the display mode selection processes.

A- (5). Operation of the timing circuit 321 of the VDP 320:
Next, the operation of the timing circuit 321 of the VDP 320 will be described. As an example of the operation of the timing circuit 321, the operation of generating a timing signal based on the setting of the LCD module A (400 × 234) shown in FIG. 5 will be described. FIG. 7 is a time chart showing timing signals generated based on the settings of the LCD module A shown in FIG. In the present embodiment, it is assumed that the horizontal clock signal (HC) is generated at the same timing as the dot clock signal (VC) for simplicity of explanation. In the following description, “clock” used as a unit refers to the time during which the number of pulses of the horizontal clock signal (HC) is generated.

  The generation unit 327 of the timing circuit 321 generates a vertical synchronization signal (#VSYNC) and a horizontal synchronization signal (#HSYNC) based on the dot clock signal (VC). In the case of the LCD module A, the horizontal synchronization signal (#HSYNC) is a signal in which a falling pulse is generated at a clock interval of “528 (value of HTOTAL in FIG. 5)” (FIG. 7 (e)). The vertical synchronization signal (#VSYNC) is a signal in which a falling pulse is generated at intervals at which “262 (value of VTOTAL in FIG. 5)” of the horizontal synchronization signal (#HSYNC) is output (FIG. 7). (A), (b)). In FIG. 7, “c” after the number means “clock”, and “p” after the number indicates the time when the number of pulses of the horizontal synchronization signal (#HSYNC) is generated, that is, It means 528 clocks.

  For the RGB data, by synchronizing with the read signal generated by the generation unit 328 of the timing circuit 321, “15” of the horizontal synchronization signal (#HSYNC) after the falling edge (timing t 1 A) of the vertical synchronization signal (#VSYNC). (Value of VBACK in FIG. 5) The data for the first line is output in synchronization with the falling of the pulse p15. Thereafter, data for one line is successively output for each pulse up to the 249th pulse p249, and data for “234 (value of VDSP in FIG. 5)” corresponding to one frame is output (FIG. 7 ( c)). The output of the data for one line is started after “108 (value of HBACK in FIG. 5)” clock from the falling edge of the pulse of the horizontal synchronization signal (#HSYNC). Between the subsequent “400 (value of HDSP in FIG. 5)” clocks, data for one pixel is successively output every clock, and data for 400 pixels corresponding to one line is output (FIG. 7F). , (K)).

  The generation unit 328 of the timing circuit 321 generates various timing signals based on the dot clock signal (VC), the vertical synchronization signal (#VSYNC), and the horizontal synchronization signal (#HSYNC). From the falling edge of the pulse of the vertical synchronization signal (#VSYNC) (timing t1A), when the falling edge of the 13th pulse (value of GS_J in FIG. 5) of the horizontal synchronization signal (#HSYNC) is received (timing) At t2A), the gate start pulse signal (GS) is raised (FIG. 7D). The rise of the gate start pulse signal (GS) is after “264 (value of GS_H in FIG. 5)” clock (timing t3A) from the falling of the pulse p13 of the horizontal synchronization signal (#HSYNC) (timing t2A). (FIG. 7 (g)). After that, when the trailing edge of the “14 (value of GS_K in FIG. 5)” pulse p14 following the pulse p13 in the horizontal synchronization signal (#HSYNC) is received (timing t4A), the gate start pulse signal (GS) is generated. It falls (FIG. 7 (d)). The fall of the gate start pulse signal (GS) is after “264 (value of GS_H in FIG. 5)” clock (timing t5A) from the falling of the pulse p14 of the horizontal synchronization signal (#HSYNC) (timing t4A). (FIG. 7 (g)).

  Thereafter, with respect to the timing signal for the gate driver 352, when the falling of the pulse p15 next to the pulse p14 in the horizontal synchronization signal (#HSYNC) is received (timing t6A), after “0 (the value of GC_J in FIG. 5)” That is, the gate shift clock signal (GC) is immediately raised (timing t6A), and the gate-on enable signal (#GE) is lowered (timing t7A) after "90 (value of #GE_K in FIG. 5)" clock. After that, from the fall of the pulse p15 of the horizontal synchronization signal (#HSYNC) (timing t6A), after the “264 (value of GC_K in FIG. 5)” clock, the gate shift clock signal (GC) falls (timing t8A). 500 (value of #GE_J in FIG. 5) "The gate-on enable signal (#GE) is raised after the clock (timing t9A) (FIGS. 7 (h) and (i)). After that, when the falling edge of the pulse p16 next to the pulse p15 in the horizontal synchronization signal (#HSYNC) is received (timing t10A), the gate shift clock signal (GC) and the gate on enable signal (#GE) are the same as in the case of the pulse p15. ) Is generated.

  On the other hand, regarding the timing signal for the data driver 353, when the falling of the pulse p15 of the horizontal synchronization signal (#HSYNC) is received (timing t6A), the data latch enable signal (DE) is set to “10 (value of DE_J in FIG. 5). "Rise after the clock (timing t1a)", "80 (DE_K value in FIG. 5)" falls after the clock (timing t2a), and the data start pulse signal (DS) is "105 (DS_J value in FIG. 5)" clock It rises later (timing t3a) and falls after “106 (value of DS_K in FIG. 5)” clock (timing t4a) (FIG. 7 (l), (m)). Thereafter, when the falling of the pulse p16 following the pulse p15 in the horizontal synchronization signal (#HSYNC) is received (timing t10A), the data latch enable signal (DE) and the data start pulse signal (DS) are the same as in the case of the pulse p15. The pulse is generated.

  By generating pulses of the gate shift clock signal (GC), the gate on enable signal (#GE), the data latch enable signal (DE), and the data start pulse signal (DS), one line is drawn on the liquid crystal panel 351. Is called. The generation of these timing signal pulses is repeated 234 times in response to the fall of the horizontal synchronization signal (#HSYNC) from pulse p15 to pulse p249. In the period from the pulse p15 to the pulse p249 of the horizontal synchronization signal (#HSYNC), RBG data is output from the VDP 320 to the data driver 353 for 108 clocks after the falling of these pulses. FIG. 7 (c), (f), (k)).

  Thereafter, when the fall of the pulse of the vertical synchronization signal (#VSYNC) is received again (timing t11A), the above operation is similarly performed from the beginning (FIG. 7A). By this series of operations, drawing for one frame is performed on the liquid crystal panel 351.

  Next, as an example of the operation of the timing circuit 321, an operation of generating a timing signal based on the setting of the LCD module B (640 × 480) illustrated in FIG. 5 will be described. FIG. 8 is a time chart showing timing signals generated based on the settings of the LCD module B shown in FIG. In the case of the LCD module B, various timing signals are generated based on the setting data of the register unit 322 in the same manner as in the case of the LCD module A shown in FIG.

  According to the display control device 30 and the pachinko machine 10 using the display control device 30 according to the embodiment described above, the CPU 311 of the display control processor 310 rewrites the setting data in the register unit 322 so that only a specific display driver is used. In addition, various display drivers can be driven. As a result, even if a timing circuit for driving the display driver is provided in the display control device 30, versatility in the combination of the VDP 320 and the display driver can be realized. Therefore, versatility in the combination of the VDP 320 and the display driver can be realized, and the gaming machine system can be simplified.

  Further, the setting data to be written can be changed by changing the software of the CPU 311 stored in the ROM 313 of the display control processor 310 without developing and designing the timing circuit 321 again. As a result, it is possible to suppress an increase in development man-hours due to changing the display driver, compared to hardware development / design. In addition, a timing circuit for driving the data generation circuit 324, the gate driver 352, and the data driver 353 of the VDP 320 can be integrated. Therefore, versatility in the combination of the VDP and the display driver can be realized, and the gaming machine system can be simplified. Even if the setting data of the register unit 322 at the time of activation is abnormal setting data, the normal setting data is written in the register unit 322 before starting the selection of the display mode, so that the pachinko machine 10 It is possible to prevent an abnormal moving image from being displayed at the time of activation.

B. Other embodiments:
As mentioned above, although embodiment of this invention was described, this invention is not limited to such embodiment at all, Of course, it can implement with various forms within the range which does not deviate from the meaning of this invention. is there. For example, various timing signals may not be generated from a single reference signal oscillated by the oscillator 323 but may be generated from a plurality of reference signals.

  Here, a display control device that generates timing signals from a plurality of reference signals will be described. This display control device is the same as the display control device 30 shown in FIG. 3 except that a VDP 340 is provided instead of the VDP 320. FIG. 9 is a block diagram illustrating an internal configuration of the VDP 340 according to another embodiment. The configuration of VDP 340 is the same as that of VDP 320 except that oscillators 342 and 343 are provided instead of oscillator 323 in VDP 320. The PCG 325 in the VDP 340 generates a system clock signal (SC) and a peripheral device clock signal (PC) based on the reference signal of the oscillator 342. On the other hand, the PCG 326 generates a dot clock signal (VC) based on the reference signal of the oscillator 343. The operation of the VDP 340 is the same as that described above except that timing signals are generated from the two oscillators 342 and 343.

  According to the display control device of the other embodiments described above and the pachinko machine using the display control device, the data generation circuit 324 of the VDP 340, the gate driver 352 and the data driver 353 which are display drivers are provided. The timing signals based on the independent clock frequencies can be generated. As a result, even if the clock frequency is finely adjusted according to one circuit characteristic, the clock frequency suitable for each circuit characteristic can be set without affecting the other clock frequency. Further, when the EMI in the pachinko machine 10 is to be reduced by spectrum spreading of the clock signal, the spectrum spreading is performed only for the oscillator 342 so that the display image quality of the LCD 35 is not degraded by the spectrum spreading. The EMI in the machine 10 can be reduced.

  The gaming machine to which the present invention is applied is not limited to a pachinko machine, and may be applied to a gaming machine including an image display unit such as a slot machine. The image display device is not limited to the LCD, and may be applied to a CRT display, an EL display, or the like. The setting data is not written to the register unit 322 by the CPU 311 of the display control processor 310, but from the LCD 35 which is an image display device or the hall computer of the game hall which manages the pachinko machine 10. Also good. When setting data is written from the image display device, the setting data can be written without changing the design of software or the like on the display control device 30 side. When setting data is written from the hall computer, setting data of a plurality of pachinko machines can be centrally managed.

It is a front view of the pachinko machine 10 which is one form of the present invention. 2 is a block diagram showing an electrical schematic configuration of a pachinko machine 10. FIG. 3 is a block diagram showing an internal configuration of a display control device 30 and an LCD 35. FIG. It is a block diagram which shows the internal structure of VDP320. 3 is an explanatory diagram illustrating an example of a configuration and setting of a register unit 322 of a timing circuit 321. FIG. 4 is a flowchart showing a startup process of a CPU 311 of a display control processor 310. 6 is a time chart showing timing signals generated based on the settings of the LCD module A shown in FIG. 5. 6 is a time chart showing timing signals generated based on the settings of the LCD module B shown in FIG. 5. It is a block diagram which shows the internal structure of VDP340 of other embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Pachinko machine 11 ... Outer frame 12 ... Inner frame 13 ... Game board 14 ... Glass frame 15 ... Handle 20 ... Main controller 30 ... Display controller 35 ... LCD
40 ... Voice control device 45 ... Speaker 50 ... Lamp control device 55, 56, 57, 58, 59 ... Electric decoration 60 ... Panel input / output device 61 ... Winning hole 65 .. Switch 66 ... Solenoid 70 ... Dispensing control device 90 ... Card unit 310 ... Display control processor 311 ... CPU
312 ... RAM
313 ... ROM
320 ... VDP
321 ... Timing circuit 322 ... Register section 323 ... Oscillator 324 ... Data generation circuit 325, 326 ... PCG
327, 328 ... generating unit 330 ... character ROM
340 ... VDP
342, 343 ... Oscillator 351 ... Liquid crystal panel 352 ... Gate driver 353 ... Data driver 354 ... Backlight unit 355 ... Power supply circuit

Claims (5)

A display control device that is mounted on a gaming machine having a display driver that displays image data as an image on an image display unit, and that supplies image data according to the progress of the game to the display driver,
A display control processor that selects a display mode of a moving image in the image display unit based on an instruction from a main control device that controls the progress of the game;
An image display processor for generating image data for displaying the selected display mode on the image display unit;
A setting register that stores setting data that defines a generation condition of a timing signal for driving the display driver, and a timing circuit that generates a timing signal based on the setting data.
The display control processor is a processor for rewriting setting data in the setting register.   The display control apparatus according to claim 1, wherein the timing circuit is a circuit that generates a timing signal for driving the display driver and a timing signal for driving the image display processor. The display control device according to claim 1 or 2,
A first oscillator for oscillating a first reference signal;
A second oscillator that oscillates a second reference signal having a frequency different from that of the first reference signal;
The timing circuit is a circuit that generates a timing signal for driving the image display processor using the first reference signal and generates a timing signal for driving the display driver using the second reference signal. Display control device. The display control device according to any one of claims 1 to 3,
The image display unit is a liquid crystal panel,
The display driver comprises a gate driver and a data driver.   A gaming machine using the display control device according to any one of claims 1 to 4.

Images