JP2017124169A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine realizing a high image quality of a display device, while suppressing unnecessary radiation noise.SOLUTION: A game machine is provided with an image control part 23' which includes: a one-chip microcomputer 60 for generally controlling an image presentation, on the basis of a control command received from a presentation control part 22'; and a VDP 62 for supplying the image display data generated on the basis of an instruction received from the one-chip microcomputer 60 to a display device DS to progress the image presentation. A part of the operation of the VDP 62 is performed on the basis of a modulation clock Φb where a regular center frequency is shifted within a predetermined range.SELECTED DRAWING: Figure 8

Description

  The present invention relates to a gaming machine that generates a big hit state by a lottery process resulting from a gaming operation, and more particularly to a gaming machine that suppresses the occurrence of unnecessary radiation noise.

  A ball game machine such as a pachinko machine has a symbol start opening provided on the game board, a symbol display section for displaying a series of symbol variation patterns by a plurality of display symbols, and a big winning opening for opening and closing the opening and closing plate. Configured. When the detection switch provided at the symbol start port detects the passage of the game ball, the winning state is entered, and after the game ball is paid out as a prize ball, the display symbol is changed for a predetermined time in the symbol display section. Thereafter, when the symbol is stopped in a predetermined manner such as 7, 7, 7, etc., a big hit state is established, and the big winning opening is repeatedly opened to generate a gaming state advantageous to the player.

  Whether or not to generate such a game state is determined by a jackpot lottery executed on the condition that a game ball has won at the symbol start opening, and the above symbol variation operation is based on this lottery result. It has become a thing. For example, when the lottery result is in a winning state, an effect operation called reach action or the like is executed for about 20 seconds, and then the special symbols are aligned. On the other hand, a similar reach action may be executed even in the case of a lost state. In this case, the player pays close attention to the big hit state and pays close attention to the transition of the performance operation. When the predetermined symbols are aligned on the stop line at the end of the symbol variation operation, the player is guaranteed to be in the big hit state.

JP 2013-128578 A

  The above-described effect operation is centered on the image effect on the liquid crystal display device. However, in order to increase the force of the image effect, the image quality of the liquid crystal display device has been remarkable recently. As a result, the amount of data per pixel increases and the number of pixels (resolution) of the liquid crystal display device also increases, and a large amount of image data is transferred from the VDP (Video Display Processor) to the liquid crystal display device. Need to be transmitted at a high speed corresponding to (Patent Document 1).

  For this reason, the transmission line of the image data functions as a radiation antenna for unnecessary radiation noise EMI (Electro Magnetic Interference), which adversely affects the surrounding computer electronic elements and may cause the computer to run out of control. Here, the range of adverse effects is not necessarily limited to the inside of the gaming machine, and if the portable computer device of the player is adversely affected, it may cause trouble between the player and the gaming hall.

  Various noise countermeasures have been proposed. For example, when an LVDS signal is transmitted to a display device, five pairs of differential signal lines are required. Moreover, it cannot be said that it is preferable in terms of cost.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a gaming machine that realizes high image quality of a display device while suppressing unnecessary radiation noise.

  To achieve the above object, the present invention provides a first processor that generally controls image effects based on control commands received from other control means, and image display data generated based on instructions received from the first processor. And a second processor for advancing the image production by providing the image processing means to the display device, wherein at least part of the operation of the second processor has a predetermined center frequency at a predetermined center frequency. It is configured to be executed based on the modulation clock shifted in the range of.

  Preferably, the operation executed based on the modulation clock includes an image display data generation operation and an image display data output operation. Further, it is preferable that the center frequency of the modulation clock is set corresponding to the operation time for displaying one pixel of the display device. More preferably, it should be an integer multiple of the dot clock frequency.

  The second processor is preferably supplied with a system clock different from the modulation clock, and the frequency of the system clock is preferably fixed without being frequency-modulated. The amount of frequency shift with respect to the center frequency of the modulation clock is preferably limited to a predetermined range (preferably 3.0% or less, more preferably 2.0% or less) with respect to the center frequency. Further, the image display data is output from the second processor as a differential signal, or is output from the second processor as a single-ended signal.

  As described above, according to the gaming machine of the present invention, it is possible to achieve high image quality of the display device while suppressing unnecessary radiation noise.

It is a perspective view of the pachinko machine shown in an example. It is the front view which illustrated the game board of the pachinko machine of FIG. It is a block diagram which shows the whole structure of the pachinko machine of FIG. It is a block diagram illustrating a circuit configuration of an effect control unit. It is drawing explaining a frequency modulation circuit. It is drawing explaining the principal part and operation | movement content of the internal structure of the one-chip microcomputer of an effect control part. It is a block diagram which shows the internal structure of three lamp drive boards. It is a block diagram which illustrates the circuit structure of an image control part. 2 is a diagram illustrating an internal configuration and operation of a power supply sequence circuit. It is a block diagram which illustrates the internal structure of VDP. It is drawing explaining the connection relation of VDP and a display apparatus.

  Hereinafter, the present invention will be described in detail based on examples. FIG. 1 is a perspective view showing a pachinko machine GM of the present embodiment. This pachinko machine GM includes a rectangular frame-shaped wooden outer frame 1 that is detachably mounted on an island structure, and a front frame 3 that is pivotably mounted via a hinge 2 fixed to the outer frame 1. It is configured. A game board 5 is detachably attached to the front frame 3 from the front side, not from the back side, and a glass door 6 and a front plate 7 are pivotally attached to the front side so as to be openable and closable.

  On the outer periphery of the glass door 6, an electric lamp such as an LED lamp is arranged in a substantially C shape. On the other hand, at the upper left and right positions and the lower side of the glass door 6, all three speakers are arranged. The two speakers arranged in the upper part are each configured to output sound of the left and right channels R and L, and the lower speaker is configured to output heavy bass.

  The front plate 7 is provided with an upper plate 8 for storing game balls for launching, and a lower plate 9 for storing game balls overflowing or extracted from the upper plate 8 and a launch handle at the lower part of the front frame 3. 10 are provided. The launch handle 10 is interlocked with the launch motor, and a game ball is launched by a striking rod that operates according to the rotation angle of the launch handle 10.

  A chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated with the left hand of the player, and the player can operate the chance button 11 without releasing the right hand from the firing handle 10. The chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp is turned on and can be operated. The button chance state is a game state provided as necessary.

  On the right side of the upper plate 8, an operation panel 12 for ball lending operation with respect to the card-type ball lending machine is provided, a frequency display unit for displaying the remaining amount of the card with a three-digit number, and a ball of game balls for a predetermined amount A ball lending switch for instructing lending and a return switch for instructing to return the card at the end of the game are provided.

  As shown in FIG. 2, a guide rail 13 made of a metal outer rail and an inner rail is provided on the surface of the game board 5 in an annular shape, and a central opening HO is provided at the approximate center thereof. A display device DS composed of a large liquid crystal color display (LCD) is disposed in the central opening HO.

  The display device DS is a device that variably displays a specific symbol related to the big hit state and displays a background image and various characters in an animated manner. This display device DS has special symbol display portions Da to Dc in the center portion and a normal symbol display portion 19 in the upper right portion. In the special symbol display portions Da to Dc, there is a case where a reach effect that expects a big hit state is invited, and in the special symbol display portions Da to Dc and the surroundings, an appropriate notice effect is executed.

  In the game area where the game ball falls and moves, a symbol start port 15, a big winning port 16, a normal winning port 17, and a gate 18 are arranged. Each of these winning openings 15 to 18 has a detection switch inside, and can detect the passage of a game ball.

  The symbol start port 15 is configured to be opened and closed by an electric tulip having a pair of left and right opening and closing claws 15a, and when the stop symbol after fluctuation of the normal symbol display unit 17 displays a winning symbol, a predetermined time is displayed. The opening / closing claw 15a is opened only until a predetermined number of game balls are detected.

  The normal symbol display unit 19 displays a normal symbol. When a game ball that has passed through the gate 18 is detected, the normal symbol fluctuates for a predetermined time and is extracted when the game ball passes through the gate 18. The stop symbol determined by the selected lottery random value is displayed and stopped.

  The special winning opening 16 includes an opening / closing plate 16a that advances and retreats in the front-rear direction. The operation of the special winning opening 16 is not particularly limited, but in a typical big hit state, a predetermined time elapses after the opening / closing plate 16a of the special winning opening 16 is opened, or a predetermined number (for example, ten) of games. When the ball wins, the opening / closing plate 16a is closed. Such an operation is continued up to 15 times, for example, and is controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol display parts Da to Dc is a specific symbol among the special symbols, there is a privilege that the game after the end of the special game becomes a high probability state (probability variation state). Is granted.

  FIG. 3 is a block diagram showing an overall circuit configuration of the pachinko machine GM that realizes the above-described operations. As shown in the figure, this pachinko machine GM mainly receives a 24V AC and outputs various DC voltages, power supply abnormality signals ABN1, ABN2, a system reset signal (power reset signal) SYS, and the like, and a game control operation. Based on the main control board 21 that performs overall control, the effect control board 22 that executes the lamp effect and the sound effect based on the control command CMD received from the main control board 21, and the control command CMD ′ received from the effect control board 22 The image control board 23 for driving the display device DS, the payout control board 24 for controlling the payout motor M based on the control command CMD "received from the main control board 21, and paying out the game balls. It is mainly composed of a launch control board 25 that responds and launches a game ball.

  However, in this embodiment, the control command CMD output from the main control board 21 is transmitted to the effect control board 22 via the command relay board 26 and the effect interface board 27. The control command CMD ′ output from the effect control board 22 is transmitted to the image control board 23 via the effect interface board 27 and the image interface board 28, and is output from the main control board 21. Is transmitted to the payout control board 24 via the main board relay board 32. Although the control commands CMD, CMD ′, and CMD ″ are all 16 bits long, the main control board 21 and the payout control board 24 are used. The control commands related to are transmitted in parallel every two 8 bit lengths. On the other hand, the control command CMD 'transmitted from the effect control board 22 to the image control board 23 is 16 bits in length and transmitted in parallel. Therefore, even when the notification effects including the movable notification effect are diversified and a large number of control commands are continuously transmitted and received, the processing can be completed quickly, and other control operations are not hindered.

  By the way, in the present embodiment, the production interface board 27 and the production control board 22 are directly connected to each other by a male connector and a female connector without passing through a wiring cable, and two circuit boards are laminated. . Similarly, with respect to the image interface board 28 and the image control board 23, two circuit boards are laminated by directly connecting a male connector and a female connector without going through a wiring cable. Therefore, even if the circuit configuration of each electronic circuit is complicated and sophisticated, the storage space of the entire board can be minimized, and noise resistance can be improved by minimizing the connection lines.

  The main control board 21, the effect control board 22, the image control board 23, and the payout control board 24 are each equipped with a computer circuit including a one-chip microcomputer. Therefore, in this specification, the control board 21 to 24, the circuits mounted on the interface boards 27 to 28, and the operations realized by the circuits are generically named. May be referred to as a section 22 ′, an image control section 23 ′, and a payout control section 24. That is, in this embodiment, the effect control board 22 and the effect interface board 27 constitute an effect control part 22 ′, and the image control board 23 and the image interface board 28 constitute an image control part 23 ′. . Note that all or part of the effect control unit 22 ′, the image control unit 23 ′, and the payout control unit 24 are sub-control units.

  The pachinko machine GM is roughly divided into a frame side member GM1 surrounded by a broken line in FIG. 3 and a board side member GM2 fixed to the back of the game board 5. The frame side member GM1 includes a front frame 3 on which a glass door 6 and a front plate 7 are pivotally attached, and a wooden outer frame 1 on the outside thereof. Is fixedly installed. On the other hand, the board side member GM2 is replaced in response to the model change, and a new board side member GM2 is attached to the frame side member GM1 instead of the original board side member. All except the frame side member 1 is the panel side member GM2.

  As shown in the broken line frame in FIG. 3, the frame side member GM1 includes a power supply board 20, a payout control board 24, a launch control board 25, a frame relay board 35, and a lamp drive board 36. These circuit boards are respectively fixed at appropriate positions of the front frame 3.

  A plurality of LEDs are connected to the lamp drive board 36, and the drive data SDATA for driving these LED groups is a serial signal, the production control board 22 → the production interface board 27 → the frame relay board 34 → the frame relay. The signal is transmitted to a plurality of drivers DRij mounted on the lamp driving substrate 36 via the substrate 35.

  Each of the drivers DRij (driver ICs) of the embodiment can drive up to 24 LED groups such as LEDs and electric lamps, but in the following description, five drivers mounted on the lamp driving board 36 are used. It is assumed that a total of 5 × 24 LEDs are driven by DRij (see FIG. 8). In this specification, these LEDs are referred to as a 0th channel (CH0) LED group for convenience.

  On the back surface of the game board 5, a main control board 21, an effect control board 22, and an image control board 23 are fixed together with the display device DS and other circuit boards. And the frame side member GM1 and the board | substrate side member GM2 are electrically connected by the connection connectors C1-C4 concentratedly arranged in one place.

  The power supply board 20 is connected to the main board relay board 32 through the connection connector C2, and is connected to the power supply relay board 33 through the connection connector C3. The power supply board 20 is provided with a power supply monitoring unit MNT that monitors whether AC power is turned on or off. When power supply monitoring unit MNT detects that AC power is turned on, it maintains system reset signal SYS at L level for a predetermined time, and then transitions it to H level.

  Further, when power supply monitoring unit MNT detects the interruption of the AC power supply, power supply abnormality signals ABN1 and ABN2 are immediately shifted to the L level. The power supply abnormality signals ABN1 and ABN2 quickly become H level after the power is turned on.

  Incidentally, the system reset signal of this embodiment is generated by a DC power supply based on an AC power supply. For this reason, after detecting the turning-on of the AC power supply (usually turning on the power switch) and increasing it to the H level, the H level is maintained unless the DC power supply voltage drops to an abnormal level. Therefore, even if the AC power supply is in an instantaneous power interruption state while the DC power supply voltage is maintained, the system reset signal SYS does not reset the CPU. The power supply abnormality signals ABN1 and ABN2 are also output even when the AC power supply is instantaneously stopped.

  The main board relay board 32 outputs the power abnormality signal ABN1, the backup power supply BAK, and DC5V, DC12V, and DC32V output from the power board 20 to the main control unit 21 as they are. On the other hand, the power relay board 33 outputs the system reset signal SYS received from the power board 20 and the AC and DC power supply voltages to the effect interface board 27 as they are. The effect interface board 27 outputs the received system reset signal SYS to the effect control unit 22 'and the image control unit 23' as it is.

  On the other hand, the payout control board 24 is directly connected to the power supply board 20 without going through the relay board, and directly receives the same power abnormality signal ABN2 and backup power supply BAK as the main control unit 21 receives together with other power supply voltages. Is receiving.

  The system reset signal SYS output from the power supply board 20 is a power supply reset signal indicating that the AC power supply 24V has been applied to the power supply board 20, and one of the effect control unit 22 ′ and the image control unit 23 ′ is generated by the power supply reset signal. The chip microcomputer is reset together with other IC elements.

  However, the system reset signal SYS is not supplied to the main control unit 21 and the payout control unit 24, and a power reset signal (CPU reset signal) is generated in the reset circuit RST of each of the circuit boards 21 and 24. ing. Therefore, for example, even if the connection connector C2 is rattled or noise is superimposed on the wiring cable, there is no possibility that the CPU of the main control unit 21 or the payout control unit 24 is abnormally reset. The production control unit 22 ′ and the image control unit 23 ′ perform production operations dependently on the basis of the control command from the main control unit 21, so that the power supply board 20 is avoided in order to avoid complication of the circuit configuration. The system reset signal SYS output from is used.

  By the way, the reset circuits RST provided in the main control unit 21 and the payout control unit 24 each have a built-in watchdog timer, and unless a regular clear pulse is received from the CPUs of the control units 21 and 24, Each CPU is forcibly reset.

  In this embodiment, the RAM clear signal CLR is generated by the main control unit 21 and transmitted to the one-chip microcomputer of the main control unit 21 and the payout control unit 24. Here, the RAM clear signal CLR is a signal for deciding whether or not to initialize all the areas of the built-in RAM of the one-chip microcomputer of each control unit 21 and 24. It has a value corresponding to the / OFF state.

  The main control unit 21 and the payout control unit 24 receive the power supply abnormality signals ABN1 and ABN2 from the power supply board 20 to start necessary end processing prior to a power failure or business end. The backup power supply BAK is a DC5V DC power source that retains data in the RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 24 even after the AC power supply 24V is shut off due to business termination or power failure. Therefore, the main control unit 21 and the payout control unit 24 can resume the game operation before power-off after power-on (power backup function). This pachinko machine is designed to retain the stored contents of the RAM of each one-chip microcomputer for at least several days.

  As shown in FIG. 3, the main control unit 21 transmits a control command CMD ″ to the payout control unit 24 via the main board relay board 32, while the payout control unit 24 indicates a game ball payout operation. A prize ball counting signal, a status signal CON relating to an abnormality in the payout operation, and an operation start signal BGN are received, and the status signal CON includes, for example, a replenishment signal, a payout shortage error signal, and a lower plate full signal. The operation start signal BGN is a signal for notifying the main control unit 21 that the initial operation of the payout control unit 24 has been completed after the power is turned on.

  The main control unit 21 is connected to each game component of the game board 5 via the game board relay board 31. And while receiving the switch signal of the detection switch built in each winning opening 16-18 on a game board, solenoids, such as an electric tulip, are driven. The solenoids and the detection switch are configured to operate with the power supply voltage VB (12 V) distributed from the main control unit 21. Each switch signal indicating a winning state to the symbol start opening 15 is converted to a TTL level or CMOS level switch signal by an interface IC that operates with the power supply voltage VB (12 V) and the power supply voltage Vcc (5 V). And then transmitted to the main control unit 21.

  As described above, the effect control board 22 and the effect interface board 27 are integrated by connector connection, and the effect control unit 22 ′ is connected to each level from the power supply board 20 via the power relay board 33. A DC voltage (5V, 12V, 32V) and a system reset signal SYS are received (see FIGS. 3 and 4). The effect control unit 22 'receives the control command CMD and the strobe signal STB from the main control unit 21 via the command relay board 26 (see FIGS. 3 and 4).

  The effect control unit 22 ′ supplies lamp drive data SDATA (serial signal) to the driver DRij mounted on the lamp drive board 29 and the lamp drive board 30 via the effect interface board 27. Although not particularly limited, the driver DRij mounted on the lamp driving boards 29 and 30 has the same configuration as the driver DRij mounted on the lamp driving board 36, and each of the lamp driving boards 29 and 30 includes Five drivers DRij are arranged.

  As described above, each of these drivers DRij can drive a maximum of 24 lamps. In the following description, a total of 24 × 5 lamps connected to the lamp driving board 29 are connected to the first lamps. A total of 24 × 5 lamps connected to the lamp driving substrate 30 may be referred to as a lamp group of the second channel CH2, which is referred to as a lamp group of the channel CH1.

  As described above, in this embodiment, a large number (3 × 24 × 5) of lamps are divided into three groups of lamps of channel CH0 to channel CH2, respectively, and the lamp driving board 36, the lamp driving board 29, and the lamp driving, respectively. It is connected to the substrate 30. In addition, all the drivers DRij receive the corresponding signals among the serial signals SDATA that are collectively output by the one-chip microcomputer 40 of the effect control unit 22 ′ and drive the lamp group in charge (FIG. 4). reference).

  By the way, it is possible to drive the stepping motor using the same driver DRij. For example, it is also preferable to drive the effect motor groups M1 to Mn via the lamp driving board 30 as indicated by a broken line. In this case, the motor drive data is a serial signal similar to the lamp drive data, and even if the number of production motors is increased in order to enrich production contents, the number of wiring cables does not increase, and the device configuration is simplified. .

  As shown in FIGS. 3 and 4, the effect control unit 22 ′ has two types of control commands CMD ′ and strobe signal STB ′, and a system reset signal SYS received from the power supply board 20, with respect to the image control unit 23 ′. DC voltage (12V, 5V).

  Then, the image controller 23 'drives the display device DS based on the control command CMD' to execute various image effects. The display device DS emits light by an LED backlight, and is driven by receiving five pairs of LVDS (Low voltage differential signaling) signals and a backlight power supply voltage (12 V) from the image interface board 28. (See FIG. 4).

  Next, the configurations of the effect control unit 22 'and the image control unit 23' will be described in more detail. As shown in FIG. 4, the production interface board 27 receives three types of DC voltages (5V, 12V, and 32V) from the power supply board 20 via the power supply relay board 33. Here, the DC voltage 5V is distributed as power supply voltage of the digital logic circuit to the rendering interface board 27, the lamp driving board 29, the lamp driving board 30, the image interface board 28, and the image control board 23, and is supplied to each digital circuit. Is operating.

  However, the direct current voltage 5V is not distributed on the effect control board 22, and the direct current voltage 3.3V stepped down from 12V by the DC / DC converter and the direct current stepped down from 3.3V by the DC / DC converter. Only the voltage 1.8V is distributed from the production interface board 27 to the production control board 22.

  In this way, the production control board 22 of the present embodiment is driven by the power supply voltage of 3.3V or lower because all the circuits are driven. Therefore, even if the production interface board 27 is arranged and laminated immediately above the production control board 22, there is no problem in heat dissipation.

  However, the DC voltage 12V received from the power supply board 20 is used as it is as the power supply voltage of the digital amplifier 46 and is distributed to the lamp drive board 30 and the lamp drive board 29 to become the power supply voltage of each lamp group. The direct current voltage 32V is stepped down to the direct current voltage 13V in the DC / DC converter of the production interface board and used as a drive power source for the production motors M1 to Mn as necessary.

  As shown in FIG. 4, the effect control unit 22 ′ includes a one-chip microcomputer 40 that executes processing such as a sound effect, a lamp effect, a notice effect by the effect movable body, and data transfer, and a control program for the one-chip microcomputer 40. A non-volatile memory 41 for storing, a voice synthesizing circuit 42 for reproducing and outputting a voice signal based on an instruction from the one-chip microcomputer 40, and a voice for storing compressed voice data as original data of the reproduced voice signal The memory 43 and a clock oscillator 39 that generates a system clock SCK that defines the operation timing of the one-chip microcomputer 40 are provided.

  The one-chip microcomputer 40, the flash memory 41, and the voice memory 43 operate at a power supply voltage of 3.3V, and the voice synthesis circuit 42 operates at a power supply voltage of 3.3V and a power supply voltage of 1.8V. Therefore, significant power saving is realized. 1.8V is the power supply voltage of the computer core part of the speech synthesis circuit, and 3.3V is the power supply voltage of the I / O part.

  Incidentally, the clock oscillating unit 39 of this embodiment does not oscillate fixedly the center frequency Fi defined by the natural frequency of the crystal resonator Xtal, but has a frequency (Fi within a predetermined range with the center frequency Fi as the center. A system clock SCK (modulation clock) in which (−δ to Fi + δ) shifts is generated. The frequency shift amount δ is about ± 1.0% above and below the center frequency Fi (center spread), or about 0 to 2.0% above or below the center frequency Fi. Preferred (up spread or down spread).

  FIG. 5A illustrates the circuit configuration, and includes an original oscillation circuit OSC using a crystal resonator Xtal and a frequency modulation circuit FS that shifts the oscillation frequency Fi of the original oscillation circuit OSC. It is configured. The original oscillation circuit OSC includes a crystal resonator Xtal, an inverter IN, a feedback resistor Rs, and load capacitors C11 and C12, and generates a reference clock having a center frequency Fi. Here, the positive feedback loop connecting the inverter IN and the feedback resistor Rs is configured to be open / close controlled by the control signal CTL, and is configured to be able to control whether the oscillation operation is permitted by the control signal CTL.

  FIG. 5A shows a configuration in which a crystal resonator Xtal is connected between the signal terminals Xin and Xout to cause self-excited oscillation. However, as shown in FIG. In the released state, the external clock received from another circuit can be frequency-modulated. In this case, the reference clock has a logic level obtained by logically negating the external clock.

  The frequency modulation circuit FS includes a PLL block 37 that executes a PLL (phase locked loop) operation, and control terminals T1 and T2 that control the PLL operation. When an H level control signal is received at the control terminal T1, the operations of the original oscillation circuit OSC and the PLL block 37 are permitted. Further, the degree of modulation can be set high or low according to the logic level of the setting signal received at the control terminal T2. The degree of modulation means the amount of frequency deviation from the center frequency Fi, and is either ± 0.5% or ± 1.0%, for example, depending on the logic level of the setting signal received by the control terminal T2. This is the frequency shift amount. In the illustrated example, the setting signal is at the H level (modulation level is high), and the frequency shift amount is ± 1.0%.

  However, it is not always necessary to perform frequency modulation above and below the center frequency Fi by the center spread method, for example, −1.0% below the center frequency Fi, depending on the logic level of the setting signal received by the control terminal T2. A down spread method in which any frequency shift amount of −2.0% may be adopted.

  In any case, since the frequency of the system clock SCK output from the PLL block 37 is shifted by about δ = Fi × 2/100, it effectively contributes to suppression of unnecessary radiation noise EMI. This point will be further described later with respect to the lamp driving signal and the motor driving signal.

  FIG. 5B illustrates the internal configuration of the PLL block 37, and is substantially the same as a normal PLL circuit except for the modulation logic unit 59. That is, the PLL block 37 includes, in addition to the modulation logic unit 59, a first frequency division unit 50 that divides the output signal (modulation clock output) by 1 / M, and a second frequency division that divides the reference clock by 1 / N. Unit 51, a third frequency divider 52 that divides the reference clock by 1 / L, a phase comparator 53 that compares the outputs of first frequency divider 50 and second frequency divider 51, and phase comparator 53 A charge pump 54 that receives the output, a loop filter 55 that includes a resistor and a capacitor, and a voltage-controlled oscillator VCO that changes the output frequency Fo in accordance with the output voltage of the loop filter 55 are configured.

  However, unlike a normal PLL circuit, the PLL block 37 realizes frequency modulation in which the frequency of the voltage-controlled oscillation unit VCO fluctuates up to about 2% based on the modulation signal MD received from the modulation logic unit 59. It is configured to be. In the embodiment, the modulation cycle is switched over time, the output frequency of the VCO is changed in the range of Fo−δ to Fo + δ in the modulation cycle τ1, and then the output frequency of the VCO is changed from Fo−δ to the modulation cycle τ2. It is changed in the range of Fo + δ. As a result, the output frequency is further irregularly frequency-modulated, thereby increasing the effect of suppressing unnecessary radiation noise EMI.

  In any case, in the PLL block 37, the phase difference between the output signal of the first frequency divider 50 having the frequency Fo / M and the output signal of the second frequency divider 51 having the frequency Fi / N is a phase comparator. Since the negative feedback loop functions so that the phase difference is detected at 53 and the phase difference becomes zero, the relationship Fo / M = Fi / N is established, and the frequency Fo of the output signal (modulation clock output) slightly fluctuates. = Fi × M / N. In this embodiment, this output signal is supplied to the one-chip microcomputer 40 as the system clock SCK, and defines the operation timing of the internal operation of the one-chip microcomputer 40.

  The one-chip microcomputer 40 that operates based on such a system clock SCK includes a plurality of parallel input / output ports PIO (Pi + Po + Po ′) and a plurality of serial output ports SI. Here, more specifically, the serial output port SI includes three-channel serial ports (S0 to S2) (see FIG. 6), and is mounted on the lamp driving boards 36, 29, and 30. Lamp drive data SDATA0 to SDATA2 are output to the five drivers DRij in synchronization with the clock signals CK0 to CK2, respectively.

  That is, the serial port S0 to serial port S2 transmit the lamp drive data SDATA0 to SDATA2 to the corresponding lamp drive boards 36, 29, and 30 based on the clock synchronization method. Note that the lamp driving data SDATA0 to SDATA2 are luminance data for adjusting the luminance of light emitted from each LED by PWM control (pulse width modulation).

  The lamp driving boards 36, 29, 30 are also connected to the parallel output port Po ′ of the parallel input / output port PIO. The driver DRij mounted on each of the lamp driving boards 36, 29, 30 is a parallel output port. The operation is started based on any of the 3-bit operation enable signals ENABLE0 to ENABLE2 output by Po ′.

  On the other hand, the control command CMD and the strobe signal STB from the main control unit 21 are input to the input port Pi of the parallel input / output port PIO, and the control command CMD ′ and the strobe signal STB ′ are output from the command output port Po. It is comprised so that.

  Specifically, a control command CMD and a strobe signal (interrupt signal) STB output from the main control board 21 correspond to the power supply voltage 3.3 V in the buffer 44 of the effect interface board 27 at the input port Pi. Converted to a logic level to be supplied in units of 8 bits. The interrupt signal STB is supplied to the interrupt terminal of the one-chip microcomputer, and the effect control unit 22 'is configured to acquire the control command CMD by the reception interrupt process.

  The control command CMD acquired by the effect control unit 22 ′ includes (1) an abnormality notification and other notification control commands, and (2) control for specifying an outline of various effect operations resulting from winning at the symbol start opening. A command (variation pattern command) and a control command (symbol designation command) for designating a symbol type are included. Here, the outline of the production operation specified by the variation pattern command includes the production total time from the production start to the production end and the result of winning or failing in the jackpot lottery.

  In addition, the symbol designating command includes information for identifying information on the jackpot type (15R probability variation, 2R probability variation, 15R normal, 2R normal, etc.) in the case of a jackpot according to the result of the jackpot lottery. In some cases, information for identifying a loss is included. The outline of the production operation specified by the variation pattern command includes the production total time from the production start to the production end, and the result of success or failure in the big hit lottery. In addition to these, the change pattern command including the presence or absence of the reach effect or the notice effect may be specified, but even in this case, the specific content of the effect content is not specified.

  Therefore, when the change pattern command is acquired, the effect control unit 22 ′ performs an effect lottery subsequently to further specify the effect outline specified by the acquired change pattern command. For example, the specific contents of the reach effect and the notice effect are determined. Then, in accordance with the determined specific game content, a lamp effect by blinking LEDs and a sound effect preparation operation by a speaker are performed, and an effect operation by a lamp or speaker is performed on the image control unit 23 ′. A control command CMD ′ relating to the synchronized image effect is output.

  In order to realize such an image effect synchronized with the effect operation, the effect control unit 22 ′, along with the strobe signal (interrupt signal) STB ′ for the image control unit 23 ′, is sent to the image control unit 23 ′ through the command output port Po. CMD ′ is output toward the production interface board 27. When the production control unit 22 ′ receives a design designation command, a notification control command related to the display device DS, and other control commands, the control command is summarized in a 16-bit length. It is output toward the production interface board 27 together with the interrupt signal STB ′.

  Corresponding to the configuration of the production control board 22 described above, the production interface board 27 is provided with an output buffer 45, and a 16-bit control command CMD ′ and a 1-bit interrupt signal STB ′ are sent to the image interface. It is output to the substrate 28. These data CMD ′ and STB ′ are transmitted to the image control board 23 via the image interface board 28.

  The effect interface board 27 is provided with a digital amplifier 46 that receives the audio signal output from the audio synthesis circuit 42. As described above, the speech synthesis circuit 42 operates with power supply voltages of 3.3 V and 1.8 V, and the digital amplifier 46 performs class D amplification operation with a power supply voltage of 12 V, reducing power consumption. It is possible to produce a loud sound while suppressing it.

  The left and right speakers at the upper part of the gaming machine and the speakers at the lower part of the gaming machine are driven by the output of the digital amplifier 46. Therefore, the voice synthesis circuit 42 needs to generate a three-channel voice signal, and if this is transmitted in parallel, the wiring between the voice synthesis circuit 42 and the digital amplifier 46 becomes complicated.

  Therefore, in this embodiment, the voice synthesis circuit 42 and the digital amplifier 46 are connected by four signal lines in order to prevent deterioration of sound quality and avoid complicated wiring. In this case, the transfer clock signal SCLK, the channel control signal LRCLK, and the 2-bit serial signals SD1 and SD2 are suppressed to a total of 4 bit signal lines. Note that the amplitude level of any signal is 3.3V.

  Here, SD1 is a serial signal for PCM data specifying the stereo signals R and L of the left and right speakers arranged at the upper part of the gaming machine, and SD2 is a monaural signal of the heavy bass speaker arranged at the lower part of the gaming machine. This is a serial signal for the PCM data to be specified. The voice synthesis circuit 342 transmits the left channel audio signal L while maintaining the channel control signal LRCLK at the L level, and maintains the channel control signal LRCLK at H level while maintaining the channel control signal LRCLK at the L level. Is transmitted. Note that since there is only one heavy bass speaker in this embodiment, a monaural audio signal is transmitted, but it is of course possible to transmit it as a stereo audio signal.

  In any case, in this embodiment, four types of audio signals can be transmitted with four cables, and therefore, signal transmission without audio deterioration due to noise can be performed with the minimum number of cables. That is, since it is serial transmission, the number of cables is far smaller than that of parallel transmission. Note that when analog transmission is employed, the number of cables is the same, but noise is superimposed on an analog signal having an amplitude of 3.3 V, and the sound quality is greatly deteriorated. On the other hand, when the amplitude level is increased, the power supply wiring becomes complicated and the power consumption increases.

  Such serial signals SD1 and SD2 are acquired by the digital amplifier 46 in synchronization with the rising edge of the clock signal SCLK. In the digital amplifier 46, parallel conversion is performed for each predetermined bit length, and after D / A conversion, D-class amplification is performed and supplied to each speaker.

  In this embodiment, since the voice synthesis circuit 42 and the digital amplifier 46 are connected by a serial line, even if the bit length of the PCM data (voice data) is increased to achieve higher sound quality, the wiring cable and the like are changed. There is no need, and simplification of the circuit configuration can be maintained.

  The effect interface board 27 is provided with parallel output port Po 'of the one-chip microcomputer 40, serial buffer SI, and output buffer circuits 47, 48, and 49 for transmitting various signals to be output. Here, the output buffer 47 is related to the LED group of the 0th channel, and outputs the lamp driving data SDATA0, the clock signal CK0, and the operation permission signal ENABLE0 output from the one-chip microcomputer 40 to the frame relay board 34. doing. The output 3-bit signal is transmitted to the driver DRij of the lamp driving board 36 via the frame relay board 34 and the frame relay board 35.

  Similarly, the output buffer 48 transmits the lamp drive data SDATA1, the clock signal CK1, and the operation permission signal ENABLE1 output from the one-chip microcomputer 40 to the driver DRij of the lamp drive board 29, and the output buffer 49 The drive data SDATA2, the clock signal CK2, and the operation permission signal ENABLE2 are transmitted to the driver DRij of the lamp drive board 30. The driver DRij of the lamp driving board 29 drives the LED group of the first channel, and the driver DRij of the lamp driving board 30 drives the LED group of the second channel.

  FIG. 6A illustrates the internal configuration of the serial port SI built in the one-chip microcomputer 40. As shown in the figure, the serial ports S0 to S2 all have the same configuration, and are configured so that a clock synchronous serial transmission / reception operation can be realized.

  Each serial port SI includes a transmission data register DR that receives 1-byte data from the CPU core, a transmission shift register SR that receives 1-byte data from the transmission data register DR, and serially outputs the data as lamp drive data SDATAi. And a number of control registers RG for managing the internal operation state of the serial port, and a baud rate generator BG for receiving the output pulse Φ of the counter circuit CT and outputting a clock signal CKi having a frequency division ratio designated by the control register RG. Configured.

  The control register RG includes a READable control register including the empty bit EMP, and indicates whether or not the transmission data register DR can accept new data. That is, when transmission of 1-byte data in transmission shift register SR is completed, empty bit EMP changes to H level (empty level), indicating that new data can be written into transmission data register DR. Therefore, the CPU core writes new data to the transmission data register DR after confirming that the empty bit EMP is at the H level.

  The control register RG includes a WRITE control register including a transmission permission bit TXE. When the CPU sets the transmission permission bit TXE to the ON (H) level, the serial port transmission operation is permitted. When set to the OFF level, the transmission operation is prohibited. Therefore, in this embodiment, the CPU sets the transmission permission bit TXE to the ON state at the start of the transmission process, and resets the transmission permission bit TXE to the OFF level at the end of the transmission process.

  FIG. 6B is a time chart showing the operation at the start of transmission for the serial ports S0 to S2. As shown in the figure, when the serial ports S0 to S2 are in the transmission prohibited state (TXE = L), or after the data of the transmission data register DR is serially output, the clock signal CK is at the fixed H level. The transmission data register DR is empty, and the empty bit EMP is also at the H level (empty level).

  Then, after the CPU sets the transmission permission bit TXE to the ON state (transmission permission state) and then writes the first byte of transmission data to the transmission data register DR, the empty bit EMP transitions to the L level, and then After a predetermined time (τ) elapses, the first byte of transmission data is transferred to the transmission shift register SR, and the serial transmission operation is started.

  Further, since the transmission data is transferred to the transmission shift register SR, the empty bit EMP transitions to the H level (empty level) thereafter in response to the start of serial transmission of the first bit. Therefore, after confirming the H level empty bit EMP, the CPU writes the second byte of transmission data into the transmission data register DR.

  Then, in response to the data write operation to the transmission data register DR, the empty bit EMP transitions to the L level (full level). After that, when all the transmission data of the first byte is transmitted, the second byte of data is transferred from the transmission data register DR to the transmission shift register SR, and the data transmission of the second byte is started, and the empty bit EMP Transitions to the H level.

  The empty bit EMP changes to the L level in response to the data write operation of the third byte to the transmission data register DR. However, as shown in the figure, the empty bit EMP maintains the H level when no new data is written. . Further, after all the data is transmitted, the clock signal CK maintains the H level and does not change.

  FIG. 7 shows the circuit configuration of the lamp driving substrates 36, 29, and 30 in a confirmed manner. As shown in the figure, on the lamp driving board 36, five drivers DR00, DR01... DR04 are mounted to drive the LED group of the 0th channel (5 × 24 LEDs in total). Similarly, five drivers DR10, DR11... DR14 are mounted on the lamp driving board 29, and five drivers DR18, DR19... DR1C are mounted on the lamp driving board 30. Each of the LED groups of the first channel and the second channel (a total of 5 × 24 LEDs) is driven to light.

  Each driver DRij is provided with a 5-bit numbering terminal. By adopting a circuit configuration in which fixed digital data is supplied to this numbering terminal, each slave address (port address) is assigned in series. It is numbered. In other words, in the illustrated example, the slave addresses of the drivers (DR00, DR01... DR04, DR10, DR11... DR14, DR18, DR19... DR1C) are expressed in hexadecimal notation as 00H, 01H. ... 04H, 10H, 11H... 14H, 18H, 19H.

  By assigning a series of slave addresses to the drivers DRij of the lamp control boards 36, 29, and 30, it is possible to speed up the setting process of luminance data and the like for each driver DRij. Each driver DRij has built-in gradation registers GR0 to GR23 that can define analog levels of lighting drive signals for driving 24 LEDs.

  Each of the gradation registers GRn can store 8-bit long luminance data, and the luminance level of the LED can be set in 256 steps from 00H to FFH.

  Next, the image control unit will be described. FIG. 8 is a circuit block diagram illustrating in detail the image control unit 23 ′ (image interface board 28 and image control board 23) including the surrounding boards. As described above, the image control unit 23 'operates by receiving the control command CMD', the strobe signal STB ', and the system reset signal SYS from the effect control unit 22'. In addition, two types of DC voltages 5V and 12V are received via the production control unit.

  As shown in the figure, the image control unit 23 ′ receives a control command via the effect interface board 27 and executes an image control operation, and a flash that stores a control program of the one-chip microcomputer 60 and the like. A memory 61, a VDP (Video Display Processor) 62 that drives the display device DS based on an instruction from the one-chip microcomputer 60, a graphic ROM (CGROM) 63 that stores compressed image data for image effects, and a work area of the VDP 62 ( An SDRAM (Synchronous Dynamic Random Access Memory) 64 functioning as a Video RAM) and a watchdog timer WDT for forcibly resetting the one-chip microcomputer 60 are included.

  As shown in FIG. 8, the VDP 62 of the embodiment separately receives the scan clock of the display device DS, the display system clock Φb that defines the image data transmission operation, and the system clock Φa that defines the operation timing of other processing. ing. Here, the system clock Φa is a fixed value defined by the natural frequency of the crystal unit Xa.

  On the other hand, the display system clock Φb is an output signal of the frequency modulation circuit FS having the same configuration as that shown in FIG. 5A, and the natural frequency Fi of the crystal unit Xb is shifted within a predetermined range (modulation degree). Has a frequency. As described above, the modulation degree means a frequency shift amount from the center frequency Fi, but the modulation degree of the display system clock Φb is set to 2.0% or less of the center frequency Fi.

  In addition, the center frequency Fi of the display system clock Φb (modulation clock) is an integral multiple (about 1, 2 or 4 times) of the dot clock frequency, and increases in accordance with the resolution of the display device DS. The dot clock frequency is the reciprocal of the operation time required to display one pixel (dot) of the display device DS. For example, when the vertical synchronization signal is 60 Hz and the resolution is 1280 × 1024, the dot clock frequency is The clock frequency is about 100 MHz.

  Since one pixel is composed of the three primary colors of RGB, it is necessary to transmit a large amount of image data at high speed, and there is a concern about the generation of unnecessary radiation noise EMI. However, in this embodiment, since the frequency of the display system clock Φb (modulation clock) fluctuates moderately, unnecessary radiation noise can be effectively suppressed.

  Further, it is not necessary to take noise countermeasures for each of the five pairs of LVDS signal lines, which is effective in terms of cost and space. That is, if a ferrite core is arranged for each wiring, at least five parts are required. Further, when a coil or a capacitor is arranged as a noise countermeasure, there are similarly disadvantages in terms of cost and space, and the effect of the configuration of the present embodiment in which these countermeasures are unnecessary is remarkable.

  The other configuration shown in FIG. 8 will also be described. The output of the watchdog timer WDT is supplied to the OR circuit together with the system reset signal SYS, and when one of the input signals to the OR circuit becomes an active level, one chip The microcomputer 60 and the VDP 62 are reset synchronously. Therefore, when the control operation is initialized due to the program runaway of the one-chip microcomputer 60, the operation of the VDP 62 is initialized correspondingly, and the contradictory and unnatural image effect is executed. It will not be done.

  In this embodiment, the power supply voltage of each element is minimized in order to suppress the power consumption as much as possible. The power supply voltage of each element is (1) the one-chip microcomputer 60 is 3.3V and 1.25V. (2) Flash memory 61 is 1.25V, (3) VDP62 is 3.3V, 1.8V and 1.1V, (4) CGROM 63 is 3.3V, and (5) SDRAM 64 is 1.8V. .

  A plurality of DC / DC converters having control terminals and a power sequencer 65 are provided to supply a large number of DC voltages to each element at an optimal timing. FIG. 9 shows an internal configuration (a) of LM3881 (national semiconductor) as an example of the power sequencer 65 and an operation time chart (b) executed even when the power sequencer 65 is used.

  In the case of the power sequencer 65 in FIG. 9A, when the INV terminal is at the L level, the operation starts in response to the operation start command EN at the H level, and the clock defined by the capacitance connected to the TADJ terminal. The first control signal PCNT1 rises after nine cycles of the signal Clock, the second control signal PCNT2 rises after eight cycles of the clock signal, and the third control signal PCNT3 rises after another eight cycles of the clock signal.

  On the other hand, when the operation start command EN transitions to the L level, the third control signal PCNT3 falls after 9 cycles of the clock signal, the second control signal PCNT2 falls after 8 cycles of the clock signal, and further 8 cycles after the clock signal. The third control signal PCNT3 falls.

  In the present embodiment, as shown in FIG. 8, the operation start command EN is an AND logic output of two types of DC voltages supplied from the effect control unit 22 '(effect interface board 27). The first control signal PCNT1 is supplied to the operation enable terminal EN of the DC / DC converter V1 for generating 1.1V, and the second control signal PCNT2 is an operation enable for the DC / DC converter V2 for generating 3.3V. It is supplied to the terminal EN.

  The third control signal PCNT3 is converted into an AND logic output with 3.3V and supplied to the operation enable terminal EN of the DC / DC converter V3 for generating 1.8V. Each DC / DC converter described above starts the voltage conversion operation on condition that the operation enable terminal EN becomes H level.

  Therefore, as shown in FIG. 9B, the DC / DC converter V1 first functions based on 5V distributed from the effect control unit 22 'to generate the DC voltage 1.1V. This DC voltage 1.1V is a power supply voltage for the digital circuit and the built-in VRAM built in the VDP 62, and the normal operation start sequence of the VDP 62 after the power is turned on by starting the operation before other built-in circuits. Is secured.

  After the above operation, since the second control signal PCNT2 becomes H level, the DC / DC converter V2 that receives 12V distributed from the effect control unit 22 'functions to generate the DC voltage 3.3V. The DC voltage 3.3V is supplied to the DC / DC converter V4 for 1.25V. Since this converter V4 does not have an operation enable terminal, the DC voltage 1.V is started immediately. 25V is generated.

  The two types of DC voltages 3.3V and 1.25V generated by being controlled by the second control signal PCNT2 are supplied to the one-chip microcomputer 60, the flash memory 61, and the CGROM 63 at almost the same timing. Each of the circuit elements is ready for operation start without delay after power-on. At this timing, the system reset signal SYS is at the L level, and after this level has been maintained for a while, the power supply circuit of the power supply board is operating so as to change to the H level. The power will be reset.

  Finally, when the third control signal PCNT3 changes to H level, the AND logic output of the third control signal PCNT3 and 3.3V is supplied to the DC / DC converter V3 to generate a DC voltage of 1.8V. The DC voltage 1.8V is supplied to the VDP 62, the DDR SRAM 64, and the power circuit 68 for the DDR SRAM at almost the same timing, so that the DDR SRAM 64 and the DDR SRAM interface circuit in the VDP 62 can be operated in synchronization. Become. Therefore, when the system reset signal SYS changes to the H level, the VDP 62 can smoothly start the initial setting operation.

  FIG. 10 is a block diagram showing the internal configuration of the VDP 62 and the connection relationship between the SDRA 64, the CGROM 63, and the one-chip microcomputer. Based on an instruction from the one-chip microcomputer 60, the VDP 62 separately generates and outputs a series of image data groups for change effects and image data groups for notice effects executed by the display device DS. These image data groups are finally generated by the display controller 78a and output to the LVDS_I / F unit 75.

  Here, each of the image data group for change effect and the image data group for notice effect is configured by combining moving image data that continuously changes and still image data that does not move continuously. Further, the RGB pixels constituting these image data groups are each 8 bits long (256 gradations), and realize high-quality image effects on the display device DS.

  As shown in the figure, the one-chip microcomputer 60 and the VDP 62 are connected via a CPU_I / F unit, and the command memory 70 stores in advance a large number of command lists that specify a series of image effects. The command list is classified into a variable effect and a notice effect, and various types of lists are prepared to increase the variety of effects.

  The one-chip microcomputer 60 accesses the system control register 71 when necessary, and sets a start address of a predetermined command list that specifies a series of image effects to be executed. Then, the command parser (syntax analyzer) 72 analyzes the command list specified by the system control register 71 and passes the internal code corresponding to the analysis result to the internal modules such as the moving picture decoder 73 and the still picture decoder 74. .

  Then, each internal module starts an operation to secure necessary image data in a VRAM (Video RAM) area, and at the same time, frame image data is transferred to an LVDS_IF unit (LVDS transmission unit) 75 or a DRGB_IF unit. Output to 76. The LVDS_IF unit 75 is a part that converts the frame image data into an LVDS signal and outputs it. The DRGB_IF unit 76 is a part that outputs the digital RGB signal together with a control signal such as a horizontal / vertical synchronization signal.

  In the above configuration, the operation of the command parser 72 is executed based on the system clock Φa. On the other hand, operations relating to generation and output of image display data to be supplied to the display device DS, such as the moving picture decoder 73, the still picture decoder 74, the display controllers 78a and 78b, the LVDS_IF unit 75, and the DRGB_IF unit 76 It is executed based on the clock (modulation clock) Φb.

  In this embodiment, the DRGB_IF unit 76 is not used, but the DRGB_IF unit 76 may be used instead of the LVDS_IF unit 75, and a single-ended signal is used instead of the differential signal. However, according to the present embodiment, the generation of unnecessary radiation noise is greatly reduced.

  By the way, in this embodiment, in order to facilitate a series of drawing operations by the VDP 62 at high speed, the CGROM 63 includes moving image compression data for specifying a series of moving images that change at high speed, still compression data for specifying a still image, Is memorized separately. The still compressed data read from the CGROM 63 via the ROM_I / F unit or the CG memory controller is expanded by the still image decoder 74 and temporarily stored in the built-in VRAM 77. On the other hand, the moving image compressed data read from the CGROM 63 is configured to be decompressed by the moving image decoder 73 and temporarily stored in the SDRAM 64.

  That is, in this embodiment, since the external SDRAM 64 is used as the VRAM, there is no limit on the memory capacity as in the case of using the built-in RAM. It is also possible to continuously decode the moving image compressed data and secure it in advance of the SDRAM, so that image processing can be realized at high speed. In addition, the RAM 63 of the present embodiment is particularly composed of a DDRS2 DRAM (Double-Data-Rate2 SDRAM), which realizes data transfer at a higher speed than that of the SDRAM, and generates two uncommon image data at a high speed. be able to.

  The image data secured in the VRAM areas 64 and 77 in this way is read out to the display controller 78a and output from the LVDS / IF unit 75 after gamma correction or the like.

  FIG. 11 shows the relevant part (LVDS transmitter 75) of FIG. 8 and FIG. 10 in more detail with respect to the connection relationship between the VDP 62 having the above-described internal configuration and the display device DS. As shown in the figure, the display device DS of the present embodiment is configured to incorporate an LVDS reception unit (LVDS_I / F) 81 corresponding to the LVDS transmission unit (LVDS_I / F) 75 of the VDP 62.

  As shown in FIG. 11A, the LVDS_I / F unit (LVDS transmission unit) 75 is a part that converts parallel data including 24 bits of RGB data into an LVDS (low voltage differential signaling) signal. LVDS means a low-voltage differential transmission system for high-speed transmission of RGB data and the like with low noise and low power. In this embodiment, several mA is applied to a pair of signal transmission lines (one twisted pair line). While a low level signal current is supplied from the transmission side, this signal current is received by a terminating resistor of about 100Ω provided on the reception side. Therefore, although the voltage amplitude is a low level of about several hundred mV, reliable signal transmission is realized by changing the current direction corresponding to the logic level (H / L).

  In this embodiment, as shown in FIG. 11A, a total of 28-bit parallel data (TA0 to TA0) including all 24-bit RGB signals (each 8 bits long) and horizontal / vertical synchronization signals. TA6, TB0 to TB6, TC0 to TC6, TD0 to TD6) are converted into four pairs of differential signals in the LVDS transmission unit 75. Then, a differential signal of a pair of transfer clocks is added to this and transmitted to the display device DS through five twisted pair lines.

  In FIG. 8 and FIG. 11A, these four pairs of differential signals are evaluated from the standpoint of the display device DS, and (RXIN0 +, RXIN0−), (RXIN1 +, RXIN1−), (RXIN2 +, RXIN2−). ), (RXIN3 +, RXIN3 +), (RXCLK +, RXCLK−).

  As shown in FIG. 11 (b), during a period of the transfer clock RXCLK, the twisted pair lines (RXIN0 +, RXIN0−) serially transfer G0 → R5 → R4 → R3 → R2 → R1 → R0 to obtain the twisted pair line. In (RXIN1 +, RXIN1-), B1 → B0 → G5 → G4 → G3 → G2 → G1 are serially transferred, and in twisted pair lines (RXIN2 +, RXIN2-), DE → (VS) → (HS) → B5 → B4 → B3 → B2 is serially transferred, and NA → B7 → B6 → G7 → G6 → R7 → R6 is serially transferred on the twisted pair line (RXIN3 +, RXIN3-).

  Here, R0 to R7 are 8-bit length data indicating the luminance of the red pixel, G0 to G7 are 8-bit length data indicating the luminance of the green pixel, and B0 to B7 are 8-bit length data indicating the luminance of the blue pixel. It is. In addition, (VS) and (HS) indicate vertical synchronization timing and horizontal synchronization timing, and DE means DATA ENABLE. Note that NA is unused.

  The display device DS that receives the four pairs of differential signals is provided with an LVDS receiver 81 corresponding to the LVDS transmitter 75 of the VDP 62. A series of serial data is converted into parallel data, and four sets of parallel data RA0 to RA6, RB0 to RB6, RC0 to RC6, and RD0 to RD6 are obtained. As is apparent from the serial data string shown in FIG. 11B, the parallel data RA0 to RA6 are specifically 7 bits of R0 to R5 and G0, and other parallel data are also shown in FIG. 11B. This corresponds to the serial data shown.

  And a display apparatus implement | achieves a screen display based on RGB gradation data extracted from these. In this way, in this embodiment, the pixel data is 8 bits for each RGB (256 gradations), and a full color image effect can be realized.

  Moreover, since the LVDS signal is used for signal transmission between the VDP 62 and the display device DS, the voltage amplitude is low enough (several hundred mV), and the rise time and fall time of the digital signal are correspondingly short, so high-speed communication is possible. It can be realized, and an image effect transitioning to a high speed can be realized smoothly. Moreover, since it is not affected by common mode noise, an unnatural pixel does not occur.

  Since the frequency modulation degree of the display clock Φb is 2.0% or less, the frequency fluctuation does not adversely affect the display screen.

  As mentioned above, although the Example of this invention was described in detail, the concrete description content does not specifically limit this invention. In particular, the embodiment has been described with respect to a ball game machine, but it is needless to say that the application of the present invention is also suitably applied to a spinning game machine and other game machines.

GM gaming machine 23 'image control unit 40 first processor 62 second processor Φb modulation clock

To achieve the above object, the present invention provides a first processor that generally controls image effects based on control commands received from other control means, and image display data generated based on instructions received from the first processor. Is a game machine provided with an image control means having a second processor for advancing image effects by supplying the display device with an internal operation timing for analyzing an instruction received from the first processor. In addition to the system clock that regulates the image display data, the display system clock that regulates the operation timing of the image display data sending operation is supplied, and the image display data that is sent based on the display system clock that can shift the prescribed center frequency is The differential signal is output from the second processor to the display device .

Claims (8)

A first processor that comprehensively controls image effects based on control commands received from other control means, and image display data generated based on instructions received from the first processor is supplied to the display device to advance image effects. A gaming machine provided with an image control means having a second processor,
At least a part of the operation of the second processor is configured to be executed based on a modulation clock obtained by shifting a specified center frequency within a predetermined range.   2. The gaming machine according to claim 1, wherein the operation executed based on the modulation clock includes an operation for generating image display data and an operation for outputting image display data.   The gaming machine according to claim 1 or 2, wherein the center frequency of the modulation clock is set corresponding to an operation time for displaying one pixel of the display device.   The gaming machine according to claim 1, wherein the second processor is supplied with a system clock different from the modulation clock.   The gaming machine according to claim 4, wherein the frequency of the system clock is fixed without frequency modulation.   The gaming machine according to claim 1, wherein the amount of frequency shift with respect to the center frequency of the modulation clock is limited within a predetermined range with respect to the center frequency.   The game machine according to claim 1, wherein the image display data is output from the second processor as a differential signal. The gaming machine according to claim 1, wherein the image display data is output from the second processor as a single-ended signal.

Images