JP2003325871A - Display control device for game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display control device for a game machine which deals with a plurality of kinds of display modules without changing components. <P>SOLUTION: The display control device 1 for the game machine is provided with a VDP 13 for inputting a video signal and a synchronizing signal to an LCD 3, a clock frequency control part 9 for changing a frequency of a clock to be outputted to the VDP 13 in accordance with inputted frequency setting data, and a crystal oscillator 15 for supplying a reference clock to the clock frequency control part 9. The clock frequency control part 9 is composed of a frequency divider circuit 92 and a multiplier circuit 91 and frequency dividing ratio data and multiplication rate setting data from a CPU 7 are inputted to the respective circuits. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device for gaming machines such as pachinko machines and slot machines.

[0002]

2. Description of the Related Art In recent game machines, LCD (liquid cry
stal display: Liquid crystal display) is adopted in many cases. The LCD is generally configured as a display module including a liquid crystal element and a drive circuit that drives the element. In game machines, such liquid crystal display modules are mainly used in two types: a normal screen with an aspect ratio of 3: 4 and a wide screen with an aspect ratio of 9:16. An image is displayed by inputting a synchronizing signal and a video signal generated by the image processing LSI to such a display module. A clock pulse generated by a crystal oscillator is input to the image processing LSI as a dot clock or a reference clock serving as a basis thereof.

The image processing LSI (VDP) generates a synchronization signal matching the resolution of the LCD to be connected with reference to the input clock. Therefore, when connecting LCDs having different resolutions such as a normal screen and a wide screen, for example, the clock input to the image processing LSI is changed in order to generate a synchronization signal matching the resolution of each LCD. May have to be.

[0004]

However, in the gaming machine, when the parts to be used are changed, it is necessary to set a new board control number and remake a new board even if the circuit pattern is the same. It's a rule. This is also one of the measures to prevent unauthorized modification of the gaming machine and production of illegal gaming machines that do not conform to the standard. Due to such special circumstances, it is inevitable that the number of types of substrates will increase depending on the type of display module. If this is the case, manufacturing costs will increase and inventory management will be troublesome. In some cases, a large amount of unused parts inventory may occur. Some crystal oscillators have multiple oscillation frequency outputs, but their frequencies are fixed. In other words, simply providing such a crystal oscillator in the display control device cannot cope with a case where a frequency outside the fixed range is required, and it cannot be said that the display control device is highly flexible. For that,
The cost is high.

Therefore, it is an object of the present invention to provide a display control device for a gaming machine, which can cope with a plurality of types of display modules without changing parts.

[0006]

In order to solve the above problems, a display control device for a gaming machine according to the present invention has an image processing unit for creating a video signal and a synchronizing signal, and an input frequency setting. The present invention is characterized by including a clock frequency adjustment unit that changes the frequency of the clock output to the image processing unit according to data, and a clock supply unit that supplies a reference clock to the clock frequency adjustment unit.

According to the above configuration, the reference clock output from the clock supply unit and input to the clock frequency adjustment unit is input to the image processing unit after the frequency is increased or decreased according to the frequency setting data. Becomes The frequency setting data is programmable data that is not restricted by the hardware configuration of the display control device, and by changing this in various ways, it is possible to create clocks of various frequencies based on the reference clock. Therefore, even when the screen type is changed and a different dot clock is required, it is not necessary to change the hardware of the display control device, and only the frequency setting data, that is, the software can be changed.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the accompanying drawings. First, FIG. 1 is a block diagram showing a configuration of a display control device (also referred to as a display control board) of a gaming machine. In recent game machines, a plurality of control devices (control boards) are each equipped with a microcomputer. In FIG. 1 as well, a game control board 5 that executes processing such as lottery for displaying or not the jackpot pattern.
The display control board 1 configured as a board different from (also referred to as a main control board) is shown. However, the present invention is not limited to this, and a mode in which the display control board 1 and the game control board 5 are combined, or a mode in which the voice control board and the display control board 1 (not shown) are combined will be described below. Technology can be applied.

As shown in FIG. 1, the display control board 1 has a C
PU7, crystal oscillator 15, VDP13 (video display
processor), a character ROM 19, a VRAM 17, and a clock frequency adjusting unit 9. In the present embodiment, an example in which the CPU 7 is a one-chip microcomputer provided with an arithmetic unit, ROM and RAM in the same package is shown, but of course ROM, RAM and DMAC.
An IC such as a (direct memory access controller) may be individually provided on the display control board 1. VDP13 is
Often called an image processing LSI or an image controller (display controller), it creates a video signal and an image signal in accordance with an instruction from the CPU 7 and outputs those signals to the LCD 3. When the LCD 3 is configured as a display module including an IC that takes charge of image amplification, γ processing, synchronization processing, interface, etc., the image signal and the synchronization signal from the VDP 13 are input to the IC. Otherwise, a γ correction circuit, a video amplification circuit, etc. are provided separately from the VDP 13 on the display control board 1.
Provided on top.

A control signal (display control command) from the game control board 5 is input to the CPU 7 via the input buffer 11. Communication between the game control board 5 and the display control board 1 is one-way communication from the game control board 5 to the display control board 1. The CPU 7 included in the display control board 1 creates screen display information including information such as symbols, backgrounds and characters to be displayed on the LCD 3, based on the display control command sent from the game control board 5. Then, the created screen display information is transferred to the VDP 13. VDP
A VRAM 1 13 stores the image data stored in the character ROM 19 based on the transferred screen display information.
7 is read out to create a video signal, and the video signal is transmitted to the LCD 3 together with the synchronization signal to display an image.

On the other hand, the reference clock generated by the crystal oscillator 15 is input to the CPU 7 and the clock frequency adjusting section 9. In addition to the reference clock, frequency setting data is input to the clock frequency adjusting unit 9. The clock frequency adjusting unit 9 controls the frequency of the input reference clock to VD in order to control the LCD 3 according to the frequency setting data.
It is adjusted to the frequency required by P13 and output to VDP13. The clock input to the VDP 13 is a so-called dot clock or an operation clock which is the basis of the dot clock. The crystal oscillator 15 only needs to be capable of outputting a clock having a specific frequency, and need not be capable of outputting a clock having a plurality of frequencies. The clock frequency adjusting unit 9 described above forms an essential part of the present invention, and its configuration is shown in FIG.

As shown in FIG. 2, the clock frequency adjusting section 9 comprises a frequency dividing circuit 92 and a frequency multiplying circuit 91. The reference clock generated by the crystal oscillator 15 is
Of the circuits forming the clock frequency adjusting unit 9, the clock frequency adjusting unit 9 is input to the multiplication circuit 91 at the preceding stage. The clock multiplied by a predetermined multiplication factor in the multiplication circuit 91 is frequency-divided in a predetermined ratio in the frequency division circuit 92 in the subsequent stage and output. The frequency setting data input to the clock frequency adjusting unit 9 includes the frequency division ratio setting data input to the frequency dividing circuit 92 and the frequency multiplying circuit 91.
And the multiplication rate setting data input to. The order of the frequency multiplying circuit 91 and the frequency dividing circuit 92 may be reversed.

For example, as shown in FIG. 3, when the reference clock supplied from the crystal oscillator is 19.5 MHz, the frequency multiplying circuit 91 is set to 4 and the frequency dividing circuit is set to 1/6 frequency, First, the reference clock is 78MHz
That is, the frequency is multiplied by 1 and the frequency is then divided to 13 MHz, resulting in a total of 2/3. As described above, by combining the multiplication and the frequency division, it is possible to create a desired clock over a wide range. It is possible to easily create a halfway clock that is 2/3 times the reference clock.

Both the frequency multiplication circuit 91 and the frequency division circuit 92 are composed of programmable circuits capable of changing the multiplication rate and frequency division ratio by input data, that is, by software. The frequency dividing circuit 92 is a programmable counter, and the frequency multiplying circuit 91 is a PLL (phase locked l
oop) A frequency synthesizer can be used. The PLL frequency synthesizer includes a phase comparator, a low pass filter (LP
F), a voltage controlled oscillator (VCO), a programmable counter (frequency divider), and the like. In this case, the multiplication rate setting data becomes the division ratio setting data of the frequency divider that constitutes the PLL frequency synthesizer (multiplication circuit 91).

The frequency setting data is often input serially, but parallel input may be used. Note that such a frequency setting data may be input to the clock frequency adjusting unit 9 from other than the CPU 7. Alternatively, a PLL frequency synthesizer with a built-in EPROM or the like can be adopted.

Further, in this embodiment, the reference clock generated by the crystal oscillator 15 is also input to the CPU 7. The reference clock input to the CPU 7 is used as it is or after being multiplied as the system clock of the CPU 7. By using the clock input to the clock frequency adjusting unit 9 and the clock input to the CPU 7 in common, the cost is reduced.

Further, since the CPU 7 and the VDP 13 do not perform processing in synchronization with each other, the clock input to the clock frequency adjusting unit 9 and the clock input to the CPU 7 may have different frequencies. Or, it does not have to be synchronized. However, since it is not economical to provide a plurality of crystal oscillators, either the configuration shown in FIG. 1 or another configuration shown in FIG. 4 is preferable.

The example shown in FIG. 4 is an example in which the clock output from the CPU 7 is input to the clock frequency adjusting unit 9 as a reference clock. In this configuration, the clock generated by the crystal oscillator 15 is only input to the CPU 7. The reference clock to be input to the clock frequency adjusting unit 9 is the CPU along with the frequency setting data.
I try to get from 7. That is, in the example of FIG. 4, the CPU 7 functions as a supply unit of the reference clock to be input to the clock frequency adjustment unit 9 (that is,
It is also used as a supply unit for the reference clock).

Further, as shown in FIG. 5, it is conceivable to configure the clock frequency adjusting unit 9'with a multiplication circuit 91a having a fixed multiplication rate and a frequency division circuit 92 whose frequency division ratio can be changed.
Further, a mode may be adopted in which the frequency division ratio is fixed and only the multiplication rate can be changed by software.

Although a liquid crystal display is exemplified in this specification, the present invention is not limited to this, and the present invention can be applied to any display device if a dot clock is required. is there.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a display control device.

FIG. 2 is a block diagram showing a configuration of a clock frequency adjusting unit.

FIG. 3 is a diagram following FIG. 2;

FIG. 4 is a block diagram showing another example of the circuit configuration of the display control device.

FIG. 5 is a block diagram showing another example of the clock frequency adjusting unit.

[Explanation of symbols]

1 game control device 3 LCD (display device) 7 CPU (central processing unit, clock supply unit) 9,9 'Clock frequency adjustment unit 13 VDP (image processing section) 15 Crystal oscillator (clock supply unit) 91, 91a multiplication circuit 92 frequency divider

Front page continuation (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 650 G09G 3/20 650B 5C082 650J 3/36 3/36 5/00 H04N 5/66 102B H04N 5/66 102 G09G 5/00 520W (72) Inventor Katsuya Yasuda Katsuya Yasuda 1-47-1, Naguno, Nakamura-ku, Nagoya, Aichi Nagoya International Center Building, 2nd floor, Daikoku Electric Co., Ltd. (72) Inventor Hitoshi Shinkawa, Nakamura-ku, Nagoya, Aichi 1-47, Nagano 1-chome Nagoya International Center Building 2nd floor Daikoku Denki Co., Ltd. F-term (reference) 2C088 AA36 CA13 EB55 2H093 NA06 NC09 NC11 NC50 NC90 ND50 ND60 5C006 AA02 AA03 AF01 AF13 AF25 AF46 AF47 AF72 BF08 BF09 BF16 BF15 BF14 BF15 BF14 BF22 BF23 BF25 EC08 FA08 FA16 FA52 5C058 AA07 AA08 BA01 BA22 BA25 BB08 BB10 BB14 5C080 AA10 BB05 DD21 DD27 EE01 EE18 GG02 GG12 JJ02 KK50 5C082 AA06 AA39 BA12 BB12 BB32 DA64 DA14 DA14 CA14 DA14 CA84 M06 MM07

Claims (5)

[Claims] 1. An image processing unit for generating a video signal and a synchronizing signal, a clock frequency adjusting unit for changing the frequency of a clock output to the image processing unit according to input frequency setting data, and the clock frequency. A display control device for a gaming machine, comprising: a clock supply unit that supplies a reference clock to an adjustment unit. 2. The display control device for a gaming machine according to claim 1, wherein the clock frequency adjusting unit includes a frequency dividing circuit and a frequency multiplying circuit. 3. The display control of the gaming machine according to claim 2, wherein the frequency setting data includes frequency division ratio setting data input to the frequency dividing circuit and / or multiplication rate setting data input to the frequency multiplying circuit. apparatus. 4. The frequency setting data is output from an arithmetic device included in the display control device.
A display control device for a gaming machine according to any one of 1. 5. The crystal supply unit is a crystal oscillator that outputs a clock of a specific frequency.
A display control device for a gaming machine according to any one of 1.