JP2007282788A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a game machine capable of preventing reset owing to influence of noise. <P>SOLUTION: When game balls rub each other to be charged, static discharge occurs and the noise occurs. Even when a reset signal RSTb is input to a serial/parallel IF chip 720 as the result of the influence of the noise, a built-in noise elimination part 790 eliminates a noise component from the reset signal RSTb. A put-out control board 70 is arranged in the vicinity of a guide path for an upper tray, a guide path for a lower tray, a ball-removing discharging path, a removed ball discharging path, a safe ball discharging path and an out ball discharging path to prevent the serial/parallel IF chip 720 from being reset due to the influence of the noise even when the put-out control board 70 is under influence of the noise. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a gaming machine with noise countermeasures taken.

  Conventionally, a ball tank for receiving and storing a game ball supplied from a pachinko island facility is provided above the back of a pachinko machine as a game machine. Below the ball tank, a tank rail is provided in an inclined state so that the game ball rolls from the ball tank toward the payout device. The payout device pays out game balls to an upper plate or a lower plate provided on the front surface of the pachinko machine. Since the game board is mounted in the center of the pachinko machine, the ball tank, the tank rail and the payout device are arranged around the back of the pachinko machine so as not to interfere with the game board.

  The game balls that have been driven into the game area defined on the game board are entered into various winning ports such as a normal winning port, a starting winning port, and a big winning port, or collected at the out port. The game balls that have entered the various winning awards and the game balls collected at the out outlets return to the pachinko island facility through various passages, and are stored again in the ball tank and circulate. The game balls are rubbed against each other, such as during circulation, and are charged. When the charged game ball is electrostatically discharged in the pachinko machine, noise may be generated and various control boards of the pachinko machine may output abnormal data.

There has been proposed a pachinko gaming machine in which a reset signal is directly connected to a reset terminal of a CPU, and connected to the reset signal of an output port via a delay circuit (for example, Patent Document 1). In this pachinko gaming machine, abnormal data is not output from the output port by a delay circuit that delays the operation start time of the output port until the CPU can operate.
Japanese Patent Laid-Open No. 11-47408 (FIG. 5)

  By the way, in the vicinity of the passage for paying out game balls from the payout device to the upper plate or lower plate, in the vicinity of the passage for returning the game balls that have entered the various winning openings and the game balls collected at the out port to the pachinko island facility, When a payout control board that performs payout control of the payout device based on a command from the main control board is arranged, the payout control board is particularly easily affected by noise caused by the charged game ball as described above. Then, for example, if the reset signal is affected by noise during the game and the CPU of the payout control board is reset, a command from the main control board may be missed.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a gaming machine that can prevent a reset due to the influence of noise.

  Effective solutions for achieving the above-described object will be described below. In addition, the effect | action etc. are demonstrated as needed. In addition, for easy understanding, the corresponding configuration in the embodiment of the invention is also shown as appropriate, but is not limited at all.

(Solution 1)
A ball tank for storing game balls, a tank rail provided below the ball tank in an inclined state so that the game ball rolls downstream from the ball tank, and a game supplied from the tank rail A payout device for paying out a ball as a prize ball, a guide passage for guiding a game ball paid out from the payout device, a discharge passage for discharging the game ball driven into the game board to the outside of the gaming machine, and the progress of the game A game machine comprising: a main control board for controlling the game machine; and a payout control board for performing payout control of the game ball by the payout device based on a command from the main control board, wherein the main control board A main control central processing unit having a main control serial interface unit for serially transmitting and receiving the command, and the payout control board includes a payout control serial interface for serially transmitting and receiving the command. An interface device incorporating a case unit, and reading out and analyzing the command from the interface device and performing payout control of the payout device, while a command different from the command is serialized from the interface device to the main control central processing unit A payout control central processing unit that performs control to be transmitted in a payout, a payout control oscillator that outputs a payout control clock signal to the interface device, and a payout that outputs a payout control reset signal to the interface device and the payout control central processing unit A control power-on reset circuit, and the interface device predetermines based on the payout control clock signal and an interface frequency divider that divides the payout control clock signal by a predetermined frequency dividing ratio. The band frequency component An interface noise removing unit for removing from the control reset signal, dividing the payout control clock signal by the interface divider, and sending the command serially transmitted from the main control central processing unit. While setting the reception timing received at the payout control serial interface unit and the transmission rate at which a command different from the command is sent from the payout control serial interface unit to the main control central processing unit, the interface noise A gaming machine that is reset by a payout control reset signal from which the predetermined band frequency component has been removed by a removing unit.

  In this gaming machine, a ball tank for storing game balls, a tank rail provided below the ball tank in an inclined state so that the game ball rolls downstream from the ball tank, and the tank rail A payout device for paying out the game balls supplied from the payout device as a prize ball, a guide passage for guiding the game balls paid out from the payout device, and a discharge passage for discharging the game balls driven into the game board to the outside of the gaming machine And a main control board that controls the progress of the game, and a payout control board that performs payout control of the game ball by the payout device based on a command from the main control board.

  The main control board includes a main control central processing unit having a main control serial interface unit for serially transmitting and receiving commands. The payout control board has an interface device with a payout control serial interface that serially transmits and receives commands, and performs payout control of the payout device by reading and analyzing commands from this interface device. Payout control central processing unit for performing serial transmission control from the apparatus to the main control central processing unit, payout control oscillator for outputting a payout control clock signal to the interface device, interface device and payout control central processing unit A payout control power-on reset circuit for outputting a payout control reset signal.

  The interface device includes an interface divider that divides by a predetermined dividing ratio using a payout control clock signal as a source oscillation, and an interface that removes a predetermined band frequency component from the payout control reset signal based on the payout control clock signal Built-in noise removal unit. The interface device divides the payout control clock signal by the interface divider and receives the command transmitted serially from the main control central processing unit at the payout control serial interface unit, and the main control central processing A transmission rate at which a command different from the command is serially transmitted from the payout control serial interface unit is set in the apparatus. Further, the interface device is reset by a payout control reset signal from which a predetermined band frequency component has been removed by the interface noise removal unit.

  When the game balls rub against each other and are charged, electrostatic discharge occurs and noise is generated. Even if the payout control reset signal is input to the interface device due to the influence of this noise, the built-in interface noise removal unit removes the noise component from the payout control reset signal. In this way, for example, a payout control board is arranged in the vicinity of the guide passage and the discharge passage, and even when the payout control board is in an environment that is extremely affected by noise, resetting of the interface device due to the influence of noise can be prevented. .

  In this embodiment, the ball tank 17 in FIG. 2 corresponds to a ball tank, the tank rail 18 in FIG. 2 corresponds to a tank rail, the payout device 76 in FIG. 2 corresponds to a payout device, and the upper plate for FIG. The guide passage 16a and the lower plate guide passage 19a correspond to the guide passage, the game board 13 in FIG. 1 corresponds to the game board, the pachinko machine 10 in FIG. 1 corresponds to the game machine, and the ball discharge passage in FIG. 16b, a ball discharge passage 16e, a safe ball discharge passage 16f, and an out ball discharge passage 16g correspond to discharge passages, the main control board 20 in FIG. 5 corresponds to a main control board, and a discharge command is a command from the main control board. 5, the payout control board 70 in FIG. 5 corresponds to the payout control board, the serial IF section 220 in FIG. 6 corresponds to the main control serial interface section, and the main CPU 200 in FIG. 6 corresponds to the main control central processing unit. 6 The serial IF unit 722 of the para IF chip 720 corresponds to a payout control serial interface unit, the serial para IF chip 720 in FIG. 6 corresponds to an interface device, the operation state commands correspond to different commands, and the payout CPU 700 in FIG. 6 corresponds to the control central processing unit, the clock signal CLKb in FIG. 6 corresponds to the payout control clock signal, the oscillator 792 in FIG. 6 corresponds to the payout control oscillator, and the reset signal RSTb in FIG. 6 corresponds to the payout control reset signal. The power-on reset circuit 794 in FIG. 6 corresponds to a payout control power-on reset circuit, the frequency divider 796 in FIG. 6 corresponds to an interface frequency divider, and the noise removing unit 790 of the serial para IF chip 720 in FIG. It corresponds to an interface noise removal unit.

(Solution 2)
The gaming machine according to claim 1, wherein the payout control oscillator outputs the payout control clock signal to the payout control central processing unit in addition to the interface device, and the payout control clock signal is the payout control clock signal. A gaming machine that is a system clock of a control central processing unit.

  Here, like the payout control clock signal, the clock signal includes a frequency component (high frequency) that is an integral multiple of its own frequency. For example, when the clock signal is 8 MHz, high frequency components such as 16 MHz, 24 MHz,... Are included. Thus, in a digital circuit, the clock signal has the highest frequency and is likely to be a noise source. Therefore, by outputting the payout control clock signal, which is the system clock, from the payout control oscillator to the payout control central processing unit and the interface device, that is, by sharing the payout control clock signal from the payout control oscillator, Noise generated by the signal is reduced.

(Solution 3)
The gaming machine according to claim 1 or 2, wherein the main control board outputs a main control clock signal which is a system clock of the main control central processing unit to the main control central processing unit. And a main control power-on reset circuit that outputs a main control reset signal to the main control central processing unit, wherein the main control central processing unit is configured to use the predetermined band based on the main control clock signal. A main control noise removing unit for removing a frequency component from the main control reset signal is incorporated, and the main control noise removing unit is reset by the main control reset signal from which the predetermined band frequency component is removed. To play. When the game balls rub against each other and are charged, electrostatic discharge occurs and noise is generated. Even if the main control reset signal is input to the main control central processing unit due to the influence of this noise, the built-in main control noise removal unit removes the noise component from the main control reset signal. Thus, even when the main control board is in an environment affected by noise, it is possible to prevent the main control central processing unit from being reset due to the influence of noise.

  In the present embodiment, the clock signal CLKa in FIG. 6 corresponds to the main control clock signal, the oscillator 292 in FIG. 6 corresponds to the main control oscillator, the reset signal RSTa in FIG. 6 corresponds to the main control reset signal, and FIG. The power-on reset circuit 294 corresponds to the main control power-on reset circuit, and the noise removal unit 290 of the main CPU 200 in FIG. 6 corresponds to the main control noise removal unit.

(Solution 4)
The gaming machine according to claim 2 or 3, wherein the payout control central processing unit removes the predetermined band frequency component from the payout control reset signal based on the payout control clock signal. A gaming machine comprising a removal unit and being reset by a payout control reset signal from which the predetermined band frequency component has been removed by the payout control noise removing unit. When the game balls rub against each other and are charged, electrostatic discharge occurs and noise is generated. Even if the payout control reset signal is input to the payout control central processing unit due to the influence of this noise, the built-in payout control noise removal unit removes the noise component from the payout control reset signal. In this way, for example, a payout control board is arranged in the vicinity of the guide passage and the discharge passage to prevent resetting of the payout control central processing unit due to the influence of noise even when the payout control board is in an environment that is extremely affected by noise. can do.

  In the present embodiment, the noise removal unit 712 of the payout CPU 700 in FIG. 6 corresponds to the payout control noise removal unit.

(Solution 5)
The gaming machine according to any one of solution means 1 to 4, wherein the gaming machine is a pachinko gaming machine.

  In the gaming machine of the present invention, since the gaming machine is a pachinko gaming machine, the effects of the solving means 1 to 4 can be obtained in the pachinko gaming machine. As a basic configuration of this pachinko gaming machine, a game ball is divided into a game area (a game area partitioned and formed on the game board 13 in this embodiment) in accordance with the operation of the operation means (in this embodiment, the operation handle 15). The symbol display means (LCD 35 in the present embodiment) displays the symbol information on condition that the game ball that has been struck and wins a winning opening (in this embodiment, the starting winning port 61) provided in the game area. A variable display is performed, and the display result of the symbol information is stopped and displayed. In addition, when a profit granting state (a big hit gaming state) occurs, a big winning opening provided in the gaming area (this embodiment, the big winning opening 62) is opened in a predetermined manner to allow a game ball to be won. Based on the winning, a game privilege (awarding a prize ball, writing a point on a magnetic card, etc.) is given to the player.

(Solution 6)
The gaming machine according to any one of solving means 1 to 4, wherein the gaming machine is a spinning-type gaming machine.

  In the gaming machine of the present invention, since the gaming machine is a spinning type gaming machine, the effects of the solving means 1 to 4 can be obtained in the spinning type gaming machine. As a basic configuration of this spinning machine, after a symbol information string composed of a plurality of symbol information (for example, a plurality of reel columns with a plurality of symbol information) is displayed in a variable manner, the display result of the symbol information is stopped and displayed. Fluctuation display means for starting, the fluctuation display of the symbol information is started based on the operation of the start operation means (for example, the operation lever), and the operation of the stop operation means (for example, the stop button) or the elapse of a predetermined time Based on this, the variable display of symbol information is stopped. And it is provided with the profit provision state generation | occurrence | production means which generate | occur | produces a profit provision state (big hit game state) on the condition that symbol information becomes a predetermined specific display mode.

(Solution 7)
The gaming machine according to any one of solution means 1 to 4, wherein the gaming machine is a fusion gaming machine in which a pachinko gaming machine and a revolving gaming machine are fused.

  In the gaming machine of the present invention, since the gaming machine is a fusion gaming machine, the operational effects of the solving means 1 to 4 can be obtained in the fusion gaming machine. As a basic configuration of the fusion gaming machine in which the pachinko gaming machine and the revolving type gaming machine are fused, a symbol information string composed of a plurality of symbol information (for example, a plurality of reel rows with a plurality of symbols) is variably displayed. Later, it is provided with a fluctuation display means for stopping and displaying the display result of the symbol information, and starts the fluctuation display of the symbol information based on the operation of the start operation means (for example, the operation lever), and the stop operation means (for example, the stop operation means) Button) or the change display of the symbol information is stopped based on the passage of a predetermined time. And it is provided with the profit grant state generation means which generates a profit grant state (big hit game state) on condition that the symbol information becomes a predetermined specific display mode, and by using the game ball as a game medium, A predetermined number of game balls are required at the start of the change, and a large amount of game balls are paid out when a profit granting state occurs.

  In the gaming machine of the present invention, reset due to the influence of noise can be prevented.

  In order to further clarify the configuration and operation of the present invention described above, a gaming machine to which the present invention is applied will be described below. In the present specification, a signal name prefixed with “#” means negative logic. “High level” means the “1” level of the two levels of the binary signal, and “Low level” means the “0” level.

A. Configuration of the pachinko machine 10:
A configuration of the pachinko machine 10 that is one of the embodiments of the present invention will be described. FIG. 1 is a front view showing the overall configuration of the pachinko machine 10, FIG. 2 is a diagram showing the back configuration of the pachinko machine 10, and FIG. 3 is a diagram showing various guide paths for guiding the game balls into the pachinko machine 10. FIG. 4 is a view showing various discharge passages for discharging the game ball out of the pachinko machine 10. First, the front configuration of the pachinko machine 10 will be described, and then the back configuration of the pachinko machine 10 will be described.

  As shown in FIG. 1, the pachinko machine 10 has an outer frame 11 fixed to a so-called island of a pachinko store, an inner frame 12 fitted into the outer frame 11, an upper center of the inner frame 12, and a game by a game ball is played. A game board 13 to be performed, a glass frame 14 having a glass plate disposed at the front of the game board 13, a handle 15 for receiving an operation by a player for launching a game ball to the game board 13, and the back of the pachinko machine 10 , A ball tank 17 for storing game balls for payout supplied from a pachinko island facility (not shown), an upper plate 16 and a lower plate 19 for storing game balls paid out to the player, a prepaid card A card unit 90 that accepts rental of game balls by the player.

  In the central part of the game board 13, there is provided a center accessory device 34 having a liquid crystal display (hereinafter referred to as LCD) 35, and a game ball winning is received below the center accessory device 34. A start winning opening 61 is provided. The start winning opening 61 includes a game ball sensor 65 that detects a winning game ball, and a game board driving unit 66 that expands and contracts the introduction path of the game ball in a predetermined case. A regular winning port 63 is disposed on the left and right sides of the starting winning port 61, and a large winning port 64 is disposed below.

  The pachinko machine 10 includes electrical decorations 55, 56, 57, 58, and 59 having light emitting diodes (LEDs). The electrical decorations 55 and 56 are provided on the left and right ends of the game board 13, the electrical decoration 57 is provided on the upper part of the LCD 35, and the electrical decorations 58 and 59 are provided on the left and right of the upper part of the glass frame 14, respectively. In addition, on the left of the upper part of the glass frame 14, a state display unit 72 for displaying a state relating to payout of the game ball is provided. A speaker 45 for outputting sound is built in the front center of the inner frame 12.

  Next, the back configuration of the pachinko machine 10 will be described. On the back of the pachinko machine 10, as shown in FIG. 2, a ball tank 17 is mounted on the upper side, and a dispensing device 76 is mounted on the right side thereof. Below the ball tank 17, a tank rail 18 is provided in a state where the game ball is inclined so as to roll from the ball tank 17 toward the payout device 76 (in a state of having a downward slope in FIG. 2). Yes. The ball tank 17 receives a game ball supplied from a pachinko island facility (not shown), and the game ball rolls on the tank rail 18 and is taken in by the payout device 76.

  A game board 13 shown in FIG. 1 is arranged below the tank rail 18. A center accessory device 34 shown in FIG. 1 is arranged near the center of the rear surface of the game board 13, and an LCD 35 is attached to the rear portion of the center accessory device 34. The LCD 35 is modularized with a symbol control board 30 that performs display control of the LCD 35, and is accommodated in a symbol control board box 31.

  A box mounting base 39 is disposed below the back side of the game board 13. The box mounting base 39 is mounted with a sub control board box 41 in which the sub control board 40 is housed and a main control board box 21 in which the main control board 20 is housed. Specifically, the main control board box 21 is mounted in a state of being superimposed on the sub control board box 41. The box mounting base 39 is arranged so that the sub control board box 41 and the main control board box 21 do not protrude outside the outline of the game board 13 even when the sub control board box 41 and the main control board box 21 are mounted. ing.

  Thus, the symbol control board box 31 and the main control board box 21 project below the tank rail 18. For this reason, the rear cover 42 is provided so that damage or an electrical short circuit due to the game ball falling from the ball tank 18 does not occur. The rear cover 42 is formed in a rectangular shape that covers the upper sides of the symbol control board box 31 and the main control board box 21, and is mounted so as to be openable and detachable by a cover hinge mechanism (not shown). The rear cover 42 is formed of a semi-transparent synthetic resin material so that, for example, an operator can visually check the symbol control board box 31 and the like even when the rear cover 42 is closed.

  The main control board box 21 is exposed without being covered by the rear cover 42 except for its upper side. The main control board 20 includes an inspection connector 22 and a RAM clear switch 23 on the lower side, and the inspection connector 22 and the RAM clear switch 23 are exposed from the main control board box 21. For this reason, even if the rear cover 42 is in the closed state, a connector of a board inspection apparatus (not shown) can be inserted into the inspection connector 22, and the main control board 20 can be inspected. Further, the RAM clear switch 23 can be operated to erase (clear) various information related to the game from the main control board 20.

  A launching device 43 is attached to the left side of the lower back area of the pachinko machine 10 (hereinafter simply referred to as “lower area”). This launching device 43 includes a firing motor 44 and a firing hammer 45. The firing motor 44 activates the firing hammer 46 to fire (shoot) a game ball toward a game area defined on the game board 13. In the center of the lower region, a payout control board box 71 in which the payout control board 70 is accommodated is mounted. The payout control board 70 performs payout control by performing drive control of a payout drive unit 75 (in this embodiment, a stepping motor) that is a drive source of the payout device 76. An interface board box 48 in which the interface board 47 is accommodated is mounted on the right side of the lower region. The interface board 47 electrically connects the card unit 90 and the payout control board 70 shown in FIG. 1 installed adjacent to the pachinko machine 10, and transmits and receives signals related to ball rental.

  Next, circulation of the game balls of the pachinko machine 10 and the pachinko island facility will be described. As shown in FIG. 3, the game balls stored in the ball tank 17 roll on the tank rail 18 and are taken in by the payout device 76. The taken game ball is cut out to either the upper dish guide passage 16a or the ball discharge / discharge passage 16b by a ball cutout member 77 that rotates integrally with the output shaft of the payout drive unit 75.

  The game ball cut out to the upper plate guide passage 16 a is guided to the upper plate ball storage unit 16 c communicating with the upper plate 16 and falls. When the upper plate 16 and the upper plate ball storage unit 16c are full and the game ball further falls, the game ball overflowing from the upper plate ball storage unit 16c passes over the partition wall 16d and is guided to the lower plate. It is guided to the lower dish ball storage part 19b that communicates with the lower dish 19 through 19a and falls.

  On the other hand, as shown in FIG. 4, the game ball cut out to the ball discharge passage 16b is guided to the pachinko island facility through the ball discharge passage 16e as a ball. Note that the game balls that have entered the start winning opening 61, the big winning opening 62, and the normal winning opening 63 shown in FIG. 1 are guided to the pachinko island facility through the safe ball discharge passage 16f as safe balls. Further, the game balls collected at the out port 64 shown in FIG. 1 are guided to the pachinko island facility through the out ball discharge passage 16g as the out ball. The extracted balls, safe balls, and out balls guided to the pachinko island facility are supplied again to the ball tank shown in FIG. 3, and the game balls circulate in the pachinko machine 10 and the pachinko island facility. The circulating game balls rub against each other and become charged, and electrostatic discharge generates noise.

  The extraction ball discharge passage 16e, the safe ball discharge passage 16f, and the out ball discharge passage 16g are arranged so as not to communicate with the upper plate guide passage 16a and the lower plate guide passage 19a. Thus, on the back surface of the payout control board box 71 shown in FIG. 2, there are a ball discharge passage 16e, a safe ball discharge passage 16f, an out ball discharge passage 16g, an upper plate guide passage 16a and a lower plate guide passage 19a. And the payout control board 70 accommodated in the payout control board box 71 is in an environment that is extremely susceptible to noise.

  FIG. 5 is a block diagram showing a schematic electrical configuration of the pachinko machine 10. The pachinko machine 10 includes a main control board 20 that controls the progress of the game, a payout control board 70 that controls the payout of the game ball based on a command from the main control board 20, an LCD 35, a speaker 45, A sub-control board 40 that controls effects using the electric decorations 55 to 59 and a symbol control board 30 that controls the display of moving images (performs display control) on the LCD 35 are provided. The payout control board 70 is connected to a payout drive unit 75 that executes payout of game balls, and a state display unit 72 that displays a state relating to the payout described above.

  Each of the main control board 20, the payout control board 70, the sub-control board 40, and the symbol control board 30 has a central processing unit (Central Processing Unit, hereinafter referred to as a CPU) that performs various arithmetic processes, and a CPU. Read-only memory (hereinafter referred to as ROM) that pre-stores a program that prescribes the arithmetic processing, random access memory (hereinafter referred to as RAM) that temporarily stores data handled by the CPU, etc. A circuit board on which electronic components corresponding to each board are mounted.

  Various commands are transmitted serially between the main control board 20 and the payout control board 70. Commands between the main control board 20 and the payout control board 70 are configured in units of 2 bytes, and are transmitted serially after being divided into units of 1 byte. The board that has received the command normally transmits an ACK (Acknowledge) signal that is a confirmation signal indicating that the command has been received normally to the board that has transmitted the command. Details of command transmission / reception between the main control board 20 and the payout control board 70 will be described later.

  Various commands are transmitted in parallel from the main control board 20 to the sub control board 40 and from the sub control board 40 to the symbol control board 30, respectively. As main commands from the main control board 20 to the sub-control board 40, there are commands for instructing basic effects relating to games such as so-called “big hit” and “out of game”. A main command from the sub control board 40 to the symbol control board 30 is a command for instructing a display mode of a moving image on the LCD 35 based on a command from the main control board 20.

  FIG. 6 is a block diagram showing details of the electrical configuration of the main control board 20 and the payout control board 70. The main control board 20 serves as a CPU for performing various arithmetic processes in the main control board 20, and outputs a main CPU 200 having a serial communication function and a parallel communication function with the outside, and a clock signal CLKa that is a system clock to the main CPU 200. An oscillator 292 and a power-on reset circuit 294 that outputs a reset signal RSTa for resetting the main CPU 200 are provided. In the present embodiment, 24 megahertz (MHz) is set as the clock signal CLKa that is the system clock. The power-on reset circuit 294 outputs a reset signal RSTa to the main CPU 200 to forcibly stop the operation of the main CPU 200 until the power supply voltage reaches a stable specified voltage when the power is turned on.

  The main CPU 200 divides the arithmetic processing unit 210 that performs arithmetic processing, the serial IF unit 220 that performs serial communication with the outside, the serial transmission rate and the serial reception timing based on the clock signal CLKa. A frequency divider 296 to be set in this way, a parallel IF unit 230 that performs parallel communication with the outside, and a noise removal unit 290 that removes a predetermined band frequency component are configured. The noise removing unit 290 receives the clock signal CLKa from the oscillator 292 and the reset signal RSTa from the power-on reset circuit 294, respectively. The noise removal unit 290 performs a filter process for removing a predetermined band frequency component from the reset signal RSTa based on the clock signal CLKa (the noise removal unit 290 is a so-called digital noise removal circuit). In this filter processing, noise of 1 microsecond (μs) obtained by experiment is removed. The filtered reset signal RSTa is input to the arithmetic processing unit 210, the serial IF unit 220, and the parallel IF unit 230, respectively. As described above, the impulse-like reset signal RSTa due to the influence of noise is not directly input to the arithmetic processing section 210, the serial IF section 220, and the parallel IF section 230, respectively, so that the reset due to the influence of noise does not work. It has become.

  The serial IF unit 220 receives and stores the parallel data TDa from the arithmetic processing unit 210, receives the data stored in the transmission buffer register 240, converts it into serial data Dab, and transmits it serially to the payout control board 70. The transmission shift register 250, the reception shift register 260 that receives and stores the serial data Dba from the payout control board 70, and the data that is stored in the reception shift register 260 is received and stored as parallel data RDa by the arithmetic processing unit 210. A reception buffer register 270 and a serial management unit 280 for managing the operation state of each unit in the serial IF unit 220 are provided. The constituent circuits of the serial IF unit 220 are integrated on one chip. The transmission buffer register 240, the transmission shift register 250, the reception shift register 260, and the reception buffer register 270 are registers each having a storage capacity of 1 byte.

  The serial management unit 280 allows the transmission shift register 250 and the transmission buffer register 240 to transfer data from the transmission buffer register 240 to the transmission shift register 250 when the transmission shift register 250 is not performing serial transmission. After being passed, the circuit is configured to erase data from the transmission buffer register 240.

  The serial management unit 280 permits the data transfer from the reception shift register 260 to the reception buffer register 270 when the data is not stored in the reception buffer register 270 with respect to the reception shift register 260 and the reception buffer register 270. The processing unit 210 is configured to erase data from the reception buffer register 270 after reading the parallel data RDa from the reception buffer register 270.

  The arithmetic processing unit 210 writes the parallel data TDa to the transmission buffer register 240 by lowering the write signal #WRa to the transmission buffer register 240, and sets the read signal #REa to the reception buffer register 270. By lowering, the parallel data RDa is read from the reception buffer register 270.

  The arithmetic processing unit 210 receives signals indicating various states in the serial IF unit 220 from the serial management unit 280. Signals that the arithmetic processing unit 210 receives from the serial management unit 280 include a transmission buffer empty signal TEa that is set to a high level when the transmission buffer register 240 is cleared, and a transmission shift register 250 that is transmitting serially. There is a serial transmission signal TCa that is set to a high level, and a reception data presence signal DFa that is set to a high level when data is stored in the reception buffer register 270.

  As shown in FIG. 6, the payout control board 70 includes a payout CPU 700 for performing various arithmetic processes in the payout control board 70, a serial para IF chip 720 in which a circuit for performing serial communication and parallel communication with the outside is formed, and a payout An oscillator 792 that outputs a clock signal CLKb to the CPU 700 and the serial para IF chip 720, and a power-on reset circuit 794 that outputs a reset signal RSTb that resets the payout CPU 700 and the serial para IF chip 720 are provided. In this embodiment, the clock signal CLKb is a system clock of the payout CPU 700, and 8 MHz is set as the clock signal CLKb. The power-on reset circuit 794 outputs a reset signal RSTb to the payout CPU 700 to forcibly stop the operation of the payout CPU 700 until the power supply voltage reaches a stable specified voltage when the power is turned on, and the serial para IF chip 720. Also, the reset signal RSTb is output.

  The clock signal includes a frequency component (high frequency) that is an integral multiple of its own frequency. For example, when the clock signal CLKb of the oscillator 792 is 8 MHz, it includes high frequency components such as 16 MHz, 24 MHz,. Thus, in a digital circuit, the clock signal has the highest frequency and is likely to be a noise source. Therefore, in the present embodiment, the clock signal CLKb, which is the system clock, is output from the oscillator 792 to the payout CPU 700 and the serial IF chip 720, that is, the clock signal CLKb from the oscillator 792 is shared, thereby generating the clock signal. Noise caused by the cause is reduced.

  The payout CPU 700 has a circuit configuration of an arithmetic processing unit 710 that performs arithmetic processing and a noise removing unit 712 that removes a predetermined band frequency component. The noise removal unit 712 receives the clock signal CLKb from the oscillator 792 and the reset signal RSTb from the power-on reset circuit 794, respectively. The noise removing unit 712 performs a filtering process for removing a predetermined band frequency component from the reset signal RSTb based on the clock signal CLKb (the noise removing unit 712 is a so-called digital noise removing circuit). In this filter processing, noise of 1 μs obtained by experiment is removed. The filtered reset signal RSTb is input to the arithmetic processing unit 710. As described above, the impulse-like reset signal RSTb due to the influence of noise is not directly input to the arithmetic processing unit 710, and the reset due to the influence of noise does not work.

  The serial interface IF chip 720 includes a serial IF unit 722 that performs serial communication with the outside, a parallel IF unit 730 that performs parallel communication with the outside, and a noise removal unit 790 that removes a predetermined band frequency component. The constituent circuits of the serial IF chip 720 are integrated on one chip.

  As will be described in detail later, the noise removal unit 790 receives the clock signal CLKb from the oscillator 792 and the reset signal RSTb from the power-on reset circuit 794, respectively. The noise removing unit 790 performs a filtering process for removing a predetermined band frequency component from the reset signal RSTb based on the clock signal CLKb (the noise removing unit 790 is a so-called digital noise removing circuit). In this filter processing, noise of 1 μs obtained by experiment is removed. The filtered reset signal RSTb is input to the serial IF unit 722 and the parallel unit 750. As described above, the impulse-like reset signal RSTb caused by the noise is not input to the serial IF unit 722 and the parallel IF unit 730, and the reset caused by the noise affects the serial IF unit 722 and the parallel IF unit 730. There is no such thing.

  The serial IF unit 722 receives and stores the parallel data TDb from the arithmetic processing unit 710, receives the data stored in the transmission buffer register 740, converts it into serial data Dba, and transmits it to the main control board 20 in serial. The transmission shift register 750, the reception shift register 760 that receives and stores the serial data Dab from the main control board 20, and the data that is stored in the reception shift register 760 is received and stored as parallel data RDb by the arithmetic processing unit 710. A reception buffer register 770 and a serial management unit 780 for managing the operation state of each unit in the serial para IF chip 720 are provided. The transmission buffer register 740, the transmission shift register 750, the reception shift register 760, and the reception buffer register 770 are registers each having a storage capacity of 1 byte.

  The serial management unit 780 is configured to permit data transfer from the reception shift register 760 to the reception buffer register 770 when no data is stored in the reception buffer register 770. Also, the serial management unit 780 allows the transmission shift register 750 and the transmission buffer register 740 to pass data from the transmission buffer register 740 to the transmission shift register 750 when the transmission shift register 750 is not transmitting serially. Is also configured to erase data from the transmission buffer register 740 after the data is transferred.

  Note that the timing (reception timing) at which the serially-transmitted IF chip 720 receives a command transmitted serially from the main control board 20 is determined based on the clock signal CLKb output from the oscillator 792. It is made by a built-in frequency divider 796. The reception timing is set to 16 times the transmission rate for serial transmission from the serial para IF chip 720 (transmission shift register 750) to the main control board 20. Specifically, when the clock signal CLKb of the oscillator 792 is 8 MHz, the clock signal CLKb is divided by the frequency divider 796, the transmission rate is set to 1200 baud rate (bps), and the reception timing is 19.2 kilohertz. (KHz).

  The payout CPU 700 (arithmetic processing unit 710) writes the parallel data TDb to the transmission buffer register 740 by lowering the write signal #WRb to the transmission buffer register 740, and reads the read signal to the reception buffer register 770. The parallel data RDb is read from the reception buffer register 770 by causing #REb to fall.

  The arithmetic processing unit 710 receives signals indicating various states in the serial para IF chip 720 from the serial management unit 780. Signals that the arithmetic processing unit 710 receives from the serial management unit 780 include a transmission buffer empty signal TEb that is set to a high level when the transmission buffer register 740 is cleared, and a transmission shift register 750 that is transmitting serially. There are a serial transmission signal TCb that is at a high level and a reception data presence signal DFb that is at a high level when data is stored in the reception buffer register 770.

  The command transmitted from the main control board 20 to the payout control board 70 is a payout command relating to payout of game balls. The payout command is, for example, a command for designating the number of game balls to be paid out, and is a multi-bit command. The payout command is serially transmitted from the transmission shift register 250 to the reception shift register 760. When the payout CPU 700 determines that the payout command has been normally received, the payout CPU 700 transmits an ACK signal to the main control board 20. The ACK signal is transmitted from the parallel IF unit 730 to the parallel IF unit 230 in parallel. Although not shown, the parallel IF unit 730 and the parallel IF unit 230 are provided with a plurality of parallel ports. The ACK signal is a 1-bit signal, and is transmitted and received between the parallel IF unit 730 and the parallel IF unit 230 using a 1-bit port among a plurality of parallel ports.

  The command that the payout control board 70 transmits to the main control board 20 is an operation state command for notifying the main control board 20 of the operation state of the pachinko machine 10 detected by the payout CPU 700. The payout command is a multi-bit command, and the operation state command includes, for example, ball break information indicating that there are not enough game balls in the prize ball unit, and that the card unit 90 is not connected to the pachinko machine 10. And information indicating that the command cannot be normally transmitted and received between the main control board 20 and the payout control board 70. The operation state command is serially transmitted from the transmission shift register 750 to the reception shift register 260. When the main CPU 200 determines that the operation state command has been normally received, the main CPU 200 transmits an ACK signal to the payout control board 70. The ACK signal is a 1-bit signal, and is transmitted / received between the parallel IF unit 230 and the parallel IF unit 730 using a 1-bit port among a plurality of parallel ports.

  Here, the noise removing unit 790 integrated (incorporated) in the serial para IF chip 720 will be described. FIG. 7 is a schematic configuration diagram illustrating an example of a circuit configuration of the noise removing unit 790, and FIG. 8 is a timing chart illustrating an operation of the noise removing unit 790. As shown in FIG. 7, the noise removal unit 790 is configured with a shift register group 790a as a center. The shift register group 790a is configured by connecting flip-flop circuits in multiple stages. In this embodiment, the shift register group 790a is configured by 10 stages of flip-flop circuits.

The clock signal CLKb from the oscillator 792 shown in FIG. 6 is inputted to the CK terminal of the shift register group 790a, and the reset signal RSTb from the power-on reset circuit 794 shown in FIG. 6 is inputted to the A terminal of the shift register group 790a. The logic is inverted through the inverter 790b, and the inverted reset signal RSTb is input. The shift register group 790a takes in the inverted reset signal RSTb input to the A terminal as data every time the clock signal CLKb is input. Then, each time the clock signal CLKb is inputted, the fetched data is moved one by one to the adjacent flip-flop circuit and a signal is output from the output terminal. As a result, signals are sequentially output from the Q ₀ terminal, Q ₁ terminal,..., And Q ₉ which are output terminals of the flip-flop circuit based on the moved data. Specifically, the Q ₁ terminal is output with a delay of one clock of the inverted reset signal RSTb from the Q ₀ terminal, the Q ₂ terminal is output with a delay of one clock of the inverted reset signal RSTb from the Q ₁ terminal, and so on. , Q ₉ terminal is output with a delay of one clock of the inverted reset signal RSTb from the Q ₈ terminal. Thus, the Q ₉ terminal outputs a signal delayed from the Q ₀ terminal by 10 clocks of the inverted reset signal RSTb.

The signals output from the Q ₀ terminal to Q ₉ terminal are input to the AND circuit 790c, and the AND circuit 790c takes a logical product from these signals. This operation result is inverted in logic via the inverter 790d (point X in the figure) and output to the serial IF unit 722 and the parallel IF unit 730 as the reset signal RSTb. Note that the logic of the inverter 790d is inverted to return to the logic of the reset signal RSTb input to the noise removing unit 790.

Next, the operation of the noise removal unit 790 in a state where the reset signal RSTb is input will be described. As shown in FIG. 8, when the clock signal CLKb is input to the CK terminal, the shift register group 790a starts to fetch the inverted reset signal RSTb input to the A terminal as data (timing t0). A signal is output from the Q ₀ terminal to the AND circuit 790c based on the data captured at the next rising edge (referred to as “up edge”) of the clock signal CLKb (timing t1). Subsequently, data is moved from the flip-flop circuit having the Q ₀ terminal to the flip-flop circuit having the Q ₁ terminal at the next up edge, and a signal is output from the Q ₁ terminal to the AND circuit 790c based on the moved data ( Timing t2). Flip-flop circuit having a timing t2, the Q ₀ pin captures the inverted reset signal RSTb is input to the A terminal as data.

Subsequently, the data is moved from the flip-flop circuit having the Q ₁ terminal to the flip-flop circuit having the Q ₂ terminal at the next up edge, and a signal is output from the Q ₂ terminal to the AND circuit 790c based on the moved data ( Timing t3). In the timing t3, move the data to the flip-flop circuit having a Q ₁ terminal from the flip-flop circuit having a Q ₀ terminal and outputs a signal from the Q ₁ terminal on the basis of the movement data to the AND circuit 790c. The flip-flop circuit having the Q ₀ terminal takes in the inverted reset signal RSTb input to the A terminal as data.

After that, the up edge by the clock signal CLKb continues, and data is output from the flip-flop circuit having the Q ₈ terminal to the flip-flop circuit having the Q ₉ terminal at the tenth up edge after the signal is output from the Q ₀ terminal at the timing t1. And a signal is output from the Q ₉ terminal to the AND circuit 790c based on the moved data. Inverted reset signal RSTb from the timing t0 is output to the inverter 790c becomes true operation result for the first time by a signal output from the Q ₀ pin to Q ₉ terminal for a state which is input to the A terminal. The inverter 790c inverts the logic of the input signal, and outputs it to the serial IF unit 722 and the parallel IF unit 730 shown in FIG. 6 as the reset signal RSTb at the point X (timing t4).

Thus, the period from the timing t1~ timing t4 is reached 10 clocks of the inverted clock signal CLKb, Q ₉ terminal outputs 10 clocks delayed signal of the inverted reset signal RSTb from Q ₀ pin. When the clock signal CLKb is 8 MHz, one clock is 0.125 μs, so that 10 clocks is 1.25 μs. That is, unless a signal for at least 10 clocks is input to the A terminal, the reset signal RSTb is not output to the serial IF unit 722 and the parallel IF unit 730 at the point X. Therefore, noise of 1 μs obtained by experiment is removed by the noise removing unit 790.

B. Operation of the pachinko machine 10:
B-1. Dispensing scheduled interruption processing by the dispensing control board 70:
As one of the operations of the pachinko machine 10, the payout interruption process in the payout control board 70 will be described. FIG. 9 is a flowchart showing a payout interruption process by the payout control board 70. The payout scheduled interrupt process is repeatedly executed by the payout CPU 700 of the payout control board 70 at a predetermined interval (in this embodiment, 1 millisecond (hereinafter referred to as ms)).

  The payout CPU 700 (arithmetic processing unit 710) of the payout control board 70 executes various processes in the payout scheduled interrupt process. In the present embodiment, the payout CPU 700 performs an ACK output process (step S10), a CR communication process (step S20), a full / ball-out check process (step S30), a command reception process (step S40), and a command analysis process (step S50), a payout process (step S60), a status display process (step S70), and a command transmission process (step S80) are executed in this order. Each process (steps S10 to S80) in the payout scheduled interrupt process varies depending on the progress of the game, so the time required for completion varies depending on the progress of the game. The process of the ACK output process (step S10) in the payout scheduled interrupt process has priority over the processes of the other processes (steps S20 to S80). In this embodiment, the process of the ACK output process (step S10) is a payout scheduled interrupt. It is executed at the beginning of the process.

  The ACK output process (step S10) is a process for outputting an ACK signal to the main control board 20 when a command is normally received from the main control board 20. Details of the ACK output process (step S10) will be described later.

  The CR communication process (step S20) is a process for exchanging data related to the rental of game balls with the card unit 90. In the full tank / out of ball check process (step S30), it is confirmed whether the game balls stored in the lower plate 19 are full or the game balls stored in the ball tank 17 are not empty. By doing so, it is a process for detecting a physical state which becomes an obstacle to payout of the game ball.

  The command reception process (step S40) is a process for receiving a payout command transmitted serially from the main control board 20 in units of 1 byte. Details of the command reception process (step S40) will be described later. The command analysis process (step S50) is a process for analyzing the contents of the payout command received in the command reception process (step S40). Specifically, in the command analysis process (step S50), it is determined whether or not the number of payouts indicated by the payout command is within a normal value range (for example, 1 to 15). Assuming that game balls are not paid out, the payout command is ignored. If the payout number is within the normal value range, the payout number indicated by the payout command is added to the total payout number stored in the payout number buffer. The payout number buffer is a buffer for storing the total number of game balls to be paid out by the pachinko machine 10.

  The payout process (step S60) is a process for executing payout of game balls. In the payout process (step S60), the payout CPU 700 instructs the payout drive unit 75 to operate in accordance with the lending instruction obtained in the CR communication process (step S20) and the contents of the payout number buffer. The signal is output. In the present embodiment, when there is an abnormal change in the number of game balls requested to be paid out from the card unit 90 or the main control board 20, there is a physical failure in the full tank / out of ball check process (step S30). Is confirmed, the payout CPU 700 temporarily stops paying out the game balls.

  The state display process (step S70) is a process for causing the state display unit 72 to display the operation state of the pachinko machine 10 detected by the payout CPU 700. In the present embodiment, the display of the operation state in the state display unit 72 is performed by displaying a number corresponding to each state. For example, an abnormality occurs in transmission / reception of commands between the main control board 20 and the payout control board 70. In this case, “0” is displayed on the state display unit 72, and “1” is displayed on the state display unit 72 when a ball break occurs in the ball tank 17, and the card unit 90 is connected to the payout control board 70. If not, “7” is displayed in the status display section 72.

  The command transmission process (step S80) is a process for transmitting an operation state command in units of 2 bytes from the payout control board 70 to the main control board 20 in units of 1 byte. Details of the command transmission process will be described later.

B-2. Command reception processing in the payout scheduled interrupt processing:
FIG. 10 is a flowchart showing details of the command reception process (step S40) executed in the payout scheduled interrupt process. As described above, the command reception process (step S40) is one of various processes in the payout scheduled interrupt process shown in FIG. 9, and is executed by the payout CPU 700 (calculation processing unit 710) of the payout control board 70. The The command reception process is a process for receiving a payout command transmitted serially from the main control board 20.

  When the payout CPU 700 starts the command receiving process shown in FIG. 10, it is “whether the received data present signal DFb is at a high level”, that is, “when data is stored in the receiving buffer register 770”. Whether or not (step S410). Here, when it is determined in the command reception process that “the received data present signal DFb is at the high level” (step S410), the 2-byte payout transmitted from the main control board 20 to the payout control board 70. In the command, the first byte is stored in the reception buffer register 770.

  When “the received data present signal DFb is at the high level” (step S410), the payout CPU 700 reads the first byte of the payout command stored in the reception buffer register 770 (step S412). When the first byte of the payout command is read, the serial management unit 780 of the serial para IF chip 720 clears the first byte of the payout command stored in the reception buffer register 770, and the payout command stored in the reception shift register 760. Are transferred to the reception buffer register 770.

  Subsequent to step S412, the payout CPU 700 reads the second byte of the payout command stored in the reception buffer register 770 (step S422). When the second byte of the payout command is read, the serial management unit 780 of the serial para IF chip 720 clears the second byte of the payout command stored in the reception buffer register 770.

  Subsequent to step S422, the payout CPU 700 collates the first byte of the payout command read in step S412 with the second byte of the command read in step S422 (step S440), and determines whether or not they match. Judgment is made (step S445). In the present embodiment, the second byte of the payout command is data generated by inverting each bit of the first byte of the payout command on the main control board 20. If the first byte and the second byte of the read out payout command match (step S445), the payout CPU 700 sets an ACK flag Fa for transmitting an ACK signal to the main control board 20 (step S450). ), The command transmission process is terminated. The ACK flag Fa is data used in the ACK output process (step S10) described above and stored in a register or RAM (not shown) built in the payout CPU 700. The ack flag Fa is set to “0” when the payout CPU 700 is activated.

  On the other hand, if the first byte and the second byte of the read command do not match (step S445), the payout CPU 700 ends the command reception process without setting the ack flag Fa. As a result, when the payout command is not normal, the ACK signal is not output to the main control board 20, and the main control board 20 determines that an abnormality has occurred in the transmission of the payout command because the ACK signal is not returned. Can do.

  FIG. 11 is a time chart showing the state of each signal on the payout control board 70 when the command receiving process (step S40) is executed. For convenience of explanation, in FIG. 11, the scale of the serial transmission time of the first byte and the second byte of the payout command is reduced compared to the scale of the arithmetic processing time of the payout CPU 700 (arithmetic processing unit 710). .

  In the command reception process shown in FIG. 10, when it is determined that “the reception data present signal DFb is at the high level” by the fall of the read signal #REb (step S410 in FIG. 10), the reception buffer register 770. The first byte of the payout command is output to the parallel data RDb, and the first byte of the payout command is read from the reception buffer register 770 by the payout CPU 700. When the first byte of the payout command is read, the reception buffer register 770 is cleared, and the reception data presence signal DFb becomes low level (timing tb11 to tb12, step S412 in FIG. 10). When the second byte of the payout command is transferred from the reception shift register 760 to the reception buffer register 770, the reception data presence signal DFb becomes high level (timing tb13).

  Thereafter, the second byte of the payout command is read from the reception buffer register 770 in the same manner as the first byte of the command. When the second byte of the payout command is read, the reception buffer register 770 is cleared, and the reception data presence signal DFb becomes low level (timing tb21 to tb22, step S422 in FIG. 10).

  In this embodiment, the reception timing of the serial IF chip 720 is set to 19.2 kHz, which is 16 times the transmission rate (1200 bps), as described above. The serial IF chip 720 samples three times for each of the start bit ST, the data bits D0 to D7 of the payout command, and the stop bit SP, and determines the majority of the values detected by the three times of sampling. To do. As a result, the reliability of the payout command reception is improved.

B-3. ACK output processing in the payout scheduled interrupt processing:
FIG. 12 is a flowchart showing details of the ACK output process (step S10) executed in the payout scheduled interrupt process. As described above, the ACK output process (step S10) is one of various processes in the payout scheduled interrupt process shown in FIG. 9, and is executed by the payout CPU 700 (calculation processing unit 710) of the payout control board 70. The

  When the payout CPU 700 starts the ACK output process (step S10) shown in FIG. 12, if the ACK flag Fa is set (step S110), the payout signal is sent via the parallel IF unit 730 of the serial IF chip 720. Output to the main control board 20 (step S120). Thereafter, the payout CPU 700 resets the ACK flag Fa (step S130), and then ends the ACK output process. If the ack flag Fa is not set (step S110), the payout CPU 700 ends the ack output process without outputting an ack signal.

  The case where the ACK flag Fa is set means that the ACK flag Fa is set when the payout command is normally received in the command reception process (step S40) shown in FIG. 10 (step S450 in FIG. 10). It is. As shown in FIG. 9, in the scheduled interrupt process, the ACK output process (step S10) is executed first in preference to the command reception process (step S40), so the ACK flag Fa is set. In this case, an ACK signal is output in the ACK output process (step S10) in the next scheduled interrupt process.

B-4. Command transmission processing in the payout scheduled interrupt processing:
FIG. 13 is a flowchart showing details of the command transmission process (step S80) executed in the payout scheduled interrupt process. As described above, the command transmission process (step S80) is one of various processes in the payout scheduled interrupt process shown in FIG. 9, and is executed by the payout CPU 700 (calculation processing unit 710) of the payout control board 70. The The command transmission process is a process for serially transmitting an operation state command to the main control board 20.

  The payout CPU 700, when starting the command transmission process shown in FIG. 13, determines the value of the transmission job flag Fj (step S810). The transmission job flag Fj is a flag indicating a state in the command transmission process, and is set to “0” when the payout CPU 700 is activated, and is data stored in a register or RAM (not shown) built in the payout CPU 700. .

  In the case of “transmission job flag Fj = 0”, the payout CPU 700 executes command preparation processing (step S815) for preparing an operation state command to be transmitted to the main control board 20. In the command preparation process, when the payout CPU 700 determines that it is necessary to transmit an operation state command based on signals from the sensors input to the plurality of ports of the serial para IF chip 720, the payout CPU 700 is based on the signals from the sensors. To generate the first byte of the operation state command. Then, after setting the transmission job flag Fj to “1”, the command preparation process (step S815) is terminated.

  In the case of “transmission job flag Fj = 1”, the payout CPU 700 executes command output processing for outputting an operation state command in units of 2 bytes to the main control board 20 (step S820). When the flag Fj = 2 ”, an ACK waiting process for confirming an ACK signal from the main control board 20 is executed (step S860). The payout CPU 700 ends the command preparation process (step S815), the command output process (step S820), and the ACK waiting process (step S860), and then ends the command transmission process (step S80). Details of the command output process (step S820) and the ACK waiting process (step S860) will be described later.

  FIG. 14 is a flowchart showing details of command output processing (step S820) in command transmission processing (step S80). When the payout CPU 700 (arithmetic processing unit 710) starts the command output process (step S820) shown in FIG. 14, it is determined whether “the transmission buffer empty signal TEb is at the high level” and “the serial transmission signal TCb is at the low level”. That is, it is determined whether or not “when no data is stored in the transmission buffer register 740” and “when the transmission shift register 750 is not performing serial transmission” (step S822). When “Transmission buffer empty signal TEb is high level” and “Serial transmission signal TCb is low level” (step S822), payout CPU 700 inverts each bit of the first byte of the operation state command, That is, among the bits of the first byte, the bit that is “0” is set to “1”, the bit that is “1” is set to “0”, and the second byte that is the remaining lower 1 byte of the operation state command is generated. (Step S834). In the present embodiment, the first byte of the operation state command is data having a substantial meaning as the operation state command, and the second byte of the operation state command is the correctness of the operation state command on the main control board 20 side. This is data for judgment.

  Then, after generating the second byte of the operation state command (step S834), the first byte of the operation state command is written into the transmission buffer register 740 (step S842). Thereafter, after waiting for a preset write standby period Lwa (step S844), the second byte of the generated operation state command is written to the transmission buffer register 740 (step S846). The payout CPU 700 outputs the operation state command (step S846), sets the transmission job flag Fj to “2” (step 850), and ends the command output processing.

  Here, the write standby period Lwa is a transmission register delivery period that is a period from the writing of the first byte of the operation state command to the transmission buffer register 740 to the delivery of the first byte to the transmission shift register 750. This is a period longer than Lbs, and is a period in which sufficient time is allowed to execute the second byte write process (step S846 in FIG. 14) until the end of the scheduled interrupt process, and until the start of the next scheduled interrupt process. It is not a long period. The write standby period Lwa is shorter than the serial transmission period Lsc that is a period until the serial transmission of the first byte of the operation state command is completed, and is shorter than 1 ms that is the interval of the scheduled interrupt processing. It is a short period. In the present embodiment, the write standby period Lwa is set to 2.5 microseconds. Note that the transmission register delivery period Lbs according to the hardware specifications of the serial para IF chip 720 of this embodiment is about 1.25 microseconds. If the calculation processing time of the payout CPU 700 required for the second byte writing process (step S846 in FIG. 14) is equal to or longer than the transmission register delivery period Lbs of the serial para IF chip 720, the command waiting process shown in FIG. The standby process (step S844) by the software is unnecessary.

  FIG. 15 is a time chart showing the state of each signal on the payout control board 70 when the command output process (step S820) is executed. In the command output process shown in FIG. 14, it is determined that “the transmission buffer empty signal TEb is at the high level” and “the serial transmission signal TCb is at the low level” (step S822 in FIG. 14). When writing is performed (step S842 in FIG. 14), output of the first byte of the operation state command is started to the parallel data TDb (timing ta1), and then transmitted by the falling edge of the write signal #WRb. The first byte of the operation state command is written to the buffer register 740 (timing ta2).

  The transmission buffer register 740 delivers the first byte of the written operation state command to the transmission shift register 750, and is cleared by the serial management unit 780 when the delivery is completed. The transmission shift register 750 outputs the first byte of the operation state command received from the transmission buffer register 740 to the serial data Dba. In the serial data Dba during serial transmission, each bit from the first bit D0 to the eighth bit D7 of the command follows the start bit ST, and finally the stop bit SP is output. In this way, when serial transmission of the first byte of the operation state command is started, the serial transmission in-progress signal TCb becomes high level (timing ta3).

  After writing the first byte of the operation state command (timing ta2, step S842 in FIG. 14) and after waiting for the write standby period Lwa (step S844 in FIG. 14), the same as the first byte of the operation state command The second byte of the operation state command is written into the transmission buffer register 740 (timing ta4, step S846 in FIG. 14). At this time, the transmission shift register 750 is serially transmitting the first byte of the operation state command and cannot receive the second byte of the operation state command from the transmission buffer register 740. The second byte of the received operation state command is stored and held, and the transmission buffer empty signal TEb becomes low level (timing ta4).

  Thereafter, when the transmission of the first byte of the operation state command by the transmission shift register 750 is completed, the transmission buffer register 740 transfers the second byte of the operation state command to be stored to the transmission shift register 750, and this transfer is completed. Then, it is cleared by the serial manager 780, and the transmission buffer empty signal TEb becomes high level (timing ta5). Thereafter, the transmission shift register 750 outputs the second byte of the operation state command received from the transmission buffer register 740 to the serial data Dba in the same manner as the first byte of the operation state command (timing ta6 to ta7).

  In this embodiment, the payout CPU 700 repeatedly executes the scheduled interrupt process at an interval of 1 ms, while the serializer IF chip 720 executes serial transmission at a transmission rate of 1200 bps (Bit Per Second). 1200 bps is a low-speed communication speed that can use a transmission / reception element with a low response speed, such as a relatively inexpensive photocoupler, and is not affected by electrical noise. If the transmission rate in serial transmission is 1200 bps, the reliability of command transmission against electrical noise can be ensured. Since the transmission rate is 1200 bps, in this embodiment, the time required for the serial para IF chip 720 to serially transmit the 2-byte operation state command is about 16.7 ms, and the payout CPU 700 repeatedly executes the scheduled interrupt processing about 16 times during that time. Will be. In this way, the payout CPU 700 can leave the serial transmission of the operation state command to the main control board 20 to the serial para IF chip 720 if the command is written in the transmission buffer register 740. That is, the payout CPU 700 can execute the control process without interruption even during serial transmission (a state in which the transmission buffer register 740 has an operation state command).

  FIG. 16 is a flowchart showing details of the ACK waiting process (step S860) in the command transmission process (step S80). When the payout CPU 700 (calculation processing unit 710) starts the ACK waiting process shown in FIG. 16, it determines whether or not the parallel IF unit 730 has detected an ACK signal from the main control board 20 (step S862). If an ACK signal is detected (step S862), the payout CPU 700 determines that the command has been normally transmitted to the main control board 20 (step S870), and sets the transmission job flag Fj to “0” (step S870). S880), the ACK waiting process is terminated.

  On the other hand, when the ACK signal is not detected (step S862), the payout CPU 700 determines whether or not a predetermined time has elapsed since the completion of the command writing (step S846 in FIG. 14) (step S864). . This predetermined time is a time for waiting for a response of the ACK signal from the main control board 20, and is set to 100 ms in this embodiment. When the predetermined time has not elapsed (step S864), the payout CPU 700 ends the ACK waiting process as it is, and when the predetermined time has elapsed (step S864), the payout CPU 700 supplies the main control board 20. It is determined that the command transmission is an error (step S875), the transmission job flag Fj is set to “0” (step S880), and the ACK waiting process is terminated. In the present embodiment, when the payout CPU 700 determines that the transmission of the operation state command to the main control board 20 is an error (step S875), the payout CPU 700 retransmits the operation state command that caused the transmission error.

  Incidentally, even when the main CPU 200 transmits a payout command to the payout control board 70, an ACK waiting process is executed in the same manner as described above. The main CPU 200 needs to generate a payout command when a game ball wins the winning slot 61 during the ACK waiting process. If the main CPU 200 does not receive an ACK signal for a predetermined time or more in the ACK waiting process and determines that the transmission of the payout command to the payout control board 70 is an error, the main CPU 200 replaces the payout command by resending. A confirmation command for confirming again whether or not an ACK signal is returned from the control board 70 is transmitted. This is because if the payout command is retransmitted, the payout control board 70 may pay out the prize balls for two payout commands based on the payout command transmitted twice in total. The payout control board 70 transmits an acknowledgment signal to the main control board 20 when the confirmation command is received. The payout control board 70 may transmit an operation state command when the confirmation command is received. When receiving the ACK signal, the main CPU 200 transmits the next payout command to the payout control board 70.

  Although the scheduled interrupt process in the payout CPU 700 has been described above, the scheduled interrupt process is also executed in the main CPU 200 in the same manner. In the scheduled interrupt process, an operation state command reception process and an ACK signal are transmitted. Processing, sending out a payout command, and waiting for ack.

  The operation in which the main control board 20 transmits a payout command and an ACK signal to the payout control board 70 is replaced with the arithmetic processing unit 210 instead of the payout CPU 700, the transmission buffer register 240 instead of the transmission buffer register 740, and the transmission shift. The transmission shift register 250 instead of the register 750 and the parallel IF unit 230 instead of the parallel IF unit 730 operate in the same manner as the ACK output process (step S10) and command transmission process (step S80) of the payout control board 70 described above, respectively. It is realized by doing.

  Further, the operation in which the main control board 20 receives the operation state command and the ACK signal from the payout control board 70 is replaced with the arithmetic processing unit 210 instead of the payout CPU 700, the reception shift register 260 instead of the reception shift register 760, and the reception buffer register. The reception buffer register 270 instead of 770 and the parallel IF unit 230 instead of the parallel IF unit 730 perform the same operations as the command reception process (step S40) and the ACK waiting process (step S860) of the payout control board 70 described above, respectively. Realized by doing.

  According to the pachinko machine 10 of the present embodiment described above, the ball tank 17 that stores the game balls, and the ball tank 17 that is inclined so that the game balls roll from the ball tank 17 toward the downstream side. A tank rail 18 provided below, a payout device 76 for paying out game balls supplied from the tank rail 18 as prize balls, and a guide path for an upper plate for guiding the game balls discharged from the payout device 76 16a and lower plate guiding passage 19a, a ball discharge passage 16b for discharging game balls driven into the game board 13 to the pachinko island facility, a ball discharge passage 16e, a safe ball discharge passage 16f and an out ball discharge passage 16g The main control board 20 that controls the progress of the game, and the payout control board that controls the payout of the game ball by the payout device 76 based on the payout command from the main control board 20 And a 0, a.

  The main control board 20 includes a main CPU 200 including a serial IF unit 220 that transmits a payout command serially or receives an operation state command. The payout control board 70 receives and analyzes the payout command from the serial interface IF chip 720 including the serial IF unit 722 that receives the discharge command or transmits the operation state command, and issues the payout device 76. A payout CPU 700 for performing a payout control of the serial number, a control for serially transmitting an operation state command from the serial serial IF chip 720 to the main CPU 200, an oscillator 792 for outputting an 8 MHz clock signal CLKb to the serial serial IF chip 720, And a power-on reset circuit 794 that outputs a reset signal RSTb to the IF chip 720 and the payout CPU 700.

  The serial IF chip 720 includes a frequency divider 796 that divides the frequency of the 8 MHz clock signal CLKb as a source oscillation, and a noise removal unit 790 that removes 1 μs of noise obtained from the reset signal RSTb based on the 8 MHz clock signal CLKb. And built-in. The serial interface IF chip 720 divides the 8 MHz clock signal CLKb by the frequency divider 796, sets the operation rate command to the main CPU 200 in serial, sets the transmission rate to 1200 bps, and transmits from the main CPU 200 in serial. The receiving timing of the payout command is set to 16 times the transmission rate of 1200 bps. The serial IF chip 720 is reset by the reset signal RSTb from which noise of 1 μs has been removed by the noise removing unit 790.

  As described above, when the game balls rub against each other and are charged, electrostatic discharge occurs and noise is generated. Even if the reset signal RSTb is input to the serial para IF chip 720 due to the influence of this noise, the built-in noise removal unit 790 removes the noise component from the reset signal RSTb. In this way, the payout control board 70 is arranged in the vicinity of the upper plate guide passage 16a, the lower plate guide passage 19a, the ball discharge passage 16b, the ball discharge passage 16e, the safe ball discharge passage 16f, and the out ball discharge passage 16g. Thus, even when the payout control board 70 is in an environment that is extremely affected by noise, resetting of the serial IF chip 720 due to the influence of noise can be prevented.

  The oscillator 792 outputs a clock signal CLKb to the payout CPU 700 in addition to the serial IF chip 720. This clock signal CLKb is a system clock of the payout CPU 700. As described above, the clock signal includes a frequency component (high frequency) that is an integral multiple of its own frequency. For example, when the clock signal is 8 MHz, high frequency components such as 16 MHz, 24 MHz,... Are included. Thus, in a digital circuit, the clock signal has the highest frequency and is likely to be a noise source. Therefore, the clock signal is caused by outputting the clock signal CLKb which is the system clock from the oscillator 792 to the payout CPU 700 and the serial IF chip 720, that is, by sharing the clock signal CLKb from the oscillator 792. The generated noise is reduced.

  The main control board 20 further includes an oscillator 292 that outputs a clock signal CLKa, which is a system clock of the main CPU 200, to the main CPU 200, and a power-on reset circuit 294 that outputs a reset signal RSTa to the main CPU 200. The CPU 200 has a built-in noise removing unit 290 that removes 1 μs noise obtained from an experiment from the reset signal RSTa based on the clock signal CLKa. As described above, when the game balls rub against each other and are charged, electrostatic discharge occurs and noise is generated. Even if the reset signal RSTa is input to the main CPU 200 due to the influence of the noise, the noise component is removed from the reset signal RSTa by the built-in noise removing unit 290. Thus, even when the main control board 20 is in an environment that is affected by noise, the reset of the main CPU 200 due to the influence of noise can be prevented.

  Furthermore, the payout CPU 700 has a built-in noise removing unit 712 that removes 1 μs noise obtained from an experiment from the reset signal RSTb based on the clock signal CLKb, and the reset signal from which the noise removing unit 712 has removed 1 μs noise. Reset by RSTb. As described above, when the game balls rub against each other and are charged, electrostatic discharge occurs and noise is generated. Even if the reset signal RSTb is input to the payout CPU 700 under the influence of this noise, the noise component is removed from the reset signal RSTb by the built-in noise removal unit 712. Dispensing control by disposing the dispensing control board 70 in the vicinity of the upper dish guiding path 16a, the lower dish guiding path 19a, the ball discharge path 16b, the ball discharge path 16e, the safe ball discharge path 16f, and the out ball discharge path 16g. Even when the substrate 70 is in an environment that is extremely affected by noise, it is possible to prevent the payout CPU 700 from being reset due to the influence of noise.

  It should be noted that the present invention is not limited to the above-described embodiment, and it goes without saying that the present invention can be implemented in various modes as long as it belongs to the technical scope of the present invention.

  For example, in the embodiment described above, the pachinko machine 10 has been described as an example, but the gaming machine to which the present invention can be applied is not limited to the pachinko machine, and a gaming machine other than the pachinko machine, for example, a slot machine or a pachinko machine The present invention can also be applied to a fusion game machine (which performs a slot game using a game ball) in which a slot machine is fused.

1 is a front view showing an overall configuration of a pachinko machine 10. FIG. It is a figure which shows the back surface structure of the pachinko machine. FIG. 3 is a diagram showing various guide paths for guiding game balls into the pachinko machine 10. It is a figure which shows the various discharge passages which discharge a game ball out of the pachinko machine. 2 is a block diagram showing an electrical schematic configuration of a pachinko machine 10. FIG. 4 is a block diagram showing details of an electrical configuration of a main control board 20 and a payout control board 70. FIG. 3 is a schematic configuration diagram illustrating an example of a circuit configuration of a noise removing unit 790. FIG. 6 is a timing chart showing the operation of a noise removing unit 790. 7 is a flowchart showing a payout fixed time interruption process by the payout control board 70; It is a flowchart which shows the detail of the command reception process (step S40) performed in the payment fixed time interruption process. It is a time chart which shows the mode of each signal in the payout control board 70 at the time of command reception processing (step S40) being performed. It is a flowchart which shows the detail of the ack output process (step S10) performed in the payment fixed time interruption process. It is a flowchart which shows the detail of the command transmission process (step S80) performed in a payment fixed time interruption process. It is a flowchart which shows the detail of the command output process (step S820) in a command transmission process (step S80). It is a time chart which shows the mode of each signal in the payout control board 70 at the time of command output processing (step S820) being performed. It is a flowchart which shows the detail of the ACK waiting process (step S860) in a command transmission process (step S80).

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Pachinko machine (game machine), 11 ... Outer frame, 12 ... Inner frame, 13 ... Game board, 14 ... Glass frame, 15 ... Handle, 16 ... Upper plate, 16a ... Guidance passage (guide passage) for upper plate, 16b: Ball removal discharge passage (discharge passage), 16e ... Ball removal discharge passage (discharge passage), 16f ... Safe ball discharge passage (discharge passage), 16g ... Out ball discharge passage (discharge passage), 17 ... Ball tank (ball Tank), 18 ... tank rail (tank rail), 19 ... lower plate, 19a ... lower plate guide passage (guide passage), 20 ... main control board (main control board), 30 ... design control board, 35 ... LCD, 40 ... Sub control board, 45 ... Speaker, 55, 56, 57, 58, 59 ... Electric decoration, 61 ... Winning opening, 65 ... Game ball sensor, 66 ... Game board drive unit, 70 ... Payout control board (Payout control board) , 72 ... Status display section, 75 ... Dispensing drive , 76 ... Dispensing device (dispensing device), 90 ... Card unit, 200 ... Main CPU (main control central processing unit), 210 ... Arithmetic processing unit, 220 ... Serial IF unit (main control serial interface unit), 230 ... Parallel IF unit, 240 ... transmission buffer register, 250 ... transmission shift register, 260 ... reception shift register, 270 ... reception buffer register, 280 ... serial management unit, 290 ... noise removal unit, 292 ... oscillator (main control oscillator), 294 ... Power-on reset circuit (main control power-on reset circuit), 296 ... frequency divider, 700 ... payout CPU (payout control central processing unit), 710 ... arithmetic processing unit, 712 ... noise removal unit, 720 ... serial para IF chip ( Interface device), 722 ... Serial IF unit (dispensing control serial interface) 730 ... transmission buffer register, 750 ... transmission shift register, 760 ... reception shift register, 770 ... reception buffer register, 780 ... serial management unit, 790 ... noise Removal unit, 792... Oscillator (payout control oscillator), 794... Power-on reset circuit (payout control power-on reset circuit), 796... Divider (divider), CBb... Set signal, CLKa. Clock signal), CLKb ... clock signal (payout control clock signal), RSTa ... reset signal (main control reset signal), RSTb ... reset signal (payout control reset signal), Fa ... acck flag, Fj ... job flag, Dab ... serial data , Dba ... serial data, Lbs ... Transmission register delivery period, Lsc... Serial transmission period, Lwa.

Claims (1)

A ball tank for storing game balls;
A tank rail provided below the ball tank in an inclined state so that the game ball rolls downstream from the ball tank;
A payout device for paying out the game balls supplied from the tank rail as prize balls;
A guide passage for guiding a game ball paid out from the payout device;
A discharge passage for discharging game balls driven into the game board to the outside of the gaming machine;
A main control board for controlling the progress of the game;
A payout control board for performing payout control of game balls by the payout device based on a command from the main control board;
A gaming machine comprising
The main control board is:
A main control central processing unit having a main control serial interface unit for serially transmitting and receiving the command;
The payout control board is:
An interface device incorporating a payout control serial interface unit for serially transmitting and receiving the command;
A payout control center that performs control of reading out the command from the interface device and performing payout control of the payout device, while transmitting a command different from the command from the interface device to the main control central processing unit. An arithmetic processing unit;
A payout control oscillator for outputting a payout control clock signal to the interface device;
A payout control power-on reset circuit that outputs a payout control reset signal to the interface device and the payout control central processing unit;
With
The interface device
An interface divider that divides the payout control clock signal by a predetermined division ratio as a source oscillation;
An interface noise removing unit for removing a predetermined band frequency component from the payout control reset signal based on the payout control clock signal;
Receiving timing at which the payout control serial interface unit receives the command that is serially transmitted from the main control central processing unit, and divides the payout control clock signal by the interface divider. A transmission rate for serially transmitting a command different from the command to the main control central processing unit from the payout control serial interface unit is set, while the predetermined band frequency component is removed by the interface noise removing unit. The game machine is reset by a payout control reset signal.

Images