JP2007215645A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique to reduce burden on a main control board while improving the reliability of a put-out command. <P>SOLUTION: The main control board 70 splits a 2-byte put out command into 1-byte units and serially sends them to a putting-out control board 20. The putting-out CPU 710 of the putting-out control board 70 judges whether or not the put-out command is normally received in a time interruption process. When judging that the command is normally received, the CPU parallelly sends an ACK (acknowledgment) signal to the main control board 20. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to communication between a main control board that controls the progress of a game and a payout control board that controls the payout of a game ball or a game medal in a gaming machine.

In a gaming machine, a payout command relating to payout of a game ball or the like is transmitted from a main control board that controls the progress of the game to a payout control board that controls payout of game balls or game medals. A person who intends to cause a gaming machine to perform an illegal act to pay out a game ball, etc., by illegally processing the signal line to which the payout command is transmitted and changing the payout command, There are times when you want to pay out the ball. Conventionally, a payout command is transmitted in parallel from the main control board to the payout control board. In parallel, for example, an 8-bit payout command is transmitted at the same time. Therefore, compared to serial communication in which data is transmitted bit by bit at a predetermined timing, there is a high possibility that an unauthorized person changes the payout command. Therefore, in order to improve the reliability of communication from the main control board to the payout control board and to prevent illegal play balls etc. from being paid out, communication from the main control board to the payout control board can be performed serially. Proposed.

By the way, in gaming machines, static electricity often occurs due to friction between gaming balls and the passage thereof, friction between gaming balls, contact between gaming machines and a charged human body, or the like. When the payout command is transmitted serially in consideration of the fact that the payout command is misunderstood due to the influence of electrical noise caused by the occurrence of static electricity, the transmission speed of the payout command is reduced. Thereby, the reliability of the payout command transmitted from the main control board to the payout control board is improved. The transmission speed of the payout command is, for example, 1200 bps (Bit Per Second). If the transmission speed is 1200 bps, the time required to transmit a 2-byte command is about 16.7 ms.

Furthermore, in order to improve the reliability of communication from the main control board to the payout control board, a technique has been proposed in which the payout control board that has received the payout command notifies the main control board that the payout command has been received. (For example, patent document 1). After the main control board transmits the payout command, the payout control board receives the payout command by receiving a confirmation signal (ACK signal, ACK signal) indicating that the payout command has been received from the payout control board. Can be confirmed.

JP 2003-190615 A

As described above, in order to improve the reliability of the payout command sent from the main control board to the payout control board, the payout command is sent serially, the payout command transmission speed is reduced, and the ACK signal is sent and received. It is. However, for this reason, as described above, the processing speed related to the transmission / reception of the payout command is low. In particular, if the main control board does not receive an ACK signal from the payout control board, the reliability of communication with the payout control board is doubtful, and therefore the next payout command is not transmitted to the payout control board. Therefore, while the ACK signal is not received, the payout command to be transmitted to the payout control board is stored in the main control board, which is a burden on the main control board. In addition to the main control board, in order to control the progress of the game, it is necessary to execute a number of processes corresponding to state changes that occur irregularly. For example, when a game ball enters the start winning opening, the main control board acquires a random number and performs a lottery, or stores the acquired random number if it is changing when the game ball enters the start winning opening. There are a number of processes that need to be executed. On the other hand, the payout control board mainly performs processing for paying out game balls and the like in accordance with payout commands. Therefore, in order to reduce the burden on the main control board, it is desirable to send the payout command to the payout control board at an early stage.

  The present invention has been made to solve the above-described problems, and an object thereof is to provide a technique for reducing the burden on the main control board while improving the reliability of the payout command.

In order to solve the above-described problems, a gaming machine of the present invention includes a main control board that controls the progress of a game,
A payout control board that controls payout of game balls or game medals based on payout commands that are commands related to payout of game balls or game medals transmitted from the main control board;
The main control board includes: a main control board serial transmission unit that serially transmits a command to the payout control board at a low communication speed not affected by electrical noise; and a general-purpose parallel in the main control board A main control board parallel reception port, which is a part of the ports, and the payout control board is a serial command at a low communication speed not affected by electrical noise from the main control board. The payout control board serial reception unit for receiving the payout control board, the payout control board parallel transmission port which is a part of the general-purpose parallel port in the payout control board, and the process related to the payout by repeatedly executing the interrupt processing for a predetermined time. A payout control board central processing unit for performing, and the payout command is sent from the main control board serial transmission unit When the payout control board central processing unit determines that the payout command has been received normally, the payout control board serial reception unit sends a payout command confirmation signal to the payout control board parallel transmission port. The payout command confirmation signal is transmitted in parallel from the payout control board parallel transmission port to the main control board parallel reception port.

According to the present invention, since the payout command confirmation signal (ACK signal) is transmitted in parallel, the ACK signal can be transmitted to the main control board earlier than in the case of serial transmission. If the main control board can receive the ACK signal early, the next payout command can be transmitted to the payout control board, so the burden on the main control board can be reduced. That is, according to the present invention, it is possible to reduce the burden on the main control board while improving the reliability of the payout command.

The main control board includes: a main control board serial receiving unit that receives commands serially from the payout control board at a low communication speed that is not affected by electrical noise; and a general-purpose parallel port in the main control board A main control board parallel transmission port that is a part of the main control board, and a main control board central processing unit that repeatedly executes a fixed-time interrupt process to control the progress of the game, and the payout control The board includes a payout control board serial transmission unit that serially transmits a command to the main control board at a low communication speed that is not affected by electrical noise, and a part of the general-purpose parallel port in the payout control board A payout control board parallel receiving port that is a port of the payout control board, and the payout control board central processing unit is a gaming machine. The operation state command that is a command indicating the operation state is output via the payout control board serial transmission unit, and the operation state command is output from the payout control board serial transmission unit. When the main control board central processing unit determines that the operation state command has been normally received, the operation state command confirmation signal is sent in parallel to the main control board parallel transmission. The operation state command confirmation signal may be output via a port and transmitted in parallel from the main control board parallel transmission port to the payout control board parallel reception port.

According to this, since the operation state command is transmitted from the payout control board to the main control board at a low communication speed that is not affected by electrical noise, the reliability of the operation state command can also be improved. The operation state command confirmation signal (ACK signal) is transmitted in parallel. Since the transmission / reception is performed in two systems, serial and parallel, the reliability of transmission / reception can be improved.

The payout control board serial receiving unit and the general-purpose parallel port in the payout control board may be integrated on one chip.

According to this, since these components are integrated on one chip, the space on the payout control board can be saved.

Note that the gaming machine of the present invention may be a pachinko machine or a slot machine, and the present invention can be applied to various modes such as a control method for controlling the gaming machine and a program for controlling the gaming machine.

In order to further clarify the configuration and operation of the present invention described above, a gaming machine to which the present invention is applied will be described below. In the present specification, a signal name prefixed with “#” means negative logic. “High level” means the “1” level of the two levels of the binary signal, and “Low level” means the “0” level.

A. Configuration of Pachinko Machine 10: The configuration of the pachinko machine 10 that is one embodiment of the present invention will be described. FIG. 1 is a front view showing the overall configuration of the pachinko machine 10. As shown in FIG. 1, a pachinko machine 10 has an outer frame 11 fixed to a so-called island of a pachinko store, an inner frame 12 fitted into the outer frame 11, an upper center of the inner frame 12, and a game by a game ball is played. A game board 13 to be performed, a glass frame 14 disposed on the front surface of the game board 13 and having a glass plate at the center, a handle 15 for receiving an operation by a player for launching a game ball on the game board 13, and the back surface of the pachinko machine 10 A ball tank 17 for storing game balls for payout, a lower plate 19 for storing game balls paid out to the player, a card unit 90 for accepting lending of game balls by a prepaid card, and the like.

A liquid crystal display (hereinafter referred to as LCD) 35 is provided at the center of the game board 13, and a winning opening 61 for receiving a winning game ball is provided below the LCD 35. The winning opening 61 includes a game ball sensor 65 that detects a winning game ball, and a game board drive unit 66 that expands and contracts the introduction path of the game ball in a predetermined case. The pachinko machine 10 includes electrical decorations 55, 56, 57, 58, 59 having light emitting diodes (LEDs). The electrical decorations 55 and 56 are provided on the left and right ends of the game board 13, the electrical decoration 57 is provided on the upper part of the LCD 35, and the electrical decorations 58 and 59 are provided on the left and right of the upper part of the glass frame 14, respectively. A speaker 45 for outputting sound is built in the front center of the inner frame 12.

FIG. 2 is a block diagram showing an electrical schematic configuration of the pachinko machine 10. The pachinko machine 10 includes a main control board 20 that controls the progress of the game, a payout control board 70 that controls the payout of the game ball based on a command from the main control board 20, an LCD 35, a speaker 45, A sub-control board 40 that controls the effect using the electric decorations 55 to 59 and a symbol control board 30 that controls the moving image display on the LCD 35 are provided. The payout control board 70 is connected to a payout drive unit 75 that executes payout of game balls, and a state display unit 72 that displays a state relating to payout of game balls to the outside by LEDs. Each of these substrates, the payout drive unit 75, and the state display unit 72 are provided on the back surface (not shown) of the inner frame 12 shown in FIG.

Each of the main control board 20, the payout control board 70, the sub control board 40, and the symbol control board 30 includes a central processing unit (Central Processing Unit, hereinafter referred to as a CPU) for performing various arithmetic processes, and a CPU. Read-only memory (hereinafter referred to as ROM) that pre-stores a program that prescribes arithmetic processing, random access memory (hereinafter referred to as RAM) that temporarily stores data handled by the CPU, etc. A circuit board on which electronic components corresponding to each board are mounted.

Various commands are transmitted serially between the main control board 20 and the payout control board 70. Commands between the main control board 20 and the payout control board 70 are configured in units of 2 bytes, and are transmitted serially after being divided into units of 1 byte. The board that has received the command normally transmits an ACK (acknowledge) signal, which is a confirmation signal indicating that the command has been received normally, to the board that has transmitted the command. Details of command transmission / reception between the main control board 20 and the payout control board 70 will be described later.

Various commands are transmitted in parallel from the main control board 20 to the sub control board 40 and from the sub control board 40 to the symbol control board 30, respectively. As main commands from the main control board 20 to the sub-control board 40, there are commands for instructing basic effects relating to games such as so-called “big hit” and “out of game”. A main command from the sub control board 40 to the symbol control board 30 is a command for instructing a display mode of a moving image on the LCD 35 based on a command from the main control board 20.

FIG. 3 is a block diagram showing details of the electrical configuration of the main control board 20 and the payout control board 70. The main control board 20 includes a main CPU 200 having a serial communication function and a parallel communication function with the outside as a CPU for performing various arithmetic processes in the main control board 20. The main CPU 200 is configured with an arithmetic processing unit 210 that performs arithmetic processing, a serial IF unit 220 that performs serial communication with the outside, and a parallel IF unit 230 that performs parallel communication with the outside. The parallel IF unit 230 corresponds to the general-purpose parallel port in the present invention.

The serial IF unit 220 receives and stores the parallel data TDa from the arithmetic processing unit 210, receives the data stored in the transmission buffer register 240, converts it into serial data Dab, and transmits it serially to the payout control board 70. The transmission shift register 250, the reception shift register 260 that receives and stores the serial data Dba from the payout control board 70, and the data that is stored in the reception shift register 260 is received and stored as parallel data RDa by the arithmetic processing unit 210. A reception buffer register 270 and a serial management unit 280 for managing the operation state of each unit in the serial IF unit 220 are provided. The constituent circuits of the serial IF unit 220 are integrated on one chip. The transmission buffer register 240, the transmission shift register 250, the reception shift register 260, and the reception buffer register 270 are registers each having a storage capacity of 1 byte. The transmission buffer register 240, the transmission shift register 250, and the serial management unit 280 correspond to the main control board serial transmission unit of the present invention. The reception shift register 260, the reception buffer register 270, and the serial management unit 280 correspond to the main control board serial reception unit of the present invention.

The serial management unit 280 allows the transmission shift register 250 and the transmission buffer register 240 to transfer data from the transmission buffer register 240 to the transmission shift register 250 when the transmission shift register 250 is not performing serial transmission. After being passed, the circuit is configured to erase data from the transmission buffer register 240.

The serial management unit 280 permits the data transfer from the reception shift register 260 to the reception buffer register 270 when the data is not stored in the reception buffer register 270 with respect to the reception shift register 260 and the reception buffer register 270. The processing unit 210 is configured to erase data from the reception buffer register 270 after reading the parallel data RDa from the reception buffer register 270.

Note that the serial transmission rate by the serial IF unit 220 is determined based on a signal obtained by dividing the clock signal for operating the main CPU 200. The frequency division ratio of the clock signal that determines the transmission rate can be set by the value of a register (not shown) built in the serial IF unit 220.

The arithmetic processing unit 210 writes the parallel data TDa to the transmission buffer register 240 by lowering the write signal #WRa to the transmission buffer register 240, and sets the read signal #REa to the reception buffer register 270. By lowering, the parallel data RDa is read from the reception buffer register 270.

The arithmetic processing unit 210 receives signals indicating various states in the serial IF unit 220 from the serial management unit 280. Signals that the arithmetic processing unit 210 receives from the serial management unit 280 include a transmission buffer empty signal TEa that is set to a high level when the transmission buffer register 240 is cleared, and a transmission shift register 250 that is transmitting serially. There is a serial transmission signal TCa that is set to a high level, and a reception data presence signal DFa that is set to a high level when data is stored in the reception buffer register 270.

As shown in FIG. 3, the payout control board 70 includes a payout CPU 710 that performs various arithmetic processes in the payout control board 70, and a serial para IF chip 720 in which a circuit that performs serial communication and parallel communication with the outside is formed. .

The serial interface IF chip 720 receives and stores the parallel data TDb from the payout CPU 710, and receives the data stored in the transmission buffer register 740, converts the data stored in the transmission buffer register 740 into serial data Dba, and transmits the serial data to the main control board 20 A shift register 750, a reception shift register 760 that receives and stores the serial data Dab from the main control board 20, and a reception buffer register 770 that receives and stores the data stored in the reception shift register 760 so as to be readable as parallel data RDb. A serial management unit 780 that manages the operation state of each unit in the serial para IF chip 720, and a parallel IF unit 730 that performs parallel communication with the outside. Road are integrated into one chip. The transmission buffer register 740, the transmission shift register 750, the reception shift register 760, and the reception buffer register 770 are registers each having a storage capacity of 1 byte. The transmission buffer register 740, the transmission shift register 750, and the serial management unit 780 correspond to the payout control board serial transmission unit of the present invention. The reception shift register 760, the reception buffer register 770, and the serial management unit 780 correspond to the payout control board serial reception unit of the present invention. The parallel IF unit 730 corresponds to the general-purpose parallel port in the present invention.

The serial management unit 780 includes a clear register 782 that is set in response to the set signal CBb output from the payout CPU 710 to clear the reception buffer register 770. When the clear register 782 is set, the serial manager 780 erases data from the reception buffer register 770 and resets the clear register 782 in response to the data being cleared from the reception buffer register 770. It is configured. The serial management unit 780 is also configured to allow data transfer from the reception shift register 760 to the reception buffer register 770 when no data is stored in the reception buffer register 770.

The serial management unit 780 allows the transmission shift register 750 and the transmission buffer register 740 to transfer data from the transmission buffer register 740 to the transmission shift register 750 when the transmission shift register 750 is not transmitting serially. The circuit is configured to erase the data from the transmission buffer register 740 after being passed.

Note that the timing at which the serially-transmitted IF chip 720 samples the serially transmitted command is based on a sampling clock obtained by frequency-dividing a clock signal for operating the main CPU 200 of the main control board 20 by a frequency dividing circuit (not shown). It is determined. The frequency division ratio from the clock signal that determines the sampling clock is to change the value of a register (not shown) built in the serial para IF chip 720 when the frequency dividing circuit is built in the serial para IF chip 720. It may be configured to be settable by

The payout CPU 710 writes the parallel data TDb to the transmission buffer register 740 by lowering the write signal #WRb to the transmission buffer register 740, and lowers the read signal #REb to the reception buffer register 770. As a result, the parallel data RDb is read from the reception buffer register 770.

The payout CPU 710 receives signals indicating various states in the serial para IF chip 720 from the serial management unit 780. The payout CPU 710 receives a signal from the serial management unit 780 as a transmission buffer empty signal TEb that is set to a high level when the transmission buffer register 740 is cleared, and a high signal when the transmission shift register 750 is transmitting serially. There is a serial transmission signal TCb that is set to the level and a reception data presence signal DFb that is set to the high level when data is stored in the reception buffer register 770.

The command transmitted from the main control board 20 to the payout control board 70 is a payout command relating to payout of game balls. The payout command is, for example, a command for designating the number of game balls to be paid out, and is a multi-bit command. The payout command is serially transmitted from the transmission shift register 250 to the reception shift register 760. If the payout CPU 710 determines that the payout command has been received normally, the payout CPU 710 transmits an ACK signal to the main control board 20. The ACK signal is transmitted from the parallel IF unit 730 to the parallel IF unit 230 in parallel. Although not shown, the parallel IF unit 730 and the parallel IF unit 230 are provided with a plurality of parallel ports. The ACK signal is a 1-bit signal, and is transmitted and received between the parallel IF unit 730 and the parallel IF unit 230 using a 1-bit port among a plurality of parallel ports. The 1-bit port corresponds to the payout control board parallel transmission port and the main control board parallel reception port in the present invention.

  The command that the payout control board 70 transmits to the main control board 20 is an operation state command for notifying the main control board 20 of the operation state of the pachinko machine 10 detected by the payout CPU 710. The payout command is a multi-bit command, and the operation state command includes, for example, ball break information indicating that there are not enough game balls in the prize ball unit, and that the card unit 90 is not connected to the pachinko machine 10. And information indicating that the command cannot be normally transmitted and received between the main control board 20 and the payout control board 70. The operation state command is serially transmitted from the transmission shift register 750 to the reception shift register 260. When the main CPU 200 determines that the operation state command has been normally received, the main CPU 200 transmits an ACK signal to the payout control board 70. The ACK signal is a 1-bit signal, and is transmitted / received between the parallel IF unit 230 and the parallel IF unit 730 using a 1-bit port among a plurality of parallel ports. The 1-bit port corresponds to the main control board parallel transmission port and the payout control board parallel reception port in the present invention.

B. Operation of pachinko machine 10: B-1. Dispensing scheduled interrupt processing by the dispensing control board 70: As one operation of the pachinko machine 10, the dispensing scheduled interrupt processing in the dispensing control board 70 will be described. FIG. 4 is a flowchart showing a payout fixed time interruption process by the payout control board 70. The payout interruption processing is repeatedly executed by the payout CPU 710 of the payout control board 70 at a predetermined interval (in this embodiment, 1 millisecond (hereinafter referred to as ms)).

The payout CPU 710 of the payout control board 70 executes various processes in the payout scheduled interrupt process. In this embodiment, the payout CPU 710 includes an ack output process (step S10), a CR communication process (step S20), a full / ball check process (step S30), a command reception process (step S40), and a command analysis process (step). S50), a payout process (step S60), a status display process (step S70), and a command transmission process (step S80) are executed in this order. Each process (steps S10 to S80) in the payout scheduled interrupt process varies depending on the progress of the game, so the time required for completion varies depending on the progress of the game. The process of the ACK output process (step S10) in the payout scheduled interrupt process has priority over the processes of the other processes (steps S20 to S80). In this embodiment, the process of the ACK output process (step S10) is a payout scheduled interrupt. It is executed at the beginning of the process.

The ACK output process (step S10) is a process for outputting an ACK signal to the main control board 20 when a command is normally received from the main control board 20. Details of the ACK output process (step S10) will be described later.

The CR communication process (step S20) is a process for exchanging data related to the rental of game balls with the card unit 90. In the full tank / out of ball check process (step S30), it is confirmed whether the game balls stored in the lower plate 19 are full or the game balls stored in the ball tank 17 are not empty. By doing so, it is a process for detecting a physical state which becomes an obstacle to payout of the game ball.

The command reception process (step S40) is a process for receiving a payout command transmitted serially from the main control board 20 in units of 1 byte. Details of the command reception process (step S40) will be described later. The command analysis process (step S50) is a process for analyzing the contents of the payout command received in the command reception process (step S40). Specifically, in the command analysis process (step S50), it is determined whether or not the number of payouts indicated by the payout command is within a normal value range (for example, 1 to 15). Assuming that game balls are not paid out, the payout command is ignored. If the payout number is within the normal value range, the payout number indicated by the payout command is added to the total payout number stored in the payout number buffer. The payout number buffer is a buffer for storing the total number of game balls to be paid out by the pachinko machine 10.

The payout process (step S60) is a process for executing payout of game balls. In the payout process (step S60), the payout CPU 710 instructs the payout drive unit 75 to operate in accordance with the lending instruction obtained in the CR communication process (step S20) and the contents of the payout number buffer. The signal is output. In this embodiment, when there is an abnormal change in the number of game balls requested to be paid out from the card unit 90 or the main control board 20, there is a physical failure in the full / ball check process (step S30). Is confirmed, the payout CPU 710 temporarily stops paying out the game balls.

The state display process (step S70) is a process for displaying the operation state of the pachinko machine 10 detected by the payout CPU 710 on the state display unit 72. In the present embodiment, the display of the operation state in the state display unit 72 is performed by displaying numbers corresponding to each state. For example, an abnormality occurs in the transmission / reception of commands between the main control board 20 and the payout control board 70. In this case, “0” is displayed on the state display unit 72, and “1” is displayed on the state display unit 72 when a ball break occurs in the ball tank 17, and the card unit 90 is connected to the payout control board 70. If not, “7” is displayed in the status display section 72.

The command transmission process (step S80) is a process for transmitting an operation state command in units of 2 bytes from the payout control board 70 to the main control board 20 in units of 1 byte. Details of the command transmission process will be described later.

B-2. Command Receiving Process in Payout Scheduled Interrupt Process: FIG. 5 is a flowchart showing details of the command receiving process (step S40) executed in the payout scheduled interrupt process. As described above, the command reception process (step S40) is one of various processes in the payout scheduled interrupt process shown in FIG. 4, and is executed by the payout CPU 710 of the payout control board 70. The command reception process is a process for receiving a payout command transmitted serially from the main control board 20.

When the payout CPU 710 starts the command receiving process shown in FIG. 5, it is “whether the received data present signal DFb is at a high level”, that is, “when data is stored in the receiving buffer register 770”. Whether or not (step S410). Here, when it is determined in the command reception process that “the received data present signal DFb is at the high level” (step S410), the 2-byte payout transmitted from the main control board 20 to the payout control board 70. In the command, the first byte is stored in the reception buffer register 770.

If “the received data present signal DFb is at the high level” (step S410), the payout CPU 710 reads the first byte of the payout command stored in the reception buffer register 770 (step S412), and then receives it again. The first byte of the payout command stored in the buffer register 770 is read (step S414). Thereafter, the payout CPU 710 compares the first byte of the payout command read out the first time with the first byte of the payout command read out the second time (step S416), and determines whether or not they match. (Step S418).

If the first byte of the read out payout command matches the first time and the second time (step S418), the payout CPU 710 outputs a set signal to the clear register 782 of the serial para IF chip 720, and the bit of the clear register 782 Is set (step S420). By setting the clear register 782, the serial management unit 780 of the serial para IF chip 720 clears the first byte of the payout command stored in the reception buffer register 770, and the payout command stored in the reception shift register 760. The second byte is transferred to the reception buffer register 770. Thereafter, the clear register 782 is automatically reset.

After setting the clear register 782 (step S420), the payout CPU 710 verifies the second byte of the payout command stored in the reception buffer register 770 after two readings in the same manner as the first byte of the payout command. (Steps S422, S424, S426) If the first time and the second time match (Step S428), the set signal CBb is output to the clear register 782 of the serial para IF chip 720, and the bit of the clear register 782 is set. Set (step S430). As a result, the serial management unit 780 of the serial interface IF chip 720 clears the second byte of the payout command stored in the reception buffer register 770.

The payout CPU 710, after setting the clear register 782 (step S430), collates the first byte of the read payout command with the second byte of the read command (step S440) and determines whether or not they match. Is determined (step S445). In this embodiment, the second byte of the payout command is data generated by inverting each bit of the first byte of the payout command on the main control board 20. If the first byte and the second byte of the read out payout command match (step S445), the payout CPU 710 sets an ACK flag Fa for transmitting an ACK signal to the main control board 20 (step S450). ), The command transmission process is terminated. The ack flag Fa is data used in the ack output process (step S10) described above and stored in a register or RAM (not shown) built in the payout CPU 710. The ack flag Fa is set to “0” when the payout CPU 710 is activated.

On the other hand, when the first byte or the second byte of the read out payout command does not match between the first time and the second time (steps S418 and S428), the payout CPU 710 receives the reception shift register 760 and the reception in preparation for the next command reception. In order to clear the payout command stored in the buffer register 770, after setting the bit of the clear register 782 (steps S492 and S494), the command transmission process is terminated. In addition, even when the first byte and the second byte of the read command do not match (step S445), the payout CPU 710 ends the command transmission process without setting the ack flag Fa. As a result, when the payout command is not normal, the ACK signal is not output to the main control board 20, and the main control board 20 determines that an abnormality has occurred in the transmission of the payout command because the ACK signal is not returned. Can do.

FIG. 6 is a time chart showing the state of each signal on the payout control board 70 when the command receiving process (step S40) is executed. For convenience of explanation, in FIG. 6, the scale of the serial transmission time of the first byte and the second byte of the payout command is reduced compared to the scale of the calculation processing time of the payout CPU 710.

In the command reception process shown in FIG. 5, if it is determined that “the reception data present signal DFb is at the high level” due to the fall of the read signal #REb (step S410 in FIG. 5), the reception buffer register 770. The first byte of the payout command is output to the parallel data RDb, and the first byte of the payout command is read from the reception buffer register 770 by the payout CPU 710 (timing tb11 to tb12, step S412 in FIG. 5). Thereafter, the first byte of the payout command is further read in the same manner as the first time (timing tb13 to tb14, step S414 in FIG. 5).

After the second reading of the first byte of the payout command is completed, the reception buffer register 770 is cleared according to the setting of the clear register 782, and the reception data present signal DFb becomes low level (timing tb15, in FIG. 5). Step S420). Thereafter, when the second byte of the payout command is transferred from the reception shift register 760 to the reception buffer register 770, the reception data presence signal DFb becomes high level (timing tb16).

Thereafter, the second byte of the payout command is read from the reception buffer register 770 in the same manner as the first byte of the command (timing tb21 to tb24, steps S422 and S424 in FIG. 5). After the reading of the second byte of the payout command is completed, the reception buffer register 770 is cleared according to the setting of the clear register 782, and the reception data presence signal DFb becomes low level (timing tb25, step S430 in FIG. 5). .

In this embodiment, the sampling timing of the serial IF chip 720 is set to 19.2 kilohertz (kHz), which is 16 times the transmission rate (1200 bps). In this embodiment, the serial para IF chip 720 performs sampling three times for each of the start bit ST, the data bits D0 to D7 of the payout command, and the stop bit SP, and is detected by the three samplings. Determine the majority value. As a result, the reliability of the payout command reception is improved.

B-3. Ac output process in payout scheduled interrupt process: FIG. 7 is a flowchart showing details of an ack output process (step S10) executed in the payout scheduled interrupt process. As described above, the ACK output process (step S10) is one of various processes in the payout scheduled interrupt process shown in FIG. 4, and is executed by the payout CPU 710 of the payout control board 70.

The payout CPU 710 starts the ACK output process (step S10) shown in FIG. 7. If the ACK flag Fa is set (step S110), the payout CPU 710 sends the ACK signal via the parallel IF unit 730 of the serial IF chip 720. Output to the main control board 20 (step S120). Thereafter, the payout CPU 710 resets the ack flag Fa (step S130), and ends the ack output process. If the ack flag Fa is not set (step S110), the payout CPU 710 ends the ack output process without outputting an ack signal.

The case where the ACK flag Fa is set means that the ACK flag Fa is set when the payout command is normally received in the command reception process (step S40) shown in FIG. 5 (step S450 in FIG. 5). It is. As shown in FIG. 4, in the scheduled interrupt process, the ACK output process (step S10) is executed prior to the command reception process (step S40), so the ACK flag Fa is set. In this case, an ACK signal is output in the ACK output process (step S10) in the next scheduled interrupt process.

B-4. Command Sending Process in Payout Scheduled Interrupt Process: FIG. 8 is a flowchart showing details of the command sending process (step S80) executed in the payout scheduled interrupt process. As described above, the command transmission process (step S80) is one of various processes in the payout scheduled interrupt process shown in FIG. 4, and is executed by the payout CPU 710 of the payout control board 70. The command transmission process is a process for serially transmitting an operation state command to the main control board 20.

The payout CPU 710, when starting the command transmission process shown in FIG. 8, determines the value of the transmission job flag Fj (step S810). The transmission job flag Fj is a flag indicating a state in the command transmission processing, and is set to “0” when the payout CPU 710 is activated, and is data stored in a register or RAM (not shown) built in the payout CPU 710. .

In the case of “transmission job flag Fj = 0”, the payout CPU 710 executes a command preparation process (step S815) for preparing an operation state command to be transmitted to the main control board 20. In the command preparation process, when the payout CPU 710 determines that it is necessary to transmit an operation state command based on signals from each sensor input to the plurality of ports of the serial para IF chip 720, the payout CPU 710 is based on the signal from the sensor. To generate the first byte of the operation state command. Then, after setting the transmission job flag Fj to “1”, the command preparation process (step S815) is terminated.

In the case of “transmission job flag Fj = 1”, the payout CPU 710 executes a command output process for outputting an operation state command in units of 2 bytes to the main control board 20 (step S820). When the flag Fj = 2 ”, an ACK waiting process for confirming an ACK signal from the main control board 20 is executed (step S860). The payout CPU 710 ends the command preparation process (step S815), the command output process (step S820), and the ACK waiting process (step S860), and then ends the command transmission process (step S80). Details of the command output process (step S820) and the ACK waiting process (step S860) will be described later.

FIG. 9 is a flowchart showing details of command output processing (step S820) in command transmission processing (step S80). When the payout CPU 710 starts the command output process (step S820) shown in FIG. 9, it is determined whether or not “the transmission buffer empty signal TEb is at the high level” and “the serial transmission signal TCb is at the low level”. It is determined whether or not “when no data is stored in the buffer register 740” and “when the transmission shift register 750 is not performing serial transmission” (step S822). When “transmission buffer empty signal TEb is high level” and “serial transmission signal TCb is low level” (step S822), payout CPU 710 inverts each bit of the first byte of the operation state command, That is, among the bits of the first byte, the bit that is “0” is set to “1”, the bit that is “1” is set to “0”, and the second byte that is the remaining lower 1 byte of the operation state command is generated. (Step S834). In this embodiment, the first byte of the operation state command is data having a substantial meaning as the operation state command, and the second byte of the operation state command is the correctness of the operation state command on the main control board 20 side. This is data for judgment.

Then, after generating the second byte of the operation state command (step S834), the first byte of the operation state command is written into the transmission buffer register 740 (step S842). Thereafter, after waiting for a preset write standby period Lwa (step S844), the second byte of the generated operation state command is written to the transmission buffer register 740 (step S846). The payout CPU 710 outputs the operation state command (step S846), sets the transmission job flag Fj to “2” (step 850), and ends the command output process.

Here, the write standby period Lwa is a transmission register delivery period that is a period from the writing of the first byte of the operation state command to the transmission buffer register 740 to the delivery of the first byte to the transmission shift register 750. This is a period longer than Lbs, and is a period in which sufficient time is allowed to execute the second byte write process (step S846 in FIG. 9) until the end of the scheduled interrupt process, and until the start of the next scheduled interrupt process. It is not a long period. The write standby period Lwa is shorter than the serial transmission period Lsc that is a period until the serial transmission of the first byte of the operation state command is completed, and is shorter than 1 ms that is the interval of the scheduled interrupt processing. It is a short period. In this embodiment, the write standby period Lwa is set to 2.5 microseconds. The transmission register delivery period Lbs according to the hardware specifications of the serial para IF chip 720 of this embodiment is about 1.25 microseconds. If the calculation processing time of the payout CPU 710 required for the second byte write process (step S846 in FIG. 9) is equal to or longer than the transmission register delivery period Lbs of the serial IF chip 720, the command wait process shown in FIG. The standby process (step S844) by the software is unnecessary.

FIG. 10 is a time chart showing the state of each signal on the payout control board 70 when the command output process (step S820) is executed. In the command output process shown in FIG. 9, it is determined that “the transmission buffer empty signal TEb is at the high level” and “the serial transmission signal TCb is at the low level” (step S822 in FIG. 9). When writing is executed (step S842 in FIG. 9), output of the first byte of the operation state command to the parallel data TDb is started (timing ta1), and then transmitted by the falling edge of the write signal #WRb. The first byte of the motion a state command is written to the buffer register 740 (timing ta2).

The transmission buffer register 740 delivers the first byte of the written operation state command to the transmission shift register 750, and is cleared by the serial management unit 780 when the delivery is completed. The transmission shift register 750 outputs the first byte of the operation state command received from the transmission buffer register 740 to the serial data Dba. In the serial data Dba during serial transmission, each bit from the first bit D0 to the eighth bit D7 of the command follows the start bit ST, and finally the stop bit SP is output. In this way, when serial transmission of the first byte of the operation state command is started, the serial transmission in-progress signal TCb becomes high level (timing ta3).

After writing the first byte of the operation state command (timing ta2, step S842 in FIG. 9) and after waiting for the write standby period Lwa (step S844 in FIG. 9), the same as the first byte of the operation state command Then, the second byte of the operation state command is written into the transmission buffer register 740 (timing ta4, step S846 in FIG. 9). At this time, the transmission shift register 750 is serially transmitting the first byte of the operation state command and cannot receive the second byte of the operation state command from the transmission buffer register 740. The second byte of the received operation state command is stored and held, and the transmission buffer empty signal TEb becomes low level (timing ta4).

Thereafter, when the transmission of the first byte of the operation state command by the transmission shift register 750 is completed, the transmission buffer register 740 transfers the second byte of the operation state command to be stored to the transmission shift register 750, and this transfer is completed. Then, it is cleared by the serial manager 780, and the transmission buffer empty signal TEb becomes high level (timing ta5). Thereafter, the transmission shift register 750 outputs the second byte of the operation state command received from the transmission buffer register 740 to the serial data Dba in the same manner as the first byte of the operation state command (timing ta6 to ta7).

In this embodiment, the payout CPU 710 repeatedly executes the scheduled interrupt process at an interval of 1 ms, while the serial para IF chip 720 executes serial transmission at a transmission rate of 1200 bps (Bit Per Second). 1200 bps is a low-speed communication speed that can use a transmission / reception element with a low response speed, such as a relatively inexpensive photocoupler, and is not affected by electrical noise. If the transmission rate in serial transmission is 1200 bps, the reliability of command transmission against electrical noise can be ensured. Since the transmission rate is 1200 bps, in this embodiment, the time required for the serial para IF chip 720 to serially transmit the 2-byte operation state command is about 16.7 ms, and the payout CPU 710 repeatedly executes the scheduled interrupt processing about 16 times during that time. Will be. In this manner, the payout CPU 710 can leave the serial transmission of the operation state command to the main control board 20 to the serial para IF chip 720 if the command is written in the transmission buffer register 740. That is, the payout CPU 710 can execute the control process without interruption even during serial transmission (a state in which the transmission buffer register 740 has an operation state command).

FIG. 11 is a flowchart showing details of the ACK waiting process (step S860) in the command transmission process (step S80). When the payout CPU 710 starts the ACK waiting process shown in FIG. 11, it determines whether or not the parallel IF unit 730 has detected an ACK signal from the main control board 20 (step S862). If an ACK signal is detected (step S862), the payout CPU 710 determines that the command has been normally transmitted to the main control board 20 (step S870), and sets the transmission job flag Fj to “0” (step S870). S880), the ACK waiting process is terminated.

On the other hand, when the ACK signal is not detected (step S862), the payout CPU 710 writes the command (step S84 in FIG. 9).
It is determined whether or not a predetermined time has elapsed since the completion of 6) (step S864). This predetermined time is a time for waiting for the response of the ACK signal from the main control board 20, and is set to 100 ms in this embodiment. If the predetermined time has not elapsed (step S864), the payout CPU 710 ends the ACK waiting process as it is, and if the predetermined time has elapsed (step S864), the payout CPU 710 It is determined that the command transmission is an error (step S875), the transmission job flag Fj is set to “0” (step S880), and the ACK waiting process is terminated. In this embodiment, when the payout CPU 710 determines that the transmission of the operation state command to the main control board 20 is an error (step S875), the payout CPU 710 retransmits the operation state command that has caused the transmission error.

Incidentally, even when the main CPU 200 transmits a payout command to the payout control board 70, an ACK waiting process is executed in the same manner as described above. The main CPU 200 needs to generate a payout command when a game ball wins the winning slot 61 during the ACK waiting process. If the main CPU 200 does not receive an ACK signal for a predetermined time or more in the ACK waiting process and determines that the transmission of the payout command to the payout control board 70 is an error, the main CPU 200 replaces the payout command by resending. A confirmation command for confirming again whether or not an ACK signal is returned from the control board 70 is transmitted. This is because if the payout command is retransmitted, the payout control board 70 may pay out the prize balls for two payout commands based on the payout command transmitted twice in total. The payout control board 70 transmits an acknowledgment signal to the main control board 20 when the confirmation command is received. The payout control board 70 may transmit an operation state command when the confirmation command is received. When receiving the ACK signal, the main CPU 200 transmits the next payout command to the payout control board 70.

Although the scheduled interrupt process in the payout CPU 710 has been described above, the scheduled interrupt process is similarly executed in the main CPU 200. In the scheduled interrupt process, a process for receiving an operation state command and an ACK signal are transmitted. Processing, sending out a payout command, and waiting for ack.

The operation in which the main control board 20 transmits a payout command and an ACK signal to the payout control board 70 is replaced with the arithmetic processing unit 210 instead of the payout CPU 710, the transmission buffer register 240 instead of the transmission buffer register 740, and the transmission shift. The transmission shift register 250 instead of the register 750 and the parallel IF unit 230 instead of the parallel IF unit 730 operate in the same manner as the ACK output process (step S10) and command transmission process (step S80) of the payout control board 70 described above, respectively. It is realized by doing.

Further, the operation in which the main control board 20 receives the operation state command and the ACK signal from the payout control board 70 is replaced with the arithmetic processing unit 210 instead of the payout CPU 710, the reception shift register 260 instead of the reception shift register 760, and the reception buffer register. The reception buffer register 270 instead of 770 and the parallel IF unit 230 instead of the parallel IF unit 730 perform the same operations as the command reception process (step S40) and the ACK waiting process (step S860) of the payout control board 70 described above, respectively. Realized by doing.

  According to the pachinko machine 10 of the present embodiment described above, the ACK signal is transmitted in parallel. Therefore, the ACK signal can be transmitted to the main control board 20 faster than in the case of serial transmission. If the main control board 20 can receive the ACK signal early, the next payout command can be transmitted to the payout control board 70, so the burden on the main control board 20 can be reduced. In the pachinko machine 10 according to the present embodiment, the main control board 20 serially transmits a payout command to the payout control board 70 at a low communication speed that is not affected by noise, and the payout CPU 710 executes the normal payout command. The payout control board 70 transmits / receives the payout command in the procedure of sending the ACK signal to the main control board 20 if it is determined that it has been received normally. It is possible to improve the reliability of the payout command by performing sending and receiving of the payout command according to these procedures. That is, in the pachinko machine 10 of the present embodiment, it is possible to reduce the burden on the main control board while improving the reliability of the payout command.

Further, in the pachinko machine 10 according to the present embodiment, since the operation state command is serially transmitted from the payout control board to the main control board at a low communication speed that is not affected by electrical noise, the reliability of the operation state command is also improved. can do. Furthermore, when the operation state command is normally received, the ACK signal transmitted from the main control board 20 to the payout control board 70 is transmitted in parallel. Since the transmission / reception is performed in two systems, serial and parallel, the reliability of transmission / reception can be improved.

Further, in the pachinko machine 10 of this embodiment, as the serial para IF chip 720, a reception shift register 760 that performs serial transmission / reception, a reception buffer register 770, a serial management unit 780, a transmission buffer register 740, and a transmission shift register 750 Since the parallel IF unit 730 that performs parallel transmission / reception is integrated on one chip, the space of the payout control board 70 can be saved. Also, by integrating on one chip, it is less susceptible to noise. In this embodiment, the serial IF chip 720 is used for the payout control board 70, but it may be used for the main control board 20. When used for the main control board 20, the space of the main control board 20 can be saved. By saving the space of these substrates, the area of the substrate itself is reduced, so that the degree of freedom of arrangement of the substrates is increased. Thereby, the freedom degree of arrangement | positioning of other components, such as a center accessory with which the pachinko machine 10 is equipped, also becomes high, and components can be arrange | positioned now in order to raise the interest of the pachinko machine 10.

Also, on the payout control board 70 side, the response corresponding to the payout command is quickly processed within the period of the payout scheduled interrupt process (FIG. 4) when the payout command is received, and the same timing every time in the subsequent payout scheduled interrupt process. Thus, an ACK signal for the main control board 20 can be output with certainty. Accordingly, it is possible to reliably check the normality of the payout command transmission without delaying the payout control. As a result, it is possible to improve the reliability of command transmission when the command is divided and serially transmitted between the main control board 20 and the payout control board 70. Further, in the payout scheduled interrupt process (FIG. 4), the payout process (step S60) is executed after the command receiving process (step S40), so that the payout control board 70 receives the payout command within the period of the payout interrupt process. An operation corresponding to the payout command can be quickly instructed to the payout driving unit 75.

C. Other Embodiments Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and can be implemented in various forms without departing from the spirit of the present invention. Of course you get. For example, in this embodiment, it is determined that the payout command has been normally received and the ack flag Fa is set in the determinations in step S418, step S428, and step S445, but it is determined that the payout command has been normally received. When doing, it is not restricted to this but various. For example, in addition to step S418, step S428, and step S445, when it is determined in the command analysis process of step S50 that the number of prize balls indicated by the payout command is within a normal value range (for example, 1 to 15). It is also possible to determine that the payout command has been received normally and set the ack flag Fa. It may be determined that the payout command is normally received in any of step S418, step S428, and step S445.

In this embodiment, the serial IF chip 720 is used as a component that performs serial transmission / reception and parallel transmission / reception. However, a reception shift register 760, a reception buffer register 770, and a serial management unit 780 that perform serial transmission / reception are used. The transmission buffer register 740, the transmission shift register 750, and the parallel IF unit 730 that performs parallel transmission / reception may not be integrated on one chip.

Further, the reception buffer register 270, the reception shift register 260, the transmission buffer register 740, and the transmission shift register 750 of the serial IF chip 720 can be omitted as appropriate without departing from the spirit of the present invention. is there.

Further, the present invention may be applied to a gaming machine provided with a plurality of control boards, and can be applied not only to a pachinko machine but also to a gaming machine such as an arrangement ball or a slot machine. Further, the board that has not received the command normally may request the retransmission of the command to the board that has transmitted the command. In this case, the retransmission request may be performed by serial transmission or may be performed by parallel transmission. This can improve the reliability of command transmission.

Further, the processing for various processing in the payout scheduled interrupt processing is not limited to that in the embodiment shown in FIG. 4, and the ACK output processing (step S10) is executed with priority over the time variation processing. Anything is fine. For example, a process in which the time required for completion is constant for each interrupt process according to the progress of the game may be executed before the ack output process (step S10).

Further, a command of 2 bytes or more generated by the sending CPU may be an even number of bytes. As a result, it is possible to efficiently store a 2-byte command per one-time interrupt process by the sending CPU. For example, the main control board 20 and the payout control board 70 generate a total of 4-byte commands consisting of a 3-byte instruction command and a 1-byte check command obtained by calculating the checksum of the instruction command as a group of commands. A group of commands of 4 bytes may be divided into two parts and transmitted serially every two bytes by two scheduled interrupt processes. In addition, the main control board 20 and the payout control board 70, together with a 4-byte inversion command obtained by inverting each bit of the 3-byte instruction command and the 1-byte check command, a total of 8-byte commands are grouped. It is also possible to generate a command as a command, divide a group of commands of 8 bytes into four times, and transmit serially every two bytes by four scheduled interrupt processes.

1 is a front view showing an overall configuration of a pachinko machine 10. FIG. 2 is a block diagram showing an electrical schematic configuration of a pachinko machine 10. FIG. 4 is a block diagram showing details of an electrical configuration of a main control board 20 and a payout control board 70. FIG. 7 is a flowchart showing a payout fixed time interruption process by the payout control board 70; It is a flowchart which shows the detail of the command reception process (step S40) performed in the payment fixed time interruption process. It is a time chart which shows the mode of each signal in the payout control board 70 at the time of command reception processing (step S40) being performed. It is a flowchart which shows the detail of the ack output process (step S10) performed in the payment fixed time interruption process. It is a flowchart which shows the detail of the command transmission process (step S80) performed in a payment fixed time interruption process. It is a flowchart which shows the detail of the command output process (step S820) in a command transmission process (step S80). It is a time chart which shows the mode of each signal in the payout control board 70 at the time of command output processing (step S820) being performed. It is a flowchart which shows the detail of the ACK waiting process (step S860) in a command transmission process (step S80).

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Pachinko machine 11 ... Outer frame 12 ... Inner frame 13 ... Game board 14 ... Glass frame 15 ... Handle 17 ... Ball tank 19 ... Lower plate 20 ... Main control board 30 ... Symbol control board 35 ... LCD 40 ... Sub control board 45 ... Speaker 55, 56, 57, 58, 59 ... Electric decoration 61 ... Winning slot 65 ... Game ball sensor 66 ... Game board drive unit 70 ... Payout control board 72 ... Status display unit 75 ... Payout drive unit 90 ... Card unit 200 ... Main CPU 210: Arithmetic processing unit 220 ... Serial IF unit 230 ... Parallel IF unit 240 ... Transmission buffer register 250 ... Transmission shift register 260 ... Reception shift register 270 ... Reception buffer register 280 ... Serial management unit 710 ... Discharge CPU 720 ... Serial I / F Chip 730 ... Parallel IF unit 740 ... Transmission buffer register 750 ... Transmission Shift register 760 ... Reception shift register 770 ... Reception buffer register 780 ... Serial management unit 782 ... Clear register CBb ... Set signal Fa ... Acknowledgment flag Fj ... Job flag Dab ... Serial data Dba ... Serial data Lbs ... Transmission register delivery period Lsc ... Serial transmission Period Lwa ... Writing standby period

Claims (3)

A main control board for controlling the progress of the game,
A payout control board that controls payout of game balls or game medals based on payout commands that are commands related to payout of game balls or game medals transmitted from the main control board;
The main control board includes: a main control board serial transmission unit that serially transmits a command to the payout control board at a low communication speed not affected by electrical noise; and a general-purpose parallel in the main control board A main control board parallel reception port, which is a part of the ports, and the payout control board is a serial command at a low communication speed not affected by electrical noise from the main control board. The payout control board serial reception unit for receiving the payout control board, the payout control board parallel transmission port which is a part of the general-purpose parallel port in the payout control board, and the process related to the payout by repeatedly executing the interrupt processing for a predetermined time. A payout control board central processing unit for performing, and the payout command is sent from the main control board serial transmission unit When the payout control board central processing unit determines that the payout command has been received normally, the payout control board serial reception unit sends a payout command confirmation signal to the payout control board parallel transmission port. The payout command confirmation signal is transmitted in parallel from the payout control board parallel transmission port to the main control board parallel reception port. 2. The gaming machine according to claim 1, wherein the main control board includes a main control board serial receiving unit that serially receives commands from the payout control board at a low communication speed that is not affected by electrical noise. A main control board parallel transmission port which is a part of general-purpose parallel ports in the main control board, and a main control board center which performs processing related to the control of the progress of the game by repeatedly executing a fixed-time interrupt process A payout control board serial transmission unit that serially transmits a command to the main control board at a low communication speed that is not affected by electrical noise, and the payout control board. A payout control board parallel receiving port which is a part of general-purpose parallel ports on the control board, and the payout system The substrate central processing unit detects a predetermined operation state of the gaming machine, and outputs an operation state command that is a command indicating the operation state via the payout control substrate serial transmission unit, and the operation state command is , Serially transmitted from the payout control board serial transmission unit to the main control board serial reception unit, and when the main control board central processing unit determines that the operation state command has been normally received, the operation state command A confirmation signal is output via the main control board parallel transmission port, and the operation state command confirmation signal is transmitted in parallel from the main control board parallel transmission port to the payout control board parallel reception port. A game machine. 2. The gaming machine according to claim 1, wherein the payout control board serial receiving unit and the general-purpose parallel port in the payout control board are integrated on one chip.

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