JP4777009B2 - Game machine - Google Patents

Description

  The present invention includes variable display means capable of variably displaying a plurality of types of identification information that can identify each of the identification information. After a predetermined variable display execution condition is satisfied, the variable display start condition is satisfied. The present invention relates to a gaming machine that starts variable display of identification information and shifts to a specific gaming state advantageous to the player when the display result of variable display of identification information becomes a specific display result.

  As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a prize area such as a prize opening provided in the game area, a predetermined number of prize balls are paid out to the player. There is something to be done. Furthermore, there is provided a variable display unit capable of changing the display state, and configured to give a predetermined game value to the player when the display result of the variable display unit is in a predetermined specific display mode. is there.

  The game value is the right that the state of the variable winning ball apparatus provided in the gaming area of the gaming machine becomes advantageous for a player who is easy to win, and the right for becoming advantageous for a player. In other words, or a condition for winning a prize ball is easily established.

  In the gaming machine, when a predetermined transition condition is established, the gaming state is shifted to a specific gaming state that is advantageous to the player. For example, in a pachinko gaming machine, a combination of a specific display mode in which a display result of a variable display unit that displays a special symbol is a predetermined combination is generally referred to as “big hit”. When the big hit occurs, for example, the big winning opening is opened a predetermined number of times, and the game shifts to a big hit gaming state where the hit ball is easy to win.

  Game progress in the gaming machine is controlled by game control means such as a microcomputer. In addition, the game control means includes means for generating a pseudo-random number, and whether or not a predetermined transition condition is satisfied based on the value of the random number (for example, whether or not the display result of variable display is a combination of specific display modes) Or). For example, the game control means determines whether or not a predetermined transition condition is satisfied by determining whether or not a random number value matches a predetermined determination value. When it is determined that a predetermined transition condition is satisfied, the game control means shifts the gaming state to the specific gaming state.

  There is a gaming machine in which the mounting area for mounting the random number generation means and the game control means on a board is reduced by using a microcomputer equipped with a random number circuit as the game control means (see, for example, Patent Document 1). In addition, in the gaming machine described in Patent Document 1, the control burden on the microcomputer is reduced by using a random number generated by a random number circuit mounted on the microcomputer. Further, in Patent Document 1, the random number circuit is initialized from the start of power-on to the gaming machine until the timer interrupt is set, and the game control process for controlling the progress of the game is executed. It is described that it comprises.

Japanese Patent Laying-Open No. 2005-103166 (paragraphs 0039, 0041, 0095-0100, FIGS. 3-4 and 20-21)

  In the gaming machine described in Patent Document 1, the initial setting of the random number circuit from the start of power-on to the gaming machine until the timer interrupt setting is performed. Set the cycle for updating the random number. However, the initial value of the generated random number cannot be set in advance. Therefore, when using a plurality of gaming machines, each gaming machine starts generating random numbers from a common initial value. Then, when using a plurality of gaming machines described in Patent Document 1, when the power of each gaming machine is turned on at the same time, each gaming machine starts generating random numbers at the same timing from the same initial value. There is a risk of the timing being recognized by a player or a game store. Therefore, there is a possibility that conditions for shifting to a specific gaming state such as a jackpot may be illegally established by generating a capture signal using a wireless signal or the like at a predetermined cycle.

  Further, in the gaming machine described in Patent Document 1, it is disclosed that a microcomputer used as a game control means prevents malfunction due to a communication error when communicating with each control board mounted on the gaming machine. Absent.

  Therefore, the present invention is to determine a display result of variable display of identification information in a gaming machine that shifts to a specific gaming state advantageous to a player when the display result of variable display of identification information becomes a specific display result. When generating random numbers to be used, the randomness of the generated random numbers can be improved, so that it is possible to prevent the condition for transition to the specific gaming state from being illegally generated and to prevent malfunction due to a communication error The purpose is to.

The gaming machine according to the present invention includes variable display means (for example, a special symbol display 8) capable of variably displaying a plurality of types of identification information (for example, special symbols) that can be distinguished from each other. After the execution condition (for example, winning a game ball to the start winning opening 14) is satisfied, the identification information is variable based on the satisfaction of the variable display start condition (for example, final stop of special symbol and end of jackpot game). A game machine that starts display and shifts to a specific gaming state advantageous to the player when the display result of variable display of identification information becomes a specific display result (for example, jackpot symbol), and executes control processing A control CPU (for example, CPU 56), a random number circuit (for example, random number circuit 503) for generating random numbers, and a CPU other than the control CPU (for example, a payout control microcomputer) Control microcomputer (for example, for game control) including a microcomputer (for example, a payout control microcomputer 370) and a serial communication circuit (for example, serial communication circuit 505) for serial communication. The random number circuit is provided with a predetermined value from a predetermined initial value within a predetermined range in which numerical data (for example, a count value) can be updated based on an input of a predetermined signal (for example, a clock signal). Numerical value updating means (for example, counter 521) for updating numerical data according to a predetermined order up to the final value, and random number storage means (for example, random value storage circuit) for storing numerical data updated by the numerical value updating means as random values 531) and a, serial communication circuit, a plurality of interrupt request conditions For example, when any of the following occurs: a communication error has occurred in the serial communication circuit 505, transmission of transmission data has been completed, or reception data has been received from the control board, Including an interrupt request means (for example, an interrupt control circuit 714) for generating an interrupt request according to the established interrupt request condition, and the control microcomputer is predetermined when power supply to the gaming machine is started. Timer interrupt setting means (for example, a part for executing step S16 in the gaming control microcomputer 560) for setting to generate a timer interrupt every time, and when power supply to the gaming machine is started , Random number circuit initial setting means (for example, game control microcomputer) for initial setting of the random number circuit before the timer interrupt setting means sets the timer interrupt. And the control CPU executes an interrupt process based on an interrupt request from the interrupt request means (for example, a game control micro). Steps S41, S42, and S43 executed by the CPU 56 of the computer 560 and control processing (for example, steps S21 to S32 (excluding steps S28 and S31) in the timer interrupt processing) when a timer interrupt occurs. Timer interrupt processing execution means (for example, a portion for executing steps S20 to S33 in the CPU 56 of the game control microcomputer 560) and variable display when the timer interrupt occurs Whether or not the execution condition (for example, winning a game ball to the start winning opening 14) is established. When the execution condition determining means to determine (for example, the part for executing step S311 in the CPU 56 of the game control microcomputer) and the execution condition determining means determine that the execution condition for variable display is satisfied, the random number storage means Random number reading means for reading out the stored random number value (for example, a part for executing step S324 in the CPU 56 of the game control microcomputer 560) and whether or not the random number value read by the random number reading means matches a predetermined determination value. Display result determining means for determining whether or not the display result of the variable display of the identification information is set as the specific display result (for example, the step of executing step S386 in the CPU 56 of the game control microcomputer 560) ), And the random number circuit initial setting means in the initial setting, Microcomputer identification information (for example, an ID number unique to the game control microcomputer 560) for identifying the control microcomputer assigned to each control microcomputer with a predetermined initial value of the numerical data updated by the value update means can be set based on (e.g., portions for performing the steps S154 in the gaming control microcomputer 560), an interrupt request interrupt request means for generating an interrupt when a communication error occurs in the serial communication circuit Including an error time interrupt request (for example, communication error time interrupt request) that occurs when the request condition is satisfied, the interrupt processing execution means performs an error time interrupt request based on the error time interrupt request. Exceptions that can be executed in preference to interrupt processing based on other interrupt requests (for example, interrupt requests at reception and interrupts at transmission) Including an earlier processing means (for example, the part for executing step S15b in the game control microcomputer 560), serial communication is prohibited in the interrupt process based on the error time interrupt request (for example, the game control microcomputer 560 is Based on the fact that the communication error flag has been set in step S41, the process is terminated if it is determined in steps S1241, S1251, S1261, S1271, and S1291 that the communication error flag has been set). To do.

  The control microcomputer includes a plurality of random number circuits (for example, a 12-bit random number circuit 503a and a 16-bit random number circuit 503b) having different predetermined ranges of numerical data that can be updated by the numerical value updating means. In the initial setting, a usable random number circuit is set from among a plurality of random number circuits built in the control microcomputer (for example, the game control microcomputer 560 executes step S151) and used by the random number circuit initial setting means. Random number circuit stop means for stopping the function of the random number circuit other than the set random number circuit (for example, the game control microcomputer 560 is set not to be used when the random number circuit 503 used in step S151 is set) So that the counter 521 of the random number circuit does not update the count value C Gosuru portion) may be configured to include.

  In the initial setting, the random number circuit initial setting means sets a numerical maximum value register (for example, the random number maximum value setting register 535) in which a value as a maximum value in a predetermined range in which numerical data is updated is set by the numerical value updating means. A predetermined maximum value (for example, a random number maximum value) is set within the range of the numerical data that can be updated (for example, the part in which the game control microcomputer 560 executes step S153), and the numerical value updating means performs random circuit initialization. Setting value determination means (for example, game control) for determining whether or not the predetermined maximum value set by the means is equal to or less than a predetermined lower limit value (for example, “256” when the 12-bit random number circuit 503a is set) Part for executing step S153b in the microcomputer 560) and the numerical value maximum value register by the set value judging means When it is determined that the set predetermined maximum value is equal to or less than the predetermined lower limit value, a predetermined value within the range of numerical data that can be updated by the numerical value updating means (for example, a 12-bit random number circuit) is stored in the numerical maximum value register. Maximum value resetting means (for example, a part for executing step S153c in the game control microcomputer 560) for resetting “4095” in the case of setting 503a may be included.

  The gaming machine includes clock signal generation means (for example, a clock circuit 501) that generates a clock signal having a predetermined period and outputs the clock signal to a random number circuit, and the numerical value updating means is configured to input a numerical value on condition that the clock signal is input a predetermined number of times. The data is updated (for example, when the clock signal output circuit 524 inputs the random number generation clock signal SI obtained by dividing the reference clock signal CLK by 16), the counter 521 updates the count value C). In the initial setting, the number updating means may be configured to set the number of input clock signals that is a condition for updating the numerical data (for example, the game control microcomputer 560 executes step S156).

  The control microcomputer executes numerical calculation means for calculating a predetermined initial value of the numerical data set by the random number circuit initial setting means using the microcomputer identification information (for example, the process of step S154b in the gaming microcomputer). In this case, the random number circuit initial setting means includes a numerical value of the game control microcomputer 560 by calculating the ID number and a predetermined value (for example, a portion for calculating the calculated value by adding the predetermined value to the ID number). An initial value is set based on the value calculated by the calculation by the calculation means (for example, when the gaming microcomputer executes the process of step S154b, the calculated calculation value is set as the initial value of the count value). It may be configured.

  The random number circuit initial setting means sets whether or not to change the predetermined initial value set by the random number circuit initial setting means when the numerical data is updated to a predetermined final value by the numerical value updating means in the initial setting. (For example, the game control microcomputer 560 executes step S157). When the numerical data is updated to the predetermined final value by the numerical value updating means, the random number circuit is updated to the predetermined final value. Based on the notification signal output means (for example, the output terminal of the counter 521) that outputs a notification signal indicating the fact and the output of the notification signal, the initial value is set by the random number circuit initial setting means. Sometimes, an initial value changing means for changing a predetermined initial value (for example, step S220 in the game control microcomputer 560). It may be configured so as to include a portion) and for executing S226.

  The gaming machine outputs a winning detection signal (for example, a winning detection signal SS) by detecting that the game medium has won in the winning area (for example, the start winning port 14) in the gaming area and the variable display execution condition is satisfied. The random number circuit stores numerical data updated by the numerical value updating means in the random number storage means based on the input of the winning detection signal from the winning detection means. A latch signal output means (for example, a latch signal generation circuit 533) that outputs a latch signal for instructing to perform the instruction, and the latch signal output means that the winning detection signal is continuously input from the winning detection means for a predetermined period. (For example, when the timer circuit 534 measures a predetermined period (for example, 3 ms), the random value read signal output from the random value read signal output circuit 526) (For example, the latch signal generation circuit 533 outputs the random number read signal output from the random value read signal output circuit 526 to the inverted clock signal SI2 output from the inversion circuit 532). The portion may be configured to be output to the random value storage circuit 531 as a latch signal SL in synchronization with the rising edge of

  The gaming machine includes a winning detection means (for example, a start port switch 14a) for detecting that a game medium has won a winning area in the gaming area, and that a variable display execution condition is satisfied, and outputs a winning detection signal. The circuit outputs a latch signal for instructing to store numerical data updated by the numerical value updating means in the random number storage means based on the input of the winning detection signal from the winning detection means. For example, a latch signal generation circuit 533), and the latch signal output means outputs a latch signal (for example, a latch signal generation circuit) on condition that the winning detection signal is continuously input from the winning detection means for a predetermined period. 533 is the random number value read signal output from the random number value read signal output circuit 526 and the rising edge of the inverted clock signal SI2 output from the inversion circuit 532 is The portion that is output to the random value storage circuit 531 as a latch signal SL in synchronization with the edge), and the random number reading means continues to detect a prize while the timer interrupt processing execution means is executed a predetermined number of times. The condition that the winning detection signal is input from the means (for example, when the game control microcomputer 560 executes the process of step S322, the number of executions of the timer interrupt process indicated by the interrupt counter is a predetermined number ( For example, the random number stored in the random number storage means is read out (for example, the CPU 56 stores the random R stored as the random number value from the random number storage circuit 531 of the random number circuit 503). The value is read out), and the predetermined period (for example, 3 ms) is shorter than the period (for example, 6 ms) in which the predetermined number of timer interruption processes are executed. It may be configured.

  In the initial setting, the random number circuit initial setting means sets the order of values from a predetermined initial value to a predetermined final value of the numerical data updated by the numerical value updating means (for example, a permutation of count values C updated by the counter 521). Numerical value order setting means for setting whether or not to change (for example, a part for executing step S158 in the game control microcomputer 560), the random number circuit updates the numerical data up to a predetermined final value by the numerical value update means. A notification signal output means (for example, an output terminal of the counter 521) for outputting a notification signal indicating that the numerical data has been updated to a predetermined final value, and a random number based on the output of the notification signal. When the circuit initial setting means has been set to change the order of numerical data from a predetermined initial value to a predetermined final value, A numerical order changing means for changing the order of numerical data to be updated from a predetermined initial value to a predetermined final value (for example, a part for executing step S24 in the game control microcomputer 560). May be.

  The control microcomputer is a serial communication circuit initial setting means for performing initial setting of the serial communication circuit before the timer interrupt setting means is set by the timer interrupt setting means when power supply to the gaming machine is started. The interrupt request generated by the interrupt request means includes a microcomputer (for example, payout control) including a CPU other than the control CPU (including the part for executing step S15a in the game control microcomputer 560). Serial communication circuit initial setting including a reception interrupt request (for example, a reception interrupt request that is performed when the serial communication circuit 505 detects reception data full) that is generated when data is received from the microcomputer 370) The means is a setting for changing the priority order of the interrupt processing executed by the priority processing means. Priority change means that is executed before the timer interrupt is set by the timer interrupt setting means (for example, when the game control microcomputer 560 executes step S15b, the reception priority interrupt execution flag is set) The priority processing means prioritizes the interrupt processing based on the receiving interrupt request rather than the interrupt processing based on the error interrupt request by the priority changing means. The interrupt process based on the interrupt request at the time of reception is executed in preference to the interrupt process based on the interrupt request at the time of error (for example, the game control microcomputer 560 performs the process). , A portion that executes step S42 in preference to steps S41 and S43).

According to the first aspect of the present invention, the control microcomputer performs initial setting of the random number circuit from the start of power-on to the gaming machine until the timer interrupt is set, and based on the microcomputer identification information in the initial setting. which is configured to settable der so that the value as a predetermined initial value, it is possible to improve the randomness of the random number by the random number circuit generates. Moreover, since randomness of random numbers can be improved, the timing of random number generation can be made difficult to be recognized by a player or a game store, and the execution condition of variable display is established illegally using radio signals. It is possible to prevent the condition for shifting to the specific gaming state from being illegally established. Furthermore, when the serial communication circuit issues an interrupt request, it is possible to preferentially execute interrupt processing when a communication error is set as an interrupt request condition, and control communication to a prohibited state. Therefore, it is possible to prevent communication with the control board mounted on the gaming machine in a state where a communication error has occurred. Therefore, malfunction due to a communication error can be prevented.

  In the invention described in claim 2, since it is configured to set whether or not each of a plurality of random number circuits having different predetermined ranges of numerical data that can be updated can be used, only the random number circuit to be used is used. By setting, the range of the random number value to be generated can be appropriately set.

  In the invention described in claim 3, since the value as the maximum value of the predetermined range in which the numerical data is updated is set in advance, a value larger than the range of random numbers used during the execution of the timer interrupt process Can be prevented, and the processing load on the random number circuit and the control microcomputer can be reduced. In addition, when the predetermined maximum value that is set is equal to or less than the predetermined lower limit value, it is configured to reset the predetermined maximum value, so that a malfunction of the control microcomputer or a radio signal is used. It is possible to prevent an excessively small value from being set as the maximum value of the random number by an action such as generating a capture signal for the gaming machine.

  In the invention described in claim 4, since the numerical value updating means is configured to preset the number of times of input of the clock signal which is a condition for updating the numerical data, the randomness of the random number generated by the random number circuit is further improved. be able to.

  In the invention described in claim 5, since the initial value is set based on the value calculated by the calculation using the microcomputer identification information, the randomness of the random number generated by the random number circuit is further improved. Can do. For this reason, it is possible to make it difficult to recognize the initial value of the random number simply by looking at the microcomputer identification information, and the security can be improved.

  In the invention described in claim 6, since the predetermined initial value is updated when the numerical data is updated to the predetermined final value, the randomness of the random number generated by the random number circuit is further improved. Can do.

  According to the seventh aspect of the present invention, when the random number storage means stores the random number based on the output of the latch signal, the latch signal is supplied on condition that the winning detection signal is input continuously for a predetermined period. Since it is configured to output, it is possible to prevent the occurrence of noise from being erroneously recognized as the input of the input detection signal, outputting the latch signal, and storing the generated random number. In addition, it is possible to reduce the possibility that a random number generated by an illegal latch signal is stored due to an output of a latch signal by an action such as generating a capture signal using a radio signal to the gaming machine. .

  In the invention according to claim 8, when reading the random number from the random number storage means, the random number is read from the random number storage means on condition that the winning detection signal is continuously input while the timer interruption process is executed a predetermined number of times. Therefore, it is possible to prevent the random number from being read again after the random number is read and before the value of the random number stored in the random number storage unit is updated. Therefore, it is possible to prevent a random number having the same value as the random number read from the previous random number storage unit from being read again.

  According to the ninth aspect of the invention, when the numerical data is updated to the predetermined final value, the arrangement order from the predetermined initial value to the predetermined final value is updated, so the random number circuit generates The randomness of random numbers can be further improved.

  In the invention according to claim 10, since it is configured to change the priority of the interrupt processing, among the interrupt processing corresponding to a plurality of types of interrupt request conditions, the interrupt processing to be executed with priority. Can be executed reliably. In addition, since the interrupt process to be executed with priority can be initially set, the degree of freedom of the program executed by the control microcomputer can be improved.

Embodiment 1 FIG.
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
First, the overall configuration of a pachinko gaming machine that is an example of a gaming machine will be described. FIG. 1 is a front view of a pachinko gaming machine as viewed from the front, and FIG. 2 is a front view showing the front of the game board. In the following embodiments, a pachinko gaming machine will be described as an example. However, the gaming machine according to the present invention is not limited to a pachinko gaming machine, and can be applied to other gaming machines such as a slot machine.

  The pachinko gaming machine 1 includes an outer frame (not shown) formed in a vertically long rectangular shape, and a game frame attached to the inside of the outer frame so as to be opened and closed. Further, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape that is provided in the game frame so as to be opened and closed. The game frame includes a front frame (not shown) installed to be openable and closable with respect to the outer frame, a mechanism plate to which mechanism parts and the like are attached, and various parts attached to them (excluding game boards described later). Is a structure including

  As shown in FIG. 1, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2 is a hitting ball supply tray (upper plate) 3. Under the hitting ball supply tray 3, an extra ball receiving tray 4 for storing game balls that cannot be accommodated in the hit ball supply tray 3 and a hitting operation handle (operation knob) 5 for launching the game balls are provided. A game board 6 is detachably attached to the back surface of the glass door frame 2. The game board 6 is a structure including a plate-like body constituting the game board 6 and various components attached to the plate-like body. A game area 7 is formed on the front surface of the game board 6.

  Near the center of the game area 7, there is provided a variable display device (decorative symbol display device) 9 including a plurality of variable display portions each variably displaying an effect decorative symbol. The variable display device 9 has, for example, three variable display portions (symbol display areas) of “left”, “middle”, and “right”. The variable display device 9 performs variable display of a decorative symbol as a symbol for decoration (production) during the variable symbol display period of the special symbol by the special symbol indicator 8. The variable display device 9 that performs variable display of decorative symbols is controlled by an effect control microcomputer mounted on the effect control board.

  At the bottom of the variable display device 9, four special symbol hold memory indicators 18 for displaying the number of valid winning balls that have entered the start winning opening 14, that is, the number of hold memories (also referred to as start memory or start prize memory), are provided. ing. The special symbol reservation storage display 18 displays up to four reservation storage numbers in the order of winning. The special symbol hold storage display 18 increases the number of LEDs in the lit state by 1 each time there is a start winning in the start winning opening 14. Then, each time the special symbol display 8 starts variable display, the special symbol hold storage indicator 18 reduces the number of LEDs in the lit state by 1 (that is, turns off one LED). Specifically, the special symbol hold storage display 18 shifts the lighting state each time variable display is started on the special symbol display 8. In this example, the upper limit number (up to 4) is provided for the number of starting memories by winning to the start winning opening 14, but the upper limit number may be four or more.

  A special symbol display (special symbol display device) 8 that variably displays a special symbol as identification information is provided on the variable display device 9. In this embodiment, the special symbol display 8 is realized by a simple and small display (for example, 7 segment LED) capable of variably displaying numbers 0 to 9, for example. The special symbol display 8 may be configured to variably display a larger number of numbers such as 0 to 99 in order to make it difficult for the player to grasp a specific stop symbol. In addition, the variable display device 9 performs variable display of a decorative symbol as a symbol for decoration (for production) during the variable symbol display period of the special symbol by the special symbol indicator 8.

  Further, on the left side of the variable display device 9, a hammer 151 is provided as a movable member used for game effects. The hammer 151 can fall to the right with the movable portion 152 as a fulcrum, and can produce an effect of hitting the leftmost decorative symbol among the decorative symbols displayed on the variable display device 9.

  Further, the pachinko gaming machine 1 includes an operation switch 81 that can be operated by the player while the game is in progress. For example, when the operation switch 81 is operated (pressed), the hammer 151 as a movable member operates.

  Below the variable display device 9 is provided a variable winning ball device 15 that forms a start winning opening 14. The winning ball that has entered the start winning opening 14 is guided to the back of the game board 6 and detected by the start opening switch 14a. The variable winning ball device 15 is opened by a solenoid 16.

  Below the variable winning ball apparatus 15, a special variable winning ball apparatus 20 using an opening / closing plate that is controlled to be opened by a solenoid 21 in a specific gaming state (big hit state) is provided. The special variable winning ball apparatus 20 is a means for opening and closing the big winning opening. Of the winning balls that are won in the special variable winning ball apparatus 20 and guided to the back of the game board 6, the winning ball that has entered one (V winning area: special area) is detected by the V winning switch 22 and then counted by the count switch 23. The game ball that has been detected and entered the other area is detected by the count switch 23 as it is. On the back of the game board 6, a solenoid 21A for switching the route in the special winning opening is also provided.

  When the game ball passes through the gate 32 and is detected by the gate switch 32a, variable display of the normal symbol display 10 is started. In this embodiment, variable display is performed by alternately lighting left and right lamps (designs can be visually recognized when lit). For example, if the left lamp is lit at the end of variable display, it is a hit. When the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined number of times. In the vicinity of the normal symbol display 10, a normal symbol start memory display 41 having a display unit with four LEDs for displaying the number of winning balls that have passed through the gate 32 is provided. Each time there is a game ball passing through the gate 32, the normal symbol start memory display 41 increases the number of LEDs to be turned on by one. Each time the variable display on the normal symbol display 10 is started, the number of LEDs to be lit is reduced by one.

  The game board 6 is provided with a plurality of winning holes 29, 30, 33, 39, and winning of game balls to the winning holes 29, 30, 33, 39 is performed by winning hole switches 29a, 30a, 33a, 39a, respectively. Detected. Each winning opening 29, 30, 33, 39 constitutes a winning area provided in the game board 6 as an area for accepting game media and allowing winning. The start winning opening 14 and the big winning opening also constitute a winning area that accepts game media and allows winning. Around the left and right of the game area 7, there are provided decorative lamps 25 blinking and displayed during the game, and at the lower part there is an outlet 26 for absorbing a game ball that has not won a prize. Two speakers 27 that emit sound effects are provided on the left and right upper portions outside the game area 7. A top frame lamp 28a, a left frame lamp 28b, and a right frame lamp 28c are provided on the outer periphery of the game area 7. Further, a decoration LED is installed around each structure (such as a big prize opening) in the game area 7. The top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, and the decorative LED are examples of a decorative light emitter provided in the gaming machine.

  In this example, a prize ball lamp 51 that is lit during award ball payout is provided in the vicinity of the left frame lamp 28b, and a ball break lamp 52 that is lit when the supply ball is cut in the vicinity of the top frame lamp 28a. Is provided. Further, a prepaid card unit (hereinafter referred to as “card unit”) 50 that enables lending a ball by inserting a prepaid card is installed adjacent to the pachinko gaming machine 1.

  The card unit 50 includes, for example, a usable display lamp that indicates whether or not the card unit 50 is in a usable state, a connection table direction indicator that indicates which side of the pachinko gaming machine 1 corresponds to the card unit, and a card unit. When checking the card insertion indicator lamp indicating that a card is inserted in the card, the card insertion slot into which the card as a recording medium is inserted, and the card reader / writer mechanism provided on the back of the card insertion slot A card unit lock for releasing the card unit is provided.

  A game ball launched from the ball striking device by the player's operation enters the game area 7 through the hit ball rail, and then descends the game area 7. When the game ball enters the start winning opening 14 and is detected by the start opening switch 14a, the special symbol on the special symbol display 8 starts variable display (variation) if the variable display of the symbol can be started. If the variable display of the symbol cannot be started, the number of reserved memories is increased by one.

  The variable display of the special symbol on the special symbol display device 8 stops when a certain time has elapsed. If the special symbol (stop symbol) at the time of stoppage is a jackpot symbol (specific display result), the game shifts to a jackpot gaming state. That is, the special variable winning ball apparatus 20 is released until a predetermined time elapses or a predetermined number (for example, 10) of gaming balls wins. When the game ball is won in the V winning area while the special variable winning ball apparatus 20 is opened and detected by the V winning switch 22, a continuation right is generated and the special variable winning ball apparatus 20 is opened again. The generation of the continuation right is allowed a predetermined number of times (for example, 15 rounds). Note that without providing the V winning area, the special variable winning ball apparatus 20 may always be allowed to be released up to the final round (for example, up to 15 rounds).

  When the special symbol on the special symbol display 8 at the time of stoppage is a jackpot symbol (probability variation symbol) with a probability variation, the probability of the next jackpot increases. That is, it becomes a more advantageous state for the player in the probability variation state.

  When the game ball passes through the gate 32, the normal symbol display unit 10 enters a state in which the normal symbol is variably displayed. Further, when the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the probability variation state, the probability that the stop symbol in the normal symbol display 10 becomes a winning symbol is increased, and the opening time and the number of times of opening of the variable winning ball device 15 are increased. That is, the opening time and the number of times of opening of the variable winning ball device 15 can be increased when the stop symbol of the normal symbol is a winning symbol or the stop symbol of the special symbol is a probabilistic symbol. Change to an advantageous state. It should be noted that increasing the number of times of opening is a concept including changing from a closed state to an open state.

  Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. FIG. 3 is a rear view of the gaming machine as seen from the back side.

  As shown in FIG. 3, on the back side of the gaming machine, a variable display control unit 49 including an effect control board 80 on which an effect control microcomputer for controlling the variable display device 9 is mounted, a game control microcomputer and the like are mounted. A game control board (main board) 31 is installed. In addition, a payout control board 37 on which a payout control microcomputer for performing ball payout control is mounted is installed. The production control microcomputer controls the variable display device 9 provided on the game board 6, and various decoration LEDs, a decoration lamp 25, a top frame lamp 28a, a left frame lamp 28b provided on the frame side, and The lighting of the right frame lamp 28c is controlled, and the sound generation from the speaker 27 is controlled.

  Further, a power supply substrate 910 and a touch sensor substrate 91 on which a power supply circuit for generating DC30V, DC21V, DC12V, and DC5V is mounted are provided. Although most of the power supply substrate 910 overlaps with the main substrate 31, there is an exposed portion that is exposed so as to be visible from the outside without overlapping the main substrate 31. The exposed portion is operated by supplying power to the main board 31 and each electrical component control board (production control board 80 and payout control board 37) in the gaming machine 1 and each electrical component provided in the gaming machine. A power switch is provided as a power supply permission means for executing or cutting off power supply to the component to be performed. Furthermore, a replaceable fuse is provided inside the power switch in the exposed portion (inside the substrate).

  An electrical component control means including an electrical component control microcomputer is mounted on the electrical component control board. The electrical component control means is an electrical component (game device: ball payout device 97, variable display device 9, lamp, LED, etc.) provided in the gaming machine according to a command signal (control signal) as a command from the game control means or the like. The light emitter, speaker 27, etc.). Hereinafter, description may be made by including the main board 31 in the electric component control board. In that case, the electrical component control means mounted on the electrical component control board includes a game control means and a means for controlling the electrical components provided in the gaming machine according to a command signal from the game control means or the like. Point to. A substrate on which a microcomputer other than the main substrate 31 is mounted may be referred to as a sub-substrate.

  On the back side of the gaming machine, a terminal board 160 provided with terminals for outputting various information to the outside of the gaming machine is installed above. The terminal board 160 includes at least a ball break terminal for introducing the output of the ball break detection switch 167 and outputting it externally, a prize ball terminal for outputting prize ball information (prize ball number signal) and a ball. A ball lending terminal for externally outputting lending information (ball lending number signal) is provided. Further, an information terminal board (information output board) 36 having terminals for outputting various information from the main board 31 to the outside of the gaming machine is installed near the center.

  The game balls stored in the storage tank 38 pass through the guide rail 39 and reach the ball payout device covered with the payout case 40A via the curve rod. A ball break switch 187 as a game medium break detection means is provided on the upper part of the ball payout device. When the ball break switch 187 detects a ball break, the dispensing operation of the ball dispensing device stops. The ball break switch 187 is a switch for detecting the presence or absence of a game ball in the game ball passage. In the vicinity of the head). When the ball break detection switch 167 detects the shortage of game balls, the game machine is replenished to the game machine from the supply mechanism provided on the gaming machine installation island.

  When a large number of game balls as prizes based on winning a prize and game balls based on a ball lending request are paid out and the hitting ball supply tray 3 is full, the game balls are guided to the surplus ball receiving tray 4 through the surplus ball passage. When the game ball is further paid out, a sensing lever (not shown) presses a full tank switch (not shown) as a storage state detection means, and the full tank switch as a storage state detection means is turned on. In this state, the rotation of the payout motor in the ball payout device is stopped, the operation of the ball payout device is stopped, and the driving of the ball hitting device is also stopped.

  FIG. 4 is a block diagram illustrating an example of a circuit configuration in the main board 31. 4 also shows a payout control board 37, a lamp driver board 35, an audio output board 70, an interface board 66, a relay board 77, and an effect control board 80 mounted on the gaming machine. The main board 31 includes a basic circuit (corresponding to game control means) 53 for controlling the pachinko gaming machine 1 according to a program, a gate switch 32a, a start port switch 14a, a V winning switch 22, a count switch 23, a winning port switch 29a, 30a, 33a, 39a and an input driver circuit 58 for supplying a signal from the total winning counting switch 34 to the basic circuit 53, a solenoid 16 for opening and closing the variable winning ball device 15, a solenoid 21 for opening and closing the special variable winning ball device 20, and A solenoid circuit 59 for driving the solenoid 21A for switching the route in the special winning opening according to a command from the basic circuit 53 is mounted.

  It should be noted that switches such as the gate switch 32a, the start port switch 14a, the V winning switch 22, the count switch 23, the winning port switches 29a, 30a, 33a, 39a, the all winning count switch 34, and the like may be referred to as sensors. . That is, the name of the game medium detection means is not limited as long as it is a game medium detection means (game ball detection means in this example) that can detect a game ball. Each of the start port switch 14a, the count switch 23, and the winning port switches 29a, 30a, 33a, and 39a that perform winning detection is also a winning detection means that detects the winning of a game ball in the winning area. Note that even if a passing gate such as the gate 32 is used, if a prize ball is paid out, a game ball entering the passing gate becomes a winning and a switch provided on the passing gate (for example, The gate switch 32a) becomes a winning detection means. Furthermore, in this embodiment, the game ball that has won the V winning area is detected by the V winning switch 22 and also by the count switch 23. Therefore, the number of game balls won in the special winning opening corresponds to the number detected by the count switch 23. However, the game balls won in the V prize area are detected only by the V prize switch 22, and the number of game balls won in the big prize opening is determined by the number detected by the V prize switch 22 and the number detected by the count switch 23. You may make it become the sum. Further, the V winning area may not be provided, and a continuation right may always be generated in rounds other than the final round.

  The basic circuit 53 includes a ROM 54 for storing a program for game control (game progress control), a RAM 55 as storage means (variation data storage means for storing fluctuation data) used as a work memory, and a control operation according to the program. A game control microcomputer 560 having a CPU 56 is included. In this embodiment, the CPU 56 refers to a central processing unit (a portion excluding the storage means such as the ROM 54 and the RAM 55, the I / O port unit 57, etc.) operating in accordance with the program in the basic circuit 53. The game control microcomputer 560 includes a portion of the basic circuit 53 including a storage means such as a ROM 54 and a RAM 55, a random number circuit 503, a serial communication circuit 505, an I / O port unit 57, etc. in addition to the CPU 56. Point to. In this embodiment, the ROM 54, the RAM 55 serving as storage means as a work memory, and the I / O port unit 57 are built in the game control microcomputer 560. That is, the game control microcomputer 560 is a one-chip microcomputer. The one-chip microcomputer only needs to include at least the RAM 55, and the ROM 54 may be external or internal.

  In the game control microcomputer 560, the CPU 56 executes control in accordance with the program stored in the ROM 54. Therefore, hereinafter, the game control microcomputer 560 executes (or performs processing) specifically. Is that the CPU 56 executes control according to the program. The same applies to microcomputers mounted on substrates other than the main substrate 31. The game control means is realized by a basic circuit 53 including a game control microcomputer 560.

  The RAM 55 is a backup RAM as a non-volatile storage means, part or all of which is backed up by a backup power source created on the power supply substrate 910. That is, even if the power supply to the gaming machine is stopped, a part or all of the contents of the RAM 55 is stored for a predetermined period (until the capacitor as the backup power supply is discharged and the backup power supply cannot be supplied). In particular, at least data (special symbol process flag, etc.) corresponding to the game state, that is, the control state of the game control means, and data indicating the number of unpaid winning balls are stored in the backup RAM. The data corresponding to the control state of the game control means is data necessary for restoring the control state before the occurrence of a power failure or the like based on the data when the power is restored after a power failure or the like occurs. Further, the data corresponding to the control state is defined as the data indicating the number of unpaid prize balls and the data indicating the game progress state. In this embodiment, it is assumed that the entire RAM 55 is backed up.

  A reset signal from the power supply board 910 is input to the reset terminal of the game control microcomputer 560. The reset signal from the power supply board 910 is also input to the reset terminal of the payout control microcomputer. When the reset signal becomes high level, the game control microcomputer 560 and the payout control microcomputer become operable, and when the reset signal becomes low level, the game control microcomputer 560 and the payout control microcomputer stop operating. It becomes a state. Accordingly, during the period in which the reset signal is at a high level, an allowable signal that allows the operation of the game control microcomputer 560 and the payout control microcomputer is output, and in the period in which the reset signal is at a low level, An operation stop signal for stopping the operations of the game control microcomputer 560 and the payout control microcomputer is output. Note that the reset circuit may be mounted on each electric component control board (including the main board 31), or a reset circuit is mounted on one or more of the plurality of electric component control boards, and a reset signal is output therefrom. May be supplied to another electric component control board.

  Furthermore, a power-off signal indicating that the power supply voltage from the power supply board 910 has decreased to a predetermined value or less is input to the input port of the basic circuit 53 via the payout control board 37. A clear signal indicating that the clear switch for instructing to clear the contents of the RAM is operated is input to the input port of the basic circuit 53.

  The clear signal is branched in the main board 31 and is also supplied to the payout control board 37. Note that the state of the clear signal input by the game control microcomputer 560 via the input port may be output to the payout control board 37 via the output port.

  In this embodiment, the effect control means (configured by the effect control microcomputer) mounted on the effect control board 80 receives the effect control command from the game control microcomputer 560 via the relay board 77. The display control and the like of the variable display device 9 that receives and variably displays decorative symbols are performed.

  FIG. 5 is a block diagram showing a circuit configuration of the main board 31 and signal lines of an effect control command transmitted from the main board 31 to the effect control board 80. As shown in FIG. 5, in this embodiment, the game control microcomputer 560 mounted on the main board 31 produces an effect control command by using eight signal lines CD0 to CD7 for transmitting the effect control signal. Transmit to the control board 80. In addition, a signal line of an effect control INT signal for transmitting and receiving a strobe signal is also wired between the main board 31 and the effect control board 80.

  As shown in FIG. 5, wiring from the start port switch 14a is connected to the main board 31. The main board 31 is also provided with wiring from the special variable winning ball apparatus 20 which is a big winning opening, and various switches 29a, 30a, 33a, 39a for detecting the winning of a game ball to other winning openings. It is connected. Further, the main board 31 is connected to a solenoid 16 for opening and closing the variable winning ball apparatus 15, a solenoid 21 for opening and closing the special variable winning ball apparatus 20, and a wiring to the solenoid 21A for switching the path in the special winning opening. .

  The main board 31 includes a game control microcomputer 560, an input driver circuit 58, and an output circuit 59. The game control microcomputer 560 operates in accordance with a clock circuit 501, a reset controller 502 that functions as a system reset means, a random number circuit 503a, 503b, a ROM 54 that stores a game control program, a RAM 55 that is used as a work memory, and a program. CPU 56, CTC 504 for sending an interrupt request signal to the CPU, serial communication circuit 505 for performing asynchronous serial communication with the CPU included in payout control board 37 and effect control board 80, and I / O port unit 57 are incorporated.

  In this embodiment, communication with the CPU of a board (for example, the payout control board 37 or the effect control board 80) different from the board (for example, the main board 31) on which the microcomputer incorporating the serial communication circuit 505 is mounted. However, the serial communication circuit 505 may perform serial communication with another CPU included in a board on which a microcomputer incorporating the serial communication circuit 505 is mounted. For example, when two microcomputers having the same configuration are mounted on the same substrate, serial communication circuits built in the microcomputers may perform serial communication with each other.

The clock circuit 501 outputs a reference clock signal CLK having a predetermined period generated by dividing the system clock signal by 2 ⁷ (= 128) to the random number circuits 503a and 503b. When a low level signal is input for a predetermined period, the reset controller 502 outputs a predetermined initialization signal to the CPU 56 and the random number circuits 503a and 503b to reset the game control microcomputer 560.

  Further, in this embodiment, as shown in FIG. 5, the game control microcomputer 560 is equipped with two random number circuits 503a and 503b having different ranges of random value values that can be generated. The random number circuit 503a is a random number circuit (hereinafter also referred to as a 12-bit random number circuit) that generates a 12-bit pseudo-random number. The 12-bit random number circuit 503a has a function of generating a random number having a value within a range that can be generated by 12 bits (that is, a range from 0 to 4095). The random number circuit 503b is a random number circuit (hereinafter also referred to as a 16-bit random number circuit) that generates a 16-bit pseudo-random number. The 16-bit random number circuit 503b has a function of generating a random number having a value in a range that can be generated in 16 bits (that is, a range from 0 to 65535). In this embodiment, the case where the game control microcomputer 560 includes two random number circuits is described. However, the game control microcomputer 560 may include three or more random number circuits. In this embodiment, when the 12-bit random number circuit 503a and the 16-bit random number circuit 503b are comprehensively expressed, or when indicating either the 12-bit random number circuit 503a or the 16-bit random number circuit 503b, This is called a random number circuit 503.

  Next, the configuration of the random number circuit 503 will be described. FIG. 6 is a block diagram illustrating a configuration example of the random number circuit 503. In this embodiment, the basic configurations of the 12-bit random number circuit 503a and the 16-bit random number circuit 503b are the same. 6, the random number circuit 503 includes a counter 521, a comparator 522, a count value permutation changing circuit 523, a clock signal output circuit 524, a count value update signal output circuit 525, a random value read signal output circuit 526, and a random number update. A system selection signal output circuit 527, a selector 528, a random number circuit activation signal output circuit 530, a random value storage circuit 531, an inversion circuit 532, a latch signal generation circuit 533, and a timer circuit 534 are included.

  In this embodiment, the random number circuit 503 determines whether or not the display result of variable display of a plurality of types of identification information is a specific display result (for example, the combination of display symbols of the special symbol display device 8 is a combination of jackpot symbols) A random number for determination is generated. When the game control microcomputer 560 determines that the specific display result is based on the random number generated by the random number circuit 503, the game state is shifted to a specific game state (for example, a big hit game state) advantageous to the player. . It should be noted that a random number for determination other than the jackpot symbol, such as a random number for probability variation determination for determining whether or not the random number generated by the random number circuit 503 is a probability variation, or a random number for variation pattern determination for determining a variation pattern for a special symbol. It may be used as

  The counter 521 receives a predetermined signal selected by the selector 528 and outputs a count value C in response to the signal input from the selector 528. In this case, the counter 521 inputs a predetermined initial value, and cyclically updates the count value C from the initial value to a predetermined final value according to a certain rule, and outputs it. Further, when the count value C is updated to the final value, the counter 521 outputs a notification signal indicating that the count value C has been updated to the final value to the CPU 56. In this embodiment, when a notification signal is output from the counter 521, the CPU 56 updates the initial value.

  In this embodiment, every time a signal is input from the selector 528 (every time a rising edge in the signal from the selector 528 is input), the counter 521 increments the count value C from “0” to “4095” by one. Count up. Further, when the counter 521 counts up the count value C to “4095”, the counter 521 outputs a notification signal indicating that the count value C has been updated to the final value to the CPU 56. Then, the CPU 56 inputs a notification signal from the counter 521 and updates the initial value. Then, the counter 521 counts up the count value C again from the initial value updated by the CPU 56 to “4095”. Further, when counting up to “4095”, the counter 521 starts counting from “0” again. Then, the counter 521 outputs a notification signal to the CPU 56 when it counts up to a value (final value) immediately before the updated initial value. In this embodiment, the comparator 522 outputs a notification signal to the counter 521 when all the count values are input, as will be described later. In this case, when the notification signal is input from the comparator 522, the counter 521 resets the count value to “0”.

  The comparator 522 determines whether the input count value is larger than the random number maximum value set in the random number maximum value setting register 535, and the count value is larger than the random number maximum value (exceeded the random number maximum value). ), A communication signal may be output to the counter 521. In this case, for example, when the comparator 522 determines that the count value exceeds the random number maximum value, the notification signal is output to the counter 521 before the clock signal output circuit 524 next outputs the random number generation clock signal SI1. . For example, consider a case where the random number maximum value “256” is set in the random number maximum value setting register 535. In this case, when the counter 521 counts up from “0” to “256” and further outputs the count value “257”, the comparator 522 determines that the input count value “257” exceeds the random number maximum value “256”. Determine and output a notification signal to the counter 521. When the notification signal is input from the comparator 522, the counter 521 updates the count value to “258” and outputs it without waiting for the input of the random number generation clock signal SI1 from the clock signal output circuit 524. By repeatedly executing the above processing, the comparator 522 determines that the count value exceeds the random number maximum value while inputting from the count value “257” to “4095”. Output a notification signal. The counter 521 repeatedly updates and outputs the count value without waiting for the input of the random number generation clock signal SI1 from the clock signal output circuit 524 while the notification signal is input from the comparator 522. By doing so, until the clock signal output circuit 524 next outputs the random number generation clock signal SI1, the count value is controlled to be counted up from “257” to “4095” at a high speed, Control is performed so that random numbers from “257” to “4095” are skipped (not stored in the random value storage circuit 531).

  The count value permutation change circuit 523 includes a count value permutation change register (RSC) 536, an update rule selection register (RRC) 542, and an update rule memory 543. The count value permutation change register 536 stores count value permutation change data “01h” for changing the permutation (order of arrangement from the initial value to the final value), which is the update order of the count value C counted up by the counter 521. . When the numerical value permutation change data “01h” is stored in the count value permutation change register 536, the count value permutation change circuit 523 displays the count value C permutation that the counter 521 counts up and updates. The permutation is changed to a different permutation from when “01h” is not stored. In this case, when the numerical value permutation change data “01h” is stored, the count value permutation changing circuit 523 switches the update rule used for changing the permutation of the count values. In addition, when the counter 521 starts updating the count value after switching the update rule used for changing the count value permutation, the count value permutation change data in the count value permutation change register 536 is initialized from “01h” by the CPU 56. The value is returned to “0 (= 00h)” (cleared).

  FIG. 7 is an explanatory diagram illustrating an example of the update rule selection register 542. The update rule selection register 542 is a register that sets an update rule used for rearranging the order of count values output from the counter 521 (changing the permutation). In this embodiment, by setting a register value in the update rule selection register 542, an update rule used for changing the permutation of count values output by the counter 521 is set. As shown in FIG. 7, the update rule selection register 542 is an 8-bit register, and the initial value is set to “0 (= 00h)”. The update rule selection register 542 is configured in a state where bits 0 to 3 can be written and read. In addition, the update rule selection register 542 is configured in a state where bits 4 to 7 cannot be written or read. Therefore, even if control is performed to write values to bits 4 to 7 of the update rule selection register 542, it is invalid, and all the values read from bits 4 to 7 are “0 (= 0000b)”.

  The value (register value) of the update rule selection register 542 is changed from “0 (= 00h)” to “15” in response to the count value permutation change data “01h” being written in the count value permutation change register 536. (= 0Fh) ”is updated cyclically. That is, each time the count value permutation data “01h” is written to the count value permutation change register 536, the register value of the update rule selection register 542 is incremented by “1” from “0”. Return to "0".

  FIG. 8 is an explanatory diagram showing an example of the update rule memory 543. As shown in FIG. 8, the update rule memory 543 stores the value (register value) of the update rule selection register 542 and the count value update rule in association with each other. In the example shown in FIG. 8, for example, when the register value 1 is set in the update rule selection register 542, it can be seen that the permutation of the count values output by the counter 521 is changed using the update rule B. In FIG. 8, the update rule A is the same update rule as that for the counter 521 to update the count value C, and is stored in the update rule memory 543 in association with the register value “0”. Also, in the update rule memory 543, update rules B to P different from the update rule in which the counter 521 updates the count value C are stored in association with the register values “1” to “15”.

  When the count value permutation change data “01h” is written in the count value permutation change register 536, the count value permutation change circuit 523 first counts from the counter 521 until the final count value “4095” is first input. The count value is output as it is according to the currently set update rule. The count value permutation changing circuit 523 changes the count value update rule when the final value “4095” of the count value is input from the counter 521. When the initial value is changed by the CPU 56, the count value permutation changing circuit 523 inputs the final value after the change (the value immediately before the initial value) from the counter 521, and updates the count value. Will be changed.

  The count value permutation change circuit 523 selects an update rule corresponding to the register value of the update rule selection register 542 from the update rule memory 543, and sets it as an update rule used for changing the count value permutation. The count value permutation changing circuit 523 changes the permutation from the initial value of the count value to the final value according to the set update rule when the counter 521 starts updating the count value again from the initial value “0”. To do. When the initial value is changed by the CPU 56, the count value permutation changing circuit 523 starts counting in accordance with the set update rule when the counter 521 starts updating the count value in order from the changed initial value. The permutation from the initial value to the final value will be changed. Then, the count value permutation change circuit 523 outputs a count value according to the changed permutation.

  In this embodiment, when the maximum random number value to be generated is limited by setting the random number maximum value in the random number maximum value setting register 535 described later, the count value permutation changing circuit 523 counts The value C is limited to the maximum random number or less, and the permutation is changed and output. For example, it is assumed that the random number maximum value “256” is set in the random number maximum value setting register 535, and the count value permutation changing circuit 523 changes the update rule A to the update rule B to change the count value permutation. Shall. In this case, the count value permutation changing circuit 523 changes the count value permutation to “256 → 255” according to the update rule B based on the random number maximum value “256” set in the random number maximum value setting register 535 of the comparator 522. → → → 0 "and output.

  As described above, when the count value permutation change data “01h” is written in the count value permutation change register 536, the count value permutation change circuit 523 changes the update rule to use the permutation of the count value C. Change and output. Therefore, the randomness of the random number generated by the random number circuit 503 can be improved.

  FIG. 9 is an explanatory diagram illustrating an example in which the count value permutation changing circuit 523 changes the permutation of count values output from the counter 521. As shown in FIG. 9, the CPU 56 writes the count value permutation change data “01h” into the count value permutation change register 536 at a predetermined timing. Then, 1 is added to the register value of the update rule selection register 542. For example, the register value of the update rule selection register 542 is updated from “0” to “1”. When the register value is updated, the count value permutation changing circuit 523 updates the “update rule A” corresponding to the register value “0” before the update until the final value “4095” of the count value is input from the counter 521 for the first time. The count value is updated according to "." At this time, the count value permutation changing circuit 523 outputs the count values in a permutation of “0 → 1 →... → 4095” according to the update rule A.

  When the final value “4095” of the count value is input from the counter 521, the count value permutation changing circuit 523 selects “update rule B” corresponding to the updated register value “1” from the update rule memory 543. To set. When the count value permutation changing circuit 523 starts to input the count values after the initial value “0” from the counter 521 again, the count value permutation changing circuit 523 changes the permutation of the count values according to the selected “update rule B” and outputs it. In this example, the count value permutation changing circuit 523 changes the permutation from “0 → 1 →... → 4095” to “4095 → 4094 →... → 0” and outputs the count value.

  Thereafter, the count value permutation change register 536 is reset in response to the count value permutation change circuit 523 starting the count value updating operation in accordance with the updated update rule, as will be described later. Then, until the next count value permutation change data “01h” is written to the count value permutation change register 536, the count value permutation change circuit 523 counts the permutation as “4095 → 4094 →. Continue to output values.

  When the count value permutation change data “01h” is written again to the count value permutation change register 536 by the CPU 56, the register value of the count value permutation change register 536 is updated from “1” to “2”. When the final value “4095” of the count value is input from the counter 521, the count value permutation changing circuit 523 selects and sets “update rule C” corresponding to the register value “2” from the update rule memory 543. . When the count value permutation changing circuit 523 starts to input the count value after the initial value “0” again from the counter 521, the count value permutation changing circuit 523 updates and outputs the count value permutation in accordance with the “update rule C” selected and set. In this example, the count value permutation changing circuit 523 changes the permutation from “4095 → 4094 →... → 0” to “1 → 3 →... → 4095 → 0 →. Is output.

  As described above, after the count value permutation change register 536 is reset, the count value permutation data “01h” is written again in the count value permutation change register 536, so that the count value permutation can be further changed.

  FIG. 10 is an explanatory diagram illustrating an example of the count value permutation change register 536. The count value permutation change register 536 is a register that sets count value permutation change data “01h” for changing the permutation of count values counted up by the counter 521. As shown in FIG. 10, the count value permutation change register 536 is a readable 8-bit register, and the initial value is set to “0 (= 00h)”. Further, count value permutation change register 536 is configured such that only bit 0 can be written and read. That is, count value permutation change register 536 is configured such that bits 1 to 7 cannot be written or read. Therefore, even if control is performed to write values to bits 1 to 7 of the count value permutation change register 536, it is invalid, and all the values read from bits 1 to 7 are “0 (= 0000000b)”.

  Note that the value of the count value permutation change register 536 is reset by the CPU 56 in response to the count value permutation change circuit 523 starting a count value update operation in accordance with the updated update rule. In this case, the CPU 56 returns the value written in the count value permutation change register 536 from the count value permutation change data “01h” to the initial value “0 (= 00h)”.

  The comparator 522 includes a random number maximum value setting register (RMX) 535 that stores random number maximum value setting data for designating the maximum value of random R (random number maximum value). The comparator 522 limits the update range of the count value updated by the counter 521 according to the random number maximum value indicated in the random number maximum value setting data stored in the random number maximum value setting register 535. In this embodiment, the comparator 522 has a random number maximum value (for example, “00FFh”) indicated by the count value input from the counter 521 and the random number maximum value setting data (for example, “00FFh”) stored in the random number maximum value setting register 535. 256 "). When the comparator 522 determines that the input count value is equal to or less than the random number maximum value, the comparator 522 outputs the input count value to the random value storage circuit 531.

  In this embodiment, the comparator 522 specifically performs the following control. The comparator 522 obtains the initial value of the count value from the CPU 56 when updating the initial value of the count value, and obtains the number of count values from the initial value to the maximum random number. For example, when the initial value of the count value is “157” and the maximum random number value is “256”, the comparator 522 calculates the number of count values from the initial value to the maximum random number value as “100”. The comparator 522 counts up how many count values have been input from the initial value as the count values are input from the count value permutation changing circuit 523. When the number of input count values from the initial value reaches “100”, the comparator 522 determines that all count values from the initial value “157” to the maximum value “256” have been input. Then, the comparator 522 outputs a notification signal indicating that all count values have been input to the counter 521. By determining based on the number of count values, even when the count value permutation circuit 523 has changed the count value permutation, the comparator 522 limits the update range of the count value to the maximum random number or less. When all count values are input, a notification signal can be output to the counter 521.

  An operation in which the comparator 522 limits the update range of the count value will be described. In this example, a case where the count value permutation changing circuit 523 selects the update rule A and the random number maximum value “256” is set in the random number maximum value setting register 535 will be described.

  While the counter 521 is updating the count value from “0” to “256”, the count value permutation changing circuit 523 updates based on the random number maximum value “256” set in the random number maximum value setting register 535. In accordance with rule A, the count values from “0” to “256” are output to the comparator 522 as they are. In this case, the count value permutation changing circuit 523 receives the value of the random number maximum value “256” from the comparator 522, determines whether the count value input from the counter 521 is larger than the random number maximum value, and the update rule is changed. Even when it is set (for example, update rule B), the count values from “257” to “4095” are compared based on the random number maximum value “256” set in the random number maximum value setting register 535. The data is not output to the device 522. For example, when the initial value is set to “0” and the count value is updated to the final value “256”, the counter 521 outputs a notification signal to the CPU 56. When the notification signal is output, the CPU 56 changes the initial value of the count value of the counter 521. In this example, it is assumed that the initial value is changed to “50” by the CPU 56.

  Based on the update rule A, while the count value is input from “0” to “255” from the count value permutation changing circuit 523, the comparator 522 inputs the count value below the maximum random number “256”. Therefore, the input count value is output to the random value storage circuit 531 as it is. Next, when the count value input from the count value permutation changing circuit 523 reaches “256”, the comparator 522 outputs the input count value to the random value storage circuit 531 and all the values from the initial value to the maximum value. A notification signal indicating that the count value is input is output to the counter 521. Specifically, the comparator 522 receives an initial value (“0” in this example) of the count value from the CPU 56 when changing the initial value of the count value, and the random number maximum value (the main value) from the initial value “0”. In the example, the number of count values up to “256” (in this example, “257”) is obtained. When the number of count values input from the count value permutation changing circuit 523 reaches 257, a notification signal indicating that all count values have been input is output to the counter 521. In this example, since the CPU 56 changes the initial value to “50”, the counter 521 does not reset the count value even when the notification signal is input from the comparator 522, and the changed initial value “50”. The count value is updated.

  While the counter 521 updates the count value from the changed initial value “50” to “256”, the count value permutation changing circuit 523 sets the random number maximum value “256” set in the random number maximum value setting register 535. Based on the update rule A, the count values from “50” to “256” are output to the comparator 522 as they are. Further, the count value permutation changing circuit 523 does not output the count values from “257” to “4095” to the comparator 522 based on the random number maximum value “256” set in the random number maximum value setting register 535. When the count value to be updated by the counter 521 makes one round (when updated 257 times), when the count value permutation change data is written in the count value permutation change register 536, the count value permutation change circuit 523 Change the permutation of count values and output. For example, when the update rule is changed to the update rule B, the count value permutation changing circuit 523 changes the count value permutation from “256 → 255 →... 50” and outputs the result.

  While the count values from “256” to “50” are input from the count value permutation changing circuit 523, the comparator 522 outputs the input count value as it is to the random value storage circuit 531. Next, when the count value input from the count value permutation change circuit 523 reaches “50”, the comparator 522 outputs the input count value to the random value storage circuit 531 and all the values from the initial value to the maximum value. A notification signal indicating that the count value is input is output to the counter 521. Specifically, the comparator 522 receives the initial count value (“50” in this example) from the CPU 56 when the initial count value is changed, and the random number maximum value (this In the example, the number of count values up to “256” (in this example, “207”) is obtained. When the number of count values input from count value permutation changing circuit 523 reaches 207, a notification signal indicating that all count values have been input is output to counter 521.

  Even when the count value permutation changing circuit 523 changes the count value permutation, the comparator 522 outputs a notification signal to the counter 521 when the number of count values reaches 207. By doing so, even if the permutation of the count values is changed, the notification signal is counted based on the input of all the count values from the initial value “50” to the maximum value “256”. 521 can be output.

  When the notification signal is input from the comparator 522, the counter 521 resets the initial value of the count value and returns it to “0”. Then, the counter 521 updates the count value from “0”. When the value of the counter 521 is updated again from “0”, the count value permutation changing circuit 523 outputs the count values from “49” to “0” to the comparator 522 based on the count value from the counter 521. The comparator 522 outputs the count value to the random value storage circuit 531 based on the count value input from the count value permutation changing circuit 523. When the counter 521 updates the count value to the final value (“49” in this example), the counter 521 outputs a notification signal to the CPU 56. When the notification signal is output, the initial value of the count value of the counter 521 is changed again by the CPU 56.

  By repeating the operation as described above, the comparator 522 causes the counter 521 to continuously count up the count value from “0” to the random number maximum value “256”, and the value from “0” to “256”. Is stored in the random value storage circuit 531 as a random R (random number value). That is, the comparator 522 limits the update range of the count value to the random number maximum value “256” or less, and causes the counter 521 to update the count value.

  FIG. 11 is an explanatory diagram showing an example of the random number maximum value setting register 535. FIG. 11A shows an example of the random number maximum value setting register 535 installed in the 12-bit random number circuit 503a. FIG. 11B shows an example of the random number maximum value setting register 535 installed in the 16-bit random number circuit 503b. First, the random number maximum value setting register 535 mounted in the 12-bit random number circuit 503a will be described. As shown in FIG. 11A, in the 12-bit random number circuit 503a, the random number maximum value setting register 535 is a 16-bit register, and the initial value is set to “4095 (= 0FFFh)”. The random number maximum value setting register 535 is configured so that bits 0 to 11 can be written and read. The random number maximum value setting register 535 is configured such that bits 12 to 15 cannot be written or read. Therefore, in the 12-bit random number circuit 503a, even if control is performed to write values to bits 12 to 15 of the random number maximum value setting register 535, the values read from bits 12 to 15 are all “0 (= 0000b)”. It is.

  The random number maximum value set in the random number maximum value setting register 535 has a predetermined lower limit value. In this embodiment, when random number maximum value setting data “0000h” to “00FEh” designating a value smaller than the lower limit value “256” is written in the random number maximum value setting register 535, the CPU 56 stores the random number maximum value setting register. The random number maximum value setting data “0FFFh” for specifying the initial value “4095” is set again in 535. That is, the random number maximum value that can be set in the random number maximum value setting register 535 is from “256” to “4095”, and when the CPU 56 determines that a value smaller than the lower limit value “256” is set, the random number maximum value Is reset to a predetermined value “4095”. The CPU 56 controls the random number maximum value setting register 535 in which the random number maximum value setting data is written to be unwritable until the game control microcomputer 560 is system reset by the reset controller 502.

  Next, the random number maximum value setting register 535 mounted in the 16-bit random number circuit 503b will be described. As shown in FIG. 11B, in the 16-bit random number circuit 503b, the random number maximum value setting register 535 is a 16-bit register, and the initial value is set to “65535 (= FFFFh)”. Further, in the 16-bit random number circuit 503b, the random number maximum value setting register 535 is configured in a state in which all bits 0 to 15 can be written and read.

  When random number maximum value setting data “0000h” to “00FEh” for designating a value smaller than the lower limit value “256” is written in the random number maximum value setting register 535, the CPU 56 sets the initial value in the random number maximum value setting register 535 to the initial value. The random number maximum value setting data “FFFFh” specifying the value “65535” is reset. That is, the random number maximum value that can be set in the random number maximum value setting register 535 is from “256” to “65535”, and when the CPU 56 determines that a value smaller than the lower limit value “256” is set, the random number maximum value Is reset to a predetermined value “65535”. The CPU 56 controls the random number maximum value setting register 535 in which the random number maximum value setting data is written to be unwritable until the game control microcomputer 560 is system reset by the reset controller 502.

  The clock signal output circuit 524 includes a cycle setting register (RPS) 537 for storing cycle setting data for designating the cycle of the clock signal output to the selector 528 and the inverting circuit 532 (that is, the count value update cycle). The clock signal output circuit 524 divides the reference clock signal CLK input from the clock circuit 501 mounted on the game control microcomputer 560 based on the cycle setting data stored in the cycle setting register 537, and generates a random number circuit. A clock signal (random number generating clock signal SI1) used to generate a random number value is generated inside 503. By doing so, the clock signal output circuit 524 operates to output the random number generation clock signal SI1 for updating the count value C to the counter 521 on condition that the clock signal has been input a predetermined number of times. . The period setting data is data for setting how many times the reference clock signal CLK input from the clock circuit 501 is to be divided. The clock output circuit 524 outputs the generated random number generating clock signal SI1 to the selector 528 and the inverting circuit 532. For example, when the cycle setting data “0Fh (= 16)” is written in the cycle setting register 537, the clock signal output circuit 524 divides the reference clock signal CLK input from the clock circuit 501 by 16, and generates random numbers. A clock signal SI1 is generated. In this case, the cycle of the random number generating clock signal SI1 generated by the clock signal output circuit 524 is “cycle of system clock signal × 128 × 16”.

  FIG. 12 is an explanatory diagram showing an example of the cycle setting register 537. As shown in FIG. 12, the cycle setting register 537 is an 8-bit register, and the initial value is set to “256 (= FFh)”. The cycle setting register 537 is configured in a state where both writing and reading are possible.

  In addition, a predetermined lower limit value is determined for the value of the cycle setting data set in the cycle setting register 537. In this embodiment, when the cycle setting data “00h to 06h” designating a value smaller than the lower limit value “system clock signal cycle × 128 × 7” is written in the cycle setting register 537, the CPU 56 In 537, the cycle setting data “07h” for specifying the lower limit value “system clock signal cycle × 128 × 7” is reset. That is, the period that can be set in the period setting register 537 is “system clock signal period × 128 × 7” to “system clock signal period × 128 × 256”, and the CPU 56 is set to a value smaller than the lower limit value. If it is determined that the cycle setting data is correct, the cycle setting data is reset. The CPU 56 controls the period setting register 537 in which the period setting data is written to be unwritable until the game control microcomputer 560 is system-reset by the reset controller 502.

  Note that, without setting the cycle setting data as the lower limit value in the cycle setting register 537, based on the set cycle setting data, for example, the clock signal output circuit 524 directly supplies the reference clock signal CLK to the counter 521 and the inverting circuit 532. You may make it output. In this case, the CPU 56 does not need to perform processing for setting the value of the cycle setting data set in the cycle setting register 537 by comparing it with the lower limit value. The counter 521 updates the count value C every time the reference clock signal CLK is input from the clock signal output circuit 524.

  The count value update signal output circuit 525 includes a count value update register (RGN) 538 that stores count value update data “01h”. The count value update data is data for requesting update of the count value. The count value update signal output circuit 525 outputs the count value update signal SI3 to the selector 528 in response to the count value update data “01h” being written in the count value update register 538.

  FIG. 13 is an explanatory diagram illustrating an example of the count value update register 538. As shown in FIG. 13, the count value update register 538 is an unreadable 8-bit register and is configured so that only bit 0 can be written. Therefore, even if control is performed to write a value to bits 1 to 7 of the count value update register 538, it is invalidated.

  The random value read signal output circuit 526 includes a random value take-in register (RLT) 539 for storing random value take-in data “01h”. The random value acquisition data is data for requesting acquisition of the count value to the random value storage circuit 531. The random value read signal output circuit 526 generates a random value read signal for requesting reading of the random value in response to the random value fetch data “01h” being written in the random value fetch register 539. Output to the circuit 533.

  FIG. 14 is an explanatory diagram showing an example of the random value fetch register 539. As shown in FIG. 14, the random value fetch register 539 is an unreadable 8-bit register. The random value fetch register 539 is configured so that only bit 0 can be written. In other words, even if control is performed to write a value to bits 1 to 7 of the random value fetch register 539, it is invalidated.

  The random number update method selection signal output circuit 527 includes a random number update method selection register (RTS) 540 that stores random number update method selection data. The random number update method selection data is data for designating one of the random number update methods that is a method for updating the value of the random R. The random number update method selection signal output circuit 527 responds to the random number update method selection data written in the random number update method selection register 540 with a random number corresponding to the random number update method specified by the written random number update method selection data. The update method selection signal is output to the selector 528 and the latch signal generation circuit 533.

  FIG. 15A is an explanatory diagram illustrating an example of the random number update method selection register 540. As shown in FIG. 15A, the random number update method selection register 540 is an 8-bit register, and the initial value is set to “00h”. The random number update method selection register 540 is configured in a state where bits 0 to 1 can be written and read. The random number update method selection register 540 is configured in a state where bits 2 to 7 cannot be written or read. Therefore, even if control is performed to write a value to bits 2 to 7 of the random number update method selection register 540, it is invalid, and all the values read from bits 2 to 7 are “0 (= 000000b)”.

  FIG. 15B is an explanatory diagram of an example of random number update method selection data written to the random number update method selection register 540. As shown in FIG. 15B, the random number update method selection data is composed of 2-bit data. The random number update method selection data “01b” is used to specify the first random number update method. The random number update method selection data “10b” is used to specify the second random number update method. In this embodiment, the first random number update method is a method of updating the count value triggered by the output of the count value update signal SI3 from the count value update signal output circuit 525. The second random number update method is a method of updating the count value triggered by the output of the random number generation clock signal SI1 from the clock signal output circuit 524. Further, when the random number update method selection data “01b” or “10b” is written in the random number update method selection register 540, the random number circuit 503 is ready to be activated. On the other hand, when the random number update method selection data “00b” or “11b” is written to the random number update method selection register 540, the random number circuit 503 cannot be activated.

  The selector 528 selects either the count value update signal SI 3 output from the count value update signal output circuit 525 or the random number generation clock signal SI 1 output from the clock signal output circuit 524 and outputs the selected signal to the counter 521. When a random number update method selection signal (also referred to as a first random number update method selection signal) corresponding to the first random number update method is input from the random number update method selection signal output circuit 527, the selector 528 outputs a count value update signal. The count value update signal SI3 output from the circuit 525 is selected and output to the counter 521. On the other hand, when a random number update method selection signal (also referred to as a second random number update method selection signal) corresponding to the second random number update method is input from the random number update method selection signal output circuit 527, the selector 528 outputs a clock signal. The random number generation clock signal SI 1 output from the circuit 524 is selected and output to the counter 521. When the first update method selection signal is input from the random number update method selection signal output circuit 527, the selector 528 receives a clock signal according to the count value update signal SI3 output from the count value update signal output circuit 525. A numerical value update instruction signal for instructing update of numerical data synchronized with the random number generation clock signal SI1 output from the output circuit 524 may be output to the counter 521.

  The random number circuit activation signal output circuit 530 includes a random number circuit activation register (RST) 541 that stores random number circuit activation data “80h”. The random number circuit activation data is data for requesting activation of the random number circuit 503. When random number circuit activation data “80h” is written to the random number circuit activation register 541, the random number circuit activation signal output circuit 530 outputs a predetermined random number circuit activation signal to the counter 521 and the clock signal output circuit 537, and the counter 521 and the clock The signal output circuit 524 is turned on. The random number circuit 503 is activated by starting the count value updating operation by the counter 521 and the internal clock signal output operation by the clock signal output circuit 524.

  FIG. 16 is an explanatory diagram illustrating an example of the random number circuit activation register 541. As shown in FIG. 16, the random number circuit activation register 541 is an 8-bit register, and the initial value is set to “00h”. The random number circuit activation register 541 is configured such that only bit 7 can be written and read. The random number circuit activation register 541 is configured in a state in which bits 0 to 6 cannot be written or read. That is, even if control is performed to write a value to bits 0 to 6 of the random number circuit activation register 541, the value is invalid, and all values read from bits 0 to 6 are “0 (= 000000b)”.

  The random value storage circuit 531 is a 16-bit register, for example, and stores a random R value that is a random number used in the jackpot determination in the game control process. The random value storage circuit 531 stores the count value C output from the counter 521 via the comparator 522 as a random R value in response to the input of the latch signal SL from the latch signal generation circuit 533. Each time the latch signal SL is input from the latch signal generation circuit 533, the random value storage circuit 531 reads the count value C updated by the counter 521 and stores the random R value.

  FIG. 17 is a circuit diagram showing a configuration example of the random value storage circuit 531. As shown in FIG. 17, the random value storage circuit 531 includes two AND circuits 201 and 203, two NOT circuits 202 and 204, 16 flip-flop circuits 2101 to 2116, and 16 OR circuits. 2201-2216.

  As shown in FIG. 17, the input terminal of the AND circuit 201 is connected to the output terminal of the latch signal generation circuit 533 and the output terminal of the NOT circuit 204, and the output terminal is connected to the input terminal of the NOT circuit 202 and the flip-flop circuit 2101. Are connected to clock terminals Clk1 to Clk16. The input terminal of the NOT circuit 202 is connected to the output terminal of the AND circuit 201, and the output terminal is connected to one input terminal of the AND circuit 203.

  The input terminal of the AND circuit 203 is connected to the output terminal of the NOT circuit 202 and the CPU 56 mounted on the game control microcomputer 560, and the output terminal is connected to the input terminal of the NOT circuit 204. The input terminal of the NOT circuit 204 is connected to the output terminal of the AND circuit 203, and the output terminal is connected to one input terminal of the AND circuit 201 and one input terminal of the OR circuits 2201 to 2216.

  Input terminals D1 to D16 of the flip-flop circuits 2101 to 2116 are connected to an output terminal of the comparator 522. The clock terminals Clk1 to Clk16 of the flip-flop circuits 2101 to 2116 are connected to the output terminal of the AND circuit 201, and the output terminals Q1 to Q16 are connected to the other input terminals of the OR circuits 2201 to 2216.

  The input terminals of the OR circuits 2201 to 2216 are connected to the output terminal of the NOT circuit 204 and the output terminals of the flip-flop circuits 2101 to 2116, and the output terminals are connected to the CPU 56 mounted on the game control microcomputer 560. .

  The operation of the random value storage circuit 531 will be described. FIG. 18 is a timing chart showing the timing at which each signal is input to the random value storage circuit 531 and the timing at which the random value storage circuit 531 outputs each signal. As shown in FIG. 18, when the output control signal SC (high level signal in this example) is not input from the CPU 56 mounted on the game control microcomputer 560 (that is, to one input terminal of the AND circuit 203). When the latch signal SL is input from the latch signal generation circuit 533 (when the input is at a low level) (at the timings T1, T2, and T7 in the example illustrated in FIG. 18), the input to the two input terminals of the AND circuit 201 is performed. Both inputs are high. Therefore, the signal SR output from the output terminal of the AND circuit 201 is at a high level. The signal SR output from the AND circuit 201 is input to the clock terminals Clk1 to Clk16 of the flip-flop circuits 2101 to 2116.

  The flip-flop circuits 2101 to 2116 respond to the rising edges of the signal SR input from the clock terminals Clk1 to Clk16, and receive the bit data C1 to C1 of the count value C input from the comparator 522 via the input terminals D1 to D16. C16 is latched and stored as bit data R1 to R16 of a random value. The flip-flop circuits 2101 to 2116 output random R bit data R1 to R16 to be stored from the output terminals Q1 to Q16.

  When the output control signal SC is not input (in the example shown in FIG. 18, the period up to the timing T3 and the period after the timing T6), the input to one input terminal of the AND circuit 203 is at the low level. The signal SG output from the output terminal of the circuit 203 is at a low level. The signal SG output from the AND circuit 203 is inverted in the NOT circuit 204 to be a high level signal. A high level signal is input from the NOT circuit 204 to one input terminal of the OR circuits 2201 to 2216.

  As described above, since the input to one of the input terminals of the OR circuits 2201 to 2216 is at a high level, the OR is input regardless of whether the signal input to the other input terminal is at a high level or a low level. The circuits 2201 to 2216 output high level signals. That is, the signals SO1 to SO16 output from the OR circuits 2201 to 2216 are all at a high level regardless of whether the values of the input random R bit data R1 to R16 are “0” or “1”. (“1”). By doing so, the value output from the random value storage circuit 531 is always “65535 (= 1111111111111111b)”, and the random R cannot be read from the random value storage circuit 531. That is, even if an attempt is made to read a random number from the random value storage circuit 531, only the same value “65535” can always be read from the random value storage circuit 531, and when the output control signal SC is not input, the random value storage circuit 531 becomes an unreadable (disabled) state. When the 16-bit random number circuit 503b is used, the value “65535” as the random number value may be used. In this case, even if the game control microcomputer 560 reads the value “65535”, it cannot determine whether the value is a random number or an unreadable state. Therefore, in the determination table for each jackpot determination shown in FIG. 37, when the random R is “65535”, it may be set to determine “lost” in advance.

  When the output control signal SC is input from the CPU 56 when the latch signal SL is not input from the latch signal generation circuit 533 (in the example shown in FIG. 18, the period from the timing T4 to the timing T6), Since the inputs to the two input terminals are both at the high level, the signal SG output from the output terminal of the AND circuit 203 is at the high level. The signal SG output from the AND circuit 203 is inverted in the NOT circuit 204 to be a low level signal. A low level signal is input from the NOT circuit 204 to one input terminal of the OR circuits 2201 to 2216.

  As described above, since the input to one input terminal of the OR circuits 2201 to 2216 is at a low level, when the signal input to the other input terminal is at a high level, the output from the output terminals of the OR circuits 2201 to 2216 is high. A level signal is output. In addition, when a signal input to the other input terminal of the OR circuits 2201 to 2216 is at a low level, a low level signal is output from the OR circuits 2201 to 2216. That is, the values of the random R bit data R1 to R16 input to the other input terminals of the OR circuits 2201 to 2216 are unchanged from the output terminals of the OR circuits 2201 to 2216 (that is, the values of the bit data R1 to R16 are “ “1” is output when it is “1” and “0” when it is “0”). By doing so, random R can be read from the random value storage circuit 531. That is, when the output control signal SC is input, the random value storage circuit 531 is in a readable (enable) state.

  However, if the latch signal SL is input from the latch signal generation circuit 533 before the output control signal SC is input from the CPU 56, the input to one input terminal of the AND circuit 203 is at a low level. Even if the output control signal SC is input while the signal SL is being input (in the example shown in FIG. 18, the period from the timing T3 to the timing T4), the signal SG output from the output terminal of the AND circuit 203. Remains low. The signal SG output from the AND circuit 203 is inverted in the NOT circuit 204 to be a high level signal. A high level signal is input from the NOT circuit 204 to one input terminal of the OR circuits 2201 to 2216.

  As described above, since the input to one of the input terminals of the OR circuits 2201 to 2216 is at a high level, the OR is input regardless of whether the signal input to the other input terminal is at a high level or a low level. The signals SO1 to SO16 output from the circuits 2201 to 2216 are all at a high level. Even though the output control signal SC is input, the random R cannot be read from the random value storage circuit 531. That is, when the latch signal SL is input, the random value storage circuit 531 cannot receive the output control signal SC. When the 16-bit random number circuit 503b is used, the value “65535” as a random number value may be used. In this case, even if the game control microcomputer 560 reads the value “65535”, it cannot determine whether the value is a random number or an unreadable state. Therefore, in the determination table for each jackpot determination shown in FIG. 27, when the random R is “65535”, it may be set to determine “lost” in advance.

  In addition, when the output control signal SC is input from the CPU 56 before the latch signal SL is input from the latch signal generation circuit 533, the input to one input terminal of the AND circuit 201 is at a low level. Even if the latch signal SL is input while the control signal SC is being input (timing T5 in the example shown in FIG. 18), the signal SR output from the output terminal of the AND circuit 201 remains at the low level. It becomes. Therefore, the signal SR input to the clock terminals Clk1 to Clk16 of the flip-flop circuits 2101 to 2116 does not rise from the low level to the high level, and the random R bit data R1 to R16 stored in the flip-flop circuits 2101 to 2116. Although the latch signal SL is input, the stored random number is not updated. That is, when the output control signal SC is input, the random value storage circuit 531 cannot receive the latch signal SL.

  The inverting circuit 532 generates the inverted clock signal SI2 in which the polarity of the clock signal is inverted by inverting the signal level in the random number generating clock signal SI1 input from the clock signal output circuit 524. Further, the inverting circuit 532 outputs the generated inverted clock signal SI2 to the latch signal generating circuit 533.

  The latch signal generation circuit 533 is configured using a selector, a flip-flop circuit, and the like. The latch signal generation circuit 533 receives the random number read signal from the random number read signal output circuit 526 and the inverted clock signal SI2 from the inversion circuit 532, and stores the random value in the random value storage circuit 531. SL is output. The latch signal generation circuit 533 outputs the latch signal SL in accordance with the random value update method designated by the random number update method selection signal from the random number update method selection signal output circuit 527. In this case, when the first random number update method selection signal output circuit 527 receives the first random number update method selection signal output circuit 527, the latch signal generation circuit 533 selects the inverted clock signal SI2 output from the inversion circuit 532, and the latch signal It outputs to the random value storage circuit 531 as SL. On the other hand, when the second random number update method selection signal is input from the random number update method selection signal output circuit 527, the latch signal generation circuit 533 inverts the random value read signal output from the random value read signal output circuit 526. In synchronization with the rising edge of the inverted clock signal SI2 output from the circuit 532, the latch signal SL is output to the random value storage circuit 531.

  The timer circuit 534 inputs a winning detection signal SS indicating that a winning of a game ball to the starting port 14 has been detected from the starting port switch 14a. The timer circuit 534 measures the time during which the winning detection signal SS is continuously input from the start port switch 14a. Then, when the measurement time reaches a predetermined period (for example, 3 ms), the timer circuit 534 writes the random number value capture data “01h” in the random value capture register 539 of the random value read signal output circuit 526. For example, the timer circuit 534 is configured by an up counter or a down counter that is activated in response to the input of a high level signal. The timer circuit 534 receives the reference clock signal CLK sequentially input from the clock circuit 501 while the input from the start port switch 14a is at a high level (that is, while the winning detection signal SS is continuously input). Count up or down. Then, when the count value to be counted up or down reaches a value corresponding to 3 ms, the timer circuit 534 determines that the winning detection signal SS is input from the start port switch 14a, and receives the random number value capture data “01h”. Write to the random value fetch register 539.

  Next, the configuration of the serial communication circuit 505 will be described. The serial communication circuit 505 performs serial communication with each control board (for example, the payout control board 37 and the effect control board 80) in a data format using a full duplex method, an asynchronous method, and standard NRZ (non-return zero) encoding. Do. The serial communication circuit 505 receives various data (for example, a prize ball ACK command) from a transmission unit that transmits various data (for example, a prize ball number command and an effect control command) to each control board. Part.

  FIG. 19 is a block diagram illustrating a configuration example of the transmission unit of the serial communication circuit 505. FIG. 20 is a block diagram illustrating a configuration example of a receiving unit of the serial communication circuit 505. The serial communication circuit 505 includes a baud rate register 702, a baud rate generation circuit 703, two status registers 705 and 706, three control registers 707, 708, and 709, a transmission data register 710, a reception data register 711, a transmission shift register 712, and a reception. Shift register 713, interrupt control circuit 714, transmission format / parity generation circuit 715, and reception format / parity check circuit 716. As shown in FIG. 19, the transmission unit of the serial communication circuit 505 includes a baud rate register 702, a baud rate generation circuit 703, a status register A 705, control registers 707, 708, and 709, and a transmission data register 710. , A transmission shift register 712, an interrupt control circuit 714, and a transmission format / parity generation circuit 715. As shown in FIG. 20, the receiving unit of the serial communication circuit 505 includes a baud rate register 702, a baud rate generation circuit 703, status registers 705 and 706, control registers 707, 708, and 709, received data, among these components. The register 711, the reception shift register 713, the interrupt control circuit 714, and the reception format / parity check circuit 716 are configured.

  In the serial communication circuit 505, the transmission unit and the reception unit are actually configured using a common circuit. As described above, the serial communication circuit 505 functions as a transmission circuit or a reception circuit by properly using each component of the serial communication circuit 505.

  First, the data format of data transmitted and received by the serial communication circuit 505 with each control board will be described. FIG. 21 is an explanatory diagram illustrating an example of a data format of data transmitted / received by the serial communication 505 to / from each control board. As shown in FIG. 21, the data format of data transmitted and received by the serial communication circuit 505 is configured with a start bit, data, and stop bits as one frame. Further, the data length of data transmitted / received by the serial communication circuit 505 can be set to either 8 bits or 9 bits by performing an initial setting in a serial communication circuit setting process described later. FIG. 21A shows an example of a data format when the data length is set to 8 bits. FIG. 21B is an example of a data format when the data length is set to 9 bits.

  As shown in FIG. 21, the data format of data transmitted and received by the serial communication circuit 505 is a start bit (logic “0”) indicating the start of one frame after an idle line of high level (logic “1”). ")including. The data format includes 8-bit or 9-bit transmission / reception data after the start bit. The data format includes a stop bit (logic “1”) indicating the end of one frame after transmission / reception data.

  The serial communication circuit 505 transmits / receives data first from the least significant bit (bit 0) of transmission / reception data according to the data format shown in FIG. Further, if initial setting is performed in a serial communication circuit setting process described later, it is possible to set so that a parity bit is added to transmission / reception data. When a setting is made to add a parity bit, the most significant bit of the transmission / reception data is used as a parity bit (odd parity or even parity). For example, when the data length is set to 8 bits, bit 7 of transmission / reception data is used as a parity bit. For example, when the data length is set to 9 bits, bit 8 of transmission / reception data is used as a parity bit.

  The baud rate generation circuit 703 generates a baud rate used by the serial communication circuit 505 based on a clock signal output from the clock circuit 501 and a setting value (also referred to as a baud rate setting value) set in the baud rate register 702. In this case, the baud rate generation circuit 703 obtains the baud rate using a predetermined calculation formula based on the clock signal and the baud rate setting value. For example, the baud rate generation circuit 703 obtains the baud rate used by the serial communication circuit 505 using equation (1).

Baud rate = clock frequency / (baud rate set value x 16) Equation (1)

  FIG. 22 shows a baud rate register 702 that sets a predetermined set value for designating a baud rate value generated by the baud rate generation circuit 703. For example, it is assumed that the baud rate register 702 obtains the baud rate using the equation (1) and the clock frequency is 3 MHz. In this case, if the desired target baud rate is 1200 bps, the setting value “156” is set in the baud rate register 702. Then, the baud rate generation circuit 703 generates the baud rate “1201.92 bps” using the equation (1) based on the clock frequency “3 MHz” and the baud rate set value “156”. The baud rate register 702 is a 16-bit register, and an initial value is set to “0 (= 00h)”. The baud rate register 702 is configured such that bits 0 to 12 can be written and read. Further, the baud rate register 702 is configured such that bits 13 to 15 cannot be written or read. Therefore, even if a control for writing a value to bits 13 to 15 of the baud rate register 702 is performed, the value is invalid and all the values read from the bits 13 to 15 are “0 (= 0000b)”.

  FIG. 23A is an explanatory diagram illustrating an example of the control register A707. The control register A 707 is a register for setting the communication format of the serial communication circuit 505. In this embodiment, the communication format of the serial communication circuit 505 is set by setting the value of each bit of the control register A707. In the control register A707, communication format setting data for setting a communication format such as a data format of transmission / reception data and various communication methods is set. As shown in FIG. 23A, the control register A707 is an 8-bit register, and the initial value is set to “0 (= 00h)”. Control register A 707 is configured such that bits 0 to 4 can be written and read. Control register A 707 is configured such that bits 5 to 7 cannot be written or read. Therefore, even if control is performed to write a value to bits 5 to 7 of the control register A707, it is invalid, and all the values read from bits 5 to 7 are “0 (= 0000b)”.

  FIG. 23B is an explanatory diagram of an example of communication format setting data set in the control register A707. As shown in FIG. 23B, setting data for setting the data length of data to be transmitted and received is set in bit 4 (bit name “M”) of the control register A707. As shown in FIG. 23B, by setting bit 4 to “0”, the data length of the transmission / reception data is set to 8 bits. Further, by setting bit 4 to “1”, the data length of the transmission / reception data is set to 9 bits.

  In bit 3 (bit name “WAKE”) of the control register A707, setting data for setting a wake-up method for waking up the receiver circuit (the receiving unit of the serial communication circuit 505) in the standby state. Is set. As shown in FIG. 23 (B), by setting bit 3 to “0”, an idle line wakeup method for wakeup when an idle line is recognized is set. In addition, by setting bit 3 to “1”, an address mark wakeup method for wakeup by recognizing a predetermined address mark is set.

  In bit 2 (bit name “ILT”) of the control register A707, setting data for selecting an idle line detection method of received data is set. As shown in FIG. 23B, by setting bit 2 to “0”, a detection method for detecting an idle line after the start bit included in the received data is set. In addition, by setting bit 2 to “1”, a detection method for detecting an idle line after a stop bit included in received data is set.

  Setting data for setting whether to use the parity function is set in bit 1 (bit name “PE”) of the control register A707. As shown in FIG. 23B, the parity function is not used by setting bit 1 to “0”. Further, by setting bit 1 to “1”, the parity function is set to be used.

  Setting data for setting the type of parity when the parity function is used is set in bit 0 (bit name “PT”) of the control register A707. As shown in FIG. 23B, even parity is set as the parity type by setting bit 0 to “0”. Also, by setting bit 0 to “1”, odd parity is set as the parity type.

  FIG. 24A is an explanatory diagram illustrating an example of the control register B708. The control register B 708 is a register for setting whether to permit an interrupt request from the serial communication circuit 505. In this embodiment, whether the interrupt request from the serial communication circuit 505 is permitted or prohibited is set by setting the value of each bit of the control register B708. In the control register B708, interrupt request setting data indicating whether or not various interrupt requests are permitted is mainly set. In addition to the interrupt request setting data, setting data for performing various settings of the serial communication circuit 505 is also set in the control register B708. As shown in FIG. 24A, the control register B 708 is an 8-bit register, and the initial value is set to “0 (= 00h)”. Control register B 708 is configured such that bits 0 to 7 can be written and read.

  FIG. 24B is an explanatory diagram showing an example of interrupt request setting data set in the control register B708. As shown in FIG. 24B, setting data indicating whether or not a transmission interrupt request, which is an interrupt request to be performed at the time of data transmission, is permitted is set in bit 7 (bit name “TIE”) of the control register B708. Is done. As shown in FIG. 24B, by setting bit 7 to “0”, the transmission interrupt request is set to be prohibited. Also, by setting bit 7 to “1”, the transmission interrupt request is set to be permitted.

  Bit 6 (bit name “TCIE”) of the control register B708 is set with setting data indicating whether or not to permit a transmission completion interrupt request, which is an interrupt request to be made when data transmission is completed. As shown in FIG. 24B, by setting bit 6 to “0”, the transmission completion interrupt request is set to be prohibited. Also, by setting bit 6 to “1”, the transmission completion interrupt request is set to be permitted.

  Bit 5 (bit name “RIE”) of the control register B 708 is set with setting data indicating whether or not a reception interrupt request, which is an interrupt request performed when data is received, is permitted. As shown in FIG. 24B, by setting bit 5 to “0”, the reception interrupt request is set to be prohibited. Further, by setting bit 5 to “1”, the reception interrupt request is set to be permitted.

  Bit 4 (bit name “ILIE”) of the control register B 708 is set with setting data indicating whether or not to allow an idle line interrupt request, which is an interrupt request when an idle line of received data is detected. As shown in FIG. 24B, by setting bit 4 to “0”, an idle line interrupt request is set to be prohibited. Further, by setting bit 4 to “1”, it is set to permit an idle line interrupt request.

  In bit 3 (bit name “TE”) of the control register B708, setting data indicating whether to use the transmission circuit (the transmission unit of the serial communication circuit 505) is set. As shown in FIG. 24B, by setting bit 3 to “0”, the transmission circuit is set not to be used. Further, by setting bit 3 to “1”, the transmission circuit is set to be used.

  In bit 2 (bit name “RE”) of the control register B708, setting data indicating whether or not to use the receiving circuit is set. As shown in FIG. 24B, by setting bit 2 to “0”, the receiving circuit is set not to be used. Further, by setting bit 2 to “1”, the receiving circuit is set to be used.

  Setting data indicating whether or not to use the wakeup function of the receiving circuit is set in bit 1 (bit name “RWU”) of the control register B708. As shown in FIG. 24B, by setting bit 1 to “0”, the wakeup function is set not to be used. Further, by setting bit 1 to “1”, the wakeup function is set to be used.

  Setting data indicating whether or not to use a predetermined break code transmission function is set in bit 0 (bit name “SBK”) of the control register B708. As shown in FIG. 24B, by setting bit 1 to “0”, the break code transmission function is set not to be used. Further, by setting bit 1 to “1”, the break code transmission function is set to be used. When bit 1 is set to “1”, serial communication circuit 505 transmits a break code (for example, a signal continuously including “0”) to the control board (payout control board 37 and effect control board 80).

  FIG. 25A is an explanatory diagram illustrating an example of the status register A705. The status register A 705 is a register for confirming various statuses of the serial communication circuit 505. In this embodiment, the game control microcomputer 560 can check various statuses of the serial communication circuit 505 by checking the value of each bit of the status register A 705. As shown in FIG. 25A, the status register A705 is an 8-bit register, and the initial value is set to “0 (= 00h)”. In addition, the status register A705 is configured so that bits 0 to 7 can only be read. Therefore, even if control is performed to write a value to bit 0 to bit 7 of the status register A705, it is invalidated.

  FIG. 25B is a diagram showing an example of status confirmation data stored in the status register A705. As shown in FIG. 25B, transmission data indicating that transmission data is not stored in transmission data register 710 in bit 7 (bit name “TDRE”) of status register A 705 (transmission data empty). Stores an empty flag. As shown in FIG. 25B, when “0” is stored in the bit 7, the transmission data is not yet transferred from the transmission data register 710 to the transmission shift register 712, and transmitted to the transmission data register 710. Indicates that the data is still stored. When “1” is stored in bit 7, the transmission data is transferred from the transmission data register 710 to the transmission shift register 712, and there is no transmission data in the transmission data register 710 (transmission data empty). ).

  Bit 6 (bit name “TC”) of the status register A 705 stores a transmission completion flag indicating that transmission of transmission data from the serial communication circuit 505 has been completed. As shown in FIG. 25B, when “0” is stored in bit 6, the transmission data stored in the transmission shift register 712 is being transmitted, and the transmission data from the serial communication circuit 505 is not transmitted. Indicates that transmission has not been completed. Further, when “1” is stored in bit 6, the transmission data stored in the transmission shift register 712 has been transferred, and transmission of transmission data from the serial communication circuit 505 has been completed. It shows that.

  Note that the transmission of the transmission data is completed, and the game control microcomputer 560 waits for a reception confirmation signal from the transmission destination control board. In this embodiment, when a transmission interrupt is set as will be described later, the serial communication circuit 505 sets the bit 6 of the status register A 705 to “1” and confirms reception when detecting the completion of transmission of transmission data. An interrupt request (referred to as an interrupt request at the time of transmission) is made to the game control microcomputer 560 as a signal waiting state.

  Bit 5 (bit name “RDRF”) of status register A 705 stores a reception data full flag indicating that reception data is stored in reception data register 711 (reception data full). As shown in FIG. 25B, when “0” is stored in bit 5, it indicates that the reception data register 711 contains no reception data. When “1” is stored in bit 5, the value of the reception shift register 713 is transferred to the reception data register 711, and reception data is stored in the reception data register 711 (reception data Full).

  When the reception data is stored in the reception data register 711, the game control microcomputer 560 reads the reception data from the reception data register 711 and can perform reception processing. In this embodiment, when the serial communication circuit 505 detects that the received data is full, the bit 5 of the status register A 705 is set to “1” and the game control microcomputer 560 is interrupted on the assumption that reception processing is possible. Make a request (called an interrupt request when receiving).

  Bit 4 (bit name “IDLE”) of status register A705 stores an idle line detection flag indicating that the receiving circuit has detected an idle line. As shown in FIG. 25B, when “0” is stored in bit 4, it indicates that the receiving unit of the serial communication circuit 505 has not detected an idle line. When “1” is stored in bit 4, it indicates that the receiving unit of the serial communication circuit 505 has detected an idle line.

  In bit 3 (bit name “OR”) of the status register A 705, the reception shift register 713 receives the next data before the game control microcomputer 560 reads the reception data stored in the reception data register 711. An overrun flag indicating that it has been closed (overrun) is stored. As shown in FIG. 25B, when “0” is stored in bit 3, it indicates that the receiving circuit has not detected an overrun. If “1” is stored in bit 3, it indicates that the receiving circuit has detected an overrun.

  If an overrun occurs, the next received data is stored in the receiving shift register 713 before the received data in the received data register 711 is read, so that the received data is overwritten and the game control microcomputer. 560 cannot read the received data correctly. For this reason, communication with each control board cannot be performed correctly, causing the game control microcomputer 560 to malfunction. In this embodiment, when detecting an overrun, the serial communication circuit 505 sets bit 3 of the status register A 705 to “1” and issues an interrupt request to the game control microcomputer 560 as an error has occurred during communication. Do.

  Bit 2 (bit name “NF”) of status register A 705 stores a noise error flag indicating that noise has been detected in the received data. As shown in FIG. 25B, when “0” is stored in bit 2, it indicates that the receiving circuit is not detecting noise in the received data. Further, when “1” is stored in bit 2, it indicates that the receiving circuit has detected noise in the received data.

  For example, when detecting each bit of the received data, the serial communication circuit 505 detects “1” or “0” having a predetermined bit length using the baud rate generated by the baud rate generation circuit 703. In this case, when the detected length of “1” or “0” is less than the predetermined bit length, the serial communication circuit 505 detects a noise error as noise generated in the received data. When a noise error occurs, there is a high possibility that correct received data cannot be received due to the noise, which causes the game control microcomputer 560 to malfunction. In this embodiment, when the serial communication circuit 505 detects a noise error, the serial communication circuit 505 sets bit 2 of the status register A 705 to “1” and issues an interrupt request to the game control microcomputer 560 as an error has occurred during communication. Do.

  Bit 1 (bit name “FE”) of the status register A 705 indicates that it is detected that the position of the stop bit of the received data is “0” (originally, the stop bit is “1”) (framing error). A framing error flag is stored. As shown in FIG. 25B, when “0” is stored in bit 1, it indicates that the receiving circuit has not detected a framing error in the received data. When “1” is stored in bit 1, it indicates that the receiving circuit has detected a framing error.

  When a framing error occurs, it is in a state where the stop bit of the received data has not been correctly received, and therefore there is a high possibility that correct received data cannot be received, causing the gaming control microcomputer 560 to malfunction. In this embodiment, when detecting a framing error, the serial communication circuit 505 sets bit 1 of the status register A 705 to “1”, and issues an interrupt request to the game control microcomputer 560 as an error has occurred during communication. Do.

  Bit 0 (bit name “PF”) of the status register A 705 has a parity error flag indicating that the parity value obtained from the received data does not match the parity value included in the received data (parity error). Is stored. As shown in FIG. 25B, when “0” is stored in bit 0, it indicates that the receiving circuit has not detected a parity error in the received data. Further, when “1” is stored in bit 0, it indicates that the receiving circuit has detected a parity error.

  When a parity error occurs, each data bit or parity bit of the received data has not been correctly received, so there is a high possibility that correct received data cannot be received, causing the gaming control microcomputer 560 to malfunction. . In this embodiment, when the serial communication circuit 505 detects a parity error, the serial communication circuit 505 sets bit 0 of the status register A 705 to “1”, and issues an interrupt request to the game control microcomputer 560 that an error has occurred during communication. Do.

  FIG. 26A is an explanatory diagram illustrating an example of the status register B706. The status register B 706 is a register for confirming the reception state (reception status) of the serial communication circuit 505. In this embodiment, the game control microcomputer 560 can confirm the reception status of the serial communication circuit 505 by confirming the value of the bit in the status register B 706. As shown in FIG. 26B, the status register B 706 is an 8-bit register, and the initial value is set to “0 (= 00h)”. Further, the status register B 706 is configured so that bit 0 can only be read. Therefore, even if control is performed to write a value to bit 0 of status register A 705, it is invalid. Status register B 706 is configured such that bits 1 to 7 cannot be written or read. Therefore, even if control is performed to write a value to bits 1 to 7 of the status register A 705, the value is invalid and all the values read from bits 1 to 7 are “0 (= 0000b)”.

  FIG. 26B is a diagram showing an example of status confirmation data stored in the status register B706. As shown in FIG. 26B, a reception active flag indicating that the reception circuit is receiving reception data (reception active) is stored in bit 0 (bit name “RAF”) of the status register B706. . As shown in FIG. 26B, when “0” is stored in bit 0, it indicates that the reception circuit is not receiving reception data. Further, when “1” is stored in bit 0, it indicates that the reception circuit is receiving reception data. When the serial communication circuit 505 detects the start bit, it assumes that reception of received data has started, and sets bit 0 of the status register B 706 to “1”.

  FIG. 27A is an explanatory diagram illustrating an example of the control register C709. The control register C709 is a register for setting whether to permit an interrupt request when a communication error occurs in the serial communication circuit 505. In this embodiment, by setting the value of each bit of the control register C709, it is set whether to permit or prohibit an interrupt request during communication from the serial communication circuit 505. In the control register C709, error interrupt request setting data indicating whether or not various interrupt requests at the time of a communication error are permitted is mainly set. In addition to the error interrupt request setting data, the control register C709 stores 9th bit data when the data length is set to 9 bits. Various settings of the serial communication circuit 505 are also set. As shown in FIG. 27A, the control register C709 is an 8-bit register, and the initial value is set to “0 (= 00h)”. Control register C709 is configured such that bits 0 to 3 and bits 6 and 7 can be written and read. Further, the control register C709 is configured such that bits 4 and 5 cannot be written or read. Therefore, even if control is performed to write a value to bits 4 and 5 of the control register C709, it is invalid, and all values read from bits 4 and 5 are “0 (= 0000b)”.

  FIG. 27B is an explanatory diagram showing an example of error interrupt request setting data set in the control register C709. As shown in FIG. 27B, bit 7 (bit name “R8”) of the control register C709 stores the 9th bit of the received data when the data length is set to 9 bits. Further, bit 6 (bit name “T8”) of the control register C709 stores the ninth bit of transmission data when the data length is set to nine bits.

  In bit 3 (bit name “ORIE”) of the control register C709, setting data indicating whether or not to permit an overrun flag interrupt request, which is an interrupt request to be performed when an overrun is detected, is set. As shown in FIG. 27B, by setting bit 3 to “0”, the overrun flag interrupt request is set to be prohibited. Further, by setting bit 3 to “1”, the overrun flag interrupt request is set to be permitted.

  Bit 2 (bit name “NEIE”) of the control register C709 is set with setting data indicating whether or not to permit a noise error flag interrupt request, which is an interrupt request to be performed when a noise error is detected. As shown in FIG. 27B, by setting bit 2 to “0”, the noise error flag interrupt request is set to be prohibited. Also, by setting bit 2 to “1”, the noise error flag interrupt request is set to be permitted.

  Bit 1 (bit name “FEIE”) of the control register C709 is set with setting data indicating whether or not to permit a framing error flag interrupt request, which is an interrupt request to be performed when a framing error is detected. As shown in FIG. 27B, by setting bit 1 to “0”, the framing error flag interrupt request is set to be prohibited. Further, by setting bit 1 to “1”, the framing error flag interrupt request is set to be permitted.

  Bit 0 (bit name “PEIE”) of the control register C709 is set with setting data indicating whether or not to permit a parity error flag interrupt request which is an interrupt request to be performed when a parity error is detected. As shown in FIG. 27B, by setting bit 0 to “0”, the parity error flag interrupt request is set to be prohibited. Further, by setting bit 0 to “1”, the parity error flag interrupt request is set to be permitted.

  FIG. 28 is an explanatory diagram illustrating an example of a data register included in the serial communication circuit 505. The data register 701 is a register that stores data transmitted and received by the serial communication circuit 505. As shown in FIG. 28, the data register is an 8-bit register, and the initial value is set to “0 (= 00h)”. Data register 701 is configured such that bits 0 to 7 can be written and read.

  In this embodiment, when the serial communication circuit 505 transmits transmission data, the data register is used as the transmission data register 710. When the data length is set to 9 bits, bit 6 of the data register and control register C709 is used as the transmission data register 710. In this case, bits 0 to 7 of the data register are used as bits 0 to 7 of the transmission data register 710, and bit 6 of the control register C709 is used as bit 8 of the transmission data register 710.

  When the serial communication circuit 505 receives received data, the data register is used as the received data register 711. When the data length is set to 9 bits, bit 7 of the data register and control register C709 is used as the reception data register 711. In this case, bits 0 to 7 of the data register are used as bits 0 to 7 of the reception data register 711, and bit 7 of the control register C709 is used as bit 8 of the reception data register 711.

  The interrupt control circuit 714 makes various interrupt requests to the game control microcomputer 560. In this embodiment, when the bit 6 (TCIE) of the control register B 708 is set to “1”, the interrupt control circuit 714 controls the game control when the transmission data transmission to the transmission data register 710 is completed. An interrupt signal is output to the microcomputer 560 for use to make an interrupt request. Further, the interrupt control circuit 714 sets “1” to bit 6 (TC) of the status register A705.

  In addition, when the bit 5 (RIE) of the control register B 708 is set to “1”, the interrupt control circuit 714 enters a state where the reception data is stored in the reception data register 711 (when reception data full is detected). ), An interrupt signal is output to the game control microcomputer 560 to make an interrupt request. Further, the interrupt control circuit 714 sets “1” in bit 5 (RDRF) of the status register A705.

  The interrupt control circuit 714 outputs an interrupt signal to the game control microcomputer 560 when various communication errors occur when any of bits 0 to 3 of the control register C709 is set to “1”. Make an interrupt request. Further, the interrupt control circuit 714 sets “1” to bits 0 to 3 of the status register A 705 according to the type of communication error. For example, when bit 3 (ORIE) of the control register C709 is set to “1”, when an overrun is detected and an interrupt request is made, “1” is set to bit 3 (OR) of the status register A705. . For example, when bit 2 (NEIE) of the control register C709 is set to “1”, if a noise error is detected and an interrupt request is made, “1” is set to bit 2 (NF) of the status register A705. Set. Also, for example, when bit 1 (FEIE) of the control register C709 is set to “1”, if a framing error is detected and an interrupt request is made, “1” is set to bit 1 (FE) of the status register A705. Set. For example, when bit 0 (PEIE) of the control register C709 is set to “1”, if a parity error is detected and an interrupt request is made, “1” is set to bit 0 (PF) of the status register A705. Set. When a plurality of communication errors are detected, the interrupt control circuit 714 makes an interrupt request based on the plurality of communication errors and sets the corresponding bits of the status register A 705 to “1”.

  The transmission format / parity generation circuit 715 generates a data format of transmission data. In this embodiment, the transmission format / parity generation circuit 715 generates a data format by adding a start bit and a stop bit to the transmission data stored in the transmission data register 710 and transfers the data format to the transmission shift register 712. When bit 1 (PE) of the control register A707 is set to “1” and the parity function is set to be used, the transmission format / parity generation circuit 715 adds a parity bit to the transmission data. Generate a data format.

  The reception format / parity check circuit 716 detects the data format of the reception data. In this embodiment, the reception format / parity check circuit 716 detects the start bit and the stop bit from the reception data stored in the reception shift register 713, detects the data portion included in the reception data, and receives the reception data register. Forward to 711. When bit 1 (PE) of the control register A707 is set to “1” and the parity function is set to be used, the reception format / parity check circuit 716 obtains the parity of the reception data and receives the reception data. It is detected whether or not it matches the parity included in. If the obtained value does not match the parity included in the received data, the reception format / parity check circuit 716 detects a parity error. If it is set in the serial communication circuit setting process to be described later that an interrupt request at the time of communication error is permitted, the reception format / parity check circuit 716 detects the occurrence of the parity error and causes the CPU 56 to generate the communication error as an interrupt cause. Interrupt request.

  FIG. 29 is an explanatory diagram showing an example of an address map of a storage area in the game control microcomputer 560. As shown in FIG. 29, the area from address 0000h to address 1FFFh in the storage area of the game control microcomputer 560 is allocated to the ROM 54. An area from addresses 7E00h to 7FFFh is allocated to the RAM 55. Further, the area from the address FD00h to the address FE00h is allocated to a built-in register such as the random number maximum value setting register 535.

  As shown in FIG. 29, the area of addresses 0000h to 1FFFh allocated to the ROM 54 includes a user program area and a user program management area. A program (user program) 550 created in advance by a user (for example, a game machine manufacturer) is stored in the user program area in the area of addresses 0000h to 1F7Fh. Further, data (user program execution data) necessary for the CPU 56 to execute the user program 550 is stored in the user program management area in the area of addresses 1F80h to 1FFFh. Of the areas 7E00h to 7FFFh allocated to the RAM 55, the areas 7E00h to 7EFFh are unused areas, and the areas 7F00h to 7FFFh are used as work areas.

  FIG. 30 is an explanatory diagram showing an example of an address map in the user program management area. As shown in FIG. 30, the initial value changing method selected by the user among the initial value changing methods, which is a method for changing the initial value input to the counter 521 of the random number circuit 503, is stored in the area of address 1F97h. The initial value change method setting data for designating is stored. Further, in the areas 1F98h and 1F99h, RAM address data for specifying an address in the RAM 55 (designated RAM address) designated in advance by the user among addresses 7F00h to 7FFFh allocated to the RAM 55 is stored. The In this case, of the values indicating the designated RAM address, the lower value of the designated RAM address is stored in the 1F98h address, and the higher value of the designated RAM address is stored in the 1F99h address.

  FIG. 31 is an explanatory diagram of an example of the initial value change method setting data. As shown in FIG. 31, the initial value change data is composed of 8-bit data. The initial value change data “00h” is data specifying that the initial value is not changed as the initial value change method. In this embodiment, when the initial value change data “00h” is set, the counter 521 of the random number circuit 503 updates the count value from a predetermined initial value “0” to a predetermined final value. Become. Further, the initial value change data “01h” is data specifying that the initial value input to the counter 521 is changed to a value based on an ID number for identifying the game control microcomputer 560 as an initial value change method. It is. In this embodiment, when the initial value change data “01h” is set, the initial value of the counter value updated by the counter 521 is changed from “0” to a value based on the ID number. The count value is updated from the initial value to a predetermined final value.

  The user program 550 stored in the user program area will be described. FIG. 32 is an explanatory diagram showing a configuration example of the user program 550. As shown in FIG. 32, in this embodiment, the user program 550 includes a random number circuit setting program 551 composed of a plurality of types of program modules, a display result determination program 552, a count value permutation change program 554, and a random program. A numerical value update program 555, a serial communication circuit setting program 556, and an interrupt priority setting program 557 are included.

  The random number circuit setting program 551 is a program for executing a random number circuit setting process for performing initial setting for causing the random number circuit 503 to update the value of the random R. That is, the CPU 56 functions as random number circuit initial setting means by executing processing according to the random number circuit setting program 551.

  FIG. 33 is an explanatory diagram showing a configuration example of the random number circuit setting program 551. As shown in FIG. 33, the random number circuit setting program 551 includes a random number maximum value setting module 551a, a random number update method selection module 551b, a cycle setting module 551c, a random number circuit activation module 551d, as a plurality of types of program modules. An initial value changing module 551e and a random number circuit selecting module 551f are included.

  The random number maximum value setting module 551a is a program module for causing the random number circuit 503 to set the maximum value of the random R preset by the user (for example, the manufacturer of the gaming machine). The CPU 56 executes processing according to the random number maximum value setting module 551a, thereby writing random number maximum value setting data for specifying the maximum value of the random R preset by the user in the random number maximum value setting register 535. By doing so, the CPU 56 sets the maximum value of the random R preset by the user in the random number circuit 503. For example, when “255” is set in advance as the maximum value of the random R by the user, the CPU 56 writes the random number maximum value setting data “00FFh” in the random number maximum value setting register 535 and the random R maximum value “255”. Is set in the random number circuit 503.

  The random number update method selection module 551b is a program module for causing the random number circuit 503 to set the random number update method (first random number update method or second random number update method) selected by the user. The CPU 56 writes the random number update method selection data “01b” or “10b” designating the random number update method selected by the user in the random number update method selection register 540 by executing the process according to the random number update method selection module 551b. By doing so, the CPU 56 sets the random number update method selected by the user in the random number circuit 503. Therefore, the game control microcomputer 560 has a function of selecting either the first random number update method or the second random number update method as the random number update method used by the random number circuit 503 for the random number update.

  The cycle setting module 551c is a program for causing the random number circuit 503 to set the cycle of the internal clock signal preset by the user (that is, the cycle in which the clock signal output circuit 524 outputs the clock signal to the selector 528 and the inverting circuit 532). It is a module. The CPU 56 writes processing in the cycle setting register 537 for designating the cycle of the internal clock signal preset by the user by executing processing in accordance with the cycle setting module 551c. By doing so, the CPU 56 sets the cycle of the internal clock signal preset by the user in the random number circuit 503. For example, when the cycle of the internal clock signal is set in advance as “system clock signal cycle × 128 × 16” by the user, the CPU 56 writes the cycle setting data “0Fh” in the cycle setting register 537 and sets the internal clock signal The period “system clock signal period × 128 × 16” is set in the random number circuit 503.

  The random number circuit activation module 551d is a program module for activating the random number circuit 503. The CPU 56 activates the random number circuit 503 by writing the random number circuit activation data “80h” into the random number circuit activation register 541 by executing processing according to the random number circuit activation module 551d.

  The initial value change module 551e is a program module for changing the initial value of the count value updated by the counter 521. The CPU 56 functions as an initial value changing unit by executing processing according to the initial value changing module 551e. The CPU 56 executes the initial value changing module 551e to change the initial value of the count value updated by the counter 521 by the initial value changing method selected by the user. By doing so, the game control microcomputer 560 has a function of selecting an initial value changing method.

  In this embodiment, when initial value change method setting data “01h” is stored in the area of address 1F97h in the user program management area, the CPU 56 sets the initial value of the count value for each game control microcomputer 560. The value is changed to a value calculated based on the assigned unique ID number.

  For example, the game control microcomputer 560 associates in advance a predetermined storage area of the RAM 55 with the ID number of the game control microcomputer 560 and a calculated value obtained by performing a predetermined calculation based on the ID number. I remember it. In this case, for example, if the ID number of the game control microcomputer 560 is “100”, the calculated value “150” obtained by adding the predetermined value “50” to the ID number “100” is set in advance as the ID number. Are stored in association with each other. Further, for example, the calculated value “50” obtained by subtracting the predetermined value “50” from the ID number “100” is stored in advance in association with the ID number. Further, for example, only a predetermined value may be stored in advance in association with the ID number. Then, the game control microcomputer 560 uses a value “150” obtained by adding an ID number (eg, “100”) to a predetermined value (eg, “50”) stored in advance as an initial value of the count value. In addition, the game control microcomputer 560 uses a value “50” obtained by subtracting a predetermined value (for example, “50”) stored in advance from the ID number (for example, “100”) as an initial count value. It may be a value.

  When the initial value change method setting data “01h” is stored, the CPU 56 changes the initial value of the count value to the calculated value based on the ID number stored in advance. By doing so, the randomness of the random number generated by the random number circuit 503 can be further improved, and the initial value of the random number can be made difficult to recognize simply by looking at the ID number of the game control microcomputer 560. . Therefore, it is possible to more reliably prevent the transition condition to the big hit state from being illegally established by an action such as generating a captured signal using a radio signal to the gaming machine, and improving security. Can be improved.

  For example, when initial value change method setting data “01h” is stored, the CPU 56 calculates the ID number of the game control microcomputer 560 and a predetermined value (for example, adds a predetermined value to the ID number). The initial value of the count value is changed to the calculated value obtained. In this case, for example, the CPU 56 may calculate a value that is randomly changed using a random number as an ID number, thereby randomly updating a value used for the calculation and obtaining an initial value. By doing so, the randomness of the random numbers generated by the random number circuit 503 can be further improved.

  The random number circuit selection module 551f is a program module for setting a random number circuit to be used when executing a timer interrupt process including a game control process from among the random number circuits 503 built in the game control microcomputer 560. The CPU 56 executes a process according to the random number circuit selection module 551f, so that any of the two random number circuits (12-bit random number circuit 503a and 16-bit random number circuit 503b) built in the game control microcomputer 560 is selected. Set whether to use when executing timer interrupt processing. For example, the CPU 56 uses a 12-bit random number circuit 503a or 16-bit as a random number circuit used when executing the timer interrupt process according to a predetermined set value (a value set in advance by the user) stored in a predetermined storage area of the ROM 54. The random number circuit 503b is set.

  Note that both the 12-bit random number circuit 503a and the 16-bit random number circuit 503b may be set as random number circuits used when the timer interrupt process is executed. In this case, for example, the game control microcomputer may perform a jackpot determination based on a random number generated by the 12-bit random number circuit 503a and may perform a probability change determination based on the random number generated by the 16-bit random number circuit 503b. . In this embodiment, the random value storage circuit 531 exists in each of the 12-bit random number circuit 503a and the 16-bit random number circuit 503b (that is, a random-value storage circuit that stores a random number for 12 bits and a 16-bit random-number storage circuit). A random value storage circuit for storing random numbers exists separately). When both the 12-bit random number circuit 503a and the 16-bit random number circuit 503b are set, the game control microcomputer 560 outputs the random number read from the 12-bit random number circuit 503a and the random number read from the 16-bit random number circuit 503b. , And stored in separate buffer areas provided in the RAM 55. Therefore, even when the timing for reading a random number from the 12-bit random number circuit 503a and the timing for reading a random number from the 16-bit random number circuit 503b are the same, two different random numbers can be extracted and stored in different buffer areas.

  The random value update program 555 is a program for updating the value of the random R stored in the random value storage circuit 531 when the first random number update method is selected as the random number update method. The CPU 56 functions as a random value updating unit by executing processing according to the random value updating program 555. When the first random number update method is selected, the CPU 56 executes the random number value update program 555 and writes the count value update data “01h” in the count value update register 538, whereby the count value is stored in the counter 521. And the value of the random R stored in the random value storage circuit 531 is updated. When the second random number update method is selected as the random number update method, the counter 521 is updated with the random number generation clock signal output from the clock signal output circuit 537, and the random value storage circuit 531 is updated. The value of random R stored in is updated.

  The display result determination program 552 is a program for determining whether or not the display result in the special symbol display device 8 is a jackpot symbol. The CPU 56 functions as a display result determination unit by executing processing according to the display result determination program 552.

  In this embodiment, the CPU 56 follows the display result determination program 552 in response to the fact that the game ball has won the variable winning ball device 15 and the condition (execution condition) for executing the variable symbol special display is established. Execute the process. Then, the CPU 56 reads the updated random R value from the random value storage circuit 531, and determines whether or not the display result in the special symbol display device 8 is a jackpot symbol.

  FIG. 34 is an explanatory diagram illustrating an operation in which the CPU 56 updates the random R value or reads the random R value when the first random number update method is selected. As shown in FIG. 34, when the first random number update method is selected, the CPU 56 writes the count value update data “01h” to the count value update register 538, thereby storing the random number value storage circuit 531. The value of R (for example, “2”) is updated. Then, the CPU 56 receives a random R value from the random value storage circuit 531 in response to the fact that the game ball has won the variable winning ball device 15 and the condition (execution condition) for executing the variable symbol special display is established. (For example, “2”) is read.

  When the random R value stored in the random value storage circuit 531 is further updated, an interval equal to or longer than the period of the system clock signal output from the clock circuit 501 has elapsed since the random R value was updated at the previous update. Sometimes, the count value update data “01h” must be written to the count value update register 538. This is because it is necessary to secure time for reading the updated random R value from the random value storage circuit 531.

  FIG. 35 is an explanatory diagram illustrating an operation in which the CPU 56 updates the random R value or reads the random R value when the second random number update method is selected. As shown in FIG. 35, when the second random number update method is selected, the CPU 56 writes the random number value take-in command “01h” into the random value take-in register 539 so that the count value output by the counter 521 is output. (For example, “2”) is taken into the random value storage circuit 531 to update the random R value stored in the random value storage circuit 531. Then, the CPU 56 reads the updated random R value (for example, “2”) from the random value storage circuit 531.

  Specifically, when the second random number update method is selected, the counter 521 updates the count value C using the input of the random number generation clock signal SI1 as a trigger. Thereafter, when the random value acquisition command “01h” is written in the random value acquisition register 539, the latch signal generation circuit 533 outputs the latch signal SL to the random value storage circuit 531. Then, the random value storage circuit 531 reads and stores the count value output from the counter 521 with the input of the latch signal SL as a trigger. Then, the CPU 56 reads the value of random R stored in the random value storage circuit 531.

  If the CPU 56 does not write the random value acquisition command “01h” to the random value acquisition register 539, even if the counter 521 updates the count value, the random value storage circuit 531 stores the random value that the counter 521 updates. I don't remember. For example, the CPU 56 writes the random value fetch command “01h” into the random value fetch register 539, causes the count value “3” output from the counter 521 to be fetched into the random value memory circuit 531, and the random value memory circuit 531 stores it. Assume that the random R value “3” is updated. In this case, if the CPU 56 does not write the random value acquisition command “01h” again in the random value acquisition register 539, the count value output from the counter 521 is updated from “3” to “4” or “5”. The random value stored in the random value storage circuit 531 is not updated, and the random value read from the random value storage circuit 531 remains “3”.

  The count value permutation change program 554 writes count value permutation change data “01h” to the count value permutation change register 536, and executes count value permutation change processing for changing the permutation of count values stored in the random value storage circuit 531. It is a program for. The CPU 56 functions as numerical data permutation changing means by executing processing according to the count value permutation changing program 554. The CPU 56 executes the count value permutation change program 554 and writes the count value permutation change data “01h” in the count value permutation change register 536, whereby the count value permutation change circuit 523 outputs and inputs to the random value storage circuit 531. The permutation of the count values to be changed is changed.

  The serial communication circuit setting program 556 executes a serial communication circuit setting process for performing an initial setting for serial communication with a microcomputer (in this example, a payout control microcomputer) mounted on each control board in the serial communication circuit 505. It is a program to make it. That is, the CPU 56 functions as serial communication circuit setting means by executing processing according to the serial communication circuit setting program 556.

  The interrupt priority setting program 557 is a program for initially setting the priority of interrupt processing executed in response to an interrupt request from the serial communication circuit 505. That is, the CPU 56 functions as priority order initial setting means by executing processing according to the interrupt priority order setting program 556.

  As shown in FIG. 36, the game control microcomputer 560 includes a special figure holding memory 570, a big hit determination table memory 571, a flag memory 572, and a start winning port switch timer memory 573.

  In the special figure holding memory 570, the game ball wins the variable winning ball device 15 and the execution condition of the variable symbol variable display is satisfied, but the variable display start condition is not yet satisfied (for example, the special symbol display device). 8 is a memory for storing pending data including the number of times the execution condition of variable display is satisfied (8 is still executing variable display). The special figure holding memory 570 includes four entries. Each entry includes a holding number and a random R read from the random number storage circuit 531 according to the winning order in the order in which the game balls win the variable winning ball device 15. A value is stored in association with each other. In addition, each time the special symbol variable display in the special symbol display device 8 is finished once or the big hit gaming state is finished, the variable display start condition based on the top information of the special symbol holding memory 570 is set. It is established, and variable display based on the top information of the special figure holding memory 570 is executed. In this case, when the condition for starting the variable display of special symbols is satisfied, the information registered in the second or lower place in the special figure holding memory 570 is moved up by one place. In addition, when a game ball newly wins the variable winning ball apparatus 15 during the variable display of the special symbol, the value of the random R read from the random value storage circuit 531 based on the new winning is the special R value. It is registered in the empty entry in the figure holding memory 570.

  The jackpot determination table memory 571 stores a plurality of jackpot determination tables used by the CPU 56 to determine whether or not the display result of the special symbol display device 8 is a jackpot symbol. Specifically, as shown in FIG. 37A, the big hit determination table memory 571 stores a normal time big hit determination table 571a used in a gaming state (referred to as a normal state) other than the probability variation state. Also, the jackpot determination table memory 571 stores a probability change jackpot determination table 571b used in the probability change state, as shown in FIG. Note that, when the big hit determination is performed using the determination table shown in FIG. 37, the probability of determining a big hit depends on the random number maximum value set in the random number maximum value setting register 535. In this case, for example, if the set random number maximum value is too small, the difference in the probability of determining a big hit between the case where the normal big hit determination table 571a is used and the case where the probability variation big hit determination table 571b is used is small. As a result, the player's interest in the game is diminished. Therefore, a plurality of determination tables (a plurality of normal time big hit determination tables 571a and a plurality of probability variation big hit determination tables 571b) are stored in the big hit determination table memory 571 in association with the random number circuit 503 and the maximum random number. Also good. The game control microcomputer 560 uses the random number circuit 503 to be used and the determination tables 571a and 571b corresponding to the maximum random number among the determination tables stored in the jackpot determination table memory 571 to display the display result determination program 552. Accordingly, it may be determined whether or not the display result of the special symbol display device 8 is a jackpot symbol. By doing so, even if the type of random number circuit 503 to be used and the maximum random number value are different, it is possible to control so that the probability of determining a jackpot is the same to some extent.

  In the flag memory 572, various flags used in the game control process for controlling the progress of the game are set. For example, in the flag memory 572, a probability change flag indicating that the gaming state is a probability change state and a big hit flag indicating that the game state is a big hit state are set.

  The start port switch timer memory 573 stores a timer value that is added or cleared in accordance with the winning detection signal SS input from the start port switch 14a.

  Next, the operation of the gaming machine will be described. FIG. 38 and FIG. 39 show main processing executed by the game control microcomputer 560 in response to the start of power supply to the game machine and the reset signal to the game control microcomputer 560 becoming high level. It is a flowchart. When the input level of the reset terminal to which the reset signal is input becomes high level, the game control microcomputer 560 executes a security check process that is a process for confirming whether the contents of the program are valid, The main processing after S1 is started. In the main process, the game control microcomputer 560 first performs necessary initial settings.

  In the initial setting process, the game control microcomputer 560 first sets the interrupt prohibition (step S1). Next, an interrupt mode for maskable interrupts is set (step S2), and a stack pointer designation address is set for the stack pointer (step S3). In step S2, the address synthesized from the value (1 byte) of the specific register (I register) of the game control microcomputer 560 and the interrupt vector (1 byte: least significant bit 0) output from the built-in device is Set to the mode indicating the interrupt address. When a maskable interrupt occurs, the game control microcomputer 560 automatically sets the interrupt disabled state and saves the contents of the program counter in the stack.

  Next, the built-in device register is set (initialized) (step S4). By the processing in step S4, the CTC (counter / timer) and PIO (parallel input / output port) which are built-in devices (built-in peripheral circuits) are set (initialized).

  The game control microcomputer 560 used in this embodiment also incorporates an I / O port (PIO) and a timer / counter circuit (CTC) 504.

  Next, it is confirmed whether or not the power-off signal is in an OFF state depending on the state of bit 0 of the input port 1 (step S5). When the power supply to the gaming machine is started, the output voltage of various power sources such as the + 5V power source gradually reaches the specified value, but the power-off signal is not output by the process of step S5, that is, the high power The game control microcomputer 560 can confirm that the power supply voltage is stable.

  When the power-off signal is on, the game control microcomputer 560 turns off the power-off signal again after a delay time of a predetermined period (for example, 0.1 second) (step S80). Check if it is. If the power-off signal is off, the RAM 55 is set to an accessible state (step S6), and the process proceeds to a clear signal check process.

  When the power-off signal is in the on state, software delay processing for delaying the start timing of the gaming device control processing (game control processing) for controlling the progress of the game by software may be executed. By such software delay processing, the start timing of the game control processing can be delayed as compared with the case where the software delay processing is not executed. When the delay process is executed, a situation occurs in which another control board cannot receive a command transmitted from the game control board (main board 31) with respect to another control board (for example, the payout control board 37). Can be prevented.

  Note that the game control microcomputer 560 may confirm the state of the clear signal only once through the input port 0, but may confirm the state of the clear signal a plurality of times. For example, if it is confirmed that the state of the clear signal is an off state, after a delay time of a predetermined time (for example, 0.1 seconds), the state of the clear signal is reconfirmed. If it is confirmed that the clear signal is in the on state at that time, it is determined that the clear signal is in the on state. Further, at this time, if it is confirmed that the state of the clear signal is the off state, after a delay time of a predetermined time, the state of the clear signal may be confirmed again. Here, the number of reconfirmations is not limited to once or twice, but may be three or more times. It is also possible to check twice and check again when the check results do not match.

  Next, the game control microcomputer 560 checks whether or not the clear switch is turned on (step S7). If the clear switch is not on, it is confirmed whether or not data protection processing of the backup RAM area (for example, power supply stop processing such as addition of parity data) has been performed when power supply to the gaming machine is stopped ( Step S8). In this embodiment, when power supply is stopped, a process for protecting data in the backup RAM area is performed. When it is confirmed that such power supply stop processing has been performed, the game control microcomputer 560 stores the power supply stop processing, that is, the control state at the time of power supply stop. It is determined that When it is confirmed that the power supply stop process is not performed, the game control microcomputer 560 executes an initialization process.

  Whether or not the power supply stop process has been performed is determined by the value of the backup monitoring timer stored in the backup RAM area in the power supply stop process corresponding to the execution of the power supply stop process (for example, 2). ) Is confirmed by whether or not. Note that such a confirmation method is an example. For example, a flag indicating that the power supply stop process has been executed is set in the backup flag area in the power supply stop process, and the flag is set in step S8. If it is confirmed that the power supply is stopped, it may be determined that the power supply stop process has been performed.

  If it is determined that the control state at the time of stopping power supply is stored, the game control microcomputer 560 performs data check (parity check in this example) of the backup RAM area (step S9). In this embodiment, clear data (00) is set in the checksum data area, and the checksum calculation start address is set in the pointer. Also, the number of checksum calculations corresponding to the number of data to be checksum is set. Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated. The calculation result is stored in the checksum data area, the pointer value is incremented by 1, and the checksum calculation count value is decremented by 1. The above processing is repeated until the value of the checksum calculation count becomes zero. When the value of the checksum calculation count becomes 0, the game control microcomputer 560 inverts the value of each bit of the contents of the checksum data area and uses the inverted data as a checksum.

  In the power supply stop process, a checksum is calculated by the same process as described above, and the checksum is stored in the backup RAM area. In step S9, the calculated checksum is compared with the stored checksum. When the power supply is stopped after an unexpected power failure or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area may be different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state when the power supply is stopped, the initialization process (the process of steps S10 to S14) executed at the time of power-on that is not the time of recovery from the stop of the power supply is performed. Execute.

  If the check result is normal, the game control microcomputer 560 returns the internal state of the game control means and the control state of the electric component control means such as the effect control means to the state when the power supply is stopped. I do. Specifically, the start address of the backup setting table stored in the ROM 54 is set as a pointer (step S91), and the contents of the backup setting table are sequentially set in the work area (area in the RAM 55) (step S92). ). The work area is backed up by a backup power source. In the backup setting table, initialization data for an area that may be initialized in the work area is set. As a result of the processing in steps S91 and S92, the saved contents of the work area that should not be initialized remain. The parts that should not be initialized include, for example, data indicating the gaming state before the power supply is stopped (special symbol process flag, etc.), the area where the output state of the output port is saved (output port buffer), unpaid prize balls This is the part where data indicating the number is set.

  Further, the game control microcomputer 560 sets the head address of the backup command transmission table stored in the ROM 54 as a pointer (step S93), and proceeds to step S15.

  In the initialization process, the game control microcomputer 560 first performs a RAM clear process (step S10). Note that the predetermined data may be left as it is without initializing the entire area of the RAM 55. Also, the initial address of the initialization setting table stored in the ROM 54 is set as a pointer (step S11), and the contents of the initialization setting table are sequentially set in the work area (step S12).

  Control states such as a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol buffer, a total prize ball number storage buffer, a special symbol process flag, an award ball flag, an out-of-ball flag, etc. An initial value is set in a flag for selectively performing processing according to the above. In addition, a bit corresponding to the output port that outputs the connection confirmation signal in the output port buffer is set (corresponding to the ON state of the connection confirmation signal).

  The game control microcomputer 560 also sets the initial address of the initialization command transmission table stored in the ROM 54 as a pointer (step S13), and issues an initialization command for initializing the sub-board according to the contents. Processing to transmit to the sub-board is executed (step S14). As an initialization command, a command indicating an initial symbol displayed on the variable display device 9, an initialization command to the payout control board 37, or the like can be used.

  Further, the game control microcomputer 560 executes random number circuit setting processing for initial setting of the random number circuits 503a and 503b (step S15). In this case, the CPU 56 performs settings in accordance with the random number circuit setting program 551 to make the random number circuits 503a and 503b update the random R value.

  In addition, the game control microcomputer 560 executes a serial communication circuit setting process for initial setting of the serial communication circuit 505 (step S15a). In this case, the CPU 56 performs processing according to the serial communication circuit setting program 556, thereby setting the serial communication circuit 505 to perform serial communication with the payout control microcomputer.

  When the serial communication circuit 505 is initialized, the game control microcomputer 560 initializes the priority of interrupt processing executed in response to the interrupt request from the serial communication circuit 505 (step S15b). In this case, the CPU 56 initializes the priority of interrupt processing by executing processing according to the interrupt priority setting program 557.

  For example, the game control microcomputer 560 initializes the priority of each interrupt process according to a predetermined interrupt process priority table including the default priority of each interrupt process. FIG. 40 is an explanatory diagram of an example of the interrupt processing priority table. In this embodiment, the game control microcomputer 560 gives priority to the interrupt processing that causes the occurrence of a communication error in the serial communication circuit 505 according to the interrupt processing priority table shown in FIG. Initialize to run. In this case, for example, the game control microcomputer 560 sets an error time interrupt priority execution flag indicating that priority is given to interrupt processing that causes the occurrence of a communication error.

  In addition, the default priority of each interrupt process can be changed by the user. For example, the game control microcomputer 560 stores specification information for specifying an interrupt process set by a user (for example, a game machine manufacturer) in a predetermined storage area of the ROM 54 in advance. Then, the game control microcomputer 560 sets the priority of interrupt processing according to the designation information stored in a predetermined storage area of the ROM 54.

  The game control microcomputer 560 sets a timer interrupt setting for setting a CTC register built in the game control microcomputer 560 so that a timer interrupt is periodically taken every predetermined time (for example, 2 ms). Processing is executed (step S16). That is, a value corresponding to, for example, 2 ms is set in a predetermined register (time constant register) as an initial value. In this embodiment, it is assumed that a timer interrupt is periodically taken every 2 ms.

  When the setting of the timer interrupt is completed, the game control microcomputer 560 repeatedly executes the display random number update process (step S18). The game control microcomputer 560 disables the interrupt when the display random number update process is executed (step S17), and enters the interrupt enable state when the display random number update process ends (step S19). Note that the display random number is a random number for determining the symbol displayed on the special symbol display 8, and the display random number update processing is to update the count value of the counter for generating the display random number. It is processing.

  Note that when the display random number update process is executed, the interrupt disabled state is executed because the display random number update process is also executed in the timer interrupt process described later. This is to avoid doing so. That is, if a timer interrupt is generated during the process of step S18 and the count value of the counter for generating the display random number is updated during the timer interrupt process, the continuity of the count value is impaired. There is a case. However, such an inconvenience will not occur if the interrupt is prohibited during the process of step S18.

  As described above, a game clerk or the like can easily perform initial initialization by starting the power supply to the gaming machine (for example, turning on the power switch 914) while the clear switch 921 is turned on and the clear signal is output. Can be executed. That is, RAM clear or the like can be performed.

  Next, the random number circuit setting process (step S15) in the main process will be described. FIG. 41 is a flowchart showing random number circuit setting processing. In the random number circuit setting process, the CPU 56 first executes the process according to the random number circuit selection module 551f included in the random number circuit setting program 551, and from among the random number circuits 503a and 503b built in the game control microcomputer 560, the game A random number circuit to be used when executing the timer interrupt process including the control process is set (step S151). For example, the game control microcomputer 560 stores, in a predetermined storage area of the ROM 54, designation information for designating the random number circuit 503 used when executing a timer interrupt process set by a user (for example, a game machine manufacturer). I remember it. Then, the CPU 56 selects either the 12-bit random number circuit 503a or the 16-bit random number circuit 503b according to the designation information stored in the predetermined storage area of the ROM 54, and uses the selected random number circuit when executing the timer interrupt process. Set as a random number circuit. Note that both the 12-bit random number circuit 503a and the 16-bit random number circuit 503b may be set as random number circuits used when the timer interrupt process is executed. In this case, for example, the game control microcomputer may perform a jackpot determination based on a random number generated by the 12-bit random number circuit 503a and may perform a probability change determination based on the random number generated by the 16-bit random number circuit 503b. .

  As described above, in step S151, whether or not each of a plurality of random number circuits (12-bit random number circuit 503a and 16-bit random number circuit 503b) having different predetermined ranges of numerical data that can be updated can be used is set. Therefore, it is possible to prevent unnecessary random numbers from being processed during the execution of the timer interrupt process, and the control burden on the game control microcomputer 560 can be reduced. For example, when the game control microcomputer 560 performs the game control process using only the random number generated by one of the two random number circuits 503a and 503b, the random number is read from the random number circuit that is not used for the game control process. Processing or the like can be prevented, and the control burden on the control microcomputer 560 can be reduced.

  When the random number circuit 503 used in step S151 is set, the game control microcomputer 560 stops the operations of the counter 521 and the clock signal output circuit 524, for example, by not writing data to the random number circuit activation register 541. The counter 521 of the random number circuit set not to be used is prevented from updating the count value C. Further, for example, the game control microcomputer 560 updates the count value C of the counter 521 of the random number circuit that is set not to be used, but the game control microcomputer 560 does not output the output control signal SC. Control may be performed so that random numbers cannot be read from the random value storage circuit 531. Further, for example, the game control microcomputer 560 prevents the random number value fetch data “01h” from being written in the random number fetch register 539 of the random number circuit that is set not to be used. Control may be performed so that the latch signal SL is not output to the random value storage circuit 531.

  As described above, by setting the random number circuit 503 to be used, by setting only the random number circuit 503 to be used, the range of the random number value to be generated can be appropriately set. Further, it is possible to prevent unnecessary random numbers from being processed during the execution of the timer interrupt process, and the control burden on the game control microcomputer 560 can be reduced. For example, when the big hit determination is performed using a determination table including a distant value (for example, “1” and “100”) as the big hit determination value, the big hit is determined with a predetermined big hit probability (for example, 1/100). In this case, the number of types of determination values to be processed is smaller when the random number by the 12-bit random number circuit 503a is used than when the random number by the 16-bit random number circuit 503b is used, and the game control microcomputer 560 is used. The control burden is reduced.

  Further, the CPU 56 executes processing in accordance with the random number maximum value setting module 551a included in the random number circuit setting program 551, and generates random number maximum value setting data for designating a random number maximum value preset by the user as a random number maximum value setting register 535. (Step S152). By doing so, the random number maximum value of random R preset by the user is set in the random number circuit 503. When the 12-bit random number circuit 503a is set as the random number circuit used when the timer interrupt is executed, the CPU 56 sets the random number maximum value that specifies the random number maximum value (any value from “0” to “4095”). Data is written into the random number maximum value setting register 535 of the 12-bit random number circuit 503a. When the 16-bit random number circuit 503b is set as the random number circuit used when the timer interrupt is executed, the CPU 56 sets the random number maximum value that specifies the maximum random number value (any value from “0” to “65535”). Data is written into the random number maximum value setting register 535 of the 16-bit random number circuit 503b.

  In this embodiment, when “0” to “255” are set as the random number maximum value, the random number maximum value is reset to a predetermined value in the random number maximum value resetting process described later. Even when control is performed to write a value greater than “256” as the random number maximum value, values “0” to “255” are set in the random number maximum value setting register 535 due to data corruption or the like. In the case where it is lost, the random number maximum value is reset to a predetermined value in the random number maximum value resetting process described later.

  As described above, since the maximum value of the random number to be generated is set in advance in the random number maximum value setting register 535 in step S152, a random number having a value larger than the range of random numbers used during execution of the timer interrupt process is generated. Can be prevented, and the processing load of the random number circuit 503 and the game control microcomputer 560 can be reduced.

  Further, the CPU 56 checks whether or not the random number maximum value set in the random number maximum value setting register 535 in step S152 is not less than a predetermined lower limit value. A random number maximum value resetting process for resetting the random number maximum value set in 535 is executed (step S153).

  Further, the CPU 56 executes a process according to the initial value change module 551e included in the random number circuit setting program 551, and executes an initial value change process for changing the initial value of the count value updated by the counter 521 of the random number circuit 503 (step). S154).

  Further, the CPU 56 executes processing in accordance with the random number update method selection module 551b included in the random number circuit setting program 551, and writes the random number update method selection data in the random number update method selection register 540 (step S155). By doing so, the random number update method of the random number circuit 503 is set. In this embodiment, the CPU 56 writes the random number update method selection data “10h” in the random number update method selection register 540. That is, in this embodiment, the second random number update method is set as the random number update method of the random number circuit 503.

  Further, the CPU 56 executes processing according to the cycle setting module 551c included in the random number circuit setting program 551, and sets the cycle setting data (the reference clock signal by how many minutes) that specifies the cycle of the random number generation clock signal SI1 preset by the user. The data for setting whether to circulate) is written in the period setting register 537 (step S156). By doing so, the cycle of the random number generating clock signal SI1 preset by the user is set in the random number circuit 503.

  Further, the CPU 56 sets whether or not to update the initial value input to the counter 521 when the count value is updated to a predetermined final value by the counter 521 of the random number circuit 503 (step S157). For example, the game control microcomputer 560 sets in advance a setting value indicating whether or not to update the initial value input to the counter 521 when the count value is updated to a predetermined final value by the counter 521. And stored in a predetermined area of the ROM 54. Whether or not the CPU 56 updates the initial value input to the counter 521 when the counter 521 updates the count value to a predetermined final value in accordance with a predetermined set value stored in a predetermined storage area of the ROM 54. Set In this embodiment, when the CPU 56 determines to update the initial value input to the counter 521 in step S157, the count value is updated to a predetermined final value (when a notification signal is input from the counter 521). An initial value update flag indicating that the initial value is updated is set.

  Further, the CPU 56 sets whether or not to change the permutation of the count values updated by the counter 521 when the count value is updated to a predetermined final value by the counter 521 of the random number circuit 503 (step S158). For example, the game control microcomputer 560 sets in advance a set value indicating whether or not to change the permutation of the count values output by the counter 521 when the counter 521 updates the count value to a predetermined final value. Is stored in a predetermined area of the ROM 54. Then, the CPU 56 changes the permutation of count values output by the counter 521 when the count value is updated by the counter 521 to a predetermined final value according to a predetermined set value stored in a predetermined storage area of the ROM 54. Set whether or not. In this embodiment, if the CPU 56 determines in step S158 that the permutation of the count values output from the counter 521 is to be changed, the CPU 56 changes the permutation of the count values when the count values are updated to a predetermined final value. The indicated count value permutation change flag is set. In this embodiment, the case where the count value permutation change flag is set in step S158 according to a predetermined set value will be described. Then, the CPU 56 changes the permutation of the count values output by the counter 521 based on the fact that the count value permutation change flag is set in the count value permutation changing process described later.

  Then, the CPU 56 executes processing according to the random number circuit activation module 551d included in the random number circuit setting program 551, and writes the random number circuit activation data “80h” in the random number circuit activation register 541 (step S159). By doing so, the game control microcomputer 560 activates the random number circuit 503.

  Next, the random number maximum value resetting process (step S153) in the random number circuit setting process will be described. FIG. 42 is a flowchart showing the random number maximum value resetting process. In the random number maximum value resetting process, the CPU 56 reads the random number maximum value set in the random number maximum value setting register 535 (step S153a). When the 12-bit random number circuit 503a is set as the random number circuit used when the timer interrupt process is executed, the CPU 56 reads the random number maximum value set in the random number maximum value setting register 535 of the 12-bit random number circuit 503a. When the 16-bit random number circuit 503b is set as the random number circuit used when the timer interrupt process is executed, the CPU 56 reads the random number maximum value set in the random number maximum value setting register 535 of the 16-bit random number circuit 503b.

  The game control microcomputer 560 determines whether or not the read random number maximum value is equal to or less than a predetermined lower limit value (step S153b). When the 12-bit random number circuit 503a is set, the maximum random number value that can be set in the 12-bit random number circuit 503a is from “256” to “4095”. It is determined whether or not the maximum random number read from is lower limit value “256” or less. When the 16-bit random number circuit 503b is set, the maximum random number that can be set in the 16-bit random number circuit 503b is “256” to “65535”. It is determined whether the maximum random number value read from the register 535 is equal to or lower than the lower limit value “256”.

  If the read random number maximum value is less than or equal to the lower limit value, the game control microcomputer 560 resets the random number maximum value set in the random number maximum value setting register 535 to a predetermined value (step S153c). When the 12-bit random number circuit 503a is set, if the random number maximum value read from the random number maximum value setting register 535 of the 12-bit random number circuit 503a is determined to be less than or equal to the lower limit “256”, the CPU 56 determines the random number maximum value setting register 535. The random number maximum value set in is reset to a predetermined value “4095”. Further, when the 16-bit random number circuit 503b is set, if the random number maximum value read from the random number maximum value setting register 535 of the 16-bit random number circuit 503b is determined to be less than or equal to the lower limit value “256”, the CPU 56 sets the random number maximum value setting. The random number maximum value set in the register 535 is reset to a predetermined value “65535”.

  As described above, when the random number maximum value set in the random number maximum value setting register 535 is equal to or smaller than the predetermined lower limit value, the random number maximum value is reset to a predetermined value. Therefore, it is possible to prevent an excessively small value from being set as the maximum value of the random number due to a malfunction of the game control microcomputer 560 or an action such as generating a capture signal using a radio signal for the game machine. be able to. Therefore, it is possible to prevent a situation in which a random number having an excessively small value range from the minimum value to the maximum value is generated.

  Next, the initial value changing process (step S154) in the random number circuit setting process will be described. FIG. 43 is a flowchart showing the initial value changing process. In the initial value changing process, the CPU 56 first reads the initial value changing method setting data stored in the area 1F97h in the user program execution data area, and specifies the initial value changing method selected by the user. In this case, the CPU 56 determines whether or not the value of the read initial value changing method setting data is “01h” (step S154a), thereby specifying the initial value changing method selected by the user.

  When the value of the initial value change method setting data is “01h”, the CPU 56 sets the initial value input to the counter 521 of the random number circuit 503 to a value set based on the ID number unique to the game control microcomputer 560. Change (step S154b). For example, the game control microcomputer 560 associates, in a predetermined storage area of the ROM 54, the ID number of the game control microcomputer 560 with a calculated value obtained by performing a predetermined calculation based on the ID number. I remember it. In step S154b, the CPU 56 changes the initial value of the count value to the calculated value based on the ID number stored in advance. Further, for example, in step S154b, the CPU 56 calculates the ID number of the game control microcomputer 560 and a predetermined value (for example, the ID number (for example, “100”) to a predetermined value (for example, “100”). The initial value of the count value is set to the calculated value (for example, “200”). When the initial value input to the counter 521 is changed, the CPU 56 sets an initial value change flag indicating that the initial value of the count value has been changed (step S154c).

  When the game control microcomputer 560 changes the initial value input to the counter 521 in step S154b, the game control microcomputer 560 checks the value of the random number maximum value setting register 535 of the comparator 522 of the random number circuit 503, and based on the ID number. It is determined whether the set value is equal to or greater than the maximum random number. When it is determined that the value set based on the ID number is equal to or greater than the maximum random number, the game control microcomputer 560 does not change the initial value input to the counter 521 (for example, the initial value is “0”). Do not change). By doing so, it is possible to prevent a situation where the initial value of the count value is set to a value equal to or greater than the maximum random number.

  If the value of the initial value change method setting data is not “01h” in step S154a (that is, the value of the initial value change method setting data stored in the area 1F97h of the user program execution data area is “00h”). In the case), the CPU 56 does not change the initial value of the count value, ends the initial value changing process as it is, and proceeds to step S155.

  By executing the random number circuit setting process, various signals are input to the random number circuit 503 when the timer interrupt process including the game control process is performed, and various signals are generated in the random number circuit 503. FIG. 44 is a timing chart showing the timing at which each signal is input to the random number circuit 503 and the timing at which each signal is generated in the random number circuit 503.

  As shown in FIG. 44, the clock circuit 501 increases the signal level of the output terminal from the low level to the high level at predetermined intervals (timing T11, T21,... Shown in FIG. 44). A reference clock signal CLK (see FIG. 44A) is input to 503.

  The clock signal output circuit 524 divides the reference clock signal CLK supplied from the clock circuit 501 to generate a random number generation clock signal SI1 (see FIG. 44B). For example, the clock signal output circuit 524 raises the signal level of the output terminal from the low level to the high level at timings T11, T12,..., And changes the signal level from the high level to the low level at timings T21, T22,. To output a random number generating clock signal SI1.

  In the example shown in FIG. 44, the case where the clock signal output circuit 524 generates the random number generating clock signal SI1 by dividing the reference clock signal CLK by two is shown for easy understanding. However, in the actual random number circuit, the period that can be set in the period setting register 537 is from “system clock signal period × 128 × 7” to “system clock signal period × 128 × 256”. Therefore, in an actual random number circuit, the clock signal output circuit 524 is set in the cycle setting register 537 in a range from “system clock signal cycle × 128 × 7” to “system clock signal cycle × 128 × 256”. The reference clock signal CLK is divided by a division ratio corresponding to the cycle setting data “07h” to “FFh” to generate a random number generating clock signal SI1. The random number generating clock signal SI 1 generated by the clock signal output circuit 524 is output to the selector 528 and the inverting circuit 532.

  In this embodiment, since the second random number update method is set in the random number circuit setting process, the second random number update method selection signal is input from the random number update method selection signal output circuit 527 to the selector 528. When the second random number update method selection signal output circuit 527 receives the second random number update method selection signal output circuit 527, the selector 528 selects the random number generation clock signal SI1 input from the clock signal output circuit 524 and outputs it to the counter 521. . Each time the rising edge of the random number generating clock signal SI1 supplied from the selector 528 is input, the counter 521 updates the count value C and outputs it to the count value permutation changing circuit 523.

  The inversion circuit 532 generates the inverted clock signal SI2 (see FIG. 44C) by inverting the signal level of the random number generation clock signal SI1 input from the clock signal output circuit 524. For example, the inverting circuit 532 lowers the signal level of the output terminal from the high level to the low level at timings T11, T12,..., And the signal level from the low level to the high level at timings T21, T22,. As a result, the inverted clock signal SI2 is output. Further, the inverted clock signal SI <b> 2 generated by the inverting circuit 532 is output to the latch signal generating circuit 533.

  When a predetermined time (for example, 3 milliseconds) elapses after the winning detection signal SS (see FIG. 44D) is input to the timer circuit 534, the latch signal generation circuit 533 receives a disturbance from the random value read signal output circuit 526. A numerical reading signal is input. For example, when the signal level of the output terminal of the random number read signal output circuit 526 rises from a low level to a high level, the random value read signal is input to the latch signal generation circuit 533. The latch signal generation circuit 533 inverts the random value read signal input from the random value read signal output circuit 526 in response to the input of the second random number update method selection signal from the random number update method selection signal output circuit 527. A latch signal SL (see FIG. 44E) is output in synchronization with the rising edge of the inverted clock signal SI2 supplied from 532.

  As described above, the random number circuit 503 updates the count value C at the timings T11, T12, T13..., And outputs the latch signal SL at the timing T22 different from the timings T11, T12, T13. The random number value is stored in 531.

  Next, the serial communication circuit setting process (step S15a) in the main process will be described. FIG. 45 is a flowchart showing the serial communication circuit setting process. In the serial communication circuit setting process, the CPU 56 first executes the process according to the serial communication circuit setting program 556 to set the baud rate of the serial communication circuit 505 (step S1511). In this case, the CPU 56 writes a setting value corresponding to the baud rate to be set in the baud rate register 702 of the serial communication circuit 505. For example, the game control microcomputer 560 stores specification information for specifying a set value set by a user (for example, a game machine manufacturer) in a predetermined storage area of the ROM 54 in advance. Then, the CPU 56 writes the setting value in the baud rate register 702 according to the designation information stored in a predetermined storage area of the ROM 54. For example, when the baud rate set value “156” is set by the CPU 56, the baud rate “1201.92 bps” is generated by the baud rate generation circuit 703 using the equation (1) and the clock frequency “3 MHz”.

  Further, the CPU 56 sets a data format of data transmitted / received by the serial communication circuit 505 (step S1512). In this case, the CPU 56 sets the data length (8 bits or 9 bits) of the transmission / reception data and the presence / absence of the parity function by setting the value of each bit of the control register A707. For example, the game control microcomputer 560 stores specification information for specifying the value of each bit of the control register A707 set by the user (for example, the manufacturer of the game machine) in a predetermined storage area of the ROM 54 in advance. Yes. Then, the CPU 56 sets the value of each bit of the control register A707 according to the designation information stored in a predetermined storage area of the ROM 54.

  In addition, the CPU 56 sets whether to permit each interrupt request generated by the serial communication circuit 505 (step S1513). In this case, the CPU 56 sets whether or not to permit a transmission interrupt request (interrupt request to be made when transmission is completed) and a reception interrupt request by setting the values of bits 5 and 6 of the control register B708. Further, the CPU 56 sets whether or not to permit an interrupt request at the time of each communication error by setting the values of the bits 0 to 3 of the control register C709. For example, the gaming control microcomputer 560 stores, in advance, a predetermined storage area in the ROM 54 for specifying information for specifying the value of each bit of the control register B 708 and the control register C 709 set by the user (for example, the manufacturer of the gaming machine). I remember it. Then, the CPU 56 sets the value of each bit of the control register B 708 and the control register C 709 according to the designation information stored in a predetermined storage area of the ROM 54.

  Next, the game control process will be described. FIG. 46 is a flowchart showing the timer interrupt process. When a timer interrupt occurs during execution of the main process, specifically, in a period during which interruption is permitted during execution of the loop process of steps S17 to S19, the CPU 56 of the game control microcomputer 560 A game control process is executed in a timer interrupt process activated in response to the occurrence of a timer interrupt. In the timer interrupt process, the CPU 56 first executes a power-off process (power-off detection process) for detecting whether or not a power-off signal is output (whether the power-on signal is turned on) (step S20). Subsequently, detection signals of switches such as the gate switch 32a, the start port switch 14a, the count switch 23, and the winning port switches 29a, 30a, 33a, and 39a are input via the switch circuit 58, and their state is determined (switch) Process: Step S21). Specifically, if the state of the input port for inputting the detection signal of each switch is ON, the value of the switch timer provided corresponding to each switch is incremented by one.

  Next, the CPU 56 checks whether the initial value is set to be updated when the count value is updated to a predetermined final value in the random number circuit setting process (see step S157), and the counter of the random number circuit 503 is checked. A process of updating the initial value input to 521 is performed (initial value update process: step S22). Further, the CPU 56 performs a process of updating the count value of the counter for generating the display random number (display random number update process: step S23).

  When the initial value update process and the display random number update process are performed, the CPU 56 performs a count value permutation change process that causes the count value permutation change circuit 523 to change the permutation of count values output by the counter 521 of the random number circuit 503 (step S24). ). In this embodiment, whether or not to execute the count value permutation change process is determined depending on whether or not the count value permutation change flag is set in step S158 of the random number circuit setting process. Then, the CPU 56 executes the count value permutation change process based on the fact that the count value permutation change flag is set.

  Further, the CPU 56 performs special symbol process processing (step S25). In the special symbol process control, corresponding processing is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state. Further, normal symbol process processing is performed (step S26). In the normal symbol process, the corresponding process is selected and executed according to the normal symbol process flag for controlling the display state of the normal symbol display 10 in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state.

  Next, the CPU 56 performs a process of setting an effect control command related to the decorative symbol synchronized with the change of the special symbol in a predetermined area of the RAM 55 and sending the effect control command (decorative symbol command control process: step S27). Note that the fact that the variation of the decorative symbol is synchronized with the variation of the special symbol means that the variation time (variable display period) is the same.

  Further, the CPU 56 performs information output processing for outputting data such as jackpot information, start information, probability variation information supplied to the hall management computer, for example (step S28).

  Further, the CPU 56 executes prize ball processing for setting the number of prize balls based on detection signals from the prize opening switches 29a, 30a, 33a, 39a and the like (step S29). Specifically, a payout command command such as a prize ball number command indicating the number of prize balls is output to the payout control board 37 in response to winning detection based on the winning opening switches 29a, 30a, 33a, 39a being turned on. . The payout control microcomputer 370 mounted on the payout control board 37 drives the ball payout device 97 in response to receiving a prize ball number command indicating the number of prize balls.

  And CPU56 performs the memory | storage process which checks the increase / decrease in a pending | holding memory | storage number (step S30). Further, a test terminal process, which is a process for outputting a test signal for enabling the control state of the gaming machine to be confirmed outside the gaming machine, is executed (step S31). In this embodiment, a RAM area (output port buffer) corresponding to the output state of the output port is provided, but the CPU 56 outputs the contents related to the solenoid in the RAM area of the output port 2 to the output port. (Step S32: Solenoid output processing). Thereafter, the CPU 56 sets the interrupt permitted state (step S33) and ends the process.

  With the above control, in this embodiment, the game control process is started periodically (for example, every 2 ms). In this embodiment, the game control process is executed by the timer interrupt process. However, in the timer interrupt process, for example, only a flag indicating that an interrupt has occurred is set, and the game control process has a flag. It may be executed in the main process based on the setting.

  Also, for example, in the timer interrupt process, only the switch process (see step S21), the decorative symbol command control process (see step S27), and the interrupt count process (described later in steps S321a and S322) are included in the game control process. It may be executed, and other processes in the game control process may be executed in the main process. In this case, the game control microcomputer 560 includes steps S22 to S26 (excluding the interrupt count processing) and step S29 in the loop process from step S17 to step S19 in the main process. Step S33 (excluding step S31) is executed. In addition, after the CPU 56 of the game control microcomputer has counted the number of interrupts in the timer interrupt process (see step S321a), the number of executions of the timer interrupt process has reached a predetermined number (for example, 3 times). If this is detected (see step S322), it is determined that a condition for reading a random number value from the random number circuit 503 is satisfied, and a random number read flag indicating that the condition for reading the random number value is satisfied is set. Further, the CPU 56 of the game control microcomputer 560 determines whether or not the random number read flag is set during execution of the start port switch passing process (see step S312) in the special process (see step S25) in the main process. If it is determined that the random number read flag is set, the output control signal SC is output to the random value storage circuit 531 of the random number circuit 503 (see step S323), and stored as a random value from the random value storage circuit 531. The random R value thus read is read (see step S324). In the main process, the CPU 56 determines whether or not to make a big hit based on the read random number value when executing the special symbol normal process (see step S300) in the special process process (see step S25). become. In this embodiment, the processes of steps S21 to S32 (except for steps S28 and S31) correspond to a game control process for controlling the progress of the game.

  Next, the initial value update process (step S22) in the timer interrupt process will be described. FIG. 47 is a flowchart showing the initial value update process. In the initial value update process, the game control microcomputer 560 checks the state of the notification signal indicating that the count value C output from the counter 521 of the random number circuit 503 has been updated to the final value (step S220). When it is detected that the notification signal is in the on state, the game control microcomputer 560 checks whether or not the initial value update flag is set (step S221). That is, the game control microcomputer 560 confirms whether or not the setting for updating the initial value is made when the count value is updated to a predetermined final value in the random number circuit setting process (see step S157). .

  When the initial value update flag is set, the game control microcomputer 560 determines to update the initial value input to the counter 521 when the counter 521 of the random number circuit 503 updates the count value to a predetermined final value. To do. If the initial value update flag is set, the game control microcomputer 560 checks whether the initial value change flag is set (step S222). That is, the game control microcomputer 560 determines whether or not the initial value of the count value is currently changed (that is, whether or not it is changed to a value based on the ID number of the game control microcomputer 560).

  When the initial value change flag is set (that is, the initial value is currently changed based on the value based on the ID number of the game control microcomputer 560), the game control microcomputer 560 inputs the initial value to the counter 521. The value is returned to the original value (for example, “1”) from the value based on the ID number of the game control microcomputer 560 (step S223). Then, the game control microcomputer 560 resets the initial value change flag (step S224), and ends the initial value update process.

  When the initial value change flag is not set (that is, the initial value is not currently changed), the game control microcomputer 560 uses the initial value input to the counter 521 as the ID number of the game control microcomputer 560. The value is changed to the original value (step S225). In this case, for example, if the ID number of the game control microcomputer 560 is “100”, the initial value input to the counter 521 is calculated by adding a predetermined value “100” to the ID number “100”. Change to the value “200”. Further, for example, the initial value input to the counter 521 is changed to the calculated value “50” obtained by subtracting the predetermined value “50” from the ID number “100”. Then, the game control microcomputer 560 sets an initial value change flag (step S226), and ends the initial value update process.

  When both the 12-bit random number circuit 503a and the 16-bit random number circuit 503b are set, in step S225, the game control microcomputer 560 uses the random number read from one random number circuit (for example, the 12-bit random number circuit 503a). An initial value input to the counter 521 may be obtained by adding the ID number as a predetermined value. Then, the game control microcomputer 560 may use the random number read from the other one (for example, the 16-bit random number circuit 503b) as the random number for determining the big hit.

  When the game control microcomputer 560 updates the initial value input to the counter 521 in step S225, the game control microcomputer 560 checks the value of the random number maximum value setting register 535 of the comparator 522 of the random number circuit 503, and based on the ID number. It is determined whether the set value is equal to or greater than the maximum random number. When it is determined that the value set based on the ID number is equal to or greater than the maximum random number, the game control microcomputer 560 does not update the initial value input to the counter 521 with the predetermined value (for example, the predetermined value “ 0 ”is not updated). By doing so, it is possible to prevent a situation where the initial value of the count value is set to a value equal to or greater than the maximum random number.

  If it is determined in step S220 that the notification signal is in the off state, and if it is determined in step S221 that the initial value update flag is not set, the game control microcomputer 560 inputs the initial value to the counter 521. Without updating the initial value update process, the process proceeds to step S23.

  Next, the count value permutation change process (step S24) in the timer interrupt process will be described. FIG. 48 is a flowchart showing the count value permutation changing process. The game control microcomputer 560 executes the count value permutation change process by executing the process according to the count value permutation change program 554. In the count value permutation changing process, the game control microcomputer 560 checks the state of the notification signal indicating that the count value C output from the counter 521 of the random number circuit 503 has been updated to the final value (step S241). When it is detected that the notification signal is turned on, the game control microcomputer 560 checks whether or not the count value permutation change flag is set (step S242). That is, whether or not the game control microcomputer 560 is set to change the permutation of the count values updated by the counter 521 when the count values are updated to a predetermined final value in the random number circuit setting process ( Confirm step S158).

  When the count value permutation change flag is set, the game control microcomputer 560 displays the permutation of the count values updated by the counter 521 when the counter 521 of the random number circuit 503 updates the count value to a predetermined final value. Judge to change. Then, the game control microcomputer 560 writes the count value permutation change data “01h” in the count value permutation change register 536 (step S243). That is, the game control microcomputer 560 causes the count value permutation change circuit 523 to change the permutation of the count values C input to the random value storage circuit 531 by writing the count value permutation change data “01h”.

  As described above, in the count value permutation changing process, when the random number is updated to a predetermined final value, the permutation of the count value updated by the counter 521 is changed, so that the randomness generated by the random number circuit 503 is more random. Can be improved.

  Next, the special symbol process (step S25) in the main process will be described. FIG. 49 is a flowchart showing an example of a special symbol process processing program executed by the game control microcomputer 560. When the CPU 56 of the game control microcomputer 560 performs the special symbol process, the variation shortening timer subtraction process (step S310) is performed, and the game ball is won in the start winning opening 14 provided in the game board 6. If the start opening switch 14a for detecting is turned on, that is, if a start winning that causes the game ball to win the start winning opening 14 is generated (step S311), the start opening switch passing process (step S312) is performed. After that, any one of steps S300 to S308 is performed according to the internal state. The variation shortening timer is a timer for setting the variation time when the variation time of the special symbol is shortened.

  Special symbol normal processing (step S300): A state where variable symbol special display can be started (for example, the symbol variation has not been made in the special symbol display 8, and the previous symbol variation in the special symbol display 8 has ended) Waits for a predetermined period of time to elapse, and not a big hit game). When the special symbol variable display can be started, the start winning memory number for the special symbol is confirmed. If the start winning memorized number is not 0, it is determined based on the random R generated by the random number circuit 503 whether or not the result of variable symbol special display is a big hit. Then, the internal state (special symbol process flag) is updated so as to shift to step S301.

  Special symbol stop symbol setting process (step S301): A stop symbol after variable display of the special symbol is determined. Then, the internal state (special symbol process flag) is updated so as to shift to step S302.

  Variation time setting process (step S302): A variation pattern is determined, and variation time in the variation pattern (variable display time: time from when variable display is started until display result is derived display (stop display)) is a special symbol It is determined to be a variable display variable time. In addition, a variation time timer that measures the variation time of the determined special symbol is started. Then, the internal state (special symbol process flag) is updated so as to shift to step S303.

  Special symbol variation process (step S303): When a predetermined time (the time indicated by the variation time timer in step S302) elapses, the internal state (special symbol process flag) is updated to shift to step S304.

  Special symbol stop process (step S304): A decorative symbol stop command for instructing stop of the decorative symbol is transmitted to the effect control board 80. Moreover, the special symbol in the special symbol display 8 is stopped. If the stop symbol of the special symbol is a big hit symbol, the internal state (special symbol process flag) is updated to shift to step S305. If not, the internal state is updated to shift to step S300. Note that a configuration in which a decorative symbol stop command is not transmitted may be employed. In this case, the effect control board 80 sets the change time in the change time timer based on the change pattern command from the main board 31 and updates the change time timer to uniquely change the change time of the decorative pattern. What is necessary is just to perform the process which stops the decorative design when it monitors and it determines with the fluctuation | variation time having passed.

  Preliminary winning opening opening process (step S305): Control for opening the large winning opening is started. Specifically, a counter (for example, a counter that counts the number of game balls that have entered the grand prize opening) and a flag (a flag used when detecting winning in the prize opening) are initialized, and the solenoid 21 is driven. Open the big prize opening. Also, the process timer sets the execution time of the big prize opening opening process and sets the big hit flag. Then, the internal state (special symbol process flag) is updated so as to shift to step S306.

  Processing for opening a special prize opening (step S306): control for sending a presentation control command for round display of the special prize opening to the production control board 80 and closing conditions for the special prize opening (for example, a predetermined number (for example, 10 for the special prize opening) ) To confirm that the game ball has won a prize). When the closing condition for the special prize opening is satisfied, the internal state is updated to shift to step S307.

  Specific area valid time process (step S307): The presence / absence of passing through the V winning switch 22 is monitored, and a process of confirming that the big hit gaming state continuation condition is satisfied is performed. If the condition for continuing the big hit gaming state is satisfied and there are still remaining rounds, the internal state is updated to shift to step S305. In addition, when the big hit gaming state continuation condition is not satisfied within a predetermined effective time, or when all rounds are finished, the internal state is updated to shift to step S308.

  Big hit end processing (step S308): Control for causing the effect control means to perform display control for notifying the player that the big hit gaming state has ended. Then, the internal state is updated so as to shift to step S300.

  FIG. 50 is a flowchart showing the start port switch passage process (step S312). In the start port switch passing process, the CPU 56 of the game control microcomputer 560 sets the start winning memory number indicated by the start winning counter (or the start winning memory number stored in the special figure holding memory 570) to 4 which is the maximum value. It is confirmed whether it has reached (step S321). If the start winning memorized number has not reached 4, the CPU 56 adds 1 to the value of the interrupt counter indicating the number of times the timer interrupt process has been executed (step S321a). That is, the CPU 56 executes a process of counting the number of times that the timer interrupt process has been executed. In this embodiment, by executing step S321a, the CPU 56 counts up an interrupt number counter indicating the number of times the timer interrupt process has been executed each time the timer interrupt process is executed. When the value of the interrupt counter is incremented by 1, the CPU 56 checks whether or not the number of executions of the timer interrupt process indicated by the interrupt execution counter is reached a predetermined number (for example, 3 times) (step S322). ). When detecting that the game ball has won the start winning opening 14, the CPU 56 resets the interrupt execution counter. Then, after the game ball has won the start winning opening 14, the CPU 56 checks whether or not the interrupt execution counter has reached a predetermined number.

  The value set in advance as the predetermined number of times in step S322 is determined as follows. As described above, the timer circuit 534 of the random number circuit 503 measures the time that the winning detection signal SS is continuously input from the start port switch 14a, and detects that the measurement time has reached a predetermined period, Write numerical value capture data “01h”. In this embodiment, a predetermined period (for example, 3 ms) measured by the timer circuit 534 is a period in which a predetermined number of timer interrupt processes are executed (for example, when the timer interrupt process for every 2 ms is executed three times). The predetermined number of times (for example, 3 times) used in step S322 is set so as to be shorter than 6 ms. By setting in this way, it is possible to prevent the random number from being read again after the random number is read and before the random number value stored in the random value storage circuit 531 is updated. It is possible to prevent a random number having the same value as the random number read from the circuit 531 from being read again.

  When the number of executions of the timer interrupt process has reached a predetermined number, the CPU 56 can output the output control signal SC to the random number storage circuit 531 of the specified random number circuit 503 and read the random number storage circuit 531 (enable). The state is controlled (step S323).

  The CPU 56 reads the random R value stored as the random number value from the random value storage circuit 531 of the random number circuit 503 (step S324). Further, the CPU 56 stores the read random R value in, for example, a predetermined buffer area provided in the RAM 55 (step S325). Further, when the random value R is stored in the buffer area, the CPU 56 stops outputting the output control signal SC to the random value storage circuit 531 and controls the random value storage circuit 531 to be in a non-readable (disabled) state (step). S326). In addition, the CPU 56 resets the interrupt execution number counter (step S327). Then, the CPU 56 sets the value of the random R stored in the predetermined buffer area to the head of the empty entry in the special figure reservation memory 570 (step S328), and adds 1 to the count number of the start winning counter, thereby storing the start winning memory. The number is incremented by 1 (step S329).

  If the start prize is stored in step S321 but the maximum value of 4 has been reached, and if the number of executions of the timer interrupt process has not reached the predetermined number in step S322, the start port switch passing process is terminated.

  As described above, the timer interrupt process has been executed a predetermined number of times when reading the random R from the random value storage circuit 531 in the starting port switch passing process (that is, continued while the timer interrupt process is executed a predetermined number of times). The random number is read from the random value storage circuit 531 on the condition that the winning detection signal SS is input). Therefore, it is possible to prevent the random number from being read again after the random number is read and before the value of the random number stored in the random value storage circuit 531 is updated. Further, it is possible to prevent a random number having the same value as the random number read from the previous random number value storage circuit 531 from being read again.

  Next, the special symbol normal process (step S300) in the special symbol process will be described. FIG. 51 is a flowchart showing special symbol normal processing. In the special symbol normal process, the CPU 56 of the game control microcomputer 560 can start the variation of the special symbol (for example, when the value of the special symbol process flag is a value indicating step S300) ( In step S380), the random R value stored in correspondence with the hold number “1” is read from the special figure hold memory 570 (step S381). In this case, the CPU 56 decrements the count of the start winning counter by 1 to reduce the number of reserved memories by 1, and the second to fourth entries of the special figure reservation memory 570 (hold numbers “2” to “4”). The value of random R stored in is shifted upward by one entry (step S382).

  Further, the CPU 56 checks whether or not the probability variation flag is set (step S383). That is, the CPU 56 confirms whether or not the gaming state is controlled to the certain change state. When the probability variation flag is not set, the CPU 56 determines that the gaming state is a normal state other than the probability variation state, and is a table used for determining whether or not the display result of the special symbol display device 8 is a jackpot symbol. The normal big hit determination table 571a (see FIG. 37A) is set (step S384). Further, when the probability change flag is set, the CPU 56 determines that the gaming state is a probability change state, and as a table used to determine whether or not the display result of the special symbol display device 8 is a jackpot symbol. A probability change big hit determination table 571b (see FIG. 37B) is set (step S385).

  The CPU 56 determines whether or not the display result of the special symbol display device 8 is a big hit symbol based on the random R value stored in the predetermined buffer area in the start port switch passing process (step S386). In this case, the CPU 56 uses the normal-time big hit determination table 571a set in step S384 or the probability change big hit determination table 571b set in step S385 to determine whether or not to win.

  If it is determined that the display result of the special symbol display device 8 is a jackpot symbol, the CPU 56 turns on a jackpot flag indicating that it is a jackpot state (step S387). If it is determined that the display result of the special symbol display device 8 is not to be a big hit symbol, the CPU 56 turns off the big hit flag (step S388). Then, the CPU 56 updates the value of the special symbol process flag to a value corresponding to the special symbol stop symbol setting process (step S389).

  Next, payout control signals and payout control commands transmitted and received between the main board 31 and the payout control board 37 will be described. FIG. 52 is an explanatory diagram showing an example of the contents of a control signal output from the game control means to the payout control means. In this embodiment, a connection confirmation signal is transmitted and received as a control signal between the main board 31 and the payout control board 37 in order to perform various controls relating to payout control and the like. As shown in FIG. 52, the connection confirmation signal is output when the main board 31 rises (when the game control means starts the game control process), indicating that the main board 31 has risen with respect to the payout control board 37. This is a signal for notification (connection confirmation signal for the main board 31). The connection confirmation signal indicates that the winning ball can be paid out.

  Similarly to the game control microcomputer 560, the payout control microcomputer 370 includes a serial communication circuit 375. Various payout control commands are transmitted and received between the serial communication circuit 505 built in the game control microcomputer 560 and the serial communication circuit 375 built in the payout control microcomputer 370. The configuration and function of the serial communication circuit 375 built in the payout control microcomputer 370 are the same as the configuration and function of the serial communication circuit 505 built in the game control microcomputer 560.

  FIG. 53 is an explanatory diagram showing an example of the contents of control commands transmitted and received between the game control means and the payout control means. In this embodiment, various control commands are transmitted and received between the main board 31 and the payout control board 37 in order to perform various controls relating to payout control and the like.

  The award ball number command is a command that is output to designate the number of game balls (0 to 15) for which a payout request is made. In this embodiment, when a game ball is detected by the start port switch 14a, four prize balls are paid out, and when a game ball is detected by any of the prize port switches 33a, 39a, 29a, 30a, seven balls are detected. When a game ball is detected by the count switch 23, 15 prize balls are paid out. Therefore, when a game ball is detected by the start port switch 14a, a prize ball number command “04” for notifying the number of prize balls of 4 is transmitted, and any of the prize port switches 33a, 39a, 29a, 30a is transmitted. When a game ball is detected, a prize ball number command “07” for notifying the number of prize balls 7 is transmitted, and when a game ball is detected by the count switch 23, the number of prize balls 15 is notified. The award ball number command “0F” is transmitted.

  The prize ball ACK command “D2” is a command for notifying the game control means that the payout control means has received the prize ball number command. The prize ball ACK command corresponds to a reception confirmation signal indicating that a prize ball number command has been received.

  54 is a block diagram showing signal lines and the like used for transmission / reception of the control signal shown in FIG. 52 and the control command shown in FIG. FIG. 54 also shows a power-off signal. As shown in FIG. 54, the connection confirmation signal is output by the game control microcomputer 560 via the output circuit 67 and input to the payout control microcomputer 370 via the input circuit 373A. The power-off signal is output via the output circuit 373B and input to the game control microcomputer 560 via the input circuit 68. The prize ball number command is output from the serial circuit 505 built in the game control microcomputer 560 and is input to the serial circuit 375 built in the payout control microcomputer 370. The award ACK command is output from the serial circuit 375 built in the payout control microcomputer 370 and input to the serial circuit 505 built in the game control microcomputer 560.

  Each of the connection confirmation signal and the power-off signal is 1-bit data and is transmitted through one signal line. Also, between the main board 31 and the payout control board 37, the signal line for the power-off signal to the game control microcomputer 560 and the signal line for the control signal (connection confirmation signal) related to the payout control are wired together. can do. Therefore, in the gaming machine, the wiring space related to the power-off signal to the gaming control microcomputer 560 can be saved.

  FIG. 55 is a timing chart showing an example of how to output a payout control signal and a payout control command. As shown in FIG. 55, when the winning detection switch detects a winning of a game ball, the game control means (game controlling microcomputer 560) pays out a winning ball number command corresponding to the number of winning balls paid out in accordance with the winning. This is transmitted to the control means (dispensing control microcomputer 370). Specifically, when the gaming control microcomputer 560 detects that a game ball has won a winning area provided in the gaming machine by a detection signal of the winning detection switch, the gaming control microcomputer 560 calculates a predetermined number of winning balls. It is added to the content of the total number of winning balls stored in the backup RAM. When the content of the total winning ball number storage buffer becomes a non-zero value, a winning ball number command corresponding to the number of winning balls paid out in accordance with winning is transmitted to the payout control microcomputer 370.

  In this embodiment, when a game ball is detected by the start port switch 14a, four prize balls are paid out, and when a game ball is detected by any of the prize port switches 33a, 39a, 29a, 30a. Seven prize balls are paid out, and when a game ball is detected by the count switch 23, 15 prize balls are paid out. Specifically, the game control microcomputer 560 determines that the number of prize balls is four when the number of prize balls is four according to the number of prize balls to be paid out. When the number of prize balls is 7, a prize ball number command “07” indicating that the number of prize balls is 7, and the number of prize balls is 15 when the number of prize balls is 15. A prize ball number command “0F” indicating 15 is transmitted.

  When the transmission of the award ball number command is completed, the serial communication circuit 505 of the game control microcomputer 560 makes a transmission interrupt request to the CPU 56 of the game control microcomputer 560 as shown in FIG. Due to the transmission interrupt request, the CPU 56 recognizes that the transmission of the award ball number command has been completed, and waits for a reception confirmation signal from the payout control microcomputer.

  When the payout control microcomputer 370 confirms reception of the prize ball number command, it stores the number of prize balls indicated in the received prize ball number command in the reception buffer of the payout control microcomputer 370. Also, the payout control microcomputer 370 adds the number of prize balls to a prize ball non-payout number counter provided in a predetermined area of the RAM. Then, the payout control microcomputer 370 transmits a prize ball ACK command “D2” to the game control microcomputer 560. Note that the payout control microcomputer 370 may store the number of prize balls in the reception counter in the interrupt process based on the reception interrupt request from the serial communication circuit 375 built in the payout control microcomputer 370. In this case, when the serial communication circuit 375 built in the payout control microcomputer 370 receives the prize ball number command, the serial communication circuit 375 makes an interrupt request during reception to the CPU of the payout control microcomputer 370. Then, the CPU of the payout control microcomputer 370 stores the prize ball number in the reception buffer by executing an interrupt process in response to an interrupt request from the serial communication circuit 375.

  When the prize ball ACK command is received and the prize data ACK command is stored in the reception data register 711, the serial communication circuit 505 of the game control microcomputer 560, as shown in FIG. A reception interrupt request is made to the CPU 56 of 560. The CPU 56 recognizes that the serial communication circuit 505 has received the data by executing the interrupt process by the interrupt request at the time of reception, and receives a prize ball ACK command from the reception data register 711 in the prize ball ACK wait process described later. Read.

  FIG. 56 is a flowchart showing an example of the prize ball processing in step S29. In the prize ball process, the game control microcomputer 560 executes a prize ball number addition process (step S1201) and a prize ball control process (step S1202). Then, the contents of the port 0 buffer formed in the RAM 55 are output to port 0 (step S1203). The contents of the port 0 buffer are updated in the prize ball control process.

  In the loop process from step S17 to step S19 in the main process, if there is an interrupt request from the serial communication circuit 505 during the interrupt enabled state, the CPU 56 of the game control microcomputer 560 causes the serial communication circuit 505 to generate an interrupt request. Execute interrupt processing according to the cause of the interrupt. FIG. 57 is a flowchart showing an example of interrupt processing performed by the serial communication circuit 505 in response to an interrupt request. FIG. 57A shows a communication error interrupt process executed by the CPU 56 when the serial communication circuit 505 makes an interrupt request with a communication error as an interrupt cause. FIG. 57B shows reception interrupt processing executed by the CPU 56 when an interrupt request is issued with the serial communication circuit 505 receiving reception data as an interrupt cause. FIG. 57 (c) shows a transmission completion interrupt process executed by the CPU 56 when an interrupt request is issued with the cause of the interruption that the serial communication circuit 505 has completed transmission of transmission data.

  The CPU 56 determines whether or not any interrupt process is preferentially executed. For example, the CPU 56 determines whether or not any interrupt process is preferentially executed. In this embodiment, the CPU 56 gives priority to an interrupt process that causes the occurrence of a communication error in the serial communication circuit 505 based on the setting of the error priority interrupt execution flag. Execute.

  When there is an interrupt request from the serial communication circuit 505, the CPU 56 checks each bit of the status register A 705 of the serial communication circuit 505 to identify the cause of the interrupt. In this case, the CPU 56 determines whether or not any interrupt process is preferentially executed. For example, the CPU 56 determines whether or not any interrupt process is preferentially executed. In this embodiment, the CPU 56 gives priority to an interrupt process that causes the occurrence of a communication error in the serial communication circuit 505 based on the fact that the communication error interrupt priority execution flag is set. And execute.

  The CPU 56 preferentially checks bit 0 to bit 3 of the status register A705 based on the fact that the communication error interrupt priority execution flag is set, and identifies the cause of the interrupt. That is, the CPU 56 determines whether another interrupt cause (reception of received data has been received) as to whether or not an interrupt request has occurred due to the occurrence of a communication error (overrun, noise error, framing error or parity error) in the serial communication circuit 505. Or, determination is performed with priority over transmission data transmission completion). If the CPU 56 determines that one or more of the bits 0 to 3 of the status register A 705 is “1”, the CPU 56 specifies that the cause of the interruption is that a communication error has occurred in the serial communication circuit 505. To do.

  If it is determined that the cause of the interruption is that a communication error has occurred in the serial communication circuit 505, the CPU 56 changes the communication error interrupt processing shown in FIG. 57A to another interrupt processing (FIG. 57B and FIG. It is executed with priority over the interrupt processing shown in (c). In this case, the CPU 56 sets a communication error flag indicating that a communication error has occurred in the serial communication circuit 505 (step S41).

  When a communication error is detected, the game control microcomputer 560 notifies the effect control means that a communication error has occurred in the serial communication circuit 505. Display command). When receiving the communication error display command, the effect control CPU performs an effect using sound, display, light emitter, etc., and notifies that a communication error has occurred.

  If the cause of the interruption is not the occurrence of a communication error in the serial communication circuit 505, the CPU 56 checks bit 5 of the status register A. That is, the CPU 56 determines whether or not the cause of the interrupt is that the serial communication circuit 505 has received the received data. When determining that the bit 5 of the status register A is “1”, the CPU 56 specifies that the cause of the interruption is that the serial communication circuit 505 has received the reception data.

  If it is determined that the cause of the interruption is that the serial communication circuit 505 has received the received data, the CPU 56 executes a reception interrupt process shown in FIG. In this case, the CPU 56 sets a reception interrupt flag indicating that the serial communication circuit 505 is receiving reception data (step S42).

  If the cause of the interruption is not a communication error occurring in the serial communication circuit 505, the CPU 56 confirms bit 6 of the status register A. That is, the CPU 56 determines whether or not the cause of the interrupt is that the serial communication circuit 505 has completed transmission of transmission data. When determining that the bit 6 of the status register A is “1”, the CPU 56 specifies that the cause of the interruption is that the serial communication circuit 505 has completed transmission of transmission data.

  If it is determined that the cause of the interruption is that the serial communication circuit 505 has completed transmission of transmission data, the CPU 56 executes transmission completion interrupt processing shown in FIG. In this case, the CPU 56 sets a transmission interrupt flag indicating that the serial communication circuit 505 has completed transmission of transmission data (step S43).

  By executing the processing described above, the CPU 56 of the game control microcomputer 560 identifies an interrupt cause when an interrupt request is received from the serial communication circuit 505, and a flag corresponding to the identified interrupt cause. (Communication error flag, reception interrupt flag or transmission interrupt flag) is set. When the flag is set according to the specified interrupt cause, the CPU 56 recognizes that a communication error has occurred in the serial communication circuit 505, that data has been received, or that data transmission has been completed.

  Note that the CPU mounted on the payout control microcomputer 370 also identifies the cause of the interrupt according to the same process as the process shown in FIG. 57 when an interrupt request is received from the serial communication circuit 375, and the identified interrupt cause. Set the flag according to.

  For example, consider a case where a prize ball number command is transmitted from the game control microcomputer 560 to the payout control microcomputer 370 by one-way communication. In this case, the game control microcomputer 560 is configured to generate a timer interrupt to the payout control microcomputer 370, for example, every 2 ms. After the prize ball number command is transmitted, the next interrupt process is performed. Assume that the award ball number command is transmitted again after 2 ms. The payout control microcomputer 370 is configured to generate a timer interrupt every 4 ms, for example, and can receive a prize ball number command every 4 ms. Then, even though the game control microcomputer 560 has not read the first prize ball number command transmitted, the payout control microcomputer 370 may receive the next prize ball number command. If the CPU of the payout control microcomputer 370 is set to receive the award ball number command in response to the interrupt request at the time of reception from the serial communication circuit 375, the award ball number command from the game control microcomputer 560 is surely received. Can be received.

  In the prize ball number adding process, a prize ball number table shown in FIG. 58 is used. The prize ball number table is set in the ROM 54. The number of processes (in this example, “6”) is set in the first address of the winning ball number table, and then the lower address of the switch-on buffer (the one corresponding to input port 0 of the 2-byte switch-on buffer) The switch input bit determination value and the number of winning balls for each switch of the winning opening that will pay out the winning ball by winning are sequentially set corresponding to each of the switches of the winning opening. The switch input bit determination value is a value corresponding to a bit to which the detection signal of each switch at the input port 0 is input. The upper address of the switch-on buffer is a fixed value (for example, 7F (H)). In the prize ball number table, the same data is set in each of the lower addresses of the six switch-on buffers. In this embodiment, the addresses of the ROM 54 and the RAM 55 are designated by 16 bits.

  FIG. 59 is a flowchart showing the prize ball number adding process. In the winning ball number adding process, the game control microcomputer 560 sets the start address of the winning ball number table as a pointer (step S1211). Then, the data at the address pointed to by the pointer (in this case, the number of processes) is loaded (step S1212). Next, the upper address (8 bits) of the switch-on buffer is set in the upper 1 byte of the 2-byte check pointer (step S1213).

  Then, the value of the pointer is incremented by 1 (step S1214), the prize ball number table data pointed to by the pointer (in this case, the lower address of the switch-on buffer) is set in the lower 1 byte of the check pointer (step S1215), The pointer value is incremented by 1 (step S1216). Next, the address data pointed to by the check pointer, that is, the contents of the switch-on buffer is loaded into the register (step S1217). ) And the logical product (step S1218). As a result, 7 bits other than the bit corresponding to the detection signal of the switch to be inspected become 0 in the register loaded with the contents of the switch-on buffer. Then, the pointer value is increased by 1 (step S1219).

  If the calculation result in step S1218 is 0, that is, if the detection signal of the switch to be inspected is on, the prize ball number table data pointed to by the pointer (in this case, the number of prize balls) is the prize ball addition value. (Steps S1220 and S1221), and the prize-ball addition value is added to the contents of the 16-bit total prize-ball number storage buffer formed in the RAM 55 (step S1222). If a carry occurs as a result of the addition, the content of the total number of winning balls storage buffer is set to 65535 (= FFFF (H)) (steps S1223 and 1224).

  In step S1225, the number of processes is reduced by 1. If the number of processes is 0, the process ends. If the number of processes is not 0, the process returns to step S1214 (step S1226). In step S1220, when it is confirmed that the calculation result in step S1218 is 0, that is, the detection signal of the switch to be inspected is in an OFF state, the process proceeds to step S1225.

  FIG. 60 is a flowchart showing the prize ball control process in step S1202. In the prize ball control process, the game control microcomputer 560 executes any one of steps S1231 to S1235 in accordance with the value of the prize ball process code after executing the prize ball abnormality detection process in step S1230.

  FIG. 61 is a flowchart showing a prize ball transmission waiting process (step S1231) executed when the value of the prize ball process code is zero. The game control microcomputer 560 checks whether or not the communication error flag is set in the award ball transmission waiting process (step S1241). That is, the game control microcomputer 560 first checks whether or not a communication error has occurred in the serial communication circuit 505. If the communication error flag is set, the game control microcomputer 560 ends the process. That is, since a communication error has occurred in the serial communication circuit 505, the game control microcomputer 560 controls to prohibit communication with the payout control board 37.

  If the communication error flag is not set, the game control microcomputer 560 checks the contents of the total prize ball number storage buffer (step S1242). If the value is 0, the process ends. If not, the prize ball process code value is set to 1 (step S1243), and the process ends.

  FIG. 62 is a flowchart showing a prize ball number command transmission process (step S1232) executed when the value of the prize ball process code is 1. The game control microcomputer 560 checks whether or not the communication error flag is set in the prize ball transmission process (step S1251). That is, the game control microcomputer 560 first checks whether or not a communication error has occurred in the serial communication circuit 505. When the communication error flag is set, the game control microcomputer 560 prohibits communication with the payout control board 37 and ends the processing as it is. That is, since a communication error has occurred in the serial communication circuit 505, the game control microcomputer 560 controls to prohibit communication with the payout control board 37. In this case, the game control microcomputer 560 performs control to prohibit data transmission to the payout control board 37 by, for example, stopping the function of the transmission unit of the serial communication circuit 505. For example, the CPU 56 prohibits data transmission to the payout control board 37 by setting bit 3 of the control register B 708 of the serial communication circuit 505 to “0” and not using the transmission circuit.

  If the communication error flag is not set, the game control microcomputer 560 checks whether or not the content of the total prize ball number storage buffer is smaller than the prize ball command maximum value (“15” in this example) (step). S1252). If the content of the total prize ball number storage buffer is equal to or greater than the prize ball command maximum value, the prize ball command maximum value is set in the prize ball number buffer (step S1253). If the content of the total prize ball number storage buffer is smaller than the maximum value of the prize ball command, the content of the total prize ball number storage buffer is set in the prize ball number buffer (step S1254).

  Thereafter, the game control microcomputer 560 writes the content of the prize ball number buffer as a prize ball number command to the transmission data register 710 of the serial communication circuit 505 (step S1255), and sets the value of the prize ball process code to 2 ( In step S1256), the process ends. In this embodiment, the maximum value of the prize ball command is “15”. Therefore, a prize ball number command for designating the maximum number of payouts of “15” is written in the transmission data register 710. Thereafter, the award ball number command written in the transmission data register 710 is transferred to the transmission shift register 712 and transmitted from the transmission shift register 712 to the payout control microcomputer.

  FIG. 63 is a flowchart showing a prize ball transmission completion waiting process (step S1233) executed when the value of the prize ball process code is 2. The game control microcomputer 560 checks whether or not the communication error flag is set in the award ball transmission completion waiting process (step S1261). That is, the game control microcomputer 560 first checks whether or not a communication error has occurred in the serial communication circuit 505. If the communication error flag is set, the game control microcomputer 560 ends the process. That is, since a communication error has occurred in the serial communication circuit 505, the game control microcomputer 560 controls to prohibit communication with the payout control board 37.

  If the communication error flag is not set, the game control microcomputer 560 checks whether or not the transmission interrupt flag is set (step S1262). If the transmission interrupt flag is set, the game control microcomputer 560 proceeds to the process of step S1263. If the transmission interrupt flag is not set, the game control microcomputer 560 ends the process. That is, the game control microcomputer 560 determines whether or not the serial communication circuit 505 has already completed transmission of the prize ball number command written to the transmission data register 710 in the prize ball number command transmission process, and the prize ball number command When it is confirmed that the transmission of is completed, the processing after step S1263 is executed.

  If the transmission interrupt flag is set, the game control microcomputer 560 resets the transmission interrupt flag (step S1263). Then, the game control microcomputer 560 subtracts the content of the prize ball number buffer (the number of prize balls paid out to the payout control means) from the content of the total prize ball number storage buffer (step S1264).

  Further, the game control microcomputer 560 sets an ACK reception completion determination time value in the prize ball timer (step S1266). Then, the value of the prize ball process code is set to 3 (step S1267), and the process is terminated. The ACK reception completion determination time value is a time value for monitoring whether or not a prize ball ACK command is received from the payout control means.

  FIG. 64 is a flowchart showing a prize ball ACK waiting process (step S1234) executed when the value of the prize ball process code is 3. The game control microcomputer 560 checks whether or not the communication error flag is set in the award ball ACK waiting process (step S1271). That is, the game control microcomputer 560 first checks whether or not a communication error has occurred in the serial communication circuit 505. When the communication error flag is set, the game control microcomputer 560 prohibits communication with the payout control board 37 and ends the processing as it is. That is, since a communication error has occurred in the serial communication circuit 505, the game control microcomputer 560 controls to prohibit communication with the payout control board 37. In this case, the game control microcomputer 560 controls the reception of data from the payout control board 37 by prohibiting the function of the receiving unit of the serial communication circuit 505, for example. For example, the CPU 56 prohibits data reception from the payout control board 37 by setting bit 2 of the control register B 708 of the serial communication circuit 505 to “0” and not using the receiving circuit.

  If the communication error flag is not set, the game control microcomputer 560 checks whether or not the reception interrupt flag is set (step S1272). That is, the game control microcomputer 560 checks whether the serial communication circuit 505 receives the received data and stores the data in the received data register 711. If the reception interrupt flag is set, the game control microcomputer 560 proceeds to the process of step S1273. If the interrupt flag at the time of reception is not set, the game control microcomputer 560 proceeds to the process of step S1275.

  If the reception interrupt flag is set, the game control microcomputer 560 reads data from the reception data register 711 of the serial communication circuit 505 (step S1273). Further, the game control microcomputer 560 determines whether or not the read data is a prize ball ACK command (whether or not it is a command “D2”) (step S1274).

  When the reception interruption flag is not set in step S1272, or when the data read in step S1274 is not a prize ball ACK command, the game control microcomputer 560 still receives a prize from the payout control microcomputer 370. It is determined that the ball ACK command has not been received. In this case, the game control microcomputer 560 decreases the value of the prize ball timer by 1 (step S1275), and if the value is not 0, the process ends (step S1276). When the value of the prize ball timer reaches 0, it is determined that the payout control microcomputer 370 has not transmitted the prize ball ACK command, a retransmission flag is set (step S1277), and the value of the prize ball process code is set to 4. (Step S1278), and the process ends. When the value of the prize ball process code becomes 4, the prize ball re-transmission process (step S1235) is executed. When the retransmission flag is set, a payout abnormality notification start command is transmitted to the effect control board 80 in the prize ball abnormality detection process (step S1230).

  In step S1274, when it is confirmed that the data read from the reception data register 711 is a prize ball ACK command, the game control microcomputer 560 resets the reception interrupt flag (step S1279), and a prize ball process code. Is set to 0 (step S1280). If the retransmission flag is set because the communication is normally completed, the retransmission flag is reset (steps S1281 and S1282).

  Through the above processing, the game control means stores the total number of game balls as prize balls to be paid out based on the establishment of the payout condition in the total prize ball number storage buffer so as to be specified. The game control means also issues a payout command command (award ball number command) for designating a payout number of a predetermined number of prize balls to the payout control means based on the number of prize balls stored in the total prize ball number storage buffer. Send. Here, the predetermined number is 15 if the number of prize balls stored in the total prize ball number storage buffer is 15 or more, and is stored in the total prize ball number storage buffer if it is less than 15. The number of prize balls. Then, when a prize ball number command designating the prize ball payout is transmitted, a subtraction process is performed to subtract the payout number designated by the prize ball number command from the prize ball number stored in the total prize ball number storage buffer. Since the payout control microcomputer 370 transmits a prize ball ACK command immediately after receiving the prize ball number command, communication regarding the prize ball number command can be completed regardless of the prize ball payout from the ball payout device 97. The control microcomputer 560 can continuously transmit the next award ball number command before the payout of the number of payouts designated by the award ball number command is completed.

  In this embodiment, as the prize game medium number storage means for storing the total number of prize game media to be paid out based on the establishment of the payout condition, a total prize ball number storage buffer for storing the total number itself is exemplified. However, the prize game medium number storage means for storing the total number of prize game media in an identifiable manner stores the number of prizes received in each prize area or the number of prizes for each prize area (for example, 4). The number of winning holes 14 corresponding to the number of winning balls, the number of winning holes 33, 39, 29, 30 corresponding to the number of 7 winning balls, and the number of winning prizes corresponding to the number of 15 winning balls, , The number of winning prizes for which the winning ball payout has not ended yet) may be stored. In that case, a prize ball number command in which a number corresponding to the number of prize balls for each winning area is set is transmitted from the game control microcomputer 560 to the payout control microcomputer 370. Further, instead of transmitting a winning ball number command indicating the number of winning balls, a game command microcomputer 560 transmits a payout command command indicating that there has been a winning or a winning number to the payout control microcomputer 370. It may be.

  FIG. 65 is a flowchart showing the prize ball re-transmission process (step S1235) executed when the value of the prize ball process code is 4. The game control microcomputer 560 checks whether or not the communication error flag is set in the winning ball re-transmission process (step S1291). That is, the game control microcomputer 560 first checks whether or not a communication error has occurred in the serial communication circuit 505. When the communication error flag is set, the game control microcomputer 560 prohibits communication with the payout control board 37 and ends the processing as it is. That is, since a communication error has occurred in the serial communication circuit 505, the game control microcomputer 560 controls to prohibit communication with the payout control board 37. In this case, the game control microcomputer 560 performs control to prohibit data transmission to the payout control board 37 by, for example, stopping the function of the transmission unit of the serial communication circuit 505. For example, the CPU 56 prohibits data transmission to the payout control board 37 by setting bit 3 of the control register B 708 of the serial communication circuit 505 to “0” and not using the transmission circuit.

  If the communication error flag is not set, the game control microcomputer 560 rewrites the contents of the prize ball number buffer in the transmission data register 710 of the serial communication circuit 505 as the prize ball number command (step S1292). Further, the game control microcomputer 560 sets the ACK reception completion determination time value in the prize ball timer again (step S1293). Then, the value of the prize ball process code is set to 3 (step S1294), and the process ends.

  Since the value of the prize ball process code is set to 3, the prize ball ACK waiting process is executed again. In the award ball ACK waiting process to be executed again, if it is not detected that the award ball ACK command has been received again, specifically, if the award ball timer times out in step S1276, the award ball again A retransmission process is executed. As described above, when the game control microcomputer 560 cannot receive the winning ball ACK command as the reception confirmation signal indicating that the payout amount data has been received, the winning ball number command is received until the winning ball ACK command can be received. Repeat retransmissions.

  FIG. 66 is a flowchart showing the prize ball abnormality detection process in step S230. In the prize ball abnormality detection process, when the game control microcomputer 560 detects that the re-transmission flag has changed from the reset state to the set state, the game control microcomputer 560 uses the payout abnormality notification start command as an effect control command to the effect control board 80 ( Specifically, transmission control is performed (to the production control microcomputer 100) (steps S1301 and S1302). Note that the game control microcomputer 560 does not transmit the payout abnormality notification start command after executing the prize ball retransmission process, but transmits the payout abnormality notification start command to the effect control board 80 and then retransmits the prize ball. Processing may be executed.

  When transmitting the effect control command to the effect control microcomputer 100, the game control microcomputer 560 stores a command transmission table (preliminarily set for each command in the ROM 54) according to the type of effect control command. Set the address to a pointer. Then, the address of the command transmission table corresponding to the effect control command is set in the pointer, and the effect control command is transmitted in the decorative symbol command control process (step S27).

  In addition, the game control microcomputer 560 detects that the re-transmission flag has changed from the set state to the reset state. Then, the payout abnormality notification end command is transmitted to the effect control board 80 (specifically, to the effect control microcomputer 100) (steps S1303 and S1304).

  In this embodiment, when the re-transmission flag is reset, the game control microcomputer 560 transmits a payout abnormality notification end command in step S1304, but may not be transmitted. In that case, the game control microcomputer 560 is reduced. In that case, the production control microcomputer 100 is configured to terminate the payout abnormality notification independently after a predetermined time, for example.

  Next, an operation in which the payout control microcomputer 370 transmits and receives various commands will be described. As shown in FIG. 54, the payout control microcomputer 370 includes a serial communication circuit 375 for serially communicating various commands with the game control microcomputer 560. The payout control microcomputer 370 uses the serial communication circuit 375 to receive the prize ball number command shown in FIG. 53 from the game control microcomputer 560. When receiving the prize ball number command, the payout control microcomputer 370 uses the serial communication circuit 375 to transmit the prize ball ACK command “D2” shown in FIG. 53 as a reception confirmation signal.

  Similarly to the CPU 56 of the game control microcomputer 560, if the CPU of the payout control microcomputer 370 receives an interrupt request from the serial communication circuit 375 while it is in the interrupt enabled state, the serial communication circuit 375 Execute interrupt processing according to the cause of the interrupt. In this embodiment, when the CPU of the payout control microcomputer 370 specifies that the cause of the interruption is that the serial communication circuit 375 has received the received data, the reception interrupt is performed according to the same processing as in FIG. Execute the process. In this case, the CPU of the payout control microcomputer 370 sets a reception interrupt flag indicating that the serial communication circuit 375 is receiving reception data.

  FIG. 67 is a flowchart showing a main control communication process in which the payout control microcomputer 370 communicates with the game control means (game control microcomputer 560) of the main board 31. In the main control communication process, the payout control microcomputer 370 checks whether or not the connection confirmation signal is on (step S541). Note that the connection confirmation signal being in the on state means that power is supplied and the game control means can control the progress of the game, and that the connection confirmation signal is in the off state means This means that the supply stop process is started and the game control means cannot progress the game (the connection confirmation signal is turned off by the output port clear process in the power supply stop process).

  The payout control microcomputer 370 confirms whether or not the reception interrupt flag is set (step S542). That is, the payout control microcomputer 370 confirms whether or not the serial communication circuit 375 receives the received data and the data is stored in the reception data register of the serial communication circuit 375.

  If the reception interrupt flag is set, the payout control microcomputer 370 reads data from the reception data register of the serial communication circuit 375 (step S543). Further, the payout control microcomputer 370 determines whether or not the read data is a prize ball number command (whether the command is “04”, “07”, or “0F”) (step). S544).

  When it is confirmed that the data read from the reception data register of the serial communication circuit 375 is a prize ball number command, the payout control microcomputer 370 resets a reception interrupt flag (step S545), and a prize ball number command. Is added to the award ball unpaid number counter (step S546). Then, the payout control microcomputer 370 writes the prize ball ACK command to the transmission data register 710 of the serial communication circuit 505 (step S547), and ends the process. Thereafter, the winning ball ACK command written in the transmission data register is transferred to the transmission shift register of the serial communication circuit 375 and is transmitted from the transmission shift register of the serial communication circuit 375 to the game control microcomputer 560. The prize ball receiving buffer is formed in the RAM.

  As described above, in this embodiment, the random number circuit 503 is initially set (random number circuit setting process) from the start of power-on to the gaming machine until the timer interrupt is set, and the random number circuit In the setting process, a value based on the ID number unique to the game control microcomputer 560 is set as the initial value of the random number. Therefore, the randomness of the random number generated by the random number circuit 503 can be improved. In addition, since randomness of random numbers can be improved, the timing of random number generation can be made difficult to be recognized by a player or a game store, and a capture signal using a radio signal can be generated for a gaming machine. It is possible to prevent the condition for shifting to a specific gaming state such as a big hit state from being illegally established.

  Also, in this embodiment, when the serial communication circuit 505 makes an interrupt request, the interrupt process when a communication error is caused as an interrupt cause is preferentially executed to control the communication to a prohibited state. Therefore, it is possible to prevent communication with the payout control board 37 mounted on the gaming machine in a state where a communication error has occurred. Therefore, malfunction due to a communication error can be prevented.

  For example, when an overrun occurs in the serial communication circuit 505, the next received data is stored in the receiving shift register 713 before the received data in the received data register 711 is read. It is overwritten and the game control microcomputer 560 cannot read the received data correctly. For this reason, communication with each control board cannot be performed correctly, causing the game control microcomputer 560 to malfunction. In this embodiment, when an overrun occurs, the serial communication circuit 505 issues an interrupt request at the time of a communication error, and the game control microcomputer 560 controls the communication to a prohibited state. Therefore, it is possible to prevent the gaming control microcomputer 560 from malfunctioning due to the occurrence of overrun.

  Further, for example, if a noise error occurs in the serial communication circuit 505, there is a high possibility that correct received data cannot be received due to the noise, which causes the gaming control microcomputer 560 to malfunction. In this embodiment, when a noise error occurs, the serial communication circuit 505 makes an interrupt request at the time of a communication error, and the game control microcomputer 560 controls the communication to a prohibited state. Therefore, it is possible to prevent the gaming control microcomputer 560 from malfunctioning due to the occurrence of a noise error.

  Also, for example, if a framing error occurs in the serial communication circuit 505, it is in a state where the stop bit of the received data has not been correctly received. Cause it. In this embodiment, when a framing error occurs, the serial communication circuit 505 issues an interrupt request at the time of a communication error, and the game control microcomputer 560 controls the communication to a prohibited state. Therefore, it is possible to prevent the gaming control microcomputer 560 from malfunctioning due to the occurrence of a framing error.

  Further, for example, when a parity error occurs in the serial communication circuit 505, it is in a state in which each data bit or parity bit of the received data has not been received correctly, so there is a high possibility that correct received data cannot be received. This may cause the computer 560 to malfunction. In this embodiment, when a parity error occurs, the serial communication circuit 505 makes an interrupt request at the time of a communication error, and the game control microcomputer 560 controls the communication to a prohibited state. Therefore, it is possible to prevent the gaming control microcomputer 560 from malfunctioning due to the occurrence of a parity error.

  Further, in this embodiment, when a communication error occurs in the serial communication circuit 505, transmission of the prize ball number command to the payout control board 37 and reception of the prize ball ACK command from the payout control board 37 are prohibited. To control. For example, if a prize ball number command is transmitted to the payout control board 37 when a communication error occurs, an incorrect prize ball number command may be transmitted. Therefore, an incorrect number of game balls may be paid out based on the number of prize balls indicated in the wrong prize ball number command, which may affect the game result. In this embodiment, when a communication error occurs, control is performed to prohibit transmission of a prize ball number command to the payout control board 37, so that an incorrect number of game balls are paid out based on an incorrect prize ball command. It is possible to prevent the game result from being affected.

  Note that when a communication error occurs in the serial communication circuit 505, only reception of data from each control board may be prevented. For example, consider a case where serial communication is performed between the game control means and the effect control means. In this case, the communication performed between the game control microcomputer 560 and the effect control microcomputer is only the transmission of the effect control command from the game control microcomputer 560 to the effect control microcomputer. No command is transmitted from the microcomputer to the game control microcomputer 560. That is, communication in only one direction is performed between the game control microcomputer 560 and the effect control microcomputer. Further, even if an erroneous effect control command is transmitted from the game control microcomputer 560 to the effect control board 80, only an incorrect effect display is performed on the variable display device 9, and an incorrect payout process is executed. Compared with the case where it ends, the influence which it has on a game result is small. Therefore, when serial communication is performed between the game control means and the effect control means, if a communication error occurs in the serial communication circuit 505, the game control microcomputer 560 controls to prohibit only data reception. Also good.

  In this embodiment, the inverting circuit 532 of the random number circuit 503 generates the inverted clock signal SI2 whose polarity is inverted, and outputs a latch signal for instructing storage of the random number in synchronization with the inverted clock signal SI2. . Therefore, the timing for updating the random number and the timing for storing the random number in the random value storage circuit 531 can be shifted, and the generated random number can be stored stably and reliably.

Embodiment 2. FIG.
In the first embodiment, the clock signal input to the latch signal generation circuit 533 is inverted, and the timing for updating the random number and the timing for storing the random number in the random value storage circuit 531 are shifted. The clock signal input to the generation circuit 533 may be delayed. Hereinafter, a second embodiment in which a clock signal input to the latch signal generation circuit 533 is delayed will be described.

  In the present embodiment, detailed description of the parts having the same configuration and processing as those in the first embodiment will be omitted, and parts different from those in the first embodiment will be mainly described.

  FIG. 68 is a block diagram illustrating another configuration example of the random number circuit 503. In this embodiment, the basic configurations of the 12-bit random number circuit 503a and the 16-bit random number circuit 503b are the same. As shown in FIG. 68, this embodiment is different from the first embodiment in that the random number circuit 503 includes a delay circuit 532A instead of the inverting circuit 532 shown in FIG.

  The delay circuit 532A delays the random number generation clock signal SI1 input from the clock signal output circuit 524, thereby generating a delayed clock signal SI4 obtained by delaying the clock signal. Further, the delay circuit 532A outputs the generated delayed clock signal SI4 to the latch signal generation circuit 533. Therefore, in this embodiment, the latch signal generation circuit 533 outputs a latch signal to the random value storage circuit 531 in synchronization with the delayed clock signal SI4 obtained by delaying the random number generation clock signal SI1.

  The basic functions of the constituent elements of the random number circuit 503 other than the delay circuit 532A are the same as those functions described in the first embodiment.

  As described above, in this embodiment, the delay circuit 532A of the random number circuit 503 generates the delayed clock signal SI4 and outputs a latch signal for instructing storage of the random number in synchronization with the delayed clock signal SI4. . Therefore, the timing for updating the random number and the timing for storing the random number in the random value storage circuit 531 can be shifted, and the generated random number can be stored stably and reliably.

Embodiment 3 FIG.
In each of the embodiments described above, the case where the gaming control microcomputer 560 executes the interrupt process at the time of a communication error with priority over other interrupt processes has been described. Other than the interrupt process at the time of a communication error The interrupt process (for example, the interrupt process at the time of reception) may be preferentially executed. Hereinafter, a third embodiment in which interrupt processing at the time of reception is preferentially executed will be described.

  In the present embodiment, detailed description of the parts having the same configuration and processing as those in the first embodiment will be omitted, and parts different from those in the first embodiment will be mainly described.

  In this embodiment, the game control microcomputer 560 executes the main process according to the same process as in FIGS. In the main process, the process from step S1 to step S15a (including the process from step S80 and the process from step S91 to step S93) is the same as those shown in the first embodiment. Further, the processes from step S16 to step S19 are the same as those shown in the first embodiment.

  When the serial communication circuit setting process in step S15a is executed and the serial communication circuit 505 is initialized, the game control microcomputer 560 initializes the priority of the interrupt process executed in response to the interrupt request from the serial communication circuit 505. (Step S15b). In this embodiment, an interrupt process that causes an interruption cause that the serial communication circuit 505 has received the received data is specified in advance in the specification information. Based on the designation information, the game control microcomputer 560 performs initialization so as to preferentially execute an interrupt process whose cause is the reception of received data. That is, in this embodiment, in the interrupt processing priority table shown in FIG. 40, by default, the interrupt processing that causes the occurrence of a communication error in the serial communication circuit 505 is preferentially executed. Although set, the game control microcomputer 560 interrupts based on the designation information set by the user so as to preferentially execute an interrupt process whose cause is the reception of received data. Change processing priority. In this case, for example, the game control microcomputer 560 sets a reception-time interrupt priority execution flag indicating that priority is given to interrupt processing that causes reception of received data.

  In the loop process from step S17 to step S19 in the main process, if there is an interrupt request from the serial communication circuit 505 during the interrupt enabled state, the CPU 56 of the game control microcomputer 560 follows the process shown in FIG. The serial communication circuit 505 executes interrupt processing according to the interrupt cause for which an interrupt request has been made.

  The CPU 56 determines whether or not any interrupt process is preferentially executed. For example, the CPU 56 determines whether or not any interrupt process is preferentially executed. In this embodiment, the CPU 56 preferentially executes an interrupt process in which the reception data is received based on the fact that the reception interrupt priority execution flag is set.

  When there is an interrupt request from the serial communication circuit 505, the CPU 56 checks each bit of the status register A 705 of the serial communication circuit 505 to identify the cause of the interrupt. In this embodiment, the CPU 56 preferentially confirms bit 5 of the status register A705 to identify the cause of the interrupt. That is, the CPU 56 determines whether or not the serial communication circuit 505 has made an interrupt request due to the fact that the received data has been received as an interrupt cause in preference to other interrupt causes (the occurrence of a communication error or the completion of transmission of transmission data). . When determining that the bit 5 of the status register A is “1”, the CPU 56 specifies that the cause of the interruption is that the serial communication circuit 505 has received the reception data.

  When it is determined that the cause of the interruption is that the serial communication circuit 505 has received the received data, the CPU 56 preferentially executes the reception interrupt process shown in FIG. In this case, the CPU 56 sets a reception interrupt flag indicating that the serial communication circuit 505 is receiving reception data (step S42).

  As described above, in this embodiment, the game control microcomputer 560 initializes the priority of interrupt processing before setting the interrupt-permitted state in the main processing. For this reason, it is possible to reliably execute an interrupt process to be preferentially executed among interrupt processes corresponding to a plurality of types of interrupt causes. In addition, since the interrupt process to be executed with priority can be initialized, the degree of freedom of the program executed by the game control microcomputer 560 can be improved.

  For example, in the reception process in the prize ball process (for example, the prize ball ACK waiting process in step S1234), each bit of the status register A705 is checked to determine whether or not a communication error has occurred in the serial communication circuit 505. If a simple program is built, control can be performed so that a command is not received when a communication error occurs without executing an interrupt process that causes the occurrence of a communication error. Therefore, when a program that confirms the occurrence of a communication error in the reception process is built, priority is given to the interrupt process that causes the reception of data to cause a game control micro The degree of freedom of the program executed by the computer 560 can be improved.

  Next, the overall configuration of a slot machine (slot machine), which is another example of the gaming machine in each of the embodiments described above, will be described. FIG. 69 is a front view of the slot machine as seen from the front.

  As shown in FIG. 69, in the slot machine 600, a game panel 601 is detachably attached near the center. Further, a variable display device 602 for variably displaying a plurality of types of symbols is provided near the center of the front surface of the game panel 601. In this embodiment, the variable display device 602 has three symbol display areas of “left”, “middle”, and “right”, and the symbol display reels 602a, 602b, and 602c correspond to the symbol display areas, respectively. Is provided.

  Below the game panel 601, an operation table 620 is provided in which various input switches and the like for the player to perform various operations are arranged. On the back side of the operation table 620, a BET switch 621 for betting (putting) coins one by one, and a MAXBET switch 622 for betting coins by the maximum number (three in this example) that can be placed in one game. A settlement switch 623 and a coin insertion slot 624 are provided. Coins inserted into the coin insertion slot 624 are detected by an inserted coin sensor (not shown).

  On the front side of the operation table 620, a start switch 625, a left reel stop switch 626a, a middle reel stop switch 626b, a right reel stop switch 626c, and a coin jam elimination switch 627 are provided. Lamps 628a and 628b are provided on the right and left sides of the operation table 620, respectively. Below the operation table 620, a speaker 630 for outputting sound effects and the like is provided.

  On the upper part of the game panel 601, an image display device (LCD: liquid crystal display device) 640 for notifying a player of a game method, a game state, and the like is provided. For example, when a winning occurs, an image in which a character performs a predetermined action is displayed on the image display device 640 to notify the player that a winning flag described later is set. Two speakers 641L and 641R that emit sound effects are provided on the left and right of the image display device 640.

  The winning combinations generated in the slot machine 600 include a small winning combination, a replay winning, a big bonus winning, and a regular bonus winning. In the slot machine 600, random numbers are extracted at the timing when the start switch 625 is operated, and it is determined whether or not the winning of any winning combination is allowed. The fact that winnings are allowed is said to be “winning internally”. When an internal winning is made, a winning flag indicating that is set in the slot machine 600. In the game with the winning flag set, the reels 602a to 602c are controlled so that the winning combination corresponding to the winning flag can be drawn. On the other hand, in a game in which the winning flag is not set, the reels 602a to 602c are controlled so that no winning is generated.

  Note that the game control microcomputer that controls the progress of the game of the slot machine 600 incorporates a random number circuit (12-bit random number circuit and 16-bit random number circuit) that generates random numbers. Further, the game control microcomputer extracts the random number (random R) generated by the random number circuit at the timing when the start switch 625 is operated. For example, when the start switch 625 is pressed, the game control microcomputer 560 inputs the detection signal SS from the start switch 625. When the timer circuit 534 of the random number circuit detects that the detection signal SS has been input continuously for a predetermined time, the random number value fetch data “01h” is written to the random value fetch register 539 and the latch signal generation circuit 533 is written. Outputs the latch signal SL to the random value storage circuit 531. When the latch signal SL is input, the random value storage circuit 531 reads and stores the count value updated by the counter 521. In addition, when the game control microcomputer 560 detects that the detection signal SS is continuously input a predetermined number of times (for example, three times), the game control microcomputer 560 outputs the output control signal SC to the random value storage circuit of the random number circuit. Then, a random value (random R) is extracted from the random number circuit. Then, the game control microcomputer determines whether or not the winning is allowed based on the extracted random R.

  The game control microcomputer of the slot machine 600 incorporates a serial communication circuit, and serially communicates various commands with each control board (payout control board and effect control board) of the slot machine 600.

Next, an outline of the game provided by the slot machine will be described.
For example, when a multiplier is set by inserting a coin from the coin insertion slot 624 and pressing the BET switch 621 or the MAXBET switch 622, the operation of the start switch 625 becomes effective. When the player operates the start switch 625, the symbol display reels 602a to 602c provided in the variable display device 602 start rotating. In addition, when a regular bonus prize or a big bonus prize is won internally at the timing when the start switch 625 is operated, for example, a screen on which a predetermined character performs a predetermined action is displayed on the image display device 640. Thus, the player or the like is notified that the internal winning is made.

  When a predetermined time elapses after the symbol display reels 602a to 602c start rotating, the operations of the reel stop switches 626a to 626c become effective. In this state, if the player presses one of the reel stop switches 626a to 626c, the rotation of the reel corresponding to the operated stop switch is stopped. When the symbol display reels 602a to 602c are left for a predetermined period or longer without being stopped, the symbol display reels 602a to 602c are automatically stopped.

  When all the symbol display reels 602a to 602c are stopped, the symbol display reels 602a to 602c displayed on the variable display device 602 are determined according to the number of symbols in the upper, middle and lower three symbols. Whether or not a prize is won is determined by a combination of symbols positioned on a valid winning line. When the multiplying number is 1, only the middle one horizontal winning line in the variable display device 602 is valid. When the multiplying number is 2, the top three, the middle, and the bottom three pay lines in the variable display device 602 are valid. When the number of multiplications is 3, a total of five pay lines of three horizontal rows and two diagonal diagonal lines in the variable display device 602 are effective lines.

  When a combination of symbols on the active line becomes a specific display mode determined in advance and a winning occurs, a predetermined game effect is made by sound, light, display on the image display device 640, etc., and the winning is generated The game according to is started.

  In the slot machine 600, the effect control means mounted on the slot machine 600 performs display control of the image display device 640 provided in the slot machine 600. The image display device 640 displays various kinds of information such as a decorative pattern change display and a display for notifying a game state and a game method under the control of the effect control means. Various information such as decorative pattern variation display, display for notifying a game state and a game method, and the like are displayed by a movie image, and display control of the movie image is performed by the image processing device 640. do it.

  The present invention is applicable to gaming machines such as pachinko gaming machines and slot machines, and in particular, can be suitably applied to gaming machines equipped with a gaming control microcomputer incorporating a random number circuit and a serial communication circuit.

It is the front view which looked at the pachinko game machine from the front. It is a front view which shows the front surface of the game board in the state which removed the glass door frame. It is the rear view which looked at the gaming machine from the back. It is a block diagram which shows the structural example of a game control board (main board). It is a block diagram showing a circuit configuration of the main board and a signal line of an effect control command transmitted from the main board to the effect control board. It is a block diagram which shows the structural example of a random number circuit. It is explanatory drawing which shows the example of an update rule selection register. It is explanatory drawing which shows the example of an update rule memory. It is explanatory drawing which shows the example in case a count value permutation change circuit changes the permutation of the count value which a counter outputs. It is explanatory drawing which shows the example of a count value permutation change register. It is explanatory drawing which shows the example of a random number maximum value setting register. It is explanatory drawing which shows the example of a period setting register. It is explanatory drawing which shows the example of a count value update register. It is explanatory drawing which shows the example of a random value taking-in register. It is explanatory drawing of an example of the random number update system selection register and the random number update system selection data written in the random number update system selection register. It is explanatory drawing which shows the example of a random number circuit starting register. It is a circuit diagram which shows one structural example of a random value memory circuit. It is a timing chart which shows the timing when each signal is input into a random value storage circuit, and the timing when a random value storage circuit outputs each signal. It is a block diagram which shows the structural example of the transmission part of a serial communication circuit. It is a block diagram which shows the structural example of the receiving part of a serial communication circuit. It is explanatory drawing which shows the example of the data format of the data which serial communication transmits / receives with each control board. It is explanatory drawing which shows the example of a baud rate register. It is explanatory drawing which shows the example of the control register A and communication format setting data. It is explanatory drawing which shows the example of the control register B and interrupt request setting data. It is a figure which shows the example of status register A and status confirmation data. It is a figure which shows the example of status register B and status confirmation data. It is explanatory drawing which shows the example of the control register C and error interrupt request setting data. It is explanatory drawing which shows the example of the data register with which a serial communication circuit is provided. It is explanatory drawing which shows an example of the address map of the storage area in the microcomputer for game control. It is explanatory drawing which shows an example of the address map in a user program management area. It is explanatory drawing which shows an example of initial value change system setting data. It is explanatory drawing which shows the structural example of a user program. It is explanatory drawing which shows the structural example of a random number circuit setting program. It is explanatory drawing which shows the operation | movement which updates the value of random R, or reads the value of random R, when the 1st random number update system is selected. It is explanatory drawing which shows the operation | movement which updates the value of random R, or reads the value of random R, when the 2nd random number update system is selected. It is explanatory drawing which shows each memory with which the microcomputer for game control is provided. It is explanatory drawing which shows the example of the table memory for jackpot determination. It is a flowchart which shows the main process which the microcomputer for game control performs. It is a flowchart which shows the main process which the microcomputer for game control performs. It is explanatory drawing which shows the example of an interruption process priority table. It is a flowchart which shows a random circuit setting process. It is a flowchart which shows a random number maximum value reset process. It is a flowchart which shows an initial value change process. It is a timing chart which shows the timing when each signal is input into a random number circuit, and the timing when each signal is generated in a random number circuit. It is a flowchart which shows a serial communication circuit setting process. It is a flowchart which shows a timer interruption process. It is a flowchart which shows an initial value update process. It is a flowchart which shows a count value permutation change process. It is a flowchart which shows an example of a special symbol process process. It is a flowchart which shows a starting port switch passage process. It is a flowchart which shows an example of a special symbol normal process. It is explanatory drawing which shows an example of the content of the control signal output with respect to the payout control means from a game control means. It is explanatory drawing which shows an example of the content of the control command transmitted / received between a game control means and a payout control means. It is a block diagram which shows the signal line etc. which are used for transmission / reception of a control signal and a control command. It is a timing chart showing an example of how to output a payout control signal and a payout control command. It is a flowchart which shows an example of a prize ball process. 6 is a flowchart illustrating an example of an interrupt process performed by the serial communication circuit in response to an interrupt request. It is explanatory drawing which shows the example of a prize ball number table. It is a flowchart which shows a prize ball number addition process. It is a flowchart which shows a prize ball control process. It is a flowchart which shows a prize ball transmission waiting process. It is a flowchart which shows a prize ball number command transmission process. It is a flowchart which shows a prize ball transmission completion waiting process. It is a flowchart which shows a prize ball ACK waiting process. It is a flowchart which shows a prize ball re-transmission process. It is a flowchart which shows a prize ball abnormality detection process. It is a flowchart which shows a main control communication process. It is a block diagram which shows the other structural example of a random number circuit. It is the front view which looked at the slot machine from the front.

Explanation of symbols

1 Pachinko machine 31 Game control board (main board)
37 Dispensing control board 56 CPU
503a 12-bit random number circuit 503b 16-bit random number circuit 505 Serial communication circuit 521 Counter 522 Comparator 523 Counter value permutation change circuit 528 Selector 531 Random value storage circuit 532 Inversion circuit 532A Delay circuit 533 Latch signal generation circuit 560 Game control microcomputer 714 Interrupt control circuit 910 Power supply board

Claims (10)

Provided with variable display means capable of variably displaying a plurality of types of identification information that can identify each of them, and after the predetermined variable display execution condition is established, the identification information can be changed based on the establishment of the variable display start condition A gaming machine that starts display and shifts to a specific gaming state advantageous to the player when the display result of the variable display of identification information becomes a specific display result,
A control microcomputer that includes a control CPU that executes control processing; a random number circuit that generates random numbers; a microcomputer that includes a CPU other than the control CPU; and a serial communication circuit that performs serial communication;
The random number circuit includes:
Numerical value updating means for updating numerical data according to a predetermined order from a predetermined initial value to a predetermined final value in a predetermined range in which the numerical data can be updated based on an input of a predetermined signal;
Random number storage means for storing numerical data updated by the numerical value update means as a random value,
The serial communication circuit includes interrupt request means for generating an interrupt request according to the established interrupt request condition for the control CPU when any of a plurality of interrupt request conditions is established. ,
The control microcomputer is:
Timer interrupt setting means for performing setting for generating a timer interrupt every predetermined time when power supply to the gaming machine is started;
Random number circuit initial setting means for performing initial setting of the random number circuit before the timer interrupt setting is set by the timer interrupt setting means when power supply to the gaming machine is started,
The control CPU is
Interrupt processing execution means for executing interrupt processing based on an interrupt request from the interrupt request means;
Timer interrupt process execution means for executing a timer interrupt process including the control process when the timer interrupt occurs;
Execution condition determination means for determining whether or not the variable display execution condition is satisfied when the timer interrupt occurs;
Random number reading means for reading a random value stored in the random number storage means when the execution condition determination means determines that the execution condition of the variable display is satisfied;
By determining whether or not the random number value read by the random number reading means matches a predetermined determination value, it is determined whether or not the display result of the variable display of the identification information is a specific display result. Display result determining means,
The random number circuit initial setting means for identifying the control microcomputer assigned to each control microcomputer with the predetermined initial value of the numerical data updated by the numerical value update means in the initial setting. can be set based on the microcomputer identification information,
The interrupt request generated by the interrupt request means includes an error time interrupt request generated when an interrupt request condition is satisfied when a communication error occurs in the serial communication circuit,
The interrupt processing execution means includes priority processing means capable of executing an interrupt process based on the error time interrupt request in preference to an interrupt process based on an interrupt request other than the error time interrupt request,
A gaming machine, wherein serial communication is prohibited in an interrupt process based on the error time interrupt request. The control microcomputer incorporates a plurality of random number circuits having different predetermined ranges of numerical data that can be updated by the numerical value updating means,
The random number circuit initial setting means, in the initial setting, sets a usable random number circuit from among a plurality of random number circuits built in the control microcomputer,
The gaming machine according to claim 1, further comprising random number circuit stop means for stopping the function of a random number circuit other than the random number circuit set to be usable by the random number circuit initial setting means. In the initial setting, the random number circuit initial setting means stores a predetermined value within a range of numerical data that can be updated by the numerical value updating means in a numerical maximum value register in which a value as a maximum value of a predetermined range in which numerical data is updated is set. Set the maximum value of
Numeric update means
Set value determining means for determining whether or not the predetermined maximum value set by the random number circuit initial setting means is equal to or less than a predetermined lower limit value;
When the predetermined maximum value set in the numerical value maximum value register is determined to be less than or equal to the predetermined lower limit value by the set value determining means, the numerical value maximum value register can be updated by the numerical value updating means. The gaming machine according to claim 1 or 2, further comprising: a maximum value resetting unit that resets a predetermined value within a range of numerical data. A clock signal generating means for generating a clock signal of a predetermined period and outputting it to a random number circuit;
The numerical value updating means updates the numerical data on the condition that the clock signal has been input a predetermined number of times,
The gaming machine according to any one of claims 1 to 3, wherein the random number circuit initial setting means sets the number of times of input of the clock signal, which is a condition for the numerical value updating means to update the numerical data in the initial setting. The control microcomputer includes numerical operation means for calculating a predetermined initial value of numerical data set by the random number circuit initial setting means using the microcomputer identification information,
The gaming machine according to any one of claims 1 to 4, wherein the random number circuit initial setting means sets an initial value based on a value calculated by calculation by the numerical value calculation means. The random number circuit initial setting means sets whether or not to change the predetermined initial value set by the random number circuit initial setting means when the numerical data is updated to a predetermined final value by the numerical value updating means in the initial setting. And
A random number circuit, when the numerical data is updated to the predetermined final value by the numerical value updating means, a notification signal output means for outputting a notification signal indicating that the numerical data is updated to the predetermined final value;
An initial value changing means for changing the value of the predetermined initial value when the initial value is set to be changed by the random number circuit initial setting means based on the output of the notification signal. The gaming machine according to any one of claims 1 to 5. A winning detection means for detecting that a game medium has won a winning area in the gaming area, and that a variable display execution condition is satisfied, and outputting a winning detection signal;
The random number circuit outputs a latch signal for instructing the random number storage means to store numerical data to be updated by the numerical value updating means based on the input of the winning detection signal from the winning detection means. Including means,
The game according to any one of claims 1 to 6, wherein the latch signal output means outputs the latch signal on condition that the winning detection signal is continuously input from the winning detection means for a predetermined period. Machine. A winning detection means for detecting that a game medium has won a winning area in the gaming area, and that a variable display execution condition is satisfied, and outputting a winning detection signal;
The random number circuit outputs a latch signal for instructing the random number storage means to store numerical data to be updated by the numerical value updating means based on the input of the winning detection signal from the winning detection means. Including means,
The latch signal output means outputs the latch signal on condition that the winning detection signal is continuously input from the winning detection means for a predetermined period,
The random number reading means stores the random number storage means on condition that a winning detection signal is input from the winning detection means while the timer interruption process is executed a predetermined number of times by the timer interrupt processing execution means. Read the random value
The gaming machine according to claim 1, wherein the predetermined period is shorter than a period in which the predetermined number of times of the timer interrupt process are executed. The random number circuit initial setting means includes numerical value order setting means for setting whether or not to change the arrangement order of values from a predetermined initial value to a predetermined final value of the numerical data updated by the numerical value updating means in the initial setting. Including
The random number circuit
A notification signal output means for outputting a notification signal indicating that the numerical data is updated to the predetermined final value when the numerical data is updated to the predetermined final value by the numerical value updating means;
Based on the output of the notification signal, the random number circuit initial setting means is configured to change the arrangement order of the numerical data from the predetermined initial value to the predetermined final value, The gaming machine according to any one of claims 1 to 8, further comprising: numerical value order changing means for changing an arrangement order of the numerical data updated by the numerical value updating means from the predetermined initial value to the predetermined final value. The control microcomputer is a serial communication circuit initial setting means for performing initial setting of the serial communication circuit before the timer interrupt setting means is set by the timer interrupt setting means when power supply to the gaming machine is started. Including
The interrupt request generated by the interrupt request means includes a reception interrupt request generated when the serial communication circuit receives data from a microcomputer incorporating a CPU other than the control CPU.
The serial communication circuit initial setting means changes the priority order for changing the priority order of interrupt processing executed by the priority processing means before the timer interrupt is set by the timer interrupt setting means. Means,
The priority processing means executes the interrupt processing based on the reception interrupt request with priority over the interrupt processing based on the error time interrupt request by the priority changing means. The interrupt process based on the reception interrupt request is executed in preference to the interrupt process based on the error interrupt request. Game machines.

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