JP4511475B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine in which a player can play a predetermined game using a game medium, and pays out a prize game medium as a prize based on the winning of the game medium in a prize area in the game area.

  As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a prize area such as a prize opening provided in the game area, a predetermined number of prize balls are paid out to the player. There is something to be done.

  Game progress in the gaming machine is controlled by game control means such as a microcomputer. When the payout control means for controlling the prize ball payout is mounted on a payout control board different from the game control board (main board) on which the game control means is mounted, the progress of the game is mounted on the main board. Therefore, the number of winning balls based on the winning is determined by the gaming control means, and a control command indicating the number of winning balls is transmitted to the payout control board. Then, the payout control means performs a process of paying out the number of prize balls based on the winning based on the control command from the game control means.

  In addition, there is a technique in which a detection signal of the all winning counting switch (a detection signal of the switch of the discharge processing device) is input to the payout control means, and the payout control means determines whether the number of winning balls is excessive or insufficient (for example, Patent Literature) 1). In the gaming machine described in Patent Document 1, a detection signal of a winning detection switch for detecting a winning of a game ball at each winning opening is input to a game control board, and the number of winning balls based on the winning is determined by the game control means. A control command indicating the number of prize balls is transmitted to the payout control board. Also, the payout control means determines whether the number of winning balls is excessive or insufficient based on the value of the winning number counter. Then, the payout control means notifies the determination result of the excess or deficiency of the number of prize balls by performing a warning process.

JP 2002-35325 A (paragraphs 109-118, FIGS. 13-14)

  However, in the gaming machine described in Patent Document 1, the detection signal of each winning detection switch is input to the game control board and the game control means manages the number of winning balls, while the payout control board includes all winning count switches. The payout control means manages the number of prize balls. For this reason, there is a risk that the number of prize balls managed by the game control means and the number of prize balls managed by the payout control means may be shifted.

  For example, the game control means manages the number of prize balls using a total prize ball buffer that stores the total number of prize balls. When paying out, the game control means subtracts the payout number detected by the payout count switch from the total prize ball number stored in the total prize ball number buffer. In addition, when the game control means detects a winning, it reads the total number of winning balls from the total winning ball number buffer, and adds the number of winning balls detected by each winning detection switch to the read total number of winning balls. Then, the game control means again writes the total number of winning balls after the addition to the total winning ball number buffer. In this case, if payout is performed between the time of reading the total number of winning balls from the total number of winning balls buffer and the time of writing again, the game control means executes the subtraction processing based on the payout and then adds the total number of winning balls The number (the total number of winning balls not reflecting the subtraction) is overwritten in the total winning ball buffer. For this reason, the amount of subtraction due to payout cannot be correctly reflected in the total number of winning balls, and there is a risk that the number of winning balls managed by the game control means and the number of winning balls managed by the payout control means may be misaligned. .

  Therefore, the present invention provides a game control means in a gaming machine in which a game control means and a payout control means are provided separately, and a prize game medium is paid out as a prize based on the winning of a game medium in a prize area in the game area. It is an object of the present invention to prevent a deviation between the number of prize balls managed by the player and the number of prize balls managed by the payout control means.

In the gaming machine according to the present invention, a player can play a predetermined game using a game medium (for example, a game ball), and a winning area in the gaming area (for example, a variable winning ball device 15, a winning opening 29, 30, 33, 39, a grand prize opening), and a game machine that pays out a prize game medium as a prize based on the fact that the game medium has been won. Is a game that controls the progress of the game by receiving a winning detection means (for example, start port switch 14a, count switch 23, winning port switches 29a, 30a, 33a, 39a) and a winning detection signal from the winning detection means. Control means (for example, a game control microcomputer 560), payout means (for example, a ball payout device 97) for paying out premium game media, and a payout means A payout detecting means (for example, a payout number count switch 301) for detecting that the game medium has been paid out and outputting a payout detection signal, and a payout control means for controlling the payout means (eg, a payout control microcomputer 370). And a game control means that generates a main process execution means that repeatedly executes a predetermined main process (for example, a portion that repeatedly executes the processes of steps S17 to S19h in the game control microcomputer 560), and occurs every predetermined time. timer interruption setting means for setting a timer interrupt (for example, in the gaming control microcomputer 560 portions for performing the process of step S16) and, when the timer interrupt occurs, interrupts the execution of the main processing Timer interrupt processing execution means (for example, a game control microphone) The portion of the computer 560 that executes the processing of steps S20 to S27) and the number-of-payout data that can specify the number of prize game media to be paid out according to the input of the winning detection signal during the execution of the timer interrupt processing ( For example, a payout number registering unit (for example, a part that executes the process of step S2124 in the game control microcomputer 560) that stores a payout number storage unit (for example, a prize ball command output counter) and a main process During execution, based on the number-of-payout data stored in the number-of-payout storage means, a number-of-payout command (for example, a prize ball number command “03”, “03” shown in FIG. 53) can be specified. 0A "," 0F ") to the payout control means (for example, in the game control microcomputer 560) A portion for executing the processing of step S1254), and the total number of payouts (for example, the total number of prize balls) indicating the total number of the prize game media to be paid out but not paid out by the payout means Total unpaid number storage means for storing (for example, total winning ball number storage buffer) and reading means for reading the total unpaid number from the total unpaid number storage means during execution of the main processing (for example, a game control microcomputer) A portion for executing the processing of step S1282 at 560) and a payout number adding means for adding the number of premium game media indicated in the payout number command transmitted by the payout number transmitting means to the total number of payouts read by the reading means (For example, the part of the game control microcomputer 560 that executes the process of step S1283) The number of output, the payout number writing means for writing the total non-payout storage means (e.g., portions for performing the processing of step S1284 in the gaming control microcomputer 560), the timer before the reading means reads the total non-payout Interrupt prohibiting means for prohibiting execution of interrupt processing (for example, a part for executing the process of step S1281 in the game control microcomputer 560) and payout number writing means for calculating the total unpaid number. , Including an interrupt permitting means for permitting execution of the timer interrupt process (for example, a part for executing the process of step S1285 in the game control microcomputer 560), during execution of the timer interrupt process, Based on the payout detection signal, the total unpaid number storage means stores the number of premium game media paid out by the payout means. Total unpaid number subtraction means for subtracting from the total unpaid number (for example, the part that executes the process of step S2131 in the game control microcomputer 560), and the number of prize game media indicated in the number-of-payments command by the payout number addition means Is added to the total unpaid number, the number-of-payout determination means for determining whether or not the total unpaid number to which the number of premium game media indicated in the payout number command is added is within a predetermined range (for example, A part for executing the processing of step S1305 in the game control microcomputer 560.

  When the game control means determines that the payout number determination means does not fall within the predetermined range, the game control means indicates an abnormality occurrence command (for example, excessive prize balls shown in FIG. 53) indicating that an abnormality has occurred in the payout means. An abnormal command “E1” and an award ball underabnormality command “E2”) are transmitted to the payout control unit, for example, in a payout abnormality occurrence command transmitting means (for example, in the gaming control microcomputer 560, the award ball excessive abnormality command “E1” ”To the payout control board 37, and a part in the game control microcomputer 560 that sends the award ball under-abnormality command“ E2 ”to the payout control board 37 in step S 1305 b), and the payout control means is a game control means. Payout of premium game media by payout means based on abnormality occurrence command received from A payout side abnormality notifying means for notifying that an abnormality has occurred (for example, in the payout control microcomputer 370, based on the fact that the excessive ball error error bit is set in step S829, the error indication LED 374 is set to “ 9 ”and a portion for displaying“ A ”on the error display LED 374 in step S759 based on the setting of the award ball under / abnormal error bit in step S832 in the payout control microcomputer 370). It may be configured as follows.

The gaming machine controls production electrical parts (for example, the speaker 27, the lamps 25, 28a, 28b, and 28c, and the variable display device 9), and performs production control means (for example, for sound / lamp control). If the game control means determines that it is not within the predetermined range by the payout number determination means, it indicates that an abnormality has occurred in the payout of the prize game medium by the payout means. An abnormality occurrence command sending means for sending an abnormality occurrence command to the effect control means (for example, a part for sending an excessive prize ball abnormality command to the sound / lamp control board 80b in step S1306 in the game control microcomputer 560, In step S1305b in the control microcomputer 560, the number of prize balls is too small. The effect control means notifies the occurrence of an abnormality in the payout of the prize game medium by the payout means based on the abnormality occurrence command received from the game control means. Effect-side abnormality notification means (for example, a part of the sound / lamp control microcomputer 100b that is notified by using the speaker 27 or each of the lamps 25, 28a, 28b, 28c in step S790, a variable display device in the symbol control microcomputer 100a) 9 may be configured to be included.

  The number-of-payout determination means pays out more game media than the number of prize game media to be paid out based on the total number of payout game media added by the number of prize game media indicated by the number-of-payout command by the number-of-payout addition means. Excessive payout abnormality determining means for determining whether or not an abnormal excessive payout abnormality has occurred (for example, based on determining that the total number of winning balls is smaller than −499 in step S1305 in the gaming control microcomputer 560). And the number of premium game media indicated by the number-of-payout command added by the number-of-payout command is added to the predetermined number. A payout underabnormality judging means (for example, a game controlling microcomputer) for judging whether or not an underpayment abnormality that is an abnormality in a state exceeding the payout underdetermination value has occurred. The portion 560 determines that the total number of winning balls is determined to be greater than 2000 in step S1305a), and the payout abnormality occurrence command transmission means When it is determined by the determining means that an excessive payout abnormality has occurred, an excessive payout abnormality command (for example, an excessive prize ball abnormality command “E1” shown in FIG. 53) indicating that an excessive payout abnormality has occurred is sent to the payout control means. An excessive payout abnormality command transmission means to be transmitted (for example, a portion of the game control microcomputer 560 that transmits an award ball excess abnormality command “E1” to the payout control board 37 in step S1306) and an underpayment abnormality determination means. When it is determined that an abnormality has occurred, an under-payout abnormality command (for example, an under-payout abnormality command has occurred) 53, a prize-ball under-abnormality command “E2”) is transmitted to the payout control means, for example, in a game-control microcomputer 560, a prize-ball under-abnormality command “E2” in step S1305b. The payout side abnormality notifying means for notifying that an excessive payout abnormality has occurred based on the payout excess abnormality command received from the game control means. (For example, in the payout control microcomputer 370, based on the setting of the excessive excessive ball error error bit set in step S829, the portion displaying “9” on the error display LED 374 in step S759) and the game control means An underdelivery abnormality has occurred based on the received underdelivery abnormality command Is displayed on the error display LED 374 in step S759 based on the fact that the payout control microcomputer 370 sets the award ball underabnormality error bit in step S832. Part).

  The number-of-payout determination means pays out more game media than the number of prize game media to be paid out based on the total number of payout game media added by the number of prize game media indicated by the number-of-payout command by the number-of-payout addition means. Excessive payout abnormality determining means for determining whether or not an abnormal excessive payout abnormality has occurred (for example, based on determining that the total number of winning balls is smaller than −499 in step S1305 in the gaming control microcomputer 560). And the number of premium game media indicated by the number-of-payout command added by the number-of-payout command is added to the predetermined number. A payout underabnormality judging means (for example, a game controlling microcomputer) for judging whether or not an underpayment abnormality that is an abnormality in a state exceeding the payout underdetermination value has occurred. The portion 560 determines that the total number of winning balls is determined to be greater than 2000 in step S1305a), and the effect abnormality occurrence command transmitting means transmits the excessive payout abnormality. When it is determined by the determining means that an excessive payout abnormality has occurred, an excessive payout abnormality command transmission means for transmitting an excessive payout abnormality command indicating that an excessive payout abnormality has occurred to the effect control means (for example, a game control micro If the computer 560 determines that an excessive payout abnormality has occurred in step S1306, the portion that transmits a prize ball excessive abnormality command to the sound / lamp control board 80b) and the excessive payout abnormality determination means, that an excessive payout abnormality has occurred. An under-performance abnormal command transmission means for transmitting a payout under-abnormal command to the effect control means ( For example, the game control microcomputer 560 includes a portion that transmits a prize ball under-abnormality command to the sound / lamp control board 80b in step S1305b), and the production-side abnormality notification unit receives the excessive payout abnormality command received from the game control unit Based on the above, a production-side excessive notification means for notifying that an excessive payout abnormality has occurred (for example, using the speaker 27 and the lamps 25, 28a, 28b, 28c in step S790 in the sound / lamp control microcomputer 100b) 99, a portion for displaying the screen of FIG. 99 (A) using the variable display device 9 in the symbol control microcomputer 100a) and a payout underabnormality command received from the game control means. Production side under-notification means (for example, sound / run 99B using the speaker 27 and the lamps 25, 28a, 28b, and 28c in step S790, and using the variable display device 9 in the symbol control microcomputer 100a. May be included.

  When it is determined by the payout number determination means that an abnormality has occurred in the payout of the prize game medium by the payout number determination means, the game control means prohibits transmission of a payout number command by the payout number transmission means (for example, The game control microcomputer 560 is configured to include a portion for ending the processing based on the fact that the excessive ball error error flag or the excessive ball error error flag is set in steps S1241, S1261, S1271, and S1291). May be.

  The payout control means is a payout detection signal input means that inputs a payout detection signal from the payout detection means (for example, the payout control microcomputer 370 from the input port 1 (I / O port 372f shown in FIG. 5)). And a payout detection signal output means for outputting the payout detection signal input by the payout detection signal input means to the game control means (for example, in the payout control microcomputer 370, the output port in step S603a). 0 (the portion that outputs the detection signal of the payout number count switch 301 from the I / O port 372a shown in FIG. 5) and the number of prize game media paid out by the payout means according to the input of the payout detection signal. External output means for outputting a signal indicating to the outside (for example, a microcomputer for payout control) The total unpaid number subtraction means is a prize game paid out by the payout means in response to an input of a payout detection signal input from the payout control means. The number of media is subtracted from the total unpaid number stored in the total unpaid number storage means (for example, in the game control microcomputer 560, the payout number count switch 301 input via the payout control microcomputer 370). The process of step S2131 may be executed based on the detection signal).

In the invention of claim 1, wherein, when the payout of prize game medium is performed by the dispensing means, the timer interrupt process, subtracts the number of paid out prize game medium from the total non-payout. Further, in the main processing, when adding the number of prize game media shown in payout command on the total non-payout, reading the total non-payout from the total non-payout storage means, again the total unpaid coin Total The execution of the timer interrupt process is prohibited until the unpaid number storage means is written. Therefore, between the total unpaid coin number memory means to write again reads the total non-payout, be the number of paid out prize game media to not execute the process of subtracting from the total non-payout This can prevent a situation in which the game control means cannot grasp the number of premium game media paid out. Therefore, it is possible to prevent a deviation between the number of prize balls managed by the game control means and the number of prize balls managed by the payout control means.

  In the invention according to claim 2, an abnormality occurrence command indicating that an abnormality has occurred in payout of prize game media by the game control means is transmitted to the payout control means, and the payout control means notifies based on the received abnormality occurrence command. Therefore, it is possible to notify an error state of payout of the prize game medium.

  According to the third aspect of the present invention, an abnormality occurrence command indicating that an abnormality has occurred in payout of prize game media is transmitted to the effect control means by the game control means, and the effect control means notifies based on the received abnormality occurrence command. Therefore, it is possible to notify the error state of the payout of the prize game medium.

  In the invention according to claim 4, it is determined by distinguishing whether the payout abnormality of the prize game medium is an excessive payout abnormality or an excessive payout abnormality. The payout control means is in a state in which more game media have been paid out than the number of prize game media to be paid out, or the number of prize game media to be paid out. By discriminating whether or not the game medium has been paid out less, it is possible to notify the payout game medium payout error status.

  In the invention according to claim 5, it is determined by distinguishing whether an abnormality in payout of the prize game medium is an excessive payout abnormality or an excessive payout abnormality. The effect control means is in a state where more game media have been paid out than the number of prize game media to be paid out, or the number of prize game media to be paid out. By discriminating whether or not the game medium has been paid out less, it is possible to notify the payout game medium payout error status.

  In the invention described in claim 6, since it is configured to prohibit the transmission of the payout number command when it is detected that an abnormality has occurred in the payout of the prize game medium, the prize game medium is illegally paid out. Can be prevented. In particular, since it is possible to reliably prevent an excessive payout state in which more game media are paid out than the number of premium game media to be paid out, it is possible to prevent fraud in which a large amount of premium game media is paid out.

  In the invention of claim 7, the payout detection signal from the payout detection means is input to the payout control means, and the payout detection signal input to the payout control means is further input to the game control means. There is no need to provide wiring for outputting the payout detection signal from the payout detecting means to both the game control means and the payout control means. Therefore, the wiring for outputting the payout detection signal from the payout detection means can be reduced.

Embodiment 1 FIG.
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
First, the overall configuration of a pachinko gaming machine that is an example of a gaming machine will be described. FIG. 1 is a front view of a pachinko gaming machine as viewed from the front, and FIG. 2 is a front view showing the front of the game board. In the following embodiments, a pachinko gaming machine will be described as an example. However, the gaming machine according to the present invention is not limited to a pachinko gaming machine, and can be applied to other gaming machines such as a slot machine.

  The pachinko gaming machine 1 includes an outer frame (not shown) formed in a vertically long rectangular shape, and a game frame attached to the inside of the outer frame so as to be openable and closable. Further, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape that is provided in the game frame so as to be opened and closed. The game frame includes a front frame (not shown) installed to be openable and closable with respect to the outer frame, a mechanism plate to which mechanism parts and the like are attached, and various parts attached to them (excluding a game board described later). Is a structure including

  As shown in FIG. 1, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2 is a hitting ball supply tray (upper plate) 3. Under the hitting ball supply tray 3, an extra ball receiving tray 4 for storing game balls that cannot be accommodated in the hit ball supply tray 3 and a hitting operation handle (operation knob) 5 for launching the game balls are provided. A game board 6 is detachably attached to the back surface of the glass door frame 2. The game board 6 is a structure including a plate-like body constituting the game board 6 and various components attached to the plate-like body. A game area 7 is formed on the front surface of the game board 6.

  Near the center of the game area 7, there is provided a variable display device (decorative symbol display device) 9 including a plurality of variable display portions each variably displaying an effect decorative symbol. The variable display device 9 has, for example, three variable display portions (symbol display areas) of “left”, “middle”, and “right”. The variable display device 9 performs variable display of a decorative symbol as a symbol for decoration (production) during the variable symbol display period of the special symbol by the special symbol indicator 8. The variable display device 9 that performs variable display of decorative symbols is controlled by a symbol control microcomputer mounted on the symbol control board.

  At the bottom of the variable display device 9, four special symbol hold memory indicators 18 for displaying the number of valid winning balls that have entered the start winning opening 14, that is, the number of hold memories (also referred to as start memory or start prize memory), are provided. ing. The special symbol hold memory display 18 displays up to four hold memory numbers in the order of winning. The special symbol hold storage display 18 increases the number of LEDs in the lit state by 1 each time there is a start winning in the start winning opening 14. Then, each time the special symbol display 8 starts variable display, the special symbol hold storage indicator 18 reduces the number of LEDs in the lit state by 1 (that is, turns off one LED). Specifically, the special symbol hold storage display 18 shifts the lighting state each time variable display is started on the special symbol display 8. In this example, the upper limit number (up to 4) is provided for the number of starting memories by winning to the start winning opening 14, but the upper limit number may be four or more.

  A special symbol display (special symbol display device) 8 that variably displays a special symbol as identification information is provided on the variable display device 9. In this embodiment, the special symbol display 8 is realized by a simple and small display (for example, 7 segment LED) capable of variably displaying numbers 0 to 9, for example. The special symbol display 8 may be configured to variably display a larger number of numbers such as 0 to 99 in order to make it difficult for the player to grasp a specific stop symbol. In addition, the variable display device 9 performs variable display of a decorative symbol as a symbol for decoration (for production) during the variable symbol display period of the special symbol by the special symbol indicator 8.

  Below the variable display device 9 is provided a variable winning ball device 15 that forms a start winning opening 14. The winning ball that has entered the start winning opening 14 is guided to the back of the game board 6 and detected by the start opening switch 14a. The variable winning ball device 15 is opened by a solenoid 16.

  Below the variable winning ball apparatus 15, a special variable winning ball apparatus 20 using an opening / closing plate that is controlled to be opened by a solenoid 21 in a specific gaming state (big hit state) is provided. The special variable winning ball apparatus 20 is a means for opening and closing the big winning opening. Of the winning balls that are won in the special variable winning ball apparatus 20 and guided to the back of the game board 6, the winning ball that has entered one (V winning area: special area) is detected by the V winning switch 22 and then counted by the count switch 23. The game ball that has been detected and entered the other region is detected by the count switch 23 as it is. On the back of the game board 6, a solenoid 21A for switching the route in the special winning opening is also provided.

  When the game ball passes through the gate 32 and is detected by the gate switch 32a, variable display of the normal symbol display 10 is started. In this embodiment, variable display is performed by alternately lighting left and right lamps (designs can be visually recognized when lit). For example, if the left lamp is lit at the end of variable display, it is a hit. When the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined number of times. In the vicinity of the normal symbol display 10, a normal symbol start memory display 41 having a display unit with four LEDs for displaying the number of winning balls that have passed through the gate 32 is provided. Each time there is a game ball passing through the gate 32, the normal symbol start memory display 41 increases the number of LEDs to be turned on by one. Each time the variable display on the normal symbol display 10 is started, the number of LEDs to be lit is reduced by one.

  The game board 6 is provided with a plurality of winning holes 29, 30, 33, 39, and winning of game balls to the winning holes 29, 30, 33, 39 is performed by winning hole switches 29a, 30a, 33a, 39a, respectively. Detected. Each winning opening 29, 30, 33, 39 constitutes a winning area provided in the game board 6 as an area for accepting game media and allowing winning. The start winning opening 14 and the big winning opening also constitute a winning area that accepts game media and allows winning. Around the left and right of the game area 7, there are provided decorative lamps 25 blinking and displayed during the game, and at the lower part there is an outlet 26 for absorbing a game ball that has not won a prize. Two speakers 27 that emit sound effects are provided on the left and right upper portions outside the game area 7. On the outer periphery of the game area 7, a top frame lamp 28a, a left frame lamp 28b, and a right frame lamp 28c are provided. Further, a decoration LED is installed around each structure (such as a big prize opening) in the game area 7. The top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, and the decoration LED are examples of a decorative light emitter provided in the gaming machine.

  In this example, a prize ball lamp 51 that is lit during award ball payout is provided in the vicinity of the left frame lamp 28b, and a ball break lamp 52 that is lit when the supply ball is cut in the vicinity of the top frame lamp 28a. Is provided. Further, a prepaid card unit (hereinafter referred to as “card unit”) 50 that enables lending a ball by inserting a prepaid card is installed adjacent to the pachinko gaming machine 1.

  The card unit 50 includes, for example, a usable display lamp that indicates whether or not the card unit 50 is in a usable state, a connection table direction indicator that indicates which side of the pachinko gaming machine 1 corresponds to the card unit, and a card unit. When checking the card insertion indicator lamp indicating that a card is inserted in the card, the card insertion slot into which the card as a recording medium is inserted, and the card reader / writer mechanism provided on the back of the card insertion slot A card unit lock for releasing the card unit is provided.

  A game ball launched from the ball striking device by the player's operation enters the game area 7 through the hit ball rail, and then descends the game area 7. When the game ball enters the start winning opening 14 and is detected by the start opening switch 14a, the special symbol on the special symbol display 8 starts variable display (variation) if the variable display of the symbol can be started. If the variable display of the symbol cannot be started, the number of reserved memories is increased by one.

  The variable display of the special symbol on the special symbol indicator 8 stops when a certain time has passed. If the special symbol (stop symbol) at the time of stoppage is a jackpot symbol (specific display result), the game shifts to a jackpot gaming state. That is, the special variable winning ball apparatus 20 is released until a predetermined time elapses or a predetermined number (for example, 10) of gaming balls wins. When the game ball is won in the V winning area while the special variable winning ball apparatus 20 is opened and is detected by the V winning switch 22, a continuation right is generated and the special variable winning ball apparatus 20 is opened again. The generation of the continuation right is allowed a predetermined number of times (for example, 15 rounds). Further, without providing the V winning area, the special variable winning ball apparatus 20 may be allowed to be released up to the last round of the determined number of rounds (for example, up to 15 rounds).

  When the special symbol on the special symbol display 8 at the time of stoppage is a jackpot symbol (probability variation symbol) with a probability variation, the probability of the next jackpot increases. That is, it becomes a more advantageous state for the player in the probability variation state.

  When the game ball passes through the gate 32, the normal symbol display unit 10 enters a state in which the normal symbol is variably displayed. Further, when the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined time.

  Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. FIG. 3 is a rear view of the gaming machine as seen from the back side.

  As shown in FIG. 3, on the back side of the gaming machine, a variable display control unit 49 including a symbol control board 80a on which a symbol control microcomputer for controlling the variable display device 9 is mounted, a game control microcomputer and the like are mounted. A game control board (main board) 31 is installed. In addition, a payout control board 37 on which a payout control microcomputer for performing ball payout control is mounted is installed. The variable display control unit controls lighting of the various decorative LEDs, the decorative lamp 25, the top frame lamp 28a, the left frame lamp 28b, and the right frame lamp 28c provided on the frame side together with the symbol control board 80a. A sound / lamp control board on which a sound / lamp control microcomputer for controlling sound generation from the sound is mounted.

  Further, a power supply substrate 910 and a touch sensor substrate 91 on which a power supply circuit for generating DC30V, DC21V, DC12V, and DC5V is mounted are provided. Although most of the power supply substrate 910 overlaps with the main substrate 31, there is an exposed portion that is exposed so as to be visible from the outside without overlapping the main substrate 31. This exposed portion is supplied with the main board 31 and each control board (sound / lamp control board, symbol control board 80a and payout control board 37) in the gaming machine 1 and each electrical component (electric power supplied to the gaming machine). A power switch is provided as a power supply permission means for executing or cutting off the power supply to the component operating by the operation. Furthermore, a replaceable fuse is provided inside the power switch in the exposed portion (inside the substrate).

  Each control board is equipped with control means including a control microcomputer. The control means is an electrical component (game device: ball payout device 97, variable display device 9, light emission from a lamp, LED, etc.) provided in the gaming machine according to a command signal (control signal) as a command from the game control means or the like. Body, speaker 27, etc.). Hereinafter, the main board 31 may be included in the control board for explanation. In that case, the control means mounted on the control board refers to each of the game control means and the means for controlling the electrical components provided in the gaming machine in accordance with a command signal from the game control means or the like. A substrate on which a microcomputer other than the main substrate 31 is mounted may be referred to as a sub-substrate.

  On the back side of the gaming machine, a terminal board 160 provided with terminals for outputting various information to the outside of the gaming machine is installed above. The terminal board 160 includes at least a ball break terminal for introducing the output of the ball break detection switch 167 and outputting it externally, a prize ball terminal and a ball for outputting prize ball information (prize ball number signal) to the outside. A ball lending terminal for externally outputting lending information (ball lending number signal) is provided. In addition, an information terminal board (information output board) 36 provided with terminals for outputting various information from the main board 31 to the outside of the gaming machine is installed near the center.

  The game balls stored in the storage tank 38 pass through the guide rail 39 and reach the ball payout device covered with the payout case 40A through the curve rod. A ball break switch 187 as a game medium break detection means is provided on the upper part of the ball payout device. When the ball break switch 187 detects a ball break, the dispensing operation of the ball dispensing device stops. The ball break switch 187 is a switch for detecting the presence or absence of a game ball in the game ball passage, but the ball break detection switch 167 for detecting the shortage of supply balls in the storage tank 38 is also an upstream portion (storage tank 38). In the vicinity of the head). When the ball break detection switch 167 detects the shortage of game balls, the game machine is replenished to the game machine from the supply mechanism provided on the gaming machine installation island.

  When a large number of game balls as prizes based on winning a prize and game balls based on a ball lending request are paid out and the hitting ball supply tray 3 is full, the game balls are guided to the surplus ball receiving tray 4 through the surplus ball passage. Further, when the game ball is paid out, a sensing lever (not shown) presses a full tank switch (not shown) as the storage state detection means, and the full tank switch as the storage state detection means is turned on. In this state, the rotation of the payout motor in the ball payout device is stopped, the operation of the ball payout device is stopped, and the driving of the ball hitting device is also stopped.

  FIG. 4 is a block diagram showing an example of the circuit configuration of the main board (game control board) 31. FIG. 4 also shows a payout control board 37, a sound / lamp control board 80b, a symbol control board 80a, and the like. A game control microcomputer (corresponding to game control means) 560 for controlling the pachinko gaming machine 1 according to a program is mounted on the main board 31. The game control microcomputer 560 includes a ROM 54 for storing a game control (game progress control) program and the like, a RAM 55 as storage means used as a work memory, a CPU 56 for performing control operations in accordance with the program, and an I / O port unit 57. including. In this embodiment, the ROM 54 and the RAM 55 are built in the game control microcomputer 560. That is, the game control microcomputer 560 is a one-chip microcomputer. The one-chip microcomputer only needs to include at least the RAM 55, and the ROM 54 may be external or internal. The I / O port unit 57 may be externally attached.

  In the game control microcomputer 560, the CPU 56 executes control in accordance with the program stored in the ROM 54, so that the game control microcomputer 560 (or CPU 56) executes (or performs processing) hereinafter. Specifically, the CPU 56 executes control according to a program. The same applies to microcomputers mounted on substrates other than the main substrate 31.

  Further, an input driver circuit 58 for supplying the basic circuit 53 with detection signals from the gate switch 32a, the start port switch 14a, the count switch 23, the V winning switch 22 and the winning port switches 29a, 30a, 33a and 39a is also provided on the main board 31. An output circuit 59 that drives the solenoid 16 that opens and closes the variable winning ball device 15, the solenoid 21 that opens and closes the special variable winning ball device, and the solenoid 21 A for switching the path in the special winning opening according to a command from the basic circuit 53. Is also mounted on the main board 31, and a system reset circuit (not shown) for resetting the game control microcomputer 560 when the power is turned on, and an information output signal such as jackpot information indicating the occurrence of a jackpot gaming state are output to a hall computer, etc. Information output circuit (not shown) ) It has also been installed in the main board 31.

  In this embodiment, the sound / lamp control means (configured by a sound / lamp control microcomputer) mounted on the sound / lamp control board 80 b is connected to the game control microcomputer 560 via the relay board 77. The effect control command from is received and transferred to the symbol control board 80a. Then, the symbol control means (comprising a symbol control microcomputer) mounted on the symbol control board 80a receives the effect control command from the sound / lamp control means, and variably displays the decorative symbol. 9 display control is performed.

  FIG. 5 is a block diagram showing components related to payout, such as the payout control board 37 and the ball payout device 97. As shown in FIG. 5, a payout control microcomputer 370 including a payout control CPU 371 is mounted on the payout control board 37. In this embodiment, the payout control microcomputer 370 is a one-chip microcomputer and incorporates at least a RAM. The payout control microcomputer 370, the RAM (not shown), the ROM (not shown) storing the payout control program, the I / O port, and the like constitute the payout control means. That is, the payout control means is realized by a payout control CPU 371, a payout control microcomputer 370 having a RAM and a ROM, and an I / O port. The I / O port may be built in the payout control microcomputer 370. At least a part of the RAM in the payout control microcomputer 370 is backed up by a backup power source mounted on the power supply board 910. In this embodiment, it is assumed that all RAM areas are backed up. Therefore, even when power is not supplied to the gaming machine, the storage contents of the RAM are preserved for a predetermined period (until the backup power supply cannot be supplied because the capacitor as the backup power supply is discharged).

  Detection signals from the ball break switch 187, the full switch 48, and the payout count switch 301 are input to the I / O port 372 f of the payout control board 37 via the relay board 72. In this embodiment, the detection signal from the payout number count switch 301 is input to the payout control microcomputer 370 and then output to the main board 31 via the I / O port 372a and the output circuit 373B. .

  A detection signal from the payout motor position sensor 295 is input to the I / O port 372e of the payout control board 37 via the relay board 72. The payout motor position sensor 295 is a sensor comprising a light emitting element (LED) and a light receiving element for detecting the rotational position of the payout motor 289, and is used for detecting that the game ball is clogged, that is, so-called ball biting. . In the payout control microcomputer 370 mounted on the payout control board 37, the detection signal from the ball break switch 187 indicates that the ball is out of ball, or the detection signal from the full tank switch 48 indicates that the ball is full. Then, the ball payout process is stopped.

  Further, when the detection signal from the full tank switch 48 indicates a full state, the payout control microcomputer 370 has a low level with respect to the launch board 90 in order to stop the ball launch from the hitting ball launcher. A full tank signal is output. A launch motor signal output from the AND circuit 91 of the launch board 90 to the launch motor 94 is transmitted from the launch board 90 to the launch motor 94. The full signal from the payout control microcomputer 370 is input to one input side of the AND circuit 91 mounted on the launch board 90, and the drive signal from the drive signal generation circuit 92 is input to the input side of the AND circuit 91. Input to the other. Then, the firing motor signal of the AND circuit 91 is input to the firing motor 94. That is, while the payout control microcomputer 370 is outputting the full tank signal, the output of the firing motor signal to the firing motor 94 is stopped.

  When a game ball is won at the winning opening, a prize ball number command indicating the number of prize balls to be paid out is issued as a payout command signal from the serial communication circuit 505 (see FIGS. 7 and 54) of the game control microcomputer 560. Output (send). The award ball number command is composed of 8-bit data (binary 8-digit data) and is output by asynchronous serial communication.

  The award ball number command is input to the serial communication circuit 380 (see FIG. 54). When a prize ball number command is input via the serial communication circuit 380, the payout control microcomputer 370 performs control for driving the ball payout device 97 to pay out the number of game balls indicated by the prize ball number command. A connection confirmation signal indicating that the main board 31 is connected is also output from the output circuit 67 of the main board 31. The prize ball number command corresponds to a payout command signal for designating the payout number.

  Also, a power-off signal indicating that the power supply voltage has dropped below a predetermined value and a clear signal indicating that a clear switch for clearing the contents of the RAM has been operated are supplied to the input port 372g from the power supply board 910. Entered. The power-off signal and the clear signal are output to the main board 31 via the output circuit 373B. Then, in the main board 31, the data is input to the game control microcomputer 560 via the input circuit 68 and the I / O port 57.

  The payout control microcomputer 370 receives, via the output port 372b, a prize ball information signal indicating the number of prize balls to be paid and a ball lending number signal indicating the number of balls to be lent. Output to 160). A driver circuit is provided outside the output port 372b, but is not shown in FIG.

  Also, the payout control microcomputer 370 outputs an error signal to the error display LED 374 using a 7-segment LED via the output port 372c. Further, a signal for instructing turning on / off is output to the winning ball LED 51 and the ball running out LED 52 via the output port 372b. A detection signal from an error release switch 375 for releasing the error state is input to the input port 372f of the payout control board 37. The error cancel switch 375 is used to cancel the error state by software reset.

  Further, a drive signal from the payout control microcomputer 370 to the payout motor 289 is transmitted to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the output port 372a and the relay board 72. Although a driver circuit (motor drive circuit) is installed outside the output port 372a, the description is omitted in FIG.

  A card unit control microcomputer is mounted on the card unit 50 installed adjacent to the gaming machine. In addition, the card unit 50 is provided with a usable display lamp, a connecting table direction indicator, a card insertion display lamp, and a card insertion slot. A frequency display LED 60, a ball lending LED 61, a ball lending switch 62, and a return switch 63 provided in the vicinity of the hitting ball supply tray 3 are connected to the interface board (relay board) 66.

  A card lending switch signal indicating that the ball lending switch 62 has been operated and a return switch signal indicating that the return switch 63 has been operated are provided to the card unit 50 from the interface board 66 in accordance with the player's operation. . Further, a card balance display signal indicating a prepaid card balance and a ball lending display signal are given from the card unit 50 to the interface board 66. Between the card unit 50 and the payout control board 37, a connection signal (VL signal), a unit operation signal (BRDY signal), a ball lending request signal (BRQ signal), a ball lending completion signal (EXS signal) and a pachinko machine operation signal ( PRDY signal) is transmitted / received via the input port 372f and the output port 372d. An interface board 66 is interposed between the card unit 50 and the payout control board 37. Therefore, a signal such as a connection signal (VL signal) is transmitted and received between the card unit 50 and the payout control board 37 via the interface board 66 as shown in FIG.

  When the power of the pachinko gaming machine 1 is turned on, the payout control microcomputer 370 mounted on the payout control board 37 outputs a PRDY signal to the card unit 50. The card unit control microcomputer outputs a VL signal when the power is turned on. The payout control microcomputer 370 determines the connected / unconnected state of the card unit 50 according to the input state of the VL signal. When a card is received in the card unit 50, the ball lending switch is operated and a ball lending switch signal is input, the card unit control microcomputer outputs a BRDY signal to the payout control board 37. When a predetermined delay time elapses from this point, the card unit control microcomputer outputs a BRQ signal to the payout control board 37.

  Then, the payout control microcomputer 370 raises the EXS signal to the card unit 50 and, when detecting the fall of the BRQ signal from the card unit 50, drives the payout motor 289 to give a predetermined number of rental balls to the player. Pay out. When the payout is completed, the payout control microcomputer 370 causes the EXS signal to the card unit 50 to fall. Thereafter, on the condition that the BRDY signal from the card unit 50 is not in the ON state, the winning ball payout control is executed when a payout command signal is received from the game control means.

  The power supply voltage AC24V used in the card unit 50 is supplied from the payout control board 37. That is, power supply from the power supply board 910 to the card unit 50 is performed via the payout control board 37 and the interface board 66. In this example, a fuse for protecting the card unit 50 is provided in a 24 V AC power supply line for the card unit 50 arranged in the interface board 66, and a voltage higher than a predetermined voltage is supplied to the card unit 50. It is prevented.

  In this embodiment, the case where the card unit 50 is installed adjacent to the gaming machine as a separate body from the gaming machine is taken as an example, but the card unit 50 may be integrated with the gaming machine. . Further, the present invention can be applied even when a game ball corresponding to the amount of money is lent out in accordance with coin insertion.

  FIG. 6 is a block diagram showing a circuit configuration example of the relay board 77, the sound / lamp control board 80b, and the symbol control board 80a. In this embodiment, the sound / lamp control board 80b performs sound output control of the sound output device 27 and display control of each lamp 25, 28a, 28b, 28c. The symbol control board 80a performs display control of the variable display device 9. In this embodiment, “effect control” means display control of the variable display device 9, sound output control of the speaker 27, and display control of the lamps 25, 28a, 28b, and 28c. It means performing such as. Further, the effect control means is a sound / lamp control for performing the display control of the variable display device 9, the sound output control of the speaker 27, and the display control of the lamps 25, 28a, 28b, 28c. This is realized by the microcomputer 100b. In this embodiment, the sound / lamp control microcomputer 100b and / or the symbol control microcomputer 100a may be referred to as production control means. Also, only the effect control board may be provided for effect control without providing the sound / lamp control board 80b and the symbol control board 80a.

  The sound / lamp control board 80b is mounted with a sound / lamp control microcomputer 100b including a sound / lamp control CPU 101b and a RAM. The RAM may be externally attached. In the sound / lamp control board 80b, the sound / lamp control CPU 101b operates in accordance with a program stored in a built-in or external ROM (not shown), and from the main board 31 input via the relay board 77. In response to the capture signal (effect control INT signal), an effect control command is received via the input driver 102 and the input port 103.

  The effect control command and the effect control INT signal are first input to the input driver 102 on the sound / lamp control board 80b. The input driver 102 passes the signal input from the relay board 77 only in the direction toward the sound / lamp control board 80b (passes the signal in the direction from the sound / lamp control board 80b to the relay board 77). It is also a unidirectional circuit as signal direction regulating means.

  A signal that allows the signal input from the main board 31 to pass through the relay board 77 only in the direction toward the sound / lamp control board 80b (does not pass the signal in the direction from the sound / lamp control board 80b to the relay board 77). A unidirectional circuit 74 as a direction regulating means is mounted. For example, a diode or a transistor is used as the unidirectional circuit. FIG. 6 illustrates a diode. A unidirectional circuit is provided for each signal. Furthermore, since the effect control command and the effect control INT signal are output from the main board 31 via the output port 571 that is a unidirectional circuit, the signal from the relay board 77 toward the inside of the main board 31 is restricted. That is, the signal from the relay board 77 does not enter the inside of the main board 31 (the game control microcomputer 560 side). The output port 571 is a part of the I / O port unit 57 shown in FIG. Further, a signal driver circuit that is a unidirectional circuit may be further provided outside the output port 571 (on the relay board 77 side).

  Further, the sound / lamp control CPU 101 b outputs a signal for driving the lamp to the lamp driver 352. The lamp driver 352 amplifies a signal for driving the lamp and supplies the amplified signal to each lamp provided on the frame side such as the top frame lamp 28a, the left frame lamp 28b, and the right frame lamp 28c. Further, it is supplied to a decorative lamp 25 provided on the frame side.

  Further, the sound / lamp control CPU 101b outputs sound number data to the speech synthesis IC 173. The voice synthesizing IC 173 generates a voice or a sound effect corresponding to the sound number data and outputs it to the amplifier circuit 175. The amplifier circuit 175 outputs an audio signal obtained by amplifying the output level of the speech synthesis IC 173 to a level corresponding to the volume set by the volume 176 to the speaker 27. The voice data ROM 174 stores control data corresponding to the sound number data. The control data corresponding to the sound number data is a collection of data indicating the sound effect or sound output mode in a time series in a predetermined period (for example, a decorative symbol variation period).

  The signal for driving the lamp and the sound number data are communicated between the sound / lamp control CPU 101b, the lamp driver 352, and the speech synthesis IC 173 (a response signal is transmitted from the signal receiving side to the transmitting side). Communication).

  In addition, the sound / lamp control microcomputer 100b determines the contents of the effect to be performed using the variable display device 9 based on the effect control command (for example, the variation pattern command). For example, the sound / lamp control microcomputer 100b uses the variable display device 9 to determine whether to perform a notice effect. Further, for example, the sound / lamp control microcomputer 100 b determines the type of the notice effect to be performed using the variable display device 9.

  The “notice effect” is an effect for informing the player in advance (before the decorative symbol stop symbol is derived and displayed on the variable display device 9) that it is a big hit or is likely to be a big hit. Say. For example, the player is informed that there is a possibility of a big hit by changing a different mode (speed, direction of rotation, etc.) or making a character appear during the change.

  In addition, the sound / lamp control microcomputer 100 b transfers (transmits) an effect control command (for example, a display result designation command) from the main board 31 to the symbol control board 80 a via the input / output port 104. Further, the sound / lamp control microcomputer 100b generates an effect content designation command indicating the determined effect content (whether or not to perform the notice effect and the type of the notice effect). In addition, the sound / lamp control microcomputer 100 b transmits the generated effect content designation command to the symbol control board 80 a via the input / output port 104.

  Note that the sound / lamp control microcomputer 100b adds the determined contents (whether or not to perform the notice effect and the type of the notice effect) to the effect control command (variation pattern command or display result designation command). Also good. Then, the sound / lamp control microcomputer 100 b may transmit an effect control command to which the effect content is added to the symbol control board 80 a via the input / output port 104.

  The symbol control board 80a is equipped with a symbol control microcomputer 100a including a symbol control CPU 101a and a RAM. The RAM may be externally attached. In the symbol control board 80a, the symbol control CPU 101a operates according to a program stored in a built-in or external ROM (not shown). Further, the symbol control CPU 101a causes the VDP (video display processor) 109 to perform display control of the variable display device 9 using the LCD, based on the effect control command received from the sound / lamp control board 80b.

  The symbol control CPU 101a reads necessary data from a character ROM (not shown) in accordance with the received effect control command. The character ROM stores character image data frequently used among images displayed on the variable display device 9, specifically, a person, a character, a figure, a symbol, or the like (including decorative designs) in advance. Is. The symbol control CPU 101a outputs the data read from the character ROM to the VDP 109. The VDP 109 executes display control based on data input from the symbol control CPU 101a.

  In this embodiment, the VDP 109 that performs display control of the variable display device 9 is mounted on the symbol control board 80a. The VDP 109 has an address space independent of the symbol control microcomputer 100a, and maps a VRAM therein. The VRAM is a buffer memory for expanding image data generated by the VDP. Then, the VDP 109 outputs the image data in the VRAM to the variable display device 9. Note that a number of VDPs corresponding to the number of variable display devices may be mounted on the symbol control board 80a.

  FIG. 7 is a block diagram showing a circuit configuration of the main board 31 and signal lines of an effect control command transmitted from the main board 31 to the sound / lamp control board 80b. As shown in FIG. 7, in this embodiment, the game control microcomputer 560 mounted on the main board 31 uses eight signal lines CD0 to CD7 for transmitting the effect control signal to output the effect control command. / Send to lamp control board 80b. In addition, a signal line of an effect control INT signal for transmitting and receiving a strobe signal is also wired between the main board 31 and the sound / lamp control board 80b.

  As shown in FIG. 7, wiring from the start port switch 14a is connected to the main board 31. The main board 31 is also provided with wiring from the special variable winning ball apparatus 20 which is a big winning opening, and various switches 29a, 30a, 33a, 39a for detecting the winning of game balls to other winning openings. It is connected. Further, the main board 31 is connected to a solenoid 16 for opening and closing the variable winning ball apparatus 15, a solenoid 21 for opening and closing the special variable winning ball apparatus 20, and a wiring to the solenoid 21A for switching the path in the special winning opening. .

  The main board 31 includes a game control microcomputer 560, an input driver circuit 58, and an output circuit 59. The game control microcomputer 560 operates in accordance with a clock circuit 501, a reset controller 502 that functions as a system reset means, a random number circuit 503a, 503b, a ROM 54 that stores a game control program, a RAM 55 that is used as a work memory, and a program. CPU 56, CTC 504 for sending an interrupt request signal (interrupt request signal by timer interrupt) to CPU 56, serial communication circuit 505 for performing asynchronous serial communication with the microcomputer provided in payout control board 37 and sound / lamp control board 80b, and An I / O port unit 57 is incorporated.

  In this embodiment, the microcomputer on a board (for example, the payout control board 37 or the sound / lamp control board 80b) different from the board (for example, the main board 31) on which the microcomputer incorporating the serial communication circuit 505 is mounted. Although the case where the serial communication circuit 505 is used for communication with the serial communication circuit 505 will be described, the serial communication circuit 505 may perform serial communication with another microcomputer included in the board on which the microcomputer incorporating the serial communication circuit 505 is mounted. For example, when two microcomputers having the same configuration are mounted on the same substrate, serial communication circuits built in the microcomputers may perform serial communication with each other.

The clock circuit 501 outputs a reference clock signal CLK having a predetermined period generated by dividing the system clock signal by 2 ⁷ (= 128) to the random number circuits 503a and 503b. When a low level signal is input for a predetermined period, the reset controller 502 outputs a predetermined initialization signal to the CPU 56 and the random number circuits 503a and 503b to reset the game control microcomputer 560.

  Further, in this embodiment, as shown in FIG. 7, the game control microcomputer 560 includes two random number circuits 503a and 503b having different ranges of random number values that can be generated. The random number circuit 503a is a random number circuit (hereinafter also referred to as a 12-bit random number circuit) that generates a 12-bit pseudo-random number. The 12-bit random number circuit 503a has a function of generating a random number having a value within a range that can be generated by 12 bits (that is, a range from 0 to 4095). The random number circuit 503b is a random number circuit (hereinafter also referred to as a 16-bit random number circuit) that generates a 16-bit pseudo random number. The 16-bit random number circuit 503b has a function of generating a random number having a value in a range that can be generated in 16 bits (that is, a range from 0 to 65535). In this embodiment, the case where the game control microcomputer 560 includes two random number circuits is described. However, the game control microcomputer 560 may include three or more random number circuits. In this embodiment, when the 12-bit random number circuit 503a and the 16-bit random number circuit 503b are comprehensively expressed, or when indicating either the 12-bit random number circuit 503a or the 16-bit random number circuit 503b, This is called a random number circuit 503.

  Next, the configuration of the random number circuit 503 will be described. FIG. 8 is a block diagram illustrating a configuration example of the random number circuit 503. In this embodiment, the basic configurations of the 12-bit random number circuit 503a and the 16-bit random number circuit 503b are the same. As shown in FIG. 8, the random number circuit 503 includes a counter 521, a comparator 522, a count value permutation changing circuit 523, a clock signal output circuit 524, a count value update signal output circuit 525, a random value read signal output circuit 526, a random number update. A system selection signal output circuit 527, a selector 528, a random number circuit activation signal output circuit 530, a random value storage circuit 531, an inversion circuit 532, a latch signal generation circuit 533, and a timer circuit 534 are included.

  In this embodiment, the random number circuit 503 determines whether the display result of variable display of a plurality of types of identification information is a specific display result (for example, the combination of display symbols of the special symbol display device 8 is a combination of jackpot symbols) A random number for jackpot determination is generated. When the CPU 56 of the game control microcomputer 560 determines that the specific display result is based on the random number generated by the random number circuit 503, the game state is changed to a specific game state advantageous to the player (for example, a big hit game state). Transition.

  The counter 521 receives the predetermined signal selected by the selector 528 and outputs a count value C in response to the signal input from the selector 528. In this case, the counter 521 inputs a predetermined initial value, cyclically updates the count value C from the initial value to a predetermined final value according to a certain rule, and outputs it. Further, when the count value C is updated to the final value, the counter 521 outputs a notification signal indicating that the count value C has been updated to the final value to the CPU 56. In this embodiment, when a notification signal is output from the counter 521, the CPU 56 updates the initial value.

  In this embodiment, every time a signal is input from the selector 528 (every time a rising edge in the signal from the selector 528 is input), the counter 521 increments the count value C from “0” to “4095” by one. Count up. Further, when the counter 521 counts up the count value C to “4095”, the counter 521 outputs a notification signal indicating that the count value C has been updated to the final value to the CPU 56. Then, the CPU 56 inputs a notification signal from the counter 521 and updates the initial value. Then, the counter 521 counts up the count value C again from the initial value updated by the CPU 56 to “4095”. Further, when counting up to “4095”, the counter 521 starts counting from “0” again. Then, the counter 521 outputs a notification signal to the CPU 56 when it counts up to a value (final value) immediately before the updated initial value. In this embodiment, the comparator 522 outputs a notification signal to the counter 521 when all count values are input, as will be described later. In this case, when the notification signal is input from the comparator 522, the counter 521 resets the count value to “0”.

  The comparator 522 determines whether the input count value is larger than the random number maximum value set in the random number maximum value setting register 535, and the count value is larger than the random number maximum value (exceeded the random number maximum value). ), A notification signal may be output to the counter 521. In this case, for example, when the comparator 522 determines that the count value exceeds the random number maximum value, the notification signal is output to the counter 521 before the clock signal output circuit 524 next outputs the random number generation clock signal SI1. . For example, consider a case where the random number maximum value “256” is set in the random number maximum value setting register 535. In this case, when the counter 521 counts up from “0” to “256” and further outputs the count value “257”, the comparator 522 determines that the input count value “257” exceeds the random number maximum value “256”. Determine and output a notification signal to the counter 521. When the notification signal is input from the comparator 522, the counter 521 updates the count value to “258” and outputs it without waiting for the input of the random number generation clock signal SI1 from the clock signal output circuit 524. By repeatedly executing the above processing, the comparator 522 determines that the count value exceeds the random number maximum value while inputting from the count value “257” to “4095”. Output a notification signal. The counter 521 repeatedly updates and outputs the count value without waiting for the input of the random number generation clock signal SI1 from the clock signal output circuit 524 while the notification signal is input from the comparator 522. By doing so, until the clock signal output circuit 524 next outputs the random number generation clock signal SI1, the count value is controlled to be counted up from “257” to “4095” at a high speed, Control is performed so that random numbers from “257” to “4095” are skipped (not stored in the random value storage circuit 531).

  The count value permutation change circuit 523 includes a count value permutation change register (RSC) 536, an update rule selection register (RRC) 542, and an update rule memory 543. The count value permutation change register 536 stores count value permutation change data “01h” for changing the permutation (order of arrangement from the initial value to the final value), which is the update order of the count value C counted up by the counter 521. . When the numerical value permutation change data “01h” is stored in the count value permutation change register 536, the count value permutation change circuit 523 displays the count value C permutation that the counter 521 counts up and updates. Change to a different permutation from when “01h” is not stored. In this case, when the numerical value permutation change data “01h” is stored, the count value permutation changing circuit 523 switches the update rule used for changing the permutation of the count values. When the counter 521 starts updating the count value after switching the update rule used for changing the count value permutation, the count value permutation change data in the count value permutation change register 536 is initialized from “01h” by the CPU 56. The value is returned to “0 (= 00h)” (cleared).

  Instead of clearing the count value permutation data by the CPU 56, the random number circuit 503 may clear the count value permutation data. For example, when the register value is set in the update rule selection register (RRC) 542 based on the count value permutation change data “01h” being written in the count value permutation change register 536, the count value permutation change circuit 523 The register value of the count value permutation change register 536 may be cleared.

  FIG. 9 is an explanatory diagram illustrating an example of the update rule selection register 542. The update rule selection register 542 is a register that sets an update rule used for rearranging the order of count values output from the counter 521 (changing the permutation). In this embodiment, an update rule used to change the permutation of count values output from the counter 521 is set by setting a register value in the update rule selection register 542. As shown in FIG. 9, the update rule selection register 542 is an 8-bit register, and the initial value is set to “0 (= 00h)”. The update rule selection register 542 is configured in a state where bits 0 to 3 can be written and read. In addition, the update rule selection register 542 is configured in a state where bits 4 to 7 cannot be written or read. Therefore, even if control is performed to write a value to bits 4 to 7 of the update rule selection register 542, it is invalid, and all the values read from bits 4 to 7 are “0 (= 0000b)”.

  The value (register value) of the update rule selection register 542 is changed from “0 (= 00h)” to “15” in response to the count value permutation change data “01h” being written in the count value permutation change register 536. (= 0Fh) ”is updated cyclically. That is, each time the count value permutation data “01h” is written to the count value permutation change register 536, the register value of the update rule selection register 542 is incremented by “1” from “0”. Return to "0".

  FIG. 10 is an explanatory diagram showing an example of the update rule memory 543. As shown in FIG. 10, the update rule memory 543 stores the value (register value) of the update rule selection register 542 and the count value update rule in association with each other. In the example shown in FIG. 10, for example, when the register value 1 is set in the update rule selection register 542, it can be seen that the permutation of the count values output by the counter 521 is changed using the update rule B. In FIG. 10, the update rule A is the same update rule as that by which the counter 521 updates the count value C, and is stored in the update rule memory 543 in association with the register value “0”. Also, in the update rule memory 543, update rules B to P different from the update rule in which the counter 521 updates the count value C are stored in association with the register values “1” to “15”.

  When the count value permutation change data “01h” is written in the count value permutation change register 536, the count value permutation change circuit 523 first counts from the counter 521 until the final count value “4095” is first input. The count value is output as it is according to the currently set update rule. When the count value permutation changing circuit 523 receives the final count value “4095” from the counter 521, the count value permutation changing circuit 523 changes the count value update rule. When the initial value has been changed by the CPU 56, the count value permutation changing circuit 523 inputs the final value after the change (the value immediately before the initial value) from the counter 521, and updates the count value. Will be changed.

  The count value permutation change circuit 523 selects an update rule corresponding to the register value of the update rule selection register 542 from the update rule memory 543, and sets it as an update rule used for changing the count value permutation. The count value permutation changing circuit 523 changes the permutation from the initial value of the count value to the final value according to the set update rule when the counter 521 starts updating the count value again from the initial value “0”. To do. When the initial value is changed by the CPU 56, the count value permutation changing circuit 523 starts counting in accordance with the set update rule when the counter 521 starts updating the count value in order from the changed initial value. The permutation from the initial value to the final value will be changed. Then, the count value permutation change circuit 523 outputs a count value according to the changed permutation.

  In this embodiment, when the maximum random number to be generated is limited by setting the random number maximum value in a random number maximum value setting register 535 described later, the count value permutation changing circuit 523 counts The value C is limited to the maximum random number or less, and the permutation is changed and output. For example, it is assumed that the random number maximum value “256” is set in the random number maximum value setting register 535, and the count value permutation changing circuit 523 changes the update rule A to the update rule B to change the permutation of the count values. Shall. In this case, the count value permutation changing circuit 523 changes the count value permutation to “256 → 255” in accordance with the update rule B based on the random number maximum value “256” set in the random number maximum value setting register 535 of the comparator 522. → → → 0 "and output.

  As described above, when the count value permutation change data “01h” is written in the count value permutation change register 536, the count value permutation change circuit 523 switches the update rule to use the permutation of the count value C. Change and output. Therefore, the randomness of the random number generated by the random number circuit 503 can be improved.

  FIG. 11 is an explanatory diagram illustrating an example in which the count value permutation changing circuit 523 changes the permutation of the count values output from the counter 521. As shown in FIG. 11, the CPU 56 writes the count value permutation change data “01h” into the count value permutation change register 536 at a predetermined timing. Then, 1 is added to the register value of the update rule selection register 542. For example, the register value of the update rule selection register 542 is updated from “0” to “1”. When the register value is updated, the count value permutation changing circuit 523 updates the “update rule A” corresponding to the register value “0” before the update until the final value “4095” of the count value is input from the counter 521 for the first time. The count value is updated according to "." At this time, the count value permutation changing circuit 523 outputs the count values in a permutation of “0 → 1 →... → 4095” according to the update rule A.

  When the final value “4095” of the count value is input from the counter 521, the count value permutation changing circuit 523 selects “update rule B” corresponding to the updated register value “1” from the update rule memory 543. To set. When the count value permutation changing circuit 523 starts to input the count values after the initial value “0” from the counter 521 again, the count value permutation changing circuit 523 changes the permutation of the count values according to the “update rule B” selected and set. In this example, the count value permutation changing circuit 523 changes the permutation from “0 → 1 →... → 4095” to “4095 → 4094 →... → 0” and outputs the count value.

  Thereafter, the count value permutation change register 536 is reset in response to the count value permutation change circuit 523 starting the count value updating operation according to the updated update rule, as will be described later. The count value permutation change circuit 523 then counts the permutations that remain “4095 → 4094 →... → 0” until the count value permutation change data “01h” is written to the count value permutation change register 536 next time. Continue to output values.

  When the count value permutation change data “01h” is written again to the count value permutation change register 536 by the CPU 56, the register value of the count value permutation change register 536 is updated from “1” to “2”. When the final value “4095” of the count value is input from the counter 521, the count value permutation changing circuit 523 selects and sets “update rule C” corresponding to the register value “2” from the update rule memory 543. . When the count value permutation changing circuit 523 starts to input count values after the initial value “0” again from the counter 521, the count value permutation changing circuit 523 updates and outputs the count value permutation according to the “update rule C” selected and set. In this example, the count value permutation changing circuit 523 changes the permutation from “4095 → 4094 →... → 0” to “1 → 3 →... → 4095 → 0 →. Is output.

  As described above, after the count value permutation change register 536 is reset, the count value permutation data “01h” is written again in the count value permutation change register 536, so that the count value permutation can be further changed.

  FIG. 12 is an explanatory diagram illustrating an example of the count value permutation change register 536. The count value permutation change register 536 is a register that sets count value permutation change data “01h” for changing the permutation of count values counted up by the counter 521. As shown in FIG. 12, the count value permutation change register 536 is a readable 8-bit register, and the initial value is set to “0 (= 00h)”. Further, count value permutation change register 536 is configured such that only bit 0 can be written and read. That is, count value permutation change register 536 is configured such that bits 1 to 7 cannot be written or read. Therefore, even if control is performed to write a value in bits 1 to 7 of the count value permutation change register 536, it is invalid, and all values read from bits 1 to 7 are “0 (= 0000000b)”.

  Note that the value of the count value permutation change register 536 is reset by the CPU 56 in response to the count value permutation change circuit 523 starting the update operation of the count value according to the updated update rule. In this case, the CPU 56 returns the value written in the count value permutation change register 536 from the count value permutation change data “01h” to the initial value “0 (= 00h)”.

  The comparator 522 includes a random number maximum value setting register (RMX) 535 that stores random number maximum value setting data for designating the maximum value of random R (random number maximum value). The comparator 522 limits the update range of the count value updated by the counter 521 in accordance with the random number maximum value indicated in the random number maximum value setting data stored in the random number maximum value setting register 535. In this embodiment, the comparator 522 has a random number maximum value (for example, “00FFh”) indicated by the count value input from the counter 521 and the random number maximum value setting data (for example, “00FFh”) stored in the random number maximum value setting register 535. 256 "). When the comparator 522 determines that the input count value is equal to or less than the random number maximum value, the comparator 522 outputs the input count value to the random value storage circuit 531.

  In this embodiment, the comparator 522 specifically performs the following control. The comparator 522 obtains the initial value of the count value from the CPU 56 when updating the initial value of the count value, and obtains the number of count values from the initial value to the maximum random number. For example, when the initial value of the count value is “157” and the maximum random number value is “256”, the comparator 522 calculates the number of count values from the initial value to the maximum random number value as “100”. Further, the comparator 522 counts up how many count values are input from the initial value as the count values are input from the count value permutation changing circuit 523. When the number of input count values from the initial value reaches “100”, the comparator 522 determines that all count values from the initial value “157” to the maximum value “256” have been input. Then, the comparator 522 outputs a notification signal indicating that all the count values have been input to the counter 521. By determining based on the number of count values, even if the count value permutation circuit 523 has changed the count value permutation, the comparator 522 limits the count value update range to the maximum random number or less. When all count values are input, a notification signal can be output to the counter 521.

  An operation in which the comparator 522 limits the update range of the count value will be described. In this example, a case where the count value permutation changing circuit 523 selects the update rule A and the random number maximum value “256” is set in the random number maximum value setting register 535 will be described.

  While the counter 521 is updating the count value from “0” to “256”, the count value permutation changing circuit 523 updates based on the random number maximum value “256” set in the random number maximum value setting register 535. In accordance with rule A, the count values from “0” to “256” are output to the comparator 522 as they are. In this case, the count value permutation changing circuit 523 receives the value of the random number maximum value “256” from the comparator 522, determines whether the count value input from the counter 521 is larger than the random number maximum value, and the update rule is changed. Even when it is set (for example, update rule B), the count values from “257” to “4095” are compared based on the random number maximum value “256” set in the random number maximum value setting register 535. The data is not output to the device 522. For example, when the initial value is set to “0” and the count value is updated to the final value “256”, the counter 521 outputs a notification signal to the CPU 56. When the notification signal is output, the CPU 56 changes the initial value of the count value of the counter 521. In this example, the CPU 56 changes the initial value to “50”.

  Note that the comparator 522 may determine whether the count value is greater than the maximum random number “256”, instead of the count value permutation changing circuit 523. In this case, for example, the comparator 522 determines whether or not the count value is larger than the random number maximum value set in the random number maximum value setting register 535, and determines that the count value is larger than the random number maximum value. Is output to the counter 521. When the comparator 522 determines that the count value exceeds the random number maximum value, the comparator 522 outputs a notification signal to the counter 521 before the clock signal output circuit 524 next outputs the random number generation clock signal SI1. By doing so, the comparator 522 counts up the count value from “257” to “4095” at high speed until the clock signal output circuit 524 next outputs the random number generation clock signal SI1. Thus, the counter 521 is controlled. By doing so, the count value is output to the random value storage circuit 531 only when the value from the count value permutation changing circuit 523 is less than “257”, and the value from the count value permutation changing circuit 523 is “257”. When the value is greater than or equal to “,” the count value can be updated at high speed.

  Based on the update rule A, while the count value is input from “0” to “255” from the count value permutation changing circuit 523, the comparator 522 inputs the count value below the maximum random number “256”. Therefore, the input count value is output to the random value storage circuit 531 as it is. Next, when the count value input from the count value permutation changing circuit 523 reaches “256”, the comparator 522 outputs the input count value to the random value storage circuit 531 and all the values from the initial value to the maximum value. A notification signal indicating that the count value is input is output to the counter 521. Specifically, the comparator 522 receives the initial value of the count value (“0” in this example) from the CPU 56 when changing the initial value of the count value, and from the initial value “0” to the maximum random number (this In the example, the number of count values up to “256” (in this example, “257”) is obtained. When the number of count values input from the count value permutation changing circuit 523 reaches 257, a notification signal indicating that all count values have been input is output to the counter 521. In this example, since the CPU 56 changes the initial value to “50”, the counter 521 does not reset the count value even when the notification signal is input from the comparator 522, and the changed initial value “50”. The count value is updated.

  While the counter 521 updates the count value from the changed initial value “50” to “256”, the count value permutation changing circuit 523 sets the random number maximum value “256” set in the random number maximum value setting register 535. Based on this, according to the update rule A, the count values from “50” to “256” are output to the comparator 522 as they are. Further, the count value permutation changing circuit 523 does not output the count values from “257” to “4095” to the comparator 522 based on the random number maximum value “256” set in the random number maximum value setting register 535. When the count value to be updated by the counter 521 makes one round (when updated 257 times), when the count value permutation change data is written in the count value permutation change register 536, the count value permutation change circuit 523 Change the permutation of count values and output. For example, when the update rule is changed to the update rule B, the count value permutation changing circuit 523 changes the count value permutation from “256 → 255 →... → 50” and outputs the result.

  While the count values from “256” to “50” are input from the count value permutation changing circuit 523, the comparator 522 outputs the input count value as it is to the random value storage circuit 531. Next, when the count value input from the count value permutation change circuit 523 reaches “50”, the comparator 522 outputs the input count value to the random value storage circuit 531 and all the values from the initial value to the maximum value. A notification signal indicating that the count value is input is output to the counter 521. Specifically, the comparator 522 receives the initial value of the count value (“50” in this example) from the CPU 56 when changing the initial value of the count value, and the random number maximum value (this In the example, the number of count values up to “256” (in this example, “207”) is obtained. When the number of count values input from count value permutation changing circuit 523 reaches 207, a notification signal indicating that all count values have been input is output to counter 521.

  Even when the count value permutation changing circuit 523 changes the count value permutation, the comparator 522 outputs a notification signal to the counter 521 when the number of count values reaches 207. By doing so, even if the permutation of the count values is changed, the notification signal is counted based on the input of all the count values from the initial value “50” to the maximum value “256”. 521 can be output.

  When the notification signal is input from the comparator 522, the counter 521 resets the initial value of the count value and returns it to “0”. Then, the counter 521 updates the count value from “0”. When the value of the counter 521 is updated again from “0”, the count value permutation changing circuit 523 outputs the count values from “49” to “0” to the comparator 522 based on the count value from the counter 521. The comparator 522 outputs the count value to the random value storage circuit 531 based on the count value input from the count value permutation changing circuit 523. When the counter 521 updates the count value to the final value (“49” in this example), it outputs a notification signal to the CPU 56. When the notification signal is output, the initial value of the count value of the counter 521 is changed again by the CPU 56.

  By repeating the operation as described above, the comparator 522 causes the counter 521 to continuously count up the count value from “0” to the maximum random number “256”, and the value from “0” to “256”. Is stored in the random value storage circuit 531 as a random R (random number value). That is, the comparator 522 limits the update range of the count value to the random number maximum value “256” or less, and causes the counter 521 to update the count value.

  FIG. 13 is an explanatory diagram illustrating an example of the random number maximum value setting register 535. FIG. 13A shows an example of the random number maximum value setting register 535 installed in the 12-bit random number circuit 503a. FIG. 13B shows an example of the random number maximum value setting register 535 installed in the 16-bit random number circuit 503b. First, the random number maximum value setting register 535 mounted in the 12-bit random number circuit 503a will be described. As shown in FIG. 13A, in the 12-bit random number circuit 503a, the random number maximum value setting register 535 is a 16-bit register, and the initial value is set to “4095 (= 0FFFh)”. The random number maximum value setting register 535 is configured such that bits 0 to 11 can be written and read. The random number maximum value setting register 535 is configured such that bits 12 to 15 cannot be written or read. Therefore, in the 12-bit random number circuit 503a, even if control is performed to write values to bits 12 to 15 of the random number maximum value setting register 535, the values read from bits 12 to 15 are all “0 (= 0000b)”. It is.

  The random number maximum value set in the random number maximum value setting register 535 has a predetermined lower limit value. In this embodiment, when random number maximum value setting data “0000h” to “00FEh” designating a value smaller than the lower limit value “256” is written in the random number maximum value setting register 535, the CPU 56 stores the random number maximum value setting register. The random number maximum value setting data “0FFFh” for specifying the initial value “4095” is set again in 535. That is, the random number maximum value that can be set in the random number maximum value setting register 535 is from “256” to “4095”, and when the CPU 56 determines that a value smaller than the lower limit value “256” is set, the random number maximum value Is reset to a predetermined value “4095”. The CPU 56 controls the random number maximum value setting register 535 in which the random number maximum value setting data is written to be unwritable until the game control microcomputer 560 is system-reset by the reset controller 502. Instead of controlling the CPU 56 to disable writing, the random number maximum value setting register 535 may be formed so that writing is not possible until a reset signal is input after data is written.

  Next, the random number maximum value setting register 535 mounted in the 16-bit random number circuit 503b will be described. As shown in FIG. 13B, in the 16-bit random number circuit 503b, the random number maximum value setting register 535 is a 16-bit register, and the initial value is set to “65535 (= FFFFh)”. Further, in the 16-bit random number circuit 503b, the random number maximum value setting register 535 is configured in a state in which all of the bits 0 to 15 can be written and read.

  When random number maximum value setting data “0000h” to “00FEh” for designating a value smaller than the lower limit value “512” is written in the random number maximum value setting register 535, the CPU 56 stores the initial value in the random number maximum value setting register 535. The random number maximum value setting data “FFFFh” specifying the value “65535” is reset. That is, the random number maximum value that can be set in the random number maximum value setting register 535 is from “512” to “65535”, and when the CPU 56 determines that a value smaller than the lower limit value “512” is set, the random number maximum value Is reset to a predetermined value “65535”. The CPU 56 controls the random number maximum value setting register 535 in which the random number maximum value setting data is written to be unwritable until the game control microcomputer 560 is system-reset by the reset controller 502. In this case, the random number maximum value setting register 535 may be formed not to be writable until a reset signal is input after data is written, instead of being controlled so as not to be writable by the CPU 56.

  The clock signal output circuit 524 includes a cycle setting register (RPS) 537 that stores cycle setting data for designating the cycle of the clock signal output to the selector 528 and the inverting circuit 532 (that is, the count value update cycle). The clock signal output circuit 524 divides the reference clock signal CLK input from the clock circuit 501 mounted on the game control microcomputer 560 based on the period setting data stored in the period setting register 537, and generates a random number circuit. A clock signal (random number generating clock signal SI1) used to generate a random number value is generated inside 503. By doing so, the clock signal output circuit 524 operates to output the random number generation clock signal SI1 for updating the count value C to the counter 521 on condition that the clock signal has been input a predetermined number of times. . The period setting data is data for setting how many times the reference clock signal CLK input from the clock circuit 501 is to be divided. The clock output circuit 524 outputs the generated random number generating clock signal SI1 to the selector 528 and the inverting circuit 532. For example, when the cycle setting data “0Fh (= 16)” is written in the cycle setting register 537, the clock signal output circuit 524 divides the reference clock signal CLK input from the clock circuit 501 by 16, and generates random numbers. A clock signal SI1 is generated. In this case, the cycle of the random number generating clock signal SI1 generated by the clock signal output circuit 524 is “cycle of system clock signal × 128 × 16”.

  FIG. 14 is an explanatory diagram illustrating an example of the cycle setting register 537. As shown in FIG. 14, the period setting register 537 is an 8-bit register, and the initial value is set to “256 (= FFh)”. The cycle setting register 537 is configured in a state where both writing and reading are possible.

  In addition, a predetermined lower limit value is determined for the value of the cycle setting data set in the cycle setting register 537. In this embodiment, when the cycle setting data “00h to 06h” designating a value smaller than the lower limit value “system clock signal cycle × 128 × 7” is written in the cycle setting register 537, the CPU 56 In 537, the cycle setting data “07h” for specifying the lower limit value “cycle of system clock signal × 128 × 7” is reset. That is, the period that can be set in the period setting register 537 is “system clock signal period × 128 × 7” to “system clock signal period × 128 × 256”, and the CPU 56 is set to a value smaller than the lower limit value. If it is determined that the cycle setting data is correct, the cycle setting data is reset. The CPU 56 controls the period setting register 537 in which the period setting data is written to be unwritable until the game control microcomputer 560 is system-reset by the reset controller 502. Instead of controlling the CPU 56 to disable writing, the period setting register 537 may be formed so that writing is not possible until a reset signal is input after data is written.

  Note that, without setting the cycle setting data as the lower limit value in the cycle setting register 537, based on the set cycle setting data, for example, the clock signal output circuit 524 directly supplies the reference clock signal CLK to the counter 521 and the inverting circuit 532. You may make it output. In this case, the CPU 56 does not need to perform processing for comparing the value of the cycle setting data set in the cycle setting register 537 with the lower limit value. The counter 521 updates the count value C every time the reference clock signal CLK is input from the clock signal output circuit 524.

  The count value update signal output circuit 525 includes a count value update register (RGN) 538 that stores count value update data “01h”. The count value update data is data for requesting update of the count value. The count value update signal output circuit 525 outputs the count value update signal SI3 to the selector 528 in response to the count value update data “01h” being written in the count value update register 538.

  FIG. 15 is an explanatory diagram illustrating an example of the count value update register 538. As shown in FIG. 15, the count value update register 538 is an unreadable 8-bit register, and is configured in a state where only bit 0 can be written. Therefore, even if control is performed to write a value to bits 1 to 7 of the count value update register 538, it is invalidated.

  The random value read signal output circuit 526 includes a random value take-in register (RLT) 539 for storing random value take-in data “01h”. The random value acquisition data is data for requesting acquisition of the count value to the random value storage circuit 531. The random value read signal output circuit 526 generates a latch signal for a random value read signal for requesting reading of the random value in response to the random value fetch data “01h” being written in the random value fetch register 539. Output to the circuit 533.

  FIG. 16 is an explanatory diagram showing an example of the random value fetch register 539. As shown in FIG. 16, the random value fetch register 539 is an unreadable 8-bit register. The random value fetch register 539 is configured so that only bit 0 can be written. That is, even if control is performed to write a value to bits 1 to 7 of the random value fetch register 539, it is invalidated.

  The random number update method selection signal output circuit 527 includes a random number update method selection register (RTS) 540 that stores random number update method selection data. The random number update method selection data is data for designating one of the random number update methods, which is a method for updating the value of the random R. The random number update method selection signal output circuit 527 responds to the random number update method selection data written in the random number update method selection register 540, and corresponds to the random number update method specified by the written random number update method selection data. The update method selection signal is output to the selector 528 and the latch signal generation circuit 533.

  FIG. 17A is an explanatory diagram illustrating an example of the random number update method selection register 540. As shown in FIG. 17A, the random number update method selection register 540 is an 8-bit register, and the initial value is set to “00h”. The random number update method selection register 540 is configured in a state where bits 0 to 1 can be written and read. The random number update method selection register 540 is configured in a state where bits 2 to 7 cannot be written or read. Therefore, even if control is performed to write a value to bits 2 to 7 of the random number update method selection register 540, it is invalid, and all the values read from bits 2 to 7 are “0 (= 000000b)”.

  FIG. 17B is an explanatory diagram of an example of random number update method selection data written to the random number update method selection register 540. As shown in FIG. 17B, the random number update method selection data is composed of 2-bit data. The random number update method selection data “01b” is used to specify the first random number update method. The random number update method selection data “10b” is used to specify the second random number update method. In this embodiment, the first random number update method is a method of updating the count value triggered by the output of the count value update signal SI3 from the count value update signal output circuit 525. The second random number update method is a method of updating the count value triggered by the output of the random number generation clock signal SI1 from the clock signal output circuit 524. Further, when the random number update method selection data “01b” or “10b” is written in the random number update method selection register 540, the random number circuit 503 is ready to be activated. On the other hand, when the random number update method selection data “00b” or “11b” is written to the random number update method selection register 540, the random number circuit 503 cannot be activated.

  The selector 528 selects either the count value update signal SI 3 output from the count value update signal output circuit 525 or the random number generation clock signal SI 1 output from the clock signal output circuit 524 and outputs the selected signal to the counter 521. When a random number update method selection signal (also referred to as a first random number update method selection signal) corresponding to the first random number update method is input from the random number update method selection signal output circuit 527, the selector 528 outputs a count value update signal. The count value update signal SI3 output from the circuit 525 is selected and output to the counter 521. On the other hand, when a random number update method selection signal (also referred to as a second random number update method selection signal) corresponding to the second random number update method is input from the random number update method selection signal output circuit 527, the selector 528 outputs a clock signal. The random number generation clock signal SI 1 output from the circuit 524 is selected and output to the counter 521. When the first update method selection signal is input from the random number update method selection signal output circuit 527, the selector 528 receives a clock signal according to the count value update signal SI3 output from the count value update signal output circuit 525. A numerical value update instruction signal for instructing update of numerical data synchronized with the random number generation clock signal SI 1 output from the output circuit 524 may be output to the counter 521.

  The random number circuit activation signal output circuit 530 includes a random number circuit activation register (RST) 541 that stores random number circuit activation data “80h”. The random circuit activation data is data for requesting activation of the random number circuit 503. When the random number circuit activation data “80h” is written in the random number circuit activation register 541, the random number circuit activation signal output circuit 530 outputs a predetermined random number circuit activation signal to the counter 521 and the clock signal output circuit 537, and the counter 521 and the clock The signal output circuit 524 is turned on. The random number circuit 503 is activated by starting the count value update operation by the counter 521 and the internal clock signal output operation by the clock signal output circuit 524.

  FIG. 18 is an explanatory diagram showing an example of the random number circuit activation register 541. As shown in FIG. 18, the random number circuit activation register 541 is an 8-bit register, and the initial value is set to “00h”. The random number circuit activation register 541 is configured such that only bit 7 can be written and read. In addition, the random number circuit activation register 541 is configured such that bits 0 to 6 cannot be written or read. That is, even if control is performed to write a value to bit 0 to bit 6 of the random number circuit activation register 541, it is invalid, and all the values read from bit 0 to bit 6 are “0 (= 000000b)”.

  The random value storage circuit 531 is a 16-bit register, for example, and stores a random R value that is a random number used in the jackpot determination in the game control process. The random value storage circuit 531 stores the count value C output from the counter 521 via the comparator 522 as a random R value in response to the input of the latch signal SL from the latch signal generation circuit 533. Each time the latch signal SL is input from the latch signal generation circuit 533, the random value storage circuit 531 reads the count value C updated by the counter 521 and stores the random R value.

  FIG. 19 is a circuit diagram showing a configuration example of the random value storage circuit 531. As shown in FIG. 19, the random value storage circuit 531 includes two AND circuits 201 and 203, two NOT circuits 202 and 204, 16 flip-flop circuits 2101 to 2116, and 16 OR circuits. 2201-2216.

  As shown in FIG. 19, the input terminal of the AND circuit 201 is connected to the output terminal of the latch signal generation circuit 533 and the output terminal of the NOT circuit 204, and the output terminal is connected to the input terminal of the NOT circuit 202 and the flip-flop circuit 2101. Are connected to clock terminals Clk1 to Clk16. The input terminal of the NOT circuit 202 is connected to the output terminal of the AND circuit 201, and the output terminal is connected to one input terminal of the AND circuit 203.

  The input terminal of the AND circuit 203 is connected to the output terminal of the NOT circuit 202 and the CPU 56 mounted on the game control microcomputer 560, and the output terminal is connected to the input terminal of the NOT circuit 204. The input terminal of the NOT circuit 204 is connected to the output terminal of the AND circuit 203, and the output terminal is connected to one input terminal of the AND circuit 201 and one input terminal of the OR circuits 2201 to 2216.

  The input terminals D1 to D16 of the flip-flop circuits 2101 to 2116 are connected to the output terminal of the comparator 522. The clock terminals Clk1 to Clk16 of the flip-flop circuits 2101 to 2116 are connected to the output terminal of the AND circuit 201, and the output terminals Q1 to Q16 are connected to the other input terminals of the OR circuits 2201 to 2216.

  The input terminals of the OR circuits 2201 to 2216 are connected to the output terminal of the NOT circuit 204 and the output terminals of the flip-flop circuits 2101 to 2116, and the output terminals are connected to the CPU 56 mounted on the game control microcomputer 560. .

  The operation of the random value storage circuit 531 will be described. FIG. 20 is a timing chart showing the timing at which each signal is input to the random value storage circuit 531 and the timing at which the random value storage circuit 531 outputs each signal. As shown in FIG. 20, when the output control signal SC (high level signal in this example) is not input from the CPU 56 mounted in the game control microcomputer 560 (that is, to one input terminal of the AND circuit 203). When the latch signal SL is input from the latch signal generation circuit 533 (in the example shown in FIG. 20, at the timings T1, T2, and T7), the input to the two input terminals of the AND circuit 201 is performed. Both inputs are high. Therefore, the signal SR output from the output terminal of the AND circuit 201 is at a high level. The signal SR output from the AND circuit 201 is input to the clock terminals Clk1 to Clk16 of the flip-flop circuits 2101 to 2116.

  The flip-flop circuits 2101 to 2116 are responsive to the rising edges of the signal SR input from the clock terminals Clk1 to Clk16, and the bit data C1 to C1 of the count value C input from the comparator 522 via the input terminals D1 to D16. C16 is latched and stored as bit data R1 to R16 of the random value. The flip-flop circuits 2101 to 2116 output random R bit data R1 to R16 to be stored from the output terminals Q1 to Q16.

  When the output control signal SC is not input (in the example shown in FIG. 20, the period up to the timing T3 and the period after the timing T6), the input to one input terminal of the AND circuit 203 is at the low level. The signal SG output from the output terminal of the circuit 203 is at a low level. The signal SG output from the AND circuit 203 is inverted in the NOT circuit 204 to be a high level signal. A high level signal is input from the NOT circuit 204 to one input terminal of the OR circuits 2201 to 2216.

  As described above, since the input to one of the input terminals of the OR circuits 2201 to 2216 is at the high level, the OR is input regardless of whether the signal input to the other input terminal is at the high level or the low level. The circuits 2201 to 2216 output high level signals. That is, the signals SO1 to SO16 output from the OR circuits 2201 to 2216 are all at the high level regardless of whether the values of the input random R bit data R1 to R16 are “0” or “1”. (“1”). By doing so, the value output from the random value storage circuit 531 is always “65535 (= 1111111111111111b)”, and the random R cannot be read from the random value storage circuit 531. That is, even if an attempt is made to read a random number from the random value storage circuit 531, only the same value “65535” can always be read from the random value storage circuit 531, and when the output control signal SC is not input, the random value storage circuit 531 becomes an unreadable (disabled) state. When the 16-bit random number circuit 503b is used, the value “65535” as the random number value may be used. In this case, even if the game control microcomputer 560 reads the value “65535”, it cannot determine whether the value is a random number or is unreadable. Therefore, in the determination table for each jackpot determination shown in FIG. 39, when the random R is “65535”, it may be set to determine “lost” in advance.

  When the latch signal SL is not input from the latch signal generation circuit 533 and the output control signal SC is input from the CPU 56 (in the example shown in FIG. 20, the period from the timing T4 to the timing T6), the AND circuit 203 Since the inputs to the two input terminals are both at the high level, the signal SG output from the output terminal of the AND circuit 203 is at the high level. The signal SG output from the AND circuit 203 is inverted in the NOT circuit 204 to be a low level signal. A low level signal is input from the NOT circuit 204 to one input terminal of the OR circuits 2201 to 2216.

  As described above, since the input to one input terminal of the OR circuits 2201 to 2216 is at a low level, when the signal input to the other input terminal is at a high level, the output from the output terminals of the OR circuits 2201 to 2216 is high. A level signal is output. In addition, when a signal input to the other input terminal of the OR circuits 2201 to 2216 is at a low level, a low level signal is output from the OR circuits 2201 to 2216. That is, the values of the random R bit data R1 to R16 input to the other input terminals of the OR circuits 2201 to 2216 are directly received from the output terminals of the OR circuits 2201 to 2216 (that is, the values of the bit data R1 to R16 are “ “1” is output when “1” and “0” when “0”). By doing so, random R can be read from the random value storage circuit 531. That is, when the output control signal SC is input, the random value storage circuit 531 is in a readable (enable) state.

  However, if the latch signal SL is input from the latch signal generation circuit 533 before the output control signal SC is input from the CPU 56, the input to one input terminal of the AND circuit 203 is at a low level. Even if the output control signal SC is input while the signal SL is being input (in the example shown in FIG. 20, the period from the timing T3 to the timing T4), the signal SG output from the output terminal of the AND circuit 203. Remains low. The signal SG output from the AND circuit 203 is inverted in the NOT circuit 204 to be a high level signal. A high level signal is input from the NOT circuit 204 to one input terminal of the OR circuits 2201 to 2216.

  As described above, since the input to one of the input terminals of the OR circuits 2201 to 2216 is at a high level, the OR is input regardless of whether the signal input to the other input terminal is at a high level or a low level. Signals SO1 to SO16 output from the circuits 2201 to 2216 are all at a high level. Even though the output control signal SC is input, the random R cannot be read from the random value storage circuit 531. That is, when the latch signal SL is input, the random value storage circuit 531 cannot receive the output control signal SC. When the 16-bit random number circuit 503b is used, the value “65535” as the random number value may be used. In this case, even if the game control microcomputer 560 reads the value “65535”, it cannot determine whether the value is a random number or is unreadable. Therefore, in the determination table for each jackpot determination shown in FIG. 39, when the random R is “65535”, it may be set to determine “lost” in advance.

  In addition, when the output control signal SC is input from the CPU 56 before the latch signal SL is input from the latch signal generation circuit 533, the input to one input terminal of the AND circuit 201 is at a low level. Even if the latch signal SL is input while the control signal SC is being input (timing T5 in the example shown in FIG. 20), the signal SR output from the output terminal of the AND circuit 201 remains at the low level. It becomes. Therefore, the signal SR input to the clock terminals Clk1 to Clk16 of the flip-flop circuits 2101 to 2116 does not rise from the low level to the high level, and the random R bit data R1 to R16 stored in the flip-flop circuits 2101 to 2116. Although the latch signal SL is input, the stored random number is not updated. That is, when the output control signal SC is input, the random value storage circuit 531 cannot receive the latch signal SL.

  The inverting circuit 532 generates the inverted clock signal SI2 in which the polarity of the clock signal is inverted by inverting the signal level in the random number generating clock signal SI1 input from the clock signal output circuit 524. Further, the inverting circuit 532 outputs the generated inverted clock signal SI2 to the latch signal generating circuit 533.

  Note that the random number circuit 503 may include a delay circuit instead of the inverting circuit 532. In this case, the delay circuit delays the random number generation clock signal SI1 input from the clock signal output circuit 524, thereby generating a delayed clock signal obtained by delaying the clock signal. The delay circuit outputs the generated delayed clock signal to the latch signal generation circuit 533. Therefore, the latch signal generation circuit 533 outputs a latch signal to the random value storage circuit 531 in synchronization with the delayed clock signal obtained by delaying the random number generation clock signal SI1.

  The latch signal generation circuit 533 is configured using a selector, a flip-flop circuit, and the like. The latch signal generation circuit 533 receives the random number read signal from the random number read signal output circuit 526 and the inverted clock signal SI2 from the inversion circuit 532, and latch signal for storing the random value in the random value storage circuit 531. SL is output. The latch signal generation circuit 533 outputs the latch signal SL in accordance with the random value update method designated by the random number update method selection signal from the random number update method selection signal output circuit 527. In this case, when the first random number update method selection signal output circuit 527 receives the first random number update method selection signal output circuit 527, the latch signal generation circuit 533 selects the inverted clock signal SI2 output from the inversion circuit 532, and the latch signal It outputs to the random value storage circuit 531 as SL. On the other hand, when the second random number update method selection signal is input from the random number update method selection signal output circuit 527, the latch signal generation circuit 533 inverts the random value read signal output from the random value read signal output circuit 526. In synchronization with the rising edge of the inverted clock signal SI2 output from the circuit 532, the latch signal SL is output to the random value storage circuit 531.

  The timer circuit 534 inputs a winning detection signal SS indicating that a winning of a game ball to the starting port 14 has been detected from the starting port switch 14a. The timer circuit 534 measures the time during which the winning detection signal SS is continuously input from the start port switch 14a. Then, when the measurement time reaches a predetermined period (for example, 3 ms), the timer circuit 534 writes the random number value capture data “01h” in the random value capture register 539 of the random value read signal output circuit 526. For example, the timer circuit 534 is configured by an up counter or a down counter that is activated in response to the input of a high level signal. The timer circuit 534 receives the reference clock signal CLK sequentially input from the clock circuit 501 while the input from the start port switch 14a is at a high level (that is, while the winning detection signal SS is continuously input). Count up or down. Then, when the count value to be counted up or down reaches a value corresponding to 3 ms, the timer circuit 534 determines that the winning detection signal SS is input from the start port switch 14a, and stores the random number value capture data “01h”. Write to the random value fetch register 539.

  Next, the configuration of the serial communication circuit 505 will be described. The serial communication circuit 505 is a data format using a full-duplex method, an asynchronous method, and standard NRZ (non-return zero) encoding, and is a micro of each control board (for example, the payout control board 37 and the sound / lamp control board 80b). Serial communication with the computer. The serial communication circuit 505 includes a transmission unit that transmits various data (for example, a prize ball number command and an effect control command) to the microcomputer of each control board, and various data (for example, a prize ball ACK) from the microcomputer of each control board. Command).

  FIG. 21 is a block diagram illustrating a configuration example of the transmission unit of the serial communication circuit 505. FIG. 22 is a block diagram illustrating a configuration example of a receiving unit of the serial communication circuit 505. The serial communication circuit 505 includes a baud rate register 702, a baud rate generation circuit 703, two status registers 705 and 706, three control registers 707, 708, and 709, a transmission data register 710, a reception data register 711, a transmission shift register 712, and a reception Shift register 713, interrupt control circuit 714, transmission format / parity generation circuit 715, and reception format / parity check circuit 716. As shown in FIG. 21, the transmission unit of the serial communication circuit 505 includes a baud rate register 702, a baud rate generation circuit 703, a status register A 705, control registers 707, 708, and 709, and a transmission data register 710. , A transmission shift register 712, an interrupt control circuit 714, and a transmission format / parity generation circuit 715. As shown in FIG. 22, the receiving unit of the serial communication circuit 505 includes a baud rate register 702, a baud rate generation circuit 703, status registers 705 and 706, control registers 707, 708, and 709, received data, among these components. The register 711, the reception shift register 713, the interrupt control circuit 714, and the reception format / parity check circuit 716 are configured.

  In the serial communication circuit 505, the transmission unit and the reception unit are actually configured using a common circuit. As described above, the serial communication circuit 505 functions as a transmission circuit or a reception circuit by properly using each component of the serial communication circuit 505.

  First, the data format of data transmitted and received by the serial communication circuit 505 with the microcomputer mounted on each control board will be described. FIG. 23 is an explanatory diagram showing an example of a data format of data transmitted and received by the serial communication 505 to and from the microcomputer mounted on each control board. As shown in FIG. 23, the data format of data transmitted and received by the serial communication circuit 505 is configured with a start bit, data, and stop bits as one frame. Further, the data length of data transmitted and received by the serial communication circuit 505 can be set to either 8 bits or 9 bits by performing initial setting in a serial communication circuit setting process described later. FIG. 23A shows an example of a data format when the data length is set to 8 bits. FIG. 23B shows an example of a data format when the data length is set to 9 bits.

  As shown in FIG. 23, the data format of data transmitted and received by the serial communication circuit 505 is a start bit (logic “0”) indicating the start of one frame after an idle line of high level (logic “1”). ")including. The data format includes 8-bit or 9-bit transmission / reception data after the start bit. The data format includes a stop bit (logic “1”) indicating the end of one frame after the transmission / reception data.

  The serial communication circuit 505 transmits / receives data first from the least significant bit (bit 0) of the transmission / reception data according to the data format shown in FIG. Further, if initial setting is performed in a serial communication circuit setting process described later, it is possible to set so that a parity bit is added to transmission / reception data. When the setting is such that a parity bit is added, the most significant bit of the transmission / reception data is used as a parity bit (odd parity or even parity). For example, when the data length is set to 8 bits, bit 7 of transmission / reception data is used as a parity bit. For example, when the data length is set to 9 bits, bit 8 of transmission / reception data is used as a parity bit.

  The baud rate generation circuit 703 generates a baud rate used by the serial communication circuit 505 based on a clock signal output from the clock circuit 501 and a setting value (also referred to as a baud rate setting value) set in the baud rate register 702. In this case, the baud rate generation circuit 703 obtains the baud rate using a predetermined calculation formula based on the clock signal and the baud rate setting value. For example, the baud rate generation circuit 703 obtains the baud rate used by the serial communication circuit 505 using equation (1).

Baud rate = clock frequency / (baud rate set value x 16) Equation (1)

  FIG. 24 is an explanatory diagram showing an example of the baud rate register 702. The baud rate register 702 is a register that sets a predetermined setting value for designating a baud rate value generated by the baud rate generation circuit 703. For example, it is assumed that the baud rate register 702 obtains the baud rate using the equation (1) and the clock frequency is 3 MHz. In this case, if the desired target baud rate is 1200 bps, the setting value “156” is set in the baud rate register 702. Then, the baud rate generation circuit 703 generates the baud rate “1201.92 bps” using the equation (1) based on the clock frequency “3 MHz” and the baud rate set value “156”. The baud rate register 702 is a 16-bit register, and an initial value is set to “0 (= 00h)”. The baud rate register 702 is configured such that bits 0 to 12 can be written and read. Further, the baud rate register 702 is configured such that bits 13 to 15 cannot be written or read. Therefore, even if control is performed to write values to bits 13 to 15 of the baud rate register 702, the values are invalid and all the values read from bits 13 to 15 are “0 (= 000b)”.

  FIG. 25A is an explanatory diagram illustrating an example of the control register A707. The control register A 707 is a register for setting the communication format of the serial communication circuit 505. In this embodiment, the communication format of the serial communication circuit 505 is set by setting the value of each bit of the control register A707. In the control register A707, communication format setting data for setting a communication format such as a data format of transmission / reception data and various communication methods is set. As shown in FIG. 25A, the control register A707 is an 8-bit register, and its initial value is set to “0 (= 00h)”. Control register A 707 is configured such that bits 0 to 4 can be written and read. Control register A 707 is configured such that bits 5 to 7 cannot be written or read. Therefore, even if a control for writing a value to bits 5 to 7 of the control register A707 is performed, it is invalid, and all values read from bits 5 to 7 are “0 (= 000b)”.

  FIG. 25B is an explanatory diagram of an example of communication format setting data set in the control register A707. As shown in FIG. 25B, setting data for setting the data length of data to be transmitted and received is set in bit 4 (bit name “M”) of the control register A707. As shown in FIG. 25B, by setting bit 4 to “0”, the data length of the transmission / reception data is set to 8 bits. Also, by setting bit 4 to “1”, the data length of the transmission / reception data is set to 9 bits.

  In bit 3 (bit name “WAKE”) of the control register A707, setting data for setting a wake-up method for waking up the receiver circuit (the receiving unit of the serial communication circuit 505) in the standby state. Is set. As shown in FIG. 25 (B), by setting bit 3 to “0”, an idle line wakeup method is set which wakes up when an idle line is recognized. In addition, by setting bit 3 to “1”, an address mark wakeup method for wakeup by recognizing a predetermined address mark is set.

  In bit 2 (bit name “ILT”) of the control register A707, setting data for selecting an idle line detection method of received data is set. As shown in FIG. 25B, by setting bit 2 to “0”, a detection method for detecting an idle line after the start bit included in the received data is set. In addition, by setting bit 2 to “1”, a detection method for detecting an idle line after a stop bit included in received data is set.

  Setting data for setting whether or not to use the parity function is set in bit 1 (bit name “PE”) of the control register A707. As shown in FIG. 25B, the parity function is not used by setting bit 1 to “0”. Further, by setting bit 1 to “1”, the parity function is set to be used.

  Setting data for setting the type of parity when the parity function is used is set in bit 0 (bit name “PT”) of the control register A707. As shown in FIG. 25B, by setting bit 0 to “0”, even parity is set as the parity type. Also, by setting bit 0 to “1”, odd parity is set as the parity type.

  FIG. 26A is an explanatory diagram illustrating an example of the control register B708. The control register B 708 is a register for setting whether to permit an interrupt request from the serial communication circuit 505. In this embodiment, whether the interrupt request from the serial communication circuit 505 is permitted or prohibited is set by setting the value of each bit of the control register B708. In the control register B708, interrupt request setting data indicating whether or not various interrupt requests are permitted is mainly set. In addition to the interrupt request setting data, setting data for performing various settings of the serial communication circuit 505 is also set in the control register B708. As shown in FIG. 26A, the control register B 708 is an 8-bit register, and the initial value is set to “0 (= 00h)”. Control register B 708 is configured such that bits 0 to 7 can be written and read.

  FIG. 26B is an explanatory diagram showing an example of interrupt request setting data set in the control register B708. As shown in FIG. 26 (B), setting data indicating whether or not a transmission interrupt request, which is an interrupt request to be performed at the time of data transmission, is permitted is set in bit 7 (bit name “TIE”) of the control register B708. Is done. As shown in FIG. 26B, by setting bit 7 to “0”, the transmission interrupt request is set to be prohibited. Also, by setting bit 7 to “1”, the transmission interrupt request is set to be permitted.

  Bit 6 (bit name “TCIE”) of the control register B708 is set with setting data indicating whether or not to permit a transmission completion interrupt request, which is an interrupt request to be made when data transmission is completed. As shown in FIG. 26B, by setting bit 6 to “0”, the transmission completion interrupt request is set to be prohibited. Further, by setting bit 6 to “1”, the transmission completion interrupt request is set to be permitted.

  Bit 5 (bit name “RIE”) of the control register B 708 is set with setting data indicating whether or not a reception interrupt request, which is an interrupt request when data is received, is permitted. As shown in FIG. 26B, the reception interrupt request is set to be prohibited by setting bit 5 to “0”. Also, by setting bit 5 to “1”, the reception interrupt request is set to be permitted.

  Bit 4 (bit name “ILIE”) of the control register B 708 is set with setting data indicating whether or not to allow an idle line interrupt request, which is an interrupt request when an idle line of received data is detected. As shown in FIG. 26B, by setting bit 4 to “0”, an idle line interrupt request is set to be prohibited. Further, by setting bit 4 to “1”, it is set to permit an idle line interrupt request.

  In bit 3 (bit name “TE”) of the control register B708, setting data indicating whether to use the transmission circuit (the transmission unit of the serial communication circuit 505) is set. As shown in FIG. 26B, by setting bit 3 to “0”, the transmission circuit is set not to be used. Further, by setting bit 3 to “1”, the transmission circuit is set to be used.

  Setting data indicating whether or not to use the receiving circuit is set in bit 2 (bit name “RE”) of the control register B708. As shown in FIG. 26B, by setting bit 2 to “0”, the receiving circuit is set not to be used. Further, by setting bit 2 to “1”, the receiving circuit is set to be used.

  Setting data indicating whether or not to use the wakeup function of the receiving circuit is set in bit 1 (bit name “RWU”) of the control register B708. As shown in FIG. 26B, by setting bit 1 to “0”, the wakeup function is set not to be used. Further, by setting bit 1 to “1”, the wakeup function is set to be used.

  Setting data indicating whether or not to use a predetermined break code transmission function is set in bit 0 (bit name “SBK”) of the control register B708. As shown in FIG. 26B, by setting bit 1 to “0”, the break code transmission function is set not to be used. Also, by setting bit 1 to “1”, the break code transmission function is set to be used. When bit 1 is set to “1”, the serial communication circuit 505 mounts a break code (for example, a signal continuously including “0”) on the control board (the payout control board 37 and the sound / lamp control board 80b). Send to microcomputer.

  FIG. 27A is an explanatory diagram illustrating an example of the status register A705. The status register A 705 is a register for confirming various statuses of the serial communication circuit 505. In this embodiment, the CPU 56 can confirm various statuses of the serial communication circuit 505 by confirming the value of each bit of the status register A 705. As shown in FIG. 27A, the status register A705 is an 8-bit register, and the initial value is set to “0 (= 00h)”. In addition, the status register A705 is configured so that bits 0 to 7 can only be read. Therefore, even if control is performed to write a value to bits 0 to 7 of the status register A705, it is invalidated.

  In the present embodiment, as will be described later, when transmission data is not stored in the transmission data register 710 (transmission data empty) or transmission of transmission data stored in the transmission shift register 712 is completed, interrupt control is performed. Circuit 714 sets the corresponding bit in status register A705. Then, the CPU 56 reads the value of each bit set in the status register A705.

  FIG. 27B is a diagram showing an example of status confirmation data stored in the status register A705. As shown in FIG. 27 (B), transmission data indicating that transmission data is not stored in transmission data register 710 (transmission data empty) in bit 7 (bit name “TDRE”) of status register A705. Stores an empty flag. As shown in FIG. 27B, when “0” is stored in bit 7, the transmission data is not yet transferred from the transmission data register 710 to the transmission shift register 712, and transmitted to the transmission data register 710. Indicates that the data is still stored. When “1” is stored in bit 7, the transmission data is transferred from the transmission data register 710 to the transmission shift register 712, and there is no transmission data in the transmission data register 710 (transmission data empty). ).

  Bit 6 (bit name “TC”) of the status register A 705 stores a transmission completion flag indicating that transmission of transmission data from the serial communication circuit 505 has been completed. As shown in FIG. 27B, when “0” is stored in bit 6, the transmission data stored in the transmission shift register 712 is being transmitted, and the transmission data from the serial communication circuit 505 is not transmitted. Indicates that transmission has not been completed. Further, when “1” is stored in bit 6, the transmission data stored in the transmission shift register 712 has been transferred, and transmission of transmission data from the serial communication circuit 505 has been completed. It shows that.

  Note that the transmission of the transmission data is completed, and the game control microcomputer 560 waits for a reception confirmation signal from the transmission destination microcomputer. In this embodiment, when a transmission interrupt is set as will be described later, the serial communication circuit 505 sets the bit 6 of the status register A 705 to “1” and confirms reception when detecting the completion of transmission of transmission data. An interrupt request (referred to as an interrupt request during transmission) is made to the CPU 56 as a signal waiting state.

  Bit 5 (bit name “RDRF”) of status register A 705 stores a reception data full flag indicating that reception data is stored in reception data register 711 (reception data full). As shown in FIG. 27B, when “0” is stored in bit 5, it indicates that the reception data register 711 contains no reception data. When “1” is stored in bit 5, the value of the reception shift register 713 is transferred to the reception data register 711, and reception data is stored in the reception data register 711 (reception data Full).

  When the reception data is stored in the reception data register 711, the CPU 56 is ready to perform reception processing by reading the reception data from the reception data register 711. In this embodiment, when the serial communication circuit 505 detects that the received data is full, the bit 5 of the status register A 705 is set to “1” and an interrupt request (interrupt upon reception) is made to the CPU 56 that reception processing is possible. Request).

  Bit 4 (bit name “IDLE”) of the status register A705 stores an idle line detection flag indicating that the reception circuit has detected an idle line. As shown in FIG. 27B, when “0” is stored in bit 4, it indicates that the receiving unit of the serial communication circuit 505 has not detected an idle line. When “1” is stored in bit 4, it indicates that the receiving unit of the serial communication circuit 505 has detected an idle line.

  In bit 3 (bit name “OR”) of the status register A 705, the reception shift register 713 has received the next data before the CPU 56 reads the reception data stored in the reception data register 711 (overload). An overrun flag indicating (run) is stored. As shown in FIG. 27B, when “0” is stored in bit 3, it indicates that the receiving circuit has not detected an overrun. When “1” is stored in bit 3, it indicates that the receiving circuit has detected an overrun.

  If an overrun occurs, the next received data is stored in the reception shift register 713 before the received data in the received data register 711 is read, so that the received data is overwritten and the CPU 56 receives the received data. It cannot be read correctly. Therefore, communication with the microcomputer mounted on each control board cannot be performed correctly, causing the CPU 56 to malfunction. In this embodiment, when the serial communication circuit 505 detects an overrun, the serial communication circuit 505 sets bit 3 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 on the assumption that an error has occurred during communication.

  Bit 2 (bit name “NF”) of the status register A705 stores a noise error flag indicating that noise has been detected in the received data. As shown in FIG. 27B, when “0” is stored in bit 2, it indicates that the receiving circuit is not detecting noise in the received data. When “1” is stored in bit 2, it indicates that the receiving circuit has detected noise in the received data.

  For example, when detecting each bit of the received data, the serial communication circuit 505 detects “1” or “0” having a predetermined bit length by using the baud rate generated by the baud rate generation circuit 703. In this case, when the detected length of “1” or “0” is less than the predetermined bit length, the serial communication circuit 505 detects a noise error as noise generated in the received data. When a noise error occurs, there is a high possibility that correct received data cannot be received due to noise, which causes the CPU 56 to malfunction. In this embodiment, when the serial communication circuit 505 detects a noise error, the serial communication circuit 505 sets bit 2 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 on the assumption that an error has occurred during communication.

  Bit 1 (bit name “FE”) of the status register A 705 indicates that it is detected that the position of the stop bit of the received data is “0” (originally, the stop bit is “1”) (framing error). A framing error flag is stored. As shown in FIG. 27B, when “0” is stored in bit 1, it indicates that the receiving circuit is not detecting a framing error in the received data. When “1” is stored in bit 1, it indicates that the receiving circuit has detected a framing error.

  When a framing error occurs, it is in a state where the stop bit of the received data has not been correctly received, and therefore there is a high possibility that correct received data cannot be received, causing the CPU 56 to malfunction. In this embodiment, when detecting a framing error, the serial communication circuit 505 sets bit 1 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 as an error has occurred during communication.

  Bit 0 (bit name “PF”) of status register A 705 has a parity error flag indicating that the parity value obtained from the received data does not match the parity value included in the received data (parity error). Is stored. As shown in FIG. 27B, when “0” is stored in bit 0, it indicates that the receiving circuit has not detected a parity error in the received data. Further, when “1” is stored in bit 0, it indicates that the receiving circuit has detected a parity error.

  When a parity error occurs, it is in a state where each data bit or parity bit of the received data has not been correctly received, so there is a high possibility that correct received data cannot be received, causing the CPU 56 to malfunction. In this embodiment, when the serial communication circuit 505 detects a parity error, the serial communication circuit 505 sets bit 0 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 on the assumption that an error has occurred during communication.

  FIG. 28A is an explanatory diagram showing an example of the status register B706. The status register B 706 is a register for confirming the reception state (reception status) of the serial communication circuit 505. In this embodiment, the CPU 56 can confirm the reception status of the serial communication circuit 505 by confirming the value of the bit of the status register B 706. As shown in FIG. 28B, the status register B 706 is an 8-bit register, and the initial value is set to “0 (= 00h)”. Further, the status register B 706 is configured so that bit 0 can only be read. Therefore, even if control is performed to write a value to bit 0 of status register A 705, it is invalid. Status register B 706 is configured such that bits 1 to 7 cannot be written or read. Therefore, even if control is performed to write a value to bits 1 to 7 of the status register A 705, the value is invalid and all the values read from bits 1 to 7 are “0 (= 0000b)”.

  FIG. 28B is a diagram showing an example of status confirmation data stored in the status register B706. As shown in FIG. 28B, a reception active flag indicating that the reception circuit is receiving reception data (reception active) is stored in bit 0 (bit name “RAF”) of the status register B706. . As shown in FIG. 28B, when “0” is stored in bit 0, it indicates that the reception circuit is not receiving reception data. Further, when “1” is stored in bit 0, it indicates that the reception circuit is receiving reception data. When the serial communication circuit 505 detects the start bit, it assumes that reception of received data has started, and sets bit 0 of the status register B 706 to “1”.

  FIG. 29A is an explanatory diagram illustrating an example of the control register C709. The control register C709 is a register for setting whether to permit an interrupt request when a communication error occurs in the serial communication circuit 505. In this embodiment, by setting the value of each bit of the control register C709, it is set whether the interrupt request at the time of communication from the serial communication circuit 505 is permitted or prohibited. In the control register C709, error interrupt request setting data indicating whether or not various interrupt requests at the time of a communication error are permitted is mainly set. In addition to the error interrupt request setting data, the control register C709 stores 9th bit data when the data length is set to 9 bits. Various settings of the serial communication circuit 505 are also set. As shown in FIG. 29A, the control register C709 is an 8-bit register, and the initial value is set to “0 (= 00h)”. The control register C709 is configured such that bits 0 to 3 and bits 6 and 7 can be written and read. In addition, the control register C709 is configured such that bits 4 and 5 cannot be written or read. Therefore, even if control is performed to write a value to bits 4 and 5 of the control register C709, it is invalid, and all the values read from bits 4 and 5 are “0 (= 0000b)”.

  FIG. 29B is an explanatory diagram showing an example of error interrupt request setting data set in the control register C709. As shown in FIG. 29B, the bit 7 (bit name “R8”) of the control register C709 stores the 9th bit of the received data when the data length is set to 9 bits. Further, bit 6 (bit name “T8”) of the control register C709 stores the 9th bit data of the transmission data when the data length is set to 9 bits.

  In bit 3 (bit name “ORIE”) of the control register C709, setting data indicating whether or not to permit an overrun flag interrupt request, which is an interrupt request to be performed when an overrun is detected, is set. As shown in FIG. 29B, by setting bit 3 to “0”, the overrun flag interrupt request is set to be prohibited. Further, by setting bit 3 to “1”, the overrun flag interrupt request is set to be permitted.

  Bit 2 (bit name “NEIE”) of the control register C709 is set with setting data indicating whether or not to permit a noise error flag interrupt request, which is an interrupt request to be performed when a noise error is detected. As shown in FIG. 29B, by setting bit 2 to “0”, the noise error flag interrupt request is set to be prohibited. Also, by setting bit 2 to “1”, the noise error flag interrupt request is set to be permitted.

  Bit 1 (bit name “FEIE”) of the control register C709 is set with setting data indicating whether or not to permit a framing error flag interrupt request, which is an interrupt request to be performed when a framing error is detected. As shown in FIG. 29B, by setting bit 1 to “0”, the framing error flag interrupt request is set to be prohibited. Further, by setting bit 1 to “1”, the framing error flag interrupt request is set to be permitted.

  Bit 0 (bit name “PEIE”) of the control register C709 is set with setting data indicating whether or not to permit a parity error flag interrupt request, which is an interrupt request to be performed when a parity error is detected. As shown in FIG. 29B, by setting bit 0 to “0”, the parity error flag interrupt request is set to be prohibited. Also, by setting bit 0 to “1”, the parity error flag interrupt request is set to be permitted.

  FIG. 30 is an explanatory diagram illustrating an example of a data register included in the serial communication circuit 505. The data register 701 is a register that stores data transmitted and received by the serial communication circuit 505. As shown in FIG. 30, the data register is an 8-bit register, and the initial value is set to “0 (= 00h)”. Data register 701 is configured such that bits 0 to 7 can be written and read.

  In this embodiment, when the serial communication circuit 505 transmits transmission data, the data register is used as the transmission data register 710. When the data length is set to 9 bits, bit 6 of the data register and control register C709 is used as the transmission data register 710. In this case, bits 0 to 7 of the data register are used as bits 0 to 7 of the transmission data register 710, and bit 6 of the control register C709 is used as bit 8 of the transmission data register 710.

  When the serial communication circuit 505 receives received data, the data register is used as the received data register 711. When the data length is set to 9 bits, bit 7 of the data register and control register C709 is used as the reception data register 711. In this case, bit 0 to bit 7 of the data register are used as bit 0 to bit 7 of the reception data register 711, and bit 7 of the control register C 709 is used as bit 8 of the reception data register 711.

  The interrupt control circuit 714 makes various interrupt requests to the CPU 56. In this embodiment, when the bit 6 (TCIE) of the control register B 708 is set to “1”, the interrupt control circuit 714 notifies the CPU 56 when transmission of transmission data to the transmission data register 710 is completed. In addition to outputting an interrupt signal, an interrupt request is made by setting bit 6 (TC) of status register A705 to “1”. The interrupt control circuit 714 may output a different interrupt signal for each interrupt factor to the CPU 56 instead of making the interrupt factor identifiable by the set value of the bit of the status register A705.

  In addition, when bit 5 (RIE) of the control register B 708 is set to “1”, the interrupt control circuit 714 enters a state where reception data is stored in the reception data register 711 (when reception data full is detected). ), An interrupt signal is output to the CPU 56, and an interrupt request is made by setting "1" to bit 5 (RDRF) of the status register A705.

  Further, when any of the bits 0 to 3 of the control register C709 is set to “1”, the interrupt control circuit 714 outputs an interrupt signal to the CPU 56 and also indicates the type of communication error. In response to this, an interrupt request is made by setting "1" to bits 0 to 3 of the status register A705. For example, if bit 3 (ORIE) of the control register C709 is set to “1”, “1” is set to bit 3 (OR) of the status register A705 when an overrun is detected and an interrupt request is made. To do. For example, when bit 2 (NEIE) of the control register C709 is set to “1”, when a noise error is detected and an interrupt request is made, “1” is set to bit 2 (NF) of the status register A705. Set. For example, when bit 1 (FEIE) of the control register C709 is set to “1”, when a framing error is detected and an interrupt request is made, “1” is set to bit 1 (FE) of the status register A705. Set. For example, when bit 0 (PEIE) of the control register C709 is set to “1”, when a parity error is detected and an interrupt request is made, “1” is set to bit 0 (PF) of the status register A705. Set. When a plurality of communication errors are detected, the interrupt control circuit 714 makes an interrupt request based on the plurality of communication errors and sets the corresponding bits of the status register A705 to “1”.

  The transmission format / parity generation circuit 715 generates a data format of transmission data. In this embodiment, the transmission format / parity generation circuit 715 generates a data format by adding a start bit and a stop bit to the transmission data stored in the transmission data register 710 and transfers the data format to the transmission shift register 712. If bit 1 (PE) of control register A707 is set to “1” and the parity function is set to be used, the transmission format / parity generation circuit 715 adds a parity bit to the transmission data. Generate a data format.

  The reception format / parity check circuit 716 detects the data format of the reception data. In this embodiment, the reception format / parity check circuit 716 detects the start bit and stop bit from the reception data stored in the reception shift register 713, detects the data portion included in the reception data, and receives the reception data register. Forward to 711. If bit 1 (PE) of the control register A707 is set to “1” and the parity function is set to be used, the reception format / parity check circuit 716 obtains the parity of the reception data and receives the reception data. It is detected whether or not it matches the parity included in. If the obtained value does not match the parity included in the received data, the reception format / parity check circuit 716 detects a parity error. If it is set in the serial communication circuit setting process to be described later that an interrupt request at the time of a communication error is permitted, the interrupt control circuit 714, when detecting a parity error, requests the CPU 56 to interrupt the occurrence of the communication error as an interrupt cause. I do.

  FIG. 31 is an explanatory diagram showing an example of an address map of a storage area in the game control microcomputer 560. As shown in FIG. 31, the area from address 0000h to 1FFFh in the storage area of the game control microcomputer 560 is allocated to the ROM 54. An area from addresses 7E00h to 7FFFh is allocated to the RAM 55. Further, the area from the address FD00h to the address FE00h is allocated to a built-in register such as the random number maximum value setting register 535.

  Further, as shown in FIG. 31, the area of addresses 0000h to 1FFFh allocated to the ROM 54 includes a user program area and a user program management area. A program (user program) 550 created in advance by a user (for example, a game machine manufacturer) is stored in the user program area in the area of addresses 0000h to 1F7Fh. Further, data (user program execution data) necessary for the CPU 56 to execute the user program 550 is stored in the user program management area in the area of addresses 1F80h to 1FFFh. Of the areas 7E00h to 7FFFh allocated to the RAM 55, the areas 7E00h to 7EFFh are unused areas, and the areas 7F00h to 7FFFh are used as work areas.

  FIG. 32 is an explanatory diagram showing an example of an address map in the user program management area. As shown in FIG. 32, in the area of address 1F97h, the initial value changing method selected by the user among the initial value changing methods which are methods for changing the initial value input to the counter 521 of the random number circuit 503 is shown. The initial value change method setting data for designating is stored. Further, in the areas 1F98h and 1F99h, RAM address data for specifying an address in the RAM 55 (designated RAM address) designated in advance by the user among addresses 7F00h to 7FFFh allocated to the RAM 55 is stored. The In this case, of the values indicating the designated RAM address, the lower value of the designated RAM address is stored in the 1F98h address, and the higher value of the designated RAM address is stored in the 1F99h address.

  FIG. 33 is an explanatory diagram of an example of initial value change method setting data. As shown in FIG. 33, the initial value change data is composed of 8-bit data. The initial value change data “00h” is data specifying that the initial value is not changed as the initial value change method. In this embodiment, when the initial value change data “00h” is set, the counter 521 of the random number circuit 503 updates the count value from a predetermined initial value “0” to a predetermined final value. Become. Further, the initial value change data “01h” is data specifying that the initial value input to the counter 521 is changed to a value based on an ID number for identifying the game control microcomputer 560 as an initial value change method. It is. In this embodiment, when the initial value change data “01h” is set, the initial value of the counter value updated by the counter 521 is changed from “0” to a value based on the ID number. The count value is updated from the initial value to a predetermined final value.

  The user program 550 stored in the user program area will be described. FIG. 34 is an explanatory diagram showing a configuration example of the user program 550. As shown in FIG. 34, in this embodiment, the user program 550 includes a random number circuit setting program 551 composed of a plurality of types of program modules, a display result determination program 552, a count value permutation change program 554, A numerical value update program 555, a serial communication circuit setting program 556, and an interrupt priority setting program 557 are included.

  The random number circuit setting program 551 is a program for executing a random number circuit setting process for performing initial setting for causing the random number circuit 503 to update the value of the random R. That is, the CPU 56 functions as random number circuit initial setting means by executing processing according to the random number circuit setting program 551.

  FIG. 35 is an explanatory diagram showing a configuration example of the random number circuit setting program 551. As shown in FIG. 35, the random number circuit setting program 551 includes a random number maximum value setting module 551a, a random number update method selection module 551b, a cycle setting module 551c, a random number circuit activation module 551d, as a plurality of types of program modules. An initial value changing module 551e and a random number circuit selecting module 551f are included.

  The random number maximum value setting module 551a is a program module for causing the random number circuit 503 to set the maximum value of random R preset by a user (for example, a game machine manufacturer). The CPU 56 executes processing in accordance with the random number maximum value setting module 551a, thereby writing random number maximum value setting data for specifying the maximum value of the random R preset by the user in the random number maximum value setting register 535. By doing so, the CPU 56 sets the maximum value of the random R preset by the user in the random number circuit 503. For example, when “255” is set in advance as the maximum value of the random R by the user, the CPU 56 writes the random number maximum value setting data “00FFh” in the random number maximum value setting register 535 and the random R maximum value “255”. Is set in the random number circuit 503.

  The random number update method selection module 551b is a program module for causing the random number circuit 503 to set the random number update method (first random number update method or second random number update method) selected by the user. The CPU 56 writes the random number update method selection data “01b” or “10b” designating the random number update method selected by the user in the random number update method selection register 540 by executing the process according to the random number update method selection module 551b. By doing so, the CPU 56 sets the random number update method selected by the user in the random number circuit 503. Therefore, the game control microcomputer 560 has a function of selecting either the first random number update method or the second random number update method as the random number update method used by the random number circuit 503 for the random number update.

  The cycle setting module 551c is a program for causing the random number circuit 503 to set the cycle of the internal clock signal preset by the user (that is, the cycle in which the clock signal output circuit 524 outputs the clock signal to the selector 528 and the inverting circuit 532). It is a module. The CPU 56 writes the period setting data for designating the period of the internal clock signal preset by the user in the period setting register 537 by executing the process according to the period setting module 551c. By doing so, the CPU 56 sets the cycle of the internal clock signal preset by the user in the random number circuit 503. For example, when the cycle of the internal clock signal is set in advance as “system clock signal cycle × 128 × 16” by the user, the CPU 56 writes the cycle setting data “0Fh” in the cycle setting register 537 and sets the internal clock signal The period “system clock signal period × 128 × 16” is set in the random number circuit 503.

  The random number circuit activation module 551d is a program module for activating the random number circuit 503. The CPU 56 activates the random number circuit 503 by writing the random number circuit activation data “80h” to the random number circuit activation register 541 by executing processing according to the random number circuit activation module 551d.

  The initial value change module 551e is a program module for changing the initial value of the count value updated by the counter 521. The CPU 56 functions as an initial value changing unit by executing processing according to the initial value changing module 551e. The CPU 56 executes the initial value changing module 551e to change the initial value of the count value updated by the counter 521 by the initial value changing method selected by the user. By doing so, the CPU 56 has a function of selecting an initial value changing method.

  In this embodiment, when the initial value change method setting data “01h” is stored in the area 1F97h in the user program management area, the CPU 56 sets the initial value of the count value for each game control microcomputer 560. The value is changed to a value calculated based on the assigned unique ID number.

  For example, the game control microcomputer 560 associates, in a predetermined storage area of the ROM 54, the ID number of the game control microcomputer 560 with a calculated value obtained by performing a predetermined calculation based on the ID number. I remember it. In this case, for example, if the ID number of the game control microcomputer 560 is “100”, the calculated value “150” obtained by adding the predetermined value “50” to the ID number “100” is set in advance as the ID number. Are stored in association with each other. Further, for example, the calculated value “50” obtained by subtracting the predetermined value “50” from the ID number “100” is stored in advance in association with the ID number. Further, for example, only a predetermined value may be stored in advance in association with the ID number. Then, the CPU 56 of the game control microcomputer 560 adds a value “150” obtained by adding an ID number (for example, “100”) to a predetermined value (for example, “50”) stored in advance, and sets the initial count value. The CPU 56 may also use a value “50” obtained by subtracting a predetermined value (eg, “50”) stored in advance from the ID number (eg, “100”) as an initial value of the count value. The game control microcomputer 560 may store the ID number of the game control microcomputer 560 in a predetermined storage area of the ROM 54 as long as data writing is prohibited in the storage area. Alternatively, it may be stored in a predetermined storage area of the RAM 55.

  When the initial value change method setting data “01h” is stored, the CPU 56 changes the initial value of the count value to the calculated value based on the ID number stored in advance. By doing so, the randomness of the random number generated by the random number circuit 503 can be further improved, and the initial value of the random number can be made difficult to recognize only by looking at the ID number of the game control microcomputer 560. . Therefore, it is possible to more reliably prevent the transition condition to the big hit state from being illegally established by an action such as generating a captured signal using a radio signal to the gaming machine, and improving security. Can be improved.

  For example, when initial value change method setting data “01h” is stored, the CPU 56 calculates the ID number of the game control microcomputer 560 and a predetermined value (for example, adds the predetermined value to the ID number). The initial value of the count value is changed to the calculated value obtained. In this case, for example, the CPU 56 may calculate a value that is randomly changed using a random number as an ID number, thereby randomly updating a value used for the calculation and obtaining an initial value. By doing so, the randomness of the random numbers generated by the random number circuit 503 can be further improved.

  The random number circuit selection module 551f is a program module for setting a random number circuit to be used at the time of executing the timer interrupt process from among the random number circuits 503 built in the game control microcomputer 560. The CPU 56 executes a process according to the random number circuit selection module 551f, so that any of the two random number circuits (12-bit random number circuit 503a and 16-bit random number circuit 503b) built in the game control microcomputer 560 is selected. Set whether to use when executing timer interrupt processing. For example, the CPU 56 uses a 12-bit random number circuit 503a or 16-bit as a random number circuit used when executing the timer interrupt process according to a predetermined set value (a value set in advance by the user) stored in a predetermined storage area of the ROM 54. The random number circuit 503b is set.

  Note that both the 12-bit random number circuit 503a and the 16-bit random number circuit 503b may be set as random number circuits used when the timer interrupt process is executed. In this case, for example, the CPU 56 may determine the variation pattern based on the random number generated by the 12-bit random number circuit 503a and perform the jackpot determination based on the random number generated by the 16-bit random number circuit 503b. In this embodiment, the random value storage circuit 531 exists in each of the 12-bit random number circuit 503a and the 16-bit random number circuit 503b (that is, a random-value storage circuit that stores a random number for 12 bits and a 16-bit random-number storage circuit). A random value storage circuit for storing random numbers exists separately). When both the 12-bit random number circuit 503a and the 16-bit random number circuit 503b are set, the CPU 56 is provided in the RAM 55 with the random number read from the 12-bit random number circuit 503a and the random number read from the 16-bit random number circuit 503b. Stored in separate buffer areas. Therefore, even when the timing for reading the random number from the 12-bit random number circuit 503a and the timing for reading the random number from the 16-bit random number circuit 503b are the same, two different random numbers can be extracted and stored in different buffer areas.

  The random value update program 555 is a program for updating the value of the random R stored in the random value storage circuit 531 when the first random number update method is selected as the random number update method. The CPU 56 functions as a random value updating unit by executing processing according to the random value updating program 555. When the first random number update method is selected, the CPU 56 executes the random number value update program 555 and writes the count value update data “01h” in the count value update register 538, whereby the count value is stored in the counter 521. And the value of the random R stored in the random value storage circuit 531 is updated. When the second random number update method is selected as the random number update method, the counter 521 is updated with the random number generation clock signal output from the clock signal output circuit 537, and the random value storage circuit 531 is updated. The value of random R stored in is updated.

  The display result determination program 552 is a program for determining whether or not the display result in the special symbol display device 8 is a jackpot symbol. The CPU 56 functions as a display result determination unit by executing processing according to the display result determination program 552.

  In this embodiment, the CPU 56 follows the display result determination program 552 in response to the fact that the game ball has won the variable winning ball device 15 and a condition (execution condition) for executing the variable symbol variable display is established. Execute the process. Then, the CPU 56 reads the updated random R value from the random value storage circuit 531 and determines whether or not the display result in the special symbol display device 8 is a jackpot symbol.

  FIG. 36 is an explanatory diagram illustrating an operation in which the CPU 56 updates the random R value or reads the random R value when the first random number update method is selected. As shown in FIG. 36, when the first random number update method is selected, the CPU 56 writes the count value update data “01h” into the count value update register 538, thereby storing the random value stored in the random value storage circuit 531. The value of R (for example, “2”) is updated. Then, the CPU 56 receives the random R value from the random value storage circuit 531 in response to the fact that the game ball has won the variable winning ball device 15 and the condition (execution condition) for executing the variable symbol special display is established. (For example, “2”) is read out.

  When the random R value stored in the random value storage circuit 531 is further updated, an interval equal to or longer than the cycle of the system clock signal output from the clock circuit 501 has elapsed since the random R value was updated during the previous update. Sometimes, the count value update data “01h” must be written to the count value update register 538. This is because it is necessary to secure time for reading the updated random R value from the random value storage circuit 531.

  FIG. 37 is an explanatory diagram showing an operation in which the CPU 56 reads the value of the random R when the second random number update method is selected. As shown in FIG. 37, when the second random number update method is selected, the timer circuit 534 writes the random value fetch data “01h” into the random value fetch register 539, so that the counter 521 outputs it. The count value (for example, “2”) is taken into the random value storage circuit 531 and the random R value stored in the random value storage circuit 531 is updated. Then, the CPU 56 reads the updated random R value (for example, “2”) from the random value storage circuit 531.

  Specifically, when the second random number update method is selected, the counter 521 updates the count value C using the input of the random number generation clock signal SI1 as a trigger. Thereafter, when the random value fetch data “01h” is written into the random value fetch register 539, the latch signal generation circuit 533 outputs the latch signal SL to the random value storage circuit 531. Then, the random value storage circuit 531 reads and stores the count value output from the counter 521 with the input of the latch signal SL as a trigger. Then, the CPU 56 reads the value of random R stored in the random value storage circuit 531.

  If the timer circuit 534 does not write the random number value acquisition data “01h” to the random number value acquisition register 539, even if the counter 521 updates the count value, the random number value storage circuit 531 does not update the counter 521. Do not memorize numerical values. For example, the timer circuit 534 writes the random value take-in data “01h” into the random value take-in register 539, the count value “3” output from the counter 521 is taken into the random value storage circuit 531, and the random value storage circuit 531 , The random R value “3” stored therein is updated. In this case, the count value output from the counter 521 is updated from “3” to “4” or “5” unless the timer circuit 534 writes the random number value capture data “01h” again to the random number capture register 539. However, the random value stored in the random value storage circuit 531 is not updated, and the random value read from the random value storage circuit 531 remains “3”.

  The count value permutation change program 554 writes count value permutation change data “01h” to the count value permutation change register 536, and executes a count value permutation change process for changing the permutation of count values stored in the random value storage circuit 531. It is a program for. The CPU 56 functions as numerical data permutation changing means by executing processing according to the count value permutation changing program 554. The CPU 56 executes the count value permutation change program 554 and writes the count value permutation change data “01h” in the count value permutation change register 536, whereby the count value permutation change circuit 523 outputs and inputs to the random value storage circuit 531. The permutation of the count values to be changed.

  The serial communication circuit setting program 556 executes a serial communication circuit setting process for performing an initial setting for serial communication with a microcomputer (in this example, a payout control microcomputer) mounted on each control board in the serial communication circuit 505. It is a program to make it. That is, the CPU 56 functions as serial communication circuit setting means by executing processing according to the serial communication circuit setting program 556.

  The interrupt priority setting program 557 is a program for initially setting the priority of interrupt processing executed in response to an interrupt request from the serial communication circuit 505. That is, the CPU 56 functions as priority order initial setting means by executing processing according to the interrupt priority order setting program 556.

  Further, as shown in FIG. 38, the game control microcomputer 560 includes a special figure holding memory 570, a big hit determination table memory 571, a flag memory 572, and a start winning port switch timer memory 573.

  In the special figure holding memory 570, the game ball wins the variable winning ball device 15 and the execution condition of the variable symbol display is satisfied, but the variable display start condition is not yet satisfied (for example, the special symbol display device). 8 is a memory (storage area) for storing pending data including the number of times the execution condition of variable display is satisfied (8 is still executing variable display). The special figure holding memory 570 includes four entries, and each entry includes a holding number and a random R read from the random value storage circuit 531 according to the winning order in the order in which the game balls win the variable winning ball device 15. A value is stored in association with each other. Further, each time the special symbol variable display on the special symbol display device 8 is finished once or the big hit gaming state is finished, the variable display start condition based on the top information of the special symbol holding memory 570 is set. The variable display based on the top information of the special figure holding memory 570 is executed. In this case, when the special symbol variable display start condition is satisfied, the information registered in the second or lower place in the special figure holding memory 570 is advanced by one place. Further, when a game ball newly wins the variable winning ball apparatus 15 during the variable display of the special symbol, the value of the random R read from the random value storage circuit 531 based on the new winning is the special R value. It is registered in the empty entry in the figure holding memory 570.

  The jackpot determination table memory 571 stores a plurality of jackpot determination tables used by the CPU 56 to determine whether or not the display result of the special symbol display device 8 is a jackpot symbol. Specifically, as shown in FIG. 39A, the big hit determination table memory 571 stores a normal time big hit determination table 571a used in a gaming state (referred to as a normal state) other than the probability variation state. Further, the jackpot determination table memory 571 stores a probability change jackpot determination table 571b used in the probability change state, as shown in FIG. Note that, when the big hit determination is performed using the determination table shown in FIG. In this case, for example, if the set random number maximum value is too small, the difference in the probability of determining a big hit between the case where the normal jackpot determination table 571a is used and the case where the probability variation big hit determination table 571b is used is small. As a result, the player's interest in the game is diminished. Therefore, a plurality of determination tables (a plurality of normal time big hit determination tables 571a and a plurality of probability variation big hit determination tables 571b) are stored in the big hit determination table memory 571 in association with the random number circuit 503 and the maximum random number. Also good. Then, the CPU 56 uses the random number circuit 503 to be used and the determination tables 571a and 571b corresponding to the maximum random number among the determination tables stored in the jackpot determination table memory 571, and displays a special symbol according to the display result determination program 552. You may make it determine whether the display result of the apparatus 8 is made a big hit symbol. By doing so, even if the type of random number circuit 503 to be used and the maximum random number value are different, it is possible to control so that the probability of determining a big hit is somewhat the same.

  In this embodiment, a 16-bit random number circuit 503b is used. That is, it is assumed that it is decided to use the 16-bit random number circuit 503b in the process of step S151. Therefore, a value in a range (range from 0 to 65535) that can be generated in 16 bits can be taken as random R.

  In the flag memory 572, various flags used in the game control process for controlling the progress of the game are set. For example, in the flag memory 572, a probability change flag indicating that the gaming state is a probability change state and a big hit flag indicating that the game state is a big hit state are set.

  The start port switch timer memory 573 stores a timer value that is added or cleared in accordance with the winning detection signal SS input from the start port switch 14a.

  40 and 41 are explanatory diagrams showing an example of output port assignment in the game control means. As shown in FIG. 40, the output port 0 is an output port for a payout control signal (in this example, a connection confirmation signal) transmitted to the payout control board 37. Further, 8-bit data (effect control signal) of the effect control command transmitted to the sound / lamp control board 80 b is output from the output port 1. Note that the logic (for example, 0 is on) opposite to the “logic” (for example, 1 is on) shown in FIG. 40 and FIG. 41 may be used. When the signal line between the control board 37 and the payout control board 37 is disconnected or when the cable is disconnected (including no cable connection), the payout control microcomputer 370 always detects “OFF”. Is defined. Specifically, generally, when disconnection or disconnection of the cable occurs, a high level is detected on the signal receiving side, so the high level on the signal line between the main board 31 and the payout control board 37 is the game control means. The “logic” is determined to be in the off state at the output port at. Therefore, if necessary, an output buffer circuit for inverting the logic of the signal is provided outside the output port on the main board 31.

  Solenoid (large winning opening door solenoid) 21 for opening and closing the variable winning ball apparatus 20 for opening and closing the large winning opening, solenoid (large winning opening guide plate solenoid) 21A for switching the path in the large winning opening, and variable winning ball apparatus A drive signal for a solenoid (normal electric accessory solenoid) 16 for opening and closing 15 is output from the output port 2. An effect control INT signal (capture signal) for the effect control command transmitted to the sound / lamp control board 80 b is also output from the output port 2. The effect control INT signal is a signal for instructing the effect control means to capture (receive) 8-bit data of the effect control command.

  Then, various information output signals from the output ports 3 and 4 to the information terminal board 34 and the terminal board 160 through the information output circuit 64, that is, output data of information related to control are output.

  FIG. 42 is an explanatory diagram showing an example of bit assignment of input ports in the game control means. As shown in FIG. 42, detection signals from the count switch 23, the gate switch 32a, the winning port switches 33a, 39a, 29a, and 30a, and the start port switch 14a are input to bits 1 to 7 of the input port 0, respectively. . Further, the power-off signal from the payout control board 37 and the detection signal of the clear switch 921 are input to the bits 0 and 1 of the input port 1, respectively. Further, the detection signal of the payout number count switch 301 is input to the input port 2 via the payout control microcomputer 370. When the V winning area is provided, the detection signal of the V winning switch (V count switch) is also input to the input port (for example, bit 0 of the input port 0) in the game control means.

  Next, the operation of the gaming machine will be described. 43, 44 and 45 are executed by the CPU 56 of the gaming control microcomputer 560 in response to the start of power supply to the gaming machine and the reset signal to the gaming control microcomputer 560 becoming high level. It is a flowchart which shows the main process to perform. When the input level of the reset terminal to which the reset signal is input becomes a high level, the CPU 56 of the game control microcomputer 560 executes a security check process that is a process for confirming whether the contents of the program are valid. The main processing after step S1 is started. In the main process, the CPU 56 first performs necessary initial settings.

  In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1). Next, an interrupt mode for maskable interrupts is set (step S2), and a stack pointer designation address is set for the stack pointer (step S3). In step S2, the address synthesized from the value (1 byte) of the specific register (I register) of the game control microcomputer 560 and the interrupt vector (1 byte: least significant bit 0) output from the built-in device is Set the mode to indicate the interrupt address. When a maskable interrupt occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter in the stack.

  Next, the built-in device register is set (initialized) (step S4). By the processing in step S4, the CTC (counter / timer) and PIO (parallel input / output port), which are built-in devices (built-in peripheral circuits), are set (initialized).

  The game control microcomputer 560 used in this embodiment also includes an I / O port (PIO) and a timer / counter circuit (CTC) 504.

  Next, it is confirmed whether or not the power-off signal is in an OFF state depending on the state of bit 0 of the input port 1 (step S5). When the power supply to the gaming machine is started, the output voltage of various power sources such as the + 5V power source gradually reaches a specified value, but the power-off signal is not output by the process of step S5, that is, the high-power signal is not output. By confirming that the power supply voltage is stable, the CPU 56 can confirm that the power supply voltage is stable.

  When the power-off signal is in the on state, the CPU 56 confirms again whether the power-off signal is in the off state after a delay time of a predetermined period (for example, 0.1 second) (step S80). To do. If the power-off signal is off, the RAM 55 is set to an accessible state (step S6), and the process proceeds to a clear signal check process.

  When the power-off signal is in the off state, software delay processing for delaying the start timing of the gaming device control processing (game control processing) for controlling the progress of the game by software may be executed. By such software delay processing, the start timing of the game control processing can be delayed as compared with the case where the software delay processing is not executed. When the delay process is executed, a situation occurs in which the microcomputer of the other control board cannot receive the command transmitted from the game control board (main board 31) to the other control board (for example, the payout control board 37). Can be prevented.

  Next, the CPU 56 checks whether or not the clear switch is turned on (step S7). The CPU 56 may confirm the state of the clear signal only once via the input port 0, but may confirm the state of the clear signal a plurality of times. For example, if it is confirmed that the clear signal is off, a delay time of a predetermined time (for example, 0.1 seconds) is set, and then the clear signal is reconfirmed. If it is confirmed that the clear signal is in the on state at that time, it is determined that the clear signal is in the on state. Further, at this time, if it is confirmed that the clear signal is in the OFF state, after a predetermined delay time, the clear signal state may be reconfirmed. Here, the number of reconfirmations is not limited to once or twice, but may be three or more times. It is also possible to check twice and check again when the check results do not match.

  If the clear switch is not turned on in step S7, whether or not data protection processing of the backup RAM area (for example, power supply stop processing such as addition of parity data) was performed when power supply to the gaming machine was stopped Confirm (step S8). In this embodiment, when power supply is stopped, a process for protecting data in the backup RAM area is performed. When it is confirmed that such power supply stop processing has been performed, the CPU 56 determines that the power supply stop processing has been performed, that is, the control state at the time of power supply stop is stored. . When it is confirmed that the power supply stop process is not performed, the CPU 56 executes an initialization process.

  Whether or not the power supply stop process has been performed is determined by the value of the backup monitoring timer stored in the backup RAM area in the power supply stop process corresponding to the execution of the power supply stop process (for example, 2). ) Is confirmed by whether or not. Note that such a confirmation method is merely an example. For example, in the power supply stop process, a flag indicating that the power supply stop process has been executed is set in the backup flag area. In step S8, the flag is set. If it is confirmed that the power supply is stopped, it may be determined that the power supply stop process has been performed.

  If it is determined that the control state at the time of stopping power supply is stored, the CPU 56 performs data check (parity check in this example) in the backup RAM area (step S9). In this embodiment, clear data (00) is set in the checksum data area, and the checksum calculation start address is set in the pointer. Also, the number of checksum calculations corresponding to the number of data to be checksum is set. Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated. The calculation result is stored in the checksum data area, the pointer value is incremented by 1, and the checksum calculation count value is decremented by 1. The above processing is repeated until the value of the checksum calculation count becomes zero. When the value of the checksum calculation count becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area and uses the inverted data as the checksum.

  In the power supply stop process, a checksum is calculated by the same process as described above, and the checksum is stored in the backup RAM area. In step S9, the calculated checksum is compared with the stored checksum. When the power supply is stopped after an unexpected power failure or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area may be different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state when the power supply is stopped, the initialization process (the process of steps S10 to S14) executed at the time of power-on that is not the time of recovery from the stop of the power supply is performed. Execute.

  If the check result is normal, the CPU 56 performs a game state restoration process for returning the internal state of the game control means and the control state of the electrical component control means such as the effect control means to the state when the power supply is stopped. Specifically, the start address of the backup setting table stored in the ROM 54 is set as a pointer (step S91), and the contents of the backup setting table are sequentially set in the work area (area in the RAM 55) (step S92). ). The work area is backed up by a backup power source. In the backup setting table, initialization data for an area that may be initialized in the work area is set. As a result of the processing in steps S91 and S92, the saved contents of the work area that should not be initialized remain. The parts that must not be initialized include, for example, data indicating a gaming state before the power supply is stopped (special symbol process flag, etc.), an area where the output state of the output port is saved (output port buffer), and unpaid prize balls This is the part where data indicating the number is set.

  Further, the CPU 56 sets the head address of the backup command transmission table stored in the ROM 54 as a pointer (step S93), and proceeds to step S15.

  In the initialization process, the CPU 56 first performs a RAM clear process (step S10). Note that the predetermined data may be left as it is without initializing the entire area of the RAM 55. Also, the initial address of the initialization setting table stored in the ROM 54 is set as a pointer (step S11), and the contents of the initialization setting table are sequentially set in the work area (step S12).

  Control states such as a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol buffer, a total prize ball number storage buffer, a special symbol process flag, an award ball flag, a ball out flag, etc. An initial value is set in a flag for selectively performing processing according to the above. In addition, a bit corresponding to the output port that outputs the connection confirmation signal in the output port buffer is set (corresponding to the ON state of the connection confirmation signal).

  Further, the CPU 56 sets the start address of the initialization command transmission table stored in the ROM 54 as a pointer (step S13), and transmits an initialization command for initializing the sub board according to the contents to the sub board. Processing is executed (step S14). As an initialization command, a command indicating an initial symbol displayed on the variable display device 9, an initialization command to the payout control board 37, or the like can be used.

  Further, the CPU 56 executes a random number circuit setting process for initially setting the random number circuits 503a and 503b (step S15). In this case, the CPU 56 performs setting according to the random number circuit setting program 551 to make the random number circuits 503a and 503b update the random R value.

  Further, the CPU 56 executes serial communication circuit setting processing for initial setting of the serial communication circuit 505 (step S15a). In this case, the CPU 56 performs processing according to the serial communication circuit setting program 556, thereby setting the serial communication circuit 505 to perform serial communication with the payout control microcomputer.

  When the serial communication circuit 505 is initialized, the CPU 56 initializes the priority of interrupt processing to be executed in response to the interrupt request from the serial communication circuit 505 (step S15b). In this case, the CPU 56 executes the process according to the interrupt priority setting program 557, thereby initializing the priority of the interrupt process.

  For example, the CPU 56 initializes the priority of each interrupt process according to a predetermined interrupt process priority table including the default priority of each interrupt process. FIG. 46 is an explanatory diagram of an example of an interrupt processing priority table. In this embodiment, the CPU 56 is initially configured to preferentially execute an interrupt process whose cause is a communication error in the serial communication circuit 505 according to the interrupt process priority table shown in FIG. Set. In this case, for example, the CPU 56 sets an interrupt priority execution flag at the time of communication error indicating that priority is given to an interrupt process whose cause is an interrupt.

  In this embodiment, when a timer interrupt and an interrupt request from the serial communication circuit 505 are generated at the same time, the CPU 56 preferentially performs an interrupt process by the timer interrupt.

  In addition, the default priority of each interrupt process can be changed by the user. For example, the game control microcomputer 560 stores specification information for specifying an interrupt process set by a user (for example, a game machine manufacturer) in a predetermined storage area of the ROM 54 in advance. Then, the CPU 56 sets the priority of interrupt processing according to the designation information stored in a predetermined storage area of the ROM 54.

  Then, the CPU 56 executes a timer interrupt setting process for setting a CTC register built in the game control microcomputer 560 so that a timer interrupt is periodically taken every predetermined time (for example, 2 ms) ( Step S16). That is, a value corresponding to, for example, 2 ms is set in a predetermined register (time constant register) as an initial value. In this embodiment, it is assumed that a timer interrupt is periodically taken every 2 ms.

  When the timer interrupt setting is completed, the CPU 56 first disables the interrupt (step S17), and detects whether or not a power-off signal is output (whether the power-off signal is turned on) A power-off detection process is executed (step S18a). Further, the CPU 56 executes the initial value random number update process (step S18b), and again sets the interrupt permitted state (step S19). That is, the CPU 56 sets the interrupt disabled state when the power-off process and the initial value random number update process are executed, and sets the interrupt enabled state when the power-off process and the initial value random number update process are completed.

  The initial value random number update process is a process of updating the count value of the counter for generating the initial value random number. The initial value random number is a random number for determining the type of jackpot (for example, a jackpot symbol determining random number for determining a special symbol that generates a jackpot, or whether to shift the gaming state to a probable state) Initial value of the count value such as a counter (determination random number generation counter) for generating a probability variation determining random number to determine whether or not to generate a hit based on a normal symbol It is a random number for determining the value. Game control processing described later (a game control microcomputer controls itself a game device such as a variable display device 9, a variable winning ball device 15, a ball payout device 97 provided in the game machine, or In a process of transmitting a command signal to cause another microcomputer to control, also referred to as a gaming apparatus control process), when the count value of the determination random number generation counter makes one round, an initial value is set in the counter.

  In addition, when the initial value random number update process is executed, the interrupt disabled state is set so that the initial value random number update process is also executed in the timer interrupt process described later (that is, the timer interrupt process step). This is to avoid competing with the processing in the timer interrupt processing because the same processing is executed in S24). That is, if the timer interrupt is generated during the process of step S18b and the count value of the counter for generating the initial value random number is updated during the timer interrupt process, the continuity of the count value is lost. May be. However, such an inconvenience does not occur if the interrupt is prohibited during the process of step S18b.

  When the interrupt-permitted state is set in step S19, the timer interrupt or interrupt request from the serial communication circuit 505 is permitted until the next processing in step S17 is executed and the interrupt-prohibited state is set. . When a timer interrupt occurs while the interrupt permission state is set, the CPU 56 of the game control microcomputer 560 executes a timer interrupt process to be described later. When an interrupt request is generated from the serial communication circuit 505 while the interrupt permission state is set, the CPU 56 of the game control microcomputer 560 causes each interrupt process (communication error interrupt process or reception Execute time interruption processing and transmission completion interruption processing). In this embodiment, priority is given to the interrupt process before the timer interrupt or the interrupt request is set to be permitted by executing step S15b before the loop process from step S17 to step S19. Processing for setting or changing the order is performed.

  Next, the CPU 56 executes a display random number update process (step S19a). The display random number is a random number for determining the display of the special symbol display 8. In this embodiment, as a display random number, a random number for determining a variation pattern for determining a variation pattern of a special symbol, or a random number for determining a reach for determining whether or not to reach when a big hit is not generated, is used. Used. The display random number update process is a process for updating the count value of the counter for generating the display random number.

  Next, the CPU 56 performs a process of sending an effect control command by setting an effect control command related to the decorative symbol synchronized with the change of the special symbol in a predetermined area of the RAM 55 (command control process: step S19b). It should be noted that the fact that the variation of the decorative symbol is synchronized with the variation of the special symbol means that the variation time (variable display period) is the same.

  Further, the CPU 56 executes prize ball processing for setting the number of prize balls based on detection signals from the prize opening switches 29a, 30a, 33a, 39a and the like (step S19c). Specifically, a payout command command such as a prize ball number command indicating the number of prize balls is output to the payout control board 37 in response to winning detection based on the winning opening switches 29a, 30a, 33a, 39a being turned on. . The payout control microcomputer 370 mounted on the payout control board 37 drives the ball payout device 97 in response to receiving a prize ball number command indicating the number of prize balls.

  In this embodiment, the number of winnings is counted in response to detection of winning based on the fact that the winning opening switches 29a, 30a, 33a, 39a, etc. are turned on in the input determination processing of the timer interruption processing described later. In the prize ball process of the main process, a prize ball number command is transmitted to the payout control board 37 based on the counted number of winnings.

  Further, the CPU 56 performs a special symbol process (step S19d). In the special symbol process, the corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state. Also, normal symbol process processing is performed (step S19e). In the normal symbol process, the corresponding process is selected and executed according to the normal symbol process flag for controlling the display state of the normal symbol display 10 in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state.

  Further, the CPU 56 performs information output processing for outputting data such as jackpot information, starting information, probability variation information supplied to the hall management computer, for example (step S19f).

  In addition, a test terminal process, which is a process for outputting a test signal for enabling the control state of the gaming machine to be confirmed outside the gaming machine, is executed (step S19g). In this embodiment, a RAM area (output port buffer) corresponding to the output state of the output port is provided, but the CPU 56 outputs the contents related to the solenoid in the RAM area of the output port 2 to the output port. (Step S19h: output process).

  When the output process is executed, the CPU 56 proceeds to step S17, and executes the processes after step S17 again. That is, the processing from step S17 to step S19h is repeatedly executed.

  Next, the random number circuit setting process (step S15) in the main process will be described. FIG. 47 is a flowchart showing random number circuit setting processing. In the random number circuit setting process, the CPU 56 first executes the process according to the random number circuit selection module 551f included in the random number circuit setting program 551, and from among the random number circuits 503a and 503b built in the game control microcomputer 560, the timer A random number circuit used when executing the interrupt process is set (step S151). For example, the game control microcomputer 560 stores, in a predetermined storage area of the ROM 54, specification information for specifying the random number circuit 503 used when executing the timer interrupt process set by the user (for example, the manufacturer of the game machine). I remember it. Then, the CPU 56 selects either the 12-bit random number circuit 503a or the 16-bit random number circuit 503b according to the designation information stored in a predetermined storage area of the ROM 54, and uses the selected random number circuit when executing the timer interrupt process. Set as a random number circuit. Note that both the 12-bit random number circuit 503a and the 16-bit random number circuit 503b may be set as random number circuits used when the timer interrupt process is executed.

  As described above, in step S151, whether or not each of a plurality of random number circuits (12-bit random number circuit 503a and 16-bit random number circuit 503b) having different predetermined ranges of numerical data that can be updated can be used is set. Therefore, it is possible to prevent unnecessary random numbers from being processed during the execution of the timer interrupt process, and the control burden on the game control microcomputer 560 can be reduced. For example, when the game control microcomputer 560 performs the game control process using only the random number generated by one of the two random number circuits 503a and 503b, the random number is read from the random circuit that is not used for the game control process. Processing or the like can be prevented, and the control burden on the game control microcomputer 560 can be reduced.

  When the CPU 56 sets the random number circuit 503 to be used in step S151, the CPU 56 stops the operation of the counter 521 and the clock signal output circuit 524, for example, by not writing data to the random number circuit activation register 541 so that the random number circuit 503 is not used. The counter 521 of the set random number circuit is prevented from updating the count value C. Further, for example, the counter 521 of the random number circuit that is set not to use updates the count value C, but the CPU 56 does not output the output control signal SC so that the random number cannot be read from the random value storage circuit 531. You may control to. Further, for example, the CPU 56 prevents the random number value fetching data “01h” from being written in the random number fetching register 539 of the random number circuit that is set not to be used for the timer circuit 534, and the latch signal generation circuit 533 Control may be performed so that the latch signal SL is not output to the random value storage circuit 531.

  As described above, by setting the random number circuit 503 to be used, by setting only the random number circuit 503 to be used, the range of the random number value to be generated can be appropriately set. Further, it is possible to prevent unnecessary random numbers from being processed during the execution of the timer interrupt process, and the control burden on the game control microcomputer 560 can be reduced. For example, when a big hit determination is performed using a determination table including a distant value (for example, “1” and “100”) as a big hit determination value, the big hit is determined with a predetermined big hit probability (for example, 1/100). In this case, the number of types of determination values to be processed is smaller when the random number by the 12-bit random number circuit 503a is used than when the random number by the 16-bit random number circuit 503b is used, and the game control microcomputer 560 is used. The control burden is reduced.

  Further, the CPU 56 executes processing in accordance with the random number maximum value setting module 551a included in the random number circuit setting program 551, and generates random number maximum value setting data for designating a random number maximum value preset by the user as a random number maximum value setting register 535. (Step S152). By doing so, the random number maximum value of random R preset by the user is set in the random number circuit 503. When the 12-bit random number circuit 503a is set as the random number circuit used when the timer interrupt is executed, the CPU 56 sets the random number maximum value that specifies the random number maximum value (any value from “0” to “4095”). Data is written into the random number maximum value setting register 535 of the 12-bit random number circuit 503a. When the 16-bit random number circuit 503b is set as the random number circuit used when the timer interrupt is executed, the CPU 56 sets the random number maximum value that specifies the maximum random number value (any value from “0” to “65535”). Data is written into the random number maximum value setting register 535 of the 16-bit random number circuit 503b.

  In this embodiment, when “0” to “255” are set as the random number maximum value, the random number maximum value is reset to a predetermined value in the random number maximum value resetting process described later. Even when control is performed to write a value greater than “256” as the random number maximum value, values “0” to “255” are set in the random number maximum value setting register 535 due to garbled data or the like. In the case where it is lost, the random number maximum value is reset to a predetermined value in the random number maximum value resetting process described later.

  As described above, since the maximum value of the random number to be generated is set in advance in the random number maximum value setting register 535 in step S152, a random number having a value larger than the range of random numbers used during execution of the timer interrupt process is generated. Can be prevented, and the processing load on the random number circuit 503 and the game control microcomputer 560 can be reduced.

  Further, the CPU 56 checks whether or not the random number maximum value set in the random number maximum value setting register 535 in step S152 is not less than a predetermined lower limit value. The random number maximum value resetting process for resetting the random number maximum value set in 535 is executed (step S153).

  Further, the CPU 56 executes a process according to the initial value change module 551e included in the random number circuit setting program 551, and executes an initial value change process for changing the initial value of the count value updated by the counter 521 of the random number circuit 503 (step). S154).

  Further, the CPU 56 executes processing according to the random number update method selection module 551b included in the random number circuit setting program 551, and writes the random number update method selection data in the random number update method selection register 540 (step S155). By doing so, the random number update method of the random number circuit 503 is set. In this embodiment, the CPU 56 writes the random number update method selection data “10h” in the random number update method selection register 540. That is, in this embodiment, the second random number update method is set as the random number update method of the random number circuit 503.

  Further, the CPU 56 executes processing according to the cycle setting module 551c included in the random number circuit setting program 551, and sets the cycle setting data (the reference clock signal by how many minutes) that specifies the cycle of the random number generation clock signal SI1 preset by the user. The data for setting whether to circulate) is written in the period setting register 537 (step S156). By doing so, the cycle of the random number generating clock signal SI1 preset by the user is set in the random number circuit 503.

  Further, the CPU 56 sets whether or not to update the initial value input to the counter 521 when the count value is updated to a predetermined final value by the counter 521 of the random number circuit 503 (step S157). For example, the game control microcomputer 560 sets in advance a setting value indicating whether or not to update the initial value input to the counter 521 when the count value is updated to a predetermined final value by the counter 521. And stored in a predetermined area of the ROM 54. Whether or not the CPU 56 updates the initial value input to the counter 521 when the counter 521 updates the count value to a predetermined final value in accordance with a predetermined set value stored in a predetermined storage area of the ROM 54. Set In this embodiment, when the CPU 56 determines in step S157 that the initial value input to the counter 521 is to be updated, the count value is updated to a predetermined final value (when a notification signal is input from the counter 521). An initial value update flag indicating that the initial value is updated is set. In this embodiment, the case where the initial value update flag is set in accordance with a predetermined set value in step S157 will be described. Then, the CPU 56 updates the initial value of the count value output from the counter 521 based on the initial value update flag being set in the random number circuit initial value update process described later.

  Instead of changing the initial value of the count value by the CPU 56, the random value circuit 503 may change the initial value of the count value to a predetermined value based on the update of the count value to the final value. For example, the random number circuit 503 includes an initial value update data register that stores initial value update data indicating that the initial value is updated, and an initial value change circuit that changes the initial value. In step S157, the CPU 56 performs initial value update. Value update data is set in the initial value update data register. In this case, when the counter 521 updates the count value to the final value, the counter 521 outputs a notification signal to the initial value change circuit. Then, the initial value changing circuit checks whether or not initial value update data is set in the initial value update data register. Then, when the initial value change circuit confirms that the initial value update data is set, the initial value change circuit changes the initial value of the count value to a predetermined value. Note that the initial value changing circuit may change the initial value of the count value whose permutation has been changed in the count value permutation changing process described later.

  Further, the CPU 56 sets whether or not to change the permutation of the count values updated by the counter 521 when the count value is updated to a predetermined final value by the counter 521 of the random number circuit 503 (step S158). For example, the game control microcomputer 560 sets a preset value indicating whether or not to change the permutation of count values output by the counter 521 when the counter 521 updates the count value to a predetermined final value. Is stored in a predetermined area of the ROM 54. Then, the CPU 56 changes the permutation of the count values output by the counter 521 when the count value is updated by the counter 521 to a predetermined final value according to a predetermined set value stored in a predetermined storage area of the ROM 54. Set whether or not. In this embodiment, if the CPU 56 determines in step S158 that the permutation of count values output by the counter 521 is to be changed, the CPU 56 changes the permutation of count values when the count value is updated to a predetermined final value. The indicated count value permutation change flag is set. In this embodiment, the case where the count value permutation change flag is set in step S158 according to a predetermined set value will be described. Then, the CPU 56 changes the permutation of the count values output by the counter 521 based on the fact that the count value permutation change flag is set in the count value permutation changing process described later.

  Instead of changing the permutation of the count values under the control of the CPU 56, the permutation of the count values may be changed on the random number circuit 503 side based on the update of the count values up to the final value. For example, the random number circuit 503 includes a permutation change data register that stores permutation change data indicating that the permutation of count values is to be changed. In step S158, the CPU 56 sets the permutation change data in the permutation change data register. In this case, when the counter 521 updates the count value to the final value, the notification signal is output to the count value permutation change circuit 523, and the count value permutation change circuit 523 that has received the notification signal receives the permutation change data in the permutation change data register. Check whether it is set. When the count value permutation changing circuit 523 confirms that the permutation change data is set, it changes the permutation of the count values.

  Then, the CPU 56 executes processing according to the random number circuit activation module 551d included in the random number circuit setting program 551, and writes the random number circuit activation data “80h” in the random number circuit activation register 541 (step S159). By doing so, the CPU 56 activates the random number circuit 503.

  Next, the random number maximum value resetting process (step S153) in the random number circuit setting process will be described. FIG. 48 is a flowchart showing the random number maximum value resetting process. In the random number maximum value resetting process, the CPU 56 reads the random number maximum value set in the random number maximum value setting register 535 (step S153a). When the 12-bit random number circuit 503a is set as the random number circuit used when the timer interrupt process is executed, the CPU 56 reads the random number maximum value set in the random number maximum value setting register 535 of the 12-bit random number circuit 503a. When the 16-bit random number circuit 503b is set as the random number circuit used when the timer interrupt process is executed, the CPU 56 reads the random number maximum value set in the random number maximum value setting register 535 of the 16-bit random number circuit 503b.

  The CPU 56 determines whether or not the read random number maximum value is equal to or less than a predetermined lower limit value (step S153b). When the 12-bit random number circuit 503a is set, the maximum random number that can be set in the 12-bit random number circuit 503a is from “256” to “4095”. It is determined whether or not the random number maximum value read from is less than or equal to the lower limit value “256”. When the 16-bit random number circuit 503b is set, the maximum random number that can be set in the 16-bit random number circuit 503b is from “512” to “65535”. Therefore, the CPU 56 sets the random number maximum value of the 16-bit random number circuit 503b. It is determined whether or not the maximum random number read from the register 535 is equal to or lower than the lower limit “512”.

  When the read random number maximum value is less than or equal to the lower limit value, the CPU 56 resets the random number maximum value set in the random number maximum value setting register 535 to a predetermined value (step S153c). When the 12-bit random number circuit 503a is set, the CPU 56 determines that the random number maximum value read from the random number maximum value setting register 535 of the 12-bit random number circuit 503a is equal to or less than the lower limit “256”, the CPU 56 determines the random number maximum value setting register 535. The random number maximum value set in is reset to a predetermined value “4095”. When the 16-bit random number circuit 503b is set, if the random number maximum value read from the random number maximum value setting register 535 of the 16-bit random number circuit 503b is determined to be less than or equal to the lower limit value “512”, the CPU 56 sets the random number maximum value setting. The random number maximum value set in the register 535 is reset to a predetermined value “65535”.

  As described above, when the random number maximum value set in the random number maximum value setting register 535 is less than or equal to the predetermined lower limit value, the random number maximum value is reset to a predetermined value. Therefore, it is possible to prevent an excessively small value from being set as the maximum value of the random number due to an action such as malfunction of the game control microcomputer 560 or generation of a capture signal using a wireless signal. be able to. Therefore, it is possible to prevent a situation in which a random number having an excessively small value range from the minimum value to the maximum value is generated.

  Next, the initial value changing process (step S154) in the random number circuit setting process will be described. FIG. 49 is a flowchart showing the initial value changing process. In the initial value changing process, the CPU 56 first reads the initial value changing method setting data stored in the area 1F97h in the user program execution data area, and specifies the initial value changing method selected by the user. In this case, the CPU 56 determines whether or not the value of the read initial value changing method setting data is “01h” (step S154a), thereby specifying the initial value changing method selected by the user.

  When the value of the initial value change method setting data is “01h”, the CPU 56 sets the initial value input to the counter 521 of the random number circuit 503 to a value set based on the ID number unique to the game control microcomputer 560. Change (step S154b). For example, the game control microcomputer 560 associates, in a predetermined storage area of the ROM 54, the ID number of the game control microcomputer 560 with a calculated value obtained by performing a predetermined calculation based on the ID number. I remember it. In step S154b, the CPU 56 changes the initial value of the count value to the calculated value based on the ID number stored in advance. Further, for example, in step S154b, the CPU 56 calculates the ID number of the game control microcomputer 560 and a predetermined value (for example, the ID number (for example, “100”) to a predetermined value (for example, “100”). The initial value of the count value is set to the calculated value (for example, “200”). When the initial value input to the counter 521 is changed, the CPU 56 sets an initial value change flag indicating that the initial value of the count value has been changed (step S154c).

  When the CPU 56 changes the initial value input to the counter 521 in step S154b, the CPU 56 checks the value of the random number maximum value setting register 535 of the comparator 522 of the random number circuit 503, and the value set based on the ID number is determined. It is determined whether or not it is greater than the maximum random number. If it is determined that the value set based on the ID number is equal to or greater than the maximum random number, the CPU 56 does not change the initial value input to the counter 521 (for example, resets the initial value to “0”). By doing so, it is possible to prevent a situation where the initial value of the count value is set to a value equal to or greater than the random number maximum value.

  If the value of the initial value change method setting data is not “01h” in step S154a (that is, the value of the initial value change method setting data stored in the area 1F97h of the user program execution data area is “00h”). In the case), the CPU 56 does not change the initial value of the count value, ends the initial value changing process as it is, and proceeds to step S155.

  By executing the random number circuit setting process, various signals are input to the random number circuit 503 when the timer interrupt process is executed, and various signals are generated in the random number circuit 503. FIG. 50 is a timing chart showing the timing at which each signal is input to the random number circuit 503 and the timing at which each signal is generated in the random number circuit 503.

  As shown in FIG. 50, the clock circuit 501 increases the signal level of the output terminal from the low level to the high level at predetermined intervals (timing T11, T21,... Shown in FIG. 50). A reference clock signal CLK (see FIG. 50A) is input to 503.

  The clock signal output circuit 524 divides the reference clock signal CLK supplied from the clock circuit 501 to generate a random number generation clock signal SI1 (see FIG. 50B). For example, the clock signal output circuit 524 raises the signal level of the output terminal from the low level to the high level at timings T11, T12,. To output a random number generating clock signal SI1.

  In the example shown in FIG. 50, for ease of explanation, the clock signal output circuit 524 divides the reference clock signal CLK by two to generate the random number generation clock signal SI1. However, in the actual random number circuit, the period that can be set in the period setting register 537 is from “system clock signal period × 128 × 7” to “system clock signal period × 128 × 256”. Therefore, in an actual random number circuit, the clock signal output circuit 524 is set in the cycle setting register 537 in a range from “system clock signal cycle × 128 × 7” to “system clock signal cycle × 128 × 256”. The reference clock signal CLK is divided by a division ratio corresponding to the cycle setting data “07h” to “FFh” to generate a random number generating clock signal SI1. The random number generating clock signal SI 1 generated by the clock signal output circuit 524 is output to the selector 528 and the inverting circuit 532.

  In this embodiment, since the second random number update method is set in the random number circuit setting process, the second random number update method selection signal is input from the random number update method selection signal output circuit 527 to the selector 528. When the second random number update method selection signal output circuit 527 receives the second random number update method selection signal output circuit 527, the selector 528 selects the random number generation clock signal SI1 input from the clock signal output circuit 524 and outputs it to the counter 521. . The counter 521 updates the count value C and outputs it to the count value permutation change circuit 523 every time the rising edge of the random number generation clock signal SI1 supplied from the selector 528 is input.

  The inversion circuit 532 generates the inverted clock signal SI2 (see FIG. 50C) by inverting the signal level of the random number generation clock signal SI1 input from the clock signal output circuit 524. For example, the inverting circuit 532 lowers the signal level of the output terminal from the high level to the low level at timings T11, T12,. As a result, the inverted clock signal SI2 is output. Further, the inverted clock signal SI <b> 2 generated by the inverting circuit 532 is output to the latch signal generating circuit 533.

  When a predetermined time (for example, 3 milliseconds) elapses after the winning detection signal SS (see FIG. 50D) is input to the timer circuit 534, the latch signal generation circuit 533 receives a disturbance from the random value read signal output circuit 526. A numerical reading signal is input. For example, when the signal level at the output terminal of the random number read signal output circuit 526 rises from a low level to a high level, the random value read signal is input to the latch signal generation circuit 533. The latch signal generation circuit 533 inverts the random value read signal input from the random value read signal output circuit 526 in response to the input of the second random number update method selection signal from the random number update method selection signal output circuit 527. A latch signal SL (see FIG. 50E) is output in synchronization with the rising edge of the inverted clock signal SI2 supplied from 532.

  As described above, the random number circuit 503 updates the count value C at the timings T11, T12, T13... And outputs the latch signal SL at the timing T22 different from the timings T11, T12, T13. The random number value is stored in 531.

  Next, the serial communication circuit setting process (step S15a) in the main process will be described. FIG. 51 is a flowchart showing the serial communication circuit setting process. In the serial communication circuit setting process, the CPU 56 first executes the process according to the serial communication circuit setting program 556 to set the baud rate of the serial communication circuit 505 (step S1511). In this case, the CPU 56 writes a setting value corresponding to the baud rate to be set in the baud rate register 702 of the serial communication circuit 505. For example, the game control microcomputer 560 stores specification information for specifying a set value set by a user (for example, a game machine manufacturer) in a predetermined storage area of the ROM 54 in advance. Then, the CPU 56 writes the setting value in the baud rate register 702 according to the designation information stored in a predetermined storage area of the ROM 54. For example, when the baud rate set value “156” is set by the CPU 56, the baud rate “1201.92 bps” is generated by the baud rate generation circuit 703 using the equation (1) and the clock frequency “3 MHz”.

  Further, the CPU 56 sets a data format of data transmitted / received by the serial communication circuit 505 (step S1512). In this case, the CPU 56 sets the data length (8 bits or 9 bits) of the transmission / reception data and the presence / absence of the parity function by setting the value of each bit of the control register A707. For example, the game control microcomputer 560 stores specification information for specifying the value of each bit of the control register A707 set by the user (for example, the manufacturer of the game machine) in a predetermined storage area of the ROM 54 in advance. Yes. Then, the CPU 56 sets the value of each bit of the control register A707 according to the designation information stored in a predetermined storage area of the ROM 54.

  In addition, the CPU 56 sets whether to permit each interrupt request generated by the serial communication circuit 505 (step S1513). In this case, the CPU 56 sets the value of bits 5, 6, and 7 of the control register B708 to thereby send an interrupt request at the time of transmission (a transmission interrupt request that is an interrupt request when transmitting data, or a transmission completion interrupt that is performed when transmission is completed). Request) and whether or not to accept interrupt request at reception. The CPU 56 can also be set to allow both a transmission interrupt request and a reception interrupt request, and allows only one of a transmission interrupt request and a reception interrupt request. It is also possible to set. Further, the CPU 56 sets whether or not to permit an interrupt request at the time of each communication error by setting the values of the bits 0 to 3 of the control register C709. For example, the game control microcomputer 560 stores in advance a designation information for designating values of each bit of the control register B 708 and the control register C 709 set by a user (for example, a manufacturer of the gaming machine) in a predetermined storage area of the ROM 54. I remember it. Then, the CPU 56 sets the value of each bit of the control register B 708 and the control register C 709 according to the designation information stored in a predetermined storage area of the ROM 54.

  Next, the prize ball process (step S19c) in the main process will be described. First, payout control signals and payout control commands transmitted and received between the main board 31 and the payout control board 37 will be described. FIG. 52 is an explanatory diagram showing an example of the contents of a control signal output from the game control means to the payout control means. In this embodiment, a connection confirmation signal is transmitted and received as a control signal between the main board 31 and the payout control board 37 in order to perform various controls relating to payout control and the like. As shown in FIG. 52, the connection confirmation signal is output when the main board 31 rises (when the game control means starts the game control process), indicating that the main board 31 has risen with respect to the payout control board 37. This is a signal for notification (connection confirmation signal for the main board 31). The connection confirmation signal indicates that the winning ball can be paid out.

  Similarly to the game control microcomputer 560, the payout control microcomputer 370 includes a serial communication circuit 380. Various payout control commands are transmitted and received between the serial communication circuit 505 built in the game control microcomputer 560 and the serial communication circuit 380 built in the payout control microcomputer 370. The configuration and function of the serial communication circuit 380 built in the payout control microcomputer 370 are the same as the configuration and function of the serial communication circuit 505 built in the game control microcomputer 560.

  FIG. 53 is an explanatory diagram showing an example of the contents of control commands transmitted and received between the game control means and the payout control means. In this embodiment, various control commands are transmitted and received between the microcomputers of the main board 31 and the payout control board 37 in order to perform various controls relating to the payout control and the like.

  The award ball number command is a command that is output to designate the number of game balls (0 to 15) for which a payout request is made. In this embodiment, when a game ball is detected by the start port switch 14a, three prize balls are paid out, and when a game ball is detected by any of the prize port switches 33a, 39a, 29a, 30a, ten game balls are detected. When a game ball is detected by the count switch 23, 15 prize balls are paid out. Therefore, when a game ball is detected by the start opening switch 14a, a prize ball number command “03” for notifying 3 prize balls is transmitted, and any of the prize opening switches 33a, 39a, 29a, 30a is transmitted. When a game ball is detected, a prize ball number command “0A” for notifying 10 prize balls is transmitted, and when a game ball is detected by the count switch 23, 15 prize balls are notified. The award ball number command “0F” is transmitted. The award ball number command may be composed of 2 bytes. In this case, for example, the CPU 56 first writes the lower 1 byte data of the prize ball number command to the transmission data register 710. When the transmission of the lower 1 byte data of the prize ball number command from the transmission shift register 712 is completed, the CPU 56 responds to the transmission interrupt request from the serial communication circuit 505, and the CPU 56 receives the upper 1 byte of the prize ball number command. Data is written to the transmission data register 710, and the upper byte data of the prize ball number command is transmitted from the transmission shift register 712.

  The prize ball ACK command “D2” is a command for notifying the game control means that the payout control means has received the prize ball number command. The prize ball ACK command corresponds to a reception confirmation signal indicating that a prize ball number command has been received.

  The award ball excess abnormality command “E1” is a command for notifying the payout control means from the game control means that a prize ball excess abnormality has occurred. In this embodiment, when the game control means detects the occurrence of excessive prize ball abnormality in which more game balls are paid out than the number of prize balls to be paid out, the game control means transmits an excessive prize ball abnormality command “E1” to the payout control means. To do. The prize ball under-abnormality command “E2” is a command for notifying the payout control means from the game control means that a prize ball under-abnormality has occurred. In this embodiment, the game control means is in a state in which the total number of winning balls exceeds a predetermined payout underdetermined value (the number of game balls being paid out is less than the number of winning balls to be paid out). When the occurrence of an abnormality is detected, a prize ball under-abnormality command “E2” is transmitted to the payout control means.

  54 is a block diagram showing signal lines and the like used for transmission / reception of the control signal shown in FIG. 52 and the control command shown in FIG. FIG. 54 also shows a power-off signal. As shown in FIG. 54, the connection confirmation signal is output by the game control microcomputer 560 via the output circuit 67 and input to the payout control microcomputer 370 via the input circuit 373A. The power-off signal is output via the output circuit 373B and input to the game control microcomputer 560 via the input circuit 68. The prize ball number command is output from the serial circuit 505 built in the game control microcomputer 560 and is input to the serial circuit 380 built in the payout control microcomputer 370. The award ACK command is output from the serial circuit 380 built in the payout control microcomputer 370 and input to the serial circuit 505 built in the game control microcomputer 560.

  Each of the connection confirmation signal and the power-off signal is 1-bit data and is transmitted through one signal line. Further, between the main board 31 and the payout control board 37, the signal line for the power-off signal to the game control microcomputer 560 and the signal line for the control signal (connection confirmation signal) related to the payout control are wired together. can do. Therefore, in the gaming machine, the wiring space related to the power-off signal to the gaming control microcomputer 560 can be saved.

  In this embodiment, the game control microcomputer 560 serially transmits a prize ball number command to the payout control microcomputer 370, and the payout control microcomputer 370 sends a prize ball ACK command to the game control microcomputer 560. Although the case of performing bidirectional communication for serial transmission will be described, the game control microcomputer 560 and the payout control microcomputer 370 may perform one-way serial communication. For example, the game control microcomputer 560 may perform one-way serial communication in which a prize ball number command is transmitted to the payout control microcomputer 370, and the payout control microcomputer 370 may not transmit a prize ball ACK command. .

  FIG. 55 is a timing chart showing an example of how to output a payout control signal and a payout control command. As shown in FIG. 55, when the winning detection switch detects a winning of a game ball, the game control means (game controlling microcomputer 560) pays out a winning ball number command corresponding to the number of winning balls paid out in accordance with the winning. This is transmitted to the control means (dispensing control microcomputer 370). Specifically, when the gaming control microcomputer 560 detects that a game ball has won a winning area provided in the gaming machine by a detection signal of the winning detection switch, the winning ball corresponding to the number of winning balls Counts up the command output counter. When the count value of the prize ball command output counter becomes a value other than 0, a prize ball number command corresponding to the number of prize balls corresponding to the prize ball command output counter is transmitted to the payout control microcomputer 370.

  Further, in this embodiment, when a game ball is detected by the start port switch 14a, three prize balls are paid out, and when a game ball is detected by any of the prize port switches 33a, 39a, 29a, 30a. Ten prize balls are paid out. When a game ball is detected by the count switch 23, 15 prize balls are paid out. Specifically, the game control microcomputer 560 determines that the prize ball number command “03” indicates that when the number of prize balls is three, the number of prize balls is three, according to the number of prize balls to be paid out. When the number of prize balls is 10, a prize ball number command “0A” indicating that the number of prize balls is 10, and when the number of prize balls is 15, the number of prize balls is A prize ball number command “0F” indicating 15 is transmitted.

  When the transmission of the award ball number command is completed, the serial communication circuit 505 of the game control microcomputer 560 makes a transmission interrupt request to the CPU 56 of the game control microcomputer 560 as shown in FIG. Due to the transmission interrupt request, the CPU 56 recognizes that the transmission of the award ball number command has been completed, and waits for a reception confirmation signal from the payout control microcomputer.

  When the payout control microcomputer 370 confirms reception of the prize ball number command, it stores the number of prize balls indicated in the received prize ball number command in the reception buffer of the payout control microcomputer 370. Also, the payout control microcomputer 370 adds the number of prize balls to a prize ball non-payout number counter provided in a predetermined area of the RAM. Then, the payout control microcomputer 370 transmits a prize ball ACK command “D2” to the game control microcomputer 560. The payout control microcomputer 370 may store the number of prize balls in the reception counter in the interrupt process based on the interrupt request upon reception from the serial communication circuit 380 built in the payout control microcomputer 370. In this case, when the serial communication circuit 380 built in the payout control microcomputer 370 receives the prize ball number command, it makes an interrupt request upon reception to the CPU of the payout control microcomputer 370. Then, the CPU of the payout control microcomputer 370 stores the prize ball number in the reception buffer by executing an interrupt process in response to an interrupt request from the serial communication circuit 380.

  When the prize ball ACK command is received and the prize data ACK command is stored in the reception data register 711, the serial communication circuit 505 of the game control microcomputer 560, as shown in FIG. A reception interrupt request is made to the CPU 56 of 560. The CPU 56 recognizes that the data has been received by the serial communication circuit 505 by executing the interrupt process based on the interrupt request at the time of reception. Read.

  In the loop process from step S17 to step S19 in the main process, the CPU 56 of the game control microcomputer 560 receives an interrupt request from the serial communication circuit 505 while it is in the interrupt enabled state. Execute interrupt processing according to the interrupt cause. FIG. 56 is a flowchart showing an example of interrupt processing performed by the serial communication circuit 505 in response to an interrupt request. FIG. 56A shows a communication error interrupt process executed by the CPU 56 when the serial communication circuit 505 makes an interrupt request with a communication error as a cause of interruption. FIG. 56B shows a reception interrupt process executed by the CPU 56 when an interrupt request is issued with the cause of the interruption that the serial communication circuit 505 has received the received data. FIG. 56C shows a transmission completion interrupt process executed by the CPU 56 when an interrupt request is issued with the cause of the interruption that the serial communication circuit 505 has completed transmission of transmission data.

  The CPU 56 determines whether or not any interrupt process is preferentially executed. For example, the CPU 56 determines whether or not any interrupt process is preferentially executed. In this embodiment, the CPU 56 gives priority to an interrupt process that causes the occurrence of a communication error in the serial communication circuit 505 based on the fact that the communication error interrupt priority execution flag is set. And execute.

  When there is an interrupt request from the serial communication circuit 505, the CPU 56 checks each bit of the status register A 705 of the serial communication circuit 505 to identify the cause of the interrupt. In this case, the CPU 56 determines whether or not any interrupt process is preferentially executed. For example, the CPU 56 determines whether or not any interrupt process is preferentially executed. In this embodiment, the CPU 56 gives priority to an interrupt process that causes the occurrence of a communication error in the serial communication circuit 505 based on the fact that the communication error interrupt priority execution flag is set. And execute.

  The CPU 56 preferentially checks bit 0 to bit 3 of the status register A705 based on the fact that the communication error interrupt priority execution flag is set, and identifies the cause of the interrupt. That is, the CPU 56 determines whether another interrupt cause (reception of received data has been received) as to whether or not an interrupt request has occurred due to the occurrence of a communication error (overrun, noise error, framing error or parity error) in the serial communication circuit 505. Or, determination is performed with priority over transmission data transmission completion). If the CPU 56 determines that one or more of the bits 0 to 3 of the status register A 705 is “1”, the CPU 56 specifies that the cause of the interruption is that a communication error has occurred in the serial communication circuit 505. To do.

  If it is determined that the cause of the interruption is that a communication error has occurred in the serial communication circuit 505, the CPU 56 changes the communication error interrupt process shown in FIG. 56A to another interrupt process (FIG. 56B and FIG. 56). It is executed with priority over the interrupt processing shown in (c). In this case, the CPU 56 sets a communication error flag indicating that a communication error has occurred in the serial communication circuit 505 (step S41).

  When a communication error is detected, the CPU 56 sends a communication error occurrence display designation effect control command (communication error display command) to notify the effect control means that a communication error has occurred in the serial communication circuit 505. Perform the process. When the sound / lamp control CPU 100b receives the communication error display command, the sound / lamp control CPU 100b performs an effect using a sound, a light emitter, and the like, and notifies that a communication error has occurred. The symbol control CPU 100a may notify that a communication error has occurred using the variable display device 9 based on the communication error display command received via the sound / lamp control board 80b. .

  If the cause of the interruption is not the occurrence of a communication error in the serial communication circuit 505, the CPU 56 confirms bit 5 of the status register A. That is, the CPU 56 determines whether or not the cause of the interrupt is that the serial communication circuit 505 has received the received data. When determining that the bit 5 of the status register A is “1”, the CPU 56 specifies that the cause of the interruption is that the serial communication circuit 505 has received the reception data.

  If it is determined that the cause of the interruption is that the serial communication circuit 505 has received the received data, the CPU 56 executes a reception interrupt process shown in FIG. In this case, the CPU 56 sets a reception interrupt flag indicating that the serial communication circuit 505 is receiving reception data (step S42).

  In step S42, the CPU 56 may set a reception interrupt flag and read data from the reception data register 711 of the serial communication circuit 505. In this case, for example, the CPU 56 determines whether or not the read received data is a prize ball ACK command. If it is determined that the prize ball ACK command is received, the CPU 56 sets a prize ball ACK reception flag indicating that the prize ball ACK command has been received.

  If the cause of the interrupt is not the occurrence of a communication error in the serial communication circuit 505, the CPU 56 checks bit 6 of the status register A. That is, the CPU 56 determines whether or not the cause of the interrupt is that the serial communication circuit 505 has completed transmission of transmission data. When determining that the bit 6 of the status register A is “1”, the CPU 56 specifies that the cause of the interruption is that the serial communication circuit 505 has completed transmission of transmission data.

  When it is determined that the cause of the interruption is that the serial communication circuit 505 has completed transmission of transmission data, the CPU 56 executes a transmission completion interrupt process shown in FIG. In this case, the CPU 56 sets a transmission interrupt flag indicating that the serial communication circuit 505 has completed transmission of transmission data (step S43).

  By executing the processing described above, the CPU 56 of the game control microcomputer 560 identifies an interrupt cause when an interrupt request is received from the serial communication circuit 505, and a flag corresponding to the identified interrupt cause. (Communication error flag, reception interrupt flag or transmission interrupt flag) is set. When the flag is set according to the specified interrupt cause, the CPU 56 recognizes that a communication error has occurred in the serial communication circuit 505, that data has been received, or that data transmission has been completed.

  Note that the CPU mounted on the payout control microcomputer 370 also identifies the cause of the interrupt according to the same process as the process shown in FIG. 56 when an interrupt request is received from the serial communication circuit 380, and the identified interrupt cause. Set the flag according to.

  For example, consider a case where a prize ball number command is transmitted from the game control microcomputer 560 to the payout control microcomputer 370 by one-way communication. In this case, the game control microcomputer 560 is configured to generate a timer interrupt to the payout control microcomputer 370, for example, every 2 ms. After the prize ball number command is transmitted, the next interrupt process is performed. Assume that the award ball number command is transmitted again after 2 ms. The payout control microcomputer 370 is configured to generate a timer interrupt every 4 ms, for example, and can receive a prize ball number command every 4 ms. Then, even though the game control microcomputer 560 has not read the first prize ball number command transmitted, the payout control microcomputer 370 may receive the next prize ball number command. If the CPU of the payout control microcomputer 370 is set to receive the award ball number command in response to the interrupt request at the time of reception from the serial communication circuit 380, the award ball number command from the game control microcomputer 560 is surely received. Can be received.

  In the prize ball processing, a prize ball number table shown in FIG. 57 is used. The prize ball number table is set in the ROM 54. The number of processes (in this example, “3”) is set at the start address of the prize ball number table, and thereafter, a prize ball command output counter and prize ball designation data for designating the number of prize balls are set in sequence. Yes. The prize ball command output counter is a counter that counts the number of prizes received in the prize opening, and is set in the ROM 54, for example. The game control microcomputer 560 includes a corresponding prize ball command output counter for each number of prize balls (0 to 15). In this embodiment, the game control microcomputer 560 includes a prize ball command output counter 1 corresponding to the number of prize balls “3”, a prize ball command output counter 2 corresponding to the number of prize balls “10”, and a prize ball. And a prize ball command output counter 3 corresponding to the number “15”. Each prize ball command output counter is counted up in the input determination process of the timer interrupt process, as will be described later.

  FIG. 58 is a flowchart showing the prize ball processing. In the prize ball process, the CPU 56 executes any one of steps S1231 to S1235 according to the value of the prize ball process code.

  FIG. 59 is a flowchart showing a prize ball number command transmission process (step S1231) executed when the value of the prize ball process code is zero. In the winning ball number command transmission process, the CPU 56 checks whether or not an error flag is set (step S1241). In this case, the CPU 56 checks whether or not the communication error flag is set. That is, the CPU 56 first checks whether or not a communication error has occurred in the serial communication circuit 505. When the communication error flag is set, the CPU 56 ends the process as it is. That is, since a communication error has occurred in the serial communication circuit 505, the CPU 56 controls to prohibit communication with the payout control microcomputer 370 mounted on the payout control board 37.

  In step S1241, the CPU 56 confirms whether or not a prize ball excess abnormality error flag or a prize ball underabnormality error flag indicating that a prize ball abnormality has occurred is set. In this embodiment, as will be described later, in the prize ball abnormality detection process, when the occurrence of excessive prize balls is detected, an excessive prize ball error error flag is set. If the excessive prize ball error error flag is set, the CPU 56 ends the process. That is, since there is an excess of prize balls, the CPU 56 controls to prohibit the sending of prize ball number commands to the payout control microcomputer 370. In addition, in the prize ball abnormality detection process, when the occurrence of a prize ball shortage is detected, a prize ball underball abnormality error flag is set. If the prize ball under / abnormal error flag is set, the CPU 56 ends the process. In other words, since there is an abnormal shortage of prize balls, the CPU 56 controls to prohibit the sending of the prize ball number command to the payout control microcomputer 370.

  If the error flag is not set, the CPU 56 sets the start address of the prize ball number table in the pointer (step S1242). Then, the data at the address pointed to by the pointer (in this case, the number of processes) is loaded (step S1243). Next, the CPU 56 loads the contents of the winning ball number command buffer for setting the winning ball number command to be transmitted to the payout control microcomputer 370 (step S1244). Then, based on the loaded contents, it is confirmed whether or not the winning ball number command to be transmitted to the payout control microcomputer 370 is already set in the winning ball number command buffer (step S1245).

  If no prize ball number command is set in the prize ball number command buffer (for example, if the loaded value is 0), the CPU 56 increments the value of the pointer by 1 (step S1246) and outputs the prize ball command indicated by the pointer. A count value of a counter (a prize ball command output counter indicated as data in the prize ball number table) is loaded (step S1247). If a winning ball number command has already been set in the winning ball number command buffer, the process proceeds to step S1254.

  Next, the CPU 56 checks whether or not the loaded count value is 0 (step S1248). If the count value is 0, the process proceeds to step S1252 as it is. If the count value is not 0, the CPU 56 increments the value of the pointer by 1 (step S1249), and loads data in the prize ball number table pointed to by the pointer (in this case, the prize ball number indicated in the prize ball designation data). (Step S1250). Further, the CPU 56 stores the loaded number of winning balls as a winning ball number command in the winning ball number command buffer (step S1251). In step S1252, the number of processes is reduced by 1, and if the number of processes is not 0, the process returns to step S1246 (step S1253).

  If the winning ball number command has already been set in step S1245, or if the processing number is 0 in step S1253, the CPU 56 reads the winning ball number command from the winning ball number command buffer, and receives the winning ball number command. Is written in the transmission data register 710 of the serial communication circuit 505 (step S1254). Then, the CPU 56 sets the value of the prize ball process code to 1 (step S1255), and ends the process.

  FIG. 60 is a flowchart showing a prize ball transmission completion waiting process (step S1232) executed when the value of the prize ball process code is 1. In the award ball transmission completion waiting process, the CPU 56 checks whether or not an error flag is set (step S1261). In this case, the CPU 56 checks whether or not the communication error flag is set. That is, the CPU 56 first checks whether or not a communication error has occurred in the serial communication circuit 505. When the communication error flag is set, the CPU 56 ends the process as it is. That is, since a communication error has occurred in the serial communication circuit 505, the CPU 56 controls to prohibit communication with the payout control microcomputer 370 mounted on the payout control board 37.

  In step S1261, the CPU 56 confirms whether or not a prize ball excess abnormality error flag or a prize ball underabnormality error flag indicating that a prize ball abnormality has occurred is set. When the prize ball excess abnormality error flag or the prize ball excess abnormality error flag is set, the CPU 56 ends the process as it is. That is, since there is an excessive number of winning balls or an abnormal winning ball, the CPU 56 controls to prohibit the sending of the winning ball number command to the payout control microcomputer 370.

  If the error flag is not set, the CPU 56 checks whether or not the transmission interrupt flag is set (step S1262). If the transmission interrupt flag is set, the CPU 56 proceeds to the process of step S1263. If the transmission interrupt flag is not set, the CPU 56 ends the process as it is. That is, the CPU 56 determines whether the serial communication circuit 505 has already completed transmission of the prize ball number command written in the transmission data register 710 in the prize ball number command transmission process, and has completed transmission of the prize ball number command. If this is confirmed, the process after step S1263 is performed.

  If the transmission interrupt flag is set, the CPU 56 resets the transmission interrupt flag (step S1263). Further, the CPU 56 sets an ACK reception completion determination time value in the prize ball timer (step S1264). Then, the value of the prize ball process code is set to 2 (step S1265), and the process is terminated. The ACK reception completion determination time value is a time value for monitoring whether or not a prize ball ACK command is received from the payout control means.

  FIG. 61 is a flowchart showing a prize ACK waiting process (step S1233) executed when the value of the prize ball process code is 2. In the award ball ACK waiting process, the CPU 56 checks whether or not an error flag is set (step S1271). In this case, the CPU 56 checks whether or not the communication error flag is set. That is, the CPU 56 first checks whether or not a communication error has occurred in the serial communication circuit 505. When the communication error flag is set, the CPU 56 ends the process as it is. That is, since a communication error has occurred in the serial communication circuit 505, the CPU 56 controls to prohibit communication with the payout control microcomputer 370 mounted on the payout control board 37.

  Further, in step S1271, the CPU 56 checks whether or not a prize ball excessive error error flag or a prize ball under error error flag indicating that a prize ball abnormality has occurred is set. When the prize ball excessive error flag or the prize ball under error flag is set, the CPU 56 ends the process as it is. That is, since there is an excessive number of winning balls or an abnormal winning ball, the CPU 56 controls to prohibit the sending of the winning ball number command to the payout control microcomputer 370.

  If the error flag is not set, the CPU 56 checks whether or not the reception interrupt flag is set (step S1272). That is, the CPU 56 checks whether or not the serial communication circuit 505 receives the received data and the received data register 711 stores the data. If the reception interrupt flag is set, the CPU 56 proceeds to the process of step S1273. On the other hand, if the reception interrupt flag is not set, the CPU 56 proceeds to the process of step S1275.

  If the reception interrupt flag is set, the CPU 56 reads data from the reception data register 711 of the serial communication circuit 505 (step S1273). Further, the CPU 56 determines whether or not the read data is a prize ball ACK command (whether or not it is a command “D2”) (step S1274).

  In the reception interrupt process shown in FIG. 56 (b), when the reception interrupt flag is set and the reception data has already been read from the reception data register 711, the CPU 56 receives the prize ball in steps S1273 and S1274. It may be determined whether or not an ACK reception flag is set. When the prize ball ACK reception flag is set, the CPU 56 may determine that the prize ball ACK command has been received.

  If the reception interrupt flag is not set in step S1272, or if the data read in step S1274 is not a prize ball ACK command, the CPU 56 still receives a prize ball ACK command from the payout control microcomputer 370. Judge that it is not in the state. In this case, the CPU 56 decreases the value of the prize ball timer by 1 (step S1275), and if the value is not 0, the process ends (step S1276). When the value of the prize ball timer reaches 0, it is determined that the payout control microcomputer 370 has not transmitted the prize ball ACK command, a retransmission flag is set (step S1277), and the value of the prize ball process code is set to 3. (Step S1278), and the process ends. When the value of the prize ball process code becomes 3, the prize ball re-transmission process (step S1234) is executed. When the retransmission flag is set, a payout abnormality notification start command is transmitted to the sound / lamp control board 80b in the prize ball abnormality detection process (step S1235).

  In step S1274, when confirming that the data read from the reception data register 711 is a prize ball ACK command, the CPU 56 resets the reception interrupt flag (step S1279) and sets the value of the prize ball process code to 4. (Step S1280).

  Next, the CPU 56 sets the interrupt prohibited state (step S1281), and loads the contents of the total winning ball number storage buffer (step S1282). Note that the total number of winning balls is a buffer for storing the total number of winning balls (total number of winning balls) that have been paid out but have not been paid out. When the content of the total prize ball number storage buffer is loaded, the CPU 56 obtains the number of prize balls corresponding to the prize ball number command transmitted in the prize ball number command transmission process, and the contents of the loaded total prize ball number storage buffer (total prize balls). Number) (step S1283). In this embodiment, the CPU 56 adds any one of 3, 10 or 15 prize balls to the contents of the loaded total prize ball number storage buffer according to the prize ball number command.

  Next, the CPU 56 stores the result of adding the total number of winning balls in the total winning ball number storage buffer (step S1284), and sets the interrupt permitted state again (step S1285). If the retransmission flag is set because the communication has been normally completed, the retransmission flag is reset (steps S1286 and S1287).

  By the above processing, the game control means stores the total number of game balls as prize balls to be paid out based on the establishment of the payout condition in the total prize ball number storage buffer so as to be specified. Further, the game control means transmits a payout command command (award ball number command) for designating a payout number of a predetermined number of prize balls to the payout control means based on the number of prize balls corresponding to the prize ball command output counter. . Then, when a prize ball number command designating the prize ball payout is transmitted, an addition process for adding the number of prizes designated by the prize ball number command to the prize ball number stored in the total prize ball number storage buffer is performed. Since the payout control microcomputer 370 transmits a prize ball ACK command immediately after receiving the prize ball number command, communication regarding the prize ball number command can be completed regardless of the prize ball payout from the ball payout device 97. The control microcomputer 560 can continuously transmit the next prize ball number command before completing the payout of the number of prizes designated by the prize ball number command.

  In addition, in the processing of steps S1281 to S1285, when the total number of winning balls is read from the total winning ball number storage buffer when the number of winning balls indicated in the winning ball number command is added to the total number of winning balls, Execution of timer interrupt processing is prohibited until the number of winning balls is written to the total winning ball number storage buffer. Therefore, it is possible not to execute the process of subtracting the paid-out prize ball number from the total prize ball number between the time of reading the total prize ball number from the total prize ball number storage buffer and writing it again. It is possible to prevent a situation in which the game control means cannot grasp the number of prize balls that have been paid out.

  For example, as will be described later, when the payout is performed, the game control means is detected by the payout count switch from the total number of winning balls stored in the total winning ball number storage buffer in the input determination process of the timer interruption process. Subtract the number of payouts. In this case, if the payout process is performed between the time of reading the total number of winning balls from the total number of winning balls storage buffer and the time of writing again in the winning ball processing, the game control means determines that the total number of winning balls is the total number of winning balls. There is a risk that the subtraction process may be executed by timer interruption before being stored in the number storage buffer. For this reason, the total number of winning balls after the addition (the total number of winning balls in which the subtraction amount is not reflected) is overwritten in the total winning ball number storage buffer, and the subtraction amount due to payout may not be correctly reflected in the total number of winning balls. There is. In this embodiment, since the timer interruption process is prohibited until the total number of winning balls after the addition is written to the total winning ball number storage buffer, the subtraction due to payout cannot be correctly reflected in the total number of winning balls. It is possible to prevent such a situation that the game control means cannot grasp the number of prize balls that have been paid out.

  FIG. 62 is a flowchart showing the prize ball re-transmission process (step S1234) executed when the value of the prize ball process code is 3. The CPU 56 checks whether or not an error flag is set in the winning ball re-transmission process (step S1291). In this case, the CPU 56 checks whether or not the communication error flag is set. That is, the CPU 56 first checks whether or not a communication error has occurred in the serial communication circuit 505. When the communication error flag is set, the CPU 56 ends the process as it is. That is, since a communication error has occurred in the serial communication circuit 505, the CPU 56 controls to prohibit communication with the payout control microcomputer 370 mounted on the payout control board 37.

  In step S1291, the CPU 56 confirms whether or not a prize ball excess abnormality error flag or a prize ball underabnormality error flag indicating that a prize ball abnormality has occurred is set. When the prize ball excess abnormality error flag or the prize ball excess abnormality error flag is set, the CPU 56 ends the process as it is. That is, since there is an excessive number of winning balls or an abnormal winning ball, the CPU 56 controls to prohibit the sending of the winning ball number command to the payout control microcomputer 370.

  If the error flag is not set, the CPU 56 rewrites the prize ball number corresponding to the prize ball number command transmitted in the prize ball number command transmission process in the transmission data register 710 of the serial communication circuit 505 as the prize ball number command. (Step S1292). Further, the CPU 56 sets the ACK reception completion determination time value in the prize ball timer again (step S1293). Then, the value of the prize ball process code is set to 2 (step S1294), and the process ends.

  Since the value of the prize ball process code is set to 2, the prize ball ACK waiting process is executed again. In the award ball ACK waiting process to be executed again, if it is not detected that the award ball ACK command has been received again, specifically, if the award ball timer times out in step S1276, the award ball again A retransmission process is executed. As described above, when the game control microcomputer 560 cannot receive the winning ball ACK command as the reception confirmation signal indicating that the payout amount data has been received, the winning ball number command is received until the winning ball ACK command can be received. Repeat retransmissions.

  FIG. 63 is a flowchart showing the prize ball abnormality detection processing in step S1235. In the prize ball abnormality detection process, when the CPU 56 detects that the retransmission flag has changed from the reset state to the set state, the CPU 56 uses the payout abnormality notification start command as an effect control command to the sound / lamp control board 80b (specifically, Is transmitted to the sound / lamp control microcomputer 100b (steps S1301 and S1302). The CPU 56 does not transmit the payout abnormality notification start command after executing the prize ball retransmission process, but transmits the payout abnormality notification start command to the sound / lamp control board 80b and then executes the prize ball retransmission process. You may make it do.

  When transmitting the effect control command to the sound / lamp control microcomputer 100b, the CPU 56 pointers the address of a command transmission table (preliminarily set for each command in the ROM 54) according to the type of effect control command. Set to. Then, the address of the command transmission table corresponding to the effect control command is set in the pointer, and the effect control command is transmitted in the command control process (step S19b).

  Further, the CPU 56 detects that the re-transmission flag is changed from the set state to the reset state (therefore, it is detected only when the reset state is first set when the set state continues). Then, control is performed to transmit a payout abnormality notification end command to the sound / lamp control board 80b (specifically, to the sound / lamp control microcomputer 100b) (steps S1303 and S1304).

  In this embodiment, when the retransmission flag is reset, the CPU 56 transmits a payout abnormality notification end command in step S1304, but may be configured not to transmit it. In this case, the burden on the game control microcomputer 560 is reduced. In that case, the sound / lamp control microcomputer 100b is configured to terminate the payout abnormality notification independently after a predetermined time, for example.

  Further, the CPU 56 confirms whether or not the total number of winning balls stored in the total winning ball number storage buffer is smaller than a predetermined payout excess determination value (step S1305). Further, when the total number of winning balls is smaller than a predetermined excessive payout determination value, the CPU 56 determines that an excessive excessive amount of winning balls has occurred, and an excessive excessive amount of winning balls indicating that an excessive excessive amount of winning balls has occurred. The command is transmitted to the sound / lamp control board 80b and the payout control board 37 (step S1306). In this embodiment, when the CPU 56 determines that the total number of winning balls stored in the total winning ball number storage buffer is smaller than “−499” (that is, 500 or less), the CPU 56 has more than the number of winning balls to be paid out. It is determined that there is an excess of prize balls from which game balls are paid out.

  In step S1306, when transmitting the effect control command (excessive ball excess abnormality command) to the sound / lamp control microcomputer 100b, the CPU 56 sends a command transmission table (commands to the ROM 54 in advance according to the type of effect control command). Set to the pointer. Then, the address of the command transmission table corresponding to the effect control command is set in the pointer, and the effect control command is transmitted in the command control process (step S19b).

  In step S1306, when transmitting an excessive prize ball abnormality command to the payout control microcomputer 370, the CPU 56 receives an excessive prize ball abnormality command (specifically “E1”) indicating that an excessive prize ball abnormality has occurred. ) Is written in the transmission data register 710 of the serial communication circuit 505. The serial communication circuit 505 transmits an excessive prize ball abnormality command “E1” to the payout control microcomputer 370.

  When the excessive prize ball abnormality command is transmitted, the CPU 56 sets an excessive prize ball error error flag indicating that an excessive prize ball abnormality has occurred (step S1307) and sets the value of the prize ball process code to 0 (step S1308). ), The process is terminated.

  If the total number of winning balls is not smaller than the predetermined payout excess determination value in step S1305, the CPU 56 determines whether or not the total number of winning balls stored in the total winning ball number storage buffer is larger than the predetermined payout underdetermination determination value. (Step S1305a). If the total number of winning balls is larger than a predetermined payout underdetermined value, the CPU 56 determines that an award ball underabnormality has occurred, and an award ball underabnormality indicating that a prize ball underabnormality has occurred. The command is transmitted to the sound / lamp control board 80b and the payout control board 37 (step S1305b). In this embodiment, when the CPU 56 determines that the total number of winning balls stored in the total winning ball number storage buffer is larger than “2000” (corresponding to the number of winning balls to be paid out per jackpot), the CPU 56 should pay out. It is determined that a prize ball under-abnormality has occurred, in which only game balls are paid out less than the number of prize balls.

  In step S1305b, when transmitting the effect control command (prize ball under / abnormal command) to the sound / lamp control microcomputer 100b, the CPU 56 sends a command transmission table corresponding to the type of effect control command (command to the ROM 54 in advance). Set to the pointer. Then, the address of the command transmission table corresponding to the effect control command is set in the pointer, and the effect control command is transmitted in the command control process (step S19b).

  In step S1305b, when transmitting a prize ball underabnormality command to the payout control microcomputer 370, the CPU 56 issues a prize ball underabnormality command (specifically, “E2”) indicating that a prize ball underabnormality has occurred. ) Is written in the transmission data register 710 of the serial communication circuit 505. The serial communication circuit 505 transmits an award ball under-abnormality command “E2” to the payout control microcomputer 370.

  When the prize ball under-abnormality command is transmitted, the CPU 56 sets a prize-ball under-abnormality error flag indicating that a prize ball under-abnormality has occurred (step S1305c), and sets the value of the prize ball process code to 0 (step S1308). ), The process is terminated.

  Next, the special symbol process (step S19d) in the main process will be described. FIG. 64 is a flowchart showing an example of a special symbol process processing program executed by the CPU 56 of the game control microcomputer 560. When the CPU 56 of the game control microcomputer 560 performs the special symbol process, the variation shortening timer subtraction process (step S310) is performed, and the game ball is won in the start winning opening 14 provided in the game board 6. If the start opening switch 14a for detecting the game is turned on, that is, if the game ball has won the start winning opening 14 and the winning detection signal SS is input from the start opening switch 14a (step S311), the start opening switch passes. After performing the process (step S312), any one of steps S300 to S308 is performed according to the internal state. The variation shortening timer is a timer for setting the variation time when the variation time of the special symbol is shortened.

  If the start port switch 14a has not been turned on in step S311, the CPU 56 clears an interrupt counter, which will be described later, and then performs any one of steps S300 to S308 according to the internal state. I do.

  Special symbol normal processing (step S300): A state where variable symbol special display can be started (for example, the symbol variation has not been made in the special symbol display 8, and the previous symbol variation in the special symbol display 8 has ended) Wait for a predetermined period of time to elapse, and not a big hit game). When the special symbol variable display can be started, the start winning memory number for the special symbol is confirmed. If the start winning memorization number is not 0, it is determined whether or not the result of variable symbol special display is a big hit based on the random R generated by the random number circuit 503 stored in the special figure holding memory 570. Then, the internal state (special symbol process flag) is updated so as to shift to step S301.

  Special symbol stop symbol setting process (step S301): A stop symbol after variable display of the special symbol is determined. Then, the internal state (special symbol process flag) is updated so as to shift to step S302.

  Variation time setting process (step S302): A variation pattern is determined, and variation time in the variation pattern (variable display time: time from when variable display is started until display result is derived and displayed (stop display)) is a special symbol. It is determined to be a variable display variable time. In addition, a variation time timer that measures the variation time of the determined special symbol is started. Then, the internal state (special symbol process flag) is updated so as to shift to step S303.

  Special symbol variation process (step S303): When a predetermined time (the time indicated by the variation time timer in step S302) elapses, the internal state (special symbol process flag) is updated to shift to step S304.

  Special symbol stop process (step S304): A decorative symbol stop command for instructing stop of the decorative symbol is transmitted to the sound / lamp control board 80b. Moreover, the special symbol in the special symbol display 8 is stopped. If the stop symbol of the special symbol is a big hit symbol, the internal state (special symbol process flag) is updated to shift to step S305. If not, the internal state is updated to shift to step S300. Note that a configuration in which a decorative symbol stop command is not transmitted may be employed. In this case, the symbol control board 80a sets the fluctuation time in the fluctuation time timer based on the fluctuation pattern command received from the main board 31 via the sound / lamp control board 80b, and updates the fluctuation time timer. It is only necessary to monitor the variation time of the decorative pattern by going and to stop the decorative symbol when it is determined that the variation time has elapsed.

  Preliminary winning opening opening process (step S305): Control for opening the large winning opening is started. Specifically, a counter (for example, a counter that counts the number of game balls that have entered the big winning opening) and a flag (a flag used when detecting winning in the winning opening) are initialized, and the solenoid 21 is driven. Open the big prize opening. Also, the process timer sets the execution time of the big prize opening opening process and sets the big hit flag. Then, the internal state (special symbol process flag) is updated so as to shift to step S306.

  Processing for opening a special prize opening (step S306): control for sending a presentation control command for round display of the special prize opening to the sound / lamp control board 80b and conditions for closing the special prize opening (for example, a predetermined number (for example, a special prize opening) A process of confirming that 10) gaming balls have won) is performed. When the closing condition of the big prize opening is satisfied, the internal state is updated to shift to step S307.

  Specific area valid time process (step S307): A process of confirming that the big hit gaming state continuation condition is satisfied is performed. If the condition for continuing the big hit gaming state is satisfied and there are still remaining rounds, the internal state is updated to shift to step S305. When all the rounds are finished, the internal state is updated so as to shift to step S308. When the V winning area is provided, the presence / absence of the V winning switch is monitored to perform processing for confirming that the big hit gaming state continuation condition is satisfied.

  Big hit end processing (step S308): Control for causing the effect control means to perform display control for notifying the player that the big hit gaming state has ended. Then, the internal state is updated so as to shift to step S300.

  FIG. 65 is a flowchart showing the start port switch passage process (step S312). In the start port switch passing process, the CPU 56 of the game control microcomputer 560 sets the start winning memory number indicated by the start winning counter (or the start winning memory number stored in the special figure holding memory 570) to 4 which is the maximum value. It is confirmed whether it has reached (step S321). If the start winning memorized number has not reached 4, the CPU 56 checks whether or not the number of executions of the timer interrupt process indicated by the interrupt execution number counter has reached a predetermined number (for example, three times) (step) S322). In other words, the CPU 56 checks whether or not the interrupt execution counter has reached a predetermined number after the game ball has won the start winning opening 14. When it is detected that the game ball has won the start winning opening 14 (that is, when YES is determined in step S322), the CPU 56 resets the interrupt execution counter.

  The interrupt execution number counter is a counter for counting the number of times the timer interrupt process has been executed. In this embodiment, the CPU 56 counts up an interrupt number counter indicating the number of times the timer interrupt process has been executed when executing a timer interrupt process to be described later.

  The value set in advance as the predetermined number of times in step S322 is determined as follows. As described above, the timer circuit 534 of the random number circuit 503 measures the time that the winning detection signal SS is continuously input from the start port switch 14a, and detects that the measurement time has reached a predetermined period, Write numerical value capture data “01h”. In this embodiment, a predetermined period (for example, 3 ms) measured by the timer circuit 534 is a period in which a predetermined number of timer interrupt processes are executed (for example, when the timer interrupt process for every 2 ms is executed three times). The predetermined number of times (for example, 3 times) used in step S322 is set so as to be shorter than 6 ms. By setting as such, it is possible to prevent the random number from being read again after the random number is read and before the random number value stored in the random value storage circuit 531 is updated. It is possible to prevent a random number having the same value as the random number read from the circuit 531 from being read again. The timer circuit 534 does not measure the input time of the winning detection signal SS, but the CPU 56 measures the input time of the winning detection signal SS and writes the random number value fetch data “01h” into the random value fetch register 539. May be.

  When the number of executions of the timer interrupt process has reached a predetermined number, the CPU 56 can output the output control signal SC to the random number storage circuit 531 of the specified random number circuit 503 and read the random number storage circuit 531 (enable). The state is controlled (step S323).

  The CPU 56 reads the random R value stored as the random number value from the random number value storage circuit 531 of the random number circuit 503 (step S324). Further, the CPU 56 stores the read random R value in a storage area (special symbol determination buffer (special symbol holding memory 570)) corresponding to the value of the start winning memorized number (step S325). Further, when the random value R is stored in the buffer area, the CPU 56 stops outputting the output control signal SC to the random value storage circuit 531 and controls the random value storage circuit 531 to be in a non-readable (disabled) state (step). S326). In addition, the CPU 56 resets the interrupt execution number counter (step S327). Then, the CPU 56 sets the value of the random R stored in the predetermined buffer area to the head of the empty entry in the special figure holding memory 570 (step S328), and adds 1 to the count number of the start winning counter, thereby storing the start winning memory. The number is incremented by 1 (step S329).

  If the start prize is stored in step S321 but the maximum value of 4 has been reached, and if the number of executions of the timer interrupt process has not reached the predetermined number in step S322, the start port switch passing process is terminated.

  As described above, the timer interrupt process has been executed a predetermined number of times in reading the random R from the random value storage circuit 531 in the starting port switch passing process (that is, continued while the timer interrupt process is executed a predetermined number of times). The random number is read from the random value storage circuit 531 on the condition that the winning detection signal SS is input). Therefore, it is possible to prevent the random number from being read again after the random number is read and before the value of the random number stored in the random value storage circuit 531 is updated. Further, it is possible to prevent a random number having the same value as the random number read from the previous random number value storage circuit 531 from being read again.

  Next, the special symbol normal process (step S300) in the special symbol process will be described. FIG. 66 is a flowchart showing special symbol normal processing. In the special symbol normal process, the CPU 56 of the game control microcomputer 560 can start the variation of the special symbol (for example, when the value of the special symbol process flag is a value indicating step S300). (Step S380), the random R value stored in correspondence with the hold number “1” is read from the special figure hold memory 570 (Step S381). In this case, the CPU 56 decrements the count of the start winning counter by 1 to reduce the reserved memory count by 1, and the second to fourth entries of the special figure hold memory 570 (hold numbers “2” to “4”). The value of random R stored in is shifted upward by one entry (step S382).

  Further, the CPU 56 confirms whether or not the probability variation flag is set (step S383). That is, the CPU 56 confirms whether or not the gaming state is controlled to the certain change state. When the probability variation flag is not set, the CPU 56 determines that the gaming state is a normal state other than the probability variation state, and is a table used to determine whether or not the display result of the special symbol display device 8 is a jackpot symbol. The normal big hit determination table 571a (see FIG. 39A) is set (step S384). Further, when the probability change flag is set, the CPU 56 determines that the gaming state is a probability change state, and as a table used to determine whether or not the display result of the special symbol display device 8 is a jackpot symbol. A probability change big hit determination table 571b (see FIG. 39B) is set (step S385).

  The CPU 56 determines whether or not the display result of the special symbol display device 8 is a big hit symbol based on the random R value stored in the predetermined buffer area in the start port switch passing process (step S386). In this case, the CPU 56 uses the normal-time big hit determination table 571a set in step S384 or the probability change big hit determination table 571b set in step S385 to determine whether or not to win.

  If it is determined that the display result of the special symbol display device 8 is a jackpot symbol, the CPU 56 turns on a jackpot flag indicating that it is a jackpot state (step S387). If it is determined that the display result of the special symbol display device 8 is not a big hit symbol, the CPU 56 turns off the big hit flag (step S388). Then, the CPU 56 updates the value of the special symbol process flag to a value corresponding to the special symbol stop symbol setting process (step S389).

  Next, the timer interrupt process will be described. FIG. 67 is a flowchart showing the timer interrupt process. When a timer interrupt occurs during execution of the main process, specifically, during a period in which the interrupt is permitted during the execution of the loop process of steps S17 to S19, the CPU 56 of the game control microcomputer 560 A timer interrupt process that is activated in response to the occurrence of a timer interrupt is executed. Further, the CPU 56 adds 1 to the count value of the interrupt counter. In the timer interrupt process, the CPU 56 first inputs detection signals of switches such as the gate switch 32a, the start port switch 14a, the count switch 23, and the winning port switches 29a, 30a, 33a, and 39a via the switch circuit 58. The input of each switch is detected (switch process: step S20). Specifically, if the state of the input port for inputting the detection signal of each switch is ON, the value of the switch timer provided corresponding to each switch is incremented by one. Further, the CPU 56 executes an input determination process for determining the input state of each switch based on the detection result of step S20 (step S21).

  Next, the CPU 56 checks whether the initial value is set to be updated when the count value is updated to a predetermined final value in the random number circuit setting process (see step S157), and the counter of the random number circuit 503 is checked. Processing for updating the initial value input to 521 is performed (random circuit initial value updating processing: step S22).

  Next, a process of updating the count value of each counter for generating each determination random number used for game control is performed (step S23). Further, the CPU 56 performs a process of updating the count value of the counter for generating the initial value random number (initial value random number update process: step S24). Further, the CPU 56 performs a process of updating the count value of the counter for generating the display random number (display random number update process: step S25).

  In step S23, the CPU 56 counts up (adds 1) a counter for generating random numbers such as a jackpot symbol determining random number, a normal symbol determining random number, a probability variation determining random number, a probability variation determining random number, and the like. Do. That is, they are determination random numbers, and other random numbers are display random numbers or initial value random numbers. Further, in order to enhance the gaming effect, random numbers related to ordinary symbols other than the random numbers shown above may be used.

  When the determination random number update process, the initial value update process, and the display random number update process are performed, the CPU 56 causes the count value permutation change circuit 523 to change the count value permutation output by the counter 521 of the random number circuit 503. Processing is performed (step S26). In this embodiment, whether or not to execute the count value permutation change process is determined depending on whether or not the count value permutation change flag is set in step S158 of the random number circuit setting process. Then, the CPU 56 executes the count value permutation change process based on the fact that the count value permutation change flag is set. Thereafter, the CPU 56 sets the interrupt permitted state (step S27) and ends the process.

  Next, the switch process (step S20) in the timer interrupt process will be described. In this embodiment, when the ON state of the detection signal of each switch related to winning detection or gate passage continues for a predetermined time, it is determined that the switch is surely turned on, and processing corresponding to the switch on is started. FIG. 68 is an explanatory diagram showing each 2-byte buffer formed in the RAM 55 used in the switching process. The previous port buffer is a buffer that stores the previous switch-on / off determination result (for example, 2 ms before). The port buffer is a buffer in which the contents of port 0 inputted this time are stored. The switch-on buffer is a buffer in which the corresponding bit is set to 1 when switch on is detected and the corresponding bit is set to 0 when switch off is detected.

  FIG. 69 is a flowchart illustrating a processing example of the switch processing in step S20 in the game control processing. In the switch process, the game control microcomputer 560 first inputs data input to the input ports 0 and 1 (see FIG. 42) (step S101), and sets the input data in the port buffer (step S102). ).

  Next, the initial value of the weight counter formed in the RAM 55 is set (step S103), and the value of the weight counter is decremented by 1 until the value of the weight counter becomes 0 (steps S104 and S105).

  When the value of the wait counter reaches 0, the data of the input ports 0 and 1 are input again (step S106), and a logical product is obtained for each bit between the input data and the data set in the port buffer. (Step S107). Then, the logical product operation result is set in the port buffer (step S108). Of the two pieces of input data input from the input ports 0 and 1 with a time interval of approximately [initial value of weight counter × (processing time of steps S104 and S105)] by the processing of steps S103 to S108, twice Only the bits that are both “1” become “1” in the port buffer. That is, if the ON state of the switch detection signal continues for the predetermined period [initial value of wait counter × (processing time of steps S104 and S105)], the corresponding bit in the port buffer becomes “1”.

  Further, the game control microcomputer 560 performs exclusive OR for each bit between the data previously set in the port buffer and the data set in the port buffer (step S109). In the result of the exclusive OR operation, the bit corresponding to the switch for which the previous switch-on / off determination result (for example, 2 ms before) and the switch-on / off determination result determined to be on this time are different is “ 1 ”. The game control microcomputer 560 further performs a logical product for each bit between the exclusive OR operation result and the data set in the port buffer (step S110). As a result, of the bits corresponding to the switches for which the previous switch on / off determination result and the switch on / off determination result determined to be on this time are different (according to the exclusive OR operation result), the current on Only the bit corresponding to the switch determined to be (by AND operation) remains as “1”.

  Then, the game control microcomputer 560 sets the logical product calculation result in step S110 in the switch-on buffer (step S111), and sets the contents of the port buffer in which the calculation result in step S108 is set in the previous port buffer. (Step S112).

  Through the above processing, among the switches that have been in the on state for a predetermined period of time, the switch on / off determination result of the previous time (for example, 2 ms ago) was off, that is, the switch has changed from the off state to the on state. The bit corresponding to the switch is “1” in the switch-on buffer.

  Next, the input determination process (step S21) in the timer interrupt process will be described. In the input determination process, a prize ball command output counter process table shown in FIG. 70 is used. The prize ball command output counter processing table is set in the ROM 54. The number of processes (“6” in this example) is set at the start address of the prize ball command output counter processing table, and then the switch-on buffer (the one corresponding to input port 0 of the 2-byte switch-on buffer) The lower address of, the switch input bit judgment value and the prize ball command output counter for each switch of the prize opening that will pay out the prize ball by winning are set in correspondence with each switch of the prize opening. . The switch input bit determination value is a value corresponding to a bit to which a detection signal of each switch at the input port 0 is input. The upper address of the switch-on buffer is a fixed value (for example, 7F (H)). In the prize ball command output counter processing table, the same data is set in each of the lower addresses of the six switch-on buffers. In this embodiment, the addresses of the ROM 54 and the RAM 55 are designated by 16 bits.

  71 and 72 are flowcharts showing the input determination process. In the input determination process, the CPU 56 sets the start address of the prize ball command output counter process table in the pointer (step S2111). Then, the data at the address pointed to by the pointer (in this case, the number of processes) is loaded (step S2112). Next, the upper address (8 bits) of the switch-on buffer is set in the upper 1 byte of the 2-byte check pointer (step S2113).

  Then, the pointer value is incremented by 1 (step S2114), and the data of the prize ball command output counter processing table pointed to by the pointer (in this case, the lower address of the switch-on buffer) is set in the lower 1 byte of the check pointer (step S2114). In step S2115, the pointer value is incremented by 1 (step S2116). Next, the address data pointed to by the check pointer, that is, the contents of the switch-on buffer is loaded into the register (step S2117), and the loaded contents and the data of the prize ball command output counter processing table pointed to by the pointer (in this case, the switch input) The logical product with the bit determination value) is calculated (step S2118). As a result, 7 bits other than the bit corresponding to the detection signal of the switch to be inspected become 0 in the register loaded with the contents of the switch-on buffer. Then, the pointer value is increased by 1 (step S2119).

  If the calculation result in step S2118 is 0, that is, if the detection signal of the switch to be inspected is on (step S2120), the prize ball command output counter pointed to by the pointer (data in the prize ball command output counter processing table) Is loaded (step S2121). Further, the CPU 56 adds 1 to the loaded count value (step S2122).

  Next, the CPU 56 checks whether or not the addition result is 256 (step S2123). If the addition result is not 256 (that is, 255 or less), the CPU 56 stores the addition result in the prize ball command output counter pointed to by the pointer (step S2124). If the addition result is 256, the CPU 56 proceeds to step S2125 without storing the addition result in the prize ball command output counter pointed to by the pointer.

  In this embodiment, the maximum value of each prize ball command output counter is set to 255. Therefore, in the processing of steps S2123 and S2124, the count value of the prize ball command output counter is incremented by 1 each time a winning of a game ball to the prize opening is detected until the count value reaches 255. When the count value reaches 255, the count value of the prize ball command output counter is not updated even if the winning of the game ball to the prize opening is detected.

  In this embodiment, the CPU 56 counts up the count value of the prize ball command output counter to store data that can specify the number of prize balls to be paid out in the storage means. For example, the CPU 56 may directly store the number of prize balls to be paid out in a predetermined buffer. Further, the CPU 56 may store data indicating the number of prize balls to be paid out in a predetermined buffer, for example, instead of storing the number of prize balls. In this case, for example, the CPU 56 may perform control such as storing data “01” for the number of winning balls 3 and storing data “02” for the number of winning balls 10.

  In step S2125, the number of processes is reduced by 1, and if the number of processes is not 0, the process returns to step S2114 (step S2126). If the number of processes is 0, the CPU 56 loads the contents of the total prize-ball number storage buffer (step S2127), and loads the contents of the switch-on buffer to the register (step S2128). Further, the CPU 56 calculates the logical product of the contents of the loaded switch-on buffer and the switch input bit determination value of the payout number count switch (step S2129). As a result, in the register loaded with the contents of the switch-on buffer, 7 bits other than the bit corresponding to the detection signal of the payout number count switch to be inspected become 0.

  If the calculation result in step S2129 is not 0, that is, if the detection signal of the payout number count switch to be inspected is on (step S2130), the CPU 56 calculates 1 from the contents of the loaded total prize-ball number storage buffer. Subtraction is performed (step S2131). Then, the CPU 56 stores the subtraction result in the total winning ball number storage buffer (step S2132) and ends the process.

  FIG. 73 is a timing chart showing an example of the timing at which the total prize ball number addition process and the subtraction process stored in the total prize ball number storage buffer are performed. As shown in FIG. 73, when the timer interrupt process is executed by the CPU 56 of the game control microcomputer 560 after the winning detection switch detects the winning of the game ball, the process of steps S2111 to S2126 of the input determination process Is executed, the count value of each prize ball command output counter is counted up. Next, when the timer interruption process is terminated and the process returns to the main process, a prize ball number command transmission process is executed, whereby a prize ball number command is transmitted to the payout control board 37 based on the count value after counting up. The Then, by executing the winning ball ACK waiting process, the winning ball number corresponding to the transmitted winning ball number command is added to the total winning ball number storage buffer.

  As shown in FIG. 73, when the CPU 56 executes a timer interrupt process after the payout number count switch detects the payout of a prize ball, the processes of steps S2127 to S2132 of the input determination process are executed. Thus, 1 is subtracted from the total number of winning balls stored in the total winning ball number storage buffer. In this case, the timer interruption process is not executed since the interruption prohibited state is set while the prize ball addition process (the processes of steps S1281 to S1285) of the prize ball ACK waiting process is being executed. Therefore, even if the payout number counting switch detects the payout of the winning ball during the winning ball addition process, the subtraction process of the total winning ball number stored in the total winning ball number storage buffer is not executed. When the winning ball addition process is completed and the interrupt enabled state is set again, the timer interrupt process is executed, and the total number of winning balls stored in the total winning ball number storage buffer is based on the detection signal of the payout number count switch. 1 is subtracted from.

  Next, the random number circuit initial value update process (step S22) in the timer interrupt process will be described. FIG. 74 is a flowchart showing random number circuit initial value update processing. In the random number circuit initial value update process, the CPU 56 checks the state of the notification signal indicating that the count value C output from the counter 521 of the random number circuit 503 has been updated to the final value (step S220). When it is detected that the notification signal is in the on state, the CPU 56 checks whether or not the initial value update flag is set (step S221). That is, in the random number circuit setting process, the CPU 56 checks whether or not the setting for updating the initial value is made when the count value is updated to a predetermined final value (see step S157).

  When the initial value update flag is set, the CPU 56 determines to update the initial value input to the counter 521 when the counter 521 of the random number circuit 503 updates the count value to a predetermined final value. When the initial value update flag is set, the CPU 56 checks whether or not the initial value change flag is set (step S222). That is, the CPU 56 determines whether or not the initial value of the count value is currently changed (that is, whether or not it is changed to a value based on the ID number of the game control microcomputer 560).

  When the initial value change flag is set (that is, when the initial value is currently changed based on the ID number of the game control microcomputer 560), the CPU 56 uses the initial value input to the counter 521 as the game control. The value based on the ID number of the microcomputer 560 is returned to the original value (for example, “1”) (step S223). Then, the CPU 56 resets the initial value change flag (step S224) and ends the initial value update process.

  If the initial value change flag is not set (that is, the initial value is not currently changed), the CPU 56 changes the initial value input to the counter 521 to a value based on the ID number of the game control microcomputer 560. (Step S225). In this case, for example, if the ID number of the game control microcomputer 560 is “100”, the initial value input to the counter 521 is calculated by adding a predetermined value “100” to the ID number “100”. Change to the value “200”. Further, for example, the initial value input to the counter 521 is changed to the calculated value “50” obtained by subtracting the predetermined value “50” from the ID number “100”. Then, the CPU 56 sets an initial value change flag (step S226) and ends the initial value update process.

  When both the 12-bit random number circuit 503a and the 16-bit random number circuit 503b are set, in step S225, the CPU 56 sets the random number read from one random number circuit (for example, the 12-bit random number circuit 503a) as a predetermined value as an ID number. The initial value input to the counter 521 may be obtained. Then, the CPU 56 may use a random number read from the other one (for example, a 16-bit random number circuit 503b) as a random number for determining the big hit.

  When updating the initial value input to the counter 521 in step S225, the CPU 56 checks the value of the random number maximum value setting register 535 of the comparator 522 of the random number circuit 503, and the value set based on the ID number is determined. It is determined whether or not it is greater than the maximum random number. When determining that the value set based on the ID number is equal to or greater than the maximum random number, the CPU 56 does not update the initial value input to the counter 521 with a predetermined value (for example, updates with the predetermined value “0”). do not do). By doing so, it is possible to prevent a situation where the initial value of the count value is set to a value equal to or greater than the random number maximum value.

  If it is determined in step S220 that the notification signal is in the OFF state, or if it is determined in step S221 that the initial value update flag is not set, the CPU 56 does not update the initial value input to the counter 521. Then, the random number circuit initial value update process is finished as it is, and the routine goes to Step S23.

  Next, the count value permutation change process (step S26) in the timer interrupt process will be described. FIG. 75 is a flowchart showing the count value permutation changing process. The CPU 56 performs the count value permutation change process by executing the process according to the count value permutation change program 554. In the count value permutation change process, the CPU 56 checks the state of the notification signal indicating that the count value C output from the counter 521 of the random number circuit 503 has been updated to the final value (step S241). When it is detected that the notification signal is in the on state, the CPU 56 checks whether or not the count value permutation change flag is set (step S242). That is, the CPU 56 determines whether or not the setting for changing the permutation of the count values updated by the counter 521 when the count values are updated to a predetermined final value has been made in the random number circuit setting process (see step S158). Check.

  When the count value permutation change flag is set, the CPU 56 determines that the permutation of the count values updated by the counter 521 is changed when the counter 521 of the random number circuit 503 updates the count value to a predetermined final value. Then, the CPU 56 writes the count value permutation change data “01h” in the count value permutation change register 536 (step S243). That is, the CPU 56 causes the count value permutation change circuit 523 to change the permutation of the count values C input to the random value storage circuit 531 by writing the count value permutation change data “01h”.

  As described above, in the count value permutation change process, when the random number is updated to a predetermined final value, the permutation of the count value updated by the counter 521 is changed, so that the randomness generated by the random number circuit 503 is more random. Can be improved.

  Next, the operation of the payout control means (the payout control microcomputer 370) will be described. FIG. 76 is an explanatory diagram showing an example of output port assignment in the payout control means. As shown in FIG. 76, the output port 0 is an output port for outputting a signal of each phase supplied to the payout motor 289 by the stepping motor and a detection signal of the payout number count switch 301. That is, the detection signal of the payout number count switch 301 is output from the output port 0 to the main board 31 via the payout control microcomputer 370. The output port 1 is an output port for outputting a ball-out LED 52, a prize ball LED 51, a prize ball in-game signal, prize ball information, ball rental information, and a gaming machine error status signal output to the outside of the gaming machine. is there. The output port 2 is an output port of each segment output of the error display LED 374 by 7 segment LED.

  Although not shown in FIG. 76, the payout control board 37 is also provided with an output port 3 for outputting an EXS signal and a PRDY signal to the card unit 50.

  FIG. 77 is an explanatory diagram showing an example of bit assignment of input ports in the payout control means. As shown in FIG. 77, a connection confirmation signal from the main board 31 is input to the bit 4. In addition, the detection signals of the ball break switch 187 and the detection signal of the payout motor position sensor 295 are input to the bits 6 and 7, respectively. In addition, the detection signal of the payout number count switch 301, the operation signal from the error release switch 375, and the detection signal of the full switch 48 are input to bits 1 to 3 of the input port 1, respectively. The VL signal, the BRDY signal, and the BRQ signal from the card unit 50 are input to bits 4 to 6 of the input port 1, respectively. The input port 2 receives the output signal of the clear switch 921 from the power supply board 910 and the power-off signal.

  Next, the operation of the payout control means will be described. FIG. 78 is a flowchart showing main processing executed by the payout control means. In the main process, the payout control CPU 371 of the payout control microcomputer 370 first performs necessary initial settings. That is, the payout control CPU 371 first sets the interruption prohibition (step S701). Next, the interrupt mode is set to interrupt mode 2 (step S702), and a stack pointer designation address is set to the stack pointer (step S703). The payout control CPU 371 sets the internal device register (step S704), sets the CTC and PIO (step S705), and then sets the RAM in an accessible state (step S706). Further, 0000 (H) is set as an initial value of the award ball unpaid number counter (step S707).

  In this embodiment, one channel of the built-in CTC is used in the timer mode. Accordingly, in the built-in device register setting process in step S704 and the process in step S705, register setting for setting the channel to be used to timer mode, register setting for permitting interrupt generation, and setting an interrupt vector. The register is set. The interrupt by the channel is used as a timer interrupt. For example, when it is desired to generate a timer interrupt every 2 ms, a value corresponding to 2 ms is set as an initial value in a predetermined register (time constant register).

  The interrupt vector set for the channel set to the timer mode (channel 3 in this embodiment) corresponds to the start address of the timer interrupt process. Specifically, the start address of the timer interrupt process is specified by the value set in the I register and the interrupt vector. In the timer interruption process, a payout control process for controlling the payout means (including at least a process of driving the ball payout device 97 in response to a command signal related to award ball payout from the main board, and a ball payout device 97 in response to a ball lending request. A process for driving the program may be included.

  In this embodiment, the interruption mode 2 is also set in the payout control microcomputer 370. Therefore, an interrupt process based on counting up the built-in CTC can be used. Also, an interrupt processing start address can be set according to the interrupt vector sent by the CTC. The interrupt based on CTC channel 3 (CH3) count-up is an interrupt generated when the CPU internal clock (system clock) is counted down and the register value becomes “0”, and is used as a timer interrupt. .

  Next, the state of the output signal of the clear switch 921 input via the input port 2 is confirmed only once (step S708). In the confirmation, when the on is detected, the payout control CPU 371 executes an initialization process (steps S712 to S715). If the clear switch 921 is not in the on state, whether or not data protection processing of the backup RAM area (for example, power supply stop processing such as addition of parity data) has been performed when power supply to the gaming machine is stopped Confirmation is made (step S709). Whether or not the protection process has been performed depends on the value of the backup monitoring timer stored in the backup RAM area in the power supply stop process described later according to the execution of the data protection process in the backup RAM area (for example, It is confirmed by whether or not 2). Note that such a confirmation method is an example. For example, a flag indicating that data protection processing has been executed is set in the backup flag area in the power supply stop processing, and the flag is set in step S709. If it is confirmed that there is a backup, it may be determined that there is a backup.

  If it is determined that there is a backup, the payout control CPU 371 performs a data check (parity check in this example) in the backup RAM area (step S710). In this embodiment, clear data (00) is set in the checksum data area, and the checksum calculation start address is set in the pointer. Also, the number of checksum calculations corresponding to the number of data to be checksum is set. Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated. The calculation result is stored in the checksum data area, the pointer value is incremented by 1, and the checksum calculation count value is decremented by 1. The above processing is repeated until the value of the checksum calculation count becomes zero. When the value of the checksum calculation count becomes 0, the game control microcomputer 560 inverts the value of each bit of the contents of the checksum data area and uses the inverted data as the checksum.

  In this embodiment, in the power supply stop process, the checksum is calculated by the same process as described above, and the checksum is stored in the backup RAM area. In step S710, the calculated checksum is compared with the stored checksum. When the power supply is stopped after an unexpected power failure or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area is different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state at the time of stopping the power supply, the payout control state restoration processing is not executed, and the initialization processing (steps S712 to S715) is executed.

  If the check result is normal, the payout control CPU 371 performs payout control state recovery processing. Specifically, the value of the award ball unpaid number counter formed in the backup RAM is set as the initial value of the award ball unpaid number counter (step S711). And the process after step S712 is performed.

  In the initialization process, the payout control CPU 371 first performs a RAM clear process (step S712). In addition, initial values are set in the flags and counters of the RAM area (step S713). The process of step S713 includes a process of setting an initial value of the award ball unpaid number counter in the award ball unpaid number counter. Therefore, when the payout control state recovery process (step S711) is executed, the value of the unsold prize ball number counter stored in the backup RAM is set again in the unsold prize ball number counter. In other words, the value of the award ball unpaid number counter stored in the backup RAM is used as it is.

  Also, the payout control CPU 371 executes serial communication circuit setting processing for initial setting of the serial communication circuit 380 (step S713a). In this case, the payout control CPU 371 causes the serial communication circuit 380 to serially communicate with the game control microcomputer 560 according to the same process as the serial communication circuit setting process (see step S15a) performed by the CPU 56 of the game control microcomputer 560. Make settings for

  When the serial communication circuit 380 is initialized, the payout control CPU 371 initializes the priority of interrupt processing executed in response to the interrupt request from the serial communication circuit 380 (step S713b). In this case, in this case, the payout control CPU 371 initializes the priority order of the interrupt process according to the same process as the priority order initial setting process (see step S15b) performed by the CPU 56 of the game control microcomputer 560.

  Then, the CTC register provided in the payout control microcomputer 370 is set so that a timer interrupt is periodically generated (step S714). That is, a value corresponding to the timer interrupt generation interval is set as an initial value in a predetermined register (time constant register). Since interruption is prohibited in step S701 of the initial setting process, interruption is permitted before the initialization process is completed (step S715). Thereafter, a loop process for monitoring the occurrence of a timer interrupt is entered.

  As described above, in this embodiment, the built-in CTC of the payout control microcomputer 370 is set to repeatedly generate a timer interrupt. When a timer interrupt occurs, the payout control CPU 371 of the payout control microcomputer 370 executes a timer interrupt process.

  FIG. 79 is a flowchart showing an example of timer interrupt processing executed by the payout control means. In the timer interrupt process, the payout control CPU 371 of the payout control microcomputer 370 executes a power-off process for monitoring whether or not a power-off signal is output (step S749). Thereafter, a payout control process after step S751 is executed. In the payout control process, the payout control CPU 371 first performs an input determination process (step S751). In the input determination process, the states of bits 4 to 6 of input port 0 and bits 3 to 6 of input port 1 (see FIG. 77) are detected, and the detection result is a predetermined 1 byte of RAM (referred to as an input state flag). It is a process to be reflected in. In the payout control process, when control is performed based on the states of bits 4 to 6 of input port 0 and bits 3 to 6 of input port 1, the state of the input port is not directly checked, but the input state is checked. Check the status of the flag.

  Next, the payout control CPU 371 executes a payout motor control process (step S753). In the payout motor control process, when the payout motor 289 is to be driven, a process for outputting the patterns of the payout motors φ1 to φ4 to the output port 0 is performed.

  Further, the payout control CPU 371 executes a prepaid card unit control process for communicating with the card unit 50 (step S754). Next, the payout control CPU 371 executes main control communication processing for communicating with the game control means of the main board 31 (step S755). Further, a prize ball lending control process for performing a control for paying out a lending ball in response to a ball lending request from the card unit 50 and for performing a control for paying out the number of award balls indicated by a prize ball number command from the main board. Is executed (step S756).

  Then, the payout control CPU 371 executes error processing for detecting various errors (step S757). Further, an information output process for outputting prize ball information and ball lending information output to the outside of the gaming machine is executed (step S758). Further, a predetermined display is performed on the error display LED 374 according to the result of the error processing, and a display control process for lighting the prize ball LED 51 and the ball out LED 52 is executed (step S759).

  In the present embodiment, when various errors (for example, a full tank error, a ball shortage error, and a prepaid card unit unconnected error) are detected in error processing described later, an error bit corresponding to the detected error is set. Then, in the display control processing in step S759, the payout control CPU 371 performs a predetermined display on the error display LED 374 based on the error bit being set. Also, the payout control CPU 371 performs control for lighting the prize ball LED 51 when the prize ball is being paid out in the display control process. When the prize ball payout is completed, control for turning off the prize ball LED 51 is performed.

  In this embodiment, a RAM area (output port 0 buffer, output port 1 buffer, output port 2 buffer) corresponding to the output state of the output port is provided. The contents of the port 0 buffer, output port 1 buffer, and output port 2 buffer are output to the output port (step S760: output processing). The output port 0 buffer, output port 1 buffer, and output port 2 buffer include a payout motor control process (step S753), a prepaid card control process (step S754), a main control communication process (step S755), and an information output process (step S758). And it is updated by the display control process (step S759).

  Next, an operation in which the payout control CPU 371 of the payout control microcomputer 370 transmits and receives various commands in the main control communication process in step S755 will be described. As shown in FIG. 54, the payout control microcomputer 370 includes a serial communication circuit 380 that serially communicates various commands with the game control microcomputer 560. The payout control microcomputer 370 uses the serial communication circuit 380 to receive the prize ball number command shown in FIG. 53 from the game control microcomputer 560. When receiving the prize ball number command, the payout control microcomputer 370 transmits the prize ball ACK command “D2” shown in FIG. 53 as a reception confirmation signal using the serial communication circuit 380.

  Similarly to the CPU 56 of the game control microcomputer 560, when the payout control CPU 371 receives an interrupt request from the serial communication circuit 380 while it is in the interrupt enabled state, the interrupt that the serial communication circuit 380 has issued an interrupt request for. Performs interrupt processing according to the cause. In this embodiment, when the payout control CPU 371 specifies that the cause of the interruption is that the serial communication circuit 380 has received the received data, the payout control CPU 371 executes a reception interrupt process according to the same process as in FIG. . In this case, the payout control CPU 371 sets a reception interrupt flag indicating that the serial communication circuit 380 is receiving reception data. The payout control CPU 371 may read data from the reception data register of the serial communication circuit 380 instead of setting the reception interrupt flag in the reception interrupt processing. In this case, for example, the payout control CPU 371 determines whether or not the received data read is a prize ball number command in the interruption process during reception. If the received data is a prize ball number command, the payout control CPU 371 may add the number of prize balls indicated by the prize ball number command to the prize ball unpaid number counter. By doing so, in the main control communication process described later, it is determined whether or not the received data is a prize ball number command based on the reception interrupt flag being set (steps S542 to S545 described later). (Refer to the above), it is not necessary to execute the process of adding the number of prize balls to the prize ball unpaid-out number counter (see step S546 described later).

  FIG. 80 is a flowchart showing main control communication processing in which the payout control CPU 371 of the payout control microcomputer 370 communicates with the game control means (game control microcomputer 560) of the main board 31. In the main control communication process, the payout control CPU 371 checks whether or not the connection confirmation signal is on (step S541). Note that the connection confirmation signal being in the on state means that power is supplied and the game control means can control the progress of the game, and that the connection confirmation signal is in the off state means This means that the supply stop process is started and the game control means cannot progress the game (the connection confirmation signal is turned off in the output port clear process in the power supply stop process).

  The payout control CPU 371 checks whether or not the reception interrupt flag is set (step S542). That is, the payout control CPU 371 checks whether or not the serial communication circuit 380 receives the received data and the data is stored in the reception data register of the serial communication circuit 380.

  If the reception interrupt flag is set, the payout control CPU 371 reads data from the reception data register of the serial communication circuit 380 (step S543). Also, the payout control CPU 371 determines whether or not the read data is a prize ball number command (whether it is any one of commands “03”, “0A”, or “0F”) (step S544). .

  Upon confirming that the data read from the reception data register of the serial communication circuit 380 is a prize ball number command, the payout control CPU 371 resets the reception interrupt flag (step S545), and the prize ball number command indicates The number of prize balls is added to the prize ball unpaid number counter (step S546). Then, the payout control CPU 371 writes the prize ball ACK command to the transmission data register 710 of the serial communication circuit 505 (step S547), and ends the process. Thereafter, the winning ball ACK command written in the transmission data register is transferred to the transmission shift register of the serial communication circuit 380, and is transmitted from the transmission shift register of the serial communication circuit 380 to the game control microcomputer 560.

  If the data read from the reception data register in step S544 is not a prize ball number command, the payout control CPU 371 checks whether or not the read data is a prize ball excessive abnormality command (step S548a). If it is confirmed that the command is an excessively rich ball abnormal command, the payout control CPU 371 resets the interruption flag at the time of reception (step S549a) and receives an excessively abnormal ball command reception flag indicating that the excessively abnormal ball command has been received. Is set (step S550a).

  If the data read from the received data register in step S548a is not an award ball excess abnormality command, the payout control CPU 371 checks whether the read data is an award ball underabnormal command (step S548b). . If it is confirmed that the command is an award ball underabnormal command, the payout control CPU 371 resets a reception interrupt flag (step S549b), and a prize ball underabnormal command reception flag indicating that a prize ball underabnormal command has been received. Is set (step S550b).

  FIG. 81 is a flowchart showing the prize ball lending control processing in step S756. In the winning ball lending control process, the payout control CPU 371 confirms that the detection signal of the payout number count switch 301 is turned on (step S601). The value is decremented by 1 (steps S602 and S604), and if the ball is not being lent, the value of the unpaid prize ball counter is decremented by 1 (steps S602 and S603). Further, when the value of the award ball unpaid number counter is decremented by 1, the detection signal of the payout number count switch 301 is transferred (output) to the main board 31 (step S603a).

  Next, the payout ball detection bit of the payout control state flag formed in the RAM is set (step S605). The payout ball detection bit is a game regardless of whether the payout motor 289 is driven during one award ball payout process (maximum 15 balls) or one ball lending process (25 payouts) in the payout passing waiting process. This is used to detect that no sphere has passed through the payout number counting switch 301. Thereafter, any one of steps S610 to S612 is executed according to the value of the payout control code.

  In the winning ball lending control process, when checking the detection signal of the payout number count switch 301 or subtracting the unpaid number counter, the error bit check is not executed. Accordingly, even if an error state relating to payout of game balls is detected, every time a payout of game balls is detected by the payout number count switch 301, if the payout game balls are loaned balls, a ball rental unpaid number counter 1 is subtracted, and if it is a prize ball, a process of subtracting 1 from the prize ball unpaid number counter is executed. Therefore, even if an error related to payout occurs, the number of unpaid game balls can be managed accurately. That is, a game ball paid out from the ball payout device 97 before the payout control CPU 371 of the payout control microcomputer 370 detects the occurrence of an error is caused by the payout number count switch 301 with a slight delay from the time of payout. As detected, the payout control CPU 371 detects the occurrence of an error after the game ball is paid out from the ball payout device 97 and before the game ball is detected by the payout number count switch 301. In this case, the game balls paid out from the ball payout device 97 before detecting the occurrence of an error can be reflected in the award ball unpaid number counter or the ball lending unpaid number counter.

  FIG. 82 is a flowchart showing the payout start waiting process (step S610) executed when the payout control code is 0. In the payout start waiting process, if the BRDY signal is not in the on state (step S621), the payout control CPU 371 executes a process for paying out a prize ball after step S631. However, if the error bit is set, the processing after step S631 is not executed (step S622). The error bit in the error flag includes a main board non-connection error bit. The main board non-connection error is set when the connection confirmation signal from the main board 31 is in the OFF state. Accordingly, the payout control CPU 371 starts substantial control on condition that the connection confirmation signal is turned on after power supply to the gaming machine is started. The fact that the connection confirmation signal is on means that power is supplied and the game control means can control the progress of the game, so that the payout control of the prize ball according to the progress of the game can be executed. means. On the other hand, the fact that the connection confirmation signal is in the off state means that the power supply is stopped and the game control means cannot advance the game, so that the award ball payout control according to the progress of the game cannot be executed. It means that there is. Accordingly, the payout control CPU 371 stops the payout control of the winning ball when the main board non-connection error bit is set. On the other hand, in this example, the lending ball payout control is executed without checking the error bit, and the lending control is continuously performed even if the main board unconnected error bit is set. .

  If the BRDY signal is on and the BRQ signal that is a ball lending request signal is on (step S623), the payout control CPU 371 checks whether the VL signal is on. (Step S623a). If the VL signal is on, the payout control CPU 371 sets a ball lending operation in progress flag (step S624). Then, “25” is set in the unpaid ball lending number counter (step S625), and “25” is set in the payout motor rotation number buffer (step S626). If the VL signal is not on in step S623a, the payout control CPU 371 proceeds to step S622 without performing the processes in and after step S624.

  The payout motor rotation frequency buffer is referred to in the payout motor control process (step S753). That is, in the payout motor control process, control is performed to rotate the payout motor 289 by the number of rotations corresponding to the value set in the payout motor rotation frequency buffer.

  Thereafter, the payout control microcomputer 370 sets a value corresponding to the payout motor start preparation process (step S522) (specifically, “1”) to the payout motor control code for selecting the process executed in the payout motor control process. ) Is set (step S627), the value of the payout control code is set to 1 (step S628), and the process is terminated.

  In step S631, the payout control CPU 371 checks whether or not the value of the award ball non-payout counter is 0 (step S631). If 0, the process ends. If the value of the award ball unpaid number counter is not 0, it is confirmed whether it is 15 or more (step S632). If it is less than 15, the value of the award ball unpaid number counter is set in the payout motor rotation count buffer (step S633), and if it is 15 or more, “15” is set in the payout motor rotation count buffer. Then, a winning ball moving flag is set (step S635), and the process proceeds to step S627.

  FIG. 83 is a flowchart showing a payout motor stop waiting process (step S611) executed when the payout control code is 1. In the payout motor stop waiting process, the payout control CPU 371 checks whether or not the payout operation is completed (step S641). For example, the payout control CPU 371 sets a flag to that effect when the payout motor brake process (step S525) in the payout motor control process ends, and whether the payout operation is completed by checking the flag in step S641. You can check whether or not.

  When the payout operation is completed, the payout control CPU 371 sets the payout passing monitoring time in the payout control monitoring timer (step S642). The payout passing monitoring time is a time that has a margin in the time from when the last payout ball is paid out by the payout motor 289 until it passes through the payout number count switch 301. Then, the value of the payout control code is set to 2 (step S643), and the process ends.

  84 to 86 are flowcharts showing a payout passing waiting process (step S612) executed when the value of the payout control code is 2. In the payout passing waiting process, when the prize ball is being paid out, it is determined that the payout has been completed normally if the value of the prize ball unpaid number counter is 0. If the value of the award ball unpaid number counter is not 0, if it is not in an error state, a re-payout operation of one game ball is tried up to 2 times. In the re-payout operation, when it is detected by the payout number count switch 301 that the game ball is actually paid out, it is determined that the payout has been completed normally. In this embodiment, the maximum number of game balls to be paid out in one prize ball payout operation is 15, and if a prize ball number command is received during the prize ball payout, the value of the prize ball unpaid number counter is received. Therefore, even when the payout is completed normally, the value of the award ball non-payout number counter may not be 0.

  Further, when the ball lending is being paid out, it is determined that the payout has been completed normally if the value of the ball lending unpaid-out counter is 0. If the value of the ball lending unpaid number counter is not 0, and if it is not in an error state, a re-payout operation of one game ball or the remaining number of ball lending (corresponding to the value of the ball lending unpaid number counter) Try. In this embodiment, the number of game balls to be paid out in one ball lending and payout operation is 25 (fixed value), and the payout motor 289 is rotated so that 25 game balls are paid out. Therefore, when the value of the unpaid ball lending counter is not 0, the payout has not been completed normally.

  In the payout waiting process, the payout control CPU 371 first checks the value of the payout control timer, and if the value is 0, the process proceeds to step S653 (step S650). If the value of the payout control timer is not 0, the value of the payout control timer is decremented by 1 (step S651). If the value of the payout control timer is not 0 (step S652), that is, if the payout control timer has not timed out, the process is terminated. Note that the process of step S650 is a process that takes into account when a game ball payout retry operation to be described later is started. When the process of step S807, which will be described later, is executed, a retry operation is started via a route that moves from step S650 to S653.

  If the payout control timer has timed out (step S652), it is confirmed whether or not the ball lending payout process (ball lending operation) has been executed (step S653). Whether or not the ball lending operation has been executed is confirmed by whether or not the ball lending operation bit in the payout control state flag formed in the RAM is set (see steps S623 and S624). When the ball lending operation is not executed, that is, when the prize ball payout process (prize ball operation) is executed, the payout control CPU 371 checks the value of the award ball unpaid number counter (step S654). ). When the value of the winning ball unpaid-out counter is 0, it is determined that the winning ball payout process has been completed normally, and the payout ball detection bit in the payout control state flag, 1 bit during re-payout operation, and during re-payout operation 2 bits, the winning ball operating flag and the ball lending operating bit are reset (step S655), the payout control code is set to 0 (step S656), and the process is terminated. This bit is set when the switch 301 is turned on, and indicates that the payout number counting switch 301 has detected at least one game ball during the payout operation. Further, 1 bit during the re-payout operation and 2 bits during the re-payout operation are control bits used when executing a re-payout process including two re-payout operations.

  The payout control CPU 371 determines that an error flag (specifically, a payout switch error error 1 bit, a payout switch error error 2 bit, and a payout case error bit when the value of the award ball unpaid number counter is not 0. (One or a plurality of bits) is not set (step S659), and if the payout ball detection bit is not set (step S661), the re-payout operation is executed. To do. If the error flag is set, the re-payout operation is not executed.

  As described above, in this embodiment, even when the payout is completed normally, the value of the unpaid prize ball number counter may not be 0. Therefore, if the payout ball detection bit is set, that is, if the payout number count switch 301 detects the payout of at least one game ball during the prize ball payout process, it is assumed that the prize ball payout process is normally completed. The process proceeds to step S655. For example, when 15 game balls should be paid out in one prize ball payout process, when only 14 game balls are actually paid out (the number of payout count switch 301 is 14 game balls). In this case, the payout ball detection bit is set, so it is considered that the award ball payout process has been completed normally. It should not have been done, and the shortage will be paid out in the next prize ball payout process, so there will be no disadvantage to the player.

  In order to execute the re-payout process, the pay-out control CPU 371 first checks whether or not 2 bits during re-payout operation are set (step S662). If not set, it is confirmed whether or not 1 bit is set during the re-payout operation (step S663). If 1 bit is not set during the re-payout operation, 1 is set as the number of re-payout operations to execute the first re-payout operation (step S664), and 1 bit is set during the re-payout operation (step S665). ) The value of the re-payout operation number or ball lending unpaid-out number counter is set in the payout motor rotation number buffer (step S666). Further, the payout control CPU 371 sets a value (specifically “1”) corresponding to the payout motor activation preparation process (step S522) to the payout motor control code for selecting the process executed in the payout motor control process. set. The payout motor rotation frequency buffer is referred to in the payout motor control process (step S753). That is, in the payout motor control process, control is performed to rotate the payout motor 289 by the number of rotations corresponding to the value set in the payout motor rotation frequency buffer. In step S666, the value of the unpaid ball lending number counter is also handled because step S666 is also used in the re-payout process in the ball lending payout process. That is, in step S666, the payout control CPU 371 sets the re-payout operation number in the re-payout process in the prize ball payout process, and sets the value of the ball lending unpaid-out number counter in the re-payout process in the ball lending payout process. . Thereafter, the payout control code is set to 1 (step S667), and the process is terminated.

  In step S663, when it is confirmed that 1 bit is set during the re-payout operation, the payout control CPU 371 sets 1 as the re-payout operation number in order to execute the second re-payout (step S668). Then, 1 bit is reset during the re-payout operation (step S669), and 2 bits are set during the re-payout operation (step S670). Then, control goes to a step S666.

  When it is confirmed in step S662 that 2 bits are set during the re-payout operation, the payout control CPU 371 does not pay out the game ball even if the re-payout process is executed twice (payout number count switch). 301 has not detected a game ball), a payout case error bit in the error flag is set (step S672). At that time, 2 bits are reset during the re-payout operation (step S671). Then, the process ends.

  As described above, if no game balls are paid out even if two re-payout operations are performed in the re-payout process (corrected payout process), it is determined that the game ball payout operation is defective and the payout number count switch is not A passing error bit (payout case error bit) is set.

  Therefore, in this embodiment, the prize game medium payout control means in the payout control microcomputer 370 does not pay out the prize game medium based on the detection signal from the payout number count switch 301 as the payout detection means. When this is detected, control is performed so that the payout means pays out one prize game medium up to a predetermined number of times (in this example, twice). In this embodiment, if the prize game medium is not paid out even if the retry operation for paying out the prize game medium is performed twice, the payout case error bit is set and an error is being generated. (Step S672), the payout case error bit may be set when it is first detected that the premium game medium has not been paid out. Note that “retry operation (or“ retry ”,“ retry operation processing ”) means that the actual payout number is the same as the normal payout processing for executing payout of a predetermined number of game balls. This is an operation to be executed when the number is small, and means an operation for executing the payout process again in order to pay out an unpaid game ball separately from the normal payout process.

  In the prize ball lending control process, the error bit is checked to determine whether or not a payout operation (one prize ball payout or one ball lending) is performed. The payout start shown in FIG. Only in the waiting process. In the payout motor stop waiting process shown in FIG. 81 and the payout passing wait process shown in FIG. 82 and the like, the error bit is not checked. Note that the error bit is also checked in step S659 or the like in the payout passing waiting process, but this check is for determining whether or not a re-payout operation is performed, and is a payout operation (single prize ball payout or 1 This is not to determine whether or not to start ball lending. Therefore, after the process of step S626, S633, or step S634 is performed and the game ball payout process is started, the payout process is not interrupted even if an error occurs. In other words, when an error occurs, the game ball payout process is continued until a point at which the game ball can be cut well (at the time when one prize ball payout or one ball lending ends). The error bits in the error flag checked in step S621 include an error bit indicating that the connection confirmation signal from the main board 31 has been turned off. Therefore, even when the connection confirmation signal is turned off, the game ball payout process is stopped at a time when it is best to turn it off. If an error occurs even after the game ball payout process is started after the process of step S626, S633 or step S634 is performed, instead of continuing the game ball payout process until a good point is reached. The game ball payout process may be stopped immediately.

  Upon confirming that the ball lending / dispensing process (ball lending operation) has been executed in step S653, the payout control CPU 371 confirms whether or not the value of the unlapped ball lending number counter is 0 (step S657). . If it is 0, it is determined that the ball lending / dispensing process is normally completed, and the process proceeds to step S655.

  In step S657, if the value of the ball lending unpaid number counter is not 0, an error flag (specifically, any one of the payout switch error error 1 bit, the payout switch error error 2 bit, and the payout case error bit) Or one bit or a plurality of bits) is not set (step S675), the re-payout process is executed. If the error flag is set, the re-payout process is not executed.

  In order to execute the re-payout process, the pay-out control CPU 371 first checks whether or not 2 bits during re-payout operation are set (step S676). If not set, it is confirmed whether or not 1 bit is set during the re-payout operation (step S677). If 1 bit is not set during re-payout operation, 1 is set as the number of re-payout operations to execute the first re-payout operation (step S678), and 1 bit is set during re-payout operation (step S679). ) After further resetting the payout ball detection bit (step S680), the process proceeds to step S666.

  In step S677, when it is confirmed that 1 bit is set during the re-payout operation, the payout control CPU 371 performs a process for re-executing the re-payout operation. Specifically, 1 bit is reset during the re-payout operation (step S681). If the payout ball detection bit is set, that is, if the game ball is paid out in the first re-payout operation, the process proceeds to step S683. If the payout ball detection bit is not set, the process proceeds to step S684 to execute the second re-payout operation.

  In step S683, the payout ball detection bit is reset, and then the process proceeds to step S666. Therefore, in this case, since 1 bit remains set during the re-payout operation, the first (first) re-payout operation is performed again. In step S684, 1 is set as the number of re-payout operations (step S684), 2 bits during re-payout operation are set (step S685), and the process proceeds to step S666.

  In step S676, when it is confirmed that the 2 bits during re-payout operation are set, the payout control CPU 371 resets 2 bits during the re-payout operation (step S686), and if the payout ball detection bit is set, That is, if the game ball is paid out by the re-payout operation, the process proceeds to step S683 to try to eliminate the remaining unpaid out. If the payout ball detection bit is not set, it is determined that the game ball has not been paid out even if the re-payout process is executed twice (the payout number count switch 301 has not detected a game ball). A payout case error bit is set (step S688). Then, the process ends.

  As described above, if one game ball is not paid out even if two re-payout operations are continuously performed in the re-payout processing (corrected payout processing) related to the ball lending process, a game ball payout operation is performed. As a failure, a payout count switch non-passing error bit (payout case error bit) is set.

  Next, error processing will be described. FIG. 87 is an explanatory diagram showing the relationship between the type of error and the display of the LED 374 for error display. As shown in FIG. 87, when the connection confirmation signal from the main board 31 is turned off, the payout control CPU 371 of the payout control microcomputer 370 displays an error display LED 374 as a main board non-connection error. Control to display “1” is performed. Therefore, if the connection confirmation signal is turned off while the input state of the connection confirmation signal is being confirmed, “1” is displayed on the error display LED 374.

  When the disconnection of the payout count switch 301 or a ball clogging occurs at the payout count switch 301, the error display LED 374 is controlled to display “2” as the payout switch abnormality detection error 1. The disconnection of the payout number count switch 301 or the occurrence of ball clogging in the payout number count switch 301 is determined by the detection signal of the payout number count switch 301 not being turned off.

  When the detection signal of the payout number count switch 301 is turned on even though the game ball is not paying out, control is performed to display “3” on the error display LED 374 as the payout switch abnormality detection error 2. Do. If the detection signal of the payout count switch 301 does not turn on despite the rotation abnormality of the payout motor 289 or the game ball being paid out, “4” is displayed on the error display LED 374 as a payout case error. Control. The specific method for detecting that the detection signal of the payout number count switch 301 is not turned on is as described above.

  In addition, when the lower pan is full, that is, when the full switch 48 is turned on, control is performed to display “5” on the error display LED 374 as a full error. When the supply ball is insufficient, that is, when the ball break switch 187 is turned on, control is performed to display “6” on the error display LED 374 as a ball break error.

  Further, when the VL signal from the card unit 50 is turned off, control is performed to display “7” on the error display LED 374 as a prepaid card unit non-connection error. When communication with the card unit 50 is performed at an improper timing, control is performed to display “8” on the error display LED 374 as a prepaid card unit communication error. The prepaid card unit communication error is detected in the prepaid card unit control process (step S754).

  Further, when an excessive prize ball abnormality command is received from the game control means, control is performed to display “9” on the error display LED 374 as an excessive prize ball abnormality error. Further, when a prize ball under / abnormal command is received from the game control means, control is performed to display “A” on the error display LED 374 as a prize ball under / abnormal error.

  Among the above errors, after the occurrence of a payout switch abnormality detection error 2, a payout case error, an excessive prize ball error error, or an excessive prize ball error error, the error release switch 375 is operated and an operation signal is output from the error release switch 375. If it becomes (on state), the payout control means returns to the state before the error occurred.

  As described above, the payout control CPU 371 specifically displays an error on the error display LED 374 in accordance with the relationship shown in FIG. 87 in the display control process of the timer interrupt process (see step S759). For example, the payout control CPU 371 indicates that a prepaid card unit unconnected error has occurred in the display control process based on the setting of the prepaid card unit unconnected error bit in an error process described later (see step S826). Is displayed on the error display LED 374. Further, for example, based on the fact that the full error bit is set in the error process (see step S809), an error display “5” indicating that a full error has occurred in the display control process is displayed on the error display LED 374. Control the display. Further, for example, based on the fact that the excessive ball error error bit is set in the error processing (see step S829), the error display “9” indicating that the excessive ball error is occurring is displayed in the display control processing. Control to display on the display LED 374 is performed. Further, for example, based on the setting of the prize ball under-abnormality error bit in the error processing (see step S832), the error display “A” indicating that the prize-ball under-abnormality has occurred is displayed as an error in the display control process. Control to display on the display LED 374 is performed.

  88, 89 and 90 are flowcharts showing the error processing in step S757. In the error process, the payout control CPU 371 checks the error flag, and the set bits are only the payout switch abnormality detection error 2 and the payout case error (only one of the two bits or those 2). It is confirmed whether or not (only bit) (step S801). If only those bits are set, it is confirmed whether or not the operation signal is turned on from the error release switch 375 (step S802). When the operation signal is turned on, the error recovery time is set in the pre-error recovery timer (step S803). The error recovery time is the time from when the error release switch 375 is operated until the actual return from the error state to the normal state.

  If the operation signal from the error release switch 375 is not on, the value of the timer before error recovery is confirmed (step S804). If the value of the timer before error recovery is 0, that is, if the timer before error recovery is not set, the process proceeds to step S808. If the pre-error recovery timer is set, the value of the pre-error recovery timer is decremented by -1 (step S805). The abnormality detection error 2 and payout case error bits are reset (step S807), and the process proceeds to step S808.

  When the processing of step S807 is executed, there may be an error bit that is not in the set state among the payout switch abnormality detection error 2 and payout case error bits. There is no problem with resetting. As described above, in this embodiment, when an error (see FIG. 87) that causes the setting of the payout switch abnormality detection error 2 or the payout case error bit occurs, the error release switch 375 is pressed. The error is canceled.

  When the process of step S807 is executed and the payout case error bit is reset, the payout control code is “2” (corresponding to the execution of the payout passing waiting process shown in FIGS. 84 to 86), and the prize ball When the value of the unpaid-out number counter or the value of the ball-lending unpaid-out number counter is not 0, a retry operation for game ball payout is started. That is, when the award ball lending control process of step S756 is executed next, when the payout passing waiting process of step S612 is executed, the repayment process is performed again. For example, if a prize ball payout process has been performed and the value of the prize ball unpaid number counter is not 0, the process proceeds from step S654 to step S659, and it is confirmed in step S659 that the error bit is in a reset state. Therefore, the process for starting the re-payout process after step S662 is executed again, and the re-payout process is executed. Regarding the payout case error bit reset by pressing the error release switch 375, when the bit is set (when step S672 is executed), the payout control timer has already expired. Therefore, when the process in step S807 is executed and the payout case error bit is reset, the payout control timer = 0 is determined in the determination in step S650 when the payout passage waiting process is executed next. Further, when the payout case error bit is set, the payout ball detection bit is 0 (since step S672 is not executed unless the payout ball detection bit is 0 according to the determination in step S661). Therefore, step S662 is always executed whenever it is confirmed in step S659 that the error bit is in the reset state. That is, the re-payout process is always executed.

  As described above, the payout control means is used for paying out a game ball when the payout number counting switch 301 detects no game ball even though the ball payout device 97 pays out a game ball. After performing the corrected payout control that causes the ball payout device 97 to execute the retry operation for a predetermined number of times (for example, twice) as a limit, the payout number count switch 301 has detected no game balls. When it is detected (see step S661 and thereafter in FIG. 85), the control state related to the payout is shifted to the error state, and corrected payout control is performed again on condition that an error release signal is output from the error release switch 375 in the error state. The correction payout control restart process for executing

  Further, even during re-payout processing in an error state (specifically, during re-payout processing before setting a payout case error and during re-payout processing after the error release switch 375 is pressed), steps S601 to S601 shown in FIG. The process of S604 is being executed. That is, even when an error relating to payout occurs, if the game ball passes the payout number count switch 301, the value of the award ball unpaid number counter or the ball lending unpaid number counter is subtracted. Therefore, the value of the award ball unpaid number counter or the ball lending unpaid number counter when returning from the error state is a value reflecting the number of game balls actually paid out. That is, even if an error related to payout occurs, the number of game balls actually paid out can be accurately managed.

  Also, in the payout passing waiting process shown in FIGS. 84 to 86, even when it is confirmed that the game ball has been paid out as a result of the re-payout process, the payout case error bit is not reset. The bit of the payout case error is reset only when the error release switch 375 is operated (specifically, when an error return time after operation has elapsed) (steps S802 and S807). That is, the state of the payout case error (payout shortage error) is not automatically canceled based on the fact that the game ball has passed the payout number count switch 301, etc. The error is not cleared. Therefore, the game store clerk and the like can surely recognize that a shortage of payout has occurred.

  When the error cancel switch 375 is operated so as to be reset in hardware (reset to the payout control CPU 371), the error cancel switch 375 is operated, for example, a prize ball has not been paid out. The value of the number counter is also cleared. However, in this embodiment, since the payout control means is configured to perform the re-payout operation again by operating the error release switch 375, the payout process is executed reliably, which is disadvantageous to the player. Can not be given.

  In step S808, the payout control CPU 371 checks the detection signal of the full tank switch 48. If the detection signal of the full tank switch 48 is output (if it is in the ON state), the full tank error bit in the error flag is set (step S809). If the detection signal of the full tank switch 48 is in the OFF state, the full tank error bit is reset (step S810).

  Also, the payout control CPU 371 checks the detection signal of the ball break switch 187 (step S811). If the detection signal of the ball break switch 187 is output (if it is on), the ball break error bit in the error flag is set (step S812). If the detection signal of the ball break switch 187 is OFF, the ball break error bit is reset (step S813). When the ball break error bit is set, the bit corresponding to the ball break LED 52 in the output port 1 buffer is set to a value corresponding to the lighting state in the display control process of step S759.

  Further, the payout control CPU 371 checks the state of the connection confirmation signal from the main board 31 (step S815). If the connection confirmation signal is not output (if it is in the off state), the main board unconnected error bit is set. Set (step S816). If the connection confirmation signal is output (if it is on), the main board non-connection error bit is reset (step S817).

  Further, the payout control CPU 371 checks the value of the switch timer corresponding to the payout number count switch 301 among the switch timers in which the state of the detection signal of each switch is set, and the value is the switch on maximum time (for example, “ 240 ") (step S818), the bit of the payout switch abnormality detection error 1 is set in the error flag (step S819). If the value of the switch timer corresponding to the payout number count switch 301 is less than the switch-on maximum time, the bit of the payout switch abnormality detection error 1 is reset (step S820). Note that the value of each switch timer is incremented by 1 when the state of the input port to which the detection signal of each switch is input is switched on in the input determination process of step S751, and cleared by 0 when it is off. Accordingly, the fact that the value of the switch timer corresponding to the payout number count switch 301 exceeds the maximum switch-on time means that the payout number count switch 301 is in the ON state beyond the maximum switch-on time. Then, it is determined that the game ball is clogged at the disconnection of the payout number count switch 301 or at the portion of the payout number count switch 301.

  Further, the payout control CPU 371, when the value of the switch timer corresponding to the payout number count switch 301 becomes a switch-on determination value (eg, “2”) (step S821), the ball lending operation flag and the winning ball operation If both the middle flags are in the reset state, the game ball has passed through the payout number count switch 301 even though the payout operation is not in progress, and the bit of the payout switch abnormality detection error 2 in the error flag is set (steps S822 and S823). . If the ball lending operation flag or the winning ball operation flag is set, the bit of the payout switch abnormality detection error 2 is reset (step S824).

  The payout control CPU 371 confirms the input state of the VL signal from the card unit 50 (step S825). If the VL signal is not input (if it is in the off state), the prepaid card unit not yet out of the error flags is displayed. A connection error bit is set (step S826). If the VL signal is input (if it is on), the prepaid card unit unconnected error bit is reset (step S827).

  In addition, the payout control CPU 371 checks whether or not a prize ball excessive abnormality command reception flag is set (step S828). If the prize ball excessive abnormality command reception flag is set, the prize ball among the error flags An excessive abnormality error bit is set (step S829). In other words, since the game control means detects an excessive prize ball abnormality, the payout control CPU 371 sets an excessive prize ball error error bit. On the other hand, if the excessive prize ball abnormality command reception flag is not set, the payout control CPU 371 resets the excessive prize ball abnormality error bit (step S830).

  Further, the payout control CPU 371 checks whether or not a prize ball under / abnormal command reception flag is set (step S831), and if the prize ball under / abnormal command reception flag is set, a prize ball out of error flags is set. An under-abnormal error bit is set (step S832). That is, since the game control means detects a prize ball under-abnormality, the payout control CPU 371 sets a prize-ball under-abnormality error bit. If the prize ball under / abnormal command reception flag is not set, the payout control CPU 371 resets the prize ball under / abnormal error bit (step S833).

  In the display control process in step S759, notification by display (numerical value display) corresponding to the error bit in the error flag is performed by the error display LED 374. Therefore, a communication error can be notified by the error display LED 374. Further, since the communication error is detected on the payout control means side, the communication error can be detected without increasing the burden on the game control means.

  In this embodiment, the main board non-connection error is automatically eliminated when the connection confirmation signal is turned on (see steps S815 and S817), but the condition that the error release switch 375 is further operated is added. Thus, the error state may be eliminated.

  In this embodiment, a communication error is reported so as to be distinguishable from a communication error with the card unit 50 (a prepaid card unit unconnected error and a prepaid card unit communication error) and other errors (see FIG. 87). ). Therefore, a communication error between the game control microcomputer 560 and the payout control microcomputer 370 is easily identified.

  Next, the operation of the effect control means (sound / lamp control microcomputer 100b and symbol control microcomputer 100a) will be described. First, a method for sending a control command from the game control means to the sound / lamp control means will be described. FIG. 91 is an explanatory diagram showing a signal line of an effect control command transmitted from the main board 31 to the sound / lamp control board 80b. As shown in FIG. 91, in this embodiment, the effect control command is transmitted from the main board 31 to the sound / lamp control board 80b through the eight signal lines of the effect control signals CD0 to CD7. Further, between the main board 31 and the sound / lamp control board 80b, a signal line of an effect control INT signal for transmitting a capture signal (effect control INT signal) is also wired.

  In this embodiment, the effect control command has a 2-byte structure, the first byte represents MODE (command classification), and the second byte represents EXT (command type). The first bit (bit 7) of the MODE data is always set to “1”, and the first bit (bit 7) of the EXT data is always set to “0”. Note that such a command form is an example, and other command forms may be used. For example, a control command composed of 1 byte or 3 bytes or more may be used.

  As shown in FIG. 92, the 8-bit effect control command data of the effect control command is output in synchronization with the effect control INT signal. The sound / lamp control microcomputer 100b mounted on the sound / lamp control board 80b detects that the effect control INT signal has risen, and starts a 1-byte data capturing process through an interrupt process. Therefore, when viewed from the sound / lamp control microcomputer 100b, the effect control INT signal corresponds to a signal that triggers the acquisition of the effect control command data.

  The effect control command is sent only once so that the sound / lamp control microcomputer 100b can recognize it. In this example, “recognizable” means that the level of the production control INT signal changes, and that it is sent only once so as to be recognizable means that, for example, the first byte and the second byte of the production control command data respectively. Accordingly, the production control INT signal is output in a pulse shape (rectangular wave shape) only once. The effect control INT signal may have a polarity opposite to that shown in FIG.

  Next, the operation of the sound / lamp control means (sound / lamp control microcomputer 100b) will be described. FIG. 93 is a flowchart showing a main process executed by the sound / lamp control microcomputer 100b (specifically, the sound / lamp control CPU 101b) mounted on the sound / lamp control board 80b. When power supply to the gaming machine is started and the reset signal becomes high level, the sound / lamp control microcomputer 100b starts main processing. In the main process, the sound / lamp control microcomputer 100b first performs an initialization process for clearing the RAM area, setting various initial values, initializing a timer for determining the activation control activation interval, and the like. This is performed (step S781). Thereafter, the sound / lamp control microcomputer 100b shifts to a loop process for monitoring the timer interrupt flag (step S782). When a timer interrupt occurs, the sound / lamp control microcomputer 100b sets a timer interrupt flag in the timer interrupt process. If the timer interrupt flag is set in the main process, the sound / lamp control microcomputer 100b clears the flag (step S783) and executes the following sound / lamp control process.

  A timer interrupt takes, for example, every 2 ms. That is, the sound / lamp control process is activated every 2 ms, for example. In this embodiment, only the flag is set in the timer interrupt process, and the specific sound / lamp control process is executed in the main process, but the sound / lamp control process is executed in the timer interrupt process. Also good.

  In the sound / lamp control process, the sound / lamp control microcomputer 100b first analyzes the received effect control command (command analysis process: step S784).

  Next, the sound / lamp control microcomputer 100b performs an effect content determination process (step S785). In the effect content determination process, the sound / lamp control microcomputer 100b uses the variable display device 9 based on the effect control command (variation pattern command or display result designation command) (whether or not to perform the notice effect). Kaya, the type of notice effect). In addition, the sound / lamp control microcomputer 100b generates an effect content designation command indicating the determined effect content.

  Next, the sound / lamp control microcomputer 100b performs sound output processing (step S786). In this case, the sound / lamp control microcomputer 100b outputs sound number data (for example, sound number data corresponding to the variation pattern indicated by the variation pattern command) to the speech synthesis IC 173. Then, the voice synthesis IC 173 generates a voice or a sound effect corresponding to the sound number data and outputs it to the amplifier circuit 175.

  Next, the sound / lamp control microcomputer 100b performs lamp display processing (step S787). In this case, the sound / lamp control microcomputer 100b performs lamp control based on the lamp control execution data set in the process data.

  Further, the sound / lamp control microcomputer 100b executes a process of updating the random number counter (step S788). Further, the sound / lamp control microcomputer 100b performs a process of sending the effect control command received from the main board 31 and the effect content designation command generated in the effect content determination process in step S785 to the symbol control board 80a ( Command control processing: Step S789). Further, the sound / lamp control microcomputer 100b executes notification processing for notifying that a prize ball abnormality has occurred (step S790). Thereafter, the process returns to the process of checking the timer interrupt flag in step S782.

  An INT signal for effect control from the main board 31 is input to an interrupt terminal of the sound / lamp control microcomputer 100b. For example, when the INT signal from the main board 31 is turned on, the sound / lamp control microcomputer 100b is interrupted. Then, the sound / lamp control microcomputer 100b executes an effect control command reception process in the interrupt process. In the effect control command reception process, the sound / lamp control microcomputer 100b stores the received effect control command data in the command reception buffer.

FIG. 94 is an explanatory diagram showing random numbers used in the sound / lamp control processing. Each random number is used as follows.
(1) Random 1: Decide whether or not to execute a notice effect (for determining notice effect execution). In this embodiment, when the variable display device 9 performs variable display of the decorative pattern in the reach mode, the sound / lamp control microcomputer 100b matches, for example, random 1 with one predetermined value. In this case, it is determined that a notice effect is to be performed. Note that the sound / lamp control microcomputer 100b may determine whether or not to perform the notice effect using the random 1 regardless of whether or not the variable display of the reach mode is performed.
(2) Random 2: When performing the notice effect, the type of the notice effect performed using the variable display device 9 is determined (for determining the notice effect type).

  FIG. 95 is a flowchart showing effect content determination processing (step S785) shown in FIG. In the effect content determination process, the sound / lamp control microcomputer 100b confirms whether or not the variation pattern command reception flag is set (step S1851). The variation pattern command reception flag is a flag that is set based on confirmation that the variation pattern command has been received from the game control microcomputer 560 in the command control process (see step S789).

  If the variation pattern command reception flag is set, the sound / lamp control microcomputer 100b resets the variation pattern command reception flag and specifies the variation pattern of the decorative design based on the received variation pattern command. Further, the sound / lamp control microcomputer 100b determines whether or not the variable display to be executed using the variable display device 9 is a variation accompanied by reach based on the identified variation pattern (step S1852). For example, if the variation pattern indicated in the received variation pattern command is a pattern with reach, the sound / lamp control microcomputer 100b determines that the variation is accompanied by reach. . If the variation pattern command reception flag is not set in step S1851, the sound / lamp control microcomputer 100b ends the processing as it is.

  If it is determined that the variation is accompanied by reach, the sound / lamp control microcomputer 100b determines whether or not to perform the notice effect based on the notice effect execution determination random number (random 1) (step S1853). For example, the sound / lamp control microcomputer 100b determines to perform a notice effect using the variable display device 9 when the random 1 matches a predetermined value. If NO in step S1852, the sound / lamp control microcomputer 100b proceeds to step S1857.

  If it is determined in step S1854 that the notice effect is not performed, the sound / lamp control microcomputer 100b receives the variation pattern command and the display when the variation pattern command is received and the display result designation command is received. The result designation command is transmitted or transferred to the symbol control microcomputer 100a, and the symbol control microcomputer 100a executes variable display of the decorative symbol and the game effect using the variable display device 9. In this case, if the sound / lamp control microcomputer 100b determines not to perform the notice effect in step S1854, the sound / lamp control microcomputer 100b generates a notification command for designating that the notice effect is not performed, and transmits it to the symbol control microcomputer 100a ( Step S1857).

  If it is determined that the notice effect is to be performed (step S1854), the sound / lamp control microcomputer 100b determines the type of the notice effect to be performed using the variable display device 9 based on the random number for determining the notice effect type (random 2). Determination is made (step S1855). For example, the sound / lamp control microcomputer 100b can change the speed of the decorative symbol and the rotation direction of the decorative symbol in the notice effect based on the random 2, variable display device. 9 determines which character is to appear.

  In this embodiment, description will be made on the case where the production contents are determined based on the variation pattern command. However, the sound / lamp control microcomputer 100b is based on the display result designation command received from the game control microcomputer 560. Thus, it may be determined that the non-probable big hit or the probable big hit is the production content. In addition, the sound / lamp control microcomputer 100b receives the symbol deviation number designation command from the game control microcomputer 560, and based on the received symbol deviation number designation command, is the stop symbol a symbol with a reach? The content of the production may be determined by specifying whether or not. In this case, for example, when the game control microcomputer 560 determines the stop symbol as the reach / displacement symbol when determining the stop symbol of the decoration symbol in the special symbol stop symbol setting process (see step S301), Obtain the number of stoppages of the decorative symbol. Further, the game control microcomputer 560 generates a symbol deviation number designation command including a value that can specify the obtained deviation number, and transmits the command to the sound / lamp control microcomputer 100b. Then, the sound / lamp control microcomputer 100b specifies that the stop symbol is a reach / delay symbol based on the reception of the symbol deviation number command, and determines the contents of the effect.

  Furthermore, the sound / lamp control microcomputer 100b may determine the contents of the effect based on all the commands (the variation pattern command, the display result designation command, and the symbol deviation number designation command) described above. Further, the sound / lamp control microcomputer 100b determines the contents of the effect based on any two of the above-described commands (variation pattern command, display result designation command, and symbol deviation number designation command). May be.

  Further, the sound / lamp control microcomputer 100b generates an effect content designation command indicating the determined effect content (whether or not to perform the notice effect and the type of the notice effect). Then, the sound / lamp control microcomputer 100b performs a process of transmitting the generated effect content designation command to the symbol control board 80a (step S1856). Note that the sound / lamp control microcomputer 100b transfers or transmits the display result designation command and the variation pattern command to the symbol control board 80a together with the effect content designation command. Then, the symbol control microcomputer 100a of the symbol control board 80a performs symbol control process processing (to be described later) based on the effect content designation command, the display result designation command, and the variation pattern command received from the sound / lamp control microcomputer 100b. In step S1705), a decorative pattern variable variation and a game effect are performed. In this case, the symbol controlling microcomputer 100a causes the VDP 109 to perform a notice effect using the variable display device 9 based on the received effect content designation command.

  In step S1856, the sound / lamp control microcomputer 100b may add the determined effect content to the variation pattern command or the display result specification command instead of generating the effect content specifying command. For example, the sound / lamp control microcomputer 100b adds an effect content to a variation pattern command or a display result designation command by adding a value indicating the effect content to the header portion of the command. In this case, the sound / lamp control microcomputer 100b may add a value indicating the effect content to the header portion of only the variation pattern command, or add a value indicating the effect content to the header portion of only the display result designation command. May be. Further, the sound / lamp control microcomputer 100b may add a value indicating the effect content to the header portions of both the variation pattern command and the display result designation command. Then, the sound / lamp control microcomputer 100b may perform a process of transmitting a variation pattern command and a display result designation command to which the contents of the effect are added to the symbol control board 80a. When the notice effect is not performed, the sound / lamp control microcomputer 100b transfers the display result designation command received from the game control microcomputer 560 to the symbol control microcomputer 100a as it is.

  Also, in this embodiment, the command for specifying the contents of the effect is performed by executing the command control process (see step S789) in the sound / lamp control main process based on the setting of the address of the transmission table in step S1856. Is transmitted to the symbol control board 80a.

  In this embodiment, sound / lamp control side process data including lamp control execution data is stored in the ROM of the sound / lamp control board 80b. Further, symbol control side process data including display control execution data is stored in the ROM in the symbol control board 80a. In this embodiment, in step S1856, the sound / lamp control microcomputer 100b transmits an effect content designation command generated according to the determined effect content to the symbol control microcomputer 100a. The symbol control microcomputer 100a reads the display control execution data from the ROM based on the received effect content designation command, and performs the effect using the variable display device 9 based on the read display control execution data.

  In addition, when adding the effect content determined in step S1856 to the variation pattern command or the display result designation command, the sound / lamp control microcomputer 100b adds the determined effect content (for example, the background color or the appearing character). A variation pattern command or a display result designation command may be transmitted to the symbol control microcomputer 100a. The symbol control microcomputer 100a reads display control execution data from the ROM based on the received variation pattern command and display result designation command, and produces an effect using the variable display device 9 based on the read display control execution data. You may go.

  Further, process data including both display control execution data and lamp control execution data may be stored in the ROM of the sound / lamp control board 80b. In this case, the sound / lamp control microcomputer 100b may extract display control execution data corresponding to the determined effect content from the ROM, and transmit the display control execution data to the symbol control microcomputer 100a together with the generated effect content designation command. . Then, the symbol control microcomputer 100a may produce an effect using the variable display device 9 based on the received display control execution data.

  When process data including both display control execution data and lamp control execution data is stored in the ROM of the sound / lamp control board 80b, the sound / lamp control microcomputer 100b responds to the determined contents of the effect. The display control execution data may be extracted from the ROM and transmitted to the symbol control microcomputer 100a together with the variation pattern command and the display result designation command to which the determined production content is added. Then, the symbol control microcomputer 100a may produce an effect using the variable display device 9 based on the received display control execution data.

  FIG. 96 is a flowchart showing the notification process (step S790) shown in FIG. In the notification process, the sound / lamp control microcomputer 100b confirms whether or not a prize ball abnormality (excess prize ball abnormality or prize ball underabnormality) is being notified (step S881). When such notification is not performed, it is confirmed whether or not a prize ball excess abnormality command has been received (step S882a). When a prize ball excess abnormality command has been received, control for notifying the prize ball excess abnormality is performed using the speaker 27 and the lamps 25, 28a, 28b, and 28c (step S883a). Further, a value corresponding to the notification time is set in the notification timer in order to determine the notification time (step S884a). Thereafter, the process proceeds to step S891.

  If no prize ball excess abnormality command has been received, it is confirmed whether or not a prize ball excess abnormality command has been received (step S882b). If a prize ball underabnormality command has been received, control for notifying the prize ball underabnormality is performed using the speaker 27 and the lamps 25, 28a, 28b, 28c (step S883b). Further, a value corresponding to the notification time is set in the notification timer in order to determine the notification time (step S884b). Thereafter, the process proceeds to step S891.

  If the prize ball abnormality is notified, the value of the notification timer is decremented by 1 (step S888). If the value of the notification timer is not 0, that is, if it has not timed out, the process proceeds to step S891, but if it has timed out, the notification is terminated.

  In this embodiment, since the error notification process is started every 2 ms, the value corresponding to the notification time set in the notification timer is (notification time [ms] / 2). In this embodiment, when the value of the value according to the notification time is counted by the notification timer (counting in the subtraction direction), the sound / lamp control microcomputer 100b independently ends the notification. The initial value may be set to 0, count in the addition direction, and the notification may be terminated when the value of the notification timer becomes a value corresponding to the notification time.

  In step S891, the sound / lamp control microcomputer 100b confirms whether or not a payout abnormality notification start command has been received. If a payout abnormality notification start command has been received, control for notifying the payout abnormality is performed using the speaker 27 and the lamps 25, 28a, 28b, and 28c (step S892). Further, the sound / lamp control microcomputer 100b confirms whether or not a payout abnormality notification end command has been received (step S893). If the payout abnormality notification end command has been received, the notification ends.

  Next, the operation of the symbol control means (the symbol control microcomputer 100a) will be described. FIG. 97 is a flowchart showing a main process executed by the symbol control microcomputer 100a (specifically, the symbol control CPU 101a) mounted on the symbol control board 80a. When the power is turned on, the symbol control microcomputer 100a starts executing the main process. In the main processing, first, initialization processing is performed for clearing the RAM area, setting various initial values, and initializing a timer for determining the start interval of symbol control (step S1701). Thereafter, the symbol controlling microcomputer 100a shifts to a loop process for monitoring a timer interrupt flag (step S1702). When a timer interrupt occurs, the symbol control microcomputer 100a sets a timer interrupt flag in the timer interrupt process. If the timer interrupt flag is set in the main process, the symbol control microcomputer 100a clears the flag (step S1703) and executes the following symbol control process.

  In the symbol control process, the symbol control microcomputer 100a first analyzes the effect control command received from the sound / lamp control board 80b (command analysis process: step S1704). Next, the symbol control microcomputer 100a performs symbol control process processing (step S1705). In the symbol control process, a process corresponding to the current control state (symbol control process flag) is selected from the processes corresponding to the control state, and the display control of the variable display device 9 is executed. Further, random number update processing for updating the counter value of the counter for generating various random numbers is executed (step S1706).

  Further, the symbol controlling microcomputer 100a executes notification processing for notifying that a prize ball abnormality has occurred (step S1707). In this case, the symbol controlling microcomputer 100a follows the same processing as the notification processing executed by the sound / lamp controlling microcomputer 100b shown in FIG. Notify that a payout abnormality has occurred. However, the symbol control microcomputer 100a uses the variable display device 9 to notify that a prize ball abnormality or a payout abnormality has occurred. For example, the symbol control microcomputer 100a displays on the variable display device 9 that a prize ball abnormality or a payout abnormality has occurred. Thereafter, the process proceeds to step S1702.

  FIG. 98 is a flowchart showing the symbol control process (step S1705) in the main process shown in FIG. In the symbol control process, the symbol control CPU 101a performs one of steps S1800 to S1807 according to the value of the symbol control process flag. In each process, the following process is executed.

  Fluctuation pattern command reception waiting process (step S1800): It is confirmed whether or not an effect control command (variation pattern command) specifying a fluctuation pattern has been received from the sound / lamp control board 80b by the command reception interrupt process. Specifically, it is confirmed whether or not a flag (variation pattern reception flag) indicating that a variation pattern command has been received is set. The variation pattern reception flag is set when it is confirmed that a variation pattern command has been received in the command analysis processing executed by the symbol control CPU 101a. When a variation pattern command is received, the decoration pattern variation mode (variation speed of the decoration pattern during the variation period, background, character type, character display start time, etc.) is previously set according to each variation pattern. Select from a number of fixed types. In addition, when one type of variation mode is determined in advance for each variation pattern, it is determined to use the variation mode according to the received variation pattern. Then, the value of the symbol control process flag is updated to a value corresponding to the notice selection process (step S1801).

  Prior notice selection process (step S1801): For example, whether or not to perform a notice effect using a character image (an effect for informing in advance that a special symbol stop symbol becomes a big hit symbol or a reach occurs), The type of notice effect when performing is specified. In this embodiment, the notice effect to be performed using the variable display device 9 is specified based on the effect content designation command received from the sound / lamp control board 80b. Then, the value of the symbol control process flag is updated to a value corresponding to all symbol variation start processing (step S1802).

  All symbol variation start processing (step S1802): Control is performed so that the variation of the left middle right decorative symbol is started. Then, the value of the symbol control process flag is updated to a value corresponding to the symbol changing process (step S1803).

  Symbol variation processing (step S1803): The end of the variation time determined in accordance with the variation pattern is monitored. In addition, stop control of the left and right symbols is performed. When the variation time is over, if it is determined to be a jackpot, the value of the symbol control process flag is updated to a value corresponding to the jackpot symbol stop process (step S1804). If it is decided not to win, the value of the symbol control process flag is removed and updated to a value corresponding to the symbol stop processing (step S1805). In the symbol variation processing, the switching timing of each variation state (variation speed) constituting the variation pattern is also controlled.

  Big hit symbol stop process (step S1804): Control is performed to finally stop the variation of the decorative symbol and display the stop symbol (determined symbol). Then, the value of the symbol control process flag is updated to a value corresponding to the jackpot display process (step S1806). In this process, the symbol control CPU 101a causes the variable display device 9 to stop and display the decorative symbol jackpot symbol, but, similar to the control of the game control microcomputer 560, the symbol control process flag value is the jackpot symbol stoppage. It is preferable to continue the processing time for a predetermined time.

  Lost symbol stop process (step S1805): Control is performed to finally stop the variation of the decorative symbol and display the stop symbol (determined symbol). Then, the value of the symbol control process flag is updated to a value corresponding to the variation pattern command reception waiting process (step S1800). In this process, the symbol control CPU 101a causes the variable display device 9 to stop and display the decorative symbols.

  Big hit display processing (step S1806): Big hit display is controlled. Then, the value of the symbol control process flag is updated to a value corresponding to the big hit game processing (step S1807).

  Big hit game processing (step S1807): Control during the big hit game is performed. For example, when an effect control command for display before opening the big winning opening or display when opening the big winning opening is received, display control of the number of rounds is performed. When the big hit game ends, the value of the symbol control process flag is updated to a value corresponding to the variation pattern command reception waiting process (step S1800).

  In addition, the symbol control microcomputer 100a performs control for notifying the excessive excessive amount of prize balls using the variable display device 9 based on the reception of the excessive prize ball abnormality command in the notification process of step S1707. In this case, for example, as shown in FIG. 99A, the symbol controlling microcomputer 100a causes the variable display device 9 to display a screen for notifying that there is an abnormality in the prize ball payout. In addition, the symbol control microcomputer 100a performs control for notifying the prize ball under-abnormality using the variable display device 9 based on the reception of the prize-ball under-abnormality command in the notification process in step S1707. In this case, for example, as shown in FIG. 99 (B), the symbol controlling microcomputer 100a causes the variable display device 9 to display a screen for notifying that there is a shortage in the payout of prize balls.

  As described above, in this embodiment, when a game ball is paid out by the ball payout device 97, the total winning ball number storage buffer stores the number of game balls paid out in the timer interruption process. Subtract from the total number of winning balls. In addition, when the total number of winning balls is read from the total winning ball number storage buffer when the number of winning balls indicated in the winning ball number command is added to the total winning ball number in the main processing, the total number of winning balls after the addition is again Timer interrupt processing is prohibited until is written in the total number of winning balls storage buffer. Therefore, it is possible not to execute the process of subtracting the number of game balls paid out from the total number of winning balls between the time of reading the total winning ball number from the total winning ball number storage buffer and writing it again. Therefore, it is possible to prevent a situation in which the game control microcomputer 560 cannot grasp the number of paid-out game balls. Therefore, it is possible to prevent a deviation between the number of prize balls managed by the game control microcomputer 560 and the number of prize balls managed by the payout control microcomputer 370.

  Further, in this embodiment, the sound / lamp control microcomputer 100b uniquely determines the contents of the effect (whether or not to perform the notice effect and the type of the notice effect) based on the change pattern command. Further, the symbol control microcomputer 100a uses the variable display device 9 to execute a game effect according to the effect content determined by the sound / lamp control microcomputer 100b. Therefore, the game control microcomputer 560 does not have to determine the contents of the effects. Therefore, the processing load of the game control microcomputer 560 can be reduced.

  In this embodiment, the random number circuit 503 is initially set (random number circuit setting process) from the start of power-on to the gaming machine until the timer interrupt is set, and in the random number circuit setting process, A value based on an ID number unique to the control microcomputer 560 is set as an initial value of a random number. Therefore, the randomness of the random number generated by the random number circuit 503 can be improved. In addition, since the randomness of random numbers can be improved, the timing of random number generation can be made difficult to be recognized by a player or a game store, and by generating a capture signal using a radio signal for a gaming machine It is possible to prevent the condition for shifting to a specific gaming state such as a big hit state from being illegally established.

  Further, in this embodiment, when the serial communication circuit 505 makes an interrupt request, the interrupt process when the communication error causes the interrupt is preferentially executed, and the communication is controlled to be prohibited. Therefore, it is possible to prevent communication with the payout control microcomputer 370 of the payout control board 37 mounted on the gaming machine in a state where a communication error has occurred. Therefore, malfunction due to a communication error can be prevented.

  For example, when an overrun occurs in the serial communication circuit 505, the next received data is stored in the receiving shift register 713 before the received data in the received data register 711 is read. It is overwritten and the CPU 56 cannot read the received data correctly. For this reason, communication with the microcomputer mounted on each control board cannot be performed correctly, causing the game control microcomputer 560 to malfunction. In this embodiment, when an overrun occurs, the serial communication circuit 505 issues an interrupt request at the time of a communication error, and the CPU 56 controls the communication to a prohibited state. Therefore, it is possible to prevent the gaming control microcomputer 560 from malfunctioning due to the occurrence of overrun.

  Further, for example, if a noise error occurs in the serial communication circuit 505, there is a high possibility that correct received data cannot be received due to the noise, which causes the CPU 56 to malfunction. In this embodiment, when a noise error occurs, the serial communication circuit 505 makes an interrupt request at the time of a communication error, and the CPU 56 controls the communication to a prohibited state. Therefore, it is possible to prevent the CPU 56 from malfunctioning due to the occurrence of a noise error.

  Further, for example, when a framing error occurs in the serial communication circuit 505, it is in a state where the stop bit of the received data has not been correctly received. . In this embodiment, when a framing error occurs, the serial communication circuit 505 issues an interrupt request at the time of a communication error, and the CPU 56 controls the communication to a prohibited state. Therefore, it is possible to prevent the CPU 56 from malfunctioning due to the occurrence of a framing error.

  Further, for example, when a parity error occurs in the serial communication circuit 505, it is in a state where each data bit or parity bit of the received data has not been correctly received, so there is a high possibility that correct received data cannot be received, and the CPU 56 malfunctions. Cause. In this embodiment, when a parity error occurs, the serial communication circuit 505 makes an interrupt request at the time of a communication error, and the CPU 56 controls the communication to a prohibited state. Therefore, it is possible to prevent the CPU 56 from malfunctioning due to the occurrence of a parity error.

  In this embodiment, when a communication error occurs in the serial communication circuit 505, the award ball number command is transmitted to the payout control microcomputer 370 mounted on the payout control board 37, and the payout control microcomputer 370 receives the command. Control is performed to prohibit reception of a prize ball ACK command. For example, if a prize ball number command is transmitted to the payout control microcomputer 370 mounted on the payout control board 37 when a communication error occurs, an incorrect prize ball number command may be transmitted. Therefore, there is a possibility that an incorrect number of game balls may be paid out based on the number of prize balls indicated in the incorrect prize ball number command, which may affect the game result. In this embodiment, when a communication error occurs, control is performed so as to prohibit transmission of a prize ball number command to the payout control microcomputer 370 mounted on the payout control board 37, so that it is based on an incorrect prize ball command. It is possible to prevent an incorrect number of game balls from being paid out and affecting the game result.

  Note that when a communication error occurs in the serial communication circuit 505, only reception of data from a microcomputer mounted on each control board may be prevented. For example, consider a case where serial communication is performed between the game control means and the effect control means. In this case, the communication performed between the game control microcomputer 560 and the sound / lamp control microcomputer 100b is only transmission of the effect control command from the game control microcomputer 560 to the sound / lamp control microcomputer 100b. No command is transmitted from the sound / lamp control microcomputer 100b to the game control microcomputer 560. That is, communication in only one direction is performed between the game control microcomputer 560 and the sound / lamp control microcomputer 100b. Further, even if an erroneous effect control command is transmitted from the game control microcomputer 560 to the sound / lamp control board 80b, an erroneous effect display is only performed on the variable display device 9, and an incorrect payout process is performed. Compared with the case where the game is executed, the influence on the game result is small. Therefore, when serial communication is performed between the game control means and the effect control means, if a communication error occurs in the serial communication circuit 505, the game control microcomputer 560 controls to prohibit only data reception. Also good.

  In this embodiment, the expression “the serial communication circuit 505 issues an interrupt request to the CPU 56” is used. Specifically, when an interrupt factor such as transmission / reception of data or occurrence of a communication error occurs. In addition, the interrupt control circuit 714 of the serial communication circuit 505 sets a set value to a corresponding bit (bit corresponding to an interrupt factor) of the status register A 705 and outputs an interrupt signal (internal IRQ) to the CPU 56. An interrupt request is made by the serial communication circuit 505. For example, when a communication error occurs, the interrupt control circuit 714 of the serial communication circuit 505 sets a set value in a corresponding bit (bits 0 to 3 corresponding to the communication error) of the status register A 705 and also sends an interrupt signal to the CPU 56. Is output, the serial communication circuit 505 issues an interrupt request when a communication error occurs.

  In this embodiment, since the payout detection signal from the payout number count switch 301 is input to the main board 31 via the payout control board 37, the payout detection signal is output. It is not necessary to provide wiring on both the main board 31 and the payout control board 37 from the payout number count switch 301. Therefore, the wiring for outputting the payout detection signal from the payout number count switch 301 can be reduced.

  Note that a payout detection signal from the payout number count switch 301 may be directly input to the main board 31. In this case, wiring for outputting a payout detection signal from the payout number count switch 301 is provided on both the main board 31 and the payout control board 37. Based on the payout detection signal directly input from the payout count switch 301, the game control microcomputer 560 performs a subtraction process for the total number of winning balls stored in the total winning ball number storage buffer in the input determination process.

  In this embodiment, the game control microcomputer 560 transmits an award ball excess abnormality command or an award ball underabnormality command indicating that an abnormality has occurred in the award ball payout to the payout control microcomputer 370 for the payout. The control microcomputer 370 makes a notification based on the received award ball excess abnormality command or a prize ball underabnormality command. Therefore, it is possible to notify an error state of payout of a prize ball.

  In this embodiment, the gaming control microcomputer 560 transmits a prize ball excess abnormality command or a prize ball underabnormality command to the sound / lamp control microcomputer 100b to indicate that an abnormality has occurred in the awarding of prize balls. The sound / lamp control microcomputer 100b makes a notification using sound or a lamp based on the received excessive prize ball abnormality command or prize ball underabnormality command. In addition, the symbol control microcomputer 100a gives notification using the variable display device 9 based on the transferred award ball excess abnormality command or prize ball underabnormality command. Therefore, it is possible to notify an error state of payout of a prize ball.

  In this embodiment, an effect control command from the main board 31 is first received by the sound / lamp control board 80b, and further, a variation pattern command and an effect content designation command are sent from the sound / lamp control board 80b to the symbol control board 80a. In the above description, the effect control command from the main board 31 may be first received by the symbol control board 80a.

  FIG. 100 is a block diagram showing another circuit configuration example of the relay board 77, the sound / lamp control board 80b, and the symbol control board 80a. When the circuit configuration shown in FIG. 100 is used, for example, the symbol controlling microcomputer 100a follows the same processing as steps S1851 to S1856 based on the variation pattern command (whether or not to perform the notice effect, Determine the type of production). Then, the symbol controlling microcomputer 100a causes the VDP 109 to perform a notice effect using the variable display device 9 in accordance with the determined effect contents. Further, the symbol control microcomputer 100a may generate an effect content designation command indicating the determined effect content and transmit it to the sound / lamp control board 80b. The sound / lamp control microcomputer 100b mounted on the sound / lamp control board 80b performs display control of the lamps 25, 28a, 28b, 28c in accordance with the contents of the effect indicated by the received effect content designation command. Sound output control of the sound output device 27 may be performed.

  In this embodiment, the case where the sound / lamp control board 80b and the symbol control board 80a are used as the case where each effector is controlled using separate control boards has been described. You may control each effect means using. For example, each rendering means may be controlled using a sound control board that controls the sound output device 27, a lamp control board that controls each lamp, and a symbol control board that controls the variable display device 9. In this case, for example, an effect control command from the main board 31 is first received by the sound control board, and the sound control microcomputer mounted on the sound control board receives the effect contents (the notice effect) based on the received variation pattern command. Whether or not to perform, and the type of the notice effect) may be determined. The production control command from the main board 31 is first received by the lamp control board or the design control board, and the microcomputer mounted on the lamp control board or the design control board determines the production contents or specifies the variation time. Also good. Further, for example, each rendering means may be controlled using a sound / design control board for controlling the sound output device 27 and the variable display device 9 and a lamp control board for controlling each lamp. Further, for example, each rendering means may be controlled using a lamp / design control board for controlling each lamp and the variable display device 9 and a sound control board for controlling the sound output device 27.

Embodiment 2. FIG.
In each of the embodiments described above, the case has been described in which the CPU 56 sets or changes which interrupt process has priority over the interrupt process corresponding to the interrupt request from the serial communication circuit 505. However, when a timer interrupt and an interrupt request from the serial communication circuit 505 are generated at the same time, it may be possible to set or change which interrupt processing is to be preferentially executed. A second embodiment for setting or changing which of the timer interrupt and the interrupt request from the serial communication circuit 505 is to be prioritized will be described below.

  In the present embodiment, detailed description of the parts having the same configuration and processing as those of the first embodiment will be omitted, and parts different from the first embodiment will be mainly described.

  First, the main process in the second embodiment will be described. FIG. 101 is a flowchart showing main processing in the second embodiment. Of the main processing, the processing from step S1 to step S6 (including step S80) is the same as the processing shown in the first embodiment (see FIG. 43). In the main process shown in FIG. 101, the processes from step S7 to step S15a (including the processes from step S91 to step S93) are the same as those shown in the first embodiment.

  When the serial communication circuit setting process in step S15a is executed and the serial communication circuit 505 is initialized, the CPU 56 executes the timer interrupt process executed when a timer interrupt occurs and the interrupt request of the serial communication circuit 505. The priority of interrupt processing is initially set (step S15c).

  For example, the CPU 56 initializes the priority of each interrupt process according to a predetermined interrupt process priority table including the default priority of each interrupt process. FIG. 102 is an explanatory diagram illustrating an example of an interrupt processing priority table according to the second embodiment. In this embodiment, the CPU 56 is initially configured to preferentially execute an interrupt process whose cause is a communication error in the serial communication circuit 505 in accordance with the interrupt process priority table shown in FIG. Set. That is, the CPU 56 sets by default so that an interrupt process (in this example, a communication error interrupt process) by an interrupt request from the serial communication circuit 505 is executed in preference to the timer interrupt process. In this case, for example, the CPU 56 sets an interrupt priority execution flag at the time of communication error indicating that priority is given to an interrupt process whose cause is an interrupt.

  In this embodiment, in step S15c, the interrupt processing priority is initially set according to the interrupt processing priority table shown in FIG. 102, so that the timer interrupt and the interrupt request from the serial communication circuit 505 are performed. Occur at the same time, priority is given to interrupt processing for an interrupt request from the serial communication circuit 505.

  In addition, the default priority of each interrupt process can be changed by the user. For example, the game control microcomputer 560 stores specification information for specifying an interrupt process set by a user (for example, a game machine manufacturer) in a predetermined storage area of the ROM 54 in advance. Then, the CPU 56 sets the priority of interrupt processing according to the designation information stored in a predetermined storage area of the ROM 54.

  For example, a case where a timer interrupt process is designated in designated information stored in advance will be described. In this case, based on the designation information, the CPU 56 performs timer interrupt processing for each interrupt processing for the interrupt request from the serial communication circuit 505 (communication error interrupt processing, reception interrupt processing, and transmission completion interrupt processing). ) To be executed in preference to (). That is, in the interrupt processing priority table shown in FIG. 102, the interrupt processing is set by default so as to preferentially execute the interrupt processing that causes the occurrence of a communication error in the serial communication circuit 505. Based on the designation information set by the user, the CPU 56 changes the priority of the interrupt process so that the timer interrupt process is executed with priority. In this case, for example, the CPU 56 sets a timer interrupt priority execution flag indicating that timer interrupt processing is executed with priority.

  Further, the processes from step S16 to step S19 are the same as those shown in the first embodiment. When the interrupt-permitted state is set in step S19, the timer interrupt or interrupt request from the serial communication circuit 505 is permitted until the next processing in step S17 is executed and the interrupt-prohibited state is set. . When a timer interrupt occurs while the interrupt permission state is set, the game control microcomputer 560 executes a timer interrupt process to be described later. When an interrupt request is generated from the serial communication circuit 505 while the interrupt permission state is set, the CPU 56 of the game control microcomputer 560 causes each interrupt process (communication error interrupt process or reception Execute time interruption processing and transmission completion interruption processing). Further, in the present embodiment, by executing step S15c before the loop processing from step S17 to step S19, the timer interrupt processing and Processing for setting or changing the priority of interrupt processing in response to an interrupt request from the serial communication circuit 505 is performed.

  In the loop process from step S17 to step S19 in the main process, if there is an interrupt request from the serial communication circuit 505 during the interrupt enabled state, the CPU 56 of the game control microcomputer 560 follows the process shown in FIG. The serial communication circuit 505 executes interrupt processing according to the interrupt cause for which an interrupt request has been made. Further, when a timer interrupt occurs in the loop process from step S17 to step S19 in the main process, the CPU 56 executes the timer interrupt process according to the process shown in FIG.

  In this embodiment, when a timer interrupt and an interrupt request from the serial communication circuit 505 occur at the same time, the CPU 56 determines whether or not an interrupt process is preferentially executed. . For example, the CPU 56 determines whether or not any interrupt process is preferentially executed. For example, the CPU 56 preferentially executes timer interrupt processing based on the setting of the timer interrupt priority execution flag.

  As described above, in this embodiment, the CPU 56 sets each interrupt corresponding to the interrupt request from the timer interrupt process and the serial communication circuit 505 before setting the interrupt enabled state in the main process. Initialize processing priority. Therefore, among the interrupt processing corresponding to the timer interrupt processing and the plurality of types of interrupt causes, the interrupt processing to be executed with priority can be surely executed. Further, since the interrupt process to be executed with priority can be initially set, the degree of freedom of the program executed by the CPU 56 of the game control microcomputer 560 can be improved.

  In the above-described embodiment, the characteristic configuration of the gaming machine as shown below is also shown.

  The payout means pays out the prize game medium as a prize based on the fact that the game medium is won in a plurality of prize areas where the number of prize game media to be paid out is different. A plurality of winning detection means (for example, winning port switches 29a, 30a, 33a, 39a) and the number of prize game media to be paid out (for example, the number of prize balls “3”, “ 10 ”,“ 15 ”) for each payout number storage means (for example, prize ball command output counters 1 to 3) for storing payout number data and any winning area based on the input detection signal from each winning detection means. Winning area specifying means for specifying whether or not a game ball has won (for example, in the game control microcomputer 560, a prize ball command output counter pointed to by a pointer in step S2121) The payout number registering means includes payout number data indicating the number of prize game media to be paid out based on winning in the winning area specified by the winning area specifying means. It may be configured to be stored in the storage means (for example, in the game control microcomputer 560, the addition result is stored in the prize ball command output counter pointed to by the pointer in step S2124). According to such a configuration, the prize game medium corresponding to the identified prize area is identified in which prize area of the plurality of prize areas where the number of prize game media to be paid out is different. Since it is configured to store the payout number data indicating the number of payouts, it is possible to store the payout number data indicating the payout number corresponding to the winning area where the game ball has won. Therefore, the game control means can manage the number of winning balls based on the number of payouts according to the winning area where the game balls have won.

  The present invention is applicable to gaming machines such as pachinko gaming machines and slot machines, and particularly suitably applied to gaming machines that perform control for managing the number of winning balls to be paid out using a total winning ball number storage buffer. it can.

It is the front view which looked at the pachinko game machine from the front. It is a front view which shows the front surface of the game board in the state which removed the glass door frame. It is the rear view which looked at the gaming machine from the back. It is a block diagram which shows the structural example of a game control board (main board). It is a block diagram which shows the circuit structural example of a payout control board. It is a block diagram which shows the circuit structural example of a relay board | substrate, a sound / lamp control board, and a symbol control board. FIG. 10 is a block diagram showing a circuit configuration of a main board and signal lines of an effect control command transmitted from the main board to the sound / lamp control board. It is a block diagram which shows the structural example of a random number circuit. It is explanatory drawing which shows the example of an update rule selection register. It is explanatory drawing which shows the example of an update rule memory. It is explanatory drawing which shows the example in case a count value permutation change circuit changes the permutation of the count value which a counter outputs. It is explanatory drawing which shows the example of a count value permutation change register. It is explanatory drawing which shows the example of a random number maximum value setting register. It is explanatory drawing which shows the example of a period setting register. It is explanatory drawing which shows the example of a count value update register. It is explanatory drawing which shows the example of a random value taking-in register. It is explanatory drawing of an example of the random number update system selection register and the random number update system selection data written in the random number update system selection register. It is explanatory drawing which shows the example of a random number circuit starting register. It is a circuit diagram which shows one structural example of a random value memory circuit. It is a timing chart which shows the timing when each signal is input into a random value storage circuit, and the timing when a random value storage circuit outputs each signal. It is a block diagram which shows the structural example of the transmission part of a serial communication circuit. It is a block diagram which shows the structural example of the receiving part of a serial communication circuit. It is explanatory drawing which shows the example of the data format of the data which serial communication transmits / receives with the microcomputer mounted in each control board. It is explanatory drawing which shows the example of a baud rate register. It is explanatory drawing which shows the example of the control register A and communication format setting data. It is explanatory drawing which shows the example of the control register B and interrupt request setting data. It is a figure which shows the example of status register A and status confirmation data. It is a figure which shows the example of status register B and status confirmation data. It is explanatory drawing which shows the example of the control register C and error interrupt request setting data. It is explanatory drawing which shows the example of the data register with which a serial communication circuit is provided. It is explanatory drawing which shows an example of the address map of the storage area in the microcomputer for game control. It is explanatory drawing which shows an example of the address map in a user program management area. It is explanatory drawing which shows an example of initial value change system setting data. It is explanatory drawing which shows the structural example of a user program. It is explanatory drawing which shows the structural example of a random number circuit setting program. It is explanatory drawing which shows the operation | movement which updates the value of random R, or reads the value of random R, when the 1st random number update system is selected. It is explanatory drawing which shows the operation | movement which updates the value of random R, or reads the value of random R, when the 2nd random number update system is selected. It is explanatory drawing which shows each memory with which the microcomputer for game control is provided. It is explanatory drawing which shows the example of the table memory for jackpot determination. It is explanatory drawing which shows the example of bit allocation of the output port in a game control means. It is explanatory drawing which shows the example of bit allocation of the output port in a game control means. It is explanatory drawing which shows the bit allocation example of the input port in a game control means. It is a flowchart which shows the main process which the microcomputer for game control performs. It is a flowchart which shows the main process which the microcomputer for game control performs. It is a flowchart which shows the main process (main loop) which the microcomputer for game control performs. It is explanatory drawing which shows the example of an interruption process priority table. It is a flowchart which shows a random circuit setting process. It is a flowchart which shows a random number maximum value reset process. It is a flowchart which shows an initial value change process. It is a timing chart which shows the timing when each signal is input into a random number circuit, and the timing when each signal is generated in a random number circuit. It is a flowchart which shows a serial communication circuit setting process. It is explanatory drawing which shows an example of the content of the control signal output with respect to the payout control means from a game control means. It is explanatory drawing which shows an example of the content of the control command transmitted / received between a game control means and a payout control means. It is a block diagram which shows the signal line etc. which are used for transmission / reception of a control signal and a control command. It is a timing chart showing an example of how to output a payout control signal and a payout control command. 6 is a flowchart illustrating an example of an interrupt process performed by the serial communication circuit in response to an interrupt request. It is explanatory drawing which shows the example of a prize ball number table. It is a flowchart which shows an example of a prize ball process. It is a flowchart which shows a prize ball number command transmission process. It is a flowchart which shows a prize ball transmission completion waiting process. It is a flowchart which shows a prize ball ACK waiting process. It is a flowchart which shows a prize ball re-transmission process. It is a flowchart which shows a prize ball abnormality detection process. It is a flowchart which shows an example of a special symbol process process. It is a flowchart which shows a starting port switch passage process. It is a flowchart which shows an example of a special symbol normal process. It is a flowchart which shows a timer interruption process. It is explanatory drawing which shows each 2 byte buffer formed in RAM used by switch processing. It is a flowchart which shows the process example of a switch process. It is explanatory drawing which shows the example of a prize ball command output counter processing table. It is a flowchart which shows an input determination process. It is a flowchart which shows an input determination process. It is a timing chart showing an example of the timing at which the addition process and the subtraction process of the total prize ball number stored in the total prize ball number storage buffer are performed. It is a flowchart which shows a random circuit initial value update process. It is a flowchart which shows a count value permutation change process. It is explanatory drawing which shows the bit allocation example of the output port in a payout control means. It is explanatory drawing which shows the example of bit allocation of the input port in a payout control means. It is a flowchart which shows the main process which CPU for payout control performs. It is a flowchart which shows the timer interruption process which CPU for payout control performs. It is a flowchart which shows a main control communication process. It is a flowchart which shows a prize ball lending control process. It is a flowchart which shows the payout start waiting process. It is a flowchart which shows a payout motor stop waiting process. It is a flowchart which shows payout passage waiting processing. It is a flowchart which shows payout passage waiting processing. It is a flowchart which shows payout passage waiting processing. It is explanatory drawing which shows an example of the relationship between the kind of error, and the display of LED for an error display. It is a flowchart which shows an error process. It is a flowchart which shows an error process. It is a flowchart which shows an error process. FIG. 38E illustrates an effect control command signal line. It is a timing chart showing the relationship between an 8-bit control signal and an INT signal that constitute an effect control command. It is a flowchart which shows the main process which the microcomputer for sound / lamp control performs. It is explanatory drawing which shows each random number used by a sound / lamp control process. It is a flowchart which shows production content determination processing. It is a flowchart which shows an alerting | reporting process. It is a flowchart which shows the main process which the microcomputer for symbol control performs. It is a flowchart which shows a symbol control process process. It is explanatory drawing which shows the example of the alerting | reporting screen which alert | reports a prize ball abnormality. It is a block diagram which shows the other circuit structural example of a relay board | substrate, a sound / lamp control board, and a symbol control board. It is a flowchart which shows the main process in 2nd Embodiment. It is explanatory drawing which shows the example of the interruption process priority table in 2nd Embodiment.

Explanation of symbols

1 Pachinko machine 9 Variable display device 14 Start winning opening 15 Variable winning ball device 31 Game control board (main board)
37 Dispensing control board 56 CPU
80a design control board 80b sound / lamp control board 100a design control microcomputer 100b sound / lamp control microcomputer 101a design control CPU
101b Sound / lamp control CPU
503a 12-bit random number circuit 503b 16-bit random number circuit 505 Serial communication circuit 560 Microcomputer for game control

Claims (7)

A gaming machine in which a player can play a predetermined game using a game medium and pays out a prize game medium as a prize based on the winning of the game medium in a winning area in the gaming area,
Winning detection means for detecting that a game medium has won in the winning area and outputting a winning detection signal;
A game control means for receiving a winning detection signal from the winning detection means and controlling the progress of the game;
And dispensing means pays out Jing products game media,
A payout detection means for outputting a payout detection signal is detected and that the scene goods game media is paid out by the payout means,
A payout control means for controlling the payout means,
The game control means includes
Main process execution means for repeatedly executing a predetermined main process;
Timer interrupt setting means for setting a timer interrupt generated every predetermined time;
Timer interrupt processing execution means for interrupting the execution of the main processing and executing the timer interrupt processing when the timer interrupt occurs;
During the execution of the timer interruption process, in accordance with the input of the winning detection signal, the number-of-payout registration means for storing the number-of-payout data that can specify the number of prize game media to be paid out in the number-of-payout storage means;
The number of payouts to be sent to the payout control means during the execution of the main process based on the payout number data stored in the payout number storage means to specify the number of prize game media to be paid out A transmission means;
Total unpaid number storage means for storing a total unpaid number indicating the total number of prize game media to be paid out and for which the payout means has not been paid out;
During execution of the main process,
Reading means for reading out the total unpaid number from the total unpaid number storage means;
A number-of- payout addition unit for adding the number of premium game media indicated in the number-of-payments command transmitted by the number-of-payout transmission unit to the total number of unpaid outs read by the reading unit;
A payout number writing means for writing the total unpaid number added by the payout number adding means into the total unpaid number storage means;
And interrupt inhibit means for the reading means prohibits execution of the timer interrupt processing before reading the total non-payout,
An interrupt permission means for permitting execution of the timer interrupt process when a total unpaid number is written in the total unpaid number storage means by the payout number writing means;
During execution of the timer interruption process, the number of premium game media paid out by the payout means is subtracted from the total number of payouts stored in the total payout number storage means based on the payout detection signal. A total unpaid number subtraction means;
When the number of premium game media indicated in the payout number command is added to the total number of payouts by the payout number addition means, the total number of payouts obtained by adding the number of premium game media indicated in the payout number command is calculated. A gaming machine, comprising: a payout amount judging means for judging whether or not it is within a predetermined range. Game control means, when it is determined not to be within a predetermined range by the payout amount determination means pairs for transmitting abnormality occurrence command indicating that an abnormality has occurred in the payout of the prize game medium by payment detecting means, to the payout control means Including a payout abnormality occurrence command transmission means,
The payout control means based on the abnormality occurrence command received from the game control unit, said dispensing means according to claim 1, further comprising a dispensing side abnormality informing means for informing that an abnormality has occurred in the payout of the prize game media by Game machines. Providing production control means for controlling the electrical parts for production and executing the game production,
Game control means, when it is determined not to be within a predetermined range by the payout amount determining means, an abnormality occurrence command indicating that an abnormality has occurred in the payout of the prize game medium by payment detecting means, transmitting to the presentation control means Including an anomaly generation command transmission means
The presentation control means, based on the abnormality occurrence command received from the game control unit, according to claim 1 or abnormal payout of prize game media including directing side abnormality informing means for informing of the occurrence by said dispensing means The gaming machine according to claim 2. The number-of-payout determination means is
Excessive payout abnormality, in which more game media are paid out than the number of prize game media to be paid out based on the total number of payout game media added to the number of prize game media indicated in the payout number command by the payout number adding means An excessive payout abnormality determination means for determining whether or not
Based on the total non-payout number is added to the prize game media indicated in the payout command by the payout amount adding means, payout total unpaid coin number is abnormal state exceeds a predetermined payout under-determination value A payout underabnormality judging means for judging whether or not an underabnormality has occurred,
Anti-payout abnormality occurrence command transmission means
When it is determined that the excessive payout abnormality has occurred by the excessive payout abnormality determining means, an excessive payout abnormality command transmitting means for transmitting to the payout control means a payout excessive abnormality command indicating that the excessive payout abnormality has occurred. ,
When the payout too little abnormality is determined to have occurred by the payout under-abnormality determining means, the dispensing under-abnormality a payout under-abnormal command indicating occurrence, versus payout under-abnormality command transmission means for transmitting to said dispensing control means Including
The payout side abnormality notification means
Based on the payout excess abnormality command received from the game control means, payout side excess notification means for notifying that the payout excess abnormality has occurred;
Based on the payout under-abnormality command received from the game controller, the gaming machine of claim 2, further comprising a dispensing side under-informing means for informing that said dispensing too little abnormality occurs. The number-of-payout determination means is
Excessive payout abnormality, in which more game media are paid out than the number of prize game media to be paid out based on the total number of payout game media added to the number of prize game media indicated in the payout number command by the payout number adding means An excessive payout abnormality determination means for determining whether or not
Based on the total non-payout number is added to the prize game media indicated in the payout command by the payout amount adding means, payout total unpaid coin number is abnormal state exceeds a predetermined payout under-determination value A payout underabnormality judging means for judging whether or not an underabnormality has occurred,
The command transmission means for the production abnormality occurrence command is
When it is determined that the excessive payout abnormality has occurred by the excessive payout abnormality determining means, an excessive payout abnormality command transmitting means for transmitting to the effect control means a payout excessive abnormality command indicating that the excessive payout abnormality has occurred. ,
When the payout under-abnormality by judging means and said dispensing too little abnormality is determined to have occurred, the dispensing under-abnormality a payout under-abnormal command indicating occurrence pairs demonstration under-abnormality command transmission means for transmitting to said presentation control means Including
Production side abnormality notification means,
On the basis of the payout excess abnormality command received from the game control means, the production side excess notification means for notifying that the payout excess abnormality has occurred,
Based on the payout under-abnormality command received from the game controller, the gaming machine of claim 3 further comprising a directing side under-informing means for informing that said dispensing too little abnormality occurs.   The game control means includes a payout number transmission prohibiting means for prohibiting transmission of a payout number command by the payout number transmitting means when it is determined by the payout number determining means that an abnormality has occurred in payout of the prize game medium by the payout means. The gaming machine according to any one of claims 1 to 5. Withdrawal control means
A payout detection signal input means for inputting a payout detection signal from the payout detection means;
A payout detection signal output means for outputting the payout detection signal input by the payout detection signal input means to the game control means;
External output means for externally outputting a signal indicating the number of premium game media paid out by the payout means in response to the input of the payout detection signal;
Total non payouts subtracting means, the total in response to an input of the payout detection signal inputted from the dispensing control means, the number of prize game media paid out by the payout means, the total non-payout storage means for storing The gaming machine according to any one of claims 1 to 6, wherein the gaming machine is subtracted from an unpaid number.

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