JP5265427B2 - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent possible missing of commands or others without considering the output timing of the commands in a game machine which has a bidirectional serial communication between a board and a putout control board. <P>SOLUTION: A microcomputer for game control and a microcomputer for putout control transmit or receive in a serial communication signals (prize ball request signal as connection checking command and reception ACK signal as connection OK command) therebetween per a prescribed cycle (1s). When a prescribed error (prize ball error, full tank error or ball exhaustion error) occurs to disable the putting out of prize balls, the microcomputer for putout control sets a data indicating ongoing preparation for the putting out of the prize balls by changing the upper 4 bits of the reception ACK signal, sets a data that allows the specification of the prescribed error by changing the lower 4 bits of the reception ACK signal and then, transmits the reception ACK signals set. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention is a pachinko machine or slot that allows a player to play a predetermined game using a game medium and pays out a prize game medium as a prize based on the winning of the game medium in a prize area in the game area. Related to gaming machines such as machines and parrot machines.

  As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a prize area such as a prize opening provided in the game area, a predetermined number of game media are paid out to the player. There is something to be done. In addition, when a premium game medium is inserted, a predetermined number of bets are set, a plurality of types of symbols are rotated by operating the operation lever, and the symbols are stopped when the symbols are stopped by operating the stop button. There are cases where a predetermined number of premium game media are paid out to a player when a specific symbol combination is obtained. Also, when a predetermined number of bets are set according to the number of game media taken in, a plurality of types of symbols are rotated by operating the operation lever, and the symbols are stopped when the symbols are stopped by operating the stop button. When the combination becomes a combination of specific symbols, a predetermined number of game media may be paid out to the player.

  Game progress in the gaming machine is controlled by game control means such as a microcomputer. If the payout control means for controlling the payout of game media is mounted on a payout control board different from the game control board (main board) on which the game control means is mounted, the progress of the game is mounted on the main board Therefore, the number of prize game media based on the winning is determined by the game control means, and a control command indicating the number of prize game media is transmitted to the payout control board. Then, the payout control means performs a process of paying out the prize game medium based on the winning based on the control command from the game control means.

  There is also a gaming machine that inputs / outputs (transmits / receives) signals between a main board and a payout control board by bidirectional serial communication (for example, see Patent Document 1). In the gaming machine described in Patent Document 1, when the payout control board normally inputs a signal (command) output from the main board, an ACK signal that is a confirmation signal indicating that the signal has been input normally is received. Output to the main board.

JP 2007-275239 A (paragraph 0037 and the like, FIG. 6)

  In the gaming machine described in the above-mentioned Patent Document 1, it is possible to check each other's state by performing bi-directional communication on the winning ball between the main board and the payout control board, but paying out regarding an error (abnormal state) If the control board tries to output a command, the output timing of the command becomes irregular, and there is a possibility that the main board cannot correctly input the command from the payout control board.

  Accordingly, the present invention provides a gaming machine capable of preventing the occurrence of command misses and the like without considering the command output timing in a gaming machine in which a main board and a payout control board perform bidirectional serial communication. For the purpose.

  The gaming machine according to the present invention is based on the fact that a player can play a predetermined game using a game medium and a predetermined payout condition is satisfied (for example, a game ball wins a winning opening). A gaming machine that pays out a prize game medium as a prize, a game control microcomputer (for example, a game control microcomputer 560) that controls the progress of the game, and a payout means (for example, a ball) that pays out the prize game medium A payout device 97) and a payout control microcomputer (for example, a payout control microcomputer 370) for controlling the payout means. The game control microcomputer and the payout control microcomputer receive signals by serial communication. The game control microcomputer outputs a request signal (for example, connection confirmation) every predetermined period (for example, 1 s). Command signal output means (for example, a part for executing step S511 in the game control microcomputer 560) and a prize to be paid out based on a predetermined payout condition being satisfied. A payout number storage means for storing payout number data for specifying the number of game media (for example, 3, 10, 15) (for example, a part for executing step S2124 in the game control microcomputer 560 and the RAM 55) And the payout control microcomputer receives a response signal (for example, a connection OK command as a received ACK signal) based on the input of the request signal output by the request signal output means. Response signal output to the game control microcomputer The request signal output means, when outputting the request signal, on the basis of the payout number data stored in the payout number storage means, including a stage (for example, a portion for executing step S547 in the payout control microcomputer 370). Data for specifying the number of premium game media to be paid out is set, and a payout number output for outputting a request signal (for example, a prize ball number command as a prize ball request signal) to the payout control microcomputer is set. Means (for example, a part for executing step S508 in the game control microcomputer 560). The payout control microcomputer is based on the request signal output by the payout number output means and is specified by the request signal. The prize game medium payout control means (for example, a prize game medium payout means for controlling the payout means to pay out The response signal output means prepares for the payout of the prize game medium when the payout game medium cannot be paid out. The data indicating that it is in the middle is set by changing predetermined bits (for example, the upper 4 bits) of the response signal, and the response signal (for example, a command for preparing a prize ball as a received ACK signal) is set. Preliminary signal output means for outputting to the game control microcomputer (for example, the portion for executing step S551 in the payout control microcomputer 370), and a predetermined error (for example, a prize ball error, a full tank error, a ball shortage error, a door) When a release error occurs), the gaming control microcomputer Data that can recognize a specific error is set by changing a specific bit (for example, lower 4 bits) of a response signal, and the response signal (for example, a received ACK signal in which error information is set) is set. Error signal output means (for example, the payout control microcomputer 370) writes the data of the award ball preparation command in the transmission data register in step S551 after outputting the award ball preparation command) to the game control microcomputer. In step S549, the process of setting data including error information as the lower 4 bits of the command for preparing a prize ball is executed in step S549). It is characterized by that. According to such a configuration, an error signal (response signal (reception signal with error information added) (reception) is received by placing predetermined error information on a response signal periodically output by the dispensing control microcomputer based on the input of the request signal. ACK signal)) can be output, so that it is possible to prevent the occurrence of error signal dropping without considering the output timing of the error signal, and between the game control microcomputer and the payout control microcomputer. Communication can be performed reliably. Note that the predetermined bit and the specific bit may be either a part of the bit overlapping or a part of which the bit does not overlap at all.

  The game control microcomputer is a connection signal output means (for example, a game control microcomputer) that outputs a connection signal (for example, a connection confirmation signal) indicating a connection state of communication with the payout control microcomputer to the payout control microcomputer. In step S11 and S12 in 560, a portion for executing processing for setting a bit corresponding to an output port that outputs a connection confirmation signal in the output port buffer), and an output port for outputting a connection signal (for example, output port 0) And may be configured to include. According to such a configuration, since the communication connection state can be confirmed at any timing on the payout control microcomputer side, the prize ball is paid out when the communication connection state is abnormal. Can be reliably prevented.

  When the game control microcomputer outputs a request signal (for example, a prize ball number command as a prize ball request signal) by the number-of-payout output means, the number of prize game media specified by the request signal is stored. A payout number subtracting means for subtracting from the payout number data stored in the means (for example, the part for executing step S507 in the game control microcomputer 560) and a response signal output by the error signal output means (for example, error information is added) Even when the received reception ACK signal is input, the payout number re-output prohibiting means for prohibiting the re-output of the request signal subject to subtraction by the payout number subtracting means (for example, connection OK in step S504) Even if it is determined that the command contains error information, the process of outputting the award ball number command again is performed. Portions do not line: a structure without running s 508) when Y in step S504, or may be configured to include. According to such a configuration, it is possible to reliably prevent an illegal act that illegally pays out a prize ball.

  The game control microcomputer outputs a request signal, and thereafter, a response signal determination means for determining whether or not a response signal (for example, a connection OK command as a received ACK signal) is input within a predetermined period (for example, 1 s). For example, a communication error occurs when it is determined by the response signal determining means that the response signal is not input within a predetermined period (for example, Y in step S502) in the game control microcomputer 560 that executes step S502. As an occurrence, an abnormal request signal output means (for example, an abnormal request signal output means (for example, a connection confirmation command) is output to the payout control microcomputer every specific period (for example, 10 s) longer than a predetermined period (for example, 1 s) Step S513 when Y in step S513 in the game control microcomputer 560 A portion) to perform 11 may be configured to include. According to such a configuration, it is possible to recognize a communication error at an early stage, and to avoid frequent output of a request signal when the communication state is not normal, thereby reducing the processing load of the game control microcomputer. be able to.

  The game control microcomputer and the payout control microcomputer incorporate a serial communication circuit (for example, serial communication circuits 505 and 480) for serial communication with the other microcomputer, and the payout control microcomputer inputs a request signal. Based on the above, an input interrupt process (for example, command reception interrupt process) for inputting the request signal is executed, and a response signal is output within the input interrupt process (for example, command reception interrupt) In the main control communication process in the process, the reception ACK signal is transmitted based on the reception of the prize ball request signal (see steps S547, S550, and S551). According to such a configuration, the output of the response signal is delayed due to the processing delay of the payout control microcomputer, and the game control microcomputer (response signal determination means) determines that it is a communication error. Can be prevented.

  An effect control microcomputer (for example, sound / lamp control microcomputer 100b) for controlling a predetermined effect device (for example, speaker 27, lamp) is provided, and the game control microcomputer is output by the error signal output means. When a response signal is input, an informing error signal output means for outputting the input response signal as it is to the effect control microcomputer (for example, a part for executing steps S585, S587, and S588 in the game control microcomputer 560). The effect control microcomputer controls the effect device to notify that a predetermined error has occurred based on the input of the response signal (for example, the sound / lamp control microcomputer 100b). Step S790 in Or it may be configured to include a portion) to be executed. According to such a configuration, it is possible to notify that a predetermined error has occurred without increasing the processing load of the game control microcomputer.

It is the front view which looked at the pachinko game machine from the front. It is a front view which shows the front surface of the game board in the state which removed the glass door frame. It is the rear view which looked at the gaming machine from the back. It is a block diagram which shows the structural example of a game control board (main board). It is a block diagram which shows the circuit structural example of a payout control board. It is a block diagram which shows the circuit structural example of a relay board | substrate, a sound / lamp control board, and a symbol control board. FIG. 10 is a block diagram showing a circuit configuration of a main board and signal lines of an effect control command transmitted from the main board to the sound / lamp control board. It is a block diagram which shows the structural example of the transmission part of a serial communication circuit. It is a block diagram which shows the structural example of the receiving part of a serial communication circuit. It is explanatory drawing which shows the example of the data format of the data which serial communication transmits / receives with the microcomputer mounted in each control board. It is explanatory drawing which shows the example of a baud rate register. It is explanatory drawing which shows the example of the control register A and communication format setting data. It is explanatory drawing which shows the example of the control register B and interrupt request setting data. It is a figure which shows the example of status register A and status confirmation data. It is a figure which shows the example of status register B and status confirmation data. It is explanatory drawing which shows the example of the control register C and error interrupt request setting data. It is explanatory drawing which shows the example of the data register with which a serial communication circuit is provided. It is explanatory drawing which shows the example of the table memory for jackpot determination. It is explanatory drawing which shows the example of bit allocation of the output port in a game control means. It is explanatory drawing which shows the example of bit allocation of the output port in a game control means. It is explanatory drawing which shows the bit allocation example of the input port in a game control means. It is a flowchart which shows the main process which the microcomputer for game control performs. It is a flowchart which shows the main process which the microcomputer for game control performs. It is a flowchart which shows a 2 ms timer interruption process. It is a flowchart which shows a serial communication circuit setting process. It is explanatory drawing which shows an example of the content of the control signal output with respect to the payout control means from a game control means. It is explanatory drawing which shows an example of the content of the control command transmitted / received between a game control means and a payout control means. It is a block diagram which shows the signal line etc. which are used for transmission / reception of a control signal and a control command. It is a sequence diagram showing transmission and reception of signals between the game control microcomputer and the payout control microcomputer during normal operation. FIG. 6 is a sequence diagram showing signal transmission / reception between a game control microcomputer and a payout control microcomputer during a prize ball operation. FIG. 5 is a timing chart showing signal transmission and reception between a game control microcomputer and a payout control microcomputer during normal operation. FIG. 10 is a timing chart showing signal transmission / reception between a game control microcomputer and a payout control microcomputer when an error occurs during a winning ball. FIG. 5 is a timing chart showing signal transmission / reception between a game control microcomputer and a payout control microcomputer when a communication error occurs during connection confirmation. FIG. 5 is a timing chart showing signal transmission / reception between a game control microcomputer and a payout control microcomputer when a communication error occurs during award ball number notification. It is explanatory drawing which shows the example of a prize ball number table. It is a flowchart which shows a prize ball process. It is a flowchart which shows a prize ball process. It is a flowchart which shows an example of a special symbol process process. It is a flowchart which shows a starting port switch passage process. It is a flowchart which shows an example of a special symbol normal process. It is explanatory drawing which shows each 2 byte buffer formed in RAM used by switch processing. It is a flowchart which shows the process example of a switch process. It is a flowchart which shows an input port data confirmation process. It is explanatory drawing which shows the example of a prize ball command output counter processing table. It is a flowchart which shows an input determination process. It is explanatory drawing which shows the bit allocation example of the output port in a payout control means. It is explanatory drawing which shows the example of bit allocation of the input port in a payout control means. It is a flowchart which shows the main process which CPU for payout control performs. It is a flowchart which shows the timer interruption process which CPU for payout control performs. It is a flowchart which shows a main control communication process. It is a flowchart which shows a prize ball lending control process. It is a flowchart which shows the payout start waiting process. It is a flowchart which shows a payout motor stop waiting process. It is a flowchart which shows payout passage waiting processing. It is a flowchart which shows payout passage waiting processing. It is a flowchart which shows payout passage waiting processing. It is explanatory drawing which shows an example of the relationship between the kind of error, and the display of LED for an error display. It is a flowchart which shows an error process. It is a flowchart which shows an error process. It is a flowchart which shows the main process which the microcomputer for sound / lamp control performs. It is explanatory drawing which shows each random number used by a sound / lamp control process. It is a flowchart which shows production content determination processing. It is a flowchart which shows alerting | reporting control process processing. It is a flowchart which shows the main process which the microcomputer for symbol control performs. It is a flowchart which shows a symbol control process process. It is a block diagram which shows the other circuit structural example of a relay board | substrate, a sound / lamp control board, and a symbol control board.

Embodiment 1 FIG.
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
First, the overall configuration of a pachinko gaming machine that is an example of a gaming machine will be described. FIG. 1 is a front view of a pachinko gaming machine as viewed from the front, and FIG. In the following embodiments, a pachinko gaming machine will be described as an example. However, the gaming machine according to the present invention is not limited to a pachinko gaming machine, and can be applied to other gaming machines such as a slot machine.

  The pachinko gaming machine 1 includes an outer frame (not shown) formed in a vertically long rectangular shape, and a game frame attached to the inside of the outer frame so as to be opened and closed. Further, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape that is provided in the game frame so as to be opened and closed. The game frame includes a front frame (not shown) installed to be openable and closable with respect to the outer frame, a mechanism plate to which mechanism parts and the like are attached, and various parts attached to them (excluding a game board described later). Is a structure including

  As shown in FIG. 1, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2 is a hitting ball supply tray (upper plate) 3. Under the hitting ball supply tray 3, an extra ball receiving tray 4 for storing game balls that cannot be accommodated in the hit ball supply tray 3 and a hitting operation handle (operation knob) 5 for launching the game balls are provided. A game board 6 is detachably attached to the back surface of the glass door frame 2. The game board 6 is a structure including a plate-like body constituting the game board 6 and various components attached to the plate-like body. A game area 7 is formed on the front surface of the game board 6.

  Near the center of the game area 7, there is provided a variable display device (decorative symbol display device) 9 including a plurality of variable display portions each variably displaying an effect decorative symbol. The variable display device 9 has, for example, three variable display portions (symbol display areas) of “left”, “middle”, and “right”. The variable display device 9 performs variable display of a decorative symbol as a symbol for decoration (production) during the variable symbol display period of the special symbol by the special symbol indicator 8. The variable display device 9 that performs variable display of decorative symbols is controlled by a symbol control microcomputer mounted on the symbol control board.

  At the bottom of the variable display device 9, four special symbol hold memory indicators 18 for displaying the number of valid winning balls that have entered the start winning opening 14, that is, the number of hold memories (also referred to as start memory or start prize memory), are provided. ing. The special symbol reservation storage display 18 displays up to four reservation storage numbers in the order of winning. The special symbol hold storage display 18 increases the number of LEDs in the lit state by 1 each time there is a start winning in the start winning opening 14. Then, each time the special symbol display 8 starts variable display, the special symbol hold storage indicator 18 reduces the number of LEDs in the lit state by 1 (that is, turns off one LED). Specifically, the special symbol hold storage display 18 shifts the lighting state each time variable display is started on the special symbol display 8. In this example, the upper limit number (up to 4) is provided for the number of starting memories by winning to the start winning opening 14, but the upper limit number may be four or more.

  A special symbol display (special symbol display device) 8 that variably displays a special symbol as identification information is provided on the variable display device 9. In this embodiment, the special symbol display 8 is realized by a simple and small display (for example, 7 segment LED) capable of variably displaying numbers 0 to 9, for example. The special symbol display 8 may be configured to variably display a larger number of numbers such as 0 to 99 in order to make it difficult for the player to grasp a specific stop symbol. In addition, the variable display device 9 performs variable display of a decorative symbol as a symbol for decoration (for production) during the variable symbol display period of the special symbol by the special symbol indicator 8.

  Below the variable display device 9 is provided a variable winning ball device 15 that forms a start winning opening 14. The variable winning ball device 15 is configured to be able to open and close the wings, and when the wings are open, the game ball is likely to win a prize (open state), and when the wings are not open (closed). The game ball becomes difficult to win (closed state). The winning ball that has entered the start winning opening 14 is guided to the back of the game board 6 and detected by the start opening switch 14a. The variable winning ball device 15 is opened by a solenoid 16. The first winning prize opening may be provided directly above the variable winning ball apparatus 15, and the variable winning ball apparatus 15 may be used as the second starting prize opening.

  Below the variable winning ball apparatus 15, a special variable winning ball apparatus 20 using an opening / closing plate that is controlled to be opened by a solenoid 21 in a specific gaming state (big hit state) is provided. The special variable winning ball apparatus 20 is a means for opening and closing the big winning opening. Of the winning balls that are won in the special variable winning ball apparatus 20 and guided to the back of the game board 6, the winning ball that has entered one (V winning area: special area) is detected by the V winning switch 22 and then counted by the count switch 23. The game ball that has been detected and entered the other region is detected by the count switch 23 as it is. On the back of the game board 6, a solenoid 21A for switching the route in the special winning opening is also provided. In this embodiment, the condition that the game ball enters the V winning area in the special variable winning ball apparatus 20 and the game ball is detected by the V winning switch 22 is a condition for continuing the big hit round. A predetermined number of rounds may be automatically continued without providing the V winning area in the winning ball apparatus 20.

  When the game ball passes through the gate 32 and is detected by the gate switch 32a, variable display of the normal symbol display 10 is started. In this embodiment, variable display is performed by alternately lighting the left and right lamps (the symbols can be visually recognized when the lamp is lit). When the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined number of times. In the vicinity of the normal symbol display 10, a normal symbol start memory display 41 having a display unit with four LEDs for displaying the number of winning balls that have passed through the gate 32 is provided. Each time there is a game ball passing through the gate 32, the normal symbol start memory display 41 increases the number of LEDs to be turned on by one. Each time the variable display on the normal symbol display 10 is started, the number of LEDs to be lit is reduced by one.

  The game board 6 is provided with a plurality of winning holes 29, 30, 33, 39, and winning of game balls to the winning holes 29, 30, 33, 39 is performed by winning hole switches 29a, 30a, 33a, 39a, respectively. Detected. Each winning opening 29, 30, 33, 39 constitutes a winning area provided in the game board 6 as an area for accepting game media and allowing winning. The start winning opening 14 and the big winning opening also constitute a winning area that accepts game media and allows winning. In addition, instead of the configuration in which the game balls won in the winning ports 29, 30, 33, and 39 are detected by the winning switch, a configuration in which the detection switch detects that the game ball has passed a predetermined area (for example, a gate) may be adopted. Good. Around the left and right of the game area 7, there are provided decorative lamps 25 blinking and displayed during the game, and at the lower part there is an outlet 26 for absorbing a game ball that has not won a prize. Two speakers 27 that emit sound effects are provided on the left and right upper portions outside the game area 7. On the outer periphery of the game area 7, a top frame lamp 28a, a left frame lamp 28b, and a right frame lamp 28c are provided. Further, a decoration LED is installed around each structure (such as a big prize opening) in the game area 7. The top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, and the decoration LED are examples of a decorative light emitter provided in the gaming machine.

  In this example, a prize ball lamp 51 that is lit during award ball payout is provided in the vicinity of the left frame lamp 28b, and a ball break lamp 52 that is lit when the supply ball is cut in the vicinity of the top frame lamp 28a. Is provided. Further, a prepaid card unit (hereinafter referred to as “card unit”) 50 that enables lending a ball by inserting a prepaid card is installed adjacent to the pachinko gaming machine 1.

  The card unit 50 includes, for example, a usable display lamp that indicates whether or not the card unit 50 is in a usable state, a connection table direction indicator that indicates which side of the pachinko gaming machine 1 corresponds to the card unit, and a card unit. When checking the card insertion indicator lamp indicating that a card is inserted in the card, the card insertion slot into which the card as a recording medium is inserted, and the card reader / writer mechanism provided on the back of the card insertion slot A card unit lock for releasing the card unit is provided.

  A game ball launched from the ball striking device by the player's operation enters the game area 7 through the hit ball rail, and then descends the game area 7. When the game ball enters the start winning opening 14 and is detected by the start opening switch 14a, the special symbol on the special symbol display 8 starts variable display (variation) if the variable display of the symbol can be started. If the variable display of the symbol cannot be started, the number of reserved memories is increased by one.

  The variable display of the special symbol on the special symbol display device 8 stops when a certain time has elapsed. If the special symbol (stop symbol) at the time of stoppage is a jackpot symbol (specific display result), the game shifts to a jackpot gaming state. That is, the special variable winning ball apparatus 20 is released until a predetermined time elapses or a predetermined number (for example, 10) of gaming balls wins. When the game ball is won in the V winning area while the special variable winning ball apparatus 20 is opened and detected by the V winning switch 22, a continuation right is generated and the special variable winning ball apparatus 20 is opened again. The generation of the continuation right is allowed a predetermined number of times (for example, 15 rounds). Further, without providing the V winning area, the special variable winning ball apparatus 20 may be allowed to be released up to the last round of the determined number of rounds (for example, up to 15 rounds).

  When the special symbol on the special symbol display 8 at the time of stoppage is a jackpot symbol (probability variation symbol) with a probability variation, the probability of the next jackpot increases. That is, it becomes a more advantageous state for the player in the probability variation state.

  When the game ball passes through the gate 32, the normal symbol display unit 10 enters a state in which the normal symbol is variably displayed. Further, when the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined time.

  Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. FIG. 3 is a rear view of the gaming machine as seen from the back side.

  As shown in FIG. 3, on the back side of the gaming machine, a variable display control unit 49 including a symbol control board 80a on which a symbol control microcomputer for controlling the variable display device 9 is mounted, a game control microcomputer and the like are mounted. A game control board (main board) 31 is installed. In addition, a payout control board 37 on which a payout control microcomputer for performing ball payout control is mounted is installed. The variable display control unit controls lighting of the various decorative LEDs, the decorative lamp 25, the top frame lamp 28a, the left frame lamp 28b, and the right frame lamp 28c provided on the frame side together with the symbol control board 80a. A sound / lamp control board on which a sound / lamp control microcomputer for controlling sound generation from the sound is mounted.

  Further, a power supply substrate 910 and a touch sensor substrate 91 on which a power supply circuit for generating DC30V, DC21V, DC12V, and DC5V is mounted are provided. Although most of the power supply substrate 910 overlaps with the main substrate 31, there is an exposed portion that is exposed so as to be visible from the outside without overlapping the main substrate 31. This exposed portion is supplied with the main board 31 and each control board (sound / lamp control board, symbol control board 80a and payout control board 37) in the gaming machine 1 and each electrical component (electric power supplied to the gaming machine). A power switch is provided as a power supply permission means for executing or cutting off the power supply to the component operating by the operation. Furthermore, a replaceable fuse is provided inside the power switch in the exposed portion (inside the substrate). In this embodiment, the main board 31 is provided on the frame side, but may be provided on the board side. In that case, the communication between the main board 31 and the payout control board 37 as will be described later is performed by serial communication, thereby facilitating the routing of the wiring when replacing the panel.

  Each control board is equipped with control means including a control microcomputer. The control means is an electrical component (game device: ball payout device 97, variable display device 9, light emission from a lamp, LED, etc.) provided in the gaming machine according to a command signal (control signal) as a command from the game control means or the like. Body, speaker 27, etc.). Hereinafter, the main board 31 may be included in the control board for explanation. In that case, the control means mounted on the control board refers to each of the game control means and the means for controlling the electrical components provided in the gaming machine in accordance with a command signal from the game control means or the like. A substrate on which a microcomputer other than the main substrate 31 is mounted may be referred to as a sub-substrate. The ball payout device 97 is a device for paying out a game ball guided by a passage for guiding the game ball and a sprocket driven by a stepping motor or the like to an upper plate or a lower plate. A payout number counting switch for counting prize balls is also configured as a part of the unit.

  On the back side of the gaming machine, a terminal board 160 provided with terminals for outputting various information to the outside of the gaming machine is installed above. The terminal board 160 includes at least a ball break terminal for introducing the output of the ball break detection switch 167 and outputting it externally, a prize ball terminal for outputting prize ball information (prize ball number signal) and a ball. A ball lending terminal for externally outputting lending information (ball lending number signal) is provided. Further, an information terminal board (information output board) 36 having terminals for outputting various information from the main board 31 to the outside of the gaming machine is installed near the center.

  The game balls stored in the storage tank 38 pass through the guide rail 39 and reach the ball payout device covered with the payout case 40A via the curve rod. A ball break switch 187 as a game medium break detection means is provided on the upper part of the ball payout device. When the ball break switch 187 detects a ball break, the dispensing operation of the ball dispensing device stops. The ball break switch 187 is a switch for detecting the presence or absence of a game ball in the game ball passage, but the ball break detection switch 167 for detecting the shortage of supply balls in the storage tank 38 is also an upstream portion (storage tank 38). In the vicinity of the head). When the ball break detection switch 167 detects the shortage of game balls, the game machine is replenished to the game machine from the supply mechanism provided on the gaming machine installation island.

  When a large number of game balls as prizes based on winning a prize and game balls based on a ball lending request are paid out and the hitting ball supply tray 3 is full, the game balls are guided to the surplus ball receiving tray 4 through the surplus ball passage. When the game ball is further paid out, a sensing lever (not shown) presses a full tank switch (not shown) as a storage state detection means, and the full tank switch as a storage state detection means is turned on. In this state, the rotation of the payout motor in the ball payout device is stopped, the operation of the ball payout device is stopped, and the driving of the ball hitting device is also stopped.

  FIG. 4 is a block diagram showing an example of the circuit configuration of the main board (game control board) 31. FIG. 4 also shows a payout control board 37, a sound / lamp control board 80b, a symbol control board 80a, and the like. A game control microcomputer (corresponding to game control means) 560 for controlling the pachinko gaming machine 1 according to a program is mounted on the main board 31. The game control microcomputer 560 includes a ROM 54 for storing a game control (game progress control) program and the like, a RAM 55 as storage means used as a work memory, a CPU 56 for performing control operations in accordance with the program, and an I / O port unit 57. including. In this embodiment, the ROM 54 and the RAM 55 are built in the game control microcomputer 560. That is, the game control microcomputer 560 is a one-chip microcomputer. The one-chip microcomputer only needs to include at least the RAM 55, and the ROM 54 may be external or internal. The I / O port unit 57 may be externally attached.

  In the game control microcomputer 560, the CPU 56 executes control in accordance with the program stored in the ROM 54, so that the game control microcomputer 560 (or CPU 56) executes (or performs processing) hereinafter. Specifically, the CPU 56 executes control according to a program. The same applies to microcomputers mounted on substrates other than the main substrate 31.

  The game control microcomputer 560 includes a random number circuit 503. The random number circuit 503 is a hardware circuit that is used to generate a random number for determination to determine whether or not to win a jackpot based on a display result of variable symbol special display. The random number circuit 503 updates numerical data in accordance with a set update rule within a numerical range in which an initial value (for example, 0) and an upper limit value (for example, 65535) are set, and starts at a random timing Based on the fact that the winning time is the reading (extraction) of the numerical data, it has a random number generation function in which the numerical data to be read becomes a random value.

  The random number circuit 503 includes a numeric data update range selection setting function (initial value selection setting function and upper limit value selection setting function), numeric data update rule selection setting function, and numeric data update rule selection. It has various functions such as a switching function. With such a function, the randomness of the generated random numbers can be improved.

  Further, the game control microcomputer 560 has a function of setting an initial value of numerical data updated by the random number circuit 503. For example, a predetermined calculation is performed using the ID number of the game control microcomputer 560 stored in a predetermined storage area such as the ROM 54 (an ID number assigned with a different value for each product of the game control microcomputer 560). The numerical data obtained by the execution is set as the initial value of the numerical data updated by the random number circuit 503. By performing such processing, the randomness of the random number generated by the random number circuit 503 can be further improved.

  The game control microcomputer 560 reads numerical data from the random number circuit 503 as a random R when a start winning to the start port switch 14a occurs, and performs a specific display based on the random R at the start of the variation of the special symbol and the production symbol. It is determined whether or not to make a jackpot display result as a result, that is, whether or not to make a jackpot. Then, when it is determined to be a big hit, the gaming state is shifted to a big hit gaming state as a specific gaming state advantageous to the player.

  The game control microcomputer 560 inputs / outputs signals through serial communication with the payout control board 37 (the payout control microcomputer 370) and the sound / lamp control board 80b (the sound / lamp control microcomputer) ( A serial communication circuit 505 for transmission / reception) is incorporated. The payout control microcomputer 370 and the sound / lamp control microcomputer also incorporate a serial communication circuit for inputting / outputting signals through the game control microcomputer 560 through serial communication (the payout control microcomputer). (See FIG. 5 for the serial communication circuit built in 370). However, in this embodiment, a signal is output only from the game control microcomputer 560 to the sound / lamp control microcomputer, and a signal is output from the sound / lamp control microcomputer 560 to the game control microcomputer 560. Is not output, the sound / lamp control microcomputer has a built-in serial communication circuit for inputting a signal. Communication between the game control microcomputer 560 and the sound / lamp control microcomputer is not limited to serial communication, but may be parallel communication.

  The RAM 55 is a backup RAM as a non-volatile storage means, part or all of which is backed up by a backup power supply created on the power supply board. That is, even if the power supply to the gaming machine is stopped, a part or all of the contents of the RAM 55 is stored for a predetermined period (until the capacitor as the backup power supply is discharged and the backup power supply cannot be supplied). In particular, at least data corresponding to the game state, that is, the control state of the game control means (such as a special symbol process flag and the value of the pending storage number counter) and data indicating the number of unpaid prize balls are stored in the backup RAM. The data corresponding to the control state of the game control means is data necessary for restoring the control state before the occurrence of a power failure or the like based on the data when the power is restored after a power failure or the like occurs. Further, data corresponding to the control state and data indicating the number of unpaid prize balls are defined as data indicating the progress state of the game. In this embodiment, it is assumed that the entire RAM 55 is backed up.

  A reset signal from the power supply board is input to the reset terminal of the game control microcomputer 560. A reset circuit for generating a reset signal supplied to the game control microcomputer 560 and the like is mounted on the power supply board. When the reset signal becomes high level, the game control microcomputer 560 and the like are in an operable state, and when the reset signal becomes low level, the game control microcomputer 560 and the like are in an operation stop state. Therefore, an allowable signal that allows the operation of the game control microcomputer 560 or the like is output during a period when the reset signal is at a high level, and a game control microcomputer is output when the reset signal is at a low level. An operation stop signal for stopping the operation of 560 or the like is output. Note that the reset circuit may be mounted on each electric component control board (a board on which a microcomputer for controlling the electric parts is mounted).

  Further, a power-off signal indicating that the power supply voltage from the power supply board has dropped below a predetermined value is input to the input port of the game control microcomputer 560. That is, the power supply board monitors the voltage value of a predetermined voltage (for example, DC30V or DC5V) used in the gaming machine, and when the voltage value decreases to a predetermined value (the power supply voltage is reduced). A power supply monitoring circuit that outputs a power-off signal indicating that). A clear signal (not shown) indicating that the clear switch for instructing to clear the contents of the RAM is operated is input to the input port of the game control microcomputer 560.

  Further, an input driver circuit 58 for supplying the basic circuit 53 with detection signals from the gate switch 32a, the start port switch 14a, the count switch 23, the V winning switch 22 and the winning port switches 29a, 30a, 33a and 39a is also provided on the main board 31. An output circuit 59 that drives the solenoid 16 that opens and closes the variable winning ball device 15, the solenoid 21 that opens and closes the special variable winning ball device, and the solenoid 21 A for switching the path in the special winning opening according to a command from the basic circuit 53. Is also mounted on the main board 31, and a system reset circuit (not shown) for resetting the game control microcomputer 560 when the power is turned on, and an information output signal such as jackpot information indicating the occurrence of a jackpot gaming state are output to a hall computer, etc. Information output circuit (not shown) ) It has also been installed in the main board 31.

  In this embodiment, the sound / lamp control means (configured by a sound / lamp control microcomputer) mounted on the sound / lamp control board 80 b is connected to the game control microcomputer 560 via the relay board 77. The effect control command from is received and transferred to the symbol control board 80a. Then, the symbol control means (comprising a symbol control microcomputer) mounted on the symbol control board 80a receives the effect control command from the sound / lamp control means, and variably displays the decorative symbol. 9 display control is performed.

  FIG. 5 is a block diagram showing components related to payout, such as the payout control board 37 and the ball payout device 97. As shown in FIG. 5, a payout control microcomputer 370 including a payout control CPU 371 is mounted on the payout control board 37. In this embodiment, the payout control microcomputer 370 is a one-chip microcomputer and incorporates at least a RAM. The payout control microcomputer 370, the RAM (not shown), the ROM (not shown) storing the payout control program, the I / O port, and the like constitute the payout control means. That is, the payout control means is realized by a payout control CPU 371, a payout control microcomputer 370 having a RAM and a ROM, and an I / O port. The I / O port may be built in the payout control microcomputer 370.

  Detection signals from the ball break switch 187, the full switch 48, and the payout count switch 301 are input to the I / O port 372 f of the payout control board 37 via the relay board 72. In this embodiment, the detection signal from the payout number count switch 301 is input to the payout control microcomputer 370 and then output to the main board 31 via the I / O port 372a and the output circuit 373B. .

  A detection signal from the payout motor position sensor 295 is input to the I / O port 372e of the payout control board 37 via the relay board 72. The payout motor position sensor 295 is a sensor composed of a light emitting element (LED) and a light receiving element for detecting the rotational position of the payout motor 289, and is used for detecting that the game ball is clogged, that is, so-called ball biting. . In the payout control microcomputer 370 mounted on the payout control board 37, the detection signal from the ball break switch 187 indicates that the ball is out of ball, or the detection signal from the full tank switch 48 indicates that the ball is full. Then, the ball payout process is stopped.

  Further, when the detection signal from the full tank switch 48 indicates a full state, the payout control microcomputer 370 has a low level with respect to the launch board 90 in order to stop the ball launch from the hitting ball launcher. A full tank signal is output. A launch motor signal output from the AND circuit 91 of the launch board 90 to the launch motor 94 is transmitted from the launch board 90 to the launch motor 94. A full tank signal from the payout control microcomputer 370 is input to one of the input sides of the AND circuit 91 mounted on the launch board 90, and a drive signal from the drive signal generation circuit 92 (for driving the launch motor 94). Is a signal that serves to supply power from the power supply board.) Is input to the other input side of the AND circuit 91. Then, the firing motor signal of the AND circuit 91 is input to the firing motor 94. That is, while the payout control microcomputer 370 is outputting the full tank signal, the output of the firing motor signal to the firing motor 94 is stopped.

  The payout control microcomputer 370 incorporates a serial communication circuit 380 for inputting / outputting (transmitting / receiving) signals with the game control microcomputer 560 through serial communication. In this embodiment, the game control microcomputer 560 and the payout control microcomputer 370 are connected between the game control microcomputer 560 and the payout control microcomputer 370 via serial communication circuits 505 and 380. In order to perform confirmation, signals (prize ball request signal and reception ACK signal) are exchanged (transmitted / received) at regular intervals (for example, 1 second). That is, the game control microcomputer 560 transmits a signal (a prize ball request signal in this embodiment) for confirming the connection at regular intervals via the serial communication circuit 505, and the payout control microcomputer 370. When a prize ball request signal is received from the game control microcomputer 560, a signal (reception ACK signal) to that effect is transmitted to the game control microcomputer 560. In this embodiment, the game control microcomputer 560 and the payout control microcomputer 370 are placed at the timing of transmitting and receiving the prize ball request signal and the reception ACK signal by putting specific data on the prize ball request signal and the reception ACK signal. Specific data is exchanged between them. For example, when a winning occurs, the game control microcomputer 560 sets data indicating the number of prize balls to be paid out by changing predetermined bits of the prize ball request signal, and the prize for which the setting has been made. The ball request signal is transmitted to the payout control microcomputer 370. When the award ball payout operation ends, the payout control microcomputer 370 sets data indicating the end of the award ball by changing a predetermined bit of the received ACK signal, and plays the received ACK signal for which the setting has been made. It transmits to the control microcomputer 560. In addition, when a predetermined error (an error such as ball lending, full tank, or out of ball) occurs, data indicating the content of the error is set by changing a predetermined bit of the received ACK signal, and the setting is The received reception ACK signal is transmitted to the game control microcomputer 560. Note that specific signal exchange by serial communication between the game control microcomputer 560 and the payout control microcomputer 370 will be described in detail with reference to FIGS.

  The payout control microcomputer 370 receives, via the output port 372b, a prize ball information signal indicating the number of prize balls to be paid and a ball lending number signal indicating the number of balls to be rented to a terminal board (frame external terminal board and board external terminal board). Output to 160). A driver circuit is provided outside the output port 372b, but is not shown in FIG.

  Also, the payout control microcomputer 370 outputs an error signal to the error display LED 374 using a 7-segment LED via the output port 372c. Further, a signal for instructing turning on / off is output to the winning ball LED 51 and the ball running out LED 52 via the output port 372b. A detection signal from an error release switch 375 for releasing the error state is input to the input port 372f of the payout control board 37. The error cancel switch 375 is used to cancel the error state by software reset.

  Further, a drive signal from the payout control microcomputer 370 to the payout motor 289 is transmitted to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the output port 372a and the relay board 72. Although a driver circuit (motor drive circuit) is installed outside the output port 372a, the description is omitted in FIG.

  A card unit control microcomputer is mounted on the card unit 50 installed adjacent to the gaming machine. In addition, the card unit 50 is provided with a usable display lamp, a connecting table direction indicator, a card insertion display lamp, and a card insertion slot. A frequency display LED 60, a ball lending LED 61, a ball lending switch 62, and a return switch 63 provided in the vicinity of the hitting ball supply tray 3 are connected to the interface board (relay board) 66.

  A card lending switch signal indicating that the ball lending switch 62 has been operated and a return switch signal indicating that the return switch 63 has been operated are provided to the card unit 50 from the interface board 66 in accordance with the player's operation. . Further, a card balance display signal indicating a prepaid card balance and a ball lending display signal are given from the card unit 50 to the interface board 66. Between the card unit 50 and the payout control board 37, a connection signal (VL signal), a unit operation signal (BRDY signal), a ball lending request signal (BRQ signal), a ball lending completion signal (EXS signal) and a pachinko machine operation signal ( PRDY signal) is transmitted / received via the input port 372f and the output port 372d. An interface board 66 is interposed between the card unit 50 and the payout control board 37. Therefore, a signal such as a connection signal (VL signal) is transmitted and received between the card unit 50 and the payout control board 37 via the interface board 66 as shown in FIG.

  When the power of the pachinko gaming machine 1 is turned on, the payout control microcomputer 370 mounted on the payout control board 37 outputs a PRDY signal to the card unit 50. The card unit control microcomputer outputs a VL signal when the power is turned on. The payout control microcomputer 370 determines the connected / unconnected state of the card unit 50 according to the input state of the VL signal. When a card is received in the card unit 50, the ball lending switch is operated and a ball lending switch signal is input, the card unit control microcomputer outputs a BRDY signal to the payout control board 37. When a predetermined delay time elapses from this point, the card unit control microcomputer outputs a BRQ signal to the payout control board 37.

  Then, the payout control microcomputer 370 raises the EXS signal to the card unit 50 and, when detecting the fall of the BRQ signal from the card unit 50, drives the payout motor 289 to give a predetermined number of rental balls to the player. Pay out. When the payout is completed, the payout control microcomputer 370 causes the EXS signal to the card unit 50 to fall. Thereafter, on the condition that the BRDY signal from the card unit 50 is not in the ON state, the winning ball payout control is executed when a payout command signal is received from the game control means.

  The power supply voltage AC24V used in the card unit 50 is supplied from the payout control board 37. That is, power supply from the power supply board 910 to the card unit 50 is performed via the payout control board 37 and the interface board 66. In this example, a fuse for protecting the card unit 50 is provided in a 24 V AC power supply line for the card unit 50 arranged in the interface board 66, and a voltage higher than a predetermined voltage is supplied to the card unit 50. It is prevented.

  In this embodiment, the case where the card unit 50 is installed adjacent to the gaming machine as a separate body from the gaming machine is taken as an example, but the card unit 50 may be integrated with the gaming machine. . Further, the present invention can be applied even in the case where game balls corresponding to the amount of money are lent out in accordance with coin insertion.

  FIG. 6 is a block diagram showing a circuit configuration example of the relay board 77, the sound / lamp control board 80b, and the symbol control board 80a. In this embodiment, the sound / lamp control board 80b performs sound output control of the sound output device 27 and display control of each lamp 25, 28a, 28b, 28c. The symbol control board 80a performs display control of the variable display device 9. In this embodiment, “effect control” means display control of the variable display device 9, sound output control of the speaker 27, and display control of the lamps 25, 28a, 28b, and 28c. It means performing such as. Further, the effect control means is a sound / lamp control for performing the display control of the variable display device 9, the sound output control of the speaker 27, and the display control of the lamps 25, 28a, 28b, 28c. This is realized by the microcomputer 100b. In this embodiment, the sound / lamp control microcomputer 100b and / or the symbol control microcomputer 100a may be referred to as production control means. Also, only the effect control board may be provided for effect control without providing the sound / lamp control board 80b and the symbol control board 80a. Moreover, one microcomputer may be mounted on the effect control board, and control related to the effect may be performed by the microcomputer.

  The sound / lamp control board 80b is mounted with a sound / lamp control microcomputer 100b including a sound / lamp control CPU 101b and a RAM. The RAM may be externally attached. In the sound / lamp control board 80b, the sound / lamp control CPU 101b operates in accordance with a program stored in a built-in or external ROM (not shown). The sound / lamp control microcomputer 100b includes a serial communication circuit 101c that inputs / outputs (transmits / receives) signals with the game control microcomputer 560 through serial communication.

  The signal input from the main board 31 (the serial communication circuit 505 of the game control microcomputer 560) is passed through the relay board 77 only in the direction toward the sound / lamp control board 80b (from the sound / lamp control board 80b). A unidirectional circuit 74 is mounted as a signal direction restricting means (a signal is not allowed to pass in the direction toward the relay board 77). For example, a diode or a transistor is used as the unidirectional circuit. FIG. 6 illustrates a diode.

  Further, the sound / lamp control CPU 101 b outputs a signal for driving the lamp to the lamp driver 352. The lamp driver 352 amplifies a signal for driving the lamp and supplies the amplified signal to each lamp provided on the frame side such as the top frame lamp 28a, the left frame lamp 28b, and the right frame lamp 28c. Further, it is supplied to a decorative lamp 25 provided on the frame side.

  Further, the sound / lamp control CPU 101b outputs sound number data to the speech synthesis IC 173. The voice synthesizing IC 173 generates a voice or a sound effect corresponding to the sound number data and outputs it to the amplifier circuit 175. The amplifier circuit 175 outputs an audio signal obtained by amplifying the output level of the speech synthesis IC 173 to a level corresponding to the volume set by the volume 176 to the speaker 27. The voice data ROM 174 stores control data corresponding to the sound number data. The control data corresponding to the sound number data is a collection of data indicating the sound effect or sound output mode in a time series in a predetermined period (for example, a decorative symbol variation period).

  The signal for driving the lamp and the sound number data are communicated between the sound / lamp control CPU 101b, the lamp driver 352, and the speech synthesis IC 173 (a response signal is transmitted from the signal receiving side to the transmitting side). Communication).

  Further, the sound / lamp control microcomputer 100b determines the contents of the effect to be performed using the variable display device 9 based on the effect control command (for example, the variation pattern command). For example, the sound / lamp control microcomputer 100b uses the variable display device 9 to determine whether to perform a notice effect. Further, for example, the sound / lamp control microcomputer 100 b determines the type of the notice effect to be performed using the variable display device 9.

  The “notice effect” is an effect for informing the player in advance (before the decorative symbol stop symbol is derived and displayed on the variable display device 9) that it is a big hit or is likely to be a big hit. Say. For example, the player is informed that there is a possibility of a big hit by changing a different mode (speed, direction of rotation, etc.) or making a character appear during the change.

  In addition, the sound / lamp control microcomputer 100 b transfers (transmits) an effect control command (for example, a display result designation command) from the main board 31 to the symbol control board 80 a via the input / output port 104. Further, the sound / lamp control microcomputer 100b generates an effect content designation command indicating the determined effect content (whether or not to perform the notice effect and the type of the notice effect). In addition, the sound / lamp control microcomputer 100 b transmits the generated effect content designation command to the symbol control board 80 a via the input / output port 104.

  Note that the sound / lamp control microcomputer 100b adds the determined contents (whether or not to perform the notice effect and the type of the notice effect) to the effect control command (variation pattern command or display result designation command). Also good. Then, the sound / lamp control microcomputer 100 b may transmit an effect control command to which the effect content is added to the symbol control board 80 a via the input / output port 104.

  The symbol control board 80a is equipped with a symbol control microcomputer 100a including a symbol control CPU 101a and RAM. The RAM may be externally attached. In the symbol control board 80a, the symbol control CPU 101a operates according to a program stored in a built-in or external ROM (not shown). Further, the symbol control CPU 101a causes the VDP (video display processor) 109 to perform display control of the variable display device 9 using the LCD, based on the effect control command received from the sound / lamp control board 80b.

  The symbol control CPU 101a reads necessary data from a character ROM (not shown) in accordance with the received effect control command. The character ROM is used for storing in advance image data of an image displayed on the variable display device 9, specifically, a person, a character, a figure, a symbol, or the like (including decorative designs). The symbol control CPU 101a outputs the data read from the character ROM to the VDP 109. The VDP 109 executes display control based on data input from the symbol control CPU 101a.

  In this embodiment, the VDP 109 that performs display control of the variable display device 9 is mounted on the symbol control board 80a. The VDP 109 has an address space independent of the symbol control microcomputer 100a, and maps a VRAM therein. The VRAM is a buffer memory for expanding image data generated by the VDP. Then, the VDP 109 outputs the image data in the VRAM to the variable display device 9. Note that a number of VDPs corresponding to the number of variable display devices may be mounted on the symbol control board 80a.

  FIG. 7 is a block diagram showing a circuit configuration of the main board 31 and signal lines of an effect control command transmitted from the main board 31 to the sound / lamp control board 80b. As shown in FIG. 7, in this embodiment, the game control microcomputer 560 mounted on the main board 31 uses a single signal line for transmission of an effect control signal to produce an effect control command (effect control signal). Is transmitted to the sound / lamp control board 80b.

  As shown in FIG. 7, the main board 31 is connected to the wiring from the start port switch 14a. The main board 31 is also provided with wiring from the special variable winning ball apparatus 20 which is a big winning opening, and various switches 29a, 30a, 33a, 39a for detecting the winning of game balls to other winning openings. It is connected. Further, the main board 31 is connected to a solenoid 16 for opening and closing the variable winning ball apparatus 15, a solenoid 21 for opening and closing the special variable winning ball apparatus 20, and a wiring to the solenoid 21A for switching the path in the special winning opening. .

  The main board 31 includes a game control microcomputer 560, an input driver circuit 58, and an output circuit 59. The game control microcomputer 560 operates in accordance with a clock circuit 501, a reset controller 502 that functions as a system reset means, a random number circuit 503a, 503b, a ROM 54 that stores a game control program, a RAM 55 that is used as a work memory, and a program. CPU 56, CTC 504 for sending an interrupt request signal (interrupt request signal by timer interrupt) to CPU 56, serial communication circuit 505 for performing asynchronous serial communication with the microcomputer provided in payout control board 37 and sound / lamp control board 80b, and An I / O port unit 57 is incorporated.

  In this embodiment, the microcomputer on a board (for example, the payout control board 37 or the sound / lamp control board 80b) different from the board (for example, the main board 31) on which the microcomputer incorporating the serial communication circuit 505 is mounted. Although the case where the serial communication circuit 505 is used for communication with the serial communication circuit 505 will be described, the serial communication circuit 505 may perform serial communication with another microcomputer included in the board on which the microcomputer incorporating the serial communication circuit 505 is mounted. For example, when two microcomputers having the same configuration are mounted on the same substrate, serial communication circuits built in the microcomputers may perform serial communication with each other.

The clock circuit 501 outputs a reference clock signal CLK having a predetermined period generated by dividing the system clock signal by 2 ⁷ (= 128) to the random number circuits 503a and 503b. When a low level signal is input for a predetermined period, the reset controller 502 outputs a predetermined initialization signal to the CPU 56 and the random number circuits 503a and 503b to reset the game control microcomputer 560.

  Further, in this embodiment, as shown in FIG. 7, the game control microcomputer 560 is equipped with two random number circuits 503a and 503b having different ranges of random value values that can be generated. The random number circuit 503a is a random number circuit (hereinafter also referred to as a 12-bit random number circuit) that generates a 12-bit pseudo-random number. The 12-bit random number circuit 503a has a function of generating a random number having a value within a range that can be generated by 12 bits (that is, a range from 0 to 4095). The random number circuit 503b is a random number circuit (hereinafter also referred to as a 16-bit random number circuit) that generates a 16-bit pseudo-random number. The 16-bit random number circuit 503b has a function of generating a random number having a value in a range that can be generated in 16 bits (that is, a range from 0 to 65535). In this embodiment, the case where the game control microcomputer 560 includes two random number circuits is described. However, the game control microcomputer 560 may include three or more random number circuits. In this embodiment, when the 12-bit random number circuit 503a and the 16-bit random number circuit 503b are comprehensively expressed, or when indicating either the 12-bit random number circuit 503a or the 16-bit random number circuit 503b, This is called a random number circuit 503.

  Next, the configuration of the serial communication circuit 505 will be described. The serial communication circuit 505 is a data format using a full-duplex method, an asynchronous method, and standard NRZ (non-return zero) encoding, and is a micro of each control board (for example, the payout control board 37 and the sound / lamp control board 80b). Serial communication with the computer. The serial communication circuit 505 includes a transmission unit that transmits various data (for example, a prize ball number command and an effect control command) to the microcomputer of each control board, and various data (for example, a prize ball ACK) from the microcomputer of each control board. Command).

  FIG. 8 is a block diagram illustrating a configuration example of the transmission unit of the serial communication circuit 505. FIG. 9 is a block diagram illustrating a configuration example of the receiving unit of the serial communication circuit 505. The serial communication circuit 505 includes a baud rate register 702, a baud rate generation circuit 703, two status registers 705 and 706, three control registers 707, 708, and 709, a transmission data register 710, a reception data register 711, a transmission shift register 712, and a reception. Shift register 713, interrupt control circuit 714, transmission format / parity generation circuit 715, and reception format / parity check circuit 716. As shown in FIG. 8, the transmission unit of the serial communication circuit 505 includes a baud rate register 702, a baud rate generation circuit 703, a status register A 705, control registers 707, 708, and 709, and a transmission data register 710. , A transmission shift register 712, an interrupt control circuit 714, and a transmission format / parity generation circuit 715. As shown in FIG. 9, the receiving unit of the serial communication circuit 505 includes a baud rate register 702, a baud rate generation circuit 703, status registers 705 and 706, control registers 707, 708, and 709, received data, among these components. The register 711, the reception shift register 713, the interrupt control circuit 714, and the reception format / parity check circuit 716 are configured.

  In the serial communication circuit 505, the transmission unit and the reception unit are actually configured using a common circuit. As described above, the serial communication circuit 505 functions as a transmission circuit or a reception circuit by properly using each component of the serial communication circuit 505.

  First, the data format of data transmitted and received by the serial communication circuit 505 with the microcomputer mounted on each control board will be described. FIG. 10 is an explanatory diagram showing an example of a data format of data transmitted and received by the serial communication 505 to and from the microcomputer mounted on each control board. As shown in FIG. 10, the data format of data transmitted and received by the serial communication circuit 505 is configured with a start bit, data, and stop bits as one frame. Further, the data length of data transmitted / received by the serial communication circuit 505 can be set to either 8 bits or 9 bits by performing an initial setting in a serial communication circuit setting process described later. FIG. 10A shows an example of a data format when the data length is set to 8 bits. FIG. 10B shows an example of the data format when the data length is set to 9 bits.

  As shown in FIG. 10, the data format of data transmitted and received by the serial communication circuit 505 is a start bit (logic “0”) indicating the start of one frame after an idle line of high level (logic “1”). ")including. The data format includes 8-bit or 9-bit transmission / reception data after the start bit. The data format includes a stop bit (logic “1”) indicating the end of one frame after transmission / reception data.

  The serial communication circuit 505 transmits / receives data first from the least significant bit (bit 0) of transmission / reception data according to the data format shown in FIG. Further, if initial setting is performed in a serial communication circuit setting process described later, it is possible to set so that a parity bit is added to transmission / reception data. When a setting is made to add a parity bit, the most significant bit of the transmission / reception data is used as a parity bit (odd parity or even parity). For example, when the data length is set to 8 bits, bit 7 of transmission / reception data is used as a parity bit. For example, when the data length is set to 9 bits, bit 8 of transmission / reception data is used as a parity bit.

  The baud rate generation circuit 703 generates a baud rate used by the serial communication circuit 505 based on a clock signal output from the clock circuit 501 and a setting value (also referred to as a baud rate setting value) set in the baud rate register 702. In this case, the baud rate generation circuit 703 obtains the baud rate using a predetermined calculation formula based on the clock signal and the baud rate setting value. For example, the baud rate generation circuit 703 obtains the baud rate used by the serial communication circuit 505 using equation (1).

Baud rate = clock frequency / (baud rate set value x 16) Equation (1)

  FIG. 11 is an explanatory diagram showing an example of the baud rate register 702. The baud rate register 702 is a register that sets a predetermined setting value for designating a baud rate value generated by the baud rate generation circuit 703. For example, it is assumed that the baud rate register 702 obtains the baud rate using the equation (1) and the clock frequency is 3 MHz. In this case, if the desired target baud rate is 1200 bps, the setting value “156” is set in the baud rate register 702. Then, the baud rate generation circuit 703 generates the baud rate “1201.92 bps” using the equation (1) based on the clock frequency “3 MHz” and the baud rate set value “156”. The baud rate register 702 is a 16-bit register, and an initial value is set to “0 (= 00h)”. The baud rate register 702 is configured such that bits 0 to 12 can be written and read. Further, the baud rate register 702 is configured such that bits 13 to 15 cannot be written or read. Therefore, even if a control for writing a value to bits 13 to 15 of the baud rate register 702 is performed, it is invalid, and all the values read from the bits 13 to 15 are “0 (= 000b)”.

  FIG. 12A is an explanatory diagram illustrating an example of the control register A707. The control register A 707 is a register for setting the communication format of the serial communication circuit 505. In this embodiment, the communication format of the serial communication circuit 505 is set by setting the value of each bit of the control register A707. In the control register A707, communication format setting data for setting a communication format such as a data format of transmission / reception data and various communication methods is set. As shown in FIG. 12A, the control register A707 is an 8-bit register, and the initial value is set to “0 (= 00h)”. Control register A 707 is configured such that bits 0 to 4 can be written and read. Control register A 707 is configured such that bits 5 to 7 cannot be written or read. Therefore, even if a control for writing a value to bits 5 to 7 of the control register A707 is performed, it is invalid, and all values read from bits 5 to 7 are “0 (= 000b)”.

  FIG. 12B is an explanatory diagram of an example of communication format setting data set in the control register A707. As shown in FIG. 12B, setting data for setting the data length of data to be transmitted and received is set in bit 4 (bit name “M”) of the control register A707. As shown in FIG. 12B, by setting bit 4 to “0”, the data length of the transmission / reception data is set to 8 bits. Further, by setting bit 4 to “1”, the data length of the transmission / reception data is set to 9 bits.

  In bit 3 (bit name “WAKE”) of control register A707, setting data for setting a wake-up method for waking up a receiver circuit in the standby state (reception unit of serial communication circuit 505). Is set. As shown in FIG. 12B, by setting bit 3 to “0”, an idle line wakeup method is set for wakeup when an idle line is recognized. In addition, by setting bit 3 to “1”, an address mark wakeup method for wakeup by recognizing a predetermined address mark is set.

  In bit 2 (bit name “ILT”) of the control register A707, setting data for selecting an idle line detection method of received data is set. As shown in FIG. 12B, by setting bit 2 to “0”, a detection method for detecting an idle line after the start bit included in the received data is set. In addition, by setting bit 2 to “1”, a detection method for detecting an idle line after a stop bit included in received data is set.

  Setting data for setting whether to use the parity function is set in bit 1 (bit name “PE”) of the control register A707. As shown in FIG. 12B, by setting bit 1 to “0”, the parity function is set not to be used. Further, by setting bit 1 to “1”, the parity function is set to be used.

  Setting data for setting the type of parity when the parity function is used is set in bit 0 (bit name “PT”) of the control register A707. As shown in FIG. 12B, by setting bit 0 to “0”, even parity is set as the parity type. Also, by setting bit 0 to “1”, odd parity is set as the parity type.

  FIG. 13A is an explanatory diagram illustrating an example of the control register B708. The control register B 708 is a register for setting whether to permit an interrupt request from the serial communication circuit 505. In this embodiment, whether the interrupt request from the serial communication circuit 505 is permitted or prohibited is set by setting the value of each bit of the control register B708. In the control register B708, interrupt request setting data indicating whether or not various interrupt requests are permitted is mainly set. In addition to the interrupt request setting data, setting data for performing various settings of the serial communication circuit 505 is also set in the control register B708. As shown in FIG. 13A, the control register B 708 is an 8-bit register, and the initial value is set to “0 (= 00h)”. Control register B 708 is configured such that bits 0 to 7 can be written and read.

  FIG. 13B is an explanatory diagram showing an example of interrupt request setting data set in the control register B708. As shown in FIG. 13B, setting data indicating whether or not a transmission interrupt request, which is an interrupt request to be performed at the time of data transmission, is permitted is set in bit 7 (bit name “TIE”) of the control register B708. Is done. As shown in FIG. 13B, by setting bit 7 to “0”, the transmission interrupt request is set to be prohibited. Also, by setting bit 7 to “1”, the transmission interrupt request is set to be permitted.

  Bit 6 (bit name “TCIE”) of the control register B708 is set with setting data indicating whether or not to permit a transmission completion interrupt request, which is an interrupt request to be made when data transmission is completed. As shown in FIG. 13B, by setting bit 6 to “0”, the transmission completion interrupt request is set to be prohibited. Also, by setting bit 6 to “1”, the transmission completion interrupt request is set to be permitted.

  Bit 5 (bit name “RIE”) of the control register B 708 is set with setting data indicating whether or not a reception interrupt request, which is an interrupt request when data is received, is permitted. As shown in FIG. 13B, by setting bit 5 to “0”, the reception interrupt request is set to be prohibited. Further, by setting bit 5 to “1”, the reception interrupt request is set to be permitted.

  Bit 4 (bit name “ILIE”) of the control register B 708 is set with setting data indicating whether or not to allow an idle line interrupt request, which is an interrupt request when an idle line of received data is detected. As shown in FIG. 13B, by setting bit 4 to “0”, an idle line interrupt request is set to be prohibited. Further, by setting bit 4 to “1”, it is set to permit an idle line interrupt request.

  In bit 3 (bit name “TE”) of the control register B708, setting data indicating whether to use the transmission circuit (the transmission unit of the serial communication circuit 505) is set. As shown in FIG. 13B, by setting bit 3 to “0”, the transmission circuit is set not to be used. Further, by setting bit 3 to “1”, the transmission circuit is set to be used. In this embodiment, setting to use the transmission circuit is performed by setting bit 3 to “1”. Such setting is performed in the initial setting of the main process (for example, step S15a).

  In bit 2 (bit name “RE”) of the control register B708, setting data indicating whether or not to use the receiving circuit is set. As shown in FIG. 13B, by setting bit 2 to “0”, the receiving circuit is set not to be used. Further, by setting bit 2 to “1”, the receiving circuit is set to be used. In this embodiment, setting to use the receiving circuit is performed by setting bit 2 to “1”. Such setting is performed in the initial setting of the main process (for example, step S15a).

  Setting data indicating whether or not to use the wakeup function of the receiving circuit is set in bit 1 (bit name “RWU”) of the control register B708. As shown in FIG. 13B, by setting bit 1 to “0”, the wakeup function is set not to be used. Further, by setting bit 1 to “1”, the wakeup function is set to be used.

  Setting data indicating whether or not to use a predetermined break code transmission function is set in bit 0 (bit name “SBK”) of the control register B708. As shown in FIG. 13B, by setting bit 1 to “0”, the break code transmission function is set not to be used. Further, by setting bit 1 to “1”, the break code transmission function is set to be used. When bit 1 is set to “1”, the serial communication circuit 505 mounts a break code (for example, a signal continuously including “0”) on the control board (the payout control board 37 or the sound / lamp control board 80b). Send to microcomputer.

  FIG. 14A is an explanatory diagram illustrating an example of the status register A705. The status register A 705 is a register for confirming various statuses of the serial communication circuit 505. In this embodiment, the CPU 56 can confirm various statuses of the serial communication circuit 505 by confirming the value of each bit of the status register A 705. As shown in FIG. 14A, the status register A705 is an 8-bit register, and the initial value is set to “0 (= 00h)”. In addition, the status register A705 is configured so that bits 0 to 7 can only be read. Therefore, even if control is performed to write a value to bit 0 to bit 7 of the status register A705, it is invalidated.

  In the present embodiment, as will be described later, when transmission data is not stored in the transmission data register 710 (transmission data empty) or transmission of transmission data stored in the transmission shift register 712 is completed, interrupt control is performed. Circuit 714 sets the corresponding bit in status register A705. Then, the CPU 56 reads the value of each bit set in the status register A705.

  FIG. 14B is a diagram illustrating an example of status confirmation data stored in the status register A705. As shown in FIG. 14B, transmission data indicating that transmission data is not stored in transmission data register 710 (transmission data empty) in bit 7 (bit name “TDRE”) of status register A 705. Stores an empty flag. As shown in FIG. 14B, when “0” is stored in bit 7, the transmission data is not yet transferred from the transmission data register 710 to the transmission shift register 712, and transmitted to the transmission data register 710. Indicates that the data is still stored. In addition, when “0” is stored in bit 7, data is not written to the transmission data register. For example, in steps S508 and S511, transmission data is set on condition that “0” is not stored in bit 7. When “1” is stored in bit 7, the transmission data is transferred from the transmission data register 710 to the transmission shift register 712, and there is no transmission data in the transmission data register 710 (transmission data empty). ).

  Bit 6 (bit name “TC”) of the status register A 705 stores a transmission completion flag indicating that transmission of transmission data from the serial communication circuit 505 has been completed. As shown in FIG. 14B, when “0” is stored in bit 6, the transmission data stored in the transmission shift register 712 is being transmitted, and the transmission data from the serial communication circuit 505 is not transmitted. Indicates that transmission has not been completed. Further, when “1” is stored in bit 6, the transmission data stored in the transmission shift register 712 has been transferred, and transmission of transmission data from the serial communication circuit 505 has been completed. It shows that. When the command storage area is in the ring buffer format, when “1” is stored in bit 6, the command read pointer is updated.

  Note that the transmission of the transmission data is completed, and the game control microcomputer 560 waits for a reception confirmation signal from the transmission destination microcomputer. In this embodiment, when a transmission interrupt is set as will be described later, the serial communication circuit 505 sets the bit 6 of the status register A 705 to “1” and confirms reception when detecting the completion of transmission of transmission data. An interrupt request (referred to as an interrupt request during transmission) is made to the CPU 56 as a signal waiting state.

  Bit 5 (bit name “RDRF”) of status register A 705 stores a reception data full flag indicating that reception data is stored in reception data register 711 (reception data full). As shown in FIG. 14B, when “0” is stored in bit 5, it indicates that the reception data register 711 contains no reception data. When “1” is stored in bit 5, the value of the reception shift register 713 is transferred to the reception data register 711, and reception data is stored in the reception data register 711 (reception data Full). Whether or not the command from the payout control microcomputer 370 has been received is confirmed by whether or not “1” is stored in bit 5. For example, in step S501, it is determined that the reception ACK signal is received on condition that “0” is not stored in bit 7.

  When the reception data is stored in the reception data register 711, the CPU 56 is ready to perform reception processing by reading the reception data from the reception data register 711. In this embodiment, when the reception interrupt is set, the serial communication circuit 505 sets the bit 5 of the status register A 705 to “1” when reception data full is detected, and enables reception processing. As an example, an interrupt request is made to the CPU 56 (referred to as an interrupt request upon reception).

  Bit 4 (bit name “IDLE”) of status register A705 stores an idle line detection flag indicating that the receiving circuit has detected an idle line. As shown in FIG. 14B, when “0” is stored in bit 4, it indicates that the receiving unit of the serial communication circuit 505 is not detecting the idle line. When “1” is stored in bit 4, it indicates that the receiving unit of the serial communication circuit 505 has detected an idle line.

  In bit 3 (bit name “OR”) of the status register A 705, the reception shift register 713 has received the next data before the CPU 56 reads the reception data stored in the reception data register 711 (overload). An overrun flag indicating (run) is stored. As shown in FIG. 14B, when “0” is stored in bit 3, it indicates that the receiving circuit is not detecting an overrun. If “1” is stored in bit 3, it indicates that the receiving circuit has detected an overrun.

  If an overrun occurs, the next received data is stored in the receiving shift register 713 before the received data in the received data register 711 is read, so that the received data is overwritten and the CPU 56 receives the received data. It cannot be read correctly. For this reason, communication with the microcomputer mounted on each control board cannot be performed correctly, causing the CPU 56 to malfunction. In this embodiment, when detecting an overrun, the serial communication circuit 505 sets bit 3 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 as an error has occurred during communication.

  Bit 2 (bit name “NF”) of status register A 705 stores a noise error flag indicating that noise has been detected in the received data. As shown in FIG. 14B, when “0” is stored in bit 2, it indicates that the receiving circuit is not detecting noise in the received data. Further, when “1” is stored in bit 2, it indicates that the receiving circuit has detected noise in the received data.

  For example, when detecting each bit of the received data, the serial communication circuit 505 detects “1” or “0” having a predetermined bit length using the baud rate generated by the baud rate generation circuit 703. In this case, when the detected length of “1” or “0” is less than the predetermined bit length, the serial communication circuit 505 detects a noise error as noise generated in the received data. When a noise error occurs, there is a high possibility that correct received data cannot be received due to the noise, which causes the CPU 56 to malfunction. In this embodiment, when detecting a noise error, the serial communication circuit 505 sets bit 2 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 as an error has occurred during communication.

  Bit 1 (bit name “FE”) of the status register A 705 indicates that it is detected that the position of the stop bit of the received data is “0” (originally, the stop bit is “1”) (framing error). A framing error flag is stored. As shown in FIG. 14B, when “0” is stored in bit 1, it indicates that the receiving circuit has not detected a framing error in the received data. When “1” is stored in bit 1, it indicates that the receiving circuit has detected a framing error.

  When a framing error occurs, it is in a state where the stop bit of the received data has not been received correctly, so there is a high possibility that correct received data cannot be received, causing the CPU 56 to malfunction. In this embodiment, when detecting a framing error, the serial communication circuit 505 sets bit 1 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 as an error has occurred during communication.

  Bit 0 (bit name “PF”) of the status register A 705 has a parity error flag indicating that the parity value obtained from the received data does not match the parity value included in the received data (parity error). Is stored. As shown in FIG. 14B, when “0” is stored in bit 0, it indicates that the receiving circuit has not detected a parity error in the received data. Further, when “1” is stored in bit 0, it indicates that the receiving circuit has detected a parity error.

  When a parity error occurs, each data bit or parity bit of the received data cannot be correctly received. Therefore, there is a high possibility that correct received data cannot be received, causing the CPU 56 to malfunction. In this embodiment, when the serial communication circuit 505 detects a parity error, the serial communication circuit 505 sets bit 0 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 on the assumption that an error has occurred during communication.

  FIG. 15A is an explanatory diagram illustrating an example of the status register B706. The status register B 706 is a register for confirming the reception state (reception status) of the serial communication circuit 505. In this embodiment, the CPU 56 can confirm the reception status of the serial communication circuit 505 by confirming the value of the bit of the status register B 706. As shown in FIG. 15B, the status register B 706 is an 8-bit register, and the initial value is set to “0 (= 00h)”. Further, the status register B 706 is configured so that bit 0 can only be read. Therefore, even if control is performed to write a value to bit 0 of status register A 705, it is invalid. Status register B 706 is configured such that bits 1 to 7 cannot be written or read. Therefore, even if control is performed to write a value to bits 1 to 7 of the status register A 705, the value is invalid and all the values read from bits 1 to 7 are “0 (= 0000b)”.

  FIG. 15B is a diagram showing an example of status confirmation data stored in the status register B706. As shown in FIG. 15B, a reception active flag indicating that the reception circuit is receiving reception data (reception active) is stored in bit 0 (bit name “RAF”) of the status register B706. . As shown in FIG. 15B, when “0” is stored in bit 0, it indicates that the reception circuit is not receiving reception data. Further, when “1” is stored in bit 0, it indicates that the reception circuit is receiving reception data. Even when “1” is stored in bit 0, command data is not written or command data cannot be written. When the serial communication circuit 505 detects the start bit, it assumes that reception of received data has started, and sets bit 0 of the status register B 706 to “1”.

  FIG. 16A is an explanatory diagram illustrating an example of the control register C709. The control register C709 is a register for setting whether to permit an interrupt request when a communication error occurs in the serial communication circuit 505. In this embodiment, by setting the value of each bit of the control register C709, it is set whether the interrupt request at the time of communication from the serial communication circuit 505 is permitted or prohibited. In the control register C709, error interrupt request setting data indicating whether or not various interrupt requests at the time of a communication error are permitted is mainly set. In addition to the error interrupt request setting data, the control register C709 stores 9th bit data when the data length is set to 9 bits. Various settings of the serial communication circuit 505 are also set. As shown in FIG. 16A, the control register C709 is an 8-bit register, and the initial value is set to “0 (= 00h)”. Control register C709 is configured such that bits 0 to 3 and bits 6 and 7 can be written and read. Further, the control register C709 is configured such that bits 4 and 5 cannot be written or read. Therefore, even if a control for writing a value to bits 4 and 5 of the control register C709 is performed, it is invalid, and all the values read from the bits 4 and 5 are “0 (= 0000b)”.

  FIG. 16B is an explanatory diagram showing an example of error interrupt request setting data set in the control register C709. As shown in FIG. 16B, the bit 7 (bit name “R8”) of the control register C709 stores the 9th bit data of the received data when the data length is set to 9 bits. Further, bit 6 (bit name “T8”) of the control register C709 stores the 9th bit data of the transmission data when the data length is set to 9 bits.

  In bit 3 (bit name “ORIE”) of the control register C709, setting data indicating whether or not to permit an overrun flag interrupt request, which is an interrupt request to be performed when an overrun is detected, is set. As shown in FIG. 16B, by setting bit 3 to “0”, the overrun flag interrupt request is set to be prohibited. Further, by setting bit 3 to “1”, the overrun flag interrupt request is set to be permitted.

  Bit 2 (bit name “NEIE”) of the control register C709 is set with setting data indicating whether or not to permit a noise error flag interrupt request, which is an interrupt request to be performed when a noise error is detected. As shown in FIG. 16B, by setting bit 2 to “0”, the noise error flag interrupt request is set to be prohibited. Also, by setting bit 2 to “1”, the noise error flag interrupt request is set to be permitted.

  Bit 1 (bit name “FEIE”) of the control register C709 is set with setting data indicating whether or not to permit a framing error flag interrupt request, which is an interrupt request to be performed when a framing error is detected. As shown in FIG. 16B, by setting bit 1 to “0”, the framing error flag interrupt request is set to be prohibited. Also, by setting bit 1 to “1”, the framing error flag interrupt request is set to be permitted.

  Bit 0 (bit name “PEIE”) of the control register C709 is set with setting data indicating whether or not to permit a parity error flag interrupt request which is an interrupt request to be performed when a parity error is detected. As shown in FIG. 16B, by setting bit 0 to “0”, the parity error flag interrupt request is set to be prohibited. Further, by setting bit 0 to “1”, the parity error flag interrupt request is set to be permitted.

  FIG. 17 is an explanatory diagram illustrating an example of a data register included in the serial communication circuit 505. The data register 701 is a register that stores data transmitted and received by the serial communication circuit 505. As shown in FIG. 17, the data register is an 8-bit register, and the initial value is set to “0 (= 00h)”. Data register 701 is configured such that bits 0 to 7 can be written and read.

  In this embodiment, when the serial communication circuit 505 transmits transmission data, the data register is used as the transmission data register 710. When the data length is set to 9 bits, bit 6 of the data register and control register C709 is used as the transmission data register 710. In this case, bits 0 to 7 of the data register are used as bits 0 to 7 of the transmission data register 710, and bit 6 of the control register C709 is used as bit 8 of the transmission data register 710.

  When the serial communication circuit 505 receives received data, the data register is used as the received data register 711. When the data length is set to 9 bits, bit 7 of the data register and control register C709 is used as the reception data register 711. In this case, bits 0 to 7 of the data register are used as bits 0 to 7 of the reception data register 711, and bit 7 of the control register C709 is used as bit 8 of the reception data register 711.

  The interrupt control circuit 714 makes various interrupt requests to the CPU 56. In this embodiment, when the bit 6 (TCIE) of the control register B 708 is set to “1”, the interrupt control circuit 714 notifies the CPU 56 when transmission of transmission data to the transmission data register 710 is completed. In addition to outputting an interrupt signal, an interrupt request is made by setting bit 6 (TC) of status register A705 to “1”. The interrupt control circuit 714 may output a different interrupt signal to the CPU 56 for each interrupt factor, instead of making the interrupt factor identifiable by the set value of the bit of the status register A705.

  In addition, when the bit 5 (RIE) of the control register B 708 is set to “1”, the interrupt control circuit 714 enters a state where the reception data is stored in the reception data register 711 (when reception data full is detected). ), An interrupt signal is output to the CPU 56, and an interrupt request is made by setting bit 5 (RDRF) of the status register A705 to “1”.

  Further, when any of the bits 0 to 3 of the control register C709 is set to “1”, the interrupt control circuit 714 outputs an interrupt signal to the CPU 56 and also indicates the type of communication error. In response to this, an interrupt request is made by setting "1" to bits 0 to 3 of the status register A705. For example, if bit 3 (ORIE) of the control register C709 is set to “1”, “1” is set to bit 3 (OR) of the status register A705 when an overrun is detected and an interrupt request is made. To do. For example, when bit 2 (NEIE) of the control register C709 is set to “1”, when a noise error is detected and an interrupt request is made, “1” is set to bit 2 (NF) of the status register A705. Set. For example, when bit 1 (FEIE) of the control register C709 is set to “1”, when a framing error is detected and an interrupt request is made, “1” is set to bit 1 (FE) of the status register A705. Set. For example, when bit 0 (PEIE) of the control register C709 is set to “1”, when a parity error is detected and an interrupt request is made, “1” is set to bit 0 (PF) of the status register A705. Set. When a plurality of communication errors are detected, the interrupt control circuit 714 makes an interrupt request based on the plurality of communication errors and sets the corresponding bits of the status register A 705 to “1”.

  The transmission format / parity generation circuit 715 generates a data format of transmission data. In this embodiment, the transmission format / parity generation circuit 715 generates a data format by adding a start bit and a stop bit to the transmission data stored in the transmission data register 710 and transfers the data format to the transmission shift register 712. When bit 1 (PE) of the control register A707 is set to “1” and the parity function is set to be used, the transmission format / parity generation circuit 715 adds a parity bit to the transmission data. Generate a data format.

  The reception format / parity check circuit 716 detects the data format of the reception data. In this embodiment, the reception format / parity check circuit 716 detects the start bit and the stop bit from the reception data stored in the reception shift register 713, detects the data portion included in the reception data, and receives the reception data register. Forward to 711. When bit 1 (PE) of the control register A707 is set to “1” and the parity function is set to be used, the reception format / parity check circuit 716 obtains the parity of the reception data and receives the reception data. It is detected whether or not it matches the parity included in. If the obtained value does not match the parity included in the received data, the reception format / parity check circuit 716 detects a parity error. If it is set in the serial communication circuit setting process to be described later that an interrupt request at the time of a communication error is permitted, the interrupt control circuit 714, when detecting a parity error, requests the CPU 56 to interrupt the occurrence of the communication error as a cause of interruption. I do.

  The jackpot determination table memory 571 stores a plurality of jackpot determination tables used by the CPU 56 to determine whether or not the display result of the special symbol display device 8 is a jackpot symbol. Specifically, as shown in FIG. 18A, the big hit determination table memory 571 stores a normal time big hit determination table 571a used in a gaming state (referred to as a normal state) other than the probability variation state. Further, the jackpot determination table memory 571 stores a probability change big hit determination table 571b used in the probability change state, as shown in FIG. When the big hit determination is performed using the determination table shown in FIG. 18, the probability of determining a big hit depends greatly on the random number maximum value set in the random number maximum value setting register 535. In this case, for example, if the set random number maximum value is too small, the difference in the probability of determining a big hit between the case where the normal big hit determination table 571a is used and the case where the probability variation big hit determination table 571b is used is small. As a result, the player's interest in the game is diminished. Therefore, a plurality of determination tables (a plurality of normal big hit determination tables 571a and a plurality of probability variation big hit determination tables 571b) are stored in the big hit determination table memory 571 in association with the random number circuit 503 and the random number maximum value. Also good. Then, the CPU 56 uses the random number circuit 503 to be used and the determination tables 571a and 571b corresponding to the maximum random number among the determination tables stored in the jackpot determination table memory 571, and displays a special symbol according to the display result determination program 552. You may make it determine whether the display result of the apparatus 8 is made a big hit symbol. By doing so, even if the type of random number circuit 503 to be used and the maximum random number value are different, it is possible to control so that the probability of determining a big hit is somewhat the same.

  19 and 20 are explanatory diagrams showing examples of output port assignment in the game control means. As shown in FIG. 19, the output port 0 is an output port of a payout control signal (in this example, a connection confirmation signal) transmitted to the payout control board 37. The output port 1 is an output port for an effect control signal (effect control command) transmitted to the sound / lamp control board 80b. The logic (for example, 0 is on) opposite to the “logic” (for example, 1 is on) shown in FIGS. 19 and 20 may be used. In particular, for the connection confirmation signal, the main board 31 is used. When the signal line between the control board 37 and the payout control board 37 is disconnected or when the cable is disconnected (including no cable connection), the payout control microcomputer 370 always detects “OFF”. Is defined. Specifically, generally, when disconnection or cable disconnection occurs, a high level is detected on the signal receiving side, so the high level on the signal line between the main board 31 and the payout control board 37 is the game control means. The “logic” is determined to be in the off state at the output port at. Therefore, if necessary, an output buffer circuit for logically inverting the signal is provided outside the output port on the main board 31.

  A solenoid (large winning opening door solenoid) 21 for opening and closing a variable winning ball apparatus 20 for opening and closing the large winning opening, a solenoid (large winning opening guide plate solenoid) 21A and a variable winning ball apparatus for switching a route in the large winning opening A drive signal for a solenoid (normal electric accessory solenoid) 16 for opening and closing 15 is output from the output port 2.

  Then, various information output signals from the output port 3 to the information terminal board 34 and the terminal board 160 through the information output circuit 64, that is, output data of information related to control are output.

  FIG. 21 is an explanatory diagram showing an example of bit assignment of input ports in the game control means. As shown in FIG. 21, the detection signals of the count switch 23, the gate switch 32a, the winning port switches 33a, 39a, 29a, and 30a and the start port switch 14a are input to bits 1 to 7 of the input port 0, respectively. . Also, the power-off signal from the power supply board 910 and the detection signal of the clear switch 921 are input to the bits 0 and 1 of the input port 1, respectively. Further, the detection signal of the payout number count switch 301 is input to bit 2 of the input port 1 via the payout control microcomputer 370. Instead of inputting the detection signal of the payout number count switch 301, a signal output from the payout control microcomputer 370 may be input when ten payout balls are reached. Further, a signal from the payout number count switch 301 may not be input to the game control means.

  Next, the operation of the gaming machine will be described. FIGS. 22 and 23 show main processing executed by the CPU 56 of the game control microcomputer 560 in response to the start of power supply to the game machine and the reset signal to the game control microcomputer 560 becoming high level. It is a flowchart which shows. When the input level of the reset terminal to which the reset signal is input becomes a high level, the CPU 56 of the game control microcomputer 560 executes a security check process that is a process for confirming whether the contents of the program are valid. The main processing after step S1 is started. In the main process, the CPU 56 first performs necessary initial settings.

  In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1). Next, an interrupt mode for maskable interrupts is set (step S2), and a stack pointer designation address is set for the stack pointer (step S3). In step S2, the address synthesized from the value (1 byte) of the specific register (I register) of the game control microcomputer 560 and the interrupt vector (1 byte: least significant bit 0) output from the built-in device is Set to the mode indicating the interrupt address. Further, when a maskable interrupt occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter in the stack.

  Next, the built-in device register is set (initialized) (step S4). By the processing in step S4, the CTC (counter / timer) and PIO (parallel input / output port) which are built-in devices (built-in peripheral circuits) are set (initialized).

  The game control microcomputer 560 used in this embodiment also incorporates an I / O port (PIO) and a timer / counter circuit (CTC) 504.

  Next, it is confirmed whether or not the power-off signal is in an OFF state depending on the state of bit 0 of the input port 1 (step S5). When the power supply to the gaming machine is started, the output voltage of various power sources such as the + 5V power source gradually reaches the specified value, but the power-off signal is not output by the process of step S5, that is, the high power By confirming that the power supply voltage is stable, the CPU 56 can confirm that the power supply voltage is stable.

  When the power-off signal is in the on state, the CPU 56 confirms again whether the power-off signal is in the off state after a delay time of a predetermined period (for example, 0.1 second) (step S80). To do. If the power-off signal is off, the RAM 55 is set to an accessible state (step S6), and the process proceeds to a clear signal check process.

  Note that a software delay process for delaying the start timing of the game device control process (game control process) for controlling the progress of the game by software may be executed. By such software delay processing, the start timing of the game control processing can be delayed as compared with the case where the software delay processing is not executed. When the delay process is executed, a situation occurs in which the microcomputer of the other control board cannot receive the command transmitted from the game control board (main board 31) to the other control board (for example, the payout control board 37). Can be prevented.

  Next, the CPU 56 checks whether or not the clear switch is turned on (step S7). Note that the CPU 56 may confirm the state of the clear signal only once via the input port 0, but may confirm the state of the clear signal a plurality of times. For example, if it is confirmed that the state of the clear signal is an off state, after a delay time of a predetermined time (for example, 0.1 seconds), the state of the clear signal is reconfirmed. If it is confirmed that the clear signal is in the on state at that time, it is determined that the clear signal is in the on state. Further, at this time, if it is confirmed that the state of the clear signal is the off state, after a delay time of a predetermined time, the state of the clear signal may be confirmed again. Here, the number of reconfirmations is not limited to once or twice, but may be three or more times. It is also possible to check twice and check again when the check results do not match.

  If the clear switch is not turned on in step S7, whether or not data protection processing of the backup RAM area (for example, power supply stop processing such as addition of parity data) has been performed when power supply to the gaming machine is stopped Confirm (step S8). In this embodiment, when power supply is stopped, a process for protecting data in the backup RAM area is performed. When it is confirmed that such power supply stop processing has been performed, the CPU 56 determines that the power supply stop processing has been performed, that is, the control state at the time of power supply stop is stored. . When it is confirmed that the power supply stop process is not performed, the CPU 56 executes an initialization process.

  Whether or not the power supply stop process has been performed is determined by the value of the backup monitoring timer stored in the backup RAM area in the power supply stop process corresponding to the execution of the power supply stop process (for example, 2). ) Is confirmed by whether or not. Note that such a confirmation method is an example. For example, a flag indicating that the power supply stop process has been executed is set in the backup flag area in the power supply stop process, and the flag is set in step S8. If it is confirmed that the power supply is stopped, it may be determined that the power supply stop process has been performed.

  If it is determined that the control state at the time of stopping power supply is stored, the CPU 56 performs data check (parity check in this example) in the backup RAM area (step S9). In this embodiment, clear data (00) is set in the checksum data area, and the checksum calculation start address is set in the pointer. Also, the number of checksum calculations corresponding to the number of data to be checksum is set. Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated. The calculation result is stored in the checksum data area, the pointer value is incremented by 1, and the checksum calculation count value is decremented by 1. The above processing is repeated until the value of the checksum calculation count becomes zero. When the value of the checksum calculation count becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area and uses the inverted data as the checksum.

  In the power supply stop process, a checksum is calculated by the same process as described above, and the checksum is stored in the backup RAM area. In step S9, the calculated checksum is compared with the stored checksum. When the power supply is stopped after an unexpected power failure or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area may be different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state when the power supply is stopped, the initialization process (the process of steps S10 to S14) executed when the power is turned on, not when the power supply is stopped is stopped. Run.

  If the check result is normal, the CPU 56 performs a game state restoration process for returning the internal state of the game control means and the control state of the electrical component control means such as the effect control means to the state when the power supply is stopped. Specifically, the start address of the backup setting table stored in the ROM 54 is set as a pointer (step S91), and the contents of the backup setting table are sequentially set in the work area (area in the RAM 55) (step S92). ). The work area is backed up by a backup power source. In the backup setting table, initialization data for an area that may be initialized in the work area is set. As a result of the processing in steps S91 and S92, the saved contents of the work area that should not be initialized remain. The parts that should not be initialized include, for example, data indicating the gaming state before the power supply is stopped (special symbol process flag, etc.), the area where the output state of the output port is saved (output port buffer), unpaid prize balls This is the part where data indicating the number is set.

  Further, the CPU 56 sets the head address of the backup command transmission table stored in the ROM 54 as a pointer (step S93), and proceeds to step S15. In addition, after setting in step S93, a backup command is transmitted after serial communication circuit setting processing in step S15a described later is performed.

  In the initialization process, the CPU 56 first performs a RAM clear process (step S10). Note that the predetermined data may be left as it is without initializing the entire area of the RAM 55. Also, the initial address of the initialization setting table stored in the ROM 54 is set as a pointer (step S11), and the contents of the initialization setting table are sequentially set in the work area (step S12).

  Control states such as a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol buffer, a total prize ball number storage buffer, a special symbol process flag, an award ball flag, an out-of-ball flag, etc. An initial value is set in a flag for selectively performing processing according to the above. In addition, a bit corresponding to the output port that outputs the connection confirmation signal in the output port buffer is set (corresponding to the ON state of the connection confirmation signal). When the bit corresponding to the output port that outputs the connection confirmation signal in the output port buffer is set, the bit corresponding to the output port 0 that outputs the connection confirmation signal is output by the output processing in step S31. The output may actually be started at the timing when the bit corresponding to the output port that outputs the connection confirmation signal is set (corresponding to the ON state of the connection confirmation signal).

  Further, the CPU 56 sets the start address of the initialization command transmission table stored in the ROM 54 as a pointer (step S13), and transmits an initialization command for initializing the sub board according to the contents to the sub board. Processing is executed (step S14). As an initialization command, a command indicating an initial symbol displayed on the variable display device 9, an initialization command to the payout control board 37, or the like can be used. After setting in step S13, an initialization command is transmitted after serial communication circuit setting processing in step S15a described later is performed.

  Further, the CPU 56 executes a random number circuit setting process for initially setting the random number circuits 503a and 503b (step S15). In this case, the CPU 56 performs setting according to the random number circuit setting program 551 to make the random number circuits 503a and 503b update the random R value.

  Further, the CPU 56 executes a serial communication circuit setting process for initial setting of the serial communication circuit 505 (step S15a). In this case, the CPU 56 sets the data stored in the predetermined area of the ROM 54 in the serial communication circuit 505 in accordance with the serial communication circuit setting program, so that the serial communication circuit 505 performs serial communication with the payout control microcomputer. I do.

  When the serial communication circuit 505 is initialized, the CPU 56 initializes the priority of interrupt processing executed in response to the interrupt request from the serial communication circuit 505 (step S15b). In this case, the CPU 56 initializes the priority of interrupt processing by executing processing according to the interrupt priority setting program 557.

  For example, the CPU 56 initializes the priority of each interrupt process according to a predetermined interrupt process priority table including the default priority of each interrupt process. In this embodiment, the CPU 56 performs initialization according to the interrupt processing priority table so as to preferentially execute an interrupt process whose cause is the occurrence of a communication error in the serial communication circuit 505. In this case, for example, the CPU 56 sets an interrupt priority execution flag at the time of communication error indicating that priority is given to an interrupt process whose cause is an interrupt.

  In this embodiment, when a timer interrupt and an interrupt request from the serial communication circuit 505 are generated at the same time, the CPU 56 preferentially performs an interrupt process by the timer interrupt.

  In addition, the default priority of each interrupt process can be changed by the user. For example, the game control microcomputer 560 stores specification information for specifying an interrupt process set by a user (for example, a game machine manufacturer) in a predetermined storage area of the ROM 54 in advance. Then, the CPU 56 sets the priority of interrupt processing according to the designation information stored in a predetermined storage area of the ROM 54.

  Then, the CPU 56 executes a timer interrupt setting process for setting a CTC register built in the game control microcomputer 560 so that a timer interrupt is periodically taken every predetermined time (for example, 2 ms) ( Step S16). That is, a value corresponding to, for example, 2 ms is set in a predetermined register (time constant register) as an initial value. In this embodiment, it is assumed that a timer interrupt is periodically taken every 2 ms.

  When the timer interrupt setting is completed, the CPU 56 first disables the interrupt (step S17), executes the initial value random number update process (step S18a) and the display random number update process (step S18b), The interrupt is permitted again (step S19). That is, the CPU 56 sets the interrupt disabled state when the initial value random number update process and the display random number update process are executed, and interrupts enable state when the initial value random number update process and the display random number update process are finished. To.

  The initial value random number update process is a process for updating the count value of the counter for generating the initial value random number. The initial value random number is a random number for determining the type of jackpot (for example, a jackpot symbol determining random number for determining a special symbol for generating a jackpot or whether to shift the gaming state to a probable state) Initial value of the count value such as a counter (determination random number generation counter) for generating a probability variation determining random number for generating, a normal random number for determining whether or not to generate a hit based on a normal symbol It is a random number for determining the value. A game control process described later (a process in which a game control microcomputer controls itself a game device such as a variable display device 9, a variable winning ball device 15, a ball payout device 97 provided in the game machine, or When the count value of the determination random number generation counter makes one round in a process of transmitting a command signal to cause another microcomputer to control, or a gaming apparatus control process), an initial value is set in the counter.

  The display random number is a random number for determining the display of the special symbol display 8. In this embodiment, as a display random number, a random number for determining a variation pattern for determining a variation pattern of a special symbol, or a random number for determining a reach for determining whether or not to reach when a big hit is not generated, is used. Used. The display random number update process is a process for updating the count value of the counter for generating the display random number.

  In addition, when the display random number update process is executed, the interrupt disabled state is executed by the display random number update process and the initial value random number update process also in the timer interrupt process described later (that is, the timer This is because the same processing is also executed in steps S24A and S24B of the interrupt processing), so as to avoid competing with the processing in the timer interrupt processing. That is, if a timer interrupt is generated during the processing of steps S18a and S18b and the count value of the counter for generating the initial value random number and the display random number is updated during the timer interrupt processing, The continuity of values may be impaired. However, such an inconvenience does not occur if the interrupt is prohibited during the processing of steps S18a and S18b.

  When the interrupt-permitted state is set in step S19, the timer interrupt or interrupt request from the serial communication circuit 505 is permitted until the next processing in step S17 is executed and the interrupt-prohibited state is set. . When a timer interrupt occurs while the interrupt permission state is set, the CPU 56 of the game control microcomputer 560 executes a timer interrupt process to be described later. When an interrupt request is generated from the serial communication circuit 505 while the interrupt permission state is set, the CPU 56 of the game control microcomputer 560 causes each interrupt process (communication error interrupt process or reception Execute time interruption processing and transmission completion interruption processing). In this embodiment, priority is given to the interrupt process before the timer interrupt or the interrupt request is set to be permitted by executing step S15b before the loop process from step S17 to step S19. Processing for setting or changing the order is performed.

  Next, the timer interrupt process will be described. FIG. 24 is a flowchart showing the timer interrupt process. When a timer interrupt occurs during execution of the main process, specifically during a period when interrupts are permitted during the execution of the loop process of steps S17 to S19, the CPU 56 of the game control microcomputer 560 A timer interrupt process that is activated in response to the occurrence of a timer interrupt is executed. In the timer interrupt process, the CPU 56 first executes a power-off process (power-off detection process) that detects whether or not a power-off signal has been output (whether or not it is turned on) (step S18a). Then, the CPU 56 inputs detection signals of switches such as the gate switch 32a, the start port switch 14a, the count switch 23 and the winning port switches 29a, 30a, 33a, and 39a via the switch circuit 58, and inputs the input of each switch. It detects (switch process: step S20). Specifically, if the state of the input port for inputting the detection signal of each switch is ON, the value of the switch timer provided corresponding to each switch is incremented by one. Further, the CPU 56 executes an input determination process for determining the input state of each switch based on the detection result of step S20 (step S21).

  Next, the CPU 56 receives the received ACK signal when the received ACK signal received by the serial communication circuit is a signal indicating the occurrence of a predetermined error (when the occurrence of the predetermined error is specified by the received received ACK signal). An input data confirmation process for transmitting the data of the predetermined error specified in (1) to the production control microcomputer 100 is executed (step S22).

  Further, the CPU 56 executes an input determination process for determining the input state of each switch based on the detection result of step S21 (step S23).

  Next, the CPU 56 performs a process of updating the count value of the counter for generating the display random number (display random number update process: step S24A). Further, the CPU 56 performs a process of updating the count value of the counter for generating the initial value random number (initial value random number update process: step S24B).

  Next, the CPU 56 performs a process of setting an effect control command related to a decorative symbol synchronized with the variation of the special symbol in a predetermined area of the RAM 55 and sending the effect control command (command control process: step S25). Note that the fact that the variation of the decorative symbol is synchronized with the variation of the special symbol means that the variation time (variable display period) is the same.

  Further, the CPU 56 executes a process of transmitting / receiving (input / output) signals to / from the payout control microcomputer 370 via the serial communication circuit 505. When a winning occurs, the winning opening switches 29a, 30a, 33a, Prize ball processing for setting the number of prize balls based on the detection signal such as 39a is executed (step S26). In this embodiment, data indicating the number of winning balls is obtained by changing predetermined bits of the winning ball request signal in response to detection of winning based on the winning opening switches 29a, 30a, 33a, 39a being turned on. Is set as a prize ball request signal, and the set prize ball request signal is output to the payout control microcomputer 370 via the serial communication circuit 505. The payout control microcomputer 370 mounted on the payout control board 37 drives the ball payout device 97 in response to receiving a prize ball request signal in which data indicating the number of prize balls is set.

  In this embodiment, in the input determination process (step S23), the number of winnings is counted according to the winning detection based on the winning opening switch 29a, 30a, 33a, 39a, etc. being turned on. Then, in the prize ball process of the main process, a prize ball request signal in which data indicating the number of prize balls is set is transmitted to the payout control board 37 based on the counted number of winnings.

  Further, the CPU 56 performs special symbol process processing (step S27). In the special symbol process, the corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state. Further, normal symbol process processing is performed (step S28). In the normal symbol process, the corresponding process is selected and executed according to the normal symbol process flag for controlling the display state of the normal symbol display 10 in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state.

  Further, the CPU 56 performs information output processing for outputting data such as jackpot information, start information, probability variation information supplied to the hall management computer (step S29).

  In addition, a test terminal process, which is a process for outputting a test signal for enabling the control state of the gaming machine to be confirmed outside the gaming machine, is executed (step S30). In this embodiment, a RAM area (output port buffer) corresponding to the output state of the output port is provided. However, the CPU 56 determines the contents related to the connection confirmation signal in the RAM area of the output port 0 and the output port. The contents related to the solenoid in the RAM area 2 are output to the output port (step S31: output process).

  Next, the serial communication circuit setting process (step S15a) in the main process will be described. FIG. 25 is a flowchart showing the serial communication circuit setting process. In the serial communication circuit setting process, the CPU 56 first executes the process according to the serial communication circuit setting program 556 to set the baud rate of the serial communication circuit 505 (step S1511). In this case, the CPU 56 writes a setting value corresponding to the baud rate to be set in the baud rate register 702 of the serial communication circuit 505. For example, the game control microcomputer 560 stores specification information for specifying a set value set by a user (for example, a game machine manufacturer) in a predetermined storage area of the ROM 54 in advance. Then, the CPU 56 writes the setting value in the baud rate register 702 according to the designation information stored in a predetermined storage area of the ROM 54. For example, when the baud rate set value “156” is set by the CPU 56, the baud rate “1201.92 bps” is generated by the baud rate generation circuit 703 using the equation (1) and the clock frequency “3 MHz”.

  Further, the CPU 56 sets a data format of data transmitted / received by the serial communication circuit 505 (step S1512). In this case, the CPU 56 sets the data length (8 bits or 9 bits) of the transmission / reception data and the use / nonuse of the parity function by setting the value of each bit of the control register A707. For example, the game control microcomputer 560 stores specification information for specifying the value of each bit of the control register A707 set by the user (for example, the manufacturer of the game machine) in a predetermined storage area of the ROM 54 in advance. Yes. Then, the CPU 56 sets the value of each bit of the control register A707 according to the designation information stored in a predetermined storage area of the ROM 54.

  In addition, the CPU 56 sets whether to permit each interrupt request generated by the serial communication circuit 505 (step S1513). In this case, the CPU 56 sets the value of bits 5, 6, and 7 of the control register B708 to thereby send an interrupt request at the time of transmission (a transmission interrupt request that is an interrupt request that is made when data is transmitted, Request) and whether or not to accept interrupt request at reception. Note that the CPU 56 can also be set to allow both a transmission interrupt request and a reception interrupt request, and allows only one of a transmission interrupt request and a reception interrupt request. It is also possible to set. Further, the CPU 56 sets whether or not to permit an interrupt request at the time of each communication error by setting the values of the bits 0 to 3 of the control register C709. For example, the gaming control microcomputer 560 stores, in advance, a predetermined storage area in the ROM 54 for specifying information for specifying the value of each bit of the control register B 708 and the control register C 709 set by the user (for example, the manufacturer of the gaming machine). I remember it. Then, the CPU 56 sets the value of each bit of the control register B 708 and the control register C 709 according to the designation information stored in a predetermined storage area of the ROM 54.

  Next, the prize ball process (step S26) in the main process will be described. First, a payout control signal (connection confirmation signal) and a prize ball request signal (payout control command) transmitted and received between the main board 31 and the payout control board 37 will be described.

  FIG. 26 is an explanatory diagram showing an example of the contents of a control signal output from the game control means to the payout control means. In this embodiment, a connection confirmation signal is transmitted and received as a control signal between the main board 31 and the payout control board 37 in order to perform various controls relating to payout control and the like. As shown in FIG. 26, the connection confirmation signal is output when the main board 31 rises (when the game control means starts the game control process), and indicates that the main board 31 has risen with respect to the payout control board 37. This is a signal for notification (connection confirmation signal for the main board 31). The connection confirmation signal indicates that the winning ball can be paid out. The connection confirmation signal is output via the I / O port 57 and the output circuit 67 of the game control microcomputer 560, and the payout control is performed via the input circuit 373A and the I / O port 372e of the payout control microcomputer 370. To the microcomputer 370. Each connection confirmation signal is 1-bit data, and is transmitted through one signal line. Note that the connection confirmation signal is ready to be output by setting an initial value to a bit corresponding to the connection confirmation signal of the output port 0 by the processing of steps S92 and S12 executed when the power is turned on (specifically, Is output by the process of step S31, but may be output at the timing of steps S92 and S12).

  Similarly to the game control microcomputer 560, the payout control microcomputer 370 includes a serial communication circuit 380. Various payout control commands are transmitted and received between the serial communication circuit 505 built in the game control microcomputer 560 and the serial communication circuit 380 built in the payout control microcomputer 370. The configuration and function of the serial communication circuit 380 built in the payout control microcomputer 370 are the same as the configuration and function of the serial communication circuit 505 built in the game control microcomputer 560.

  FIG. 27 is an explanatory diagram showing an example of the contents of control commands transmitted and received between the game control means and the payout control means. In this embodiment, various control commands (prize ball request signals) are transmitted and received between the microcomputers of the main board 31 and the payout control board 37 in order to perform various controls relating to payout control and the like.

  As described above, the prize ball request signal and the reception ACK signal are composed of 8-bit data (binary 8-digit data), and are output as control commands indicating predetermined contents according to the contents of the set 8-bit data. Is done.

  The connection confirmation command is sent from the game control microcomputer 560 at regular intervals (1 s) in order to confirm whether or not the connection state between the game control microcomputer 560 and the payout control microcomputer 370 is normal. Control command to be sent. The data content of the connection confirmation command is “A0 (H)”, that is, “1010000”.

  The connection OK command is a control command for notifying that the connection state between the game control microcomputer 560 and the payout control microcomputer 370 is normal, and the payout control microcomputer 370 issues a connection confirmation command. Is a control command that is transmitted as a response signal in response to the reception of. The data content of the connection OK command is “8x (H)”, that is, “10000xxx”. Here, a prize ball error (abnormal state in which a prize ball payout operation based on a winning or a ball lending payout operation based on a ball lending request cannot be normally performed: specifically, a payout switch abnormality detection error shown in FIG. 1) When a payout switch abnormality detection error 2, a payout case error, a prepaid card unit unconnected error, and a prepaid card unit communication error) occur, “1” is set to “x” of the first bit. If a full tank error occurs, “1” is set to “x” of the second bit. When a ball break error occurs, “1” is set to “x” of the third bit. When a door opening error occurs, “1” is set to “x” of the fourth bit. In this way, during the confirmation of the connection between the game control microcomputer 560 and the payout control microcomputer 370, the occurrence of a predetermined error in the payout control microcomputer 370 is detected. 560 can be notified.

  The award ball number command is a control command for notifying the number (0 to 15) of game balls for which a payout request is made, and is a control command transmitted by the game control microcomputer 560 based on the occurrence of a win. . The content of the prize ball number command data is “5x (H)”, that is, “0101xxx”. In this embodiment, when a game ball is detected by the start port switch 14a, three prize balls are paid out, and when a game ball is detected by any one of the prize port switches 33a, 39a, 29a, 30a, ten game balls are detected. When a game ball is detected by the count switch 23, 15 prize balls are paid out. Therefore, when a game ball is detected by the start port switch 14a, a prize ball number command “01010011” for notifying the number of prize balls of 3 is transmitted, and any of the prize port switches 33a, 39a, 29a, 30a is transmitted. When a game ball is detected, a prize ball number command “01011010” for notifying 10 prize balls is transmitted, and when a game ball is detected by the count switch 23, 15 prize balls are notified. The award ball number command “0101111” is transmitted. Note that either the connection confirmation command or the prize ball number command is transmitted as a prize ball request signal. The prize ball number command is transmitted instead of the connection confirmation command at the timing when the connection confirmation command is transmitted based on the fact that the prize ball payout condition (occurrence of winning etc.) is established. In this embodiment, as described above, data corresponding to the number of prize balls is set in the upper 4 bits. However, data corresponding to the number of prize balls is set in the lower 4 bits in common with the upper 4 bits. You may do it.

  The award ball end command is a control command indicating that the award ball operation (award ball payout operation) has ended, and is a control command that the payout control microcomputer 370 transmits based on the end of the award ball operation. The data content of the winning ball end command is “50 (H)”, that is, “01010000”. The winning ball end command is transmitted instead of the connecting OK command at the timing when the connecting OK command is transmitted based on the end of the winning ball operation. In this embodiment, data indicating error information is not set in the winning ball end command. This is because the award ball end command is transmitted only once when the award ball operation is completed, so that data indicating error information is set in the next connection OK command and transmitted without sending error information at that timing. This is because it is possible to do so. Note that data indicating error information may be set in the lower 4 bits of the winning ball end command.

  The winning ball preparation command is a control command for notifying that a predetermined error has occurred and the winning ball operation has not ended, and a predetermined error has occurred while the payout control microcomputer 370 is executing the winning ball operation. This is a control command to be transmitted based on what has been done. The data content of the connection OK command is “8x (H)”, that is, “10000xxx”. Here, when a prize ball error occurs, “1” is set to “x” of the first bit. If a full tank error occurs, “1” is set to “x” of the second bit. When a ball break error occurs, “1” is set to “x” of the third bit. When a door opening error occurs, “1” is set to “x” of the fourth bit. In this way, the payout control microcomputer 370 notifies the game control microcomputer 560 that a predetermined error has occurred during execution of the winning ball operation and the winning ball operation has not ended. In addition, the contents of the error can be notified to the game control microcomputer 560. As in the case of the connection OK command, the award ball preparation command notifies that a predetermined error has occurred by changing the contents of the lower 4 bits in accordance with the error state (by changing the predetermined bits). The connection OK command, the winning ball preparation command, and the winning ball end command are configured such that any command is transmitted as a received ACK signal. The prize ball preparing command is a command (signal) that is output not only in a state where an error has occurred and the prize ball operation cannot be executed but also in a state where the prize ball operation is being executed.

  The award ball preparation command is transmitted instead of the connection OK command at the timing when the connection OK command is transmitted based on the situation where an error has occurred and the prize ball operation cannot be performed. is there.

  FIG. 28 is a block diagram showing signal lines and the like used for transmission / reception of the control signal shown in FIG. 26 and the control command shown in FIG. As shown in FIG. 28, the connection confirmation signal is output via the output circuit 67 by the game control microcomputer 560 and input to the payout control microcomputer 370 via the input circuit 373A. Of the control commands, the connection confirmation command and the winning ball number command are output from the serial circuit 505 built in the game control microcomputer 560 and input to the serial circuit 380 built in the payout control microcomputer 370. Of the control commands, the connection OK command, the winning ball end command, and the winning ball preparation command are output from the serial circuit 380 included in the payout control microcomputer 370 and are output to the serial circuit 505 included in the game control microcomputer 560. Entered. In FIG. 28, two signal lines (a signal line for transmitting a prize ball request signal and a signal line for transmitting a reception ACK signal) are shown as signal lines for performing serial communication. Actually, a prize ball request signal and a reception ACK signal are transmitted and received through one signal line.

  Next, transmission / reception of signals (prize ball request signal, reception ACK signal; control command) between the game control microcomputer and the payout control microcomputer during normal operation will be described. The prize ball request signal includes a connection confirmation command and a prize ball number command, and the reception ACK signal includes a connection OK command, a prize ball end command, and a prize ball preparation command.

  FIG. 29 is a sequence diagram showing signal transmission / reception between the game control microcomputer and the payout control microcomputer during normal operation. As shown in FIG. 29, the game control microcomputer 560 receives an award to confirm whether or not the signal line connection with the payout control microcomputer 370 is disconnected via the serial communication circuit 505. A connection confirmation command as a ball request signal is transmitted to the payout control microcomputer 370. When the payout control microcomputer 370 receives a connection confirmation command as a prize ball request signal via the serial communication circuit 380, the payout control microcomputer 370 transmits a connection OK command as a reception ACK signal to the game control microcomputer 560. When the game control microcomputer 560 receives the connection OK command as the reception ACK signal, the game control microcomputer 560 transmits a connection confirmation command as the prize ball request signal after 1 s (1 second) has elapsed from the time of reception. As long as the connection state is normal, the game control microcomputer 560 and the payout control microcomputer 370 repeatedly execute the connection confirmation communication process as described above.

  FIG. 30 is a sequence diagram showing signal transmission / reception between the game control microcomputer and the payout control microcomputer during the prize ball operation. As shown in FIG. 30, when a winning occurs and a prize ball payout operation is executed, the game control microcomputer 560 receives a prize ball in which data indicating the number of prize balls is set via the serial communication circuit 505. A prize ball number command as a request signal is transmitted to the payout control microcomputer 370. When the payout control microcomputer 370 receives the prize ball number command as the prize ball request signal, it executes a payout operation for the number of prize balls designated by the prize ball number command, and when the prize ball payout operation is completed. A prize ball end command as a reception ACK signal indicating the end of the prize ball payout operation is transmitted to the game control microcomputer 560 via the serial communication circuit 380.

  On the other hand, the payout control microcomputer 370 executes a payout operation for the number of prize balls specified by the prize ball number command based on the reception of the prize ball number command as the prize ball request signal. When a predetermined error occurs and a state in which a prize ball payout operation cannot be performed (abnormal state, error state), a reception ACK signal is sent to notify that an error has occurred and the prize ball payout operation has not ended. A command for preparing a prize ball is transmitted to the microcomputer 560 for game control. In this case, the payout control microcomputer 370 transmits a prize ball preparing command as a reception ACK signal to the game control microcomputer 560 at regular intervals (every 1 s) unless the generated error is canceled. The prize ball preparing command is a command (signal) that is output not only in a state where an error has occurred and the prize ball operation cannot be executed but also in a state where the prize ball operation is being executed.

  FIG. 31 is a timing chart showing signal transmission / reception between the game control microcomputer and the payout control microcomputer during normal operation. As shown in FIG. 31, when the game control microcomputer 560 transmits a connection confirmation command as a prize ball request signal to the payout control microcomputer 370, the game control microcomputer 560 serves as a reception ACK command transmitted from the payout control microcomputer 370. A connection OK command is received. When the game control microcomputer 560 receives the connection OK command as the reception ACK signal, the game control microcomputer 560 transmits the connection confirmation command as the prize ball request signal again after 1 s (1 second) has elapsed from the time of reception. As long as the connection state is normal, the game control microcomputer 560 and the payout control microcomputer 370 repeatedly execute the connection confirmation communication process as described above.

  If there is a win when the connection confirmation communication process is not executed (between receiving the connection OK command as a reception ACK signal and transmitting the connection confirmation command as a prize ball request signal) The control microcomputer 560 sets data indicating the number of prize balls in the prize ball request signal, and transmits a prize ball number command as the set prize ball request signal to the payout control microcomputer 370. When the payout control microcomputer 370 receives the prize ball number command as the prize ball request signal, it pays out the number of prize balls designated by the prize ball number command, and the prize ball is paid out (prize ball payout operation). Upon completion, a prize ball end command as a reception ACK signal is transmitted to the game control microcomputer 560. When the game control microcomputer 560 receives a prize ball end command as a reception ACK signal, it transmits a connection confirmation command as a prize ball request signal after 1 s (1 second) has elapsed since the reception.

  If there is a prize during the execution of the connection confirmation communication process (between sending the connection confirmation command as a prize ball request signal and receiving the connection OK command as a reception ACK signal), the game control micro The computer 560 sets data indicating the number of prize balls in the prize ball request signal, and uses the prize ball number command as the set prize ball request signal as a connection OK command as a reception ACK signal from the payout control microcomputer 370. Is sent to the payout control microcomputer 370. When the payout control microcomputer 370 receives the prize ball number command as the prize ball request signal, it pays out the number of prize balls designated by the prize ball number command, and the prize ball is paid out (prize ball payout operation). Upon completion, a prize ball end command as a reception ACK signal is transmitted to the game control microcomputer 560. It should be noted that a prize ball preparation command as a reception ACK signal is transmitted to the game control microcomputer 560 during execution of prize ball payout (prize ball payout operation).

  FIG. 32 is a timing chart showing signal transmission / reception between the game control microcomputer and the payout control microcomputer when an error occurs in the winning ball. As shown in FIG. 32, when the game control microcomputer 560 transmits a connection confirmation command as a prize ball request signal to the payout control microcomputer 370, it receives A connection OK command is received. If there is a prize when the communication process for confirming the connection is not executed, the game control microcomputer 560 sets the data indicating the number of prize balls in the prize ball request signal, and uses the prize ball request signal as the set prize ball request signal. Are sent to the payout control microcomputer 370. When receiving the prize ball number command as the prize ball request signal, the payout control microcomputer 370 pays out the number of prize balls designated by the prize ball number command. A state in which a predetermined error (ball lending, full tank, out of ball error) occurs and the prize ball payout operation cannot be performed while executing the payout operation of the number of prize balls specified by the prize ball number command ( In the case of an abnormal state or an error state), the payout control microcomputer 370 game-controls a prize ball preparing command as a reception ACK signal for notifying that an error has occurred and the prize ball payout operation has not ended. To the microcomputer 560. In this case, the payout control microcomputer 370 transmits a prize ball preparing command as a reception ACK signal to the game control microcomputer 560 at regular intervals (every 1 s) unless the generated error is canceled. When the predetermined error state is canceled (resolved) and the winning ball payout operation ends, the payout control microcomputer 370 transmits a winning ball end command as a reception ACK signal to the game control microcomputer 560. The prize ball preparing command as a reception ACK signal is transmitted every 1 s because it is transmitted in response to receiving a prize ball request signal transmitted every 1 s from the game control microcomputer 560. It will be. The game control microcomputer 560 may be configured not to transmit a prize ball request signal as a connection confirmation command while a prize ball preparation command as a reception ACK signal is received. In this case, the payout control microcomputer 370 outputs a prize ball end command based on the completion of the prize ball payout operation, and the game control microcomputer 560 receives the prize ball end command. It may be configured to return so as to return to a state in which a prize ball request signal is output every predetermined period (1S).

  FIG. 33 is a timing chart showing signal transmission / reception between the game control microcomputer and the payout control microcomputer when a communication error occurs during connection confirmation. As shown in FIG. 33, the game control microcomputer 560 transmits a connection confirmation command as a prize ball request signal to the payout control microcomputer 370, but the connection as a reception ACK command from the payout control microcomputer 370. If an OK command has not been received, that is, if an abnormal connection state (communication error) has occurred, the prize ball is again 10 seconds (10 seconds) after the connection confirmation command is sent as a prize ball request signal. A connection confirmation command is transmitted as a request signal. If a win occurs when a communication error occurs, the game control microcomputer 560 receives a connection OK command as a reception ACK signal from the payout control microcomputer 370 as a prize ball request signal. Without transmitting the award ball number command, the connection confirmation command as a prize ball request signal is continuously transmitted at regular intervals (10 s). When the communication error is canceled (resolved) and a connection OK command as a reception ACK signal is transmitted from the payout control microcomputer 370, the game control microcomputer 560 transmits a prize ball number command as a prize ball request signal. To do.

  FIG. 34 is a timing chart showing signal transmission / reception between the game control microcomputer and the payout control microcomputer when a communication error occurs during the award ball number notification. As shown in FIG. 34, the game control microcomputer 560 has transmitted a prize ball number command as a prize ball request signal based on the occurrence of a win, but has received a received ACK signal from the payout control microcomputer 370. If a prize ball end command is not received, that is, if a connection status abnormality (communication error) occurs, the prize ball number command as a prize ball request signal is not retransmitted (retry), A connection confirmation command as a prize ball request signal is sent to the payout control microcomputer 370 after 10 seconds (10 seconds) have elapsed since the prize ball number command as a ball request signal was sent. Although not shown in FIG. 34, when the communication error is canceled (resolved) and a prize ball end command as a reception ACK signal is transmitted from the payout control microcomputer 370, the game control microcomputer 560 Return to normal (normal) operation. In this embodiment, if a communication error occurs after the prize ball number command is transmitted once, the prize ball number command is not transmitted again (retry is not performed). Although not limited to the above, the prize ball number command data is left, but the configuration may be such that the prize ball number command data is intentionally transmitted and the prize ball number command transmission is prohibited.

  Next, the prize ball process (step S26) will be described. 36 and 37 are flowcharts showing the prize ball processing. In the prize ball processing, the CPU 56 checks whether or not a reception ACK signal (connection OK command, prize ball end command, prize ball preparation command) has been received (step S501), and if no reception ACK signal has been received. (N of step S501) It is confirmed whether the 1s measurement timer which measures 1 second has timed out (step S502). If the 1s measurement timer has not timed out (N in step S502), the CPU 56 decrements the value of the 1s measurement timer by 1 (step S512) and checks whether the 10s measurement timer that measures 10 seconds has timed out (step S512). Step S513). If the 10s measurement timer has not timed out (N in step S513), the value of the 10s measurement timer is decremented by 1 (step S514). On the other hand, when the 10s measurement timer times out (Y in step S513), it is a case where a communication error has occurred, and the CPU 56 executes a process of transmitting a connection confirmation command to the payout control microcomputer 370 (step S51). S511). By such processing, when a communication error occurs, a connection confirmation command is transmitted every 10 seconds. Thereafter, the CPU 56 sets a transmitted flag (step S510) and ends the process.

  In this embodiment, “command transmission” corresponds to writing command data in the transmission data register of the serial communication circuit. That is, the command is transmitted by serial communication by writing the command data in the transmission data register of the serial communication circuit in this way. This is the same for any command transmission of the game control microcomputer 560 and the payout control microcomputer 370.

  In step S502, when the 1s measurement timer times out (Y in step S502), the CPU 56 checks whether a transmitted flag indicating that a prize ball number command or a connection confirmation command has been transmitted is set. (Step S503). If the transmitted flag is set (Y in step S503), the process in step S514 or S511 is executed following the process in step S513. If the transmitted flag is not set (N in step S503), the CPU 56 includes error information in the received ACK signal (connection OK command, winning ball preparation command) received last time from the payout control microcomputer 370. It is confirmed whether or not it has been played (step S504). Whether or not error information is included in the received ACK signal is confirmed by whether or not the error information flag is set in step S586 in the input data confirmation processing (FIG. 43) described later. If error information is included in the received ACK signal (Y in step S504), a process of transmitting a connection confirmation command as a prize ball request signal to the payout control microcomputer 370 is executed (step S511). If error information is not included in the received ACK signal (N in step S504), the CPU 56 is executing a prize ball payout operation (if it is normal, based on having transmitted a prize ball number command). It is confirmed whether or not a prize ball flag indicating that a prize ball operation is being executed is set (step S505).

  If the award ball flag is set (Y in step S505), the CPU 56 executes a process of transmitting a connection confirmation command (step S511). If the winning ball flag is not set (N in step S505), the CPU 56 checks whether there is an unpaid winning ball number (step S506). Whether there is an unpaid prize ball number is whether the value of the prize ball command output counter is 0 (if it is 0, there is no unpaid prize ball number, otherwise it is an unpaid prize ball number). It is possible to confirm. If there is no unpaid prize ball number (N in step S506), a process of transmitting a connection confirmation command is executed (step S511). If there is an unpaid prize ball number (Y in step S506), the CPU 56 subtracts the prize ball number designated by the prize ball number command from the total prize ball number storage buffer (step S507), and according to the unpaid prize ball number. A process of transmitting a winning ball number command indicating the number of winning balls is executed (step S508).

  When the prize ball number command is transmitted, the prize ball number table shown in FIG. 35 is used. The prize ball number table is set in the ROM 54. The number of processes (in this example, “3”) is set at the start address of the prize ball number table, and thereafter, a prize ball command output counter and prize ball designation data for designating the number of prize balls are set in sequence. Yes. The prize ball command output counter is a counter that counts the number of prizes received in the prize opening, and is set in the ROM 54, for example. The game control microcomputer 560 includes a corresponding prize ball command output counter for each number of prize balls (0 to 15). In this embodiment, the game control microcomputer 560 includes a prize ball command output counter 1 corresponding to the number of prize balls “3”, a prize ball command output counter 2 corresponding to the number of prize balls “10”, and a prize ball. And a prize ball command output counter 3 corresponding to the number “15”. Each prize ball command output counter is counted up in the input determination process of the timer interrupt process, as will be described later. If the prize ball command output counter 3 set in the prize ball number table is not 0, the CPU 56 indicates the number of prize balls (15) based on the prize ball designation data for designating the number of prize balls (15). The data is set as a prize ball request signal, and the set prize ball request signal is transmitted to the payout control microcomputer 370 as a prize ball number command. Further, the CPU 56 designates the number of prize balls (10) if the value of the prize ball command output counter 3 set in the prize ball number table is 0 and the value of the prize ball command output counter 2 is not 0. Data indicating the number of prize balls (10) is set in the prize ball request signal based on the prize ball designation data to be transmitted, and the set prize ball request signal is transmitted to the payout control microcomputer 370 as a prize ball number command. . The CPU 56 determines the number of prize balls if the prize ball command output counter 3 and prize ball command output counter values set in the prize ball number table are 0 and the value of the prize ball command output counter 1 is not 0. Based on the prize ball designation data for designating (three), data indicating the number of prize balls (three) is set in the prize ball request signal, and the set prize ball request signal is used as a prize ball number command for payout control. It transmits to the microcomputer 370.

  Next, the CPU 56 sets a flag in the winning ball (step S509), sets a transmitted flag (step S510), and ends the process. It should be noted that, prior to performing the process of step S524, the reception of the winning ball preparation command may be confirmed, and when the winning ball preparation command is received, the winning ball flag may be set. Further, a subtraction process for subtracting the number of prize balls may be performed before the command is transmitted. Further, before or after the process of step S510, the process of step S521 (set of 1s measurement timer) or step S522 (set of 10s measurement timer) may be performed.

  When the reception ACK signal is received in step S501 (Y in step S501), the CPU 56 sets a 1s measurement timer (step S521), sets a 10s measurement timer (step S522), and sets a transmitted flag. Reset (step S523). Then, the CPU 56 checks whether or not a winning ball end command has been received, that is, whether or not the received ACK signal is a winning ball end command (step S524). If it is a winning ball end command, the winning ball flag is reset (step S525), and the process ends. In this embodiment, even if the payout control microcomputer 370 side is set to an error state, the prize ball number command once transmitted is not transmitted again.

  As described above, in this embodiment, when a prize ball number command as a prize ball request signal is transmitted, a subtraction process for subtracting 1 from the value of the prize ball command output counter is executed. At this time, the payout control microcomputer 370 has not yet paid out the number of prize balls specified by the prize ball number command. If configured to perform subtraction processing of the total prize ball number storage buffer when the winning ball payout is completed, an illegal act of restoring the power supply after illegally stopping the power supply of the gaming machine during paying the winning ball As a result, a large number of prize balls are illegally paid out. For example, when 15 prize ball payouts are instructed by a prize ball number command, when 10 prize ball payouts are made, if the power supply is restored after illegally stopping the power supply of the gaming machine. Since the contents of the prize ball command output counter are not subtracted at all, it is assumed that the 10 prize balls are not paid out even though 10 prize balls are actually paid out. Control will continue. However, in this embodiment, when the prize ball number command is transmitted, the prize ball command output counter is subtracted, so that the above-mentioned fraud can be prevented.

  Further, when the CPU 56 is configured to perform the subtraction process of the prize ball command output counter when receiving the prize ball end command as the reception ACK signal, if the CPU 56 cannot recognize the reception of the prize ball end command, what There is a possibility that the prize ball number command will be transmitted again, and there is a risk that excessive prize ball payout will be performed. Since the processing is executed, it is possible to prevent the above inconvenience.

  Next, the special symbol process (step S27) in the main process will be described. FIG. 38 is a flowchart showing an example of a special symbol process processing program executed by the CPU 56 of the game control microcomputer 560. The CPU 56 of the game control microcomputer 560 starts the game ball when the start port switch 14a for detecting that the game ball has won the start winning port 14 provided in the game board 6 is turned on. If the winning opening 14 is won and the winning detection signal SS is input from the start opening switch 14a (step S311), after the start opening switch passing process (step S312) is performed, depending on the internal state, steps S300 to S308 are performed. One of the processes is performed.

  Special symbol normal processing (step S300): A state in which variable symbol special display can be started (for example, the symbol variation has not been made in the special symbol display 8, and the previous symbol variation in the special symbol display 8 has been completed. Waits for a predetermined period of time to elapse, and not a big hit game). When the special symbol variable display can be started, the start winning memory number for the special symbol is confirmed. If the start winning memorization number is not 0, it is determined whether or not the result of variable symbol special display is a big hit based on the random R generated by the random number circuit 503 stored in the special figure holding memory 570. Then, the internal state (special symbol process flag) is updated so as to shift to step S301.

  Special symbol stop symbol setting process (step S301): A stop symbol after variable display of the special symbol is determined. Then, the internal state (special symbol process flag) is updated so as to shift to step S302.

  Variation time setting process (step S302): A variation pattern is determined, and variation time in the variation pattern (variable display time: time from when variable display is started until display result is derived display (stop display)) is a special symbol It is determined to be a variable display variable time. In addition, a variation time timer that measures the variation time of the determined special symbol is started. Then, the internal state (special symbol process flag) is updated so as to shift to step S303.

  Special symbol variation process (step S303): When a predetermined time (the time indicated by the variation time timer in step S302) elapses, the internal state (special symbol process flag) is updated to shift to step S304.

  Special symbol stop process (step S304): A decorative symbol stop command for instructing stop of the decorative symbol is transmitted to the sound / lamp control board 80b. Moreover, the special symbol in the special symbol display 8 is stopped. If the stop symbol of the special symbol is a big hit symbol, the internal state (special symbol process flag) is updated to shift to step S305. If not, the internal state is updated to shift to step S300. Note that a configuration in which a decorative symbol stop command is not transmitted may be employed. In this case, the symbol control board 80a sets the fluctuation time in the fluctuation time timer based on the fluctuation pattern command received from the main board 31 via the sound / lamp control board 80b, and updates the fluctuation time timer. It is only necessary to monitor the variation time of the decorative pattern by going and to stop the decorative symbol when it is determined that the variation time has elapsed.

  Preliminary winning opening opening process (step S305): Control for opening the large winning opening is started. Specifically, a counter (for example, a counter that counts the number of game balls that have entered the grand prize opening) and a flag (a flag used when detecting winning in the prize opening) are initialized, and the solenoid 21 is driven. Open the big prize opening. Also, the process timer sets the execution time of the big prize opening opening process and sets the big hit flag. Then, the internal state (special symbol process flag) is updated so as to shift to step S306.

  Processing for opening a special prize opening (step S306): control for sending a presentation control command for round display of the special prize opening to the sound / lamp control board 80b and conditions for closing the special prize opening (for example, a predetermined number (eg, A process of confirming that 10) gaming balls have won) is performed. When the closing condition for the special prize opening is satisfied, the internal state is updated to shift to step S307.

  Specific area valid time process (step S307): A process of confirming that the big hit gaming state continuation condition is satisfied is performed. If the condition for continuing the big hit gaming state is satisfied and there are still remaining rounds, the internal state is updated to shift to step S305. When all the rounds have been completed, the internal state is updated to shift to step S308. In the case where the V winning area is provided, the presence / absence of the V winning switch is monitored and processing for confirming that the big hit gaming state continuation condition is satisfied is performed.

  Big hit end processing (step S308): Control for causing the effect control means to perform display control for notifying the player that the big hit gaming state has ended. Then, the internal state is updated so as to shift to step S300.

  FIG. 39 is a flowchart showing the start port switch passage process (step S312). In the start port switch passing process, the CPU 56 of the game control microcomputer 560 sets the start winning memory number indicated by the start winning counter (or the start winning memory number stored in the special figure holding memory 570) to 4 which is the maximum value. It is confirmed whether it has reached (step S321). If the start winning memory number has not reached 4, the CPU 56 checks whether or not the number of executions of the timer interrupt process has reached a predetermined number (for example, 2 times) (step S322). Whether or not the number of executions of the timer interrupt process has reached a predetermined number is determined by a flag (start) when the start port switch 14a is determined to be on for two timer interrupts in the switch process (step S21). Judgment is made based on whether or not the mouth switch-on flag is set.

  When the number of executions of the timer interrupt process has reached a predetermined number, the CPU 56 can output the output control signal SC to the random number storage circuit 531 of the specified random number circuit 503 and read the random number storage circuit 531 (enable). The state is controlled (step S323).

  The CPU 56 reads the random R value stored as the random number value from the random value storage circuit 531 of the random number circuit 503 (step S324). Further, the CPU 56 stores the read random R value in the storage area (special symbol determination buffer (special symbol holding memory 570)) corresponding to the value of the start winning memorized number (step S325). When the CPU 56 stores the value of the random R in the buffer area, the CPU 56 stops outputting the output control signal SC to the random value storage circuit 531 and controls the random value storage circuit 531 to be unreadable (disabled) (step). S326). Then, the CPU 56 sets the value of the random R stored in the predetermined buffer area to the head of the empty entry in the special figure reservation memory 570 (step S327), and adds 1 to the count number of the start winning counter, thereby storing the start winning prize memory. The number is incremented by 1 (step S328).

  If the start prize is stored in step S321 but the maximum value of 4 has been reached, and if the number of executions of the timer interrupt process has not reached the predetermined number in step S322, the start port switch passing process is terminated.

  As described above, the timer interrupt process has been executed a predetermined number of times in reading the random R from the random value storage circuit 531 in the starting port switch passing process (that is, continued while the timer interrupt process is executed a predetermined number of times). The random number is read from the random value storage circuit 531 on the condition that the winning detection signal SS is input). Therefore, it is possible to prevent the random number from being read again after the random number is read and before the value of the random number stored in the random value storage circuit 531 is updated. Further, it is possible to prevent a random number having the same value as the random number read from the previous random number value storage circuit 531 from being read again.

  Next, the special symbol normal process (step S300) in the special symbol process will be described. FIG. 40 is a flowchart showing the special symbol normal process. In the special symbol normal process, the CPU 56 of the game control microcomputer 560 can start the variation of the special symbol (for example, when the value of the special symbol process flag is a value indicating step S300). (Step S380), the random R value stored in correspondence with the hold number “1” is read from the special figure hold memory 570 (Step S381). In this case, the CPU 56 decrements the count of the start winning counter by 1 to reduce the number of reserved memories by 1, and the second to fourth entries of the special figure reservation memory 570 (hold numbers “2” to “4”). The value of random R stored in is shifted upward by one entry (step S382).

  Further, the CPU 56 checks whether or not the probability variation flag is set (step S383). That is, the CPU 56 confirms whether or not the gaming state is controlled to the certain change state. When the probability variation flag is not set, the CPU 56 determines that the gaming state is a normal state other than the probability variation state, and is a table used for determining whether or not the display result of the special symbol display device 8 is a jackpot symbol. The normal big hit determination table 571a (see FIG. 18A) is set (step S384). Further, when the probability change flag is set, the CPU 56 determines that the gaming state is a probability change state, and as a table used to determine whether or not the display result of the special symbol display device 8 is a jackpot symbol. A probability change big hit determination table 571b (see FIG. 18B) is set (step S385).

  The CPU 56 determines whether or not the display result of the special symbol display device 8 is a big hit symbol based on the random R value stored in the predetermined buffer area in the start port switch passing process (step S386). In this case, the CPU 56 uses the normal-time big hit determination table 571a set in step S384 or the probability change big hit determination table 571b set in step S385 to determine whether or not to win.

If it is determined that the display result of the special symbol display device 8 is a jackpot symbol, the CPU 56 turns on a jackpot flag indicating that it is a jackpot state (step S387). If it is determined that the display result of the special symbol display device 8 is not to be a big hit symbol, the CPU 56 turns off the big hit flag (step S388). Then, the CPU 56 updates the value of the special symbol process flag to a value corresponding to the special symbol stop symbol setting process (step S389).

  Next, the switch process (step S20) in the timer interrupt process will be described. In this embodiment, when the ON state of the detection signal of each switch related to winning detection or gate passage continues for a predetermined time, it is determined that the switch is surely turned on, and processing corresponding to the switch on is started. FIG. 41 is an explanatory diagram showing each 2-byte buffer formed in the RAM 55 used in the switching process. The previous port buffer is a buffer that stores the previous switch-on / off determination result (for example, 2 ms before). The port buffer is a buffer in which the contents of port 0 inputted this time are stored. The switch-on buffer is a buffer in which the corresponding bit is set to 1 when switch on is detected and the corresponding bit is set to 0 when switch off is detected.

  FIG. 42 is a flowchart illustrating a processing example of the switch processing in step S20 in the game control processing. In the switch process, the game control microcomputer 560 first inputs the data input to the input port 0 (see FIG. 21) (step S101), and sets the input data in the port buffer (step S102).

  Next, the initial value of the weight counter formed in the RAM 55 is set (step S103), and the value of the weight counter is decremented by 1 until the value of the weight counter becomes 0 (steps S104 and S105).

  When the value of the wait counter becomes 0, the data of the input port 0 is input again (step S106), and a logical product is obtained for each bit between the input data and the data set in the port buffer (step S106). S107). Then, the logical product operation result is set in the port buffer (step S108). Of the two input data input from the input port 0 with a time interval of approximately [initial value of weight counter × (processing time of steps S104, S105)] by the processing of steps S103 to S108, both “ Only the bits that are “1” will be “1” in the port buffer. In other words, if the ON state of the switch detection signal continues for a predetermined period [initial value of wait counter × (processing time of steps S104 and S105)], the corresponding bit in the port buffer becomes “1”.

  Further, the game control microcomputer 560 performs exclusive OR for each bit between the data previously set in the port buffer and the data set in the port buffer (step S109). In the result of the exclusive OR operation, the bit corresponding to the switch for which the previous switch-on / off determination result (for example, 2 ms before) and the switch-on / off determination result determined to be on this time are different is “ 1 ”. The game control microcomputer 560 further performs a logical product for each bit between the exclusive OR operation result and the data set in the port buffer (step S110). As a result, of the bits corresponding to the switches for which the previous switch on / off determination result and the switch on / off determination result determined to be on this time are different (according to the exclusive OR operation result), the current on Only the bit corresponding to the switch determined to be (by AND operation) remains as “1”.

  Then, the game control microcomputer 560 sets the logical product calculation result in step S110 in the switch-on buffer (step S111), and sets the contents of the port buffer in which the calculation result in step S108 is set in the previous port buffer. (Step S112).

  With the above processing, among the switches that have been on for a predetermined period of time, the switch on / off determination result of the previous time (for example, 2 ms before) is off, that is, the switch has changed from the off state to the on state. The bit corresponding to the switch is “1” in the switch-on buffer.

  FIG. 43 is a flowchart showing the input data confirmation process. In the input data confirmation processing, the CPU 56 reads the data (input data) of the serial communication circuit 505 (step S581), and exclusives every bit between the input data and the contents of the input data buffer formed in the RAM. A logical sum is taken (step S582). If there is a bit with different logic (meaning “1” or “0”) between the input data and the contents of the input data buffer formed in the RAM, the operation result of 8-bit exclusive OR Does not become 00 (H).

  Then, the CPU 56 determines whether or not the exclusive OR operation result is 00 (H) (step S583). If the calculation result is 00 (H), the process ends. If the calculation result is not 00 (H), the input data is stored in the input data buffer (step S584), and it is confirmed whether error information is included in the input data (data of the received ACK signal) (step S585). . Note that the process of step S585 is a process of determining whether the lower 4 bits of the input data are zero (eg, determining with a zero flag). When error information is included in the input data, an error information flag indicating that the error information is included (set) in the received ACK signal is set (step S586), and the input data is stored in the command buffer. Setting is made (step S587). Then, an effect control command transmission request flag is set (step S588). On the other hand, if no error information is included in the received ACK signal, the error information flag is reset (step S589). When confirming that the effect control command transmission request flag is set in the effect control command control process in step S29, the CPU 56 transmits the contents of the command buffer as an effect control command. Instead of transmitting the effect control command in the effect control command control process, the effect control command may be transmitted immediately instead of setting the effect control command transmission request flag.

  The input data is transmitted to the effect control microcomputer 100 under the condition that the input data of the serial communication circuit 505 is changed by the control as described above. At that time, the game control microcomputer 560 transmits the input data as it is as an effect control command. Therefore, even if there is a lot of information indicated by the signal input to the serial communication circuit 505, the control burden on the game control means is light. However, the input data of the serial communication circuit 505 may be once fetched and the fetched data may be stored in the input data buffer every time.

  In addition, since the effect control command related to the input data is output from the main board 31 on condition that the input data has changed, for example, the effect control command is always transmitted once in a predetermined control period (2 ms interval). Compared to the case where the transmission control command is transmitted, it is difficult to grasp the transmission cycle of the effect control command. That is, it becomes difficult to grasp the cycle of the predetermined control period. In the predetermined control period, the counter value for generating a random number related to the jackpot is updated one by one. Therefore, when the period of the predetermined control period is easily grasped, the timing at which the counter value becomes the predetermined value is easily grasped. Become. Predetermined timing refers to the big hit determination random number when the big hit determination random number is created by software, or when it is configured to determine whether or not to make a probable big hit based on the big hit symbol determination random number For example, the timing coincides with the determination value, the timing when the value of the jackpot symbol determination random number matches the value corresponding to the probability variation symbol, and the like. The fact that the timing at which the value of the counter reaches the predetermined value is easily grasped means that it is easy to receive fraud. In this embodiment, it is possible to make it difficult to receive fraud.

  Next, the input determination process (step S21) in the timer interrupt process will be described. In the input determination process, a prize ball command output counter process table shown in FIG. 44 is used. The prize ball command output counter processing table is set in the ROM 54. The number of processes (“6” in this example) is set at the start address of the prize ball command output counter processing table, and then the switch-on buffer (the one corresponding to input port 0 of the 2-byte switch-on buffer) The lower address, the switch input bit judgment value for each switch of the winning opening that will pay out the winning ball by winning, and the winning ball command output counter are sequentially set corresponding to each switch of the winning opening . The switch input bit determination value is a value corresponding to a bit to which the detection signal of each switch at the input port 0 is input. The upper address of the switch-on buffer is a fixed value (for example, 7F (H)). In the prize ball command output counter processing table, the same data is set in each of the lower addresses of the six switch-on buffers. In this embodiment, the addresses of the ROM 54 and the RAM 55 are designated by 16 bits.

  FIG. 45 is a flowchart showing the input determination process. In the input determination process, the CPU 56 sets the start address of the prize ball command output counter process table in the pointer (step S2111). Then, the data at the address pointed to by the pointer (in this case, the number of processes) is loaded (step S2112). Next, the upper address (8 bits) of the switch-on buffer is set in the upper 1 byte of the 2-byte check pointer (step S2113).

  Then, the pointer value is incremented by 1 (step S2114), and the data of the prize ball command output counter processing table pointed to by the pointer (in this case, the lower address of the switch-on buffer) is set in the lower 1 byte of the check pointer (step S2114). In step S2115, the pointer value is incremented by 1 (step S2116). Next, the address data pointed to by the check pointer, that is, the contents of the switch-on buffer is loaded into the register (step S2117), and the loaded contents and the data of the prize ball command output counter processing table pointed to by the pointer (in this case, the switch input) The logical product with the bit determination value) is calculated (step S2118). As a result, 7 bits other than the bit corresponding to the detection signal of the switch to be inspected become 0 in the register loaded with the contents of the switch-on buffer. Then, the pointer value is incremented by 1 (step S2119).

  If the calculation result in step S2118 is 0, that is, if the detection signal of the switch to be inspected is on (step S2120), the prize ball command output counter pointed to by the pointer (data in the prize ball command output counter processing table) Is loaded (step S2121). Further, the CPU 56 adds 1 to the loaded count value (step S2122).

  Next, the CPU 56 checks whether or not the addition result is 256 (step S2123). If the addition result is not 256 (that is, if it is 255 or less), the CPU 56 stores the addition result in the prize ball command output counter pointed to by the pointer (step S2124). If the addition result is 256, the CPU 56 proceeds to step S2125 without storing the addition result in the prize ball command output counter pointed to by the pointer.

  In this embodiment, the maximum value of each prize ball command output counter is set to 255. Therefore, in the processing of steps S2123 and S2124, the count value of the prize ball command output counter is incremented by 1 each time a winning of a game ball to the prize opening is detected until the count value reaches 255. When the count value reaches 255, the count value of the prize ball command output counter is not updated even if the winning of the game ball to the prize opening is detected.

  In this embodiment, the CPU 56 causes the storage means to store data that can specify the number of prize balls to be paid out by counting up the count value of the prize ball command output counter. For example, the CPU 56 may directly store the number of prize balls to be paid out in a predetermined buffer. Further, the CPU 56 may store data indicating the number of prize balls to be paid out in a predetermined buffer, for example, instead of storing the number of prize balls. In this case, for example, the CPU 56 may perform control such as storing data “01” for the number of winning balls 3 and storing data “02” for the number of winning balls 10.

  In step S2125, the number of processes is reduced by 1, and if the number of processes is not 0, the process returns to step S2114 (step S2126). If the number of processes is 0, the process is terminated.

  Next, the operation of the payout control means (the payout control microcomputer 370) will be described. FIG. 46 is an explanatory diagram showing an example of output port assignment in the payout control means. As shown in FIG. 46, the output port 0 is an output port for outputting a signal of each phase supplied to the payout motor 289 by the stepping motor and a detection signal of the payout number count switch 301. That is, the detection signal of the payout number count switch 301 is output from the output port 0 to the main board 31 via the payout control microcomputer 370. The output port 1 is an output port for outputting each segment of the error display LED 374 using a 7-segment LED.

  Although not shown in FIG. 46, the payout control board 37 is also provided with an output port 3 for outputting an EXS signal and a PRDY signal to the card unit 50.

  FIG. 47 is an explanatory diagram showing an example of bit assignment of input ports in the payout control means. As shown in FIG. 47, a connection confirmation signal from the main board 31 is input to the bit 4. In addition, the detection signals of the ball break switch 187 and the detection signal of the payout motor position sensor 295 are input to the bits 6 and 7, respectively. In addition, the detection signal of the payout number count switch 301, the operation signal from the error release switch 375, and the detection signal of the full switch 48 are input to bits 1 to 3 of the input port 1, respectively. The VL signal, the BRDY signal, and the BRQ signal from the card unit 50 are input to bits 4 to 6 of the input port 1, respectively.

  Next, the operation of the payout control means will be described. FIG. 48 is a flowchart showing main processing executed by the payout control means. In the main process, the payout control CPU 371 of the payout control microcomputer 370 first performs necessary initial settings. That is, the payout control CPU 371 first sets the interruption prohibition (step S701). Next, the interrupt mode is set to interrupt mode 2 (step S702), and a stack pointer designation address is set to the stack pointer (step S703). The payout control CPU 371 sets the internal device register (step S704), sets the CTC and PIO (step S705), and then sets the RAM in an accessible state (step S706). Further, 0000 (H) is set as an initial value of the award ball unpaid number counter (step S707).

  In this embodiment, one channel of the built-in CTC is used in the timer mode. Accordingly, in the built-in device register setting process in step S704 and the process in step S705, register setting for setting the channel to be used to timer mode, register setting for permitting interrupt generation, and setting an interrupt vector. The register is set. The interrupt by the channel is used as a timer interrupt. For example, when it is desired to generate a timer interrupt every 2 ms, a value corresponding to 2 ms is set as an initial value in a predetermined register (time constant register).

  The interrupt vector set for the channel set to the timer mode (channel 3 in this embodiment) corresponds to the start address of the timer interrupt process. Specifically, the start address of the timer interrupt process is specified by the value set in the I register and the interrupt vector. In the timer interruption process, a payout control process for controlling the payout means (including at least a process of driving the ball payout device 97 in response to a command signal related to award ball payout from the main board, and a ball payout device 97 in response to a ball lending request. A process for driving the program may be included.

  In this embodiment, the interruption mode 2 is also set in the payout control microcomputer 370. Therefore, an interrupt process based on counting up the built-in CTC can be used. Also, an interrupt processing start address can be set according to the interrupt vector sent by the CTC. The interrupt based on CTC channel 3 (CH3) count-up is an interrupt that occurs when the CPU internal clock (system clock) counts down and the register value becomes “0”, and is used as a timer interrupt. .

  Next, the payout control CPU 371 first performs a RAM clear process (step S712). In addition, initial values are set in the flags and counters of the RAM area (step S713). The process of step S713 includes a process of setting an initial value of the award ball unpaid number counter in the award ball unpaid number counter.

  Also, the payout control CPU 371 executes serial communication circuit setting processing for initial setting of the serial communication circuit 380 (step S713a). In this case, the payout control CPU 371 causes the serial communication circuit 380 to serially communicate with the game control microcomputer 560 according to the same process as the serial communication circuit setting process (see step S15a) performed by the CPU 56 of the game control microcomputer 560. Make settings for

  When the serial communication circuit 380 is initialized, the payout control CPU 371 initializes the priority of interrupt processing executed in response to the interrupt request from the serial communication circuit 380 (step S713b). In this case, in this case, the payout control CPU 371 initializes the priority order of the interrupt process according to the same process as the priority order initial setting process (see step S15b) performed by the CPU 56 of the game control microcomputer 560.

  Then, the CTC register provided in the payout control microcomputer 370 is set so that a timer interrupt is periodically generated (step S714). That is, a value corresponding to the timer interrupt generation interval is set as an initial value in a predetermined register (time constant register). Since interruption is prohibited in step S701 of the initial setting process, interruption is permitted before the initialization process is completed (step S715). Thereafter, a loop process for monitoring the occurrence of a timer interrupt is entered.

  As described above, in this embodiment, the built-in CTC of the payout control microcomputer 370 is set so as to repeatedly generate a timer interrupt. When a timer interrupt occurs, the payout control CPU 371 of the payout control microcomputer 370 executes a timer interrupt process.

  FIG. 49 is a flowchart showing an example of timer interruption processing executed by the payout control means. In the timer interruption process, the payout control CPU 371 of the payout control microcomputer 370 executes the following process as the payout control process. First, the payout control CPU 371 performs an input determination process (step S751). In the input determination process, the states of bits 4 to 6 of input port 0 and bits 3 to 6 of input port 1 (see FIG. 47) are detected, and the detection result is a predetermined 1 byte of RAM (referred to as an input state flag). It is a process to reflect on. In the payout control process, when control is performed based on the states of bits 4 to 6 of input port 0 and bits 3 to 6 of input port 1, the state of the input port is not directly checked, but the input state is checked. Check the status of the flag.

  Next, the payout control CPU 371 executes a payout motor control process (step S753). In the payout motor control process, when the payout motor 289 is to be driven, a process for outputting the patterns of the payout motors φ1 to φ4 to the output port 0 is performed.

  Also, the payout control CPU 371 executes a prepaid card unit control process for communicating with the card unit 50 (step S754). Further, a prize ball lending control process for performing a control for paying out a lending ball in response to a ball lending request from the card unit 50, and for performing a control for paying out the number of award balls indicated by a prize ball number command from the main board. Is executed (step S756).

  Then, the payout control CPU 371 executes error processing for detecting various errors (step S757). Further, an information output process for outputting prize ball information and ball lending information output to the outside of the gaming machine is executed (step S758). Further, a predetermined display is performed on the error display LED 374 according to the result of the error processing, and a display control process for lighting the prize ball LED 51 and the ball out LED 52 is executed (step S759).

  In the present embodiment, when various errors (for example, a full tank error, a ball shortage error, and a prepaid card unit unconnected error) are detected in error processing described later, an error bit corresponding to the detected error is set. Then, in the display control processing in step S759, the payout control CPU 371 performs a predetermined display on the error display LED 374 based on the error bit being set. Also, the payout control CPU 371 performs control for lighting the prize ball LED 51 when the prize ball is being paid out in the display control process. When the prize ball payout is completed, control for turning off the prize ball LED 51 is performed.

  In this embodiment, a RAM area (output port 0 buffer, output port 1 buffer, output port 2 buffer) corresponding to the output state of the output port is provided. The contents of the port 0 buffer, output port 1 buffer, and output port 2 buffer are output to the output port (step S760: output processing). The output port 0 buffer, the output port 1 buffer, and the output port 2 buffer are a payout motor control process (step S753), a prepaid card control process (step S754), a main control communication process (step S755), and an information output process (step S758). And updated in the display control process (step S759).

  Next, an operation in which the payout control CPU 371 of the payout control microcomputer 370 transmits and receives various commands in the main control communication process in step S755 will be described. As shown in FIG. 28, the payout control microcomputer 370 includes a serial communication circuit 380 for serially communicating various commands with the game control microcomputer 560. The payout control microcomputer 370 uses the serial communication circuit 380 to receive the prize ball number command shown in FIG. 27 from the game control microcomputer 560. When the prize ball number command is received, the payout control microcomputer 370 uses the serial communication circuit 380 to transmit the prize ball ACK command “D2” shown in FIG. 27 as a reception confirmation signal.

  Similarly to the CPU 56 of the game control microcomputer 560, when the payout control CPU 371 receives an interrupt request from the serial communication circuit 380 while it is in the interrupt enabled state, the interrupt that the serial communication circuit 380 has issued an interrupt request for. Performs interrupt processing according to the cause. In this embodiment, when the CPU 371 for payout control specifies that the cause of the interruption is that the serial communication circuit 380 has received the received data, the payout control CPU 371 executes an interruption process upon reception. In this case, the payout control CPU 371 sets a reception interrupt flag indicating that the serial communication circuit 380 is receiving reception data. The payout control CPU 371 may read data from the reception data register of the serial communication circuit 380 instead of setting the reception interrupt flag in the reception interrupt processing. In this case, for example, the payout control CPU 371 determines whether or not the received data read is a prize ball number command in the interruption process during reception. If the received data is a prize ball number command, the payout control CPU 371 may add the number of prize balls indicated by the prize ball number command to the prize ball unpaid number counter. By doing so, in the main control communication process described later, it is determined whether or not the received data is a prize ball number command based on the reception interrupt flag being set (steps S542 to S545 described later). It is not necessary to carry out the process of adding the number of prize balls to the prize ball unpaid number counter (see step S546 described later).

  FIG. 50 is a flowchart showing main control communication processing in which the payout control CPU 371 of the payout control microcomputer 370 communicates with the game control means (game control microcomputer 560) of the main board 31. The main control communication process is a command reception interrupt process (of the serial communication circuit 380) based on the reception of a command (connection confirmation command or prize ball number command as a prize ball request signal) from the game control microcomputer 560. This is executed as a process within an interrupt process based on a receive interrupt, which is an internal interrupt that occurs when data is stored in the receive data register. However, the main control communication process may be executed as a process in the timer interrupt process.

  In the main control communication process, the payout control CPU 371 checks whether or not the connection confirmation signal is on (step S541). Note that the connection confirmation signal being in the on state means that power is supplied and the game control means can control the progress of the game, and that the connection confirmation signal is in the off state means This means that the supply stop process is started and the game control means cannot progress the game (the connection confirmation signal is turned off by the output port clear process in the power supply stop process).

  The payout control CPU 371 reads data from the reception data register that stores the data received by the serial communication circuit 380 (step S542). Then, the payout control CPU 371 confirms whether or not a connection confirmation command as a prize ball request signal has been received (step S543). When the connection confirmation command is received (the data read from the reception data register is a connection confirmation command). If there is (Yes in Step S543), the upper 4 bits of the connection OK command are set in a predetermined data storage area of the RAM 55 (Step S547). Also, when a prize ball error, a full tank error, a full ball error, or a door open error occurs, that is, in the error processing of FIGS. 58 and 59, a prize ball error flag, a full tank error flag, a full ball error flag, or a door open error. When the flag is set (Y in step S548), error information is added to the data of the connection OK command. Specifically, information indicating an error state (error information) is set in the lower 4 bits of the connection OK command (step S549). When no prize ball error, full tank error, ball run-out error, or door opening error has occurred (N in step S548), “0000” is set in the lower 4 bits of the connection OK command. Then, the upper 4 bits of the connection OK command set in the predetermined data storage area in step S547 and the lower 4 bits of data of the connection OK command (data indicating error information or “0000” data) are transmitted data. By writing to the register, the connection OK command is transmitted to the game control microcomputer 560 (step S552).

  When the connection confirmation command has not been received (N in step S543), the payout control CPU 371 checks whether or not the prize ball payout operation has been completed (step S544). Whether or not the winning ball payout operation has ended can be determined by checking a flag (payout end flag) that is set when a series of payout processing ends. If the winning ball payout operation has ended (Y in step S544), the payout control CPU 371 writes the winning ball end command data in the transmission data register (step S550). Note that the payout end flag is reset before (or after) executing the process of step S550. The payout end flag is set when the number of unpaid becomes 0 as a result of the payout process (Y in step S654).

  If the winning ball payout operation has not ended (N in step S544), the payout control CPU confirms whether or not the winning ball payout operation is in progress (step S545). In step S545, the upper 4 bits of the winning ball preparation command are set in a predetermined data storage area of the RAM 55 (step S551). Also, when a prize ball error, full tank error, out of ball error or door open error occurs, that is, when the prize ball error flag, full tank error flag, out of ball error flag or door open error flag is set (step In step S548, Y), error information is added to the data of the command for preparing a prize ball. Specifically, information indicating the error state (error information) is set in the lower 4 bits of the winning ball preparation command (step S549). When no prize ball error, full tank error, ball run-out error, or door opening error has occurred (N in step S548), “0000” is set in the lower 4 bits of the connection OK command. Then, the upper 4 bits of the winning ball preparation command set in the predetermined data storage area in step S551 and the lower 4 bits of data of the winning ball preparation command (data indicating error information or “0000” data). ) Is written in the transmission data register, a command for preparing a prize ball is transmitted to the game control microcomputer 560 (step S552).

  If the winning ball payout operation is not in progress (N in step S545), the payout control CPU 371 adds the number indicated by the winning ball number command to the award ball unpaid number counter (step S546). Then, the upper 4 bits of the connection OK command are set in a predetermined data storage area of the RAM 55 (step S547). Also, when a prize ball error, full tank error, out of ball error or door open error occurs, that is, when the prize ball error flag, full tank error flag, out of ball error flag or door open error flag is set (step In step S548, Y), error information is added to the data of the connection OK command. Specifically, information indicating an error state (error information) is set in the lower 4 bits of the connection OK command (step S549). When no prize ball error, full tank error, ball run-out error, or door opening error has occurred (N in step S548), “0000” is set in the lower 4 bits of the connection OK command. Then, the upper 4 bits of the connection OK command set in the predetermined data storage area in step S547 and the lower 4 bits of data of the connection OK command (data indicating error information or “0000” data) are transmitted data. By writing to the register, the connection OK command is transmitted to the game control microcomputer 560 (step S552).

  When error information is set in the connection OK command or the winning ball preparation command, the error information notified to the game control microcomputer 560 side when the error bit is set in the error processing shown in FIGS. 4 bits in the 1-byte area are set to the corresponding bits. As a result, the 4 bits can be set as the lower 4 bits of the command to be transmitted to the game control microcomputer 560 as it is.

  FIG. 51 is a flowchart showing the winning ball lending control process in step S756. In the winning ball lending control process, the payout control CPU 371 confirms that the detection signal of the payout number count switch 301 is turned on (step S601). The value is decremented by 1 (steps S602 and S604), and if the ball is not being lent, the value of the unpaid prize ball counter is decremented by 1 (steps S602 and S603). When the value of the award ball unpaid number counter is decremented by 1, the detection signal of the number-of-payout count switch 301 is transferred (output) to the main board 31 (step S603a).

  Next, the payout ball detection bit of the payout control state flag formed in the RAM is set (step S605). The payout ball detection bit is a game regardless of whether the payout motor 289 is driven during one award ball payout process (maximum 15 balls) or one ball lending process (25 payouts) in the payout passing waiting process. This is used to detect that no sphere has passed through the payout number counting switch 301. Thereafter, any one of steps S610 to S612 is executed according to the value of the payout control code.

  In the winning ball lending control process, when checking the detection signal of the payout number count switch 301 or subtracting the unpaid number counter, the error bit check is not executed. Accordingly, even if an error state relating to the payout of game balls is detected, every time a payout of game balls is detected by the payout number count switch 301, if the payout game balls are loaned balls, a ball rental unpaid number counter 1 is subtracted, and if it is a prize ball, a process of subtracting 1 from the prize ball unpaid number counter is executed. Therefore, even if an error related to payout occurs, the number of unpaid game balls can be managed accurately. That is, a game ball paid out from the ball payout device 97 before the payout control CPU 371 of the payout control microcomputer 370 detects the occurrence of an error is delayed by the payout count switch 301 slightly after the payout time. As detected, the payout control CPU 371 detects the occurrence of an error after the game ball is paid out from the ball payout device 97 and before the game ball is detected by the payout number count switch 301. In this case, the game balls paid out from the ball payout device 97 before detecting the occurrence of the error can be reflected in the award ball unpaid number counter or the ball lending unpaid number counter.

  FIG. 52 is a flowchart showing the payout start waiting process (step S610) executed when the payout control code is 0. In the payout start waiting process, the payout control CPU 371 executes a process for paying out a prize ball after step S631 if the BRDY signal is not on (step S621). However, if the error bit is set, the processing after step S631 is not executed (step S622). The error bit in the error flag includes a main board non-connection error bit, a prize ball error (payout switch error detection error 1, payout switch error detection error 2, payout case error, prepaid card unit unconnected error, prepaid card unit communication error. ) Bit, full error bit, out of ball error bit, door open error bit. The main board non-connection error is set when the connection confirmation signal from the main board 31 is in the OFF state. Accordingly, the payout control CPU 371 starts substantial control on condition that the connection confirmation signal is turned on after power supply to the gaming machine is started. The fact that the connection confirmation signal is in the on state means that power supply is performed and the game control means can control the progress of the game, so that the payout control of the prize ball according to the progress of the game can be executed. means. On the other hand, the fact that the connection confirmation signal is in an off state means that the power supply is stopped and the game control means cannot advance the game, so that the award ball payout control according to the progress of the game cannot be executed. It means that there is. Accordingly, the payout control CPU 371 stops payout control of the winning ball when the main board non-connection error bit is set. On the other hand, in this example, the lending ball payout control is executed without checking the error bit, and the lending control is continuously performed even if the main board unconnected error bit is set. .

  If the BRDY signal is on and the BRQ signal that is a ball lending request signal is on (step S623), the payout control CPU 371 checks whether the VL signal is on. (Step S623a). If the VL signal is on, the payout control CPU 371 sets a ball lending operation in progress flag (step S624). Then, “25” is set in the unpaid ball lending number counter (step S625), and “25” is set in the payout motor rotation number buffer (step S626). If the VL signal is not on in step S623a, the payout control CPU 371 proceeds to step S622 without performing the processes in and after step S624.

  The payout motor rotation frequency buffer is referred to in the payout motor control process (step S753). That is, in the payout motor control process, control is performed to rotate the payout motor 289 by the number of rotations corresponding to the value set in the payout motor rotation frequency buffer.

  Thereafter, the payout control microcomputer 370 sets a value (specifically “1”) corresponding to the payout motor start preparation process (step S522) as the payout motor control code for selecting the process executed in the payout motor control process. ) Is set (step S627), the value of the payout control code is set to 1 (step S628), and the process is terminated.

  In step S631, the payout control CPU 371 checks whether or not the value of the award ball non-payout counter is 0 (step S631). If 0, the process ends. If the value of the award ball unpaid number counter is not 0, it is confirmed whether it is 15 or more (step S632). If it is less than 15, the value of the award ball unpaid number counter is set in the payout motor rotation count buffer (step S633), and if it is 15 or more, “15” is set in the payout motor rotation count buffer. Then, a winning ball operating flag is set (step S635), and the process proceeds to step S627.

  FIG. 53 is a flowchart showing a payout motor stop waiting process (step S611) executed when the payout control code is 1. In the payout motor stop waiting process, the payout control CPU 371 checks whether or not the payout operation is completed (step S641). For example, when the payout motor brake process (step S525) in the payout motor control process is completed, the payout control CPU 371 completes the flag (specifically, the rotation speed buffer becomes 0 and the drive control of the payout motor ends. It is possible to confirm whether or not the payout operation has ended by checking the flag in step S641.

  When the payout operation is completed, the payout control CPU 371 sets the payout passing monitoring time in the payout control monitoring timer (step S642). The payout passing monitoring time is a time that has a margin in the time from when the last payout ball is paid out by the payout motor 289 until it passes through the payout number count switch 301. Then, the value of the payout control code is set to 2 (step S643), and the process ends.

  54 to 56 are flowcharts showing a payout passing waiting process (step S612) executed when the value of the payout control code is 2. In the payout passing waiting process, when a prize ball is being paid out, it is determined that the payout has been completed normally if the value of the prize ball unpaid number counter is zero. If the value of the award ball unpaid out counter is not 0, if it is not in an error state, a re-payout operation of one game ball is tried up to 2 times. In the re-payout operation, when it is detected by the payout number count switch 301 that the game ball is actually paid out, it is determined that the payout has been completed normally. In this embodiment, the maximum number of game balls to be paid out in one prize ball payout operation is 15, and if a prize ball number command is received during the prize ball payout, the value of the prize ball unpaid number counter is received. Therefore, even when the payout is completed normally, the value of the award ball non-payout number counter may not be 0.

  Further, when the ball lending is being paid out, it is determined that the payout has been completed normally if the value of the ball lending unpaid-out counter is 0. If the value of the ball lending unpaid number counter is not 0, and if it is not in an error state, a re-payout operation of one game ball or the remaining number of ball lending (corresponding to the value of the ball lending unpaid number counter) Try. In this embodiment, the number of game balls to be paid out in one ball lending and payout operation is 25 (fixed value), and the payout motor 289 is rotated so that 25 game balls are paid out. Therefore, when the value of the unpaid ball lending counter is not 0, the payout has not been completed normally.

  In the payout waiting process, the payout control CPU 371 first checks the value of the payout control timer, and if the value is 0, the process proceeds to step S653 (step S650). If the value of the payout control timer is not 0, the value of the payout control timer is decremented by 1 (step S651). If the value of the payout control timer is not 0 (step S652), that is, if the payout control timer has not timed out, the process is terminated. Note that the process of step S650 is a process that takes into account when a game ball payout retry operation to be described later is started. When the process of step S807 described later is executed, a retry operation is started through a route that moves from step S650 to S653.

  If the payout control timer has timed out (step S652), it is confirmed whether or not the ball lending payout process (ball lending operation) has been executed (step S653). Whether or not the ball lending operation has been executed is confirmed by whether or not the ball lending operation bit in the payout control state flag formed in the RAM is set (see steps S623 and S624). When the ball lending operation is not executed, that is, when the prize ball payout process (prize ball operation) is executed, the payout control CPU 371 checks the value of the award ball unpaid number counter (step S654). ). When the value of the award ball unpaid number counter is 0, it is determined that the prize ball payout process has been completed normally, and the payout ball detection bit in the payout control state flag, 1 bit during re-payout operation, and during re-payout operation 2 bits, the winning ball operating flag and the ball lending operating bit are reset (step S655), the payout control code is set to 0 (step S656), and the process is terminated. This bit is set when the switch 301 is turned on, and indicates that the payout number counting switch 301 has detected at least one game ball during the payout operation. Further, 1 bit during the re-payout operation and 2 bits during the re-payout operation are control bits used when executing a re-payout process including two re-payout operations.

  The payout control CPU 371 determines that an error flag (specifically, a payout switch error error 1 bit, a payout switch error error 2 bit, and a payout case error bit when the value of the award ball unpaid number counter is not 0. The re-payout operation is executed on the condition that any one or a plurality of bits) is not set (step S659) and on the condition that the payout ball detection bit is not set (step S661). To do. If the error flag is set, the re-payout operation is not executed.

  As described above, in this embodiment, even when the payout is completed normally, the value of the unpaid prize ball number counter may not be 0. Therefore, if the payout ball detection bit is set, that is, if the payout number count switch 301 detects the payout of at least one game ball during the prize ball payout process, it is assumed that the prize ball payout process is normally completed. The process proceeds to step S655. For example, when 15 game balls should be paid out in one prize ball payout process, when only 14 game balls are actually paid out (the number of payout count switch 301 is 14 game balls). In this case, the payout ball detection bit is set, so it is considered that the award ball payout process has been completed normally. It should not have been done, and the shortage will be paid out in the next prize ball payout process, so there will be no disadvantage to the player. The winning ball payout operation of the main control communication process (FIGS. 36 and 37) is completed based on the flag set only when the value of the winning ball payout counter becomes 0 (Y in step S654). (See step S544) or a determination during a prize ball payout operation (see step S545). In this case, a prize ball preparing command is output to the game control microcomputer 560 until an unpaid prize ball is completely paid out (including a case where a re-payout process is executed). According to such a configuration, a prize ball number command is not transmitted from the game control microcomputer 560 side in a state in which an abnormality may occur even a little, so that a player's disadvantage (for example, a prize ball) The prize ball number command is sent during the payout operation, and the value specified in the prize ball number command is set in the unpaid prize ball number counter. However, the value of the unpaid prize ball number counter is cleared due to power failure. Therefore, a disadvantage that a prize ball that should be paid out is not paid out can be prevented.

  In order to execute the re-payout process, the pay-out control CPU 371 first checks whether or not 2 bits during re-payout operation are set (step S662). If not set, it is confirmed whether or not 1 bit is set during the re-payout operation (step S663). If 1 bit is not set during the re-payout operation, 1 is set as the number of re-payout operations to execute the first re-payout operation (step S664), and 1 bit is set during the re-payout operation (step S665). ) The value of the re-payout operation number or the ball lending unpaid-out number counter is set in the payout motor rotation number buffer (step S666). Further, the payout control CPU 371 sets a value (specifically “1”) corresponding to the payout motor activation preparation process (step S522) to the payout motor control code for selecting the process executed in the payout motor control process. set. The payout motor rotation frequency buffer is referred to in the payout motor control process (step S753). That is, in the payout motor control process, control is performed to rotate the payout motor 289 by the number of rotations corresponding to the value set in the payout motor rotation frequency buffer. In step S666, the value of the unpaid ball lending number counter is also handled because step S666 is used in the re-payout process in the lend-out process. That is, in step S666, the payout control CPU 371 sets the re-payout operation number in the re-payout process in the prize ball payout process, and sets the value of the ball lending unpaid-out number counter in the re-payout process in the ball lending payout process. . Thereafter, the payout control code is set to 1 (step S667), and the process is terminated. Even when the error state is set due to the occurrence of an error twice, the error state is automatically canceled after a predetermined period (for example, 120 seconds) and the retry operation (re-payout process) is resumed. It may be configured.

  In step S663, when it is confirmed that 1 bit is set during the re-payout operation, the payout control CPU 371 sets 1 as the re-payout operation number in order to execute the second re-payout (step S668). Then, 1 bit is reset during the re-payout operation (step S669), and 2 bits are set during the re-payout operation (step S670). Then, control goes to a step S666.

  When it is confirmed in step S662 that 2 bits are set during the re-payout operation, the payout control CPU 371 does not pay out the game ball even if the re-payout process is executed twice (payout number count switch). 301 has not detected a game ball), a payout case error bit in the error flag is set (step S672). At that time, 2 bits are reset during the re-payout operation (step S671). Then, the process ends.

  As described above, if no game balls are paid out even if two re-payout operations are performed in the re-payout process (corrected payout process), it is assumed that the game ball payout operation is defective and the payout number count switch is not A passing error bit (payout case error bit) is set.

  Therefore, in this embodiment, the prize game medium payout control means in the payout control microcomputer 370 does not pay out the prize game medium based on the detection signal from the payout number count switch 301 as the payout detection means. When this is detected, control is performed so that the payout means pays out one prize game medium up to a predetermined number of times (in this example, twice). In this embodiment, if the prize game medium is not paid out even if the retry operation for paying out the prize game medium is performed twice, the payout case error bit is set and an error is being generated. (Step S672), the payout case error bit may be set when it is first detected that the premium game medium has not been paid out. Note that “retry operation (or“ retry ”,“ retry operation processing ”) means that the actual number of payouts is equal to the number of game balls paid out in spite of execution of a normal payout process. This is an operation to be executed when the amount is small, and means an operation for executing the payout process again in order to pay out unpaid game balls separately from the normal payout process.

  In the prize ball lending control process, the error bit is checked to determine whether or not to perform a payout operation (one prize ball payout or one ball lending). The payout start shown in FIG. Only in the waiting process. In the payout motor stop waiting process shown in FIG. 51 and the payout passing wait process shown in FIG. 52 and the like, the error bit is not checked. Note that the error bit is also checked in step S659 or the like in the payout passing waiting process, but this check is for determining whether or not a re-payout operation is performed, and is a payout operation (single prize ball payout or 1 This is not to determine whether or not to start ball lending. Therefore, after the process of step S626, S633, or step S634 is performed and the game ball payout process is started, the payout process is not interrupted even if an error occurs. In other words, when an error occurs, the game ball payout process is continued until a point at which the game ball can be cut well (at the time when one prize ball payout or one ball lending ends). The error bits in the error flag checked in step S621 include an error bit indicating that the connection confirmation signal from the main board 31 has been turned off. Therefore, even when the connection confirmation signal is turned off, the game ball payout process is stopped at a time when it is best to turn it off. If an error occurs even after the game ball payout process is started after the process of step S626, S633 or step S634 is performed, instead of continuing the game ball payout process until a good point is reached. The game ball payout process may be stopped immediately.

  Upon confirming that the ball lending / dispensing process (ball lending operation) has been executed in step S653, the payout control CPU 371 confirms whether or not the value of the ball lending unpaid out counter is 0 (step S657). . If it is 0, it is determined that the ball lending / dispensing process is normally completed, and the process proceeds to step S655.

  In step S657, if the value of the ball lending unpaid number counter is not 0, an error flag (specifically, any one of the payout switch abnormal error 1 bit, the payout switch abnormal error 2 bit, and the payout case error bit) Or one bit or a plurality of bits) is not set (step S675), the re-payout process is executed. If the error flag is set, the re-payout process is not executed.

  In order to execute the re-payout process, the pay-out control CPU 371 first checks whether or not 2 bits during re-payout operation are set (step S676). If not set, it is confirmed whether or not 1 bit is set during the re-payout operation (step S677). If 1 bit is not set during re-payout operation, 1 is set as the number of re-payout operations to execute the first re-payout operation (step S678), and 1 bit is set during re-payout operation (step S679). ) After further resetting the payout ball detection bit (step S680), the process proceeds to step S666.

  In step S677, when it is confirmed that 1 bit is set during the re-payout operation, the payout control CPU 371 performs a process for re-executing the re-payout operation. Specifically, 1 bit is reset during the re-payout operation (step S681). If the payout ball detection bit is set, that is, if the game ball is paid out in the first re-payout operation, the process proceeds to step S683. If the payout ball detection bit is not set, the process proceeds to step S684 to execute the second re-payout operation.

  In step S683, the payout ball detection bit is reset, and then the process proceeds to step S666. Therefore, in this case, since 1 bit remains set during the re-payout operation, the first (first) re-payout operation is performed again. In step S684, 1 is set as the number of re-payout operations (step S684), 2 bits during re-payout operation are set (step S685), and the process proceeds to step S666.

  In step S676, when it is confirmed that the 2 bits during re-payout operation are set, the payout control CPU 371 resets 2 bits during the re-payout operation (step S686), and if the payout ball detection bit is set, That is, if the game ball is paid out by the re-payout operation, the process proceeds to step S683 to try to eliminate the remaining unpaid out. If the payout ball detection bit is not set, it is determined that the game ball has not been paid out even if the re-payout process is executed twice (the payout number count switch 301 has not detected a game ball). A payout case error bit is set (step S688). Then, the process ends.

  As described above, if one game ball is not paid out even if two re-payout operations are continuously performed in the re-payout process (corrected payout process) related to the ball lending process, a game ball payout operation is performed. As a failure, a payout count switch non-passing error bit (payout case error bit) is set.

  Next, error processing will be described. FIG. 57 is an explanatory diagram showing the relationship between the type of error and the display of the LED 374 for error display. As shown in FIG. 57, when the connection confirmation signal from the main board 31 is turned off, the payout control CPU 371 of the payout control microcomputer 370 displays an error display LED 374 as a main board non-connection error. Control to display “1” is performed. Therefore, when the connection confirmation signal is turned off while the input state of the connection confirmation signal is being confirmed, “1” is displayed on the error display LED 374.

  When the disconnection of the payout count switch 301 or a ball clogging occurs at the payout count switch 301, the error display LED 374 is controlled to display “2” as the payout switch abnormality detection error 1. The disconnection of the payout number count switch 301 or the occurrence of ball clogging in the payout number count switch 301 is determined by the detection signal of the payout number count switch 301 not being turned off.

  When the detection signal of the payout number count switch 301 is turned on even though the game ball is not paying out, a control for displaying “3” on the error display LED 374 as a payout switch abnormality detection error 2 is performed. Do. If the detection signal of the payout count switch 301 does not turn on despite the rotation abnormality of the payout motor 289 or the game ball being paid out, “4” is displayed on the error display LED 374 as a payout case error. Control. The specific method for detecting that the detection signal of the payout number count switch 301 is not turned on is as described above.

  In addition, when the lower pan is full, that is, when the full switch 48 is turned on, control is performed to display “5” on the error display LED 374 as a full error. When the supply ball is insufficient, that is, when the ball break switch 187 is turned on, control is performed to display “6” on the error display LED 374 as a ball break error.

  Further, when the VL signal from the card unit 50 is turned off, control is performed to display “7” on the error display LED 374 as a prepaid card unit non-connection error. When communication with the card unit 50 is performed at an improper timing, control is performed to display “8” on the error display LED 374 as a prepaid card unit communication error. The prepaid card unit communication error is detected in the prepaid card unit control process (step S754).

  Among the above errors, after the occurrence of a payout switch abnormality detection error 2, a payout case error, an excessive prize ball error error or an excessive prize ball error error, the error release switch 375 is operated and an operation signal is output from the error release switch 375. If it becomes (on state), the payout control means returns to the state before the error occurred.

  As already described, the payout control CPU 371 specifically displays an error on the error display LED 374 in accordance with the relationship shown in FIG. 57 in the display control process of the timer interrupt process (see step S759). For example, the payout control CPU 371 indicates that a prepaid card unit unconnected error has occurred in the display control process based on the setting of the prepaid card unit unconnected error bit in an error process described later (see step S826). Is displayed on the error display LED 374. Further, for example, based on the fact that the full error bit is set in the error processing (see step S809), an error display “5” indicating that a full error has occurred in the display control processing is displayed on the error display LED 374. Control the display.

  58 and 59 are flowcharts showing the error processing in step S757. In the error processing, the payout control CPU 371 checks the error flag, and the set bits are only the payout switch abnormality detection error 2 and the payout case error (only one of the two bits, or 2 It is confirmed whether or not (only bit) (step S801). If only those bits are set, it is confirmed whether or not the operation signal is turned on from the error release switch 375 (step S802). When the operation signal is turned on, the error recovery time is set in the pre-error recovery timer (step S803). The error recovery time is the time from when the error release switch 375 is operated until the actual return from the error state to the normal state.

  If the operation signal from the error release switch 375 is not on, the value of the timer before error recovery is confirmed (step S804). If the value of the timer before error recovery is 0, that is, if the timer before error recovery is not set, the process proceeds to step S808. If the pre-error recovery timer is set, the value of the pre-error recovery timer is decremented by -1 (step S805). The bits of the abnormality detection error 2 and the payout case error are reset (step S807), and the process proceeds to step S808.

  When the processing of step S807 is executed, there may be an error bit that is not in the set state among the payout switch abnormality detection error 2 and payout case error bits. There is no problem with resetting. As described above, in this embodiment, when an error (see FIG. 57) that causes the setting of the payout switch abnormality detection error 2 or the payout case error bit occurs, the error release switch 375 is pressed. The error is canceled.

  When the process of step S807 is executed and the payout case error bit is reset, the payout control code is “2” (corresponding to the execution of the payout passing waiting process shown in FIGS. 54 to 56), and the prize ball When the value of the unpaid-out number counter or the value of the ball-lending unpaid-out number counter is not 0, a retry operation for game ball payout is started. That is, when the award ball lending control process of step S756 is executed next, when the payout passing waiting process of step S612 is executed, the repayment process is performed again. For example, if a prize ball payout process has been performed and the value of the prize ball unpaid number counter is not 0, the process proceeds from step S654 to step S659, and it is confirmed in step S659 that the error bit is in a reset state. Therefore, the process for starting the re-payout process after step S662 is executed again, and the re-payout process is executed. Regarding the payout case error bit reset by pressing the error release switch 375, when the bit is set (when step S672 is executed), the payout control timer has already expired. Therefore, when the process in step S807 is executed and the payout case error bit is reset, the payout control timer = 0 is determined in the determination in step S650 when the payout passage waiting process is executed next. Further, when the payout case error bit is set, the payout ball detection bit is 0 (since step S672 is not executed unless the payout ball detection bit is 0 according to the determination in step S661). Therefore, step S662 is always executed whenever it is confirmed in step S659 that the error bit is in the reset state. That is, the re-payout process is always executed.

  As described above, the payout control means is used to pay out a game ball when the payout number count switch 301 detects no game ball even though the ball payout device 97 pays out a game ball. After performing the correct payout control for causing the ball payout device 97 to execute the retry operation for a predetermined number of times (for example, twice) as a limit, the payout number count switch 301 has detected no game balls. When it is detected (see step S661 and subsequent steps in FIG. 55), the control state related to payout is shifted to an error state, and corrected payout control is performed again on condition that an error release signal is output from the error release switch 375 in the error state. A correction payout control restart process for executing

  Further, even during re-payout processing in an error state (specifically, during re-payout processing before setting a payout case error and during re-payout processing after the error release switch 375 is pressed), steps S601 to S601 shown in FIG. The process of S604 is being executed. That is, even when an error relating to payout occurs, if the game ball passes the payout number count switch 301, the value of the award ball unpaid number counter or the ball lending unpaid number counter is subtracted. Therefore, the value of the award ball unpaid number counter or the ball lending unpaid number counter when returning from the error state is a value reflecting the number of game balls actually paid out. That is, even if an error related to payout occurs, the number of game balls actually paid out can be accurately managed.

  In the payout waiting process shown in FIGS. 54 to 56, the payout case error bit is not reset even when it is confirmed that the game ball has been paid out as a result of the re-payout process. The bit of the payout case error is reset only when the error release switch 375 is operated (specifically, when an error return time after operation has elapsed) (steps S802 and S807). That is, the payout case error (payout shortage error) state is not automatically canceled based on the fact that the game ball has passed the payout number count switch 301, etc., and the payout case must be processed without human operation. The error is not cleared. Therefore, the game store clerk and the like can surely recognize that a shortage of payout has occurred.

  When the error cancel switch 375 is operated so as to be reset in hardware (reset to the payout control CPU 371), the error cancel switch 375 is operated, for example, a prize ball has not been paid out. The value of the number counter is also cleared. However, in this embodiment, since the payout control means is configured to perform the re-payout operation again by operating the error release switch 375, the payout process is executed reliably, which is disadvantageous to the player. Can not be given.

  In step S808, the payout control CPU 371 checks the detection signal of the full tank switch 48. If the detection signal of the full tank switch 48 is output (if it is in the ON state), the full tank error bit in the error flag is set (step S809). If the detection signal of the full tank switch 48 is in the OFF state, the full tank error bit is reset (step S810).

  Also, the payout control CPU 371 checks the detection signal of the ball break switch 187 (step S811). If the detection signal of the ball break switch 187 is output (if it is on), the ball break error bit in the error flag is set (step S812). If the detection signal of the ball break switch 187 is OFF, the ball break error bit is reset (step S813). When the ball break error bit is set, the bit corresponding to the ball break LED 52 in the output port 1 buffer is set to a value corresponding to the lighting state in the display control process of step S759.

  Further, the payout control CPU 371 checks the state of the connection confirmation signal from the main board 31 (step S815). If the connection confirmation signal is not output (if it is in the off state), the main board unconnected error bit is set. Set (step S816). If the connection confirmation signal is output (if it is on), the main board non-connection error bit is reset (step S817).

  Further, the payout control CPU 371 checks the value of the switch timer corresponding to the payout number count switch 301 among the switch timers in which the state of the detection signal of each switch is set, and the value is the switch on maximum time (for example, “ 240 ") (step S818), the bit of the payout switch abnormality detection error 1 is set in the error flag (step S819). If the value of the switch timer corresponding to the payout number count switch 301 is less than the switch-on maximum time, the bit of the payout switch abnormality detection error 1 is reset (step S820). Note that the value of each switch timer is incremented by 1 when the state of the input port to which the detection signal of each switch is input is switched on in the input determination process of step S751, and cleared by 0 when it is off. Accordingly, the fact that the value of the switch timer corresponding to the payout number count switch 301 exceeds the switch on maximum time means that the payout number count switch 301 is in the on state exceeding the switch on maximum time. Then, it is determined that the game ball is clogged at the disconnection of the payout number count switch 301 or at the portion of the payout number count switch 301.

  Further, the payout control CPU 371, when the value of the switch timer corresponding to the payout number count switch 301 becomes a switch-on determination value (eg, “2”) (step S821), the ball lending operation flag and the winning ball operation If both the middle flags are in the reset state, the game ball has passed through the payout number count switch 301 even though the payout operation is not in progress, and the bit of the payout switch abnormality detection error 2 in the error flag is set (steps S822 and S823). . If the ball lending operation flag or the winning ball operation flag is set, the bit of the payout switch abnormality detection error 2 is reset (step S824).

  The payout control CPU 371 confirms the input state of the VL signal from the card unit 50 (step S825). If the VL signal is not input (if it is in the off state), the prepaid card unit not yet out of the error flags is displayed. A connection error bit is set (step S826). If the VL signal is input (if it is on), the prepaid card unit unconnected error bit is reset (step S827).

  In the display control process in step S759, notification by display (numerical value display) corresponding to the error bit in the error flag is performed by the error display LED 374. Therefore, a communication error can be notified by the error display LED 374. Further, since the communication error is detected on the payout control means side, the communication error can be detected without increasing the burden on the game control means.

  In this embodiment, the main board non-connection error is automatically eliminated when the connection confirmation signal is turned on (see steps S815 and S817), but the condition that the error release switch 375 is further operated is added. Thus, the error state may be eliminated.

  In this embodiment, a communication error is reported so as to be distinguishable from a communication error with the card unit 50 (a prepaid card unit unconnected error and a prepaid card unit communication error) and other errors (see FIG. 57). ). Therefore, a communication error between the game control microcomputer 560 and the payout control microcomputer 370 is easily identified.

  Next, the operation of the sound / lamp control means (sound / lamp control microcomputer 100b) will be described. FIG. 60 is a flowchart showing main processing executed by the sound / lamp control microcomputer 100b (specifically, the sound / lamp control CPU 101b) mounted on the sound / lamp control board 80b. When power supply to the gaming machine is started and the reset signal becomes high level, the sound / lamp control microcomputer 100b starts main processing. In the main process, the sound / lamp control microcomputer 100b first performs an initialization process for clearing the RAM area, setting various initial values, initializing a timer for determining the activation control activation interval, and the like. This is performed (step S781). Thereafter, the sound / lamp control microcomputer 100b shifts to a loop process for monitoring the timer interrupt flag (step S782). When a timer interrupt occurs, the sound / lamp control microcomputer 100b sets a timer interrupt flag in the timer interrupt process. If the timer interrupt flag is set in the main process, the sound / lamp control microcomputer 100b clears the flag (step S783) and executes the following sound / lamp control process.

  A timer interrupt takes, for example, every 2 ms. That is, the sound / lamp control process is activated every 2 ms, for example. In this embodiment, only the flag is set in the timer interrupt process, and the specific sound / lamp control process is executed in the main process, but the sound / lamp control process is executed in the timer interrupt process. Also good.

  In the sound / lamp control process, the sound / lamp control microcomputer 100b first analyzes the received effect control command (command analysis process: step S784). When an error specifying command is received, the error contents (prize ball error, full tank error, ball out error, door opening error) are specified based on the contents of the lower 4 bits of the command. Then, an error bit (error flag) corresponding to the content of the specified error is set. When the error bit is set, it is referred to in the notification control process, and error notification according to the content of the error is executed. The error notification may be executed by any one or a combination of sound, lamp, and display, or all of them, and when there is an error that is executed only by the variable display device 9, the error Only in this case, an error specifying command may be transmitted to the symbol control board.

  Next, the sound / lamp control microcomputer 100b performs an effect content determination process (step S785). In the effect content determination process, the sound / lamp control microcomputer 100b uses the variable display device 9 based on the effect control command (variation pattern command or display result designation command) (whether or not to perform the notice effect). Kaya, the type of notice effect). In addition, the sound / lamp control microcomputer 100b generates an effect content designation command indicating the determined effect content.

  Next, the sound / lamp control microcomputer 100b performs sound output processing (step S786). In this case, the sound / lamp control microcomputer 100b outputs sound number data (for example, sound number data corresponding to the variation pattern indicated by the variation pattern command) to the speech synthesis IC 173. Then, the voice synthesis IC 173 generates a voice or a sound effect corresponding to the sound number data and outputs it to the amplifier circuit 175.

  Next, the sound / lamp control microcomputer 100b performs lamp display processing (step S787). In this case, the sound / lamp control microcomputer 100b performs lamp control based on the lamp control execution data set in the process data.

  Further, the sound / lamp control microcomputer 100b executes a process of updating the random number counter (step S788). Further, the sound / lamp control microcomputer 100b performs a process of sending the effect control command received from the main board 31 and the effect content designation command generated in the effect content determination process in step S785 to the symbol control board 80a ( Command control processing: Step S789). The sound / lamp control microcomputer 100b executes notification control process processing for notifying that a predetermined error has occurred based on the reception of the error specifying command (step S790). Thereafter, the process returns to the process of checking the timer interrupt flag in step S782. For error notification, a different sound is output for each error content, or the error content is displayed on the screen of the variable display device 9 (for example, the characters “full tank error has occurred!” Are displayed. To inform the player of the contents of the error.

FIG. 61 is an explanatory diagram showing random numbers used in the sound / lamp control process. Each random number is used as follows.
(1) Random 1: Decide whether or not to execute the notice effect (for determining the notice effect execution). In this embodiment, when the variable display device 9 performs variable display of the decorative pattern in the reach mode, the sound / lamp control microcomputer 100b matches, for example, random 1 with one predetermined value. In this case, it is determined that a notice effect is to be performed. Note that the sound / lamp control microcomputer 100b may determine whether or not to perform the notice effect using random 1 regardless of whether or not the variable display of the reach mode is performed.
(2) Random 2: When performing the notice effect, the type of the notice effect performed using the variable display device 9 is determined (for determining the notice effect type).

  FIG. 62 is a flowchart showing the effect content determination process (step S785) shown in FIG. In the effect content determination process, the sound / lamp control microcomputer 100b confirms whether or not the variation pattern command reception flag is set (step S1851). The variation pattern command reception flag is a flag that is set based on confirmation that the variation pattern command has been received from the game control microcomputer 560 in the command control process (see step S789).

  If the variation pattern command reception flag is set, the sound / lamp control microcomputer 100b resets the variation pattern command reception flag and specifies the variation pattern of the decorative pattern based on the received variation pattern command. Further, the sound / lamp control microcomputer 100b determines whether or not the variable display to be executed using the variable display device 9 is a variation accompanied by reach based on the identified variation pattern (step S1852). For example, if the variation pattern indicated in the received variation pattern command is a pattern with reach, the sound / lamp control microcomputer 100b determines that the variation is accompanied by reach. . If the variation pattern command reception flag is not set in step S1851, the sound / lamp control microcomputer 100b ends the process.

  If it is determined that the variation is accompanied by reach, the sound / lamp control microcomputer 100b determines whether or not to perform the notice effect based on the notice effect execution determination random number (random 1) (step S1853). For example, the sound / lamp control microcomputer 100b determines to perform a notice effect using the variable display device 9 when the random 1 matches a predetermined value. If NO in step S1852, the sound / lamp control microcomputer 100b proceeds to step S1857.

  If it is determined in step S1854 that the notice effect is not performed, the sound / lamp control microcomputer 100b receives the variation pattern command and the display when the variation pattern command is received and the display result designation command is received. The result designation command is transmitted or transferred to the symbol control microcomputer 100a, and the symbol control microcomputer 100a executes variable display of the decorative symbol and the game effect using the variable display device 9. In this case, if the sound / lamp control microcomputer 100b determines not to perform the notice effect in step S1854, the sound / lamp control microcomputer 100b generates a notification command for designating that the notice effect is not performed, and transmits it to the symbol control microcomputer 100a ( Step S1857).

  If it is determined that the notice effect is to be performed (step S1854), the sound / lamp control microcomputer 100b determines the type of the notice effect to be performed using the variable display device 9 based on the random number for determining the notice effect type (random 2). Determination is made (step S1855). For example, the sound / lamp control microcomputer 100b can change the speed of the decorative symbol and the rotation direction of the decorative symbol in the notice effect based on the random 2, variable display device. 9 determines which character is to appear.

  In this embodiment, description will be made on the case where the production contents are determined based on the variation pattern command. However, the sound / lamp control microcomputer 100b is based on the display result designation command received from the game control microcomputer 560. Thus, it may be determined that the non-probable big hit or the probable big hit is the production content. In addition, the sound / lamp control microcomputer 100b receives the symbol deviation number designation command from the game control microcomputer 560, and based on the received symbol deviation number designation command, is the stop symbol a symbol with a reach? The content of the production may be determined by specifying whether or not. In this case, for example, when the game control microcomputer 560 determines the stop symbol as the reach / displacement symbol when determining the stop symbol of the decoration symbol in the special symbol stop symbol setting process (see step S301), Obtain the number of stoppages of the decorative symbol. Further, the game control microcomputer 560 generates a symbol deviation number designation command including a value that can specify the obtained deviation number, and transmits the command to the sound / lamp control microcomputer 100b. Then, the sound / lamp control microcomputer 100b specifies that the stop symbol is a reach / delay symbol based on the reception of the symbol deviation number command, and determines the contents of the effect.

  Furthermore, the sound / lamp control microcomputer 100b may determine the contents of the effect based on all the commands (the variation pattern command, the display result designation command, and the symbol deviation number designation command) described above. Further, the sound / lamp control microcomputer 100b determines the contents of the effect based on any two of the above-described commands (variation pattern command, display result designation command, and symbol deviation number designation command). May be.

  Further, the sound / lamp control microcomputer 100b generates an effect content designation command indicating the determined effect content (whether or not to perform the notice effect and the type of the notice effect). Then, the sound / lamp control microcomputer 100b performs a process of transmitting the generated effect content designation command to the symbol control board 80a (step S1856). Note that the sound / lamp control microcomputer 100b transfers or transmits the display result designation command and the variation pattern command to the symbol control board 80a together with the effect content designation command. Then, the symbol control microcomputer 100a of the symbol control board 80a performs symbol control process processing (to be described later) based on the effect content designation command, the display result designation command, and the variation pattern command received from the sound / lamp control microcomputer 100b. In step S1705), a decorative pattern variable variation and a game effect are performed. In this case, the symbol controlling microcomputer 100a causes the VDP 109 to perform a notice effect using the variable display device 9 based on the received effect content designation command.

  In step S1856, the sound / lamp control microcomputer 100b may add the determined effect content to the variation pattern command or the display result specification command instead of generating the effect content specifying command. For example, the sound / lamp control microcomputer 100b adds an effect content to a variation pattern command or a display result designation command by adding a value indicating the effect content to the header portion of the command. In this case, the sound / lamp control microcomputer 100b may add a value indicating the effect content to the header portion of only the variation pattern command, or add a value indicating the effect content to the header portion of only the display result designation command. May be. Further, the sound / lamp control microcomputer 100b may add a value indicating the effect content to the header portions of both the variation pattern command and the display result designation command. Then, the sound / lamp control microcomputer 100b may perform a process of transmitting a variation pattern command and a display result designation command to which the contents of the effect are added to the symbol control board 80a. When the notice effect is not performed, the sound / lamp control microcomputer 100b transfers the display result designation command received from the game control microcomputer 560 to the symbol control microcomputer 100a as it is.

  Also, in this embodiment, the command for specifying the contents of the effect is performed by executing the command control process (see step S789) in the sound / lamp control main process based on the setting of the address of the transmission table in step S1856. Is transmitted to the symbol control board 80a.

  In this embodiment, sound / lamp control side process data including lamp control execution data is stored in the ROM of the sound / lamp control board 80b. Further, symbol control side process data including display control execution data is stored in the ROM in the symbol control board 80a. In this embodiment, in step S1856, the sound / lamp control microcomputer 100b transmits an effect content designation command generated according to the determined effect content to the symbol control microcomputer 100a. The symbol control microcomputer 100a reads the display control execution data from the ROM based on the received effect content designation command, and performs the effect using the variable display device 9 based on the read display control execution data.

  In addition, when adding the effect content determined in step S1856 to the variation pattern command or the display result designation command, the sound / lamp control microcomputer 100b adds the determined effect content (for example, the background color or the appearing character). A variation pattern command or a display result designation command may be transmitted to the symbol control microcomputer 100a. The symbol control microcomputer 100a reads display control execution data from the ROM based on the received variation pattern command and display result designation command, and produces an effect using the variable display device 9 based on the read display control execution data. You may go.

  Further, process data including both display control execution data and lamp control execution data may be stored in the ROM of the sound / lamp control board 80b. In this case, the sound / lamp control microcomputer 100b may extract display control execution data corresponding to the determined effect content from the ROM, and transmit the display control execution data to the symbol control microcomputer 100a together with the generated effect content designation command. . Then, the symbol control microcomputer 100a may produce an effect using the variable display device 9 based on the received display control execution data.

  When process data including both display control execution data and lamp control execution data is stored in the ROM of the sound / lamp control board 80b, the sound / lamp control microcomputer 100b responds to the determined contents of the effect. The display control execution data may be extracted from the ROM and transmitted to the symbol control microcomputer 100a together with the variation pattern command and the display result designation command to which the determined production content is added. Then, the symbol control microcomputer 100a may produce an effect using the variable display device 9 based on the received display control execution data.

  FIG. 63 is a flowchart showing the notification control process. In the notification control process, the effect control CPU 101 performs one of steps S1900 and S1901 according to the value of the notification control process flag. In each process, the following process is executed.

  The notification start process (step S1900) is a process of starting notification of an error or the like based on each error flag (full tank error notification flag, prize ball error notification flag, ball outage error notification flag) set in the command analysis processing. is there. When the notification is started, the value of the notification control process flag is changed to a value corresponding to the processing during notification (step S1901).

  The in-notification process (step S1901) is a process of continuing the notification based on each error flag (full tank error notification flag, prize ball error notification flag, and out of ball error notification flag). When the error is canceled and the error flag (error bit) is reset, the notification is terminated. When the notification ends, the value of the notification control process flag is changed to a value corresponding to the notification start process (step S1901).

  Next, the operation of the symbol control means (the symbol control microcomputer 100a) will be described. FIG. 64 is a flowchart showing a main process executed by the symbol control microcomputer 100a (specifically, the symbol control CPU 101a) mounted on the symbol control board 80a. When the power is turned on, the symbol control microcomputer 100a starts executing the main process. In the main processing, first, initialization processing is performed for clearing the RAM area, setting various initial values, and initializing a timer for determining the start interval of symbol control (step S1701). Thereafter, the symbol controlling microcomputer 100a shifts to a loop process for monitoring a timer interrupt flag (step S1702). When a timer interrupt occurs, the symbol control microcomputer 100a sets a timer interrupt flag in the timer interrupt process. If the timer interrupt flag is set in the main process, the symbol control microcomputer 100a clears the flag (step S1703) and executes the following symbol control process.

  In the symbol control process, the symbol control microcomputer 100a first analyzes the effect control command received from the sound / lamp control board 80b (command analysis process: step S1704). Next, the symbol control microcomputer 100a performs symbol control process processing (step S1705). In the symbol control process, a process corresponding to the current control state (symbol control process flag) is selected from the processes corresponding to the control state, and display control of the variable display device 9 is executed. Further, random number update processing for updating the counter value of the counter for generating various random numbers is executed (step S1706).

  Further, the symbol control microcomputer 100a executes notification control process processing for notifying that a predetermined error (prize ball error, full tank error, ball shortage error, door opening error) has occurred (step S1707). In this case, the symbol control microcomputer 100a notifies that a predetermined error has occurred according to the same processing as the notification control process executed by the sound / lamp control microcomputer 100b shown in FIG. However, the symbol controlling microcomputer 100a uses the variable display device 9 to notify that a predetermined error has occurred. For example, the symbol control microcomputer 100a displays on the variable display device 9 that a predetermined error has occurred. Thereafter, the process proceeds to step S1702.

  FIG. 65 is a flowchart showing the symbol control process (step S1705) in the main process shown in FIG. In the symbol control process, the symbol control CPU 101a performs one of steps S1800 to S1807 according to the value of the symbol control process flag. In each process, the following process is executed.

  Fluctuation pattern command reception waiting process (step S1800): It is confirmed whether or not an effect control command (variation pattern command) specifying a fluctuation pattern has been received from the sound / lamp control board 80b by the command reception interrupt process. Specifically, it is confirmed whether or not a flag (variation pattern reception flag) indicating that a variation pattern command has been received is set. The variation pattern reception flag is set when it is confirmed that a variation pattern command has been received in the command analysis processing executed by the symbol control CPU 101a. When a variation pattern command is received, the decoration pattern variation mode (variation speed of the decoration pattern during the variation period, background, character type, character display start time, etc.) is previously set according to each variation pattern. Select from a number of fixed types. In addition, when one type of variation mode is determined in advance for each variation pattern, it is determined to use the variation mode according to the received variation pattern. Then, the value of the symbol control process flag is updated to a value corresponding to the notice selection process (step S1801).

  Prior notice selection process (step S1801): For example, whether or not to perform a notice effect using a character image (an effect for informing in advance that a special symbol stop symbol becomes a big hit symbol or a reach occurs), The type of notice effect when performing is specified. In this embodiment, the notice effect to be performed using the variable display device 9 is specified based on the effect content designation command received from the sound / lamp control board 80b. Then, the value of the symbol control process flag is updated to a value corresponding to all symbol variation start processing (step S1802).

  All symbol variation start processing (step S1802): Control is performed so that the variation of the left middle right decorative symbol is started. Then, the value of the symbol control process flag is updated to a value corresponding to the symbol changing process (step S1803).

  Symbol variation processing (step S1803): The end of the variation time determined in accordance with the variation pattern is monitored. In addition, stop control of the left and right symbols is performed. When the variation time is over, if it is determined to be a jackpot, the value of the symbol control process flag is updated to a value corresponding to the jackpot symbol stop process (step S1804). If it is decided not to win, the value of the symbol control process flag is removed and updated to a value corresponding to the symbol stop processing (step S1805). In the symbol variation processing, the switching timing of each variation state (variation speed) constituting the variation pattern is also controlled.

  Big hit symbol stop process (step S1804): Control is performed to finally stop the variation of the decorative symbol and display the stop symbol (determined symbol). Then, the value of the symbol control process flag is updated to a value corresponding to the jackpot display process (step S1806). In this process, the symbol control CPU 101a causes the variable display device 9 to stop and display the decorative symbol jackpot symbol, but, similar to the control of the game control microcomputer 560, the symbol control process flag value is the jackpot symbol stoppage. It is preferable to continue the processing time for a predetermined time.

  Lost symbol stop process (step S1805): Control is performed to finally stop the variation of the decorative symbol and display the stop symbol (determined symbol). Then, the value of the symbol control process flag is updated to a value corresponding to the variation pattern command reception waiting process (step S1800). In this process, the symbol control CPU 101a causes the variable display device 9 to stop and display the decorative symbols.

  Big hit display processing (step S1806): Big hit display is controlled. Then, the value of the symbol control process flag is updated to a value corresponding to the big hit game processing (step S1807).

  Big hit game processing (step S1807): Control during the big hit game is performed. For example, when an effect control command for display before opening the big winning opening or display when opening the big winning opening is received, display control of the number of rounds is performed. When the big hit game ends, the value of the symbol control process flag is updated to a value corresponding to the variation pattern command reception waiting process (step S1800).

  As described above, in this embodiment, the game control microcomputer 560 transmits the award ball request signal as a connection confirmation command to the payout control microcomputer every predetermined period (1 s), and the payout control microcomputer 370. Transmits a received ACK signal as a connection OK command to the game control microcomputer 560 based on the input of the prize ball request signal. In addition, the game control microcomputer specifies the number of prize balls to be paid out when outputting a prize ball request signal based on the fact that a predetermined payout condition has been established (a game ball has won a prize opening). Possible data is set by changing a predetermined bit of the prize ball request signal, and the prize ball request signal thus set is transmitted to the payout control microcomputer 370 as a prize ball number command. 370 executes a prize ball payout operation for paying out the number of game balls specified by the prize ball request signal based on the prize ball number command as the prize ball request signal. Further, the payout control microcomputer 370 receives data that allows the game control microcomputer 560 to recognize the predetermined error when a predetermined error (prize ball error, full tank error, out of ball error) occurs. A predetermined bit of the ACK signal is set to be different, and the received ACK signal that has been set is transmitted to the game control microcomputer 560 as a connection OK command. According to such a configuration, the payout control microcomputer 370 can transmit an error signal by placing predetermined error information on a reception ACK signal that is periodically transmitted based on reception of a prize ball request signal. Further, it is possible to prevent the occurrence of error signal dropping without considering the error signal transmission timing, and to reliably perform communication between the game control microcomputer 560 and the payout control microcomputer 370. . In this embodiment, the cycle (interval) for transmitting a connection confirmation command as a prize ball request signal is 1 second, but it may be 0.5 seconds or the like.

  When the game control microcomputer 560 transmits a prize ball number command as a prize ball request signal, it subtracts the prize ball number specified by the prize ball request signal from the prize ball command output counter formed in the RAM 55. Even when the reception ACK signal including the error information transmitted by the payout control microcomputer 370 is received, the prize ball number command as the prize ball request signal is prohibited from being output again. Therefore, it is possible to reliably prevent an illegal act that illegally pays out a prize ball. That is, when the number of prize balls is subtracted after the prize ball payout operation is completed, a prize ball number command is transmitted and the prize ball payout operation is executed (for example, 15 prize balls to be paid out). In this case, the number of unpaid award balls stored in the award ball command output counter after the recovery by an illegal act that causes an unauthorized power off when 10 award balls are paid out) The prize ball number command is sent again and there is a possibility that a lot of prize balls will be paid out illegally. However, if the subtraction process is executed when the prize ball number command is sent, such illegal It is possible to prevent an action in which many prize balls are paid out.

  The game control microcomputer 560 is configured to transmit a connection confirmation signal indicating a connection state of communication with the payout control microcomputer 370 to the payout control microcomputer 370 via the output port 57. Since the connection state of communication can be confirmed at any timing on the control microcomputer 370 side, it is possible to reliably prevent award balls from being paid out when the communication connection state is abnormal. .

  After outputting the connection confirmation command as the prize ball request signal, the game control microcomputer 560 determines whether or not to receive the connection OK command as the reception ACK signal within the predetermined period, and receives the reception ACK within the predetermined period. When it is determined that a signal has not been received, a communication error has occurred and a connection confirmation command as a prize ball request signal is issued at a specific period (10 s) longer than the predetermined period (1 s). Therefore, it is possible to recognize a communication error at an early stage, avoid frequent transmission of a request signal when the communication state is not normal, and the processing of the game control microcomputer 560. The burden can be reduced.

  The game control microcomputer 560 and the payout control microcomputer 370 have built-in serial communication circuits 505 and 380 for serial communication with other microcomputers, and the payout control microcomputer 370 has received the prize ball request signal. The payout control microcomputer 370 is configured to execute a reception interrupt process for receiving the prize ball request signal and to transmit a prize ball ACK signal within the reception interrupt process. Therefore, it can be prevented that the transmission of the reception ACK signal is delayed due to the delay of the process, and the game control microcomputer 560 determines that the communication error has occurred.

  A sound / lamp control microcomputer 100b for controlling a predetermined effect device (speaker 27, lamp) is provided. When the game control microcomputer 560 receives a connection OK command as a reception ACK signal including error information, The received reception ACK signal is transmitted as it is to the sound / lamp control microcomputer 100b, and the sound / lamp control microcomputer 100b controls the rendering device based on the reception of the connection OK command as the reception ACK signal. Thus, since it is configured to notify that the predetermined error has occurred, it is possible to notify that the predetermined error has occurred without increasing the processing load of the game control microcomputer 560.

  In this embodiment, since the payout detection signal from the payout number count switch 301 is input to the main board 31 via the payout control board 37, the payout detection signal is output. It is not necessary to provide wiring on both the main board 31 and the payout control board 37 from the payout number count switch 301. Therefore, the wiring for outputting the payout detection signal from the payout number count switch 301 can be reduced.

  Note that a payout detection signal from the payout number count switch 301 may be directly input to the main board 31. In this case, wiring for outputting a payout detection signal from the payout number count switch 301 is provided on both the main board 31 and the payout control board 37. Based on the payout detection signal directly input from the payout count switch 301, the game control microcomputer 560 performs a subtraction process for the total number of winning balls stored in the total winning ball number storage buffer in the input determination process.

  In this embodiment, an effect control command from the main board 31 is first received by the sound / lamp control board 80b, and further, a variation pattern command and an effect content designation command are sent from the sound / lamp control board 80b to the symbol control board 80a. In the above description, the effect control command from the main board 31 may be first received by the symbol control board 80a.

  FIG. 66 is a block diagram showing another circuit configuration example of the relay board 77, the sound / lamp control board 80b, and the symbol control board 80a. When the circuit configuration shown in FIG. 66 is used, for example, the symbol controlling microcomputer 100a follows the same processing as steps S1851 to S1856, based on the variation pattern command, whether the contents of the presentation (whether or not to perform the notice effect, Determine the type of production). Then, the symbol controlling microcomputer 100a causes the VDP 109 to perform a notice effect using the variable display device 9 in accordance with the determined effect contents. Further, the symbol control microcomputer 100a may generate an effect content designation command indicating the determined effect content and transmit it to the sound / lamp control board 80b. The sound / lamp control microcomputer 100b mounted on the sound / lamp control board 80b performs display control of the lamps 25, 28a, 28b, 28c in accordance with the contents of the effect indicated by the received effect content designation command. Sound output control of the sound output device 27 may be performed.

  In this embodiment, the case where the sound / lamp control board 80b and the symbol control board 80a are used as the case where each effector is controlled using separate control boards has been described. You may control each effect means using. For example, each rendering means may be controlled using a sound control board that controls the sound output device 27, a lamp control board that controls each lamp, and a symbol control board that controls the variable display device 9. In this case, for example, an effect control command from the main board 31 is first received by the sound control board, and the sound control microcomputer mounted on the sound control board receives the effect contents (the notice effect) based on the received variation pattern command. Whether or not to perform, and the type of the notice effect) may be determined. The production control command from the main board 31 is first received by the lamp control board or the design control board, and the microcomputer mounted on the lamp control board or the design control board determines the production contents or specifies the variation time. Also good. Further, for example, each rendering means may be controlled using a sound / design control board for controlling the sound output device 27 and the variable display device 9 and a lamp control board for controlling each lamp. Further, for example, each rendering means may be controlled using a lamp / design control board for controlling each lamp and the variable display device 9 and a sound control board for controlling the sound output device 27. Further, only one effect control board is provided, and an effect control microcomputer mounted on the effect control board executes display control of the variable display device 9, sound output from the speaker 27, and lamp lighting control. May be.

  In the above embodiment, the serial communication circuits 505 and 101c are mounted on both the game control microcomputer 560 and the sound / lamp control microcomputer 100b, and serial communication is performed between the two microcomputers. However, the present invention is not limited to this configuration, and a plurality of signal lines (between the game control microcomputer 560 (main board 31) and the sound / lamp control microcomputer 100b (sound / lamp control board 80b) ( 8 signal lines), and may be configured to perform parallel communication via an input / output port.

  In the above embodiment, the game control microcomputer 560 normally transmits a prize ball request signal 1 second after the reception of the reception ACK signal, and when a communication error occurs, the reception ACK It was configured to send a prize ball request signal 10 seconds after the signal was received and configured to measure a period of 1 second or 10 seconds with a timer (a counter configured by software). The winning ball request signal may be transmitted by an internal interrupt that occurs when the counter updated as hardware reaches a predetermined value (1 second or 10 seconds). In that case, the counter may be cleared by reception of the received ACK signal, or the counter may be cleared if an internal interrupt is generated with a predetermined value. In the above embodiment, the game control microcomputer 560 is configured to periodically transmit a prize ball request signal even when a prize ball preparation command is received. May be configured not to transmit a prize ball request signal.

  The serial communication circuit is set by the processing shown in FIG. 25, but the serial communication circuit is set as an internal function of the microcomputers 560 and 370, for example, setting information stored in a predetermined area (non-rewritable area) of ROM. The setting value may be set in the register based on the above.

  The present invention is applicable to gaming machines such as pachinko gaming machines and slot machines, and in particular to gaming machines that perform serial communication between a gaming control microcomputer and a payout control microcomputer using a serial communication circuit. It can be suitably applied.

1 Pachinko machine 9 Variable display device 14 Start winning opening 15 Variable winning ball device 31 Game control board (main board)
37 Dispensing control board 56 CPU
80a design control board 80b sound / lamp control board 100a design control microcomputer 100b sound / lamp control microcomputer 101a design control CPU
101b Sound / lamp control CPU
505 Serial communication circuit 560 Microcomputer for game control

Claims (6)

A gaming machine in which a player can play a predetermined game using a game medium, and pays out a free game medium as a prize based on a predetermined payout condition being satisfied,
A game control microcomputer for controlling the progress of the game;
A payout means for paying out the prize game medium;
A payout control microcomputer for controlling the payout means,
The game control microcomputer and the payout control microcomputer input and output signals by serial communication,
The game control microcomputer is:
Request signal output means for outputting a request signal to the payout control microcomputer at predetermined intervals;
Payout number storage means for storing payout number data capable of specifying the number of premium game media to be paid out based on the establishment of the predetermined payout condition;
The payout control microcomputer includes response signal output means for outputting a response signal to the game control microcomputer based on the input of the request signal output by the request signal output means,
The request signal output means sets data that can specify the number of premium game media to be paid out based on the payout number data stored in the payout number storage means when outputting the request signal, A payout number output means for outputting the set request signal to the payout control microcomputer;
The payout control microcomputer controls the payout means to pay out the prize game media of the number specified by the request signal based on the request signal output by the payout number output means. Including control means,
The response signal output means includes
When the premium game medium cannot be paid out, data indicating that the premium game medium is being prepared for payment is set by changing a predetermined bit of the response signal, and the setting is made. A preparation signal output means for outputting a response signal to the gaming control microcomputer;
When a predetermined error occurs, the game control microcomputer sets data by which the predetermined error can be recognized by changing a specific bit of the response signal, and the response signal with the setting is set. And an error signal output means for outputting to the game control microcomputer. The game control microcomputer
A connection signal output means for outputting a connection signal indicating a connection state of communication with the payout control microcomputer to the payout control microcomputer;
The gaming machine according to claim 1, further comprising: an output port that outputs the connection signal. The game control microcomputer
A payout number subtracting means for subtracting the number of prize game media specified by the request signal from the payout number data stored in the payout number storage means when outputting the request signal by the payout number output means;
Even when the response signal output by the error signal output means is input, the payout number re-output prohibiting means for prohibiting the output of the request signal that has been subject to subtraction by the payout number subtracting means, The gaming machine according to claim 1 or claim 2. The game control microcomputer
Response signal determination means for determining whether or not a response signal is input within a predetermined period after outputting the request signal;
When it is determined by the response signal determination means that the response signal has not been input within the predetermined period, it is determined that a communication error has occurred, and an abnormality request signal is issued at a specific period longer than a predetermined period. The gaming machine according to any one of claims 1 to 3, further comprising: an abnormal request signal output means for outputting to a computer. The game control microcomputer and the payout control microcomputer incorporate a serial communication circuit that performs serial communication with the other microcomputer.
5. The payout control microcomputer executes an input interrupt process for inputting the request signal based on the input of the request signal, and outputs a response signal within the input interrupt process. Game machines. Provided with an effect control microcomputer for controlling a predetermined effect device,
The game control microcomputer includes a notification error signal output means for outputting the input response signal as it is to the production control microcomputer when the response signal output by the error signal output means is input,
6. The effect control microcomputer includes an abnormality notifying unit that controls the effect device to notify that a predetermined error has occurred based on the input of the response signal. A gaming machine according to any one of the above.

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