JP4734084B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachinko machine, and more specifically, based on the fact that the variable display start condition is satisfied after the variable display execution condition is satisfied, a plurality of types of identification information that can be identified by each of the identification information. The present invention relates to a gaming machine that includes a variable display device that variably displays and sets a specific gaming state that is advantageous for a player after the display result of identification information becomes a specific display result.

  In gaming machines such as pachinko machines, variable display is possible by scrolling or updating and displaying predetermined identification information (hereinafter referred to as display symbols) on a display device such as a liquid crystal display (hereinafter referred to as LCD). There are many games that are enhanced by a so-called variable display game that determines whether or not to give a predetermined game value based on a display result that is a combination result.

  A special figure game that is performed as one of the variable display games is a variable display of a display symbol based on the detection of a game ball that passes through the start winning opening (that the variable display start condition is satisfied). In this game, the case where the stop symbol form when the display is completely stopped is a specific display form determined in advance is set to “big hit”. In this special figure game, when a “hit” is made, a special electric accessory called a big prize opening or an attacker is opened, and a state in which a game ball can be won extremely easily is provided to a player for a certain period of time. . Such a state is referred to as a “specific game state” or a “hit game state”.

As such a gaming machine, a random number for determining a big hit used to determine whether or not to make a “big hit” in a special game is generated by a random number circuit built in a microcomputer for game control. When the power supply to the gaming machine is started, the random number circuit is set to generate a random number, for example, the maximum value of the random number, the update method of the random number, the period of the internal clock signal, etc. There has been proposed one that permits execution of a timer interrupt process that occurs automatically (for example, Patent Document 1).
Japanese Patent Laying-Open No. 2005-103166

Further, there has been proposed one that stops the operation of the gaming machine when the oscillator used for changing the random number for determining the jackpot does not operate normally (for example, Patent Document 2).
JP-A-11-313966

  According to the techniques described in Patent Document 1 and Patent Document 2, the initial value (start value of the first round) of a random number that is set when power supply to a gaming machine is started is a different gaming control microcomputer. Even if it exists, it becomes the same value and cannot be a different value. Therefore, there is a problem in that a “big hit” may be illegally generated by generating a signal for taking in a random number value at a timing when a predetermined time has elapsed from the start of power supply.

  Further, in the technique described in Patent Document 2, since only the oscillation state of the oscillator used to change the random number for determining the big hit is monitored, an abnormality occurring in another configuration provided for generating the random number is detected. There was a problem that it could not be detected.

  The present invention has been made in view of the above circumstances, and provides a gaming machine that can generate a random number with high randomness and can detect an abnormality that has occurred in a configuration provided for generating a random number. The purpose is to provide.

In order to achieve the above object, the gaming machine according to claim 1 of the present application satisfies the variable display execution condition (for example, the game ball wins at the start winning opening provided in the normal variable winning ball apparatus 6). After that, based on the fact that the variable display start condition (for example, the previous special figure game or the big hit gaming state by the special symbol display device 4 is completed) is established, a plurality of types of identification information (for example, special A variable display device (for example, a special symbol display device 4) that variably displays symbols, etc., and a specific game state (for example, a jackpot symbol) that is advantageous to the player after the display result of the identification information becomes a specific display result (for example, a jackpot symbol) For example, a gaming machine (for example, a pachinko gaming machine 1 or the like) that is a big hit gaming state, etc., and a gaming control microcomputer (for example, a gaming control microcomputer) that controls the progress of the game. Computer 100), a reference clock signal output means (eg, reference clock signal generation circuit 111) that outputs a reference clock signal (eg, reference clock signal CLK) having a predetermined period, and a random number (eg, a random number value for jackpot determination) R1 etc.) and a game control board (eg main board 11 etc.) on which a random number circuit (eg random number circuit 112 etc.) is mounted, the random number circuit outputs a reference clock signal from the reference clock signal output means. Based on this, random number generation clock signal generation means (for example, clock signal output circuit 171) for generating a random number generation clock signal (for example, clock signal S1), and random number generation generated by the random number generation clock signal generation means The display result in the variable display based on the input of the clock signal for the specific display Specific display result determination numerical data (e.g., count value C, etc.) used when determining whether or not to be a result is determined in advance from a predetermined initial value to a predetermined final value within a predetermined updateable range. Specific display result determination numerical data updating means (for example, a random number generation circuit 173) that cyclically updates in accordance with the specified order, and specific display result determination numerical data updated by the specific display result determination numerical data update means Display result determination numerical value storage means (for example, a random number value register 176), and the game control microcomputer causes the random number circuit to generate the random number after power supply to the game machine is started. Random number circuit setting means (for example, the part where the CPU 103 executes the random number initial setting process of step S21) and the random number circuit setting After the setting by the setting means, a timer interrupt process execution permitting means (for example, a portion where the CPU 103 executes the process of step S24) for permitting execution of a timer interrupt process that occurs periodically, and the timer interrupt process During execution, execution condition determination means for determining whether or not the variable display execution condition is satisfied (for example, a portion where the CPU 103 executes the process of step S261), and execution of the variable display by the execution condition determination means. Display result determination numerical value reading means for reading specific display result determination numerical data from the display result determination numerical value storage means based on the determination that the condition is satisfied (for example, a portion where the CPU 103 executes the process of step S302) Etc.) and the numerical data for specific display result determination read by the display result determination numerical value reading means. Specific display result determination means (for example, the CPU 103) that determines whether or not the display result in the variable display is set as the specific display result by determining whether or not the data matches a predetermined specific display result determination value data. Is the portion for executing the process of step S404) and the numerical data for effect determination (for example, reach determination) updated in synchronization with the specific display result determination numerical data updated by the specific display result determination numerical data update means. Numerical value data for effect determination acquired by the numerical data acquisition means for effect determination (for example, the portion where the CPU 103 executes the process of step S334) and the numerical value acquisition means for effect determination acquired by the effect determination numerical data acquisition means. A performance that determines whether or not to execute a predetermined performance is determined by determining whether or not it matches the predetermined performance determination value data. Determining means (for example, a part where the CPU 103 executes the process of step S335), and the random number circuit setting means sets the predetermined initial value to a predetermined value or sets the predetermined value for each game control microcomputer. look including the initial value setting means for performing granted if a value based on the unique identification information setting (e.g. CPU103 and portions for performing the processing of step S103 to S106), the game machine further, gaming media A payout control board (for example, payout control) on which a payout device (for example, payout motor 51) and a payout control microcomputer (for example, payout control microcomputer 150) for controlling the payout operation by the payout device are mounted. The game control microcomputer includes a payout control microcomputer. A serial communication circuit (for example, the serial communication circuit 107) that performs serial communication with the computer, and a communication control means for controlling the serial communication operation by the serial communication circuit (for example, the CPU 103 performs serial communication initial setting processing in step S22) And the part for executing the interrupt initial setting process in step S23), and the serial communication circuit sets the interrupt request condition established for the communication control means when any of the plurality of interrupt request conditions is established. Including an interrupt request notification means (for example, SIST1 of the serial status register 204) for notifying an interrupt request according to the interrupt request condition established by an error occurring in serial communication. And processing corresponding to the occurrence of an error Including an error interrupt request (for example, an interrupt request at the time of a parity error, an interrupt request at the time of an overrun error, an interrupt request at the time of a framing error, an interrupt request at the time of a noise error) to be executed by the communication control means, and the communication control Means for giving priority to the interrupt process based on the error interrupt request over the process based on the interrupt request of a different type from the error interrupt request when a plurality of types of interrupt requests are simultaneously notified by the interrupt request notifying unit. Interrupt processing sequence control means (for example, the reset / interrupt controller 102 or the part that executes the process of step S122 when the read value by the CPU 104 at step S121 is other than “06h”, “07h”, etc.) And the error interrupt request is notified by the interrupt request notification means. As a result of the notification, an error interrupt processing means (for example, a portion where the CPU 104 executes the processes of steps S41 and S42) that stops the execution of the serial communication operation by the serial communication circuit as an interrupt process based on the error interrupt request; Including Note that the game control microcomputer counts the number of consecutive effect counts (eg, for example) that counts the number of times that the variable display start condition for which the predetermined effect is determined to be executed by the effect determination unit is established. The reach number counter provided in the game control counter setting unit 135 and the part where the CPU 103 executes the process of step S338) and the number of times counted by the effect continuous number counting means exceeds a predetermined effect continuous upper limit value. It has been determined that the production continuous upper limit value has been exceeded by the production continuous number judgment means (for example, the part where the CPU 103 executes the process of step S230) and the production continuous number judgment means for judging whether or not By means of the above, an abnormality detecting means (example) If when the CPU103 determines that Yes in step S230, the step S231, step S228, like portions for performing the process of S229) may include. Alternatively, the game control microcomputer counts the number of times of avoidance of the effects (for example, counts the number of times that the variable display start condition for which the predetermined effect is not executed is determined by the effect determining means). A normal loss counter provided in the game control counter setting unit 135, a portion where the CPU 103 executes the process of step S341, and the number of times counted by the effect avoidance frequency counting means exceed a predetermined effect avoidance upper limit value. It is determined that the production avoidance upper limit value is exceeded by the production avoidance number judgment means (for example, the part where the CPU 103 executes the process of step S232) and the production avoidance number judgment means. By detecting the abnormality in the random number circuit Means (e.g., step when the CPU103 determines that Yes at step S232 S233, S228, etc. portions for performing the process of S229) may include.

In order to achieve the above object, the gaming machine according to claim 2 of the present application satisfies the variable display execution condition (for example, the game ball wins at the start winning opening provided in the normal variable winning ball apparatus 6). After that, based on the fact that the variable display start condition (for example, the previous special figure game or the big hit gaming state by the special symbol display device 4 is completed) is established, a plurality of types of identification information (for example, special A variable display device (for example, a special symbol display device 4) that variably displays symbols, etc., and a specific game state (for example, a jackpot symbol) that is advantageous to the player after the display result of the identification information becomes a specific display result (for example, a jackpot symbol) For example, a gaming machine (for example, a pachinko gaming machine 1 or the like) that is a big hit gaming state, etc., and a gaming control microcomputer (for example, a gaming control microcomputer) that controls the progress of the game. Computer 100), a reference clock signal output means (eg, reference clock signal generation circuit 111) that outputs a reference clock signal (eg, reference clock signal CLK) having a predetermined period, and a random number (eg, a random number value for jackpot determination) R1 etc.) and a game control board (eg main board 11 etc.) on which a random number circuit (eg random number circuit 112 etc.) is mounted, the random number circuit outputs a reference clock signal from the reference clock signal output means. Based on this, random number generation clock signal generation means (for example, clock signal output circuit 171) for generating a random number generation clock signal (for example, clock signal S1), and random number generation generated by the random number generation clock signal generation means The display result in the variable display based on the input of the clock signal for the specific display Specific display result determination numerical data (e.g., count value C, etc.) used when determining whether or not to be a result is determined in advance from a predetermined initial value to a predetermined final value within a predetermined updateable range. Specific display result determination numerical data updating means (for example, a random number generation circuit 173) that cyclically updates in accordance with the specified order, and specific display result determination numerical data updated by the specific display result determination numerical data update means Display result determination numerical value storage means (for example, a random number value register 176), and the game control microcomputer causes the random number circuit to generate the random number after power supply to the game machine is started. Random number circuit setting means (for example, the part where the CPU 103 executes the random number initial setting process of step S21) and the random number circuit setting After the setting by the setting means, a timer interrupt process execution permitting means (for example, a portion where the CPU 103 executes the process of step S24) for permitting execution of a timer interrupt process that occurs periodically, and the timer interrupt process During execution, execution condition determination means for determining whether or not the variable display execution condition is satisfied (for example, a portion where the CPU 103 executes the process of step S261), and execution of the variable display by the execution condition determination means. Display result determination numerical value reading means for reading specific display result determination numerical data from the display result determination numerical value storage means based on the determination that the condition is satisfied (for example, a portion where the CPU 103 executes the process of step S302) Etc.) and the numerical data for specific display result determination read by the display result determination numerical value reading means. Specific display result determination means (for example, the CPU 103) that determines whether or not the display result in the variable display is set as the specific display result by determining whether or not the data matches a predetermined specific display result determination value data. And the numerical data holding means for holding the specific display result determination numerical data read by the display result determination numerical value reading means (for example, the jackpot determination random number value holding unit 137). And the like, and whether or not the specific display result determination numerical data read by the display result determination numerical value reading means matches the specific display result determination numerical data held in the numerical data holding means Numerical match determination means (for example, the part where the CPU 103 executes the process of step S361) and the numerical match determination means. When the determination is made that the display result determination is not performed, the specific display result determination numerical data to be held in the numerical data holding means is newly updated to the specific display result determination numerical data read by the display result determination numerical value reading means. Holding numerical data updating means (for example, the part where the CPU 103 executes the process of step S363) and the coincidence continuous number counting means (for example, counting the number of times that the coincidence determination is made by the numerical value coincidence determining means) A match number counter provided in the game control counter setting unit 135, a part where the CPU 103 executes the process of step S364, and the number of times counted by the match continuous number counting means exceeds a predetermined match continuous upper limit value. The coincidence continuous number determination means for determining whether or not the CPU 103 And the abnormality detection for detecting that an abnormality has occurred in the random number circuit by the determination that the matching continuous number upper limit value has been exceeded by the matching continuous number determination means. Means (for example, the part that executes the processing of steps S366 and S367 when the CPU 103 determines Yes in step S365), the random number circuit setting means sets the predetermined initial value to a predetermined value Or initial value setting means (for example, a portion where the CPU 103 executes the processing of steps S103 to S106) for setting whether the value is based on the unique identification information assigned to each game control microcomputer. The gaming machine further includes a payout device (for example, a payout motor 51) for paying out game media and the payout device. A payout control board (for example, the payout control board 15) on which a payout control microcomputer for controlling the payout operation (for example, the payout control microcomputer 150, etc.) is mounted. A serial communication circuit (for example, the serial communication circuit 107) that performs serial communication with the control microcomputer is incorporated, and communication control means (for example, the CPU 103 performs serial communication in step S22) that controls the serial communication operation by the serial communication circuit. The serial communication circuit includes an interrupt that is established with respect to the communication control means when one of a plurality of interrupt request conditions is established. Notify interrupt request according to request conditions The interrupt request notified by the interrupt request notifying means includes an interrupt request notifying means (for example, SIST1 of the serial status register 204). Error interrupt request (for example, interrupt request at the time of parity error, interrupt request at the time of overrun error, interrupt request at the time of framing error, interrupt request at the time of noise error, etc.) The communication control means converts the interrupt process based on the error interrupt request into a process based on an interrupt request of a type different from the error interrupt request when a plurality of types of interrupt requests are notified simultaneously by the interrupt request notification means. Interrupt processing order control means (prior to execution) For example, when the read value in step S121 by the reset / interrupt controller 102 or the CPU 104 is other than “06h” or “07h”, the process of step S122 is executed), and the error is notified by the interrupt request notification unit. Error interrupt processing means for stopping execution of the serial communication operation by the serial communication circuit (for example, the part where the CPU 104 executes the processing of steps S41 and S42) as the interrupt processing based on the error interrupt request when the interrupt request is notified Etc.) .

In order to achieve the above object, the gaming machine according to claim 3 of the present application satisfies the variable display execution condition (for example, the game ball wins at the start winning port provided in the normal variable winning ball apparatus 6). After that, based on the fact that the variable display start condition (for example, the previous special figure game or the big hit gaming state by the special symbol display device 4 is completed) is established, a plurality of types of identification information (for example, special A variable display device (for example, a special symbol display device 4) that variably displays symbols, etc., and a specific game state (for example, a jackpot symbol) that is advantageous to the player after the display result of the identification information becomes a specific display result (for example, a jackpot symbol). For example, a gaming machine (for example, a pachinko gaming machine 1 or the like) that is a big hit gaming state, etc., and a gaming control microcomputer (for example, a gaming control microcomputer) Computer 100), a reference clock signal output means (eg, reference clock signal generation circuit 111) that outputs a reference clock signal (eg, reference clock signal CLK) having a predetermined period, and a random number (eg, a random number value for jackpot determination) R1 etc.) and a game control board (for example, the main board 11) mounted with a random number circuit (for example, the random number circuit 112). The random number circuit receives the reference clock signal from the reference clock signal output means. Random number generation clock signal generation means (for example, clock signal output circuit 171) for generating a random number generation clock signal (for example, clock signal S1) by dividing, and the random number generated by the random number generation clock signal generation means Based on the input of the clock signal for generation, the display result in the variable display is converted to the specific display result. Specific display result determination numerical data (e.g., count value C, etc.) used when determining whether or not to be determined is predetermined from a predetermined initial value to a predetermined final value within a predetermined updateable range. Specific display result determination numerical data updating means (for example, a random number generation circuit 173) that cyclically updates in accordance with the order and specific display result determination numerical data updated by the specific display result determination numerical data update means are stored. Display result determination numerical value storage means (for example, a random value register 176), and the game control microcomputer is configured to cause the random number circuit to generate the random number after power supply to the game machine is started. Random circuit setting means for setting (for example, the part where the CPU 103 executes the random number initial setting process in step S21) and the random circuit setting After the setting by the means, a timer interrupt process execution permission means (for example, a part where the CPU 103 executes the process of step S24) that permits execution of a timer interrupt process that occurs periodically, and the execution of the timer interrupt process are performed. The execution condition determining means for determining whether or not the variable display execution condition is satisfied (for example, the part where the CPU 103 executes the process of step S261), and the execution condition determining means for executing the variable display execution condition. Display result determination numerical value reading means for reading specific display result determination numerical data from the display result determination numerical value storage means (for example, a portion where the CPU 103 executes the process of step S302, etc.) ) And the specific display result determination numerical data read by the display result determination numerical value reading means. Specific display result determination means for determining whether or not the display result in the variable display is set as the specific display result (for example, by the CPU 103). A portion for executing the processing of step S404) and signal level detection means (for example, the CPU 103 performs processing of steps S221 to S226) for detecting a change in the level of the random number generation clock signal generated by the random number generation clock signal generation means. And an abnormality detecting means for detecting that an abnormality has occurred in the random number circuit because a change in the level of the random number generating clock signal is not detected for a predetermined period or longer by the signal level detecting means. For example, when the CPU 103 determines Yes in step S226, steps S227 to S The random number circuit setting means sets the predetermined initial value to a predetermined value set in advance, or unique identification information given to each game control microcomputer look including the initial value setting means (e.g. CPU103 and portions for performing the process of step S103 to S106) of performing one of setting a value based on, the game machine further, dispensing apparatus which performs dispensing of game media ( For example, a payout motor 51 and the like, and a payout control board (for example, the payout control board 15) on which a payout control microcomputer (for example, the payout control microcomputer 150) that controls the payout operation by the payout device is provided. The game control microcomputer is a serial communication unit that performs serial communication with the payout control microcomputer. Communication control means (for example, the CPU 103 performs the serial communication initial setting process in step S22 and the interrupt initial setting process in step S23). The serial communication circuit includes an interrupt request for notifying the communication control means of an interrupt request according to the established interrupt request condition when one of a plurality of interrupt request conditions is established. The interrupt request notified by the interrupt request notifying means includes notifying means (for example, SIST1 of the serial status register 204), and the processing corresponding to the occurrence of the error is satisfied when an error occurs in the serial communication. For causing the communication control means to execute (For example, an interrupt request at the time of a parity error, an interrupt request at the time of an overrun error, an interrupt request at the time of a framing error, an interrupt request at the time of a noise error, etc.). Interrupt processing sequence control means for preferentially executing interrupt processing based on the error interrupt request over processing based on an interrupt request of a type different from the error interrupt request when the types of interrupt requests are notified at the same time ( For example, when the read value in step S121 by the reset / interrupt controller 102 or the CPU 104 is other than “06h” or “07h”, the process of step S122 is executed), and the error is notified by the interrupt request notification unit. When the interrupt request is notified, the error interrupt request As an interrupt process based, including said serial communication circuit error interrupt processing means for stopping the execution of the serial communication operation by (e.g. CPU104 and portions for performing the process of step S41, S42).

  The present invention has the following effects.

According to the configuration of the first aspect, after the power supply to the gaming machine is started, before the timer interrupt process execution permitting unit is permitted to execute the timer interrupt process, the random number circuit setting unit is connected to the random number circuit. It is configured to make settings for generating random numbers. In the random number circuit setting means, the initial value setting means updates the specific display result determination numerical data by the specific display result determination numerical data update means to a predetermined predetermined value or for game control. A setting is made as to whether the value is based on unique identification information assigned to each microcomputer.
Thereby, the initial value of the random number that starts updating after the power supply is started can be made different for each gaming machine, and is used for determining whether or not the display result in the variable display is the specific display result. It is possible to increase the randomness of the generated random number and prevent the specific display result from being illegally generated.
The effect determining means executes the predetermined effect by determining whether or not the effect determination numerical data updated in synchronization with the specific display result determination numerical data matches the predetermined effect determination value data. Decide whether or not to do. Therefore, when a predetermined effect is not executed over a long period of time, or when a predetermined effect is executed over a long period of time, it can be estimated that an abnormality has occurred in the random number generation operation in the random number circuit, and there is an abnormality in the random number circuit. When this occurs, it is possible to prevent the player from suffering a significant disadvantage. Here, by setting the probability that the predetermined effect is executed higher than the probability that the variable display result of the identification information becomes the specific display result, an abnormality occurs in the random number circuit when the specific display result is not obtained over a long period of time. The occurrence of an abnormality can be estimated in a shorter period than when it is estimated that it has occurred.
In addition, since a special configuration for monitoring the specific display result determination numerical data read from the display result determination numerical storage means is not required, an increase in manufacturing cost can be suppressed.
Furthermore, when multiple types of interrupt requests are simultaneously notified from the interrupt request notification unit to the communication control unit, the interrupt processing based on the error interrupt request by the interrupt processing sequence control unit is different from the error interrupt request. It is executed with priority over the processing based on. Then, as interrupt processing based on the error interrupt request, the error interrupt processing execution means stops execution of the serial communication operation by the serial communication circuit.
Thus, when an error interrupt request is notified, the serial communication operation by the serial communication circuit is immediately stopped, thereby preventing erroneous information from being transmitted due to the occurrence of an abnormality in the serial communication.

According to the configuration of the second aspect, after the power supply to the gaming machine is started, before the timer interrupt process execution permission unit is permitted to execute the timer interrupt process, the random number circuit setting unit is connected to the random number circuit. It is configured to make settings for generating random numbers. In the random number circuit setting means, the initial value setting means updates the specific display result determination numerical data by the specific display result determination numerical data update means to a predetermined predetermined value or for game control. A setting is made as to whether the value is based on unique identification information assigned to each microcomputer.
Thereby, the initial value of the random number that starts updating after the power supply is started can be made different for each gaming machine, and is used for determining whether or not the display result in the variable display is the specific display result. It is possible to increase the randomness of the generated random number and prevent the specific display result from being illegally generated.
Further, the numerical data holding unit stores the specific display result determination numerical data read by the display result determination numerical value reading unit, and the specific display result determination numerical data and the numerical value read by the display result determination numerical value reading unit When the numerical data for specific display result determination held in the data holding means does not match, the numerical data for specific display result determination to be held in the numerical data holding means is newly displayed by the held numerical data update means. While updating to the specific display result determination numerical data read by the reading means, the number of times that the matching is continuously determined is counted by the matching continuous number counting means. The abnormality detecting means detects the occurrence of abnormality in the random number circuit by making a determination that the number of times counted by the coincidence continuous number counting means exceeds a predetermined coincidence continuous upper limit value. .
As described above, when the same specific display result determination numerical data is read over a predetermined period, it is possible to detect the occurrence of an abnormality in the configuration included in the random number circuit, for example, the specific display result determination numerical data update unit. it can.
Furthermore, when multiple types of interrupt requests are simultaneously notified from the interrupt request notification means to the communication control means, the interrupt processing based on the error interrupt request by the interrupt processing order control means is different from the error interrupt request. It is executed with priority over the processing based on. Then, as interrupt processing based on the error interrupt request, the error interrupt processing execution means stops execution of the serial communication operation by the serial communication circuit.
Thus, when an error interrupt request is notified, the serial communication operation by the serial communication circuit is immediately stopped, thereby preventing erroneous information from being transmitted due to the occurrence of an abnormality in the serial communication.

According to the configuration of the third aspect, after the power supply to the gaming machine is started, before the timer interrupt process execution permitting unit is permitted to execute the timer interrupt process, the random number circuit setting unit is connected to the random number circuit. It is configured to make settings for generating random numbers. In the random number circuit setting means, the initial value setting means updates the specific display result determination numerical data by the specific display result determination numerical data update means to a predetermined predetermined value or for game control. A setting is made as to whether the value is based on unique identification information assigned to each microcomputer.
Thereby, the initial value of the random number that starts updating after the power supply is started can be made different for each gaming machine, and is used for determining whether or not the display result in the variable display is the specific display result. It is possible to increase the randomness of the generated random number and prevent the specific display result from being illegally generated.
Further, the level change of the random number generation clock signal generated by dividing the reference clock signal by the random number generation clock signal generation unit is detected by the signal level detection unit, and the level change of the random number generation clock signal is not less than a predetermined period. When not detected, the abnormality detection means detects the occurrence of abnormality in the random number circuit.
As described above, when the level of the random number generation clock signal does not change for a predetermined period or more, occurrence of an abnormality in the configuration included in the random number circuit such as the random number generation clock signal generation unit can be detected.
Furthermore, when multiple types of interrupt requests are simultaneously notified from the interrupt request notification unit to the communication control unit, the interrupt processing based on the error interrupt request by the interrupt processing sequence control unit is different from the error interrupt request. It is executed with priority over the processing based on. Then, as interrupt processing based on the error interrupt request, the error interrupt processing execution means stops execution of the serial communication operation by the serial communication circuit.
Thus, when an error interrupt request is notified, the serial communication operation by the serial communication circuit is immediately stopped, thereby preventing erroneous information from being transmitted due to the occurrence of an abnormality in the serial communication.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a front view of a pachinko gaming machine 1 according to the present embodiment, and shows an arrangement layout of main members. The pachinko gaming machine (gaming machine) 1 is roughly composed of a gaming board (gauge board) 2 constituting a gaming board surface and a gaming machine frame (base frame) 3 for supporting and fixing the gaming board 2. The game board 2 is formed with a substantially circular game area surrounded by guide rails.

  A special symbol display device 4 for variably displaying a special symbol as identifiable identification information is provided above the central position of the game area. Below the special symbol display device 4, there is provided an image display device 5 that can perform variable display of decorative symbols different from the special symbol, image display that is a predetermined effect display, and the like. Below the image display device 5, an ordinary variable winning ball device 6 that forms a start winning opening is arranged. Below the ordinary variable winning ball apparatus 6, a special variable winning ball apparatus 7 that forms a large winning opening and a normal symbol display 40 are provided.

  The special symbol display device 4 includes, for example, 7-segment or dot matrix LEDs. The special symbol display device 4 is, for example, “0” to “9” in a special game as a variable display game performed based on the fact that the start condition is established by winning a game ball in the normal variable winning ball device 6. The special symbol which consists of the number etc. which show and functions as several types of identification information which can identify each is variably displayed. Each special symbol is assigned a symbol number corresponding to each special symbol, for example, the same number as the number indicated by each symbol. The special symbol display device 4 is configured to variably display more types of symbols such as numbers indicating “00” to “99”, for example, in order to make it difficult for the player to grasp a specific stop symbol. It may be.

  In the special symbol game performed by the special symbol display device 4, when a predetermined time elapses after the variation of the special symbol is started, the fixed special symbol that is a variable symbol display result is stopped (derived display). At this time, if a special symbol (big hit symbol) is stopped and displayed as a confirmed special symbol in the special symbol game on the special symbol display device 4, it becomes a “big hit” as a specific display result, and a special symbol other than the big bonus symbol is displayed. If it is stopped, it will be “lost”. When the variation display result in the special figure game is “big hit”, the big hit game state as the specific game state is controlled by opening and closing the opening / closing plate of the special variable winning ball apparatus 7. In the pachinko gaming machine 1 according to this embodiment, as a specific example, a special symbol indicating “7” is a jackpot symbol, and a special symbol indicating other numerical values is a lost symbol.

  In the jackpot gaming state based on the special symbol indicating “7” which is a jackpot symbol as a confirmed special symbol in the special symbol game by the special symbol display device 4, by the opening / closing plate of the special variable winning ball device 7, A game ball that drops on the surface of the game board 2 during a predetermined opening period (for example, 29 seconds) or a period until a predetermined number (for example, 10) of winning balls are generated and the large winning opening is opened. Is received, and it becomes possible to enter the grand prize opening, and then the round is closed by closing the grand prize opening. The round as the open / close cycle can be repeated up to a predetermined upper limit number (for example, 15 rounds).

  The image display device 5 is composed of, for example, an LCD or the like, and may be any device that performs screen display by a dot matrix method using a large number of pixels (pixels). On the display screen of the image display device 5, each can be identified by, for example, a variable display section as a display area divided into three corresponding to the special symbol variation display in the special symbol game by the special symbol display device 4. A variable display that displays various types of decorative designs in a variable manner is performed. As a specific example, variable display portions “left”, “middle”, and “right” are arranged on the image display device 5, and decorative symbols are variably displayed on the variable display portions. When the special symbol variation display on the special symbol display device 4 is started, the decorative symbol variation display (for example, switching) is displayed on each of the “left”, “middle”, and “right” variable display portions in the image display device 5. Display and scroll display) is started, and thereafter, when the confirmed special symbol is stopped and displayed as a special symbol variation display result in the special symbol display device 4, "left", "middle", "right" in the image display device 5 ”Is stopped and displayed on each variable display section, and the combination of decorative designs that are variable display results is stopped and displayed (derived display).

  For example, in each of the “left”, “middle”, and “right” variable display portions, symbols representing ten types of numbers “0” to “9” are displayed as decorative symbols in a variable manner. Each decorative symbol is given a symbol number corresponding to each decorative symbol, for example, the same number as the number indicated by each symbol. Then, in each of the “left”, “middle”, and “right” variable display sections, when the decorative symbol variation display is started, for example, the display from which the number indicated by the symbol is changed to the larger one is switched or scrolled. When the decorative symbol indicating “9” is displayed, the decorative symbol indicating “0” is displayed next. Then, when the special symbol determined in the special symbol game on the special symbol display device 4 is a big hit symbol, that is, when a big hit occurs, a fixed combination of “left”, “middle” and “right” is determined by a predetermined combination. The decorative design is stopped and displayed. Specifically, when the confirmed special symbol in the special symbol game is a special symbol indicating “7” as a jackpot symbol, the same decorative symbol is displayed on the “left”, “middle”, and “right” variable display portions. Is stopped.

  In this embodiment, the decorative symbol indicating “1”, “3”, “5”, “7” or “9” having an odd symbol number is used as a decorative symbol (probable variable symbol) for probability variation big hit, A decorative symbol indicating “0”, “2”, “4”, “6” or “8” having an even symbol number is normally used as a decorative symbol for a big hit (normal symbol). When the same probability variation symbol (decorative symbol combination symbol ornament) is stopped and displayed on the variable display portion of “left”, “middle”, and “right” as a variable symbol display result, a probability variation big hit is obtained. When a promising big hit is reached, after the big hit gaming state based on the probable big hit is finished, until a special number of games (for example, 100 times) is executed or until a variable display result in the special figure game becomes a big hit As one of the special game states, a high probability state (probability improvement state) in which probability variation control (probability variation control) is continuously performed is obtained. In this high probability state, the probability that the jackpot symbol is stopped and displayed as a variable display result in the special figure game and is controlled to the jackpot gaming state is improved as compared with the normal gaming state. The normal gaming state is a gaming state other than the big hit gaming state or the special gaming state, and the probability that the big hit symbol is stopped and displayed as a confirmed special symbol in the special figure game, such as immediately after the power is turned on. It is controlled in the same way as the initial setting state.

  When the same normal symbol (decorative symbol of a combination of normal jackpots) is stopped and displayed on the variable display portions “left”, “middle”, and “right” as a variable display result of the decorative symbols, a normal big hit is obtained. Since the probability change control is not performed when the normal big hit, the probability that the variable display result in the special figure game becomes a big hit and is controlled to the big hit gaming state is not improved. On the other hand, when a big hit is made, a high probability state is until a predetermined number of times (for example, 100 times) the execution of a special figure game is started, or until the execution of a special figure game that is a big hit is started. As one of the different special game states, a time reduction state in which time reduction control (time reduction control) is continuously performed may be set. In the time reduction state where the time reduction control is performed, the probability of being a big hit in each special figure game and being controlled to the big hit gaming state is the same as the normal gaming state, but the special symbol variable display is started in the special figure game. The variable display time, which is the time from when the displayed special symbol as the display result is stopped and displayed, is controlled to be shorter than the normal gaming state.

  In each of the “left”, “middle”, and “right” variable display portions, a plurality of types of symbols representing alphabets may be displayed as decorative designs, and a plurality of types of character designs related to a predetermined motif may be displayed. May be variably displayed as a decorative pattern. Further, in the image display device 5, during the execution of the special symbol game by the special symbol display device 4, it is possible to perform effect display in any of various effect modes. The variable display unit may be a fixed area, but may move or change in size in the display area of the image display device 5 while the game is in progress.

  In addition, the image display device 5 has a special symbol start memory display area for displaying the number of effective winning balls, that is, the number of reserved memories (starting winning memory number) entered into the starting winning opening provided in the normal variable winning ball device 6. It may be provided. In the special symbol start memory display area, a winning display is performed in response to an effective start winning when the number of reserved memories is less than a predetermined upper limit (for example, “4”). As a specific example, the display that is normally blue is changed to a red display. In this case, by providing the decorative symbol display area (variable display portion) and the special symbol start memory display area separately, the number of reserved memories can be displayed during variable display of decorative symbols. The special symbol start memory display area may be provided in a part of the decorative symbol display area. In this case, the display of the reserved storage number may be interrupted during the variable display of the decorative design. In this way, when the number of reserved memories is displayed in the special symbol start memory display area provided in the image display device 5, the special effect control microcomputer 120 (FIG. 2) mounted on the effect control board 12 is used for special display. The display operation of the number of reserved memories in the symbol start memory display area is controlled. On the other hand, even when the reserved memory number is displayed in the special symbol start memory display area, a display device (special memory) that displays the reserved memory number under the control of the game control microcomputer 100 (FIG. 2) mounted on the main board 11. A symbol start memory display) may be provided separately from the image display device 5.

  The normal variable winning ball apparatus 6 is a tulip-type accessory (ordinary electric motor) having a pair of movable wing pieces that are controlled to move between a vertical (normally open) position and a tilt (enlarged open) position by a solenoid 81 (FIG. 2). (Community). The normal variable winning ball apparatus 6 is configured to wait until a predetermined time elapses when the display result is “winning” in the variable symbol display (ordinary symbol game) on the normal symbol indicator 40. By controlling to the tilting position, it becomes easier for the game ball to win the start winning opening than when the movable wing piece is set to the vertical position. The game ball that has won the normal variable winning ball apparatus 6 is detected by the start port switch 22 (FIG. 2). Based on the detection of the game ball by the start port switch 22, a predetermined number (for example, four) of prize balls are paid out.

  The special variable winning ball apparatus 7 includes an opening / closing plate that opens and closes a large winning opening by a solenoid 82 (FIG. 2). This opening / closing plate is used for a predetermined period or a period until a predetermined number of winning balls are generated when a big hit gaming state is obtained based on a variation display result in a special symbol game by the special symbol display device 4. As a first state which is advantageous to the user, the large winning a prize opening is opened by the solenoid 82 and then closed. On the other hand, at a normal time, for example, before the big hit gaming state occurs after the power of the pachinko gaming machine 1 is turned on, the prize winning opening is closed by the solenoid 82 as a second state disadvantageous to the player. When a game ball is won at the special winning opening when the opening / closing plate opens the large winning opening at the special variable winning ball apparatus 7, the game switch is detected by the count switch 24 (FIG. 2). Based on the above, a predetermined number (for example, 15) prize balls are paid out. Of the game balls that were won at the grand prize opening and led to the back of the game board 2, those that entered one area (V winning area; special area) were detected by the V winning switch 23 (FIG. 2). A game ball that is later detected by the count switch 24 and enters the other area may be detected by the count switch 24 as it is. In this case, a solenoid for switching the route in the special winning opening may be provided on the back of the game board 2. Alternatively, it may be possible to always shift to the next round in a round other than the final round in the big hit gaming state without providing the V winning area.

  The normal symbol display 40 is composed of, for example, LEDs and the like. Lighting, blinking, coloring, etc. are controlled. When display is performed with a predetermined hit pattern in the normal game, the display result in the normal game is “win”. Here, in the above-described high probability state and time reduction state, the variable display time in the normal game by the normal symbol display device 40 is shorter than that in the normal game state, and the display result is the winning symbol in each normal game. May be improved. At this time, the tilting time of the movable wing piece in the normal variable winning ball apparatus 6 may be longer than that in the normal gaming state, and the number of tilts may be increased compared to that in the normal gaming state. As described above, in the high probability state and the time reduction state, the gaming state is advantageous to the player, which is different from the big hit gaming state. Here, in the time shortening state, probability variation control is not performed, and the probability of being in the big hit gaming state is the same as in the normal gaming state, so the high probability state is more advantageous for the player than the time shortening state.

  In addition to the above-described configuration, the game area of the game board 2 is provided with a windmill having a decorative lamp, an outlet, and the like. Two speakers 8L and 8R that emit sound effects are provided on the left and right upper portions outside the game area. A game effect lamp 9 that is lit or blinks is provided on the outer periphery of the game area. At the lower right position outside the game area, there is provided an operation knob 30 that is operated by a player or the like to drive the launch motor 61 (FIG. 2) to fire the game ball toward the game area.

  Further, FIG. 1 also shows a prepaid card unit (hereinafter referred to as a card unit) 70 that is installed adjacent to the pachinko gaming machine 1 and enables lending of a ball by inserting a prepaid card. The card unit 70 includes a usable indicator lamp that indicates whether or not the card unit 70 is in a usable state, a connection table direction indicator that indicates which side of the pachinko gaming machine 1 corresponds to the card unit 70, and the card unit 70. When checking the card insertion indicator lamp indicating that a card is inserted in the card, the card insertion slot into which the card as a recording medium is inserted, and the card reader / writer mechanism provided on the back of the card insertion slot A card unit lock or the like for opening the card unit 70 is provided.

  The pachinko gaming machine 1 includes various power supply boards 10, a main board 11, an effect control board 12, an audio control board 13, a lamp control board 14, a payout control board 15, and a launch control board 17 as shown in FIG. A control board is mounted. Between the main board 11 and the effect control board 12, a relay board 18 for relaying various control signals transmitted from the main board 11 to the effect control board 12 is also provided. The interface board 20 is interposed between the payout control board 15 and the card unit 70. Note that the audio control board 13 and the lamp control board 14 may be configured as independent boards that are separate from the effect control board 12, or may be integrated into the effect control board 12 and configured as one board. In addition, various control boards such as an information terminal board are disposed on the back surface of the pachinko gaming machine 1.

  The power supply board 10 is installed independently of each control board such as the main board 11, the effect control board 12, and the payout control board 15, and generates a voltage used by each control board and mechanism component in the pachinko gaming machine 1. For example, the power supply board 10 generates AC 24 V, VLP (DC +24 V), VSL (DC +30 V), VDD (DC +12 V), VCC (DC +5 V), and VBB (DC +5 V) as shown in FIG. For example, as shown in FIG. 3, the power supply board 10 includes a transformer circuit 301, a DC voltage generation circuit 302, a power supply monitoring circuit 303, and a clear switch 304. Further, the power supply substrate 10 may be provided with a capacitor serving as a backup power supply. For example, this capacitor may be charged from a power supply line of VBB (DC + 5V). In addition, the power supply board 10 may be provided with a power switch for executing or shutting off power supply to each control board and the mechanical components in the pachinko gaming machine 1. Alternatively, the power switch may be provided outside the power supply board 10 in the pachinko gaming machine 1.

  For example, the transformer circuit 301 may be configured to include a transformer to which commercial power is applied to the input side (primary side), a varistor as an overvoltage protection circuit provided on the input side of the transformer, and the like. Here, the transformer included in the transformer circuit 301 may be any one that electrically insulates the commercial power supply from the power supply substrate 10. The transformer circuit 301 generates AC 24V as its output voltage. The DC voltage generation circuit 302 includes, for example, a rectifying / smoothing circuit that generates VSL by rectifying and boosting AC 24V with a rectifying element. VSL is used as a power supply voltage for driving the solenoid. Further, the DC voltage generation circuit 302 includes a rectifier circuit that generates VLP by rectifying AC24V with a rectifier, for example. VLP is used as a power supply voltage for lighting the lamp. In addition, the DC voltage generation circuit 302 includes a DC-DC converter that generates VDD and VCC based on, for example, VSL. This DC-DC converter includes, for example, one or a plurality of switching regulators and a relatively large capacitor connected to the input side of the switching regulator, and power supply to the pachinko gaming machine 1 from the outside is stopped. Sometimes, it may be configured so that the direct current voltage such as VSL, VDD, VBB, etc. decreases relatively slowly. The VDD is supplied to various switches that detect game media, such as the gate switch 21, the start port switch 22, the V winning switch 23, and the count switch 24, and is used to operate these switches.

  As shown in FIG. 3, AC24V output from the transformer circuit 301 is transmitted to the payout control board 15 via a predetermined connector or a power supply line, for example. The VLP is transmitted to the lamp control board 14 via, for example, a predetermined connector or a power supply line. VSL, VDD, and VCC are transmitted to the main board 11, the lamp control board 14, and the payout control board 15 through, for example, predetermined connectors and power supply lines. The VBB is transmitted to the main board 11 and the payout control board 15 through, for example, a predetermined connector and a power supply line. Note that each voltage may be supplied to the effect control board 12 and the sound control board 13 via the lamp control board 14.

  The power monitoring circuit 303 is configured by using, for example, a power failure monitoring reset module IC, and is a circuit that realizes a power monitoring unit that outputs a power interruption signal. For example, the power supply monitoring circuit 303 has a predetermined period of time (56 milliseconds as an example) during which the predetermined voltage (VLP as an example) used in the pachinko gaming machine 1 is equal to or lower than a predetermined value (+20 V as an example). When the above is continued, a power-off signal is output. Alternatively, the power monitoring circuit 303 may output a power-off signal immediately when a predetermined voltage used in the pachinko gaming machine 1 becomes a predetermined value or less. The power-off signal may be an electrical signal that is turned on when it is at a low level, for example. The power cut-off signal output from the power supply monitoring circuit 303 is amplified by, for example, an output driver circuit mounted on the power supply board 10 and then transmitted to the payout control board 15 via a predetermined connector or signal line, thereby giving out payout control. The signal is transmitted from the substrate 15 to the main substrate 11. The condition for detecting the stop of the supply of power supplied to the pachinko gaming machine 1 from the outside is not limited to the fact that the predetermined voltage used in the pachinko gaming machine 1 has become a predetermined value or less. Any condition can be used as long as it is possible to detect that has stopped. For example, the AC wave such as AC 24V may be monitored to detect that the AC wave has stopped, or the signal obtained by digitizing the AC wave may be monitored and the AC signal may be generated when the digital signal becomes flat. It may be a detection condition for the interruption.

  The power supply monitoring circuit 303 may output a reset signal when, for example, a predetermined voltage (VCC as an example) becomes equal to or lower than a predetermined value (as an example, + 5V or more). The reset signal may be an electric signal that is turned on when the reset signal becomes low level, for example. The reset signal output from the power supply monitoring circuit 303 is amplified by, for example, an output driver circuit mounted on the power supply board 10, and then, via a predetermined connector or signal line, the main board 11, the lamp control board 14, and the payout control board. 15 is transmitted. It should be noted that a reset signal may be transmitted to the effect control board 12 via the lamp control board 14. Furthermore, the circuit that outputs the reset signal may be configured by using a watchdog timer built-in IC provided separately from the power supply monitoring circuit 303, a system reset IC, or the like.

  When the power supply to the pachinko gaming machine 1 is stopped, the power monitoring circuit 303 outputs a reset signal (sets to a low level) when a predetermined period has elapsed since the power-off circuit 303 outputs a power-off signal (sets to a low level) ) In this predetermined period, for example, the game control microcomputer 100 mounted on the main board 11 and the payout control microcomputer 150 mounted on the payout control board 15 perform predetermined power-off processing (for example, in FIG. 28). It is sufficient if the time is sufficient to execute the main-side power-off process in step S26 shown in FIG. That is, the power monitoring circuit 303 outputs a power-off signal as a power failure signal, and after the game control microcomputer 100 and the payout control microcomputer 150 complete execution of predetermined power-off processing, Output the reset signal (set to low level). The game control microcomputer 100 and the payout control microcomputer 150 that have received the reset signal output from the power supply monitoring circuit 303 are in an operation stop state, and execution of various control processes is stopped. In addition, when the power supply to the pachinko gaming machine 1 is started, for example, when a predetermined voltage (VCC as an example) exceeds a predetermined value (+5 V as an example), the power monitoring circuit 303 stops outputting the reset signal (high Level).

  FIG. 4 is a timing diagram schematically showing the states of AC 24 V, VLP, VCC, reset signal, and power-off signal when power supply to the pachinko gaming machine 1 is started and when power supply is stopped. is there. As shown in FIG. 4, when the power supply to the pachinko gaming machine 1 is started, VLP and VCC gradually reach specified values (DC + 24V and DC + 5V). At this time, when VLP exceeds the first predetermined value, the power supply monitoring circuit 303 stops outputting the power-off signal (sets it to a high level) and turns it off. When VCC exceeds the second predetermined value, the power supply monitoring circuit 303 stops outputting the reset signal (sets it to a high level) and turns it off. On the other hand, when the power supply to the pachinko gaming machine 1 is stopped, VLP and VCC gradually decrease. At this time, when the VLP drops to the first predetermined value, the power supply monitoring circuit 303 outputs the power-off signal as an ON state (sets it to a low level). Further, when VCC decreases to the second predetermined value, the power supply monitoring circuit 303 outputs the reset signal as an ON state (sets to a low level).

  The clear switch 304 included in the power supply substrate 10 illustrated in FIG. 3 has a push button structure, for example, and outputs a clear signal in response to an operation such as pressing. The clear signal may be an electric signal that is turned on when the clear signal is at a low level, for example. The clear signal output from the clear switch 304 is transmitted to the main board 11 via a predetermined connector or signal line, for example, and is transmitted from the main board 11 to the payout control board 15. When the clear switch 304 is not operated, the output of the clear signal is stopped (set to a high level). Note that the clear switch 304 may have a configuration other than a push button structure (for example, a slide switch structure, a toggle switch structure, a dial switch structure, or the like).

  A main board 11 shown in FIG. 2 is a main-side control board on which various circuits for controlling the progress of the game in the pachinko gaming machine 1 are mounted. The main board 11 is a sub-side mainly composed of a random number setting function used in a special game, a function of inputting a signal from a switch arranged at a predetermined position, an effect control board 12, a payout control board 15, and the like. A control board is provided with a function of outputting and transmitting a control command as an example of command information as a control signal, and a function of outputting various information to a hall management computer. In addition, the main board 11 controls the special symbol display on the special symbol display device 4 by controlling the lighting / extinguishing of each segment constituting the special symbol display device 4, while the normal symbol display 40 is turned on. By controlling / flashing / coloring control, the normal symbol display on the normal symbol display 40 is controlled.

  As shown in FIG. 2, wiring for receiving detection signals from the gate switch 21, the start port switch 22, the V winning switch 23, and the count switch 24 is connected to the main board 11. Note that the gate switch 21, the start port switch 22, the V winning switch 23, and the count switch 24 have any configuration that can detect a game ball as a game medium, such as a sensor. That's fine. Here, the start opening switch 22 detects that the game ball has won the start winning opening, and outputs a start winning signal indicating that a start condition for executing the special figure game by the special symbol display device 4 is satisfied. This is a start winning detection switch.

  In addition, on the main board 11, wiring for transmitting a command signal for performing tilt control of the movable blade piece in the normal variable winning ball apparatus 6 to the solenoid 81, and opening / closing of the opening / closing plate in the special variable winning ball apparatus 7 A wiring for transmitting a command signal for performing control to the solenoid 82 is connected. Furthermore, wiring for transmitting a command signal for performing display control of the special symbol display device 4 and the normal symbol display 40 is connected to the main board 11.

  A control signal output from the main board 11 toward the effect control board 12 is relayed by the relay board 18. Here, the main board 11 is provided with a main board side connector corresponding to the relay board 18, for example, and an output buffer circuit is connected between the main board side connector and the game control microcomputer 100. May be. This output buffer circuit can pass a control signal only in the direction from the main board 11 to the effect control board 12 via the relay board 18, for example, and prevents the signal input from the relay board 18 to the main board 11. . Therefore, there is no room for signals to be transmitted from the production control board 12 or the relay board 18 side to the main board 11 side.

  The relay board 18 only needs to be provided with a transmission direction regulating circuit for each wiring for transmitting a control signal output from the main board 11 to the effect control board 12, for example. Each transmission direction regulating circuit has an anode connected to a main board connector provided corresponding to the main board 11 and a cathode connected to an effect control board connector provided corresponding to the effect control board 12. The diode is composed of a resistor having one end connected to the cathode of the diode and the other end connected to the ground (GND). With this configuration, each transmission direction regulating circuit can prevent signals from being input from the effect control board 12 to the relay board 18 and pass signals only in the direction from the main board 11 to the effect control board 12. Therefore, there is no room for signals to be transmitted from the production control board 12 side to the main board 11 side. In order to prevent illegal signal input to the main board, a one-way data transfer means for restricting signal input from the sub board to the main board between the main board and the sub board has already been proposed. (For example, see JP-A-8-224339). However, since there is nothing that restricts signal input to the main board between the main board and the one-way data transfer means, it is possible to input illegal signals to the main board by modifying the one-way data transfer means. Was possible. In this embodiment, a transmission direction regulating circuit is provided for each wiring for transmitting a control signal in the relay board 18, and an output buffer circuit is provided between the game control microcomputer 100 and the main board side connector on the main board 11. By providing, illegal signal input from the outside to the main board 11 can be more reliably prevented.

  The effect control board 12 is a sub-side control board independent of the main board 11, receives a control command transmitted from the main board 11 via the relay board 18, and receives the image display device 5, speakers 8L, 8R. In addition, various circuits for controlling electric parts for production such as the game effect lamp 9 are mounted. That is, the effect control board 12 has a function of controlling the display operation in the image display device 5, the sound output operation from the speakers 8 </ b> L and 8 </ b> R, the lamp lighting operation and the light-off operation in the game effect lamp 9, and the like. The effect control board 12 is connected to wiring for transmitting a control signal to the sound control board 13 and the lamp control board 14, wiring for transmitting an image data signal to the image display device 5, and the like.

  Various control commands and notification signals are transmitted between the main board 11 and the payout control board 15 by, for example, bidirectional serial communication. The payout control board 15 is a sub-side control board independent of the main board 11, receives a control command and a notification signal transmitted from the main board 11, and controls the payout operation of the game ball by the payout motor 51. Various circuits are installed. That is, the payout control board 15 has a function of controlling the award ball payout operation by the payout motor 51. Further, the payout control board 15 has a function of controlling the ball lending operation by controlling the driving of the payout motor 51 according to the communication result with the card unit 70 via the interface board 20. The payout control board 15 receives wiring for receiving detection signals from the full tank switch 26 and the ball break switch 27, and detection signals from the payout motor position sensor 71, the payout count switch 72, and the error release switch 73. Wiring for is connected. In addition, a wiring for transmitting a command signal for performing payout control of the game ball in the payout motor 51 and a command signal for performing display control in the error display LED 74 are transmitted to the payout control board 15. Are connected to the card unit 70 via the interface board 20.

  Here, the full tank switch 26 is installed on the side wall of the surplus ball passage that communicates between the striking ball supply tray and the surplus ball receiving tray, for example, below the back of the game board 2, and detects the full tank of the surplus ball receiving tray. Is. A lot of game balls based on award balls or ball lending requests are paid out, the batting supply tray becomes full, and after the game balls reach the contact point, when the game balls are paid out, the game balls pass through the surplus ball passage. It is led to the extra ball tray. When the game ball is further paid out, for example, a predetermined sensing lever presses the full switch 26 to turn on.

  In addition, the ball break switch 27 is installed downstream of the guide rail that guides the game ball to the payout device in which the payout motor 51 is installed, for example, on the back of the game board 2, and via a curve rod downstream of the guide rail. This is for detecting the presence or absence of game balls in two rows of ball passages communicated with each other. As an example, the ball break switch 27 is locked by a locking piece at a position where it can be detected that 27 to 28 game balls are present in the ball path, and the maximum payout number (for example, 100) It is possible to confirm that at least 25 pieces corresponding to a circle are secured. The guide rail guides a game ball from a storage tank that stores a game ball as a supply ball above the back of the game board 2 to a payout device, and a payout motor 51 is provided below the ball passage. The payout device in which is installed is fixed.

  The error release switch 73 is a switch for releasing the error state by software reset when the payout control microcomputer 150 is controlled to a predetermined error state. The error display LED 74 is composed of, for example, a 7-segment LED, and is used to display error codes corresponding to various errors based on an error flag set by the payout control microcomputer 150.

  The launch control board 17 shown in FIG. 2 is for controlling the launch operation of the game ball by a predetermined launch device in accordance with the operation amount of the operation knob 30. For example, wiring for transmitting drive signals from the power supply board 10 or the main board 11, wiring for transmitting connection signals from the card unit 70 via the interface board 20 and the payout control board 15, and operation are provided on the launch control board 17. The wiring from the knob 30 is connected, and the wiring to the firing motor 61 is connected. The connection signal from the card unit 70 may be branched by the payout control board 15 and transmitted to the launch control board 17, or from the card unit 70 via the interface board 20 and not via the payout control board 15. May be transmitted to the launch control board 17. The firing control board 17 adjusts the driving force of the firing motor 61 in accordance with the operation amount of the operation knob 30. For example, the launch motor 61 elastically deforms the launch spring by a driving force adjusted by the launch control board 17, and transmits the biasing force of the launch spring to the hitting hammer to hit the game ball, thereby operating the game ball on the operation knob 30. It is fired toward the game area at a speed corresponding to the operation amount.

  The control command transmitted from the main board 11 to the effect control board 12 via the relay board 18 is, for example, an effect control command transmitted as an electric signal. The effect control command includes, for example, a display control command used for controlling an image display operation in the image display device 5, a voice control command used for controlling sound output from the speakers 8L and 8R, and a game effect lamp 9. And a lamp control command used for controlling the lighting operation of the decoration LED and the like. FIG. 5 is an explanatory diagram showing an example of the contents of display control commands used in this embodiment. The display control command has, for example, a 2-byte structure, and the first byte indicates MODE (command classification), and the second byte indicates EXT (command type). The first bit (seventh bit [bit 7]) of the MODE data is always “1”, and the first bit of the EXT data is “0”. The form of the display control command shown in FIG. 5 is an example, and other command forms may be used. In this example, the display control command has a 2-byte configuration, but the number of bytes constituting the display control command may be 1 or a plurality of 3 or more. In this embodiment, variable display start commands, display result notification commands, jackpot start commands, jackpot end commands, commands for error notification start # 1 to # 3, and the like are prepared in advance as display control commands.

  In the example illustrated in FIG. 5, the command 80XXh is a variable display start command that is transmitted when the special symbol display device 4 starts the variable symbol special symbol display in the special symbol game. XXh indicates an unspecified hexadecimal number, and may be a value that is arbitrarily set according to the instruction content by the display control command. The variable display start command is, for example, a special symbol variable display time (total variation time), which is a time from when the special symbol display device 4 starts the variable symbol variable display to when the fixed special symbol is stopped and displayed, or a decorative symbol. EXT data indicating whether or not the variable display mode is a reach loss that is lost after reaching, or a normal loss that is lost without reaching, is included.

  Here, the reach means that a decorative display (referred to as a reach variation pattern) that has not yet been derived and displayed when the decorative pattern derived and displayed on the image display device 5 forms a part of the jackpot combination is a variable display. It is a display mode that is being performed, or a display mode in which all or some of the decorative symbols are synchronously displayed while constituting all or part of the jackpot symbol. Specifically, on the combination effective line that has not been stopped yet when the symbols constituting the predetermined jackpot combination are stopped and displayed on some of the variable display portions on the predetermined combination effective line. Display mode in which variable display is performed in the variable display section (for example, "left", "right" variable display sections among "left", "middle", "right" variable display sections provided in the display area Is a display mode in which part of the big hit symbol (for example, “7”) is stopped and displayed, and the “middle” variable display section is still displaying a variable display) or variable on the effective line A display mode (for example, “left”, “middle”, “ The state of change is displayed on all the `` Right '' variable display sections. Is but display mode in variable display is being performed aspects be displayed have all the same decorative pattern). Also, during the reach, unusual effects may be performed with lamps or sounds. This production is called reach production. Further, during the reach, the image display device 5 displays a character (an effect display imitating a person or the like, which is different from the decorative design), changes the display mode of the background, or changes the decorative design. The display mode may be changed. This change in character display, background display mode, and decorative pattern variation mode is referred to as reach effect display.

  The command 90XXh is a display result notification command indicating a confirmed special symbol in the special symbol game on the special symbol display device 4 and whether or not the game state is a probable big hit that becomes a high probability state. As a specific example, the command 9000h is a command indicating that the confirmed special symbol in the special game is a lost symbol. The command 9001h is a command indicating that the confirmed special symbol in the special symbol game is a special symbol indicating “7” as a jackpot symbol, and that the gaming state is a normal jackpot that does not become a high probability state. . Further, the command 9002h is a command indicating that the confirmed special symbol in the special symbol game is a special symbol indicating “7” as a jackpot symbol, and that the game state is a probabilistic big hit in which the gaming state becomes a high probability state. Based on such a display result notification command, on the side of the effect control board 12, the type of display result of the decorative symbol that is stopped and displayed after the variable display of the decorative symbol is performed is lost or normal or big hit, It becomes possible to decide what to do.

  The command A000h is a big hit start command indicating that the big hit gaming state is started when a big hit is made in the special symbol game by the special symbol display device 4 or the variable display of the decorative symbols on the image display device 5. The command A100h is a jackpot end command indicating that the jackpot gaming state is ended.

  The command D000h indicates that an abnormality has occurred in the random number generation operation in the random number circuit 112 due to an abnormality in the clock signal generated to generate a random number in the random number circuit 112 mounted on the main board 11. This is an error notification start # 1 command transmitted to start notification. The command D001h is generated by the random number circuit 112 when the decision to reach the variable display mode of the decorative symbols in the image display device 5 is continuously performed over a predetermined number (for example, 10 times) of variable display. This is an error notification start # 2 command transmitted to start notification that an abnormality has occurred in the random number generation operation. The command D002h is used when the determination of normal losing to be lost without changing the decorative display variable display mode in the image display device 5 is continuously performed over a predetermined number (for example, 50 times) of variable display. This is an error notification start # 3 command transmitted to start notification that an abnormality has occurred in the random number generation operation in the random number circuit 112.

  The control command transmitted from the main board 11 to the payout control board 15 is, for example, a payout control command transmitted as an electrical signal. The payout control command is set to transmit the payout control command by the CPU 103 (FIG. 9) provided in the game control microcomputer 100 mounted on the main board 11, and the game control microcomputer is based on the setting. It is transmitted to the payout control board 15 by the serial communication circuit 107 (FIG. 9) provided in the computer 100. In the following description, the transmission operation of the payout control command from the main board 11 to the payout control board 15 includes a series of operations by the CPU 103 and the serial communication circuit 107 provided in the game control microcomputer 100. To do. Also, for example, a payout notification command as an electrical signal is transmitted from the payout control board 15 to the main board 11. The payout notification command is set for sending a payout notification command by the CPU 213 (FIG. 27) provided in the payout control microcomputer 150 mounted on the payout control board 15, and for payout control based on the setting. It is transmitted to the main board 11 by the serial communication circuit 217 (FIG. 27) provided in the microcomputer 150. In the following description, the transmission operation of the payout notification command from the payout control board 15 to the main board 11 includes a series of operations by the CPU 213 and the serial communication circuit 217 provided in the payout control microcomputer 150. To do. In addition, in the following description, not only a command for a predetermined operation from one of the main board 11 and the payout control board 15 to the other, but also a notification signal for notifying the other of the operation state of the other is a payout control command or a payout It shall be included in the notification command.

  FIG. 6 is an explanatory diagram showing a configuration example of commands transmitted / received between the main board 11 and the payout control board 15. As shown in FIG. 6A, the payout control command transmitted from the main board 11 to the payout control board 15 and the payout notification command sent from the payout control board 15 to the main board 11 are both It is configured to be 2 bytes, and is configured to be the second byte by inverting the first byte. Then, the first bit (7th bit [bit 7]) of each byte is used as a header, and the header is made different so that the first byte and the second byte can be distinguished. For example, the header in the first byte is set to a fixed value of “0”, while the header in the second byte is set to a fixed value of “1”.

  The payout control command transmitted from the main board 11 to the payout control board 15 includes a payout number designation command and an ACK feedback command. The payout number designation command is a command indicating the number of prize balls to be paid out, and is composed of, for example, a bit value as shown in FIG. Here, the 3rd to 0th bits [bits 3-0] of the first byte and the second byte in the payout number designation command may be values set according to the number of prize balls to be paid out. FIG. 6C shows a payout number designation command used in this embodiment in hexadecimal notation. A command E11Eh shown in FIG. 6C is a first payout number designation command indicating that the number of prize balls to be paid out is fifteen. The command EC13h is a second payout number designation command indicating that the number of prize balls to be paid out is four. In this embodiment, when a game ball is detected by the start port switch 22, four prize balls are paid out, and when a game ball is detected by the count switch 24, 15 prize balls are paid out.

  A payout motor 51 that performs a rotation operation for paying out a game ball in accordance with the payout control of the payout control board 15 is provided inside a payout case constituted by, for example, three cases 91, 92, and 93 as shown in FIG. It is included in the provided dispensing device. The upper portions of the cases 91 and 92 are respectively provided with holes 85 and 86 communicating with the ball passages, and the game balls flow into the payout device through the holes 85 and 86. A gear 87 is fitted on the rotation shaft of the payout motor 51, and a gear 88 that meshes with the gear 87 and a ball placement portion that fits on the central axis of the gear 88 are provided inside the payout case. A cam 89 and a ball passage 90 below the cam 89 are provided. For example, the game balls that have flowed in through the holes 85 and 86 fall one by one alternately through the ball passage 90 every time the ball mounting portion of the cam 89 rotates 1/3. Furthermore, a payout motor position sensor 71 composed of, for example, a light emitting element (LED) and a light receiving element is provided inside the payout case. The payout motor position sensor 71 is a sensor for detecting the rotational position of the payout motor 51, and is used for detecting the ball engagement due to the inability to rotate the cam 89. At the lower part of the ball passage 90 provided inside the payout case, for example, a payout count switch 72 by a proximity switch is arranged. The payout count switch 72 is turned on every time one game ball falls from the ball passage 90 and transmits a predetermined detection signal to the payout control board 15.

  The command F00Fh shown in FIG. 6C is an ACK feedback command that becomes a reception confirmation acceptance signal indicating that the prize ball ACK command transmitted from the payout control board 15 to the main board 11 is received on the main board 11 side. It is.

  FIG. 6D is an explanatory diagram showing a configuration example of a payout notification command transmitted from the payout control board 15 to the main board 11. The payout notification command includes a prize ball ACK command, a payout error notification command, and a payout error cancel command. The command A0F5h shown in FIG. 6D is a prize ball ACK that is a reception confirmation signal indicating that the payout number specifying command transmitted from the main board 11 to the payout control board 15 is received on the payout control board 15 side. It is a command. The command B0F4h is a payout error notification command for notifying the main board 11 that an abnormality related to payout of the game ball has occurred on the payout control board 15 side. The command B1E4h is a payout error cancel command for notifying the main substrate 11 that the error that has occurred on the payout control board 15 side has been cancelled.

  As shown in FIG. 2, a game control microcomputer 100, a reference clock signal generation circuit 111, a random number circuit 112, a switch circuit 114, and a solenoid circuit 115 are mounted on the main board 11.

  The game control microcomputer 100 is, for example, a one-chip microcomputer, and executes various processes for controlling the progress of the game in the pachinko gaming machine 1. The reference clock signal generation circuit 111 generates a reference clock signal CLK used as an internal system clock having a predetermined frequency (for example, 20 MHz). The random number circuit 112 generates a jackpot determination random value R1 that is used to determine whether or not the pachinko gaming machine 1 is put into a jackpot gaming state by generating a jackpot. The switch circuit 114 takes in detection signals from various switches such as the gate switch 21, the start port switch 22, the V winning switch 23, and the count switch 24 and detection signals from various sensors, and transmits them to the game control microcomputer 100. . The solenoid circuit 115 outputs drive signals for the solenoids 81 and 82 in accordance with a command from the game control microcomputer 100.

  FIG. 8 is a block diagram illustrating a configuration example of the random number circuit 112. FIG. 8 also shows the start port switch 22, the game control microcomputer 100, the reference clock signal generation circuit 111, and the like. As shown in FIG. 8, the random number circuit 112 includes a clock signal output circuit 171, an initial value setting circuit 172, a random number generation circuit 173, a timer circuit 174, a latch signal generation circuit 175, and a random value register 176. I have.

  The clock signal output circuit 171 receives the reference clock signal CLK supplied from the reference clock signal generation circuit 111 and, for example, a clock signal having the same cycle as the reference clock signal CLK or a clock obtained by dividing the reference clock signal CLK by 16 The signal is output as a random number generating clock signal S1. The clock signal output circuit 171 outputs a clock signal S2 having the same cycle as that of the clock signal S1 but having a different phase. For example, the clock signal output circuit 171 may generate the clock signal S2 having different rising timing and falling timing in the same cycle as the clock signal S1 by inputting the clock signal S1 to the delay circuit or the inverting circuit.

  The clock signal output circuit 171 inputs a signal obtained by multiplying the reference clock signal CLK by 2 to the clock terminal of the D-type flip-flop circuit, for example, when generating the clock signal S1 having the same cycle as the reference clock signal CLK. By connecting the output signal from the negative phase output terminal (inverted output terminal) to the D input terminal, the clock signal S1 is output from the positive phase output terminal (non-inverted output terminal), while the negative phase output terminal (inverted output terminal) ) To output the clock signal S2. In this case, the clock signal S1 having the same frequency as the reference clock signal CLK is output from the positive phase output terminal (non-inverted output terminal) of the D-type flip-flop circuit, while the clock is output from the reverse phase output terminal (inverted output terminal). A clock signal S2 having the same frequency as that of the clock signal S1, but having a phase different from that of the clock signal S1 by π (= 180 °) is output.

  The clock signal S1 output from the clock signal output circuit 171 is input to the clock terminal of the random number generation circuit 173 and used as a count clock signal. The clock signal S1 is also input to the game control microcomputer 100. The clock signal S2 output from the clock signal output circuit 171 is input to the clock terminal of the latch signal generation circuit 175 and used as a latch clock signal.

  The initial value setting circuit 172 sets the initial value of the first round when the random number circuit 112 starts generating random numbers after the power supply to the pachinko gaming machine 1 is started, and the random number generation circuit 173 has a predetermined value. When the numerical data is updated cyclically from the initial value to a predetermined final value, a new initial value is set. The initial value setting circuit 172 outputs an initial value setting signal SK indicating the set initial value and inputs it to the random number generation circuit 173.

  The random number generation circuit 173 responds to, for example, the rising edge of the clock signal S1 supplied from the clock signal output circuit 171 and outputs the count value C to be output from a predetermined initial value to a predetermined final value. Update cyclically according to. As a specific example, the random number generation circuit 173 is configured using a 16-bit binary counter, and is an initial value set in a range from “1” to “65535” in response to a rising edge of the clock signal S1. The count value C is incremented by 1 from the value to “65535”. Then, after counting up to “65535”, the numerical data is updated cyclically by counting up from “1” to a numerical value that is one final value smaller than the initial value.

  The random number generation circuit 173 may change the permutation that is the update order of the count value C when, for example, the count value C is cyclically updated from a predetermined initial value to a predetermined final value. As a specific example, the random number generation circuit 173 is a counter that counts up one by one from a predetermined initial value to a predetermined final value within a range from “1” to “65535” in response to the rising edge of the clock signal S1. And a random number sequence changing circuit that can change the numerical data output from the counter to a permutation according to a predetermined update rule, and the random number sequence changing circuit replaces or transposes bits in the numerical data output from the counter. The permutation that is the update order of the count value C may be arbitrarily set by executing the bit scramble process.

  The timer circuit 174 measures the time during which the on-time start winning signal SS1 is input from the start port switch 22, and when the measured time reaches a predetermined time (for example, 3 milliseconds), the start winning signal SS1. Is input to the latch signal generation circuit 175. For example, the timer circuit 174 is configured using an up counter or a down counter, and starts in response to the start winning signal SS1 being turned on. In this case, the timer circuit 174 increases the predetermined timer value in response to the rising edge of the reference clock signal CLK input from the reference clock signal generation circuit 111 during the period in which the start winning signal SS1 is on. By counting or counting down, the time during which the start winning signal SS1 is on is measured. When the timer value counted up or down reaches a value corresponding to 3 milliseconds, the output signal to the latch signal generation circuit 175 is turned on to output the start winning signal SS1.

  The latch signal generation circuit 175 is configured using, for example, a D-type flip-flop circuit. As a specific example, the wiring from the output terminal of the timer circuit 174 is connected to the D input terminal of the D-type flip-flop circuit constituting the latch signal generation circuit 175, and the clock signal output from the clock signal output circuit 171 is connected to the clock terminal. A wiring for transmitting the signal S2 may be connected. The latch signal generation circuit 175 generates the latch signal SL by outputting the start winning signal SS1 output from the timer circuit 174 in synchronization with the rising edge of the clock signal S2 output from the clock signal output circuit 171. , Input to the random value register 176.

  The random value register 176 is configured using a 16-bit register, for example, and stores the count value C output from the random number generation circuit 173 as a jackpot determination random value R1. More specifically, the random number value register 176, in response to the rising edge of the latch signal SL input from the latch signal generation circuit 175, changes the count value C input from the random number generation circuit 173 to the jackpot determination disturbance. By latching and storing the value as the numerical value R1, every time the start winning signal SS1 from the start port switch 22 is input to the random number circuit 112, the stored random number R1 for jackpot determination is updated. The random value register 176 is in a non-readable (disabled) state when the output control signal SC from the game control microcomputer 100 is off, and is readable (enabled) when the output control signal SC is on. ) State. In addition, when the output control signal SC is in the ON state, the random value register 176 becomes incapable of receiving the latch signal SL, and the stored data remains even if the latch signal SL input from the latch signal generation circuit 175 rises. It may not be updated.

  FIG. 9 is a block diagram showing a configuration example of the game control microcomputer 100 mounted on the main board 11. The game control microcomputer 100 shown in FIG. 9 includes a clock circuit 101, a reset / interrupt controller 102, a CPU 103, a ROM 104, a RAM 105, a timer circuit (PIT) 106, a serial communication circuit (SCI) 107, And an input / output port 108.

  In the game control microcomputer 100, numerical data as various random numbers is used to control the progress of the game. As a specific example, the CPU 103 performs setting of a random number generation operation by the random number circuit 112, setting of a random counter provided in the game control microcomputer 100, and the like, and numerical data is periodically (or alternatively) according to a predetermined procedure. (Regular). FIG. 10 is an explanatory diagram illustrating a random number value counted on the main board 11 side. As shown in FIG. 10, in this embodiment, on the main board 11 side, random number value R1 for jackpot determination, random value R2 for probability variation determination, random value R3 for initial value determination, randomness for reach determination The numerical data indicating the numerical value R4 is controlled to be countable. In order to enhance the game effect, a random value other than the above, such as a random value for determining a variable display pattern, may be used. In this embodiment, the random number circuit 112 counts the random value R1 for jackpot determination, while the random counter value different from the random number circuit 112 is updated by software so that the random number value R2 for probability variation determination and the initial value A random number value R3 for value determination, a random value R4 for reach determination, and the like are counted.

  The random number R1 for jackpot determination is a random number value used for determining whether or not the pachinko gaming machine 1 is put into a jackpot gaming state by generating a jackpot, and ranges from “1” to “65535”. Takes a value. That is, the random number R1 for jackpot determination is used to determine whether the type of variable display result in the special symbol game by the special symbol display device 4 is a jackpot or a loss. The random number value R2 for determining the probability variation is a random value used for determining whether the probability variation jackpot or the normal jackpot is determined when the special game is determined to be a jackpot. The value is in the range of “1” to “100”. The random value R3 for determining an initial value is a random value used for determining a count initial value in the random value R2 for probability variation determination. For example, “1” to “ It takes a value in the range of “100”. The reach determination random number value R4 is a random number value used for determining whether or not the variable display mode of decorative symbols is to be reached, and takes a value in the range of “1” to “10”, for example.

  The clock circuit 101 is a circuit for supplying a clock signal to each circuit in the game control microcomputer 100. As a specific example, the clock circuit 101 divides an external clock input to its input terminal to generate a clock signal to be an internal system clock, and the generated clock signal is used for game control such as the CPU 103. This is supplied to each circuit in the microcomputer 100.

  The reset / interrupt controller 102 is for controlling various reset and interrupt requests generated in the game control microcomputer 100. The reset controlled by the reset / interrupt controller 102 includes a system reset and a user reset. The system reset is a reset that occurs when a low level signal is input to a predetermined SRST terminal for a certain period. For user reset, a low-level signal is input to a predetermined URST terminal for a certain period, a time-out signal of a watchdog timer (WDT) is generated, or an out-of-designated-area travel prohibition (IAT) signal is generated Or a reset caused by a predetermined factor such as the occurrence of an interval reset signal.

  The interrupts controlled by the reset / interrupt controller 102 include four types of interrupts such as an X class interrupt (XIRQ), an I class interrupt (IRQ), a software interrupt (SWI), and an illegal opcode trap (ILGOP). . The X class interrupt is an interrupt that occurs when a low level signal is input to a predetermined XIRQ terminal for a certain period. The I class interrupt is an interrupt that can allow / prohibit acceptance of an interrupt request by a user program. When a low level signal is input to a predetermined IRQ terminal for a certain period of time, an interrupt request signal from the timer circuit 106 is received. This is an interrupt generated by various predetermined interrupt factors such as the occurrence of an interrupt request signal from the serial communication circuit 107.

  The CPU 103 reads the user program and data stored in the ROM 104, and uses the RAM 105 as a work area to perform a control operation according to the program. FIG. 11 is a diagram showing an example of an address map in the game control microcomputer 100. As shown in FIG. 11, the area from address 0000h to address 01FFh is a work area assigned to the RAM 105. Further, the area of addresses 1000h to 101Ch is a built-in register area assigned to a built-in register included in the timer circuit 106, the serial communication circuit 107, and the like. The area from address 2000h to address 200Fh is a chip select signal decode area assigned to an address decoder built in the game control microcomputer 100. The area from address E000h to FFFFh is allocated to the ROM 104, and includes a user program management area and a user program / data area.

  User programs and user data created in advance by the user are stored in the user program / data area, which is an area from addresses E080h to FFFFh allocated to the ROM 104. In the user program management area, which is an area from addresses E000h to E07Fh allocated to the ROM 104, user program management data used when the CPU 103 executes the user program to set the operation content of the pachinko gaming machine 1 is stored. Remembered.

  FIG. 12 is a diagram showing an example of an address map in the user program management area shown in FIG. As shown in FIG. 12, in the area of addresses E00Ah to E011h included in the user program management area, a predetermined microcomputer such as an ID number which is unique identification information assigned to each game control microcomputer 100 is used. Eigenvalues are stored.

  In the area of E01Bh included in the user program management area, the highest priority among the plurality of types of I class interrupt (IRQ) factors generated by the game control microcomputer 100 is set. Data indicating the priority interrupt setting (KHPR) is stored. FIG. 13A is an explanatory diagram showing a setting example of the highest priority interrupt setting data stored in the area E01Bh. FIG. 13B shows, as an example of the specific setting of the highest priority interrupt setting data, the priority order of interrupt factors in default and the priority order of interrupt factors when “05h” is set in the area E01Bh. It shows.

  As shown in FIG. 13B, in the default state in which the highest priority interrupt setting data is not set in the area of E01Bh, the interrupt factor due to the signal input to the IRQ terminal of the reset / interrupt controller 102 has the highest priority. Subsequently, the priority of the interrupt request from each channel (CH0 to CH3) of the timer circuit 106 is high, and the priority is low in the order of the error interrupt request, the reception interrupt request, and the transmission interrupt request from the serial communication circuit 107. Is set to That is, even in the default state, among the interrupt requests from the serial communication circuit 107, the error interrupt request has a higher priority than other interrupt factors such as a reception interrupt request and a transmission interrupt request. Therefore, interrupt processing based on an error interrupt request from the serial communication circuit 107 is executed with priority over interrupt processing based on a reception interrupt request or transmission interrupt request that is different from the error interrupt request from the serial communication circuit 107. Will be.

  Further, when “05h” is set as the highest priority interrupt setting data in the area of E01Bh, the priority of the error interrupt request from the serial communication circuit 107 is determined by the interrupt factor due to the signal input to the IRQ terminal, the timer circuit The priority is higher than the priority of the interrupt request from 106, and the highest priority among the factors of a plurality of types of I class interrupts (IRQ) generated in the game control microcomputer 100. In this way, by setting the highest priority interrupt setting data in the area of address E01Bh, the priority order of the factors of a plurality of types of I class interrupts (IRQ) can be changed from the default setting.

  In the area of E01Ch address shown in FIG. 12, data indicating random number initial setting (KRSS) used for initial setting of the random number circuit 112 is stored. FIG. 14 is an explanatory diagram illustrating the contents of data indicating random number initial setting (KRSS) stored in the area of E01Ch address.

  As shown in FIG. 14, the random number initial setting data is configured as 8-bit data, but the seventh and sixth bits [bits 7-6] are unused. The fifth bit [bit 5] of the random number initial setting data indicates the setting for the update cycle of the random number value generated by the random number circuit 112. In the example shown in FIG. 14, when the fifth bit [bit 5] of the random number initial setting data is “0”, the random number value generated by the random number circuit 112 is updated at the cycle of the reference clock signal CLK serving as the internal system clock. When it is “1”, the random number value generated by the random number circuit 112 is updated at a cycle 16 times the reference clock signal CLK serving as the internal system clock.

  The fourth bit [bit 4] of the random number initial setting data shown in FIG. 14 indicates the setting for the initial value that is the start value of the first round in the random number value generated by the random number circuit 112. In the example shown in FIG. 14, when the fourth bit [bit 4] of the random number initial setting data is “0”, the start value of the first round in the random number value is “0000h” (hexadecimal number of 16-bit value) which is the default value. When the value is “1”, the value is based on an ID number that is unique identification information assigned to each game control microcomputer 100.

  The third and second bits [bits 3-2] of the random number initial setting data shown in FIG. 14 indicate the setting for the initial value that becomes the start value after the second round in the random number value generated by the random number circuit 112. ing. In the example shown in FIG. 14, when the third and second bits [bits 3-2] of the random number initial setting data are “00”, it indicates that the start value in the random number value is not changed and is “01”. Sometimes the start value is a value based on the ID number, which is unique identification information assigned to each game control microcomputer 100. When the value is "10", the added value of the stored data in the RAM 105 as the user RAM is shown. A start value is indicated. When “11” is indicated, a stored value of a designated address in the RAM 105 as a user RAM is indicated as a start value.

  The first and 0th bits [bits 1-0] of the random number initial setting data shown in FIG. 14 indicate settings for a method of changing the random number sequence (permutation) in the random number value generated by the random number circuit 112. In the example shown in FIG. 14, when the first and 0th bits [bits 1-0] of the random number initial setting data are “00”, the permutation is not changed. The change by the user program is possible, and when “11”, the change is automatically made after the second round.

  In the area of E022h address and the area of E023h shown in FIG. 12, data indicating the first serial communication initial setting (KSCM1) used for initial setting of the serial communication circuit 107, and the second serial communication Data indicating the initial setting (KSCM2) is stored. FIG. 15A is an explanatory diagram illustrating the contents of data indicating the first serial communication initial setting (KSCM1) stored in the area of address E022h. FIG. 15B is an explanatory diagram illustrating the contents of data indicating the second serial communication initial setting (KSCM2) stored in the area of the address E023h.

  As shown in FIGS. 15A and 15B, each of the first and second serial communication initial setting data is composed of 8-bit data. The sixth bit [bit 7-6] and the seventh to fourth bits [bit 7-4] of the second serial communication initial setting data are unused. The fifth bit [bit 5] of the first serial communication initial setting data shown in FIG. 15A indicates whether or not to use an interrupt when the transmission data is empty. Here, the interruption at the time of transmission data empty is an interruption that occurs when data is transferred from the transmission data register provided in the transmission operation unit 202 (FIG. 20) of the serial communication circuit 107 to the transmission shift register. It is included in the transmission interrupt generated in the serial communication circuit 107. In the example shown in FIG. 15A, when the fifth [bit 5] of the first serial communication initial setting data is “0”, it indicates that no interrupt is generated when the transmission data is empty, and when it is “1”. It indicates that an interrupt is generated when the transmission data is empty.

  The fourth bit [bit 4] of the first serial communication initial setting data indicates whether to use an interrupt when transmission is completed. Here, the transmission completion interrupt is an interrupt that occurs when the data transmission operation by the transmission operation unit 202 of the serial communication circuit 107 is completed, and is included in the transmission interrupt that occurs in the serial communication circuit 107. In the example shown in FIG. 15A, when the fourth bit [bit 4] of the first serial communication initial setting data is “0”, it indicates that an interrupt at the completion of transmission is not generated, and when it is “1”. Indicates that an interrupt is generated when transmission is completed.

  The third bit [bit 3] of the first serial communication initial setting data indicates a setting as to whether or not to use an interrupt when receiving data is transferred. Here, the interrupt at the time of receiving data transfer is an interrupt that occurs when the value of the receiving shift register provided in the receiving operation unit 201 (FIG. 20) of the serial communication circuit 107 is transferred to the receiving data register. It is included in the reception interrupt generated in the serial communication circuit 107. In the example shown in FIG. 15A, when the third bit [bit 3] of the first serial communication initial setting data is “0”, it indicates that no interrupt is generated during reception data transfer, and is “1”. It sometimes indicates that an interrupt is generated when receiving data is transferred.

  The second bit [bit 2] of the first serial communication initial setting data indicates whether to use an interrupt when an idle line is detected. Here, the interrupt at the time of detecting the idle line is an interrupt that occurs when an idle line consisting of “1” for one frame is detected as received data in the reception operation unit 201 of the serial communication circuit 107. It is included in the reception interrupt generated at 107. In the example shown in FIG. 15A, when the second bit [bit 2] of the first serial communication initial setting data is “0”, it indicates that no interrupt is generated when the idle line is detected, and is “1”. Sometimes it indicates that an interrupt is generated when an idle line is detected.

  The first bit [bit 1] of the first serial communication initial setting data indicates whether or not to use the transmission operation unit 202 of the serial communication circuit 107. In the example shown in FIG. 15A, when the first bit [bit 1] of the first serial communication initial setting data is “0”, it indicates that serial transmission by the transmission operation unit 202 is not used, and “1”. In some cases, serial transmission by the transmission operation unit 202 is used.

  The 0th bit [bit 0] of the first serial communication initial setting data indicates whether to use the reception operation unit 201 of the serial communication circuit 107 or not. In the example shown in FIG. 15A, when the 0th bit [bit 0] of the first serial communication initial setting data is “0”, it indicates that serial reception by the reception operation unit 201 is not used, and “1”. In some cases, serial reception by the reception operation unit 201 is used.

  The third bit [bit 3] of the second serial communication initial setting data shown in FIG. 15B indicates whether or not to use an interrupt at the time of an overrun error. Here, an interrupt at the time of an overrun error occurs when the reception shift register provided in the reception operation unit 201 receives the next data before the reception data in the serial communication circuit 107 is read by the user program. And is included in an error interrupt generated by the serial communication circuit 107. In the example shown in FIG. 15B, when the third bit [bit 3] of the second serial communication initial setting data is “0”, it indicates that an interrupt at the time of an overrun error is not generated and is “1”. It sometimes shows that an interrupt at the time of an overrun error is generated.

  The second bit [bit 2] of the second serial communication initial setting data indicates whether to use an interrupt at the time of a noise error. Here, the interrupt at the time of noise error is an interrupt based on an error that occurs when noise of data received by the serial communication circuit 107 is detected, and is included in the error interrupt that occurs in the serial communication circuit 107. In the example shown in FIG. 15B, when the second bit [bit 2] of the second serial communication initial setting data is “0”, it indicates that an interrupt at the time of noise error is not generated, and when it is “1”. It shows that an interrupt at the time of noise error is generated.

  The first bit [bit 1] of the second serial communication initial setting data indicates whether to use an interrupt at the time of a framing error. Here, the interrupt at the time of a framing error is an interrupt based on an error that occurs when “0” is detected in the stop bit of the data received by the serial communication circuit 107, and an error interrupt that occurs in the serial communication circuit 107 include. In the example shown in FIG. 15B, when the first bit [bit 1] of the second serial communication initial setting data is “0”, it indicates that an interrupt at the time of a framing error is not generated, and when it is “1”. It indicates that an interrupt is generated when a framing error occurs.

  The 0th bit [bit 0] of the second serial communication initial setting data indicates whether to use an interrupt at the time of a parity error. Here, an interrupt at the time of a parity error is an interrupt based on an error that occurs when the parity of the data received by the serial communication circuit 107 and the parity bit in the received data do not match, and is generated by the serial communication circuit 107. Included in error interrupt. In the example shown in FIG. 15B, when the 0th bit [bit 0] of the second serial communication initial setting data is “0”, it indicates that an interrupt at the time of parity error is not generated, and when it is “1”. This indicates that an interrupt is generated when a parity error occurs.

  As described above, error interrupts generated in the serial communication circuit 107 include four types of interrupts: an interrupt at a parity error, an interrupt at an overrun error, an interrupt at a framing error, and an interrupt at a noise error. It is included.

  In addition to the game control user program, the ROM 104 provided in the game control microcomputer 100 shown in FIG. 9 stores various data tables used for controlling the progress of the game. For example, the ROM 104 stores table data constituting a plurality of determination tables and determination tables prepared for the CPU 103 to perform various determinations and determinations. The determination table includes a jackpot determination table that is referred to in order to determine whether or not the confirmed symbol is a jackpot symbol in the special symbol game by the special symbol display device 4, and a variable display of the decorative symbol in the image display device 5. A reach determination table and the like that are referred to for determining whether or not the mode is reach are included. As an example of the big hit determination table stored in the ROM 104, in this embodiment, a normal big hit determination table 140 shown in FIG. 16A and a probability change big hit determination table 141 shown in FIG. It is prepared.

  In the normal big hit determination table 140 and the probability change big hit determination table 141, whether the big hit determination random number value R1 matches the big hit determination value data indicating that the display result of the special figure game is a big hit, respectively. This is composed of setting data or the like that makes it possible to determine whether or not the display result matches the loss determination value data indicating that it is lost. In the probability change big hit determination table 141, more random number values R1 than the normal big hit determination table 140 are set to match the big hit determination value data. That is, in the normal game state in which the display result of the special figure game is determined using the normal jackpot determination table 140 by determining the display result of the special figure game using the probability change big hit determination table 141 in the probability improvement state. It is determined with a higher probability that the game state will be a big hit gaming state.

  In this embodiment, in the normal jackpot determination table 140 shown in FIG. 16A, the range of values taken by the random number R1 for jackpot determination generated by the random number circuit 112 is “1” to “65335”. Of these, “2001” to “2184” are set so as to be determined to match with the big hit determination value data indicating “big hit”. On the other hand, in the probability change big hit determination table 141 shown in FIG. 16 (B), the range of values “1” to “65335” that are the values taken by the random number R1 for jackpot determination generated by the random number circuit 112 is set. Of these, “2001” to “3104” are set so as to be determined to match with the big hit determination value data indicating “big hit”.

  As an example of the reach determination table stored in the ROM 104, in this embodiment, a reach determination table 142 shown in FIG. 17 is prepared in advance. The reach determination table 142 indicates that the random number R4 for reach determination matches the reach determination value data indicating that the variable display mode of the decorative design is set to reach, or the variable display mode of the decorative design is not set to reach. It consists of setting data that makes it possible to determine whether or not it matches the normal loss determination value data.

  As a determination table other than the big hit determination table or the reach determination table, a probability change determination table referred to determine whether to be a probability big hit or a normal big hit when the variable display result in the special figure game is “big hit”. and so on. Further, the determination table stored in the ROM 104 includes a confirmed special symbol determination table for determining a confirmed special symbol to be derived and displayed as a variable display result in the special symbol game, a special symbol game or an image by the special symbol display device 4. A variable display pattern determination table for determining a variable display pattern such as a symbol during variable display of decorative symbols on the display device 5, an effect display execution determination table for determining whether or not to perform various effect displays, etc. It is included. As the variable display pattern determination table, a big hit variable display pattern determination table, a reach variable display pattern determination table, a normal loss variable display pattern determination table, and the like may be prepared in advance. Each variable display pattern determination table is used for special display games started by the special symbol display device 4 or variable display of decorative symbols started by the image display device 5 based on random number values for variable display pattern determination. What is necessary is just to be comprised from the data for determination for determining the variable display pattern to perform.

  In the RAM 105 provided in the game control microcomputer 100, a game control data holding area 130 as shown in FIG. 18, for example, is stored as an area for holding various data used for controlling the game state and the like in the pachinko gaming machine 1. Is provided. In addition, at least a part of the RAM 105 is a backup RAM that is backed up by a backup power source created in the power supply substrate 10. That is, even if the power supply to the pachinko gaming machine 1 is stopped, at least a part of the contents of the RAM 105 is stored for a predetermined period. In this embodiment, it is assumed that the entire RAM 105 is a backup RAM that is backed up. The game control data holding area 130 shown in FIG. 18 includes a special figure holding storage unit 131, a confirmed special symbol storage unit 132, a game control flag setting unit 133, a game control timer setting unit 134, and a game control counter setting unit. 135 and a game control buffer setting unit 136.

  The special figure storage unit 131 has a start condition for executing the special figure game by the special symbol display device 4 when the game ball wins the start winning opening provided in the ordinary variable winning ball device 6 and the special symbol display device 4 is executed. The hold information relating to the special figure game in which the start condition for starting the variable display is not satisfied due to the reason that the special figure game is being executed is stored. For example, the special figure hold storage unit 131 associates the hold numbers in the order of winning to the start winning opening, and indicates the random number R1 for jackpot determination read from the random number circuit 112 based on the establishment of the starting condition by the winning. Numerical data is stored as pending data until the number reaches a predetermined upper limit (eg, “4”).

  The confirmed special symbol storage unit 132 stores data indicating a confirmed special symbol derived and displayed as a variable display result in the special symbol game by the special symbol display device 4. The game control flag setting unit 133 sets a plurality of types of flags that are set or cleared in accordance with the gaming state in the pachinko gaming machine 1 and signals transmitted from the winning prize switch etc. via the switch circuit 114. For storing data. The game control timer setting unit 134 stores data indicating a plurality of types of timer values used for game control in the pachinko gaming machine 1. The game control counter setting unit 135 stores data indicating a plurality of types of count values used for game control in the pachinko gaming machine 1. The game control buffer setting unit 136 temporarily stores various data used for game control in the pachinko gaming machine 1. The circuit used for flag setting and counter / timer may be configured by a register circuit provided separately from the RAM 105.

  The game control flag setting unit 133 includes, for example, a clear flag, a main backup flag, a serial communication error flag, a transmission setting enable flag, a transmission completion flag, a start winning flag, a special symbol process flag, a big hit flag, a probability changing flag, and a probability change confirmed. A flag or the like is provided.

  The clear flag indicates whether or not a clear signal from the clear switch 304 included in the power supply board 10 is in an ON state when power supply to the pachinko gaming machine 1 is started. That is, if the clear signal is in the on state at the start of power supply, the clear flag is set in the on state, while if the clear signal is in the off state, the clear flag is held in the off state. The main backup flag indicates whether or not a predetermined memory protection process has been executed by the gaming control microcomputer 100 when power supply to the pachinko gaming machine 1 is stopped. For example, when “55H” is set as the value of the main backup flag, backup is present (ON state), while when a value other than “55H” is set, backup is not present (OFF state).

  The serial communication error flag indicates that an error has occurred in the communication operation in the serial communication circuit 107. For example, the serial communication error flag is set to an on state in response to an error interrupt request from the serial communication circuit 107. The transmission setting enable flag indicates that the serial communication circuit 107 can be set for data transmission. For example, the transmission setting enable flag is set to an on state in response to an interrupt request from the serial communication circuit 107 when the transmission data is empty. The transmission completion flag indicates that data transmission has been completed in the serial communication circuit 107. For example, the transmission completion flag is set to an on state in response to an interrupt request at the completion of transmission from the serial communication circuit 107. The start winning flag is set to the on state when the start winning signal SS1 input from the start port switch 22 is continuously on for a predetermined period (for example, 4 milliseconds), while the start winning signal SS1 is turned off. When it is in a state, it is cleared and turned off.

  The special symbol process flag indicates which process should be selected / executed in the special symbol process (step S78 in FIG. 35 and FIG. 39) executed corresponding to the special symbol display device 4. The big hit flag is set to the on state when it is determined that the variable display result in the special figure game is a big hit when the special symbol display device 4 starts the special figure game. After that, when the big hit gaming state based on the big win in the special figure game is finished, the big hit flag is cleared and turned off. The probable change flag is set to the on state when the variable display result in the special symbol game by the special symbol display device 4 becomes the probable big hit and the big hit gaming state based on the big hit is ended. On the other hand, the flag during probability change is cleared, for example, when the number of executions of the special figure game in the high probability state reaches a predetermined probability change end reference value or when the variable display result in the special figure game is a normal big hit. Turns off. The probability variation confirmation flag is set to the on state when it is determined that the variable display result is a probability variation jackpot when the special symbol game by the special symbol display device 4 is started. On the other hand, when the big hit gaming state ends, the probability variation confirmation flag is cleared and turned off.

  The game control timer setting unit 134 is provided with, for example, first and second monitoring timers, start port switch timers, variable display time timers, and the like. The first monitoring timer is added when the clock signal S1 supplied from the clock signal output circuit 171 included in the random number circuit 112 is at a high level, and is cleared when the clock signal S1 is at a low level. It is. The second monitoring timer is added when the clock signal S1 supplied from the clock signal output circuit 171 included in the random number circuit 112 is at a low level, and is cleared when the clock signal S1 is at a high level. It is.

  The start port switch timer is a timer used to measure a period during which the start winning signal SS1 input from the start port switch 22 is in an on state. For example, when the start winning signal SS1 is in an on state, a timer value is set. Regularly count up or down by one. On the other hand, when the start winning signal SS1 is OFF, the start port switch timer is cleared and set to a predetermined timer initial value. The variable display time timer is for measuring the variable display time (total variation time) of special symbols in the special game.

  The game control counter setting unit 135 includes, for example, a wait counter, a payout notification command reception counter, a payout control command transmission counter, a reach count counter, a normal lose count counter, a probability variation determination random number counter, an initial value determination random number counter, and the like. It has been. In addition, the game control counter setting unit 135 may be provided with a variable display number counter for counting the number of executions of the special figure game in the high probability state or the time reduction state.

  When the power supply to the pachinko gaming machine 1 is started and the game control process (process for controlling the progress of the game) can be executed by the game control microcomputer 100, the weight counter It is used to delay the timing for starting execution of the control process. For example, when the power supply to the pachinko gaming machine 1 is started and the game control microcomputer 100 is activated, an initialization wait number designation value corresponding to a predetermined delay time is set in the wait counter. Thereafter, an update process such as sequentially subtracting the weight count value which is the value of the wait counter is performed, and when the value reaches a predetermined delay end determination value, the execution of the game control process is started.

  The payout notification command reception counter is used to count the number of commands received from the payout control board 15 in an identifiable manner. The payout control command transmission counter is used to count the number of commands waiting to be sent to the payout control board 15 so as to be specified.

  The reach number counter is for counting the number of times that the determination that the decorative display variable display mode in the image display device 5 is to be reached is continuously performed. The normal loss count counter is for counting the number of times that the determination that the variable display result of the loss is derived and displayed without setting the variable display mode of the decorative pattern in the image display device 5 as reach is performed. It is.

  The random number counter for probability variation determination is a counter used for counting the random number value R2 for probability variation determination. The initial value determining random number counter is a counter used for counting the initial value determining random value R3. Here, for example, game control timer interrupt processing (FIG. 35) is executed in order to prevent synchronization between the update cycle in the random number value R2 for probability variation determination and the update cycle in the random value R3 for initial value determination. Each time, the random value R2 for probability variation determination is up-counted by 1, whereas the random value R3 for initial value determination may be up-counted by 3.

  The game control buffer setting unit 136 includes, for example, a main checksum buffer, a random number initial value buffer, a command reception buffer, a command transmission buffer, and the like. The main checksum buffer is for storing a checksum calculated using stored data in a specific area of the RAM 105 when power supply to the pachinko gaming machine 1 is stopped. The random number initial value buffer is for storing the initial value determining random value R3 read from the initial value determining random number counter by the CPU 103 as an initial value in the random number value R2 for probability variation determination.

  The command reception buffer is used for temporarily storing a command received from the sub-side control board by the main board 11. FIG. 19 is a diagram illustrating a configuration example of the payout reception command buffer 191 included in the command reception buffer. The payout reception command buffer 191 is for temporarily storing a command received from the payout control board 15. The payout receive command buffer 191 shown in FIG. 19 includes 12 receive command buffers # 1 to # 12. The receive command buffer for storing commands received from the payout control board 15 is a payout notification command reception counter. It is specified. Each reception command buffer # 1 to # 12 is composed of, for example, 1 byte (8 bits), and a plurality of reception command buffers can be used as ring buffers to store six reception commands of 2 bytes. .

  The command transmission buffer is used to temporarily store a command to be transmitted from the main board 11 to the sub control board. FIG. 20 is a diagram illustrating a configuration example of the payout transmission command buffer 192 included in the command transmission buffer. The payout transmission command buffer 192 is for temporarily storing a command to be transmitted from the main board 11 to the payout control board 15. The payout transmission command buffer 192 shown in FIG. 20 includes twelve transmission command buffers # 1 to # 12, and a command buffer for storing a command waiting for transmission from the main board 11 to the payout control board 15 is provided. , Specified by the payout control command transmission counter. Each of the transmission command buffers # 1 to # 12 is composed of, for example, 1 byte (8 bits), and can store six transmission commands of 2 bytes by using a plurality of transmission command buffers as ring buffers. . The command transmission buffer may include an effect transmission command buffer for temporarily storing a command to be transmitted from the main board 11 to the effect control board 12.

  In addition, in the game control data holding area 130, although a game ball that has passed through the passing gate is detected by the gate switch 21, a start condition for executing the normal diagram game by the normal symbol display 40 is established. Even if it has a normal map hold storage unit for storing hold information related to a normal diagram game in which a start condition for starting variable display is not satisfied due to reasons such as running a normal map game Good. As described above, the hold information relating to the special figure game or the normal figure game is stored in the game control data holding area 130 provided on the main board 11 and used for the control of the special figure game or the normal figure game by the CPU 103.

  The timer circuit 106 provided in the game control microcomputer 100 shown in FIG. 9 is configured by, for example, four channels (CH0 to CH3) of built-in 8-bit programmable counters, and is capable of generating real-time interrupts and measuring time. is there. For example, the timer circuit 106 starts countdown at a predetermined cycle from a preset count value for each channel, and when there is a channel whose count value is “00”, the interrupt flag corresponding to that channel is turned on. set. At this time, if the interrupt is permitted, the timer circuit 106 generates an interrupt request to the reset / interrupt controller 102.

  The serial communication circuit 107 included in the game control microcomputer 100 is a circuit that handles communication data in, for example, full duplex, asynchronous, standard NRZ (Non Return to Zero) format, and has a configuration illustrated in FIG. ing. A serial communication circuit 107 illustrated in FIG. 21 includes a reception operation unit 201, a transmission operation unit 202, a serial communication data register 203, a serial status register 204, and a serial control register 205.

  The reception operation unit 201 can sample and acquire the reception data transmitted by serial communication and transfer the acquired reception data to the serial communication data register 203 by the reception operation based on the setting in the predetermined bit of the serial control register 205. And Further, the reception operation unit 201 sets a predetermined bit of the serial status register 204 to “0” or “1” according to an operation state in the reception operation. The reception operation unit 201 is, for example, a reception shift register that stores received data sequentially transmitted by serial communication while shifting, a reception data register that temporarily stores reception data read from the reception shift register, and serial communication Is provided with an interrupt control circuit for controlling the generation of interrupt factors related to the reception operation.

  The transmission operation unit 202 generates transmission data corresponding to the read data from the serial communication data register 203 by a transmission operation based on a setting in a predetermined bit of the serial control register 205, and enables transmission by serial communication. Further, the transmission operation unit 202 sets a predetermined bit of the serial status register 204 to “0” or “1” according to an operation state in the transmission operation. The transmission operation unit 202 includes, for example, a transmission data register that temporarily stores data read from the serial communication data register 203, a transmission shift register that stores and shifts transmission data sequentially transmitted by serial communication, It includes an interrupt control circuit that controls the generation of interrupt factors related to transmission operations in serial communication.

  The serial communication data register 203 stores the reception data acquired by the reception operation unit 201 or stores data to be supplied to the transmission operation unit 202, thereby communicating between the serial communication circuit 107 and the CPU 103. This is a circuit that enables data exchange, and is composed of, for example, 1 byte (8 bits).

  The serial status register 204 is a register for confirming the operation state in the serial communication circuit 107. For example, as shown in FIG. 22A, the serial status register 204 includes a first register SIST1 and a second register SIST2. Yes. The seventh bit [bit 7] of the first register SIST1 shown in FIG. 22A is a bit (TDRE) indicating a transmission data empty flag. For example, when data is transferred from the transmission data register included in the transmission operation unit 202 to the transmission shift register, the seventh bit [bit 7] of the first register SIST1 is set to “1” and turned on. .

  The sixth bit [bit 6] of the first register SIST1 shown in FIG. 22A is a bit (TC) indicating a transmission completion flag. For example, when transmission of data stored in the transmission shift register included in the transmission operation unit 202 is completed, the sixth bit [bit 6] of the first register SIST1 is set to “1” to be turned on. The fifth bit [bit 5] of the first register SIST1 is a bit (RDRF) indicating a reception data full flag. For example, when the data stored in the reception shift register included in the reception operation unit 201 is transferred to the reception data register, the fifth bit [bit 5] of the first register SIST1 is set to “1” and turned on. It becomes.

  The fourth bit [bit 4] of the first register SIST1 shown in FIG. 22A is a bit (IDLE) indicating an idle line detection flag. For example, when a predetermined idle line is detected in the reception data in the reception operation unit 201, the fourth bit [bit 4] of the first register SIST1 is set to “1” to be turned on. The third bit [bit 3] of the first register SIST1 is a bit (OR) indicating an overrun error flag. For example, when an overrun error is detected during the reception operation in the reception operation unit 201, the third bit [bit 3] of the first register SIST1 is set to “1” to be turned on.

  The second bit [bit 2] of the first register SIST1 shown in FIG. 22A is a bit (NF) indicating a noise error flag. For example, when a noise error is detected during the reception operation in the reception operation unit 201, the second bit [bit 2] of the first register SIST1 is set to “1” and is turned on. The first bit [bit 1] of the first register SIST1 is a bit (FE) indicating a framing error flag. For example, when a framing error is detected during the reception operation in the reception operation unit 201, the first bit [bit 1] of the first register SIST1 is set to “1” to be turned on.

  The 0th bit [bit 0] of the first register SIST1 shown in FIG. 22A is a bit (PF) indicating a parity error flag. For example, when the parity of the received data in the reception operation unit 201 does not match the parity bit in the received data, the 0th bit [bit 0] of the first register SIST1 is set to “1” and the ON state is set. Become. The 0th bit [bit 0] of the second register SIST2 is a bit (RAF) indicating a reception active flag. For example, when the receiving operation unit 201 detects “0” as the start bit, the 0th bit [bit 0] of the second register SIST2 is set to “1”, and is turned on.

  The serial control register 205 is a register for setting the communication format in the serial communication circuit 107 and permission / prohibition of various error interrupt requests. For example, as shown in FIG. 22B, the first to third registers SICL1 To SICL3. A fourth bit [bit 4] of the first register SICL1 shown in FIG. 22B is a bit (M) for selecting a data length in serial communication. For example, when the fourth bit [bit 4] of the first register SICL1 is “0”, the start bit is 1 bit, the data bit is 8 bits, the stop bit is set to 1 bit, and when it is “1”, the start bit is Is 1 bit, the data bit is 9 bits, and the stop bit is 1 bit. The third bit [bit 3] of the first register SICL1 is a bit (WAKE) for selecting a wake-up method. For example, when the third bit [bit 3] of the first register SICL1 is “0”, the reception operation unit 201 is set to wake up by recognition of the idle line, and when it is “1”, the reception operation by recognition of the address mark is set. The wakeup of the unit 201 is set.

  The second bit [bit 2] of the first register SICL1 shown in FIG. 22B is a bit (ILT) for selecting an idle line detection method. For example, when the second bit [bit 2] of the first register SICL1 is “0”, the detection method is set after the start bit, and when it is “1”, the detection method is set after the stop bit. The The first bit [bit 1] of the first register SICL1 is a bit (PE) for setting whether or not to use the parity function. For example, when the first bit [bit 1] of the first register SICL1 is “0”, it is set not to use the parity function, and when it is “1”, the parity function is set to be used.

  The 0th bit [bit 0] of the first register SICL1 shown in FIG. 22B is a bit (PT) for selecting the type of parity when the parity function is used. For example, when the 0th bit [bit 0] of the first register SICL1 is “0”, it is set to use even parity, and when it is “1”, it is set to use odd parity.

  The seventh bit [bit 7] of the second register SICL2 shown in FIG. 22B is a bit (TIE) for setting permission / prohibition of the transmission interrupt request. For example, when the seventh bit [bit 7] of the second register SICL2 is “0”, the transmission interrupt request is prohibited, and when it is “1”, the transmission interrupt request is permitted. The sixth bit [bit 6] of the second register SICL2 is a bit (TCIE) for setting permission / prohibition of the transmission completion interrupt request. For example, when the sixth bit [bit 6] of the second register SICL2 is “0”, the transmission completion interrupt request is prohibited, and when it is “1”, the transmission completion interrupt request is permitted.

  The fifth bit [bit 5] of the second register SICL2 shown in FIG. 22B is a bit (RIE) for setting permission / prohibition of the reception interrupt request. For example, when the fifth bit [bit 5] of the second register SICL2 is “0”, the reception interrupt request is prohibited, and when it is “1”, the reception interrupt request is permitted. The fourth bit [bit 4] of the second register SICL2 is a bit (ILIE) for setting permission / prohibition of the idle line interrupt request. For example, when the fourth bit [bit 4] of the second register SICL2 is “0”, the idle line interrupt request is prohibited, and when it is “1”, the idle line interrupt request is permitted.

  The third bit [bit 3] of the second register SICL2 shown in FIG. 22B is a bit (TE) for setting whether to use the transmission operation unit 202 or not. For example, when the third bit [bit 3] of the second register SICL2 is “0”, it is set not to use the transmission operation unit 202, and when it is “1”, it is set to use the transmission operation unit 202. The The second bit [bit 2] of the second register SICL2 is a bit (RE) for setting whether to use the reception operation unit 201 or not. For example, when the second bit [bit 2] of the second register SICL2 is “0”, the reception operation unit 201 is set not to be used, and when it is “1”, the reception operation unit 201 is set to be used. The

  The first bit [bit 1] of the second register SICL2 shown in FIG. 22B is a bit (RWU) for setting whether to use reception wakeup. For example, when the first bit [bit 1] of the second register SICL2 is “0”, it is set not to use the reception wakeup, and when it is “1”, the reception wakeup is set to be used. The 0th bit [bit 0] of the second register SICL2 is a bit (SBK) for setting whether or not to use break code transmission. For example, when the 0th bit [bit 0] of the second register SICL2 is “0”, it is set not to use break code transmission, and when it is “1”, it is set to use break code transmission.

  The seventh bit [bit 7] of the third register SICL3 shown in FIG. 22B is a bit (R8) for storing the ninth bit in the received data when the data bit is set to nine bits. The sixth bit [bit 6] of the third register SICL3 is a bit (T8) for storing the ninth bit in the transmission data when the data bit is set to 9 bits.

  The third bit [bit 3] of the third register SICL3 shown in FIG. 22B is a bit (ORIE) for setting permission / prohibition of an interrupt request at the time of an overrun error. For example, when the third bit [bit 3] of the third register SICL3 is “0”, an interrupt request at the time of an overrun error is prohibited, and when it is “1”, an interrupt request at the time of an overrun error is permitted. The second bit [bit 2] of the third register SICL3 is a bit (NEIE) for setting permission / prohibition of an interrupt request at the time of a noise error. For example, when the second bit [bit 2] of the third register SICL3 is “0”, an interrupt request at the time of noise error is prohibited, and when it is “1”, an interrupt request at the time of noise error is permitted.

  The first bit [bit 1] of the third register SICL3 shown in FIG. 22B is a bit (FEIE) for setting permission / prohibition of an interrupt request at the time of a framing error. For example, when the first bit [bit 1] of the third register SICL3 is “0”, an interrupt request at the time of a framing error is prohibited, and when it is “1”, an interrupt request at the time of a framing error is permitted. The 0th bit [bit 0] of the third register SICL3 is a bit (PEIE) for setting permission / prohibition of an interrupt request at the time of a parity error. For example, when the 0th bit [bit 0] of the third register SICL3 is “0”, an interrupt request at the time of a parity error is prohibited, and when it is “1”, an interrupt request at the time of a parity error is permitted.

  An input / output port 108 provided in the game control microcomputer 100 shown in FIG. 9 includes an input port for taking in various signals transmitted to the game control microcomputer 100, and various signals to the outside of the game control microcomputer 100. And an output port for transmitting.

  FIG. 23 is an explanatory diagram showing an example of bit allocation in the input port included in the input / output port 108. As shown in FIG. 23, the bits 0 to 7 of the input port # 0 have a power-off signal from the payout control board 15, a clock signal S1 from the random number circuit 112, a clear signal from the power board 10 and a reset signal, respectively. The detection signal from the V winning switch 23, the detection signal from the count switch 24, the detection signal from the gate switch 21, and the detection signal from the start port switch 22 (start winning signal SS1) are input. Random value output signals SO0 to SO15 from the random number circuit 112 are input to the input ports # 1 and # 2. The random value output signals SO0 to SO15 indicate the bit values in the 16-bit data that is the jackpot determination random value R1 read from the random number circuit 112.

  FIG. 24 is an explanatory diagram showing an example of bit allocation in the output port included in the input / output port 108. As shown in FIG. 24, from the output port # 0, the drive signal for the solenoid 82 for opening and closing the big prize opening in the special variable winning ball apparatus 7 and the movable wing piece in the normal variable winning ball apparatus 6 are tilted. A drive signal for the solenoid 81 is output. Also, a clear signal for the payout control board 15, an effect control INT signal for the effect control board 12, and an output control signal SC for the random number circuit 112 are output from the output port # 0. The effect control INT signal is a capture signal for instructing the effect control board 12 to capture (receive) 8-bit data constituting the effect control command. The output port # 1 is an output port of 8-bit data (effect control output data D0 to D7) indicating an effect control command transmitted to the effect control board 12.

  As shown in FIG. 2, an effect control microcomputer 120 is mounted on the effect control board 12. The effect control board 12 includes a command receiving circuit used for receiving the effect control command, a VDP (Video Display Processor) that generates image data in accordance with a drawing command from the effect control microcomputer 120, and the like. It may be. The effect control microcomputer 120 is a one-chip microcomputer, for example, and includes a ROM 121, a RAM 122, a CPU 123, and an I / O port 124. In addition, the production control microcomputer 120 may include a random number circuit that generates numerical data indicating random values independently of the CPU 123. A control signal transmitted from the main board 11 via the relay board 18 is input to the CPU 123 via a predetermined connector or an input port in the I / O port 124. A control signal for the audio control board 13 is output from the CPU 123 to the audio control board 13 via an output port in the I / O port 124 or a predetermined connector. A control signal for the lamp control board 14 is output from the CPU 123 to the lamp control board 14 via an output port in the I / O port 124 or a predetermined connector.

  A scaler circuit for converting the resolution in the image data may be provided between the effect control board 12 and the image display device 5. In this case, the image data generated by the VDP mounted on the effect control board 12 according to the drawing command from the effect control microcomputer 120 is supplied to the image display device 5 after the resolution is converted by the scaler circuit. . As a specific example, the scaler circuit inputs the image data with the first resolution generated by the VDP and performs the following processing on one or both of the vertical direction and the horizontal direction. The converted image data is converted to a second resolution different from the first resolution.

  For example, when converting the resolution in the vertical direction, after performing upsampling at a first sample rate along the vertical direction of the input image data, a filtering process using a filter (for example, an FIR filter) prepared in advance. Apply. Thereafter, downsampling may be performed at a second sample rate corresponding to a predetermined scaling coefficient along the vertical direction. When converting the resolution in the horizontal direction, upsampling, filtering, and downsampling similar to those in the vertical direction may be performed along the horizontal direction of the input image data. As a specific example, when image data in VGA mode (640 × 480 pixels) is generated by VDP, the image data is converted into SXGA mode (1280 × 1024 pixels) or other modes by conversion processing in the scaler circuit. Can be converted to

  The ROM 121 included in the effect control microcomputer 120 stores various data tables used for controlling the progress of the effect. For example, the ROM 121 causes the CPU 123 to make various determinations and determinations related to effects based on the EXT data in the variable display start command from the main board 11 and the confirmed special symbol in the special figure game notified by the display result notification command. A plurality of types of determination tables and determination tables prepared in the above are stored.

  In the RAM 122 included in the effect control microcomputer 120, as an area for holding various data used for controlling the effect operation by the display on the image display device 5 and the sound output from the speakers 8L and 8R, for example, FIG. An effect control data holding area 220 as shown in FIG. The effect control data holding area 220 shown in FIG. 25 includes a confirmed decorative symbol storage unit 221, an effect control flag setting unit 222, an effect control timer setting unit 223, an effect control counter setting unit 224, and an effect control buffer setting unit. 225.

  The confirmed decorative symbol storage unit 221 stores data indicating a fixed decorative symbol that is derived and displayed as a variable display result in the variable display of decorative symbols in the image display device 5. The effect control flag setting unit 222 sets a plurality of types of flags that are set or cleared according to the effect operation state such as the display state of the image display device 5, the effect control command transmitted from the main board 11, and the like. For storing data. The effect control timer setting unit 223 stores data indicating a plurality of types of timer values used for effect control such as display control on the image display device 5, for example. The effect control counter setting unit 224 stores data indicating a plurality of types of count values used for effect control such as display control on the image display device 5, for example. The circuit used for flag setting and counter / timer may be configured by a register circuit provided separately from the RAM 122.

  The effect control flag setting unit 222 is provided with, for example, a timer interrupt flag, an error notification start flag, an effect control process flag, and the like. The timer interrupt flag is set to an on state every time a predetermined time elapses and a timer interrupt is generated in the effect control microcomputer 120. The error notification start flag corresponds to the reception of any of the error notification start commands # 1 to # 3 transmitted from the main board 11, and any of a plurality of types of effects prepared in advance should be selected and executed. Indicate The effect control process flag indicates which process should be selected and executed in the effect control process (step S505 in FIG. 44 and FIG. 47) executed to control the progress of the effect.

  The effect control timer setting unit 223 is provided with a display control timer, for example. The display control timer is for measuring a time related to display control of the image display device 5, such as a variable display time of decorative symbols in the image display device 5.

  The effect control counter setting unit 224 is provided with an effect control command reception counter, for example. The effect control command reception counter is for counting the number of reception of the effect control command transmitted from the main board 11 in an identifiable manner.

  The effect control buffer setting unit 225 is provided with, for example, an effect side reception command buffer 231 as shown in FIG. The effect side reception command buffer 231 is for temporarily storing a command from the main board 11 received by the effect control board 12. The effect side reception command buffer 231 shown in FIG. 26 includes twelve reception command buffers # 1 to # 12, and the reception command buffer for storing the received command is designated by the effect control command reception counter. Each reception command buffer # 1 to # 12 is composed of, for example, 1 byte (8 bits), and a plurality of reception command buffers can be used as ring buffers to store six reception commands of 2 bytes. .

  As shown in FIG. 2, a payout control microcomputer 150 and a switch circuit 161 are mounted on the payout control board 15. The switch circuit 161 is input with detection signals from various switches and sensors such as the full tank switch 26, the ball-out switch 27, the payout motor position sensor 71, the payout count switch 72, and the error release switch 73. The switch circuit 161 takes in these detection signals and transmits them to the payout control microcomputer 150.

  FIG. 27 is a diagram illustrating a configuration example of the payout control microcomputer 150 mounted on the payout control board 15. 27 is, for example, a one-chip microcomputer similar to the game control microcomputer 100, and includes a clock circuit 211, a reset / interrupt controller 212, a CPU 213, a ROM 214, a RAM 215, A timer circuit (PIT) 216, a serial communication circuit (SCI) 217, and an input / output port 218 are provided. Each circuit such as the clock circuit 211 included in the payout control microcomputer 150 may have the same configuration as each circuit included in the game control microcomputer 100.

  The ROM 214 included in the payout control microcomputer 150 stores a payout control program. In the payout control microcomputer 150, for example, the CPU 213 reads a payout control program stored in the ROM 214, and performs various processes based on the payout control command transmitted from the main board 11, the communication result with the card unit 70, and the like. Is executed to control the game ball payout operation.

  The RAM 215 provided in the payout control microcomputer 150 is provided with an area for holding various data used for controlling the payout operation of the game ball. At least a part of the RAM 215 included in the payout control microcomputer 150 may be a backup RAM that is backed up by a backup power source created in the power supply substrate 10. That is, even if the power supply to the pachinko gaming machine 1 is stopped, at least a part of the contents of the RAM 215 provided in the payout control microcomputer 150 is stored for a predetermined time.

  Next, the operation (action) of the pachinko gaming machine 1 in this embodiment will be described. In the main board 11, when the power supply from the power supply board 10 is started and the reset signal to the game control microcomputer 100 becomes high level (off state), the game control microcomputer 100 is activated, A game control main process as shown in the flowchart of FIG. 28 is executed. Note that each process described below is executed by the CPU 103 provided in the game control microcomputer 100. An interrupt request based on various interrupt factors generated by the timer circuit 106, the serial communication circuit 107, etc. provided in the game control microcomputer 100 is for causing the CPU 103 to execute predetermined interrupt processing. The concept including the CPU 103 and various circuits other than the CPU 103 is sometimes referred to as a game control microcomputer 100. When the game control main process shown in FIG. 28 is started, in the game control microcomputer 100, first, the CPU 103 sets the interrupt prohibition (step S1) and sets the interrupt mode (step S2). For example, in step S2, the value (1 byte) of the specific register (I register) of the game control microcomputer 100 and the interrupt vector (1 byte: the least significant bit is “0”) output by the built-in device are synthesized. By this, or when the CPU 103 reads out stored data in a predetermined area (for example, interrupt vector area) of the ROM 104, an interrupt mode for maskable interrupts in which an interrupt address is generated is set. When an interrupt that can be masked occurs, the microcomputer 100 for game control is automatically set to be in an interrupt disabled state, and the contents of the program counter may be saved in the stack.

  Subsequently, settings relating to the stack pointer such as setting of a stack pointer designation address are performed (step S3). The built-in device register is set (initialized) (step S4). For example, in the process of step S4, settings (initialization) of built-in devices (built-in peripheral circuits) such as the timer circuit 106 and the input / output port 108 may be performed.

  After the process of step S4 is executed, the power-off signal is turned off by checking the state of the 0th bit [bit 0] (FIG. 23) at the input port # 0 included in the input / output port 108, for example. It is determined whether or not (step S5). When power supply to the pachinko gaming machine 1 is started, various power supply voltages such as VCC gradually increase and reach a specified value. In the process of step S5, it is confirmed that the power-off signal is not output and is in an off state (high level). Here, the game control microcomputer 100 may confirm the state of the power-off signal only once through the input port, but may confirm the state of the power-off signal a plurality of times. For example, if it is confirmed once that the power-off signal is in the OFF state, the power-off signal is confirmed once again after a predetermined time (for example, 0.1 second) has elapsed. At this time, if the power-off signal is off, it is determined that the power-off signal is off. On the other hand, if the state of the power-off signal is on at this time, the state of the power-off signal may be confirmed again after a predetermined time has elapsed. In addition, the number of times of reconfirming the state of the power-off signal may be one time or a plurality of times. Further, it is possible to check twice and check again when the check results do not match.

  When the power-off signal is in the ON state in step S5 (step S5; No), after waiting for a predetermined time (for example, 0.1 second) to elapse (step S6), the process returns to step S5, and the power It is determined again whether or not the disconnection signal is off. Thereby, the game control microcomputer 100 can confirm that the power supply voltage is stable. When the power-off signal is off in step S5 (step S5; Yes), for example, the state of the second bit [bit 2] (FIG. 23) in the input port # 0 included in the input / output port 108 is checked. By doing so, it is determined whether or not the clear signal is in an ON state (step S7). At this time, if the clear signal is on (step S7; Yes), for example, the clear flag provided in the game control flag setting unit 133 is set to the on state (step S8). On the other hand, when the clear signal is in the off state (step S7; No), the process of step S8 is skipped and the clear flag remains in the off state.

  Here, the game control microcomputer 100 may confirm the state of the clear signal only once through the input port, but may confirm the state of the clear signal a plurality of times. For example, once it is confirmed that the state of the clear signal is off, the state of the clear signal is confirmed once again after a predetermined time (for example, 0.1 second) has elapsed. At this time, if the clear signal is off, it is determined that the clear signal is off. On the other hand, if the state of the clear signal is on at this time, the state of the clear signal may be confirmed again after a predetermined time has elapsed. Note that the number of times of reconfirming the state of the clear signal may be one time or may be a plurality of times. Further, it is possible to check twice and check again when the check results do not match.

  Thereafter, a delay process for delaying the start timing of the game control process for controlling the progress of the game by executing the software is set (step S9). As a specific example, an initialization weight number designation value is set in a wait counter provided in the game control counter setting unit 135. Subsequently, the delay process based on the setting in step S9 is started, and the setting relating to the execution of the delay process is updated, for example, by subtracting 1 from the count value in the wait counter (step S10). Then, for example, it is determined whether or not a predetermined delay time has elapsed by determining whether or not the count value in the wait counter has reached a predetermined delay end determination value (step S11). Here, the data indicating the delay end determination value may be stored in advance in the ROM 104 or the like. For example, the delay end determination value is from when the game control process becomes executable until at least execution of various processes for payout control by the payout control microcomputer 150 mounted on the payout control board 15 is started. A predetermined reference value may be used so that the delay time becomes longer than the time.

  When the delay time has not elapsed in step S11 (step S11; No), the process returns to step S10. When the delay time has elapsed (step S11; Yes), the RAM 105 is set to be accessible (step S12). Subsequently, it is determined whether or not the clear flag is on (step S13). When the clear flag is off (step S13; No), data check of the RAM 105 is performed to determine whether or not the check result is normal (step S14). In the process of step S14, for example, a checksum is calculated using data stored in a specific area of the RAM 105, and the calculated checksum is compared with the checksum stored in the main checksum buffer. Here, the main checksum buffer stores a checksum calculated by the same processing when the power supply was stopped last time. If the comparison results do not match, the data in the specific area of the RAM 105 is different from the data when the power supply is stopped, so that the check result is determined to be not normal.

  When the check result in step S14 is normal (step S14; Yes), it is determined whether or not the main backup flag provided in the game control flag setting unit 133 is on (step S15). The state of the main backup flag is set in the game control flag setting unit 133 when the power supply is stopped. The main backup flag setting location is backed up by the backup power source, so that the state of the main backup flag is saved even when the power supply is stopped. In step S15, for example, if “55H” is set in the game control flag setting unit 133 as the value of the main backup flag, it is determined that there is a backup (ON state). On the other hand, if a value other than “55H” is set, it is determined that there is no backup (OFF state). Note that the determination as to whether or not the main backup flag is turned on as in step S15 is performed prior to the determination of the check result as in step S14, and the data check of the RAM 105 is performed when the main backup flag is turned on. You may make it determine whether a result is normal.

  If the main backup flag is on in step S15 (step S15; Yes), after the main backup flag is cleared and turned off (step S16), the internal state of the game control microcomputer 100 is supplied with power. Settings at the time of recovery for returning to the state when stopped are performed (step S17). As a specific example, in the process of step S17, the start address of the backup setting table stored in the ROM 104 is set as a pointer, and the contents of the backup setting table are sequentially set in the work area in the RAM 105. Here, the work area of the RAM 105 is backed up by a backup power source, and initialization data for an area that may be initialized among the work areas may be set in the backup time setting table.

  Further, when the clear flag is on in step S13 (step S13; Yes), when the check result is not normal in step S14 (step S14; No), or the main backup flag is off in step S15. If there is (step S15; No), the RAM 105 is initialized (step S18). Subsequent to the processing of step S18, settings at the time of initialization for setting the internal state and the like of the game control microcomputer 100 to the initial state are performed (step S19). As a specific example, in the process of step S19, the start address of the initialization setting table stored in the ROM 104 is set as a pointer, and the contents of the initialization setting table are sequentially set in the work area in the RAM 105. .

  After executing the processing of step S17 or step S19, a timer interrupt is generated every predetermined time (for example, 2 milliseconds) by setting a register of the timer circuit 106 provided in the gaming control microcomputer 100, for example. The internal setting of the game control microcomputer 100 is performed (step S20). Thereafter, the CPU 103 executes a random number initial setting process for initial setting of the random number generation operation based on the random number initial setting data (KRSS) read from the ROM 104 (step S21).

  Following the random number initial setting process in step S21, a serial communication initial setting process for initial setting of the serial communication operation is executed (step S22). Thereafter, an interrupt initial setting process for performing an initial setting related to the interrupt process executed based on the interrupt request is executed (step S23). Then, the game control microcomputer 100 sets the interrupt permitted state (step S24), and waits for the occurrence of various interrupts. At this time, it is determined whether or not the power-off signal has been turned on (whether or not it has been output) (step S25). If it is off (step S25; No), the generation of various interrupts is awaited. When the power-off signal is turned on (step S25; Yes), after executing the main-side power-off process (step S26), a predetermined loop process is executed to control the game by stopping power supply. Wait until the microcomputer 100 stops operating. In the process of step S25, the state of the power-off signal may be confirmed only once via the input port, but the state of the power-off signal may be confirmed a plurality of times. For example, if it is confirmed once that the power-off signal is in the OFF state, the power-off signal is confirmed once again after a predetermined time (for example, 0.1 second) has elapsed. At this time, if the power-off signal is off, it is determined that the power-off signal is off. On the other hand, if the state of the power-off signal is on at this time, the state of the power-off signal may be confirmed again after a predetermined time has elapsed. Moreover, the number of times of reconfirming the state of the power-off signal may be one time or may be a plurality of times. Further, it is possible to check twice and check again when the check results do not match. Thus, when confirming the state of the power-off signal a plurality of times, for example, when the confirmation operation is started or when the first confirmation result and the second confirmation result are compared and there is a mismatch, Retriggering is performed to clear the WDT (watchdog timer) built in the control microcomputer 100. When the retrigger does not occur within a predetermined time due to some cause (for example, program runaway), a user reset is generated based on a timeout signal output from the WDT, and the reset / interrupt controller 102, CPU 103, timer circuit is generated. After initializing each circuit such as 106 and the serial communication circuit 107, execution of the user program may be started from an address indicated by a predetermined vector table to perform automatic recovery.

  In the main-side power-off process in step S26, for example, after the CPU 103 sets the interrupt prohibition, clear data is set in the first and 0th bits [bits 1-0] of the output port # 0 included in the input / output port 108. For example, the settings related to the drive control of the solenoids 81 and 82 are initialized. At this time, in addition to the first and 0th bits [bit 1-0] of the output port # 0, clear data may be set for the output port to be cleared. Subsequently, for example, check data is generated by calculating a checksum using data stored in a specific area of the RAM 105, and the main backup flag provided in the game control flag setting unit 133 is set to an on state. . The check data created at this time is stored in a predetermined area of the RAM 105 such as a main checksum buffer provided in the game control buffer setting unit 136, for example. Then, in the game control microcomputer 100, for example, the CPU 103 prohibits access to the RAM 105 thereafter by setting an access prohibition value in a predetermined RAM access register. Thereby, even if a program runaway occurs due to the stop of power supply, it is possible to prevent the stored contents of the RAM 105 from being damaged. After such main-side power-off processing is executed, a standby state (loop processing) is entered.

  Further, after executing the main-side power-off process in step S26, for example, it is periodically determined whether or not the power-off signal is turned off. When the power-off signal is turned off, the CPU 103 performs the steps shown in FIG. The processing may be resumed in response to the momentary interruption, for example, by proceeding again from S1. Alternatively, after the main-side power-off process is executed in step S26, for example, even if a predetermined time elapses that is longer than the time required until the time-out signal is output from WDT, the power supply board 10 When the power supply is continued, the CPU 103 may restart the process in response to the instantaneous interruption, for example, by proceeding again from step S1 shown in FIG.

  FIG. 29 is a flowchart showing an example of a random number initial setting process executed in step S21 of FIG. In the random number initial setting process shown in FIG. 29, in the game control microcomputer 100, first, the CPU 103 reads the fifth bit [bit 5] of the random number initial setting data (KRSS) stored in the ROM 104 (step S101), Based on the read value, operation setting in the clock signal output circuit 171 provided in the random number circuit 112 is performed (step S102). For example, when the read value in step S101 is “0”, the clock signal S1 output from the clock signal output circuit 171 is the same as the reference clock signal CLK as the internal system clock generated by the reference clock signal generation circuit 111. Set to be a periodic clock signal. When the read value in step S101 is “1”, the clock signal S1 output from the clock signal output circuit 171 is a clock signal having a period 16 times the reference clock signal CLK as the internal system clock. Set to. In the process of step S102, the CPU 103 may directly set the operation of the clock signal output circuit 171 to output the clock signal corresponding to the read value in step S101. The operation of the clock signal output circuit 171 is indirectly controlled by setting control data corresponding to the read value in step S101 in a predetermined register provided internally or externally that can be referred to by the clock signal output circuit 171. You may make it do. When the control data is set in the register in step S102, for example, when the random number circuit 112 starts generating the random number value, the clock signal output circuit 171 refers to the control data stored in the register and controls the control data. By performing the output operation of the clock signal according to the data, the clock signal according to the setting in step S102 can be output.

  Following the processing in step S102, the CPU 103 reads the fourth bit [bit 4] of the random number initial setting data (KRSS) stored in the ROM 104 (step S103), and determines whether or not the read value is “0”. Determination is made (step S104). At this time, if the read value in step S103 is “0” (step S104; Yes), the start value of the first round in the random number value generated in the random number circuit 112 is set to “0001h” which is a default value. A determination to this effect is made (step S105). On the other hand, if the read value in step S103 is “1” (step S104; No), the start value for the first round in the random number value generated in the random number circuit 112 is assigned to each game control microcomputer 100. This is determined based on the ID number that is unique identification information (step S106). Here, in the processing of step S106, for example, the ID number of the game control microcomputer 100 read out from the ROM 104 by the CPU 103 may be set as the start value for the first round for generating a random value as it is. Or you may make it set the value calculated by performing predetermined | prescribed calculation using the ID number of the microcomputer 100 for game control to the start value of the 1st round for producing | generating a random value. For example, the calculation is performed by performing a predetermined scramble process on the ID number of the game control microcomputer 100 read from the ROM 104 by the CPU 103 or an addition / subtraction / multiplication / division operation using the ID number. A value may be used.

  The start value determined in step S105 or step S106 is input to an initial value setting circuit 172 included in the random number circuit 112, and is set as a start value for the first round for generating a random value by the random number circuit 112. Is done. Note that the processing in step S105 and step S106 may be executed by the initial value setting circuit 172 included in the random number circuit 112. For example, when the CPU 103 determines that the read value is “0” in step S <b> 104, a predetermined first initial value setting signal is sent to the random number circuit 112. When the random number circuit 112 receives the first initial value setting signal from the CPU 103, the initial value setting circuit 172 reads data stored in a predetermined register, and inputs an initial value setting signal SK indicating the read value to the random number generation circuit 173. As a result, the start value for the first round for generating the random number value is set to the default value “0001h” (processing corresponding to step S105). On the other hand, when the CPU 103 determines that the read value is “1” in step S104, the second initial value setting signal different from the first initial value setting signal is sent to the random number circuit 112. When the random number circuit 112 receives the second initial value setting signal from the CPU 103, the initial value setting circuit 172 selects data generated based on the ID number stored in a predetermined register, and the initial value indicating the selected data is displayed. By inputting the value setting signal SK to the random number generation circuit 173, the start value for the first round for generating the random number value is an ID number that is unique identification information given to each game control microcomputer 100. Is set to a value based on (processing corresponding to step S106). Here, as for the ID number stored in the predetermined register, only a numerical value of digits that is equal to or less than “65535” which is the maximum value of the random number value may be extracted and set in the random number generation circuit 173. Alternatively, an ID number stored in a predetermined register is input to an arithmetic circuit (for example, a multiplier circuit) built in the initial value setting circuit 172, so that a predetermined calculation using a numerical value in each digit of the ID number is performed. Data that is executed and indicates a value calculated by this calculation may be set in the random number generation circuit 173. Further, the CPU 103 may directly control the operation of the initial value setting circuit 172 to execute processing corresponding to steps S105 and S106. For example, the CPU 103 is provided for initial value setting control inside or outside the random number circuit 112. Thus, the operation of the initial value setting circuit 172 may be indirectly controlled by setting control data corresponding to the read value in step S103 in a predetermined register that can be referred to by the initial value setting circuit 172. . When the CPU 103 sets control data in the initial value setting control register, the initial value setting circuit 172 is stored in the initial value setting register when the random number circuit 112 starts generating random numbers, for example. By generating an initial value setting operation in accordance with the control data, a start value for the first round corresponding to the read value in step S103 is generated and set in the random number generation circuit 173 Can do.

  After executing one of the processes of steps S105 and S106, the CPU 103 reads the first and 0th bits [bits 1-0] of the random number initial setting data (KRSS) stored in the ROM 104 (step S107), Based on the read value, a random value updating method in the random number circuit 112 is set (step S108). For example, when the read value in step S107 is “00”, the permutation, which is the update order of the random value, is set not to be changed. When the read value in step S107 is “10”, the permutation in the second and subsequent rounds of the random number value is set to be changeable by the user program. Further, when the read value in step S107 is “11”, it is set so that the permutation in the second and subsequent rounds of the random number value is automatically changed. In step S108, the CPU 103 may directly control the random number circuit 112 to set a random number update method corresponding to the read value in step S107. For example, the random number circuit 112 may be provided inside or outside the random number circuit 112. The random number update method in the random number generation circuit 173 may be indirectly controlled by setting control data corresponding to the read value in step S107 in a predetermined register that can be referred to by the random number generation circuit 173. . When the control data is set in the register in step S107, for example, the random number generation circuit 173 refers to the control data stored in the register and performs a random number update operation according to the control data. The permutation for generating the random number value can be changed or held according to the set random number update method.

  Following the processing in step S108, the maximum value among the random values generated by the random number circuit 112 is set (step S109). For example, in step S109, the CPU 103 can set the maximum random value generated by the random number circuit 112 by setting the random number maximum value setting data read from the ROM 104 in the random number generation circuit 173 of the random number circuit 112. You can do it.

  Thereafter, the CPU 103 reads out the third and second bits [bit 3-2] of the random number initial setting data (KRSS) stored in the ROM 104 (step S110). Then, based on the read value in step S110, an initial setting is made regarding the start values for the second and subsequent rounds in the random value generated by the random number circuit 112 (step S111). As a specific example, in the process of step S <b> 111, read data indicating the third and second bits [bit 3-2] of the random number initial setting data (KRSS) read from the ROM 104 by the CPU 103 is sent to the random number circuit 112 or the CPU 103. Refer to the setting related to the start value for the second and subsequent rounds in the 16-bit random number while the CPU 103 is executing the timer interrupt processing for game control by storing it in a predetermined internal register or in a predetermined area of the RAM 105. It is only necessary to perform initial settings that can be performed.

  FIG. 30 is an explanatory diagram showing an example of the contents of the serial communication initial setting process executed in step S22 shown in FIG. In this serial communication initial setting process, first, the CPU 103 reads the first and second serial communication initial setting data (KSCM1 and KSCM2) stored in the ROM 104, and the serial control register provided in the serial communication circuit 107 based on the read value. 205 is set.

  For example, when the fifth bit [bit 5] of the first serial communication initial setting data (KSCM1) is “0”, the TIE that is the seventh bit [bit 7] of the second register SICL2 in the serial control register 205 is set to “0”. On the other hand, when it is “1”, TIE is set to “1”. When the fourth bit [bit 4] of the first serial communication initial setting data (KSCM1) is “0”, TCIE which is the sixth bit [bit 6] of the second register SICL2 in the serial control register 205 is set to “0”. On the other hand, when it is “1”, TCIE is set to “1”. When the third bit [bit 3] of the first serial communication initial setting data (KSCM1) is “0”, the RIE that is the fifth bit [bit 5] of the second register SICL2 in the serial control register 205 is set to “0”. On the other hand, when it is “1”, RIE is set to “1”.

  When the second bit [bit 2] of the first serial communication initial setting data (KSCM1) is “0”, ILIE which is the fourth bit [bit 4] of the second register SICL2 in the serial control register 205 is set to “0”. On the other hand, when it is “1”, ILIE is set to “1”. When the first bit [bit 1] of the first serial communication initial setting data (KSCM1) is “0”, TE that is the third bit [bit 3] of the second register SICL2 in the serial control register 205 is set to “0”. On the other hand, when “1”, TE is set to “1”. When the 0th bit [bit 0] of the first serial communication initial setting data (KSCM1) is “0”, the second bit [bit 2] of the second register SICL2 in the serial control register 205 is set to “0”. On the other hand, when “1”, RE is set to “1”.

  When the third bit [bit 3] of the second serial communication initial setting data (KSCM2) is “0”, the ORIE that is the third bit [bit 3] of the third register SICL3 in the serial control register 205 is set to “0”. On the other hand, when it is “1”, ORIE is set to “1”. When the second bit [bit 2] of the second serial communication initial setting data (KSCM2) is “0”, NEIE which is the second bit [bit 2] of the third register SICL3 in the serial control register 205 is set to “0”. On the other hand, if it is “1”, NEIE is set to “1”. When the first bit [bit 1] of the second serial communication initial setting data (KSCM2) is “0”, the FEIE that is the first bit [bit 1] of the third register SICL3 in the serial control register 205 is set to “0”. On the other hand, when it is “1”, FEIE is set to “1”. When the 0th bit [bit 0] of the second serial communication initial setting data (KSCM2) is “0”, the PEIE which is the 0th bit [bit 0] of the third register SICL3 in the serial control register 205 is set to “0”. On the other hand, when it is “1”, PEIE is set to “1”.

  FIG. 31 is a flowchart showing an example of the interrupt initial setting process executed in step S23 shown in FIG. In this interrupt initial setting process, the CPU 103 reads the highest priority interrupt setting (KHPR) stored in the ROM 104 (step S121), and sets the highest priority interrupt based on the read value (step S122). For example, in the process of step S122, it is specified whether the read value in step S121 is “00h” to “07h”, and the factor of the I class interrupt (IRQ) corresponding to the specified value is the highest priority. The reading order of stored data in a predetermined register is set so as to cause a high interrupt factor. Data indicating the setting of the reading order may be stored in an internal register of the CPU 103, for example. In this case, the CPU 103 preferentially checks the data stored in the internal register when an interrupt request signal input from the reset / interrupt controller 102 to the I class interrupt (IRQ) terminal or the like is turned on. The interrupt process to be executed can be specified.

  After the interrupt enabled state is obtained by executing the processing of step S24 shown in FIG. 28, for example, when a plurality of interrupt factors occur simultaneously in the timer circuit 106, the serial communication circuit 107, etc., step S122 shown in FIG. Based on the setting in, the reset / interrupt controller 102 accepts an interrupt factor having a high priority. When the reset / interrupt controller 102 accepts an interrupt factor, an on-state interrupt request signal is input to, for example, an I class interrupt (IRQ) terminal provided in the CPU 103. When an interrupt request signal in the on state is input to the IRQ terminal by the CPU 103, for example, based on the result of checking the data stored in the internal register, in the order according to the reading order based on the setting in step S122 shown in FIG. For example, a bit value of stored data in a predetermined register such as a timer control register included in the timer circuit 106 or a serial status register 204 included in the serial communication circuit 107 may be read. From the stored data in the register thus read, the interrupt factor that occurred is identified, and the interrupt processing based on each interrupt factor is started by executing a program that starts with the vector address corresponding to the identified interrupt factor. Can do.

  As a specific example, when the highest priority interrupt setting (KHPR) is “05h”, first, the third to zeroth bits [bits 3 to 0] of the first register SIST1 included in the serial status register 204 are read. It is determined whether the bit value is “1”. At this time, if any bit value is “1”, an interrupt process corresponding to the error interrupt factor generated in the serial communication circuit 107 (for example, the serial communication error interrupt process shown in FIG. 32) is executed. For example, an interrupt vector stored in a predetermined area of the ROM 104 is acquired, and a program having the vector address as the head address is executed. When all the bit values in the third to 0th bits [bits 3-0] of the first register SIST1 are “0”, an interrupt request in an on state is sent to the IRQ terminal provided in the gaming control microcomputer 100. It is determined whether or not an external interrupt factor has occurred due to the signal being input for a certain period. At this time, if an external interrupt factor has occurred, interrupt processing corresponding to the external interrupt factor is executed. If no external interrupt factor has occurred, the stored data in the timer control register included in the timer circuit 106 is read. Based on the read value, the timer circuit 106 determines whether or not a timer interrupt factor has occurred. At this time, if a timer interrupt factor has occurred in the timer circuit 106, a timer interrupt process corresponding to the timer interrupt factor (for example, the game control timer interrupt process shown in FIG. 35) is executed. If not, the fifth and fourth bits [bits 5-4] of the first register SIST1 included in the serial status register 204 are read to determine whether any bit value is “1”. . At this time, if any bit value is “1”, a reception interrupt process (for example, the serial reception interrupt process shown in FIG. 33) corresponding to the reception interrupt factor generated in the serial communication circuit 107 is executed. If any bit value is “0”, the seventh and sixth bits [bits 7-6] of the first register SIST1 included in the serial status register 204 are read, and any bit value becomes “1”. It is determined whether or not. At this time, if any bit value is “1”, a transmission interrupt process (for example, a serial transmission interrupt process shown in FIG. 34) corresponding to the transmission interrupt factor generated in the serial communication circuit 107 is executed.

  Thus, by checking whether or not interrupt factors have occurred in the order according to the priority order based on the setting in step S122 shown in FIG. 31, when a plurality of interrupt factors occur at the same time, for example, FIG. The interrupt processing based on the interrupt factor with the higher priority is executed at the default priority as shown in FIG. 5) or the priority changed by the highest priority interrupt setting (KHPR) stored in the ROM 104. It is executed with priority over interrupt processing based on factors.

  For example, when the highest priority interrupt setting (KHPR) stored in the ROM 104 is “06h”, the default priority order as shown in FIG. 13B is set by the setting in step S122 shown in FIG. As shown in FIG. 13A, the priority is changed so that the reception interrupt request from the serial communication circuit 107 has the highest priority. In this case, the interrupt process based on the reception interrupt request from the serial communication circuit 107 is executed more preferentially than the interrupt process based on the error interrupt request from the serial communication circuit 107. As shown in FIG. 13B, at the time of default, the interrupt process based on the interrupt request from the timer circuit 106 is executed with priority over the interrupt process based on the interrupt request from the serial communication circuit 107. It is set. In contrast, when the highest priority interrupt setting (KHPR) stored in the ROM 104 is any one of “05h”, “06h”, and “07h”, each is based on an error interrupt request from the serial communication circuit 107. The interrupt process, the interrupt process based on the reception interrupt request, and the interrupt process based on the transmission interrupt request are executed with higher priority than the interrupt process based on the interrupt request from the timer circuit 106.

  FIG. 32 is a flowchart showing an example of a serial communication error interrupt process executed each time an error interrupt occurs in the serial communication circuit 107 provided in the game control microcomputer 100. Here, the serial communication circuit 107 includes the serial status register 204 when an overrun error occurs based on the settings in the third to zeroth bits [bits 3-0] of the third register SICL3 included in the serial control register 205. The third bit [bit 3] of the first register SIST1 is set to “1” and turned on, and the second bit [bit 2] of the first register SIST1 is set to “1” due to the occurrence of a noise error. The first register that is set and turned on, the first bit [bit 1] of the first register SIST1 is set to "1" due to the occurrence of a framing error, and the first register that is turned on due to the occurrence of a parity error Any of the cases where the 0th bit [bit 0] of SIST1 is set to “1” and turned on. When the actual factor is generated, to generate an error interrupt. More specifically, when an error interrupt factor occurs in the serial communication circuit 107, an interrupt request is transmitted from the serial communication circuit 107 to the reset / interrupt controller 102, and as described above, the reset / interrupt controller 102 receives the interrupt factor. Is received, an interrupt request signal in an on state is input to an IRQ terminal included in the CPU 103, so that the CPU 103 is notified of the occurrence of an interrupt.

  In the serial communication error interrupt process shown in FIG. 32, in the game control microcomputer 100, first, the CPU 103 sets the transmission operation unit 202 provided in the serial communication circuit 107 to an unused state (step S41). As a specific example, the CPU 103 sets the transmission operation unit 202 to “0” by setting TE that is the third bit [bit 3] of the second register SICL2 in the serial control register 205 included in the serial communication circuit 107 to “0”. Set to not use. Subsequently, the CPU 103 sets the reception operation unit 201 provided in the serial communication circuit 107 to an unused state (step S42). As a specific example, the CPU 103 sets the reception operation unit 201 to “0” by setting RE, which is the second bit [bit 2] of the second register SICL2, in the serial control register 205 included in the serial communication circuit 107. Set to not use. Thereafter, in the game control microcomputer 100, for example, the CPU 103 sets the serial communication error flag provided in the game control flag setting unit 133 to the on state (step S43).

  FIG. 33 is a flowchart showing an example of a serial reception interrupt process executed each time a reception interrupt occurs in the serial communication circuit 107 provided in the game control microcomputer 100. In the serial reception interrupt process shown in FIG. 33, the game control microcomputer 100 first sets the payout notification command reception count value, which is the value of the payout notification command reception counter provided in the game control counter setting unit 135, to a predetermined count maximum. The CPU 103 determines whether or not it is a value (for example, “11”) (step S51).

  When the count reaches the maximum value in step S51 (step S51; Yes), the value of the payout notification command reception counter is set to a predetermined initial value (eg, “0”) (step S52). On the other hand, when the count is not the maximum value in step S51 (step S51; No), 1 is added to the value of the payout notification command reception counter (step S53). After executing one of the processes of steps S52 and S53, the CPU 103 reads the stored data in the serial communication data register 203 provided in the serial communication circuit 107 (step S54), and the read data is used as a payout reception command buffer. The received command buffers # 1 to # 12 provided in 191 are stored in the one corresponding to the value of the payout notification command reception counter (step S55).

  FIG. 34 is a flowchart showing an example of a serial transmission interrupt process executed each time a transmission interrupt occurs in the serial communication circuit 107 provided in the game control microcomputer 100. In the serial transmission interrupt process shown in FIG. 34, in the game control microcomputer 100, first, the CPU 103 determines whether or not the generated transmission interrupt is an interrupt at the time of transmission data empty (step S61). If the transmission data is empty (step S61; Yes), the transmission setting enable flag provided in the game control flag setting unit 133 is set to the on state (step S62).

  When it is not an interrupt at the time of transmission data empty in step S61 (step S61; No), it is determined whether or not the transmission interrupt is an interrupt at the completion of transmission (step S63). If it is an interrupt at the completion of transmission (step S63; Yes), a transmission completion flag provided in the game control flag setting unit 133 is set to an on state (step S64). If it is not an interruption at the time of completion of transmission in step S63 (step S63; No), a flag corresponding to the type of transmission interruption that has occurred is set to an on state (step S65).

  FIG. 35 is a flowchart showing an example of a game control timer interrupt process executed each time a timer interrupt occurs in the game control microcomputer 100. In the game control timer interrupt process shown in FIG. 35, in the game control microcomputer 100, first, after the CPU 103 saves the internal register (step S71), a predetermined switch process is executed, so that the switch circuit 114 is passed through. The state of the detection signal input from each switch is determined (step S72). Subsequently, by executing predetermined error processing, abnormality diagnosis of the pachinko gaming machine 1 is performed, and a warning can be generated if necessary according to the diagnosis result (step S73). After that, by executing a predetermined information output process, for example, data such as jackpot information, starting information, probability variation information supplied to a hall management computer installed outside the pachinko gaming machine 1 is output (step S74). ).

  Following the information output process, a software random number update process for updating the random number value R2 for probability variation determination and the random value R3 for determining the initial value is executed (step S75). Next, for example, based on the execution result of the switch process in step S72, the game ball to be awarded is paid out in accordance with the input of the start winning signal SS1 from the start port switch 22 or the input of the detection signal from the count switch 24. Prize ball processing for setting the number is executed (step S76). Further, the CPU 103 executes main-side reception processing for performing various settings according to the payout notification command received from the payout control board 15 by serial communication (step S77).

  In the main-side reception process in step S77, it is determined whether or not a reception command is stored in the payout reception command buffer 191 of the game control buffer setting unit 136, and when it is stored, the reception command is read out. Then, for example, processing corresponding to the type of received command, such as processing for setting or clearing a flag according to the type of the received received command, is executed. When the main side reception process in step S77 is started, it is first determined whether or not the serial communication error flag is on. If it is on, the main side reception process may be terminated as it is. . Thus, when an error occurs in the operation of the serial communication circuit 107, it is possible to control to stop receiving the payout notification command transmitted from the payout control board 15. Further, when the reception command is read from the payout reception command buffer 191 in the main-side reception processing in step S77, the exclusive OR of the first byte and the second byte in the reception command is calculated, and the calculated calculation By determining whether or not the result is a normal value, it may be checked whether or not the received command is an appropriate command. In this embodiment, the payout notification command transmitted from the payout control board 15 to the main board 11 is configured to be the second byte by reversing the first byte. As a result of calculating the exclusive OR of the first byte and the second byte, if all the bit values are “1”, it can be determined that the received command is an appropriate command.

  Thereafter, the CPU 103 executes special symbol process processing (step S78). In the special symbol process, the value of the special symbol process flag provided in the game control flag setting unit 133 is updated according to the progress of the game in the pachinko gaming machine 1, and the display operation control or special in the special symbol display device 4 is performed. Various processes are selected and executed in order to set the special winning opening / closing operation in the variable winning ball apparatus 7 in a predetermined procedure. Following the special symbol process, a normal symbol process is executed (step S79). The CPU 103 executes normal symbol process processing to control the display operation (for example, lighting and extinguishing of the LED) of the normal symbol display 40, so that variable display of the normal symbol (for example, lighting / blinking display) and the like Setting of tilt control of the movable blade piece in the normal variable winning ball apparatus 6 is enabled.

  Further, the CPU 103 transmits a payout control command from the main board 11 to the payout control board 15 by executing a payout command control process (step S80). For example, in the payout command control process, it is determined whether or not a transmission command is stored in the payout transmission command buffer 192 of the game control buffer setting unit 136, and when stored, stored data corresponding to the transmission command is stored. Is read. Then, the read data is set in the serial communication data register 203 provided in the serial communication circuit 107. When the payout command control process in step S80 is started, it is first determined whether or not the serial communication error flag is on. If it is on, the payout command control process is terminated as it is. Also good. Thus, when an error occurs in the operation of the serial communication circuit 107, it is possible to control to stop sending the payout control command to the payout control board 15. Further, when the data corresponding to the transmission command is set in the serial communication data register 203 in the payout command control processing in step S80, the transmission setting enable flag and the transmission completion flag provided in the game control flag setting unit 133 are checked. Thus, it may be determined whether the data set is possible, whether the command transmission is completed, or the like.

  After executing the payout command control process in step S80, the CPU 103 causes the main board 11 to transmit the effect control command to the effect control board 12 by executing the effect command control process (step S81). Thereafter, the contents of the register saved in step S71 are restored (step S82), and the game control timer interrupt process is terminated.

  FIG. 36 is a flowchart showing an example of the switch process executed in step S72 of FIG. In the switch processing shown in FIG. 36, the gaming control microcomputer 100 first starts by checking the state of the seventh bit [bit 7] of the input port # 0 included in the input / output port 108 by the CPU 103, for example. It is determined whether or not the start winning signal SS1 transmitted from the mouth switch 22 is in an ON state (step S201). At this time, if the start winning signal SS1 from the start port switch 22 is on (step S201; Yes), the value of the start port switch timer provided in the game control timer setting unit 134 is incremented by 1 and updated ( Step S202).

  Subsequent to step S202, the CPU 103 determines whether or not the value of the start port switch timer has reached a predetermined switch-on determination value (eg, “2”) (step S203). When the value of the start-up switch timer is a switch-on determination value in step S203 (step S203; Yes), a period (for example, 4 milliseconds) during which the game control timer interruption process is executed a predetermined number of times (for example, twice) ), It is determined that the start winning signal SS1 from the start port switch 22 has been continuously turned on, and the start winning flag provided in the game control flag setting unit 133 is set to the on state (step S204). . As described above, the switch-on determination value used for the determination in step S203 is the time from when the timer circuit 174 included in the random number circuit 112 starts measuring the input time of the start winning signal SS1 until the output signal is turned on. It is only necessary to be determined so that the start winning signal SS1 can be identified as being on for a period longer than a required period (for example, 3 milliseconds).

  If the start winning signal SS1 from the start opening switch 22 is off in step S201 (step S201; No), the start winning flag is cleared and turned off (step S205), and the start opening switch timer is set. Is cleared and set to a predetermined timer initial value (eg, “0”) (step S206).

  When the value of the start-up switch timer is different from the switch-on determination value in step S203 (step S203; No), or after performing any of the processes in steps S204 and S206, check processing for other switches is executed. Then, the timer value is updated or the flag is set or cleared according to the state of the detection signal input from each switch (step S207).

  FIG. 37 is a flowchart showing an example of error processing executed in step S73 of FIG. In the error processing shown in FIG. 37, in the gaming control microcomputer 100, first, for example, the CPU 103 checks the state of the first bit [bit 1] of the input port # 0 included in the input / output port 108, etc. It is determined whether the clock signal S1 transmitted from the clock signal output circuit 171 of the circuit 112 is at a high level or a low level (step S221).

  When the clock signal S1 is at the high level in step S221 (step S221; Yes), the second monitoring timer provided in the game control timer setting unit 134 is cleared and initialized (step S222). The timer value in the monitoring timer is incremented by 1 (step S223). On the other hand, when the clock signal S1 is at the low level in step S221 (step S221; No), the first monitoring timer is cleared and initialized (step S224), and the timer value in the second monitoring timer is set to 1. Add (step S225).

  After executing one of the processes of steps S223 and S225, the CPU 103 determines whether or not the timer value in any of the first and second monitoring timers has reached a predetermined value that is predetermined as a signal monitoring upper limit value. Is determined (step S226). At this time, if the timer value has reached the signal monitoring upper limit value (step S226; Yes), it is determined that an abnormality has occurred in the reference clock signal generation circuit 111 or the clock signal output circuit 171, and the effect control board 12 is informed. Is set to transmit the error notification start # 1 command (step S227). For example, in the process of step S227, the CPU 103 reads the control data stored in the ROM 104 for transmitting the error notification start # 1 command, and outputs each bit [bits 0 to 7] of the output port # 1 included in the input / output port 108. ] May be set.

  After executing the process of step S227, a predetermined initialization process is executed (step S228). For example, in the process of step S228, check data is created by calculating the checksum using the data stored in the specific area of the RAM 105, and the check data is stored in the main checksum buffer of the game control buffer setting unit 136. . In step S228, the RAM 105 is set to an access prohibited state. At this time, the CPU 103 may reset the operation of the random number circuit 112 by sending an initialization signal for initializing each circuit provided in the random number circuit 112. Subsequently, when the CPU 103 shifts to the HALT (stopped) state (step S229), the input state initial confirmation process is completed, and the execution of the process for controlling the progress of the game by the CPU 103 is stopped. Note that after executing the process of step S227, only the initialization process may be performed to end the input state initial confirmation process, or only the transition to the HALT state may be performed, followed by a user reset or the like. Each unit may be initialized.

  If the timer values of the first and second monitoring timers have not reached the signal monitoring upper limit value in step S226 (step S226; No), the reach number counter provided in the game control counter setting unit 135 is updated. It is determined whether or not the reach count value which is a value exceeds a predetermined value (for example, “10”) predetermined as the reach continuous upper limit value (step S230). At this time, if the reach number count value exceeds the reach continuous upper limit value (step S230; Yes), it is determined that an abnormality has been detected in the random number generation operation in the random number circuit 112, and the effect control board 12 is determined. Settings for transmitting the error notification start # 2 command are performed (step S231). After executing step S231, the process proceeds to step S227 described above.

  If the reach count value is less than or equal to the reach continuous upper limit value in step S230 (step S230; No), the normal lose count count value, which is the value of the normal lose count counter provided in the game control counter setting unit 135, is normal. It is determined whether or not a predetermined value (for example, “50”) predetermined as the continuous loss upper limit value is exceeded (step S232). At this time, if the normal loss continuous count value is equal to or less than the normal loss continuous upper limit value (step S232; No), the error processing is terminated. On the other hand, if the normal loss continuous count value exceeds the normal loss continuous upper limit value in step S232 (step S232; Yes), it is determined that an abnormality has been detected in the random number generation operation in the random number circuit 112, and the effect control is performed. Setting for transmitting the error notification start # 3 command to the board 12 is performed (step S233). After executing step S233, the process proceeds to step S227 described above.

  FIG. 38 is a flowchart showing an example of the software random number update process executed in step S75 of FIG. In the software random number update process shown in FIG. 38, in the game control microcomputer 100, first, the CPU 103 adds 1 to the probability variation determination random number count value that is the value of the probability variation determination random number counter provided in the game control counter setting unit 135. And update (step S241). At this time, it is determined whether or not the probability variation determination random number count value after the update in step S241 has exceeded a predetermined maximum count value “100” (step S242).

  When the random number count value for probability variation determination exceeds the maximum count value in step S242 (step S242; Yes), “1” that is the minimum value in the random number value R2 for probability variation determination is set as the random number count value for probability variation determination. It sets (step S243). On the other hand, when the random number value for probability variation determination is equal to or less than the maximum count value in step S242 (step S242; No), the process of step S243 is skipped.

  Subsequently, the CPU 103 compares the random number count value for probability variation determination with the initial value in the random number value R2 for probability variation determination indicated by the data stored in the random number initial value buffer provided in the game control buffer setting unit 136 (step S244). . As a comparison result in step S244, the CPU 103 determines whether or not the probability variation determination random number count value has returned to the initial value (step S245).

  When the probability variation determination random number count value has returned to the initial value in step S245 (step S245; Yes), by acquiring the stored data of the initial value determination random number counter provided in the game control counter setting unit 135, The random value R3 for determining the initial value is read (step S246). Then, the random value R3 read in step S246 is set in the probability variation determination random number counter as a new initial value in the probability variation determination random value R2 (step S247). At this time, the random number value R3 read in step S246 is stored in the random number initial value buffer (step S248). Further, when the probability variation determination random number count value does not return to the initial value in step S245 (step S245; No), the processing of steps S246 to S248 is skipped.

  Thereafter, the game control microcomputer 100 executes processing for updating other determination random numbers updated by software (step S249). Further, the CPU 103 updates the initial value determining random value R3 by adding 3 to the initial value determining count value which is the value of the initial value determining counter, for example (step S250). In the process of step S250, it is determined whether or not the updated initial value determination count value exceeds “100”, which is a predetermined maximum count value, and if it exceeds, for example, “1”, “2”. , “3” may be set in the initial value determination counter.

  FIG. 39 is a flowchart showing an example of the special symbol process executed in step S78 shown in FIG. In the special symbol process shown in FIG. 39, in the game control microcomputer 100, first, the CPU 103 determines whether or not the start winning flag provided in the game control flag setting unit 133 is ON (step S261). When the start winning flag is on in step S261 (step S261; Yes), after the winning process is executed (step S262), the start winning flag is cleared and turned off (step S263). On the other hand, when the start winning flag is OFF in step S261 (step S261; No), the winning process in step S262 and the process in step S263 are skipped.

  FIG. 40A is a flowchart showing an example of the winning process executed in step S262. In the winning process shown in FIG. 40 (A), the CPU 103 first sets the reserved storage number, which is the number of numerical data indicating the random value R1 for jackpot determination stored in the special figure storage unit 131, to a predetermined upper limit. It is determined whether or not it is a value (for example, “4”) (step S301). At this time, if the reserved storage number is the upper limit value (step S301; Yes), the start detection by the current winning is invalidated, and the winning process is ended as it is.

  When the number of pending storages is less than the upper limit value in step S301 (step S301; No), the stored value in the random value register 176 of the random number circuit 112 is read as the random number R1 for jackpot determination (step S302). For example, in the process of step S302, after setting the output control signal SC to the ON state by setting predetermined control data in the seventh bit [bit 7] of the output port # 0 included in the input / output port 108, The random value R1 read from the random value register 176 is acquired by taking in the random value output signals SO0 to SO15 input to the respective bits [bits 0 to 7] of the input ports # 1 and # 2.

  Subsequently, the random value R1 read in step S302 is set at the head of the empty entry in the special figure storage unit 131 (step S303). At this time, the number of reserved storage in the special figure storage unit 131 is incremented by 1 (step S304). After executing the process of step S304, a reach determination random number value R4 corresponding to the read value read from the random value register 176 of the random number circuit 112 in step S302 is set (step S305). For example, in the process of step S305, as shown in FIG. 40B, the random number value R4 for reach determination is set to any one of “1” to “10” corresponding to the read value in step S302. And set in a reach determination random number counter provided in the game control counter setting unit 135. Thus, the reach determination random number counter updates the reach determination random number value R4 in synchronization with the jackpot determination random number value R1 read from the random number value register 176.

  When the start winning flag is OFF in step S261 shown in FIG. 39, or after executing the process of step S263, for example, the CPU 104 responds to the value of the special symbol process flag provided in the game control flag setting unit 133. The following processes of steps S270 to S276 are executed.

  The special symbol normal process in step S270 is executed when the value of the special symbol process flag is “0”. FIG. 41 is a flowchart showing an example of the special symbol normal process executed in step S270. When the special symbol normal process is started, the CPU 103 first determines whether or not the number of reserved memories in the special symbol storage unit 131 is “0” (step S311). When the number of stored memories is “0” (step S311; Yes), the special symbol normal process is terminated as it is.

  When the number of stored memories is other than “0” in step S311 (step S311; No), it is determined that the start condition for executing the special figure game is satisfied, and the special figure holding storage unit 131 holds the hold. The random number R1 for jackpot determination stored corresponding to the number “1” is read (step S312). At this time, 1 is subtracted from the number of reserved memories in the special figure reservation storage unit 131, and lower entries in the special figure reservation storage unit 131 (for example, second to fourth entries corresponding to the reservation numbers “2” to “4”). Is shifted to the upper level by one entry (step S313).

  Thereafter, the jackpot probability variation determination process is executed based on the jackpot determination random number R1 read in step S312 (step S314). After the big hit probability change determination process is executed in step S314, the value of the special symbol process flag is updated to “1” (step S315), and the special symbol normal process is terminated.

  FIG. 42 is a flowchart illustrating an example of the big hit probability variation determination process executed in step S314. In the big hit probability change determination process shown in FIG. 42, the CPU 103 first checks whether or not the probability change flag provided in the game control flag setting unit 133 is on, for example, to determine whether or not a high probability state (probable change). ) Is determined (step S401).

  When the probability change is in progress in step S401 (step S401; Yes), as a table for determining whether or not the display result in the variable display of the special figure game or the decoration symbol is “big hit”, FIG. ) Is set (step S402). On the other hand, if the probability change is not in progress in step S401 (step S401; No), it is determined that the game is in the normal gaming state, and a normal big hit determination table 140 as shown in FIG. Step S403).

  After executing one of the processes of steps S402 and S403, it is determined whether or not the jackpot determination random number value R1 read in step S312 of FIG. "Is determined (step S404). If the random value R1 does not match the big hit determination value data in step S404 (step S404; No), the big hit probability variation determination process is terminated as it is.

  On the other hand, when the random value R1 matches the big hit determination value data in step S404 (step S404; Yes), the big hit flag provided in the game control flag setting unit 133 is set to the on state (step S405). At this time, the value of the probability variation determination random number counter provided in the game control counter setting unit 135 is read to extract the probability variation determination random number value R2 (step S406). Then, it is determined whether or not the random number value R2 extracted in step S406 matches predetermined probability variation determination value data (for example, numerical data indicating an odd number) (step S407).

  When the random value R2 matches the probability variation determination value data in step S407 (step S407; Yes), the probability variation confirmation flag provided in the game control flag setting unit 133 is set to the on state (step S408). On the other hand, when the random value R2 does not match the probability variation determination value data in step S407 (step S407; No), the probability variation confirmation flag is cleared and turned off (step S409).

  The variable display start process in step S271 shown in FIG. 39 is executed when the value of the special symbol process flag is “1”. FIG. 43 is a flowchart illustrating an example of the variable display start process executed in step S271. When the variable display start process is started, the CPU 103 first determines whether or not the big hit flag is on (step S331). If the big hit flag is ON (step S331; Yes), the big hit variable display pattern determination table stored in a predetermined area of the ROM 104 or the like is set as a table used to determine the variable display pattern (step S332). ). At this time, the reach number counter and the normal loss number counter are cleared and initialized (step S333).

  If the big hit flag is off in step S331 (step S331; No), the reach determination random number value R4 stored in the reach determination random number counter is read (step S334). Then, with reference to the reach determination table 142 shown in FIG. 17, it is determined whether or not the read value in step S334 matches the reach determination value data, whereby the decorative symbol variable display mode in the image display device 5 is determined. It is determined whether or not to reach (step S335).

  If it is determined in step S335 that reach is to be made (step S335; Yes), a reach variable display pattern determination table stored in a predetermined area of the ROM 104 or the like is used as a table for determining the variable display pattern. Setting is made (step S336). At this time, the normal lose count counter is cleared and initialized (step S337), while the reach count value which is a count value in the reach counter is incremented by 1 (step S338).

  When it is determined in step S335 that the reach is not performed (step S335; No), a normal display variable display pattern determination table used for determining a variable display pattern is stored in a predetermined area of the ROM 104 or the like. Is set (step S339). At this time, the reach counter is cleared and initialized (step S340), while the normal lose count value which is the count value in the normal lose counter is incremented by 1 (step S341).

  After executing any of the processes in steps S333, S338, and S341, the variable set in any of steps S333, S338, and S341 based on, for example, a random number for variable display pattern determination obtained from a predetermined random number counter. By referring to the display pattern determination table or the like, the variable display pattern to be used for the variable display of the special game and the decorative design satisfying the start condition is determined (step S342).

  After executing the process of step S342, the CPU 103 performs setting for transmitting a display result notification command to the effect control board 12 (step S343). For example, in the processing of step S343, the game control buffer setting unit 136 is provided with control data corresponding to whether or not the special symbol determined as the confirmed special symbol in the special symbol game or the probability variation confirmation flag is on. What is necessary is just to set to the transmission command buffer for production. Here, the confirmed special symbol in the special symbol game may be determined based on the determination result of whether or not the big hit flag is on, the random number value for determining the fixed symbol read from the predetermined random number counter, or the like. As a specific example, when the big hit flag is on, the confirmed special symbol in the special game is determined to be “7”, which is the big hit symbol. On the other hand, when the big hit flag is off, in a special game from among the lost symbols, such as by referring to a predetermined lost symbol determination table based on the random number value for determining the fixed symbol read from the predetermined random number counter. What is necessary is just to determine what becomes a definite special symbol. If the confirmed special symbol in the special figure game is determined to be “7”, which is a jackpot symbol, and the probability variation confirmation flag is on, the confirmed special symbol in the special figure game becomes “7”, which is a jackpot symbol, and the probability variation Control data for transmitting a display result notification command (for example, command 9002h) indicating a big hit is set in the effect transmission command buffer. If the confirmed special symbol in the special figure game is determined to be “7”, which is a jackpot symbol, and the probability variation confirmation flag is OFF, the confirmed special symbol in the special figure game becomes “7”, which is a jackpot symbol. Control data for transmitting a display result notification command (for example, command 9001h) indicating that it is a big hit is set in the effect transmission command buffer. When the confirmed special symbol in the special figure game is determined to be other than “7”, which is a jackpot symbol, a display result notification command (for example, command 9000h) is transmitted indicating that the confirmed special symbol in the special figure game becomes a lost symbol. Control data for performing is set in the effect transmission command buffer.

  Subsequently, the CPU 103 performs setting for transmitting a variable display start command corresponding to the variable display pattern determined in step S342 to the effect control board 12 (step S344). For example, in the process of step S344, control data corresponding to the variable display pattern determined in step S342 may be set in the effect transmission command buffer. After executing the process of step S344, the value of the special symbol process flag is updated to “2” (step S345), and the variable display start process is terminated.

  The variable display control process of step S272 shown in FIG. 39 is executed when the value of the special symbol process flag is “2”. This variable display control process includes a process of measuring the remaining variable display time of the special symbol in the special symbol game by the special symbol display device 4 based on the value of the variable display time timer. When the special symbol variable display time (total variation time) has elapsed, the value of the special symbol process flag is updated to “3”.

  The variable display stop process in step S273 is executed when the value of the special symbol process flag is “3”. In the variable display stop process, it is determined whether the variable display result of the special symbol or the decorative symbol is a big hit or a loss. Further, when the pachinko gaming machine 1 is in a high probability state, it is determined whether or not the gaming state is returned from the high probability state to the normal gaming state, and if it is determined to return, the gaming state in the pachinko gaming machine 1 has a high probability. Transition from state to normal gaming state. As a specific example, when the number of special figure games executed in the high probability state reaches a predetermined probability variation end reference value (for example, “100”), it is determined to return from the high probability state to the normal game state. When the variable display result is a big hit, the value of the special symbol process flag is updated to “4”, while when the variable display result is lost, the value of the special symbol process flag is updated to “0”.

  The pre-opening process for the special winning opening in step S274 is executed when the value of the special symbol process flag is “4”. In the pre-opening process for the big winning opening, setting of the longest opening period of the big winning opening in each round in which the big winning opening is opened by the opening / closing plate provided in the special variable winning ball apparatus 7 in the big hit gaming state is performed. Thereafter, a setting for transmitting a big hit start command to the effect control board 12 is performed, and the value of the special symbol process flag is updated to “5”.

  The special winning opening opening process in step S275 is executed when the value of the special symbol process flag is “5”. In this special prize opening opening process, the solenoid 82 is driven and controlled according to the setting in the special prize opening pre-processing, thereby opening and closing the special prize opening by the opening / closing plate of the special variable winning ball apparatus 7. When the final round in the big hit gaming state is completed, the value of the special symbol process flag is updated to “6”. The jackpot end process in step S276 is executed when the value of the special symbol process flag is “6”. In this jackpot end process, after setting for transmitting a jackpot end command to the effect control board 12, the value of the special symbol process flag is updated to “0”. In the big hit end process, it is determined whether or not the probability change confirmation flag is on. When the probability change confirmation flag is on, the probability change confirmation flag is cleared and turned off, and the game control flag setting unit 133 is provided. Set the probable change flag to ON.

  Next, the operation in the effect control board 12 will be described. In the effect control board 12, when the power supply from the power supply board 10 is started and the reset signal to the effect control microcomputer 120 becomes high level (off state), the effect control microcomputer 120 is activated. The effect control main process as shown in the flowchart of FIG. 44 is executed. Note that each process described below is executed by the CPU 123 provided in the effect control microcomputer 120. Further, the concept including the CPU 123 provided in the production control microcomputer 120 and various circuits other than the CPU 123 may be referred to as the production control microcomputer 120. When the effect control main process shown in FIG. 44 is started, in the effect control microcomputer 120, first, the CPU 123 clears the RAM 122, sets various initial values, initializes a timer for determining the execution interval of effect control, and the like. An initialization process is executed (step S501). Thereafter, the CPU 123 determines whether or not a timer interrupt has occurred, for example, by monitoring a timer interrupt flag (step S502). Until a timer interrupt occurs (step S502; No), the process enters a loop process that repeatedly executes the process of step S502. When a timer interrupt occurs (step S502; Yes), after clearing the timer interrupt flag to turn it off (step S503), the following effect control process is executed.

  Here, the timer interruption in the production control microcomputer 120 occurs, for example, every 2 milliseconds. That is, the effect control process is executed every 2 milliseconds, for example. In this embodiment, when a predetermined timer interrupt process is executed in response to the occurrence of a timer interrupt, the timer interrupt flag is set to the on state, and the specific effect control process is executed in the effect control main process. Is done. On the other hand, the effect control process may be executed in the timer interrupt process.

  In the effect control process, the effect control microcomputer 120 first executes an effect command analysis process for analyzing the effect control command received by the CPU 123 from the main board 11 via the relay board 18 (step S504). Subsequently, in the effect control microcomputer 120, for example, the CPU 123 executes effect control process processing (step S505). In the effect control process, various processes are selected and executed in accordance with the control state of the image display device 5, the speakers 8L and 8R, the game effect lamp 9, and the like that are electric parts for effects. Thereafter, a random number update process for updating various random numbers counted in the effect control microcomputer 120 is executed (step S506). Further, a notification process for controlling a notification operation based on a notification instruction by a production control command from the main board 11 is executed (step S507).

  In the CPU 123, an interrupt for receiving an effect control command from the main board 11 is generated separately from the timer interrupt that is periodically generated. This interruption is an interruption that occurs when the effect control INT signal from the main board 11 is turned on. When an interruption occurs due to the turn-on of the effect control INT signal, the CPU 123 automatically sets the interrupt prohibited state. However, if the CPU that does not automatically enter the interrupt prohibited state is used, It is preferable to issue an insertion prohibition instruction (DI instruction).

  When the production control INT signal from the main board 11 is turned on, an interruption is generated in the CPU 123, whereby execution of the command reception interruption process shown in the flowchart of FIG. 45 is started. In this command reception interrupt process, the CPU 123 first saves the value of each register in the stack (step S521). Subsequently, for example, an effect control command is read from a predetermined input port that receives a control signal transmitted from the main board 11 and assigned to the input of the effect control command data in the I / O port 124 (step S522). . And it is discriminate | determined whether it is the 1st byte of the production control commands of 2 bytes structure (step S523). Here, the first byte (MODE) and the second byte (EXT) of the effect control command are configured to be immediately distinguishable on the receiving side. In other words, the reception side can immediately detect whether the data as MODE or the data as EXT has been received by the first bit. When the first bit of the received command is “1”, it is determined that the valid first byte (MODE data) of the effect control command having a 2-byte configuration has been received.

  When it is determined in the process of step S523 that the MODE data is the first byte (step S523; Yes), the effect control command reception counter is used in the effect side reception command buffer 231 provided in the effect control buffer setting unit 225. The received command is stored in the designated reception command buffer (step S524). On the other hand, when it is determined in step S523 that it is not the first byte of the effect control command (step S523; No), it is determined whether or not the first byte of MODE data has already been received (step S525). Whether or not the first byte of MODE data has been received can be determined by checking the command data stored in the received command buffer.

  If the first byte has already been received (step S525; Yes), it is determined whether or not the first bit of the one byte received this time is “0” and if the first bit is “0”. For example, assuming that the effective second byte is received, the received command is stored in the next reception command buffer designated by the effect control command reception counter (step S526). When the second byte command data is stored in the process of step S526, the value of the effect control command reception counter is incremented by 2 (step S527), and it is determined whether or not the value is “12” or more (step S528). ). If it is “12” or more (step S528; Yes), the effect control command reception counter is cleared and its value is returned to “0” (step S529).

  After executing the process of step S524 or when the MODE data of the first byte is not received in step S525 (step S525; No), the value of the effect control command reception counter is less than “12” in step S528. If there is (Step S528; No), or after executing the processing of Step S529, the register saved in the processing of Step S521 is restored (Step S530), and interrupt permission is set (Step S531). The effect control command transmitted from the main board 11 is stored in the effect side reception command buffer 231 by such command reception interrupt processing. On the other hand, occurrence of a timer interrupt is confirmed in the process of step S502 shown in FIG.

  FIG. 46 is a flowchart showing an example of the effect control command analysis process executed in step S504 of FIG. In the effect control command analysis processing shown in FIG. 46, the CPU 123 first checks whether the effect control command transmitted from the main board 11 is stored in the effect side reception command buffer 231 or the like, for example. It is determined whether or not there is (step S601). At this time, if there is no received command (step S601; No), the effect control command analysis process is terminated as it is.

  When there is a reception command in step S601 (step S601; Yes), the CPU 123 reads the reception command from the effect side reception command buffer 231 (step S602), and the read reception command is the error notification start # 1 command. It is determined whether or not (step S603). If it is determined that the command is for error notification start # 1 (step S603; Yes), the value of the error notification start flag provided in the effect control flag setting unit 222 is set to “1” (step S603). S604).

  If it is determined in step S603 that the command is not an error notification start # 1 command (step S603; No), whether or not the received command read in step S602 is an error notification start # 2 command. Is determined (step S605). When it is determined that the command is for error notification start # 2 (step S605; Yes), the value of the error notification start flag is set to “2” (step S606).

  If it is determined in step S605 that the command is not an error notification start # 2 command (step S605; No), whether or not the received command read in step S602 is an error notification start # 3 command. Is determined (step S607). If it is determined that the command is an error notification start # 3 command (step S607; Yes), the value of the error notification start flag is set to “3” (step S608). If it is determined in step S607 that the command is not an error notification start # 3 command (step S607; No), the command reception flag corresponding to the received command is set to the on state (step S609). If it is determined in step S607 that the command is not an error notification start # 3 command, it is determined whether or not the command is a variable display start command. A process of storing the variable display pattern indicated by the variable display start command may be executed by storing the data in a predetermined area (for example, a pattern storage area). After any of the processes in steps S604, S606, S608, and S609 is executed, the process returns to step S601.

  FIG. 47 is a flowchart showing an example of the effect control process executed in step S505 of FIG. In the effect control process shown in FIG. 47, in the effect control microcomputer 120, for example, the CPU 123 performs the following steps S620 to S625 in accordance with the value of the effect control process flag provided in the effect control flag setting unit 222. Execute each process.

  The variable display start command reception waiting process in step S620 is executed when the value of the effect control process flag is “0”. In the variable display start command reception waiting process, the effect control microcomputer 120 determines whether, for example, the CPU 123 has received a variable display start command transmitted from the main board 11. At this time, if the variable display start command has not been received, the variable display start command reception waiting process is terminated. When it is determined in the variable display start command reception waiting process that the variable display start command has been received, the value of the effect control process flag is updated to “1”.

  The effect display control setting process in step S621 is executed when the value of the effect control process flag is “1”. This effect display control setting processing corresponds to the fact that the special symbol is variably displayed in the special symbol game by the special symbol display device 4, and the effect by various displays including the variable display of the decorative symbol in the image display device 5. In order to perform the above, processing for setting the display operation of the image display device 5 is included. As a specific example, in the effect display control setting process in step S621, first, it is determined whether or not the variable display pattern designated by the variable display start command from the main board 11 is a big hit pattern, and is not a big hit pattern. Is determined, it is determined whether or not it is a reach loss pattern. When it is determined that the pattern is not the reach loss pattern, it is determined that the normal loss pattern has been designated, and a normal lose symbol determination process for determining a definite decorative symbol for a normal loss combination is executed. Further, when the variable display pattern designated by the variable display start command is a reach lose pattern, a reach lose symbol determination process for determining a definite decorative symbol to be a reach lose combination is executed.

  Further, when the variable display pattern designated by the variable display start command is a big hit pattern, a big hit symbol determination process for determining a confirmed decorative symbol to be a big hit combination is executed. At this time, for example, the CPU 123 reads a display result notification command transmitted from the main board 11 to determine whether the gaming state is a probable big hit that becomes a high probability state or a normal big hit that does not become a high probability state. To do. When it is determined that the probability variation is a big hit, for example, the same probability variation among the decorative symbols “1”, “3”, “5”, “7” or “9” as the probability variation symbol having an odd symbol number. The symbol is determined to be a definite ornament symbol that is derived and displayed on each of the “left”, “middle”, and “right” variable display units as a display result in the variable display of the ornament symbol in the image display device 5. On the other hand, when it is determined that it is a normal big hit, for example, the same normal among the decorative symbols “0”, “2”, “4”, “6” or “8” as a normal symbol having an even symbol number The symbol is determined to be a definite ornament symbol that is derived and displayed on each of the “left”, “middle”, and “right” variable display units as a display result in the variable display of the ornament symbol in the image display device 5.

  After determining the final decorative symbol by executing these processes, in the effect display control setting process, the symbol display control pattern corresponding to the variable display pattern designated by the variable display start command is determined, and the symbol display control pattern is determined. For example, a drawing command corresponding to is sent to the VDP, and settings for starting variable display of decorative symbols are performed. At this time, a timer setting for measuring the variable display time of the decorative symbols is also performed corresponding to the symbol display control pattern. Thereafter, the value of the effect control process flag is updated to “2”, and the effect display control setting process ends.

  The decorative symbol variable display process in step S622 is executed when the value of the effect control process flag is “2”. In this decorative symbol variable display processing, for example, the reading position in the symbol display control pattern is switched in accordance with the elapsed time since the decorative symbol variable display was started, and drawing corresponding to the display control data read from the reading position is performed. The display operation in the image display device 5 is controlled by sending a command to the VDP. Then, when the timing to end the variable display of the decorative symbols is reached, the big hit start command reception waiting time is set and the value of the effect control process flag is updated to “3”.

  The decorative symbol stop process in step S623 is executed when the value of the effect control process flag is “3”. In this decorative symbol stop process, it is determined whether or not the jackpot start command transmitted from the main board 11 has been received. Then, when the big hit start command reception waiting time has elapsed without receiving the big hit start command, it is determined that the decorative symbol variable display result is lost, and the value of the effect control process flag is updated to “0”. Also, when it is determined that the jackpot start command is received in the decorative symbol stop process, it is determined that the variable symbol display result is a big bonus, and the value of the effect control process flag is updated to “4”. To do.

  The big hit effect process in step S624 is executed when the value of the effect control process flag is “4”. In the jackpot effect process, the display operation in the image display device 5 is controlled to perform control to display an image corresponding to the jackpot gaming state. Then, it is determined whether or not a big hit end command has been received from the main board 11, and when it is determined that it has been received, the value of the effect control process flag is updated to “5”.

  The big hit end effect process in step S625 is executed when the value of the effect control process flag is “5”. The jackpot end effect process includes a process of performing control for executing an effect display for notifying that the jackpot game state has ended on the image display device 5. Thereafter, when the various effect displays are completed, the value of the effect control process flag is updated to “0”.

  FIG. 48 is a flowchart showing an example of the notification process executed in step S507 of FIG. In the notification process shown in FIG. 48, the CPU 123 first determines whether or not the value of the error notification start flag provided in the effect control flag setting unit 222 is “1” (step S641). At this time, if the value of the error notification start flag is “1” (step S641; Yes), after updating the value of the error notification start flag to “0” (step S642), for example, as shown in FIG. Settings for starting signal abnormality notification, such as setting for displaying an image to be a signal abnormality notification screen on the image display device 5, are performed (step S643).

  If it is determined in step S641 that the value of the error notification start flag is not “1” (step S641; No), it is determined whether or not the value of the error notification start flag is “2” (step S641). S644). If the value of the error notification start flag is “2” (step S644; Yes), after updating the value of the error notification start flag to “0” (step S645), for example, as shown in FIG. A setting for starting the reach number abnormality notification, such as a setting for causing the image display device 5 to display an image that becomes the reach number abnormality notification screen, is performed (step S646).

  If it is determined in step S644 that the value of the error notification start flag is not “2” (step S644; No), it is determined whether the value of the error notification start flag is “3” (step S644). S647). If the value of the error notification start flag is “3” (step S647; Yes), after updating the value of the error notification start flag to “0” (step S648), for example, as shown in FIG. A setting for starting a normal loss count abnormality notification, such as a setting for displaying on the image display device 5 an image that becomes a normal loss count abnormality notification screen, is performed (step S649).

  Next, the operation in the payout control board 15 will be described. In the payout control board 15, the payout control microcomputer 150 is activated in response to the start of power supply from the power supply board 10 and the reset signal to the payout control microcomputer 150 becoming high level (off state). A payout control main process as shown in the flowchart of FIG. 50 is executed. Each process described below is executed by the CPU 213 provided in the payout control microcomputer 150. An interrupt request based on various interrupt factors generated by the timer circuit 216 and the serial communication circuit 217 provided in the payout control microcomputer 150 is for causing the CPU 213 to execute predetermined interrupt processing. The concept including the CPU 213 and various circuits other than the CPU 213 is sometimes referred to as a payout control microcomputer 150. When the payout control main process shown in FIG. 50 is started, the payout control microcomputer 150 first sets the interrupt prohibition (step S701) and sets the interrupt mode (step S702). Subsequently, settings relating to the stack pointer, such as setting of a stack pointer designation address, are performed (step S703). Also, the built-in device register is set (initialized) (step S704). For example, in the process of step S704, settings (initialization) of built-in devices (built-in peripheral circuits) such as the timer circuit 216 and the input / output port 218 may be performed.

  After executing the process of step S704, it is determined whether or not the power-off signal is in an OFF state by checking the state of a predetermined bit in the input port included in the input / output port 218, for example (step S705). ). For example, in the process of step S705, it is confirmed that the power-off signal is not output and is in an off state (high level).

  When the power cut-off signal is on in step S705 (step S705; No), after waiting for a predetermined time (for example, 0.1 second) to elapse (step S706), the process returns to step S705 to return to the power supply. It is determined again whether or not the disconnection signal is off. Thereby, the payout control microcomputer 150 can confirm that the power supply voltage is stable. If the power-off signal is off in step S705 (step S705; Yes), the RAM 215 is set to be accessible (step S707).

  After executing the processing of step S707, it is determined whether or not the clear signal is in an ON state by checking the state of a predetermined bit in the input port included in the input / output port 218, for example (step S708). . Here, the CPU 213 may confirm the state of the clear signal only once through the input port, but may confirm the state of the clear signal a plurality of times. For example, once it is confirmed that the state of the clear signal is off, the state of the clear signal is confirmed once again after a predetermined time (for example, 0.1 second) has elapsed. At this time, if the clear signal is off, it is determined that the clear signal is off. On the other hand, if the state of the clear signal is on at this time, the state of the clear signal may be confirmed again after a predetermined time has elapsed. Note that the number of times of reconfirming the state of the clear signal may be one time or may be a plurality of times. Further, it is possible to check twice and check again when the check results do not match.

  When it is determined in step S708 that the clear signal is in the OFF state (step S708; No), data check of the RAM 215 is performed to determine whether the check result is normal (step S709). In the process of step S709, for example, a checksum is calculated using data stored in a specific area of the RAM 215, and the calculated checksum is compared with the checksum stored in the payout checksum buffer. Here, the payout checksum buffer stores a checksum calculated by the same processing when the power supply was stopped last time. If the comparison result does not match, the data in the specific area of the RAM 215 is different from the data at the time of stopping the power supply, and therefore it is determined that the check result is not normal.

  When the check result in step S709 is normal (step S709; Yes), for example, it is determined whether or not a payout backup flag provided in a predetermined area of the RAM 215 is turned on (step S710). The state of the payout backup flag is set in a predetermined area of the RAM 215 when the power supply is stopped. Then, the place where the payout backup flag is set is backed up by the backup power source, so that the state of the payout backup flag is saved even when the power supply is stopped. It should be noted that it is determined whether or not the payout backup flag is turned on as in step S710 before the check result is determined as in step S709. When the payout backup flag is on, the data check of the RAM 215 is performed. You may make it determine whether a result is normal.

  If the payout backup flag is on in step S710 (step S710; Yes), the payout backup flag is cleared and turned off (step S711), and then the internal state of the payout control microcomputer 150 is supplied with power. The setting at the time of restoration for returning to the state when it was stopped is performed (step S712).

  Further, when the clear signal is on in step S708 (step S708; Yes), when the check result is not normal in step S709 (step S709; No), or the payout backup flag is off in step S710. If there is (step S710; No), the RAM 215 is initialized (step S713). Subsequently, setting at the time of initialization is performed to set the internal state of the payout control microcomputer 150 to an initial state (step S714). For example, in the process of step S714, initial values may be set in various flags, various timers, various counters, and the like provided in a predetermined area of the RAM 215.

  After executing the processing of step S712 or step S714, for example, by setting a register of the timer circuit 216 provided in the payout control microcomputer 150, a timer interrupt is generated every predetermined time (for example, 2 milliseconds). The internal setting of the payout control microcomputer 150 is performed (step S715).

  Thereafter, the CPU 213 executes serial communication initial setting processing for initial setting of serial communication operation by the serial communication circuit 217 (step S716). The serial communication initial setting process may be the same process as the process of step S23 shown in FIG. 27 executed by the game control microcomputer 100 on the main board 11 side. In addition, the CPU 213 executes an interrupt initial setting process for performing an initial setting related to the interrupt process executed based on the interrupt request (step S717). This interrupt initial setting process may be a process similar to the process of step S24 shown in FIG. 27 executed by the game control microcomputer 100 on the main board 11 side. Then, the CPU 213 sets the interrupt permitted state (step S718), and waits for occurrence of various interrupts. At this time, it is determined whether or not the power-off signal has been turned on (whether or not it has been output) (step S719). If it is off (step S719; No), the generation of various interrupts is awaited. When the power-off signal is turned on (step S719; Yes), the payout-side power cut-off process is executed (step S720), and then a predetermined loop process is executed for the payout control by stopping the power supply. Wait until the microcomputer 150 stops operating. In the process of step S719, the state of the power-off signal may be confirmed only once via the input port, but the state of the power-off signal may be confirmed a plurality of times. For example, if it is confirmed once that the power-off signal is in the OFF state, the power-off signal is confirmed once again after a predetermined time (for example, 0.1 second) has elapsed. At this time, if the power-off signal is off, it is determined that the power-off signal is off. On the other hand, if the state of the power-off signal is on at this time, the state of the power-off signal may be confirmed again after a predetermined time has elapsed. In addition, the number of times of reconfirming the state of the power-off signal may be one time or a plurality of times. Further, it is possible to check twice and check again when the check results do not match. Thus, when confirming the state of the power-off signal multiple times, for example, when the confirmation operation is started or when the first confirmation result is compared with the second confirmation result and there is a mismatch, etc. Retriggering is performed to clear the WDT (watchdog timer) built in the control microcomputer 150. When the retrigger does not occur within a predetermined time for some reason (for example, program runaway), a user reset is generated based on a timeout signal output from the WDT, and the reset / interrupt controller 212, CPU 213, timer circuit After initializing each circuit such as 216 and the serial communication circuit 217, execution of the user program may be started from an address indicated by a predetermined vector table to perform automatic recovery.

  In the payout-side power cut-off process in step S720, for example, after the CPU 213 sets the interruption prohibited, the operation of the payout motor 51 is stopped by setting clear data to a predetermined bit of the output port included in the input / output port 218. Make settings for At this time, clear data may be set for an output port to be cleared in addition to a predetermined bit of the output port. Subsequently, check data is created by, for example, calculating a checksum using data stored in a specific area of the RAM 215, and a payout backup flag provided in a predetermined area of the RAM 215 is set to an on state. The check data created at this time is stored, for example, in a payout checksum buffer provided in a predetermined area of the RAM 215 or the like. The payout control microcomputer 150 then prohibits access to the RAM 215, for example, by setting an access prohibition value in a predetermined RAM access register.

  In the payout control microcomputer 150, the interrupt processing executed by the game control microcomputer 100 mounted on the main board 11 is adapted to the payout control microcomputer 150 in response to the interrupt factor generated in the serial communication circuit 217. The serial communication error interrupt process thus performed may be executed. For example, every time an error interrupt occurs in the serial communication circuit 217 provided in the payout control microcomputer 150, a process in which the process shown in FIG. 32 is adapted to the payout control microcomputer 150 may be executed. In this processing, for example, the transmission operation unit provided in the serial communication circuit 217 provided in the payout control microcomputer 150 is set to an unused state, and the reception operation unit provided in the serial communication circuit 217 is set to an unused state. To do. Thereafter, in the payout control microcomputer 150, for example, the CPU 213 may perform processing such as setting a predetermined flag such as a serial communication error flag to an on state.

  Further, every time a reception interrupt is generated in the serial communication circuit 217 included in the payout control microcomputer 150, a serial reception interrupt process in which the process shown in FIG. 33 is adapted to the payout control microcomputer 150 is executed, and the payout control is performed. Each time a transmission interrupt is generated in the serial communication circuit 217 included in the microcomputer for use 150, a serial transmission interrupt process in which the process shown in FIG. 34 is adapted to the payout control microcomputer 150 may be executed.

  FIG. 51 is a flowchart showing an example of a payout control timer interrupt process executed each time a timer interrupt occurs in the payout control microcomputer 150. This payout control timer interruption process is a process that becomes a payout control process for controlling the payout motor 51 in accordance with the payout control command transmitted from the main board 11. In the payout control timer interrupt process shown in FIG. 51, in the payout control microcomputer 150, first, the CPU 213 executes a predetermined input / output process (step S731), for example, a predetermined input port included in the input / output port 218. The state of the bit is checked, or predetermined control data is set for a predetermined bit at the output port.

  Subsequently, the CPU 213 executes a prepaid card unit process to perform communication with the card unit 70 connected via the interface board 20 (step S732). Further, a payout side reception process for receiving a payout control command transmitted from the main board 11 by serial communication is executed (step S733). Then, a prize ball reception confirmation process is performed for performing a setting for transmitting a prize ball ACK command when a payout number designation command from the main board 11 is received (step S734). Further, in accordance with a ball lending request from the card unit 70 and a payout number designation command from the main board 11, a payout operation control process for controlling the payout operation of the game ball is executed (step S735).

  Subsequent to the processing in step S735, the CPU 213 executes a 7-segment display process for performing a predetermined display on the error display LED 74 in accordance with the states of various error flags provided in a predetermined area of the RAM 215, for example (step S736). ). Further, a payout side transmission process for transmitting a payout notification command to the main board 11 is executed (step S737). Thereafter, the CPU 213 executes a payout-side error canceling process to enable a predetermined error to be canceled when the detection signal from the error canceling switch 73 is turned on (step S738). The process ends.

  As described above, in the pachinko gaming machine 1 in the above embodiment, when power supply is started, the random number initial determination process is executed in step S21 shown in FIG. Setting for generating a random number to be a random number R1 for use. Thereafter, the game control microcomputer 100 is set to an interrupt-permitted state, for example, by the CPU 103 executing the process of step S24. In step S21, for example, the process shown in FIG. 29 is executed as the random number initial setting process, and the fourth bit [bit 4] of the random number initial setting data (KRSS) stored in the ROM 104 in step S103 is obtained. If the read value is “1”, the start value of the first round in the random value generated by the random number circuit 112 by executing the process of step S106 is given to each game control microcomputer 100. It is determined based on an ID number which is unique identification information. As a result, the initial value of the random number that is updated after the power supply is started can be made different for each of the plurality of pachinko gaming machines 1, and the random value generated in this way can be used for the jackpot determination disturbance. By using the numerical value R1 to determine whether or not the variable display result in the special symbol game or the like by the special symbol display device 4 is “big hit”, the randomness of the random number is increased and illegal big hits are generated. Can be prevented.

  Further, the CPU 103 provided in the game control microcomputer 100 reads the stored value that becomes the random value R1 for jackpot determination from the random value register 176 of the random number circuit 112 in step S302 of FIG. The reach determination random number value R4 corresponding to is set in the reach determination random number counter in step S305. Accordingly, the reach determination random number value R4 stored in the reach determination random number counter is updated in synchronization with the jackpot determination random number value R1 read from the random value register 176 of the random number circuit 112. The reach determination random number value R4 set in the reach determination random number counter is read by the CPU 103 in step S334 of FIG. 43 and used to determine whether or not to reach in step S335. . Therefore, when an abnormality occurs in the random number generation operation in the random number circuit 112 and the random number value R1 is not updated, the reach determination random number value R4 is not updated, and the image display device 5 performs a plurality of decorations. In the variable display of symbols, the variable display mode is continuously reached, or the display results in normal loss without reaching reach for a long period of time.

  With such a variable display mode of the decorative pattern, the player can estimate whether or not an abnormality has occurred in the random number generation operation in the random number circuit 112 and can prevent a significant disadvantage from being caused when the abnormality occurs. . In general, the probability that the decorative display variable display mode will reach is set to be higher than the probability that the variable display result will be a big hit, so the variable display result will not be a big hit for a long period of time. The occurrence of abnormality can be estimated in a shorter period than when it is estimated that an abnormality has occurred in the random number generation operation 112.

  The CPU 103 included in the game control microcomputer 100 uses the first and second monitoring counters provided in the game control counter setting unit 135 to use the clock signal S1 supplied from the clock signal output circuit 171 included in the random number circuit 112. Is checked every time a timer interrupt occurs. Here, the clock signal output circuit 171 is supplied from the reference clock signal generation circuit 111 if the value of the fifth bit [bit 5] of the random number initial setting data (KRSS) stored in the ROM 104 is “1”. By dividing the reference clock signal CLK as the internal system clock by 16, the update cycle of the random number generated by the random number circuit 112 is set to 16 times the internal system clock. Then, when a change in the level of the clock signal S1 input from the clock signal output circuit 171 is not detected for a predetermined period or more, an abnormality occurs in the clock signal output circuit 171 provided in the reference clock signal generation circuit 111 or the random number circuit 112. Can be determined.

  When it is determined in step S226 in FIG. 37 that the timer value in either the first or second monitoring timer has reached the signal monitoring upper limit value, the CPU 103 executes the process in step S227. An error notification start # 1 command is transmitted to the effect control board 12. If it is determined in step S335 in FIG. 43 that the reach determination random number R4 matches the reach determination value data and the reach is determined to be reach, the CPU 103 sets the count value in the reach count counter in step S338. On the other hand, if it is determined that the reach determination random number value R4 does not match the reach determination value data and the reach determination value data is not reached, 1 is added to the count value in the normal loss count counter in step S341. When it is determined in step S230 in FIG. 37 that the count value in the reach counter exceeds the reach continuous upper limit value, an error notification is given to the effect control board 12 by executing the process in step S231. Send start # 2 command. In addition, when it is determined in step S232 in FIG. 37 that the count value in the normal loss count counter exceeds the normal loss continuous upper limit value, the processing in step S233 is performed to the effect control board 12. The error notification start # 3 command is transmitted.

  On the side of the production control board 12, the CPU 123 provided in the production control microcomputer 120 determines that it has received the error notification start # 1 command in step S603 of FIG. 46, and thus starts error notification in step S604. Set the flag value to "1". Then, in response to setting the value of the error notification start flag to “1”, an image that becomes a signal abnormality notification screen as illustrated in FIG. 49A in step S643 of FIG. 48 is displayed on the image display device 5. The signal abnormality notification is started by performing the setting to be displayed on the screen. Further, the CPU 123 determines that the error notification start # 2 command has been received in step S605 of FIG. 46, and sets the value of the error notification start flag to “2” in step S606. Then, in response to setting the value of the error notification start flag to “2”, in step S646 in FIG. 48, an image that becomes a reach number abnormality notification screen as illustrated in FIG. 49B is displayed on the image display device. 5 is started, the reach number abnormality notification is started. Further, the CPU 123 determines that the error notification start # 3 command has been received in step S607 of FIG. 46, and sets the value of the error notification start flag to “3” in step S608. Then, in response to setting the value of the error notification start flag to “3”, an image that becomes a normal loss count abnormality notification screen as illustrated in FIG. 49C in step S649 of FIG. 48 is displayed as an image. By performing the setting to be displayed on the device 5, the normal notification of the number of times of losing is started. As described above, when an occurrence of abnormality in the random number generation operation in the random number circuit 112 is detected, an effect is generated to notify the random number circuit 112 that an abnormality has occurred. It can be easily recognized outside the pachinko gaming machine 1, and it is possible to prevent the player from continuing the game in a state where an abnormality has occurred in the random number circuit 112.

  When one of the processes of steps S227, S231, and S233 shown in FIG. 37 is executed, the CPU 123 controls the progress of the game by the CPU 103 by shifting to the HALT (stopped) state by executing the process of step S229. Execution of the process to be stopped is stopped. Thereby, when abnormality occurs in the random number generation operation in the random number circuit 112, the progress of the game in the pachinko gaming machine 1 can be stopped.

  When the highest priority interrupt setting (KHPR) stored in the ROM 104 is a value other than “06h” and “07h”, an interrupt process based on an error interrupt request from the serial communication circuit 107 is received from the serial communication circuit 107. It is executed with priority over interrupt processing based on interrupt requests and transmission interrupt requests. When the CPU 103 is notified of an error interrupt request corresponding to the occurrence of an error in the serial communication circuit 107 such as an overrun error, noise error, framing error, or parity error, the CPU 103, for example, performs steps S41 and S42 shown in FIG. By executing the above process and setting the transmission operation unit 202 and the reception operation unit 201 included in the serial communication circuit 107 to the unused state, the serial communication operation in the serial communication circuit 107 can be immediately stopped. Thereby, it is possible to prevent erroneous information from being transmitted due to the occurrence of an abnormality in serial communication.

  For determining whether or not the display result in the special display game or the variable display of the decorative design is “big hit”, the random value R1 for determining the big hit generated by the random number circuit 112 is used. On the other hand, the determination as to whether or not to set the high probability state is, for example, for the probability variation determination that is updated by the CPU 103 executing the software random number update process as shown in FIG. 38 in step S75 shown in FIG. A random value R2 is used. In this way, by using random values with different update methods for jackpot determination and probability variation determination, the occurrence of periodicity in these two determinations is prevented, and randomness between the determination results is increased. Can be increased. Further, if it is determined in step S245 that the random number count value for probability variation determination matches the initial value in the random value R2 for probability variation determination based on the comparison result in step S244 shown in FIG. 38, the process proceeds to step S246. The initial value in the random value R2 for probability variation determination is changed using the initial value determining random value R3 read from the initial value determining random number counter. In this way, by changing the initial value every time the update of the random number value R2 for the probability variation determination is completed, the randomness in determining whether or not a high probability state is to be achieved can be improved.

  Note that the random number value R4 for reach determination is updated in synchronization with the random value R1 for jackpot determination, even if the random number value R1 for jackpot determination itself is used as the random value R4 for reach determination. Good. In this case, as shown in FIG. 52, the reach determination table 142 is configured by setting data that associates the random value R1 for jackpot determination with either the reach determination value data or the normal lose determination value data. In step S305 in FIG. 40, the stored value itself read from the random value register 176 included in the random number circuit 112 in step S302 may be set in the reach determination random number counter as the reach determination random value R4.

  The numerical data that is updated in synchronization with the random number R1 for jackpot determination is not limited to the random value R4 for reach determination. For example, the determination-use randomness used for determining the effect mode in the notification effect. The random display pattern determination random number value used for determining the variable display pattern that determines the numerical value and the variable display mode of the decorative design may be updated in synchronization with the random number R1 for jackpot determination. . In this case, similarly to the reach determination random number value R4 in the above embodiment, for example, in step S305 of FIG. 40A, a table for associating the big hit determination random number value R1 with each random number value is created. It may be updated to a random value corresponding to the random number R1 for jackpot determination read out from the random number circuit 112 by referring to it. Further, the random number R1 for jackpot determination may be used as various random values. For example, when the random number value for determining the notice is updated in synchronization with the random value R1 for determining the big hit, the random number generation operation in the random number circuit 112 is abnormal and the random value R1 is updated. When there is not, the random number value for determining the notice will not be updated. Therefore, in the special display game and the variable display of the decorative symbols, the notice effect having the same effect mode is continuously executed or long. The notice effect will not be executed over the period. With such a notice effect execution mode, the player can estimate whether or not an abnormality has occurred in the random number generation operation in the random number circuit 112, and can be prevented from suffering a significant disadvantage when the abnormality occurs. .

  In the embodiment described above, the random number value R4 for reach determination is updated in synchronization with the random number value R1 for jackpot determination read out from the random number value register 176 of the random number circuit 112. It is possible to estimate the occurrence of abnormality in the random number generation operation in the random number circuit 112 when the variable display mode of the pattern is continuously reached or the display result is normal loss without reaching for a long time. It was. On the other hand, the game control microcomputer 100 holds the jackpot determination random number value R1 read from the random number circuit 112 by the CPU 103, and the random number value R1 read from the random number circuit 112 for the predetermined number of times is the same value. The occurrence of abnormality in the random number generation operation in the random number circuit 112 may be estimated. Hereinafter, an example of the pachinko gaming machine 1 that can estimate the occurrence of abnormality in the random number generation operation in the random number circuit 112 by holding the random number value R1 read from the random number circuit 112 will be described.

  In this embodiment, for example, a big hit determination random value holding unit 137 as shown in FIG. 53 is provided in the game control data holding area 130. In the jackpot determination random value holding unit 137, the jackpot determination random number value R1 read from the random number circuit 112 is set and held. The game control counter setting unit 135 is provided with a coincidence counter. The coincidence number counter is for counting the number of times that the random number value R1 held in the jackpot determination random number value holding unit 137 and the random number value R1 read out from the random number circuit 112 are continuously matched.

  FIG. 54 is a flowchart showing an example of processing executed in step S262 of FIG. 39 as the winning process in this embodiment. The processing in steps S301 to S304 shown in FIG. 54 is the same as the processing in steps S301 to S304 shown in FIG. In the winning process shown in FIG. 54, after executing the process of step S304, the random value R1 held in the jackpot determination random value holding unit 137 is read from the random number value register 176 read from the random number circuit 112 in step S302. It is determined whether or not it matches the stored value (step S361).

  If the random value R1 held in step S361 is different from the read value in step S302 (step S361; No), the coincidence counter is cleared and the count value is set to “0” (step S362). In step S302, the random number value R1 read from the random number circuit 112 is set and held in the jackpot determination random value holding unit 137 (step S363).

  If the random value R1 held in step S361 matches the read value in step S302 (step S361; Yes), the count value in the coincidence counter is incremented by 1 (step S364). Then, it is determined whether or not the count value in the coincidence counter incremented by 1 in step S364 matches a predetermined value (for example, “10”) predetermined as the coincidence upper limit (step S365). At this time, if the count value in the match count counter is less than the match count upper limit (step S365; No), the winning process is terminated.

  On the other hand, if the count value in the coincidence counter reaches the coincidence number upper limit value in step S365 (step S365; Yes), it is determined that an abnormality has occurred in the random number generation operation in the random number circuit 112, Settings are made to transmit an error notification start # 4 command to the effect control board 12 (step S366). After executing the process of step S366, a predetermined initialization process is executed (step S367), and a transition to the HALT (stop) state is made (step S368). Execution of the process for controlling is stopped. Note that after executing the process of step S366, only the initialization process may be performed to end the winning process, or only the transition to the HALT state may be performed, and then each unit may be initialized by a user reset or the like. It may be made to be.

  On the side of the effect control board 12, the CPU 123 executes the effect control command analysis process executed in step S <b> 504 shown in FIG. 44, thereby receiving the error notification start # 4 command transmitted from the main board 11. Is determined, for example, the value of the error notification start flag is set to “4”. Then, in response to setting the value of the error notification start flag to “4”, a predetermined error notification is performed by setting the image display device 5 to display an image serving as an error notification screen prepared in advance. To start.

  As described above, according to this embodiment, each time the random number value R1 is read from the random number circuit 112 in step S302 of FIG. 54, the read random number value and the jackpot determination random value holding unit 137 In step S361, it is determined whether or not the stored random number value matches. When it is determined that they do not match, the random number value R1 read from the random number circuit 112 is set and held in the jackpot determination random value holding unit 137, while it is determined that they match, the match number counter By adding 1 to the count value, the number of times that the determination of matching is continuously made is counted. In step S365, it is determined that the occurrence of abnormality in the random number generation operation in the random number circuit 112 has been detected by determining that the count value in the match number counter has reached the match number upper limit value.

  Further, the CPU 103 causes the effect control board 12 to transmit an error notification start # 4 command by executing the process of step S366, and on the effect control board 12 side, the error notification start transmitted from the main board 11 is started. In response to receiving the command # 4, a predetermined error notification is started. In this way, by performing an effect to notify that an abnormality has occurred in the random number circuit 112, the occurrence of the abnormality in the random number circuit 112 can be easily recognized outside the pachinko gaming machine 1, and the player can It is possible to prevent the game from being continued in a state where an abnormality has occurred in the random number circuit 112.

  Note that it may be determined that the occurrence of an abnormality in the random number circuit 112 has been detected when a predetermined period has elapsed without updating the random number value held in the jackpot determination random value holding unit 137. In this case, for example, an elapsed time timer for measuring an elapsed time after the random number value R1 read from the random number circuit 112 is set in the jackpot determination random value holding unit 137 is provided. 54, when the random number value R1 is read from the random number value register 176 of the random number circuit 112 in step S302 in FIG. 54, whether or not the read random number value matches the stored random number value in the same manner as in step S361. If it is determined that they do not match, the read random number value is set in the jackpot determination random value holding unit 137 and measurement of the elapsed time by the elapsed time timer is started.

  On the other hand, when it is determined that the random number value read from the random number circuit 112 matches the random number value stored in the jackpot determination random value holding unit 137, the elapsed time measured by the elapsed time timer is determined to be abnormal. It is determined whether or not the occurrence detection time has been reached. Then, when it is determined that the abnormality occurrence detection time has been reached, it may be determined that an abnormality has been detected in the random number circuit 112. Note that when the player finishes the game in the pachinko gaming machine 1, the measurement of the elapsed time by the elapsed time timer may be ended. For example, whether or not the operation knob 30 provided in the pachinko gaming machine 1 is operated is detected by a touch sensor or the like, and when the operation is not performed, the elapsed time timer is cleared and the elapsed time measurement is ended. That's fine. As a result, since the game in the pachinko gaming machine 1 is not performed, the random number value R1 is not read from the random number circuit 112, and accordingly, the random number value held in the jackpot determination random value holding unit 137 is also updated. Therefore, it is possible to prevent the elapsed time measured by the elapsed time timer from reaching the abnormality occurrence detection time and erroneously detecting that a failure has occurred in the random number circuit 112.

  In the above embodiment, the pachinko gaming machine 1 has been described as having one start winning opening provided in the normally variable winning ball apparatus 6, but the present invention is not limited to this, and a plurality of game areas are provided in the gaming area. The start winning opening may be provided. In this case, a plurality of start port switches may be installed in accordance with the number of start winning ports so that the game balls won in each start winning port can be detected. In the random number circuit 112, a plurality of initial value setting circuits, random number generating circuits, timer circuits, latch signal generating circuits, and random number value registers are provided in accordance with the number of starting winning ports, and a plurality of game balls are provided in the starting winning ports. The random number R1 for jackpot determination read based on winning at the same time may be made different according to the winning at each start winning opening.

  FIG. 55 is a block diagram showing a configuration example of the random number circuit 112 in the case where two left and right start winning ports are provided in the game area as an example when a plurality of start winning ports are provided in the game area of the pachinko gaming machine 1. FIG. In this case, a left start port switch 22A and a right start port switch 22B are provided corresponding to the two left and right start winning ports. The left start port switch 22A outputs a start winning signal SSA that is turned on when a game ball won in the left start winning port is detected. The right start port switch 22B outputs a start winning signal SSB that is turned on when a game ball won in the right start winning port is detected. Also, the random number circuit 112 shown in FIG. 55 corresponds to the left start winning opening, and an initial value setting circuit 172A, a random number generation circuit 173A, a timer circuit 174A, a latch signal generation circuit 175A, and a random value register 176A. And. In addition, the random number circuit 112 shown in FIG. 55 corresponds to the right start winning opening, the initial value setting circuit 172B, the random number generation circuit 173B, the timer circuit 174B, the latch signal generation circuit 175B, and the random value register. 176B.

  In such a configuration, the initial value setting circuits 172A and 172B are independently in the first round when the random number circuit 112 starts generating random numbers after the power supply to the pachinko gaming machine 1 is started. Set the initial value. The initial value setting circuit 172A sets a new initial value when the random number generation circuit 173A cyclically updates the numerical data from a predetermined initial value to a predetermined final value. On the other hand, the initial value setting circuit 172B sets a new initial value when the random number generation circuit 173B cyclically updates the numerical data from a predetermined initial value to a predetermined final value. The initial value setting circuit 172A outputs an initial value setting signal SKA indicating the set initial value and inputs it to the random number generation circuit 173A, while the initial value setting circuit 172B outputs an initial value setting signal SKB indicating the set initial value. To be input to the random number generation circuit 173B.

  The random number generation circuits 173A and 173B, for example in response to the rising edge of the clock signal S1 supplied from the clock signal output circuit 171 and the like, output count values CA and CB that are output independently from each other from a predetermined initial value. Are updated cyclically according to a predetermined order up to the final value. The timer circuit 174A measures the time during which the on-time start winning signal SSA is input from the left start port switch 22A, and generates a latch signal when the measured time reaches a predetermined time (for example, 3 milliseconds). The output signal for the circuit 175A is turned on. The timer circuit 174B measures the time during which the ON start winning signal SSB is input from the right start port switch 22B, and generates a latch signal when the measured time reaches a predetermined time (for example, 3 milliseconds). The output signal for the circuit 175B is turned on.

  The latch signal generation circuit 175A generates the latch signal SLA by outputting the input signal from the timer circuit 174A in synchronization with the rising edge of the clock signal S2 output from the clock signal output circuit 171, and generates a random value register. Input to 176A. The latch signal generation circuit 175B generates the latch signal SLB by outputting the input signal from the timer circuit 174B in synchronization with the rising edge of the clock signal S2 output from the clock signal output circuit 171, and generates a random value register 176B is input.

  The random value register 176A latches the count value CA input from the random number generation circuit 173A in response to the rising edge of the latch signal SLA input from the latch signal generation circuit 175A, and stores it as a random number R1 for jackpot determination. To do. The random value register 176A is in a non-readable state (disabled) when the output control signal SCA from the game control microcomputer 100 is in an off state, and is readable when the output control signal SCA is in an on state. A random number output signal SOA indicating a valid random number value is output in the (enabled) state. The random value register 176B latches the count value CB input from the random number generation circuit 173B in response to the rising edge of the latch signal SLB input from the latch signal generation circuit 175B, and stores it as a random number value R1 for jackpot determination. To do. Random value register 176B is in a non-readable (disabled) state when output control signal SCB from gaming control microcomputer 100 is off, and is readable when output control signal SCB is on. A random value output signal SOB indicating a valid random number value is output in the (enable) state.

  Also in this case, the clock signal S1 output from the clock signal output circuit 171 is input to the first bit [bit 1] of the input port # 0 included in the input / output port 108 included in the game control microcomputer 100, and the clock What is necessary is just to monitor the change of the level of signal S1. With such a configuration, even when game balls win at the same time at the left and right start winning openings, the count values CA and CB are independently stored in the random value registers 176A and 176B, respectively. The random number values (count values CA and CB) stored in the random value registers 176A and 176B at the same time are among a plurality of types of winning processes that are executed in one game control timer interrupt process. It may be read out by executing the corresponding winning process and stored in the special figure storage unit 131. As a result, the CPU 103 can read out the jackpot determination random number value R1 based on the fact that a game ball has won at a plurality of start winning holes at the same time from the random number circuit 112 without shifting the timing, which is inconvenient for the player. There is no impartiality. Even in such a configuration, since the common clock signal generation circuit 111 and the clock signal output circuit 171 in the random number circuit 112 can be used, an increase in manufacturing cost can be suppressed.

  In addition, the present invention is not limited to the above embodiment, and various modifications and applications are possible. For example, in the above embodiment, the detection signal output from the start port switch 22 is input to the timer circuit 174 provided in the random number circuit 112 as the start winning signal SS1. Then, the timer circuit 174 measures the time during which the start winning signal SS1 is input, and when the measured time reaches a predetermined time (for example, 3 milliseconds), the start winning signal SS1 is latched to the latch signal generation circuit 175. Was output. However, the present invention is not limited to this, and a detection signal from the start port switch 22 is input to the CPU 103 provided in the game control microcomputer 100, and the CPU 103 performs a game control timer for a predetermined number of times (for example, twice). When it is determined that the detection signal from the start port switch 22 is continuously on for a period (for example, 4 milliseconds) for executing the interrupt process, the latch start prize signal SN is generated as a latch signal for the random number circuit 112. It may be sent to the circuit 175. In this case, the timer circuit 174 provided in the random number circuit 112 as shown in FIG. 8 is not necessary. For example, a latch start prize output from the CPU 103 is supplied to the D input terminal of the D-type flip-flop circuit provided in the latch signal generation circuit 175. The signal SN is input. The clock signal S2 output from the clock signal output circuit 171 may be input to the clock terminal included in the latch signal generation circuit 175. The latch signal generation circuit 175 generates the latch signal SL by outputting the latch start winning signal SN input to the D input terminal in synchronization with the rising edge of the clock signal S2 input to the clock terminal. Output.

  Also, in this case, the switch-on determination value used in the determination process of step S203 shown in FIG. 36 is used as the latch start winning signal SN for the on state after the detection signal from the start port switch 22 is turned on. When the detection signal from the start port switch 22 is in an on state for a time longer than the period required for sending to the latch signal generation circuit 175, it is determined that the start winning signal from the start port switch 22 is in the on state. It is sufficient to set so as to be a determination value. As a specific example, when the detection signal from the start port switch 22 is continuously on for 4 milliseconds, which is a period for executing two game control timer interrupt processes, the start winning for the latch in the on state is performed. When the signal SN is sent to the latch signal generation circuit 175, the switch-on determination value to be compared with the timer value in the start-up switch timer in step S203 is set in advance to a value larger than “2” (eg, “3”). It is decided. If the timer value in the start port switch timer has reached the switch-on determination value in step S203, it is determined that the start winning signal is in the on state, and the start winning flag is set in the on state in step S204. . Thus, the special symbol display is performed when the detection signal from the start port switch 22 is continuously on until the number of times of execution of the game control timer interrupt process reaches a predetermined number corresponding to the switch-on determination value. It is determined that the execution condition of the special figure game by the device 4 is established. On the other hand, the start start signal SN for latch is the start port switch 22 for 4 milliseconds, which is shorter than the time until the number of executions of the game control timer interrupt process reaches the predetermined number corresponding to the switch-on determination value. The on-state is set on condition that the detection signal from is continuously on.

  In the above embodiment, when the stored value is read from the random value register 176 included in the random number circuit 112 in step S302 shown in FIG. 40A, the processing for step S305 is executed, thereby the reach determination disturbance. The numerical value R4 has been described as being updated in synchronism with the random number R1 for jackpot determination. However, the present invention is not limited to this. For example, when the jackpot determination random number value R1 is read from the special figure holding storage unit 131 in step S312 shown in FIG. 41, FIG. The reach determination random number value R4 corresponding to the read value may be set by executing the same process as in step S305. In this case, the reach determination randomness set to a value corresponding to the random number R1 for jackpot determination used for determining whether or not the display result in the special figure game or in the variable display of the decorative symbols is the jackpot. Using the numerical value R4, it is determined whether or not the decorative symbol variable display mode is to be reached. Even in this case, when an abnormality occurs in the random number generation operation in the random number circuit 112 and the random number value R1 is not updated, the random number value R4 for reach determination is not updated. In the variable display of the decorative pattern multiple times, the variable display mode is continuously reachable or the display result of normal losing without reaching reach for a long time. Abnormality can be estimated.

  In the above embodiment, the timer circuit 174 included in the random number circuit 112 measures the input time of the start winning signal SS1 using the reference clock signal CLK generated by the reference clock signal generation circuit 111. However, the present invention is not limited to this. Instead, a clock signal obtained by dividing the reference clock signal CLK or a clock signal different from the reference clock signal CLK generated by the reference clock signal generation circuit 111 may be used. For example, the timer circuit 174 may measure the input time of the start winning signal SS1 using the clock signal S1 or the clock signal S2 output from the clock signal output circuit 171. Further, in the above embodiment, the timer circuit 174 is set to 3 milliseconds as the predetermined time, but is not limited to this, and is 4 milliseconds which is the execution time of two game control timer interrupt processes. Any time shorter than a second can be set.

  Furthermore, in the above embodiment, the CPU 103 continues the start winning signal SS1, which is a detection signal from the start port switch 22, over a period (4 milliseconds) in which two game control timer interrupt processes are executed. Based on the ON state, the winning process of step S262 shown in FIG. 39 is executed. However, the present invention is not limited to this, and the number of executions of the above-described game control timer interrupt process is arbitrary. For example, the CPU 103 has a period during which three game control timer interrupt processes are executed ( The winning process may be executed based on the fact that the start winning signal SS1 is continuously on for 6 milliseconds). In this case, the timer circuit 174 provided in the random number circuit 112 may be set to a time shorter than 6 milliseconds, which is the execution time of the three game control timer interruption processes.

  In the embodiment described above, the game control microcomputer 100 includes the serial communication circuit 107, and the payout control microcomputer 150 includes the serial communication circuit 217. The game control microcomputer 100 and the payout control microcomputer It has been described that both computers 150 perform serial communication. However, the present invention is not limited to this, and it is sufficient that at least one of the game control microcomputer 100 and the payout control microcomputer 150 has a configuration for performing serial communication. In the following, one of the game control microcomputer 100 and the payout control microcomputer 150 having a serial communication circuit is referred to as a first microcomputer, and the other microcomputer having no serial communication circuit is referred to as a second microcomputer. A microcomputer. In this case, the second microcomputer may include, for example, a serial-parallel conversion circuit (for example, a shift register) that converts data transmitted from the first microcomputer via a serial communication line into parallel data. Alternatively, the second microcomputer may sample the data transmitted from the first microcomputer at a predetermined period to obtain the data transmitted via the serial communication line.

  Communication data may be transmitted from the second microcomputer to the first microcomputer by parallel communication using a plurality of data communication lines. The first microcomputer may be provided with input ports corresponding to a plurality of data communication lines so as to acquire communication data transmitted by parallel communication. In this case, in the serial communication circuit included in the first microcomputer, only the transmission operation unit may be used, and the reception operation unit may be set to an unused state.

  In the above embodiment, the first bit [bit 1] of the input port # 0 included in the input / output port 108 included in the game control microcomputer 100 has a clock output from the clock signal output circuit 171 of the random number circuit 112. It has been described that the signal S1 is input and the change in the level of the clock signal S1 is monitored. However, the present invention is not limited to this. For example, the clock signal S2 output from the clock signal output circuit 171 is input to the input / output port 108 to monitor the level change of the clock signal S2. Also good. When a clock signal generation circuit for generating the reference clock signal CLK is provided in the random number circuit 112 separately from the reference clock signal generation circuit 111 mounted on the main board 11, the clock signal generation circuit is provided. May be input to the input / output port 108 to monitor a change in the level of the reference clock signal CLK. Further, the clock signals S1, S2 and the reference clock signal CLK are not limited to those directly input to a predetermined input port included in the input / output port 108, and the clock signals S1, S2 and the reference clock signal CLK are input to a predetermined frequency dividing circuit. The frequency-divided signal input to the input port is directly input to a predetermined input port included in the input / output port 108 to monitor the level change of the frequency-divided signal input to the input port. Good. Even in such a configuration, it is possible to prevent the player from being disadvantaged by detecting that an abnormality has occurred in the operation state of the random number circuit 112.

  In the above embodiment, the random number value R4 for reach determination is updated in synchronization with the random number value R1 for jackpot determination read from the random number circuit 112, and the variable display mode of the decorative symbols continuously reaches, or By displaying a normal loss display result without reaching reach for a long period of time, it is possible to estimate the occurrence of an abnormality in the random number circuit 112 and monitor the level change of the clock signal S1 supplied from the clock signal output circuit 171. Thus, it is possible to determine that an abnormality has occurred in the clock signal output circuit 171 provided in the reference clock signal generation circuit 111 or the random number circuit 112 because the change in the level of the clock signal S1 is not detected for a predetermined time or longer. Yes. However, the present invention is not limited to this, and the random number circuit is obtained by the display result of normal loss without the reach of the variable display form of the decorative pattern continuously or reaching for a long period of time. 112, the occurrence of an abnormality can be estimated, and the change in the level of the clock signal S1 supplied from the clock signal output circuit 171 is monitored, and the change in the level of the clock signal S1 is not detected for a predetermined time or more. It suffices that at least one of the configurations that can detect the occurrence of abnormality in the clock signal output circuit 171 provided in the reference clock signal generation circuit 111 or the random number circuit 112 is provided. Furthermore, it has only a configuration for determining that an abnormality has occurred in the random number circuit 112 when the number of times that the variable display mode of the decorative symbols is continuously reached has exceeded the reach continuous upper limit value. Also good. Or, the random number circuit 112 has an abnormality when the number of times that it has been determined that the display result of normal losing exceeds the normal continuous continuation upper limit value without continuously reaching the variable display mode of the decorative pattern. It may be possible to provide only the configuration for determining.

  In the above embodiment, the random number circuit 112 is described as being provided outside the game control microcomputer 100 on the main board 11, but the present invention is not limited to this, and the game is a one-chip microcomputer. A random number circuit 112 may be incorporated in the control microcomputer 100. When the random number circuit 112 is built in the game control microcomputer 100, it becomes possible to secure a board space and to display numerical data indicating a random number value generated by the random number circuit 112 due to the installation of an illegal board or the like. It becomes difficult to rewrite from the outside, and forgery can be prevented.

  In the above embodiment, among the special symbols composed of numbers such as “0” to “9”, the special symbol indicating “7” is the jackpot symbol, and the special symbol indicating other numerical values is the lost symbol. In the above description, it is assumed that whether or not the game state becomes a probable big hit that becomes a high probability state is determined separately from the special symbol. However, the present invention is not limited to this, and the probability variation big hit symbol that is a big hit symbol when the gaming state is a high probability state and the normal big hit when the gaming state does not become a high probability state. The normal big hit symbol which is a big hit symbol may be a different special symbol. For example, a special symbol indicating “3” may be a normal jackpot symbol, and a special symbol indicating “7” may be a probability variation jackpot symbol. In this case, among the commands 90XXh serving as the display result notification command, the command 9001h is a command for notifying that the confirmed special symbol in the special game is a special symbol indicating “3” as a normal jackpot symbol, 9002h may be a command for notifying that the confirmed special symbol in the special symbol game is a special symbol indicating “7” as the probability variation big hit symbol.

  In the above embodiment, when any of the error notification start # 1 to # 4 commands is transmitted from the main board 11 to the effect control board 12, the CPU 123 of the effect control microcomputer 120 sends it to the image display device 5. In the above description, it is assumed that a predetermined image is displayed to notify that an abnormality has occurred in the random number generation operation in the random number circuit 112. However, the present invention is not limited to this, and any notification operation may be performed so that the occurrence of abnormality in the random number circuit 112 can be recognized from the outside of the pachinko gaming machine 1. For example, the CPU 123 of the production control microcomputer 120 responds to the reception of any one of the error notification start # 1 to # 4 transmitted from the main board 11 to the voice control board 13 for error notification. An audio control signal may be transmitted to notify the occurrence of an abnormality in the random number circuit 112 by audio output from the speakers 8L and 8R. Alternatively, the CPU 123 of the production control microcomputer 120 sends a lamp control signal for error notification to the lamp control board 14, and the random number circuit 112 is turned on / off by an error notification lamp included in the game effect lamp 9. The occurrence of an abnormality may be notified. Also, in the processes of steps S227, S231, and S233 shown in FIG. 37 and the process of step S366 shown in FIG. 54, the CPU 103 of the game control microcomputer 100 sends control data to predetermined bits of the output port included in the input / output port. For example, a lamp for notifying that an abnormality has occurred in the random number circuit 112 may be turned on or blinked, or a sound may be output.

  In the above embodiment, in the game control timer interrupt process as shown in the flowchart of FIG. 35, the process as shown in the flowchart of FIG. 37 is executed as the error process of step S73, so that the clock signal output circuit It has been described that the change in the level of the clock signal S1 supplied from 171 is monitored. On the other hand, the clock supplied from the clock signal output circuit 171 included in the random number circuit 112 after the power supply to the pachinko gaming machine 1 is started and before the interruption is permitted by the game control microcomputer 100. The presence or absence of a level change in the signal S1 may be confirmed. As a specific example, the following input signal initial check process is executed after the interrupt initial setting process is executed in step S23 shown in FIG.

  When the input signal initial check process is started, the CPU 103 checks the state of the first bit [bit 1] of the input port # 0 included in the input / output port 108, etc., and the clock supplied from the clock signal output circuit 171 It is determined whether or not the signal S1 is at a high level. At this time, if the clock signal S1 is at a high level, the timer value in the first monitoring timer is incremented by 1 and the second monitoring timer is cleared. On the other hand, if the clock signal S1 is at a low level, the second monitoring timer The timer value is incremented by 1 and the first monitoring timer is cleared. Then, after waiting for a predetermined time (for example, 5 milliseconds), it is determined again whether or not the clock signal S1 is at the high level, and the timer values in the first and second monitoring timers are added according to the determination result or The clearing process is repeatedly executed up to a predetermined number of times (for example, 5 times). Thereafter, it is determined whether one of the timer values in the first and second monitoring timers has reached a predetermined value that is set in advance as the signal monitoring upper limit value, and one of the timer values has reached the signal monitoring upper limit value. For example, it may be determined that an abnormality has occurred in the random number generation operation in the random number circuit 112, and processing similar to steps S227 to S229 shown in FIG. In this way, by confirming the signal input state at the input port before entering the interrupt enabled state, whether or not the operation state of the random number circuit 112 is normal before the game in the pachinko gaming machine 1 is started. Can be confirmed.

  In the above embodiment, the pachinko gaming machine 1 has been described as including one special symbol display device 4 and one image display device 5, but the present invention is not limited to this. For example, it is provided in a game area. A plurality of special symbol display devices and a plurality of image display devices may be provided so as to correspond to each of the plurality of start winning awards. For example, in the case where two left and right starting winning awards are provided, two left and right special symbol display devices and two left and right image displaying devices are provided. The execution condition of the special symbol game by the right special symbol display device may be satisfied when the execution condition of the special symbol game by the symbol display device is established and the game ball is won at the right start winning opening. In this case, when the special symbol game is executed by the left special symbol display device, the decorative symbol is variably displayed on the left image display device, and when the special symbol game is executed by the right special symbol display device, The decorative design may be variably displayed on the image display device. Alternatively, when a plurality of start winning holes are provided in the game area, a single special symbol display device may be left and a plurality of image display devices may be provided. For example, when two left and right start winning awards are provided, two left and right image display devices are provided, and a special symbol display device provides a special figure regardless of which of the two left and right start winning awards a game ball wins. It is assumed that game execution conditions are satisfied. In a special game in which the execution condition is established by winning a game ball at the left start winning opening, the left image display device of the left and right image display devices displays the decorative symbols variably. In the special figure game in which the execution condition is established by winning the game ball at the starting winning opening, the decorative image may be variably displayed on the right image display device.

  The random number updated by the CPU 103 according to the software read from the ROM 104 or the like according to the software is not limited to the random number value R2 for probability variation determination or the random value R3 for initial value determination, and other random numbers for determination and display are also used for the CPU 103. May be updated according to software. For example, a random display value for determining a variable display pattern used to determine a variable display pattern for determining a variable display time in a special figure game, an effect mode during a variable display of a decorative design, or a variable display time than a normal gaming state Random value for determining the short time used to determine whether or not to perform the short time control so as to shorten, the random number value for determining the number of rounds used to determine the number of rounds that can be executed in the big hit gaming state The CPU 103 may update the random number value for the probability variation falling lottery used for performing the lottery of whether or not to drop the high probability state into the normal gaming state according to the software.

  In the above-described embodiment, the gaming machine can execute a variable display start condition (for example, a game ball wins a start winning opening provided in the normal variable winning ball apparatus 6) after a variable display execution condition is satisfied (for example, For example, a variable display device that variably displays a plurality of types of identification information (for example, special symbols) that can each be identified based on the establishment of the previous special symbol game and the end of jackpot gaming state by the special symbol display device 4 For example, a pachinko gaming machine equipped with a special symbol display device 4) that controls to a specific gaming state (for example, a big hit gaming state) advantageous to the player when the display result of variable display becomes a predetermined specific display result. there were.

  However, the present invention is not limited to this, and the gaming machine is disadvantageous for the player due to the detection of the start detection means (for example, the start ball detector) that detects the game medium in the start area provided in the game area. It has a variable winning device (for example, a variable winning ball device) that performs a starting operation (for example, an opening operation) that becomes a first state advantageous to the player from the second state, in a specific area provided in the variable winning device. A specific gaming state (for example, jackpot) that controls the variable winning device to the first state in a specific manner that is more advantageous for the player than the starting operation by detection of a specific detection means (for example, a specific ball detector) that detects the gaming medium It may be a pachinko gaming machine that generates a gaming state.

  In addition, the gaming machine of the present invention is in a state where a right is generated on condition that a game ball is detected by special detection means (for example, a specific ball detection switch or a special region switch) provided in a special region (for example, a special device operation region). During the period in which the right is generated, the game ball is moved by the start detection means (for example, the operation ball detection switch or the start port switch) provided in the start area (for example, the start port in the start winning device or the start winning device). Based on the detection, it is possible to perform control to change the special variable winning device (for example, the big prize opening) from a disadvantageous state (for example, a closed state) to the player (for example, a closed state) for the player (for example, an open state). Possible pachinko machines may be used.

  Furthermore, the gaming machine of the present invention can start a game by setting the number of bets for one game, and one game is completed by displaying a display result on a predetermined variable display device. Further, it may be a slot machine that can generate a predetermined prize according to the display result of the variable display device. Such a slot machine has a start switch that outputs a predetermined start signal to a game control means (for example, a main board) or a random number circuit (for example, a random number circuit) based on the operation of a predetermined start lever by the player. It only has to be provided as a winning signal output means. Further, the slot machine only needs to be provided with a liquid crystal display functioning as a rendering means.

It is a front view of the pachinko gaming machine in the present embodiment. It is a block diagram which shows the various control boards etc. which were mounted in the pachinko game machine. It is a figure which shows the structural example of a power supply board. It is a timing diagram which shows typically the state of a reset signal and a power-off signal. It is explanatory drawing which shows an example of the content of a display control command. It is explanatory drawing which shows the structural example of the command transmitted / received between the main board | substrate and the payout control board. It is a disassembled perspective view which shows the structural example of the payout apparatus in which the payout motor is installed. It is a block diagram which shows one structural example of a random number circuit. It is a block diagram which shows the structural example of the microcomputer for game control. It is explanatory drawing which illustrates the random number value counted by the side of a main board | substrate. It is a figure which shows an example of the address map in the microcomputer for game control. It is a figure which shows an example of the address map in ROM. It is explanatory drawing which shows the example of a setting of the highest priority interrupt. It is explanatory drawing which shows the content of random number initialization data. It is explanatory drawing which shows the content of serial communication initial setting data. It is a figure which shows the structural example of a big hit determination table. It is a figure which shows the structural example of a reach determination table. It is a block diagram which shows the structural example of the data holding area for game control. It is a figure which shows the structural example of the reception command buffer for a payout. It is a figure which shows the structural example of the transmission command buffer for payment. It is a block diagram which shows the structural example of a serial communication circuit. It is a figure which shows the structural example of a serial status register and a serial control register. It is explanatory drawing which shows the bit allocation example of the input port in the microcomputer for game control. It is explanatory drawing which shows the bit allocation example of the output port in the microcomputer for game control. FIG. 38 is a block diagram illustrating a configuration example of an effect control data holding area. It is a figure which shows the structural example of an effect side receiving command buffer. It is a block diagram which shows the structural example of the microcomputer for payout control. It is a flowchart which shows an example of a game control main process. It is a flowchart which shows an example of a random number initialization process. It is explanatory drawing which shows the content of the process performed as a serial communication initial setting process. It is a flowchart which shows an example of an interruption initial setting process. It is a flowchart which shows an example of a serial communication error interruption process. It is a flowchart which shows an example of a serial reception interruption process. It is a flowchart which shows an example of a serial transmission interruption process. It is a flowchart which shows an example of the timer interruption process for game control. It is a flowchart which shows an example of a switch process. It is a flowchart which shows an example of an error process. It is a flowchart which shows an example of a software random number update process. It is a flowchart which shows an example of a special symbol process process. It is a flowchart which shows an example of a winning process. It is a flowchart which shows an example of a special symbol normal process. It is a flowchart which shows an example of big hit probability change determination processing. It is a flowchart which shows an example of a variable display start time process. It is a flowchart which shows an example of production control main processing. It is a flowchart which shows an example of a command reception interruption process. It is a flowchart which shows an example of an effect control command analysis process. It is a flowchart which shows an example of production control process processing. It is a flowchart which shows an example of alerting | reporting process. It is a figure which shows the example of a display operation in an image display apparatus. It is a flowchart which shows an example of payout control main processing. It is a flowchart which shows an example of the timer interruption process for payout control. It is a flowchart which shows the other structural example of a reach determination table. It is a block diagram which shows the other structural example in the data holding area for game control. It is a flowchart which shows an example of the winning process performed in the modification shown in FIG. It is a block diagram which shows the modification of a random number circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Pachinko machine 2 ... Game board 3 ... Gaming machine frame 4 ... Special symbol display device 5 ... Image display device 6 ... Normal variable winning ball device 7 ... Special variable winning ball device 8L, 8R ... Speaker 9 ... Game effect lamp DESCRIPTION OF SYMBOLS 10 ... Power supply board 11 ... Main board 12 ... Production control board 13 ... Sound control board 14 ... Lamp control board 15 ... Discharge control board 17 ... Launch control board 18 ... Relay board 20 ... Interface board 21 ... Gate switch 22 ... Start switch 22A ... Left start port switch 22B ... Right start port switch 23 ... V winning switch 24 ... Count switch 26 ... Full switch 27 ... Ball cut switch 30 ... Control knob 40 ... Normal symbol display 51 ... Discharge motor 61 ... Launch motor 70 … Card unit 71… Dispensing motor position sensor 72… Dispensing count switch 73 ... Error release switch 74 ... Error display LED
81, 82 ... Solenoid 85, 86 ... Hole 87, 88 ... Gear 89 ... Cam 90 ... Ball passage 91-93 ... Case 100 ... Game control microcomputer 101, 211 ... Clock circuit 102, 212 ... Reset / interrupt controller 103, 123, 213 ... CPU
104, 121, 214 ... ROM
105, 122, 215 ... RAM
106, 174, 174A, 174B, 216
... Timer circuits 107, 217 ... Serial communication circuits 108, 218 ... Input / output port 111 ... Reference clock signal generation circuit 112 ... Random number circuits 114, 161 ... Switch circuit 115 ... Solenoid circuit 120 ... Production control microcomputer 124 ... I / O Port 130 ... Game control data holding area 131 ... Special figure holding storage unit 132 ... Confirmed special symbol storage unit 133 ... Game control flag setting unit 134 ... Game control timer setting unit 135 ... Game control counter setting unit 136 ... Game control buffer setting Unit 137 ... Big hit determination random number holding unit 140 ... Normal time big hit determination table 141 ... Probability change big hit determination table 142 ... Reach determination table 150 ... Discharge control microcomputer 171 ... Clock signal output circuits 172, 172A, 172 B ... Initial value setting circuits 173, 173A, 173B ... Random number generation circuits 175, 175A, 175B ... Latch signal generation circuits 176, 176A, 176B ... Random value register 201 ... Reception operation unit 202 ... Transmission operation unit 203 ... Serial communication data register 204 ... serial status register 205 ... serial control register 220 ... presentation control data holding area 221 ... definite decoration symbol storage section 222 ... presentation control flag setting section 223 ... presentation control timer setting section 224 ... presentation control counter setting section 225 ... presentation control Buffer setting unit 231 ... Production side reception command buffer 301 ... Transformer circuit 302 ... DC voltage generation circuit 303 ... Power supply monitoring circuit 304 ... Clear switch

Claims (3)

Based on the fact that the variable display start condition is satisfied after the variable display execution condition is satisfied, a variable display device that variably displays each type of identification information that can be identified is provided, and the display result of the identification information is specified. A gaming machine that is in a specific gaming state that is advantageous to the player after the result,
A game control microcomputer for controlling the progress of the game;
Reference clock signal output means for outputting a reference clock signal of a predetermined period;
A game control board equipped with a random number circuit for generating random numbers,
The random number circuit includes:
Random number generating clock signal generating means for generating a random number generating clock signal based on the reference clock signal from the reference clock signal output means;
Specific display result determination used when determining whether or not the display result in the variable display is the specific display result based on the input of the random number generation clock signal generated by the random number generation clock signal generation means Specific display result determination numerical data updating means for cyclically updating the numerical data for use from a predetermined initial value to a predetermined final value in a predetermined range that can be updated, according to a predetermined order;
Display result determination numerical value storage means for storing the specific display result determination numerical data updated by the specific display result determination numerical data update means,
The game control microcomputer is:
Random number circuit setting means for setting the random number circuit to generate the random number after power supply to the gaming machine is started;
After the setting by the random number circuit setting means, a timer interrupt process execution permitting means for permitting execution of a timer interrupt process that occurs periodically,
Execution condition determination means for determining whether or not the variable display execution condition is satisfied during execution of the timer interrupt process;
Display result determination numerical value reading means for reading specific display result determination numerical data from the display result determination numerical value storage means based on the execution condition determination means determining that the variable display execution condition is satisfied; ,
By determining whether or not the specific display result determination numerical data read by the display result determination numerical value reading means matches predetermined specific display result determination value data, the display result in the variable display is converted into the display result in the variable display. Specific display result determination means for determining whether or not to obtain a specific display result;
Effect determination numerical data acquisition means for acquiring effect determination numerical data updated in synchronization with the specific display result determination numerical data updated by the specific display result determination numerical data update means;
An effect determination that determines whether or not to execute a predetermined effect by determining whether or not the effect determination numerical data acquired by the effect determination numerical data acquisition means matches the predetermined effect determination value data. Means,
The random number circuit setting means sets an initial value for setting whether the predetermined initial value is set to a predetermined value or a value based on unique identification information assigned to each game control microcomputer. means only including,
The gaming machine further includes:
A payout device for paying out game media;
A payout control board equipped with a payout control microcomputer for controlling the payout operation by the payout device,
The game control microcomputer includes a serial communication circuit that performs serial communication with the payout control microcomputer, and includes a communication control unit that controls serial communication operation by the serial communication circuit,
The serial communication circuit includes an interrupt request notification means for notifying an interrupt request according to an interrupt request condition established for the communication control means when one of a plurality of interrupt request conditions is established,
The interrupt request notified by the interrupt request notification means includes an error interrupt request for causing the communication control means to execute processing corresponding to the occurrence of an error when an interrupt request condition is satisfied due to an error occurring in serial communication. ,
The communication control means includes
When a plurality of types of interrupt requests are simultaneously notified by the interrupt request notification means, the interrupt processing based on the error interrupt request is executed in preference to processing based on an interrupt request of a type different from the error interrupt request. Interrupt processing sequence control means for
An error interrupt processing means for stopping execution of a serial communication operation by the serial communication circuit as an interrupt process based on the error interrupt request when the error interrupt request is notified by the interrupt request notification means;
A gaming machine characterized by that. Based on the fact that the variable display start condition is satisfied after the variable display execution condition is satisfied, a variable display device that variably displays each type of identification information that can be identified is provided, and the display result of the identification information is specified. A gaming machine that is in a specific gaming state that is advantageous to the player after the result,
A game control microcomputer for controlling the progress of the game;
Reference clock signal output means for outputting a reference clock signal of a predetermined period;
A game control board equipped with a random number circuit for generating random numbers,
The random number circuit includes:
Random number generating clock signal generating means for generating a random number generating clock signal based on the reference clock signal from the reference clock signal output means;
Specific display result determination used when determining whether or not the display result in the variable display is the specific display result based on the input of the random number generation clock signal generated by the random number generation clock signal generation means Specific display result determination numerical data updating means for cyclically updating the numerical data for use from a predetermined initial value to a predetermined final value in a predetermined range that can be updated, according to a predetermined order;
Display result determination numerical value storage means for storing the specific display result determination numerical data updated by the specific display result determination numerical data update means,
The game control microcomputer is:
Random number circuit setting means for setting the random number circuit to generate the random number after power supply to the gaming machine is started;
After the setting by the random number circuit setting means, a timer interrupt process execution permitting means for permitting execution of a timer interrupt process that occurs periodically,
Execution condition determination means for determining whether or not the variable display execution condition is satisfied during execution of the timer interrupt process;
Display result determination numerical value reading means for reading specific display result determination numerical data from the display result determination numerical value storage means based on the execution condition determination means determining that the variable display execution condition is satisfied; ,
By determining whether or not the specific display result determination numerical data read by the display result determination numerical value reading means matches predetermined specific display result determination value data, the display result in the variable display is converted into the display result in the variable display. Specific display result determination means for determining whether or not to obtain a specific display result;
Numerical data holding means for holding numerical data for specific display result determination read by the display result determination numerical value reading means;
Numerical value coincidence determination for determining whether or not the specific display result determination numerical data read by the display result determination numerical value reading means matches the specific display result determination numerical data held in the numerical data holding means. Means,
Due to the determination that the numerical value coincidence determination means does not match, the specific display result determination numerical data to be held in the numerical data holding means is newly read by the display result determination numerical value reading means. Retained numerical data update means for updating to result determination numerical data;
A coincidence continuous number counting unit that counts the number of times that the determination of matching by the numerical value coincidence determination unit is made continuously;
A coincidence continuous number determination unit that determines whether or not the number of times counted by the coincidence continuous number counting unit exceeds a predetermined coincidence continuous upper limit;
An abnormality detecting means for detecting that an abnormality has occurred in the random number circuit by the fact that the coincidence continuous number determining means has determined that the coincidence continuous upper limit value has been exceeded,
The random number circuit setting means sets an initial value for setting whether the predetermined initial value is set to a predetermined value or a value based on unique identification information assigned to each game control microcomputer. means only including,
The gaming machine further includes:
A payout device for paying out game media;
A payout control board equipped with a payout control microcomputer for controlling the payout operation by the payout device,
The game control microcomputer includes a serial communication circuit that performs serial communication with the payout control microcomputer, and includes a communication control unit that controls serial communication operation by the serial communication circuit,
The serial communication circuit includes an interrupt request notification means for notifying an interrupt request according to an interrupt request condition established for the communication control means when one of a plurality of interrupt request conditions is established,
The interrupt request notified by the interrupt request notification means includes an error interrupt request for causing the communication control means to execute processing corresponding to the occurrence of an error when an interrupt request condition is satisfied due to an error occurring in serial communication. ,
The communication control means includes
When a plurality of types of interrupt requests are simultaneously notified by the interrupt request notification means, the interrupt processing based on the error interrupt request is executed in preference to processing based on an interrupt request of a type different from the error interrupt request. Interrupt processing sequence control means for
An error interrupt processing means for stopping execution of a serial communication operation by the serial communication circuit as an interrupt process based on the error interrupt request when the error interrupt request is notified by the interrupt request notification means;
A gaming machine characterized by that. Based on the fact that the variable display start condition is satisfied after the variable display execution condition is satisfied, a variable display device that variably displays each type of identification information that can be identified is provided, and the display result of the identification information is specified. A gaming machine that is in a specific gaming state that is advantageous to the player after the result,
A game control microcomputer for controlling the progress of the game;
Reference clock signal output means for outputting a reference clock signal of a predetermined period;
A game control board equipped with a random number circuit for generating random numbers,
The random number circuit includes:
A random number generating clock signal generating means for dividing the reference clock signal from the reference clock signal output means to generate a random number generating clock signal;
Specific display result determination used when determining whether or not the display result in the variable display is the specific display result based on the input of the random number generation clock signal generated by the random number generation clock signal generation means Specific display result determination numerical data updating means for cyclically updating the numerical data for use from a predetermined initial value to a predetermined final value in a predetermined range that can be updated, according to a predetermined order;
Display result determination numerical value storage means for storing the specific display result determination numerical data updated by the specific display result determination numerical data update means,
The game control microcomputer is:
Random number circuit setting means for setting the random number circuit to generate the random number after power supply to the gaming machine is started;
After the setting by the random number circuit setting means, a timer interrupt process execution permitting means for permitting execution of a timer interrupt process that occurs periodically,
Execution condition determination means for determining whether or not the variable display execution condition is satisfied during execution of the timer interrupt process;
Display result determination numerical value reading means for reading specific display result determination numerical data from the display result determination numerical value storage means based on the execution condition determination means determining that the variable display execution condition is satisfied; ,
By determining whether or not the specific display result determination numerical data read by the display result determination numerical value reading means matches predetermined specific display result determination value data, the display result in the variable display is converted into the display result in the variable display. Specific display result determination means for determining whether or not to obtain a specific display result;
Signal level detecting means for detecting a change in the level of the random number generating clock signal generated by the random number generating clock signal generating means;
An abnormality detecting means for detecting that an abnormality has occurred in the random number circuit because a change in the level of the random number generating clock signal has not been detected for a predetermined period or more by the signal level detecting means,
The random number circuit setting means sets an initial value for setting whether the predetermined initial value is set to a predetermined value or a value based on unique identification information assigned to each game control microcomputer. means only including,
The gaming machine further includes:
A payout device for paying out game media;
A payout control board equipped with a payout control microcomputer for controlling the payout operation by the payout device,
The game control microcomputer includes a serial communication circuit that performs serial communication with the payout control microcomputer, and includes a communication control unit that controls serial communication operation by the serial communication circuit,
The serial communication circuit includes an interrupt request notification means for notifying an interrupt request according to an interrupt request condition established for the communication control means when one of a plurality of interrupt request conditions is established,
The interrupt request notified by the interrupt request notification means includes an error interrupt request for causing the communication control means to execute processing corresponding to the occurrence of an error when an interrupt request condition is satisfied due to an error occurring in serial communication. ,
The communication control means includes
When a plurality of types of interrupt requests are simultaneously notified by the interrupt request notification means, the interrupt processing based on the error interrupt request is executed in preference to processing based on an interrupt request of a type different from the error interrupt request. Interrupt processing sequence control means for
An error interrupt processing means for stopping execution of a serial communication operation by the serial communication circuit as an interrupt process based on the error interrupt request when the error interrupt request is notified by the interrupt request notification means;
A gaming machine characterized by that.

Images