JP5597451B2 - Slot machine - Google Patents

Description

  The present invention relates to a slot machine capable of generating a predetermined winning according to a display result of a variable display device capable of variably displaying a plurality of types of identification information each identifiable.

  A slot machine generally includes a variable display device having a plurality of (usually three) reels on which a plurality of types of symbols as identification information are drawn on the outer periphery, and first, a bet number is determined by a player's BET operation. The reels start to rotate when the start operation is performed with the set number of bets set, and the rotation is stopped by operating a stop button provided corresponding to each reel. When all reels stop rotating, a winning combination occurs when a predetermined winning symbol combination (for example, 7-7-7, hereinafter referred to as a symbol combination) is arranged on the winning line. To do. That is, the game is advanced by the player's operation.

  Also, in this type of slot machine, it is common to draw a role at the same time as the start operation and to win a winning combination on the condition that the lottery is won. There is a method of providing a counter that updates a numerical value within a certain range, extracting the numerical value of the counter when a start operation is detected, and using the extracted value as a random number (for example, see Patent Document 1).

JP 2005-152268 A

  As in the gaming machine described in Patent Document 1, when the start operation is detected, the counter value is extracted and the lottery is performed. After the start operation is detected and the counter value is extracted, When a numerical value is extracted from the counter again due to noise on the signal line of the start operation, a lottery is performed with a numerical value different from the value extracted by detecting the start operation.

  As a method of solving such a problem, a method of extracting a numerical value from the counter once and holding it until the extracted numerical value is read out can be considered. Even if it is made in a period that is not valid for the progress, the numerical value extracted from the counter remains retained, and a lottery is performed based on the numerical value extracted at a timing different from the timing at which the original start operation was performed Will cause serious problems.

  The present invention has been made paying attention to such problems, and can prevent a lottery from being performed using a numerical value different from the numerical value extracted at the timing when the game start operation is performed. The purpose is to provide a machine.

In order to solve the above-described problem, a slot machine according to claim 1 of the present invention provides:
Each comprising a plurality of variable display unit capable variable display by moving a plurality of types of identification information capable of identifying periodically,
After variable display of said variable display unit, in the variable variable display of the display unit derives a display result by stopping, a plurality of variable display portions of the display result combination winning can occur depending on the slot machine,
A game control microcomputer incorporating a control CPU for executing game control in the gaming machine based on the game control processing program;
A random number circuit that is built in or externally attached to the game control microcomputer and generates numerical data to be a random value;
Data storage means having a backup area in which stored data is retained even if power supply is stopped;
With
The random number circuit includes:
Numeric value updating means for updating and outputting numerical data according to a predetermined procedure;
Random value storage means for capturing and storing numerical data output from the numerical value updating means as a random number value;
Including
The game control microcomputer is:
Control determining means for making a predetermined determination by the control CPU based on a random number value generated by the random number circuit;
While the numerical data output from the numerical value updating means based on the input of a predetermined signal is stored in the random number storage means, the random number storage means is turned on to restrict the storage of new numerical data, while the random value storage means A predetermined flag that is turned off when the numerical value data stored in is read by the control CPU at the read timing of the random number value and permits storage of new numerical data;
Power interruption processing execution means for executing power interruption processing for enabling recovery based on data held in the backup area when a power interruption condition is satisfied;
A start command means for performing a start command when the power supply does not stop after execution of the power interruption process;
Control state return means for returning to the control state before the power interruption process based on the data held in the backup area triggered by the start command,
After executing the power interruption process, when waiting for the power supply to stop, the power interruption standby time processing means for turning off the predetermined flag,
Including
The slot machine is
A derivation operation means for operating for a player to derive a display result,
When the derivation operation means is operated, a movement value indicating a movement amount from the position where the derivation operation means is operated to a stop of the movement in a variable display unit corresponding to the derivation operation means is obtained by a predetermined compression method. Stored is the compressed compressed data, which is a compressed value obtained by compressing a plurality of movement values composed of movement values corresponding to a plurality of different determination results as to whether or not winning is permitted, by the predetermined compression method. Compressed data storage means;
A movement value acquisition means for acquiring a movement value according to a determination result as to whether or not to allow the generation of a prize from the movement value compressed data stored in the compressed data storage means;
Derivation control means for performing control for deriving a display result on the variable display unit corresponding to the operation of the derivation operation means based on the movement value acquired by the movement value acquisition means when the derivation operation means is operated;
Is further provided.
A slot machine according to claim 2 of the present invention,
Each comprising a plurality of variable display unit capable variable display by moving a plurality of types of identification information capable of identifying periodically,
After variable display of said variable display unit, in the variable variable display of the display unit derives a display result by stopping, a plurality of variable display portions of the display result combination winning can occur depending on the slot machine,
A game control microcomputer incorporating a control CPU for executing game control in the gaming machine based on the game control processing program;
A random number circuit that is built in or externally attached to the game control microcomputer and generates numerical data to be a random value;
With
The random number circuit includes:
Numeric value updating means for updating and outputting numerical data according to a predetermined procedure;
Random value storage means for capturing and storing numerical data output from the numerical value updating means as a random number value;
Including
The game control microcomputer is:
Control determining means for making a predetermined determination by the control CPU based on a random number value generated by the random number circuit;
While the numerical data output from the numerical value updating means based on the input of a predetermined signal is stored in the random number storage means, the random number storage means is turned on to restrict the storage of new numerical data, while the random value storage means A predetermined flag that is turned off when the numerical value data stored in is read by the control CPU at the read timing of the random number value and permits storage of new numerical data;
Control start time processing means for turning off the predetermined flag when game control is started with the activation of the control CPU;
Including
The slot machine is
A derivation operation means for operating for a player to derive a display result,
When the derivation operation means is operated, a movement value indicating a movement amount from the position where the derivation operation means is operated to a stop of the movement in a variable display unit corresponding to the derivation operation means is obtained by a predetermined compression method. Stored is the compressed compressed data, which is a compressed value obtained by compressing a plurality of movement values composed of movement values corresponding to a plurality of different determination results as to whether or not winning is permitted, by the predetermined compression method. Compressed data storage means;
A movement value acquisition means for acquiring a movement value according to a determination result as to whether or not to allow the generation of a prize from the movement value compressed data stored in the compressed data storage means;
Derivation control means for performing control for deriving a display result on the variable display unit corresponding to the operation of the derivation operation means based on the movement value acquired by the movement value acquisition means when the derivation operation means is operated;
Is further provided.
The slot machine according to means 1 of the present invention is:
A variable display device capable of deriving and displaying a display result in each of a plurality of variable display areas (reels 2L, 2C, 2R) that can be variably displayed by periodically moving a plurality of identifiable symbols. Prepared,
The game can be started by setting a predetermined number of bets for one game using the game value, and display results are derived in all of the plurality of variable display areas (reels 2L, 2C, 2R). A slot machine (slot machine 1) in which one game is completed by displaying the information, and a winning can be generated according to a combination of display results derived and displayed in the plurality of variable display areas (reels 2L, 2C, 2R). ) And
Start operation means (start switch 7) operated when starting the game,
Respective derivation operation means (stop switches 8L, 8C, 8R) operated when deriving display results of the plurality of variable display areas;
Game start means for starting a game when the start operation means (start switch 7) is operated in a startable state in which a game can be started;
Numerical data updating means (random number sequence changing circuit 555) for updating numerical data;
Regardless of whether the start operation means (start switch 7) is operated or not, the numerical data updated by the numerical data update means (random number sequence change circuit 555) is changed to a random value regardless of whether or not the start is possible. Random number extraction means (random number latch selector 558A) for extracting and storing in the numerical data storage area (random number value register R1D);
Numerical data reading means (reading numerical data at the start of the game) for reading numerical data stored in the numerical data storage area (random value register R1D) when the game starting means starts a game;
Pre-determining means (internal lottery) for determining whether or not to allow the generation of a prize using the numerical data read by the numerical data reading means;
When the derivation operation means (stop switches 8L, 8C, 8R) are operated, the movement from the position where the derivation operation means is operated to the stop of movement in the variable display area (reel) corresponding to the derivation operation means This is data obtained by compressing a movement value (the number of sliding frames) indicating the amount by a predetermined compression method, and is composed of movement values (number of sliding frames) corresponding to a plurality of different determination results by the prior determination means (internal lottery). Compressed data storage means (sliding frame number table) for storing moving value compressed data (1-byte data storing three sliding frame numbers) obtained by compressing a plurality of moving values (sliding frame numbers) by the predetermined compression method )When,
A movement value acquisition means for acquiring a movement value (the number of sliding frames) according to the determination result of the prior determination means from the movement value compression data stored in the compressed data storage means;
A variable display area corresponding to the operation of the derivation operation means based on the movement value (the number of sliding symbols) acquired by the movement value acquisition means when the derivation operation means (stop switches 8L, 8C, 8R) is operated. Derivation control means for performing control for deriving the display result of (reel);
After the numerical data is stored in the numerical data storage area (random value register R1D) by the random number extraction means (random number latch selector 558A), the random number extraction means (random number) is read until the stored numerical data is read out. The numerical data holding means (the latch of the new numerical data) for holding the numerical data stored in the numerical data storage area (random number register R1D) without new numerical data being stored by the latch selector 558A) Prohibited)
Game data holding means (backup power supply) for holding at least a part of game data (stored data in the RAM 507) even when power supply to the slot machine is stopped;
When power interruption conditions (detection of a voltage drop signal) are established, power interruption processing (electric power interruption processing (power interruption processing ()) is made possible based on the game data (stored in the RAM 507) held by the game data holding means. Power interruption processing execution means for executing main)),
A start command means for performing a start command (user reset) when the power supply does not stop after execution of the power cut processing (power cut processing (main));
Control state return means for returning to the control state before the power interruption process based on the game data (stored in the RAM 507) held by the game data holding means in response to the activation command (user reset);
Whether or not numerical data is stored in the numerical data storage area (random number register R1D) in a period of waiting for power supply to stop after execution of the power interruption process (power interruption process (main)) When it is determined that the numerical data is stored, the stored numerical data is read by reading the stored numerical data, so that the retention of numerical data by the numerical data holding means is released. Means (dummy reading of numerical data after power interruption processing),
It is characterized by having.
According to this feature, when the power supply is not stopped after a voltage drop temporarily due to a momentary power failure or the like, a start command is issued and the original state is restored. At the same time, when the numerical data is stored in the numerical data storage area during the period of waiting for the power supply to stop, the numerical data is read and the numerical data holding means releases the holding of the numerical data. The voltage temporarily becomes unstable, such as a momentary power failure, noise is applied to the signal line of the start operation means, the numerical data is stored in the numerical data storage area, and the state is maintained However, since it is immediately read out and new numerical data can be stored in the numerical data storage area, the numerical data that was retained due to noise during that time is used after recovery from an instantaneous power failure. The decision whether or not to allow the occurrence of a prize is not made, and the decision whether or not to allow the occurrence of a prize is made using a numerical value extracted at a timing different from the original timing. Can be prevented.
In addition, since the movement value compressed data stored in the compressed data storage means is data obtained by compressing a plurality of movement values composed of movement values corresponding to a plurality of different determination results by the prior determination means, Moving from the moving value compressed data to all of the variable display areas that are fluctuating, such as when performing control to derive the display result without using the moving value specified from the moving value compressed data for a part of the variable display area When it is not necessary to specify a value, a plurality of movement values can be efficiently compressed, and the capacity of the storage means for storing movement value compression data can be saved.
The start command means that the start command is issued when the power supply is not stopped after the power-off process is executed. For example, the power is not stopped even after a certain time has elapsed after the power-off process is executed. In this case, a start command may be issued, or after the power interruption process is performed, the supply voltage may be monitored, and a start command may be issued when the supply voltage becomes a certain value or more.

The slot machine according to means 2 of the present invention is the slot machine according to means 1,
By reading the numerical data stored in the numerical data storage area (random number register R1D) after starting the game control means (main control unit 41) for controlling the progress of the game and before starting the progress control of the game Further, it is characterized in that it comprises a holding release unit at startup (dummy reading of numeric data at startup) for releasing the numeric data held by the numeric data holding unit.
According to this feature, after starting the game control means, the numerical data stored in the numerical data storage area is read out before starting the progress control of the game, and the holding of the numerical data by the numerical data holding means is released. It is now possible to more reliably prevent the determination of whether or not to allow winnings using numerical data retained due to noise, etc., when the power is turned on or after a momentary power failure recovery can do.

The slot machine according to means 3 of the present invention is:
A variable display device capable of deriving and displaying a display result in each of a plurality of variable display areas (reels 2L, 2C, 2R) that can be variably displayed by periodically moving a plurality of identifiable symbols. Prepared,
The game can be started by setting a predetermined number of bets for one game using the game value, and display results are derived in all of the plurality of variable display areas (reels 2L, 2C, 2R). A slot machine (slot machine 1) in which one game is completed by displaying the information, and a winning can be generated according to a combination of display results derived and displayed in the plurality of variable display areas (reels 2L, 2C, 2R). ) And
Start operation means (start switch 7) operated when starting the game,
Respective derivation operation means (stop switches 8L, 8C, 8R) operated when deriving display results of the plurality of variable display areas;
Game start means for starting a game when the start operation means (start switch 7) is operated in a startable state in which a game can be started;
Numerical data updating means (random number sequence changing circuit 555) for updating numerical data;
Regardless of whether the start operation means (start switch 7) is operated or not, the numerical data updated by the numerical data update means (random number sequence change circuit 555) is changed to a random value regardless of whether or not the start is possible. Random number extraction means (random number latch selector 558A) for extracting and storing in the numerical data storage area (random number value register R1D);
Numerical data reading means (reading numerical data at the start of the game) for reading numerical data stored in the numerical data storage area (random value register R1D) when the game starting means starts a game;
Pre-determining means (internal lottery) for determining whether or not to allow the generation of a prize using the numerical data read by the numerical data reading means;
When the derivation operation means (stop switches 8L, 8C, 8R) are operated, the movement from the position where the derivation operation means is operated to the stop of movement in the variable display area (reel) corresponding to the derivation operation means This is data obtained by compressing a movement value (the number of sliding frames) indicating the amount by a predetermined compression method, and is composed of movement values (number of sliding frames) corresponding to a plurality of different determination results by the prior determination means (internal lottery). Compressed data storage means (sliding frame number table) for storing moving value compressed data (1-byte data storing three sliding frame numbers) obtained by compressing a plurality of moving values (sliding frame numbers) by the predetermined compression method )When,
A movement value acquisition means for acquiring a movement value (the number of sliding frames) according to the determination result of the prior determination means from the movement value compression data stored in the compressed data storage means;
A variable display area corresponding to the operation of the derivation operation means based on the movement value (the number of sliding symbols) acquired by the movement value acquisition means when the derivation operation means (stop switches 8L, 8C, 8R) is operated. Derivation control means for performing control for deriving the display result of (reel);
After the numerical data is stored in the numerical data storage area (random value register R1D) by the random number extraction means (random number latch selector 558A), the random number extraction means (random number) is read until the stored numerical data is read out. The numerical data holding means (the latch of the new numerical data) for holding the numerical data stored in the numerical data storage area (random number register R1D) without new numerical data being stored by the latch selector 558A) Prohibited)
By reading the numerical data stored in the numerical data storage area (random number register R1D) after starting the game control means (main control unit 41) for controlling the progress of the game and before starting the progress control of the game A release release unit at startup for releasing the numeric data held by the numeric data holding unit (a dummy reading of the numeric data at startup);
It is characterized by having.
According to this feature, after starting the game control means, the numerical data stored in the numerical data storage area is read out before starting the progress control of the game, and the holding of the numerical data by the numerical data holding means is released. When the power is turned on or the voltage at the momentary power failure is unstable, noise is applied to the signal line of the start operation means, and the numerical data is stored in the numerical data storage area. Even if it remains in the state, it is read before the progress control of the game is performed and new numerical data can be stored in the numerical data storage area. There is no decision as to whether or not to allow winnings to be made using numerical data held due to noise, etc., and lottery using numerical values extracted at a timing different from the original lottery opportunity It can be prevented taking place.
In addition, since the movement value compressed data stored in the compressed data storage means is data obtained by compressing a plurality of movement values composed of movement values corresponding to a plurality of different determination results by the prior determination means, Moving from the moving value compressed data to all of the variable display areas that are fluctuating, such as when performing control to derive the display result without using the moving value specified from the moving value compressed data for a part of the variable display area When it is not necessary to specify a value, a plurality of movement values can be efficiently compressed, and the capacity of the storage means for storing movement value compression data can be saved.

In the means 1 and 3, the numerical data holding means stores the numerical data by the random number extracting means until the stored numerical data is read after the numerical data is stored in the numerical data storage area by the random number extracting means. By prohibiting new extraction of data, the numerical data stored in the numerical data storage area may be retained, or after the numerical data is stored in the numerical data storage area by the random number extraction means The numerical value stored in the numerical data storage area is prohibited by prohibiting storage in the numerical data storage area even if the random number extracting means extracts the numerical data until the stored numerical data is read out. Data may be held.

The slot machine according to means 4 of the present invention is the slot machine according to any one of means 1 to 3,
Initial numerical data generating means (random number circuit setting processing) for generating initial numerical data (initial value of random number) when power supply starts;
Game data holding means (backup power supply) for holding at least a part of game data (stored data in the RAM 507) even when power supply to the slot machine is stopped;
Clocking means (watchdog timer 49a) for clocking based on the counter value;
Based on the establishment of a predetermined condition indicating the operation of the game control means (main control unit 41) for controlling the progress of the game (input of a drive signal for dynamically lighting the credit indicator 11), the time counting means (watchdog timer 49a) Counter value initialization means for initializing the counter value;
Processing for enabling recovery based on game data (stored in RAM 507) held by the game data holding means when the power interruption condition (detection of a voltage drop signal) is established, and establishment of the predetermined condition Power interruption processing execution means for executing power interruption processing (power interruption processing (main)) including processing for stopping
After execution of the power interruption process (power interruption process (main)), the power supply continues for a certain time without stopping, so that the counter value by the time measuring means (watchdog timer 49a) is not initialized but is predetermined. A start command means for performing a start command (user reset) when a predetermined threshold is reached (when overflowing),
Control state return means for returning to the control state before the power interruption process based on the game data (stored in the RAM 507) held by the game data holding means in response to the activation command (user reset);
With
The numerical data updating means starts updating the numerical data from the initial numerical data (initial value of random numbers) generated by the initial numerical data generating means (random number circuit setting process) when power supply is started. The update of the numerical data is continued even during a period of waiting for power supply to stop after execution of the power interruption process. After the power interruption process, the start command ( When the control state returning means returns the control state by a user reset), the updating of the numerical data is continued without using the initial numerical data (initial value of random number).
According to this feature, even if an activation command is intentionally issued, updating of numerical data continues, making it difficult to specify the timing at which updating of numerical data is started, and aiming at the timing of specific numerical data. Thus, it is possible to effectively prevent an unauthorized act of detecting the operation of the start operation means.

The slot machine according to means 5 of the present invention is the slot machine according to any one of means 1 to 3,
Initial numerical data generating means (random number circuit setting processing) for generating initial numerical data (initial value of random number) when power supply starts;
Game data holding means (backup power supply) for holding at least a part of game data (stored data in the RAM 507) even when power supply to the slot machine is stopped;
When power interruption conditions (detection of a voltage drop signal) are established, power interruption processing (electric power interruption processing (power interruption processing ()) is made possible based on the game data (stored in the RAM 507) held by the game data holding means. Power interruption processing execution means for executing main)),
Power interruption condition monitoring means for monitoring whether or not the power interruption condition is satisfied in a period of waiting for power supply to stop after execution of the power interruption process (power interruption process (main)); ,
A start command means for performing a start command (user reset) when it is determined by the power cut condition monitoring means that the power cut condition is not satisfied;
Control state return means for returning to the control state before the power interruption process based on the game data (stored in the RAM 507) held by the game data holding means in response to the activation command (user reset);
With
The numerical data updating means starts updating the numerical data from the initial numerical data (initial value of random numbers) generated by the initial numerical data generating means (random number circuit setting process) when power supply is started. The update of the numerical data is continued even during a period of waiting for power supply to stop after execution of the power interruption process. After the power interruption process, the start command ( When the control state returning means returns the control state by a user reset), the updating of the numerical data is continued without using the initial numerical data (initial value of random number).
According to this feature, even if an activation command is intentionally issued, updating of numerical data continues, making it difficult to specify the timing at which updating of numerical data is started, and aiming at the timing of specific numerical data. Thus, it is possible to effectively prevent an unauthorized act of detecting the operation of the start operation means.

The slot machine according to means 6 of the present invention is the slot machine according to any one of means 1 to 5,
The game starting means starts the game on the condition that, in the startable state, the operation of the start operating means (start switch 7) is continuously detected for a predetermined period (about 2.24 ms). It is said.
According to this feature, it is possible to prevent the game from starting and determining whether or not the winning is allowed even though the start operation means is erroneously detected due to noise such as static electricity. .

The slot machine according to means 7 of the present invention is the slot machine according to any one of means 1 to 6,
Game control means (main control unit 41) for controlling the progress of the game is provided,
The numerical data updating means (random number sequence changing circuit 555) inputs an operation clock (random number clock) having a different period from the operation clock (control clock) for operating the game control means (main control unit 41). Then, the numerical data is updated.
According to this feature, since the operation of the game control means and the update cycle of the numerical data are synchronized, it is possible to prevent the random number value used by the predetermining means from being biased, and the game control means has an illegal board. Even if is connected, it is impossible to specify the update interval of numerical data from the operation of the game control means, so it is possible to effectively prevent fraud in which the operation of the start operation means is detected aiming at the timing of specific numerical data it can.

The slot machine according to means 8 of the present invention is the slot machine according to any one of means 1 to 7,
The numerical data updating means (random number sequence changing circuit 555) inputs an operation clock (random number clock) with a predetermined period to update the numerical data,
The slot machine changes the operation state of the numerical data update means (random number sequence change circuit 555) based on the input state of the operation clock (random number clock) input to the numerical data update means (random number sequence change circuit 555). It is characterized by comprising operation clock abnormality determining means (random circuit abnormality inspection processing) for determining whether or not an abnormality has occurred.
According to this feature, it is possible to prevent fraud in which it is possible to determine whether or not to allow a prize to be generated while the numerical data is not normally updated by the numerical data updating means, that is, the numerical data is fixed.

It is a front view of a slot machine which is an example of a gaming machine to which the present invention is applied. It is an internal structure figure of a slot machine. It is a figure which shows the symbol arrangement | sequence of a reel. It is a block diagram which shows the structure of a slot machine. It is a block diagram which shows the structure of a main control part. It is a figure which shows an example of the address map in a main control part. It is a figure which illustrates the main part of a program management area and a built-in register. It is a figure which shows an example of the setting content in a header and function setting. It is a figure which shows an example of the setting content in 1st random number initial setting, 2nd random number initial setting, and interruption initial setting. It is a figure which shows an example of the setting content in security time setting. It is a figure which shows the structural example etc. of an internal information register. It is a block diagram which shows the structural example of a random number circuit. It is a figure which shows the structural example etc. of a random number sequence change register. It is explanatory drawing which shows the change operation | movement of the random number update rule by a random number sequence change circuit. It is explanatory drawing which shows the change operation | movement of the random number update rule by a random number sequence change circuit. It is a figure which shows the structural example etc. of a random value acquisition register. It is a figure which shows the structural example etc. of a random number latch selection register. It is a figure which shows the structural example of a random value register. It is a figure which shows the structural example etc. of a random number latch flag register. It is a figure which shows the structural example etc. of a random number interrupt control register. It is a figure which shows the structural example etc. of an input port register. It is a block diagram which shows the structural example of a serial communication circuit. It is a figure which shows the transmission condition of the command by a serial communication circuit. It is a block diagram which shows an example of a structure of an external output board | substrate, and an example of an external output signal. It is a figure which shows the structure of the combination defined as winning. It is a figure which shows the object combination of the internal lottery classified by game state. It is a figure which shows the structure of a sliding frame number table. It is a figure which shows the structure of a stop table. It is a figure which shows a stop data selection value. It is a figure which shows the acquisition method etc. of the number of sliding frames. It is a flowchart which shows the control content of the starting process (main) which a main control part performs at the time of starting. It is a flowchart which shows the control content of the security check process which a main control part performs. It is a flowchart which shows the control content of the random number circuit setting process which a main control part performs. It is a flowchart which shows the control content of the random circuit abnormality inspection process which a main control part performs. It is a flowchart which shows the control content of the command storage process which a main control part performs. It is a flowchart which shows the control content of the error process which a main control part performs when an error generate | occur | produces. It is a flowchart which shows the control content of the setting change process which a main control part performs. It is a flowchart which shows the control content of the game process which a main control part performs after a setting change process. It is a flowchart which shows the control content of the BET process which a main control part performs. It is a flowchart which shows the control content of the BET process which a main control part performs. It is a flowchart which shows the control content of the BET process which a main control part performs. It is a flowchart which shows the control content of the reel rotation process which a main control part performs. It is a flowchart which shows the control content of the reel rotation process which a main control part performs. It is a flowchart which shows the control content of the timer interruption process (main) which a main control part performs for every fixed interval. It is a flowchart which shows the control content of the timer interruption process (main) which a main control part performs for every fixed interval. It is a flowchart which shows the control content of the switch input determination process which a main control part performs in a timer interruption process (main). It is a flowchart which shows the control content of the random value reading process which a main control part performs in a timer interruption process (main). It is a flowchart which shows the control content of the door monitoring process which a main control part performs in a timer interruption process (main). It is a flowchart which shows the control content of the command transmission process which a main control part performs in a timer interruption process (main). (A) is a flowchart which shows the control content of the power interruption process (main) performed according to having detected the power interruption in the timer interruption process (main), (b) is the deformation | transformation. It is an example. It is a timing chart for demonstrating operation | movement in a random number circuit. It is a timing chart which shows the relationship between operation of a start switch, and a random value register. It is a timing chart which shows the relationship between operation of a start switch, and a random value register. It is a flowchart which shows the control content of the random value latch interruption process which a main control part performs when numerical data is latched in the random number circuit in a modification. It is a timing chart which shows the relationship between the operation of the start switch in a modification, and a random value register. It is a timing chart which shows the detection condition of a start switch. 5 is a timing chart showing the relationship between the status register value of the serial communication circuit and the transfer permission / prohibition of door command and operation detection command.

  Examples of the present invention will be described below.

  An embodiment of a slot machine, which is an example of a gaming machine to which the present invention is applied, will be described with reference to the drawings. A slot machine 1 according to the present embodiment includes a housing 1a having an open front surface and a side end of the housing 1a. The front door 1b is pivotally supported by the front door 1b.

  Inside the casing 1a of the slot machine 1 of the present embodiment, as shown in FIG. 2, reels 2L, 2C and 2R (hereinafter referred to as a left reel, a middle reel and a right reel) in which a plurality of types of symbols are arranged on the outer periphery. ) Are juxtaposed in the horizontal direction, and as shown in FIG. 1, three consecutive symbols out of the symbols arranged on the reels 2L, 2C, 2R can be seen from the see-through window 3 provided on the front door 1b. Are arranged as follows.

  As shown in FIG. 3, on the outer periphery of the reels 2L, 2C, and 2R, “black 7”, “net 7 (shaded 7 in the figure)”, “white 7”, “BAR”, “replay”, A plurality of identifiable symbols such as “watermelon”, “black cherry”, “white cherry”, “bell”, and “orange” are drawn in a predetermined order, 21 pieces each. The symbols drawn on the outer peripheries of the reels 2L, 2C, and 2R are displayed in the upper, middle, and lower three stages in the see-through window 3, respectively.

  The reels 2L, 2C, and 2R are provided in correspondence with each other and rotated by reel motors 32L, 32C, and 32R (see FIG. 4), so that the symbols of the reels 2L, 2C, and 2R are continuously provided in the see-through window 3. In addition to being displayed while changing, by stopping the rotation of the reels 2L, 2C, and 2R, three consecutive symbols are derived and displayed on the fluoroscopic window 3 as display results.

  Inside the reels 2L, 2C, and 2R are reel sensors 33L, 33C, and 33R that detect a reference position for each of the reels 2L, 2C, and 2R, and a reel LED 55 that irradiates the reels 2L, 2C, and 2R from the back side. , Is provided. The reel LED 55 includes 12 LEDs corresponding to three consecutive symbols of the reels 2L, 2C, and 2R, and can irradiate each symbol independently.

  A display area 51a of a liquid crystal display 51 (see FIG. 1) is disposed at a position on the front side (player side) of each reel 2L, 2C, 2R of the front door 1b. The liquid crystal display 51 has a normally white liquid crystal panel having transparency in a state where no voltage is applied to the liquid crystal element, and a transmissive region 51b corresponding to the see-through window 3 of the display region 51a. The reels 2L, 2C, and 2R can be visually recognized from the player side through the see-through window 3. Further, a backlight (not shown) for irradiating the display area 51a from behind is provided on the back surface of the display area 51a excluding the transmissive area 51b, and the back surface further has a concealing member for concealing the inside. (Not shown) is provided.

  On the front door 1b, a medal insertion unit 4 into which medals can be inserted, a medal payout exit 9 from which medals are paid out, and credits (the number of medals stored as a game value owned by the player) are used for one medal. Using a single BET switch 5 and credits that are operated when setting the bet number, an operation is performed when setting the maximum bet number among the prescribed number of bets determined according to the gaming state within the range. The MAXBET switch 6 to be operated, and the settlement switch 10 operated when the medals stored as credits and the medals used for setting the betting amount are settled (the medal used for setting the credits and the betting amount is returned). The start switch 7 that is operated when starting the game, and the stop switches 8L, 8C, 8R that are operated when stopping the rotation of the reels 2L, 2C, and 2R, respectively. It is provided operable by the player.

  The front door 1b also displays a credit indicator 11 that displays the number of medals stored as credits, the number of medals acquired in BB, which will be described later, and an error code that indicates the contents when an error occurs. An auxiliary indicator 12 and a payout indicator 13 for displaying the number of medals paid out due to the occurrence of a prize are provided.

  Further, on the front door 1b, 1BETLED 14 that notifies that the bet number is set to 1 by lighting, 2BETLED 15 that notifies that the bet number is set to 2, and 3 bets are set. 3BET LED 16 to notify when lit, insertion request LED 17 to notify that a medal can be inserted is lit, start valid LED 18 to notify that the game start operation by the operation of the start switch 7 is effective, wait (previous Waiting state LED 19 for informing that it is in the state of waiting for the start of reel rotation since a certain period of time has not elapsed since the start of the game, during replay informing that it is in the replay game described later An LED 20 is provided.

  Inside the MAXBET switch 6, there is provided a BET switch valid LED 21 (see FIG. 4) for notifying that the setting operation of the betting number by operating the one-sheet BET switch 5 and the MAXBET switch 6 is effective. Inside the stop switches 8L, 8C, and 8R, left, middle, and right stop effective LEDs 22L, 22C, and 22R for informing that the reel stop operation by the corresponding stop switches 8L, 8C, and 8R is effective by lighting (FIG. 4).

  Inside the front door 1b, there is a reset switch 23 for detecting a reset operation for releasing an error state described later and a stop state described later by a predetermined key operation, while changing a set value and confirming a set value described later. A set value display 24 for displaying the set value at that time, and a flow path of medals inserted from the medal insertion unit 4 on the side of a hopper tank 34a (see FIG. 2) described later provided in the housing 1a or A medal selector having a insertion medal sensor 31 for detecting a medal that is inserted from the flow path switching solenoid 30 and the medal insertion unit 4 and selectively flows to the hopper tank 34a side to selectively switch to one of the medal payout exits 9 side. (Not shown), a door open detection switch 25 (see FIG. 4) for detecting the open state of the front door 1b, a stop state (reset operation is performed at the end of BB described later) A stop switch 36a for selecting valid / invalid of the stop function to be controlled to a state where the progress of the game is restricted), automatic settlement processing at the end of BB (to be described later) An automatic settlement switch 36b is provided for selecting whether to enable / disable the automatic settlement function that is controlled for settlement (returning regardless of operation).

  As shown in FIG. 2, a reel sensor 33L that can detect the reel reference positions of the reels 2L, 2C, and 2R, the reel motors 32L, 32C, and 32R, and the reels 2L, 2C, and 2R, as shown in FIG. , 33C, 33R (see FIG. 4), an external output board 1000 for outputting an external output signal, a hopper tank 34a for storing medals inserted from the medal insertion section 4, and a hopper tank 34a. A hopper unit 34 including a hopper motor 34b for paying out medals from the medal payout opening 9, a payout sensor 34c for detecting medals paid out by driving the hopper motor 34b, and a power supply box 100 are provided.

  On the side of the hopper unit 34, an overflow tank 35 is provided for storing medals overflowing from the hopper tank 34a. Inside the overflow tank 35, a full sensor 35 a made up of a pair of electrically conductive members spaced apart from each other and provided at a height capable of detecting a predetermined amount of stored medals is provided. It is possible to detect that the medal storage amount stored in the inside when it is conductive by contacting through the medal stored in the inside exceeds a predetermined amount, that is, that the overflow tank is full. It has become.

  On the front face of the power supply box 100, a setting key switch 37 for switching to a setting change state or a setting confirmation state functions as a reset switch for canceling an error state or the above-described stop state in a normal state. Are provided with a reset / setting switch 38 that functions as a setting switch for changing a setting value of a winning probability (outtake rate) of internal lottery, which will be described later, and a power switch 39 that is operated when the power is turned on / off. ing.

  When a game is played in the slot machine 1 of the present embodiment, first, medals are inserted from the medal insertion unit 4 or a bet number is set using credits. In order to use credits, the single BET switch 5 or the MAXBET switch 6 may be operated. When a predetermined number of bets determined according to the gaming state are set, the pay lines L1 to L5 (see FIG. 1) become effective, and the operation of the start switch 7 is effective, that is, the game can be started. It becomes a state. In addition, when a medal is inserted exceeding the maximum number out of the prescribed number corresponding to the gaming state, the amount is added to the credit.

  The winning line is a line that is set to determine whether a combination of symbols displayed on the perspective windows 3 of the reels 2L, 2C, and 2R is a winning symbol combination. In this embodiment, as shown in FIG. 1, the winning line L1 set across the symbols arranged in the middle of each reel 2L, 2C, 2R and the symbols arranged in the upper row of each reel 2L, 2C, 2R are straddled. The winning line L2, the winning line L3, the lower stage of the reel 2L, the middle stage of the reel 2C, the upper stage of the reel 2R, that is, the upper side of the reel 2R, that is set across the symbols arranged in the lower stage of the reels 2L, 2C, 2R. There are five types of winning lines L4 set across straddling symbols: the winning line L4, the upper reel 2L, the middle reel 2C, the lower reel 2R; It is defined as.

  When the start switch 7 is operated in a state where the game can be started, the reels 2L, 2C, and 2R rotate, and the symbols of the reels 2L, 2C, and 2R continuously vary. When any one of the stop switches 8L, 8C, 8R is operated in this state, the rotation of the corresponding reels 2L, 2C, 2R is stopped, and the display result is derived and displayed on the fluoroscopic window 3.

  Then, when all the reels 2L, 2C, 2R are stopped, one game is completed, and a combination of symbols (hereinafter also referred to as roles) that are validated and predetermined on the winning line is each reel 2L, 2C, 2R. When the display result is stopped, a winning occurs, and a predetermined number of medals are awarded to the player and added to the credit. Further, when the credit reaches the upper limit number (50 in this embodiment), medals are paid out directly from the medal payout opening 9 (see FIG. 1). In addition, when a combination of symbols with payout of medals is arranged on a plurality of winning lines that are activated, the number of payouts determined for each of the combinations of symbols that are activated and aligned on the winning line is totaled, The total number of medals will be awarded to the player. However, an upper limit (15 in this embodiment) is set for the number of medals to be awarded in one game, and when the total number of medals exceeds the upper limit, the upper limit number of medals is awarded. It will be. In addition, when the combination of symbols accompanied by the transition of the gaming state is stopped as a display result of each reel 2L, 2C, 2R on the winning line, the gaming state is shifted according to the combination of symbols. ing.

  FIG. 4 is a block diagram showing a configuration of the slot machine 1. As shown in FIG. 4, the slot machine 1 is provided with a game control board 40, an effect control board 90, and a power supply board 101. The game state is controlled by the game control board 40, and the game state is controlled by the effect control board 90. The production according to the control is controlled, and the power supply board 101 generates the drive power for the electrical components constituting the slot machine 1 and supplies them to each part.

  The power supply board 101 is supplied with AC100V power from the outside, and from this AC100V power supply, a DC voltage necessary for driving electrical components constituting the slot machine 1 is generated, and the game control board 40 and the game control board 40 are generated. It is supplied to the production control board 90 connected through the. In addition, a command transmission line from the main control unit 41 to the sub control unit 91, which will be described later, and a power supply line for supplying power from the game control board 40 to the effect control board 90 are connected via a single cable and connector. Are connected to each other, and all the connectors that connect these cables and the respective boards are connected to each other so that the respective parts on the side of the effect control board 90 can operate and receive commands from the main control part 41. Become. For this reason, unless the command transmission line for transmitting a command from the main control unit 41 is connected to the effect control board 90, power is not supplied to the effect control board 90, and only the effect control board 90 side operates. There is no end to it.

  Further, the above-described hopper motor 34b, payout sensor 34c, full sensor 35a, setting key switch 37, reset / setting switch 38, and power switch 39 are connected to the power supply board 101.

  On the game control board 40, the one-sheet BET switch 5, the MAXBET switch 6, the start switch 7, the stop switches 8L, 8C, 8R, the settlement switch 10, the reset switch 23, the insertion medal sensor 31, the door opening detection switch 25, A stop switch 36a, an automatic checkout switch 36b, and reel sensors 33L, 33C, and 33R are connected, and the above-described payout sensor 34c, full sensor 35a, setting key switch 37, and reset / setting switch 38 are connected via the power supply board 101. Are connected, and the detection signals of these connected switches are inputted.

  Further, the game control board 40 includes the credit display 11, the game auxiliary display 12, the payout display 13, 1 to 3 BET LEDs 14 to 16, the insertion request LED 17, the start valid LED 18, the waiting LED 19, the replaying LED 20, and the BET. The switch effective LED 21, left, middle, and right stop effective LEDs 22L, 22C, and 22R, the set value display 24, the flow path switching solenoid 30, and the reel motors 32L, 32C, and 32R are connected to each other, and are described above via the power supply board 101. The hopper motor 34b is connected, and these electric components are driven based on control of a main control unit 41 (described later) mounted on the game control board 40.

  The game control board 40 includes a main control unit 41, a control clock generation circuit 42, a random number clock generation circuit 43, a switch detection circuit 44, a motor drive circuit 45, a solenoid drive circuit 46, an LED drive circuit 47, and a power interruption detection circuit. 48 and a reset circuit 49 are mounted.

  The main control unit 41 is configured by a one-chip microcomputer, executes a control program stored in a ROM 506, which will be described later, and performs processing related to the progress of the game, and also includes a control circuit mounted on the game control board 40. Control each part directly or indirectly.

  The control clock generation circuit 42 generates a control clock CCLK serving as an oscillation signal having a predetermined frequency outside the main control unit 41. The control clock CCLK generated by the control clock generation circuit 42 is supplied to the clock circuit 502 via the control external clock terminal EXC of the main control unit 41 as shown in FIG. 5A, for example. The random number clock generation circuit 43 generates a random number clock RCLK that is an oscillation signal having a predetermined frequency different from the oscillation frequency of the control clock CCLK, outside the main control unit 41. The random number clock RCLK generated by the random number clock generation circuit 43 is supplied to the random number circuit 509 via the random number external clock terminal ERC of the main control unit 41 as shown in FIG. 5A, for example. As an example, the oscillation frequency of the random number clock RCLK generated by the random number clock generation circuit 43 may be set to be equal to or lower than the oscillation frequency of the control clock CCLK generated by the control clock generation circuit 42.

  The switch detection circuit 44 takes in detection signals input from switches connected directly to the game control board 40 or via the power supply board 101 and transmits them to the main control unit 41. The motor drive circuit 45 transmits the motor drive signal output from the main control unit 41 to the reel motors 32L, 32C, and 32R. The solenoid drive circuit 46 transmits the solenoid drive signal output from the main control unit 41 to the flow path switching solenoid 30. The LED drive circuit transmits the LED drive signal output from the main control unit 41 to various displays and LEDs connected to the game control board 40. The power interruption detection circuit 48 monitors the power supply voltage supplied to the slot machine 1 and outputs a voltage drop signal indicating that to the main control unit 41 when a voltage drop is detected. The reset circuit 49 provides a system reset signal to the main control unit 41 in a state where the power is unstable, such as when the power is turned on or when the power is turned off. The reset circuit 49 has a built-in watchdog timer 49a (see FIG. 5B) that counts the operation stop time of the CPU 505 by adding a built-in counter value in accordance with the input of the control clock CCLK. When the timer 49a expires (when the counter value exceeds a threshold value), that is, when the operation of the CPU 505 of the main control unit 41 is stopped for a certain time, a user reset signal is given to the main control unit 41.

  FIG. 5A shows a configuration example of the main control unit 41 mounted on the game control board 40. The main control unit 41 shown in FIG. 5A is a one-chip microcomputer, and includes an external bus interface 501, a clock circuit 502, a specific information storage circuit 503, a reset / interrupt controller 504, a CPU 505, and a ROM 506. A RAM 507, a CTC (counter / timer circuit) 508, a random number circuit 509, a PIP (parallel input port) 510, a serial communication circuit 511, and an address decode circuit 512.

  FIG. 6 shows an example of an address map in the main control unit 41. As shown in FIG. 6, the area from address 0000H to address 1FFFH is allocated to the ROM 506 and includes a user program area and a program management area. FIG. 7A shows an example of the usage and contents of the main part of the program management area in the ROM 506. The area from address 2000H to address 20FFH is a built-in register area assigned to the built-in register of the main control unit 41. FIG. 7B shows an example of the usage and contents of the main part of the built-in register area. An area from address 7E00H to address 7FFFH is a work area assigned to the RAM 507, and can be assigned to an I / O map or a memory map. An area from address FDD0H to address FDFBH is an XCS decode area allocated to the address decode circuit 512.

  The program management area is a storage area for storing information necessary for the CPU 505 to execute the user program. As shown in FIG. 7A, the program management area includes a header KHDR, a function setting KFCS, a first random number initial setting KRS1, a second random number initial setting KRS2, an interrupt initial setting KIIS, a security time setting KSES, include.

  A header KHDR stored in the program management area indicates reading setting of internal data in the main control unit 41. FIG. 8A illustrates the correspondence between setting data and operation in the header KHDR. Here, the main control unit 41 can set a ROM read prevention function and a bus output mask function. The ROM read prevention function is a function for permitting or prohibiting the read operation for the data stored in the ROM 506 provided in the main control unit 41. When the read prohibition is set, the data stored in the ROM 506 cannot be read. The bus output mask function is used for address bus output, data bus output, and control signal output in the external bus interface 501 when an external device connected to the external bus interface 501 makes a read request for internal data of the main control unit 41. This function disables reading of internal data from an external device by applying a mask. As shown in FIG. 8A, the operation combination of the ROM read prevention function and the bus output mask function is set differently in accordance with the setting data of the header KHDR. Of the setting data shown in FIG. 8A, the setting data for which ROM reading is permitted and the bus output mask is valid is also referred to as bus output mask valid data. Further, the setting data (all “00H”) in which ROM reading is prohibited and the bus output mask is valid is also referred to as ROM reading prohibiting data. The setting data for which ROM reading is permitted and the bus output mask becomes invalid is also referred to as bus output mask invalid data.

  The function setting KFCS stored in the program management area indicates the operation setting of the watchdog timer in the main control unit 41 and the use setting of various function shared terminals. FIG. 8B shows an example of setting contents in the function setting KFCS.

  The bit number [7-5] of the function setting KFCS indicates, for example, permission / prohibition of the operation of the watchdog timer that can be set as an interrupt factor in the reset / interrupt controller 504, and the cycle when it is permitted. In this embodiment, since an external watchdog timer is used, the watchdog timer is set to prohibit operation. The bit number [4] of the function setting KFCS indicates that the predetermined function shared terminal (first shared terminal) in the main control unit 41 is the second channel transmission terminal TXB used by the serial communication circuit 511 or the address decoding circuit 512. Is a TXB terminal setting that designates whether to use the chip select output terminal XCS13. In the example shown in FIG. 8B, if the bit value in the bit number [4] of the function setting KFCS is “0”, the first shared terminal is used for the second channel transmission in the serial communication circuit 511. This is the setting for the 2-channel transmission terminal TXB. On the other hand, if the bit value is “1”, the first dual-purpose terminal is set to the chip select output terminal XCS13 used in the address decode circuit 512. In this embodiment, the bit number [4] of the function setting KFCS is set to “0” and the first shared terminal is set to the second channel transmission terminal TXB, so that serial communication with the effect control board 90 is possible. To.

  The bit number [3] of the function setting KFCS indicates that the predetermined function shared terminal (second shared terminal) in the main control unit 41 is the first channel transmission terminal TXA used by the serial communication circuit 511 or the address decoding circuit 512. Is a TXA terminal setting indicating whether the chip select output terminal XCS12 is used. In the example shown in FIG. 8B, if the bit value in the bit number [3] of the function setting KFCS is “0”, the second shared terminal is used for the first channel transmission in the serial communication circuit 511. 1 channel transmission terminal TXA is set. On the other hand, if the bit value is “1”, the second dual-purpose terminal is set to the chip select output terminal XCS12 used in the address decode circuit 512. In this embodiment, the bit number [3] of the function setting KFCS is set to “0” and the second shared terminal is set to the first channel transmission terminal TXA, but the first channel reception is not used.

  For the bit number [2] of the function setting KFCS, a predetermined function shared terminal (third shared terminal) in the main control unit 41 is used as the first channel reception terminal RXA used by the serial communication circuit 511, or is used by the PIP 510. This is an RXA terminal setting indicating whether the input port is P5. In the example shown in FIG. 8B, if the bit value in the bit number [2] of the function setting KFCS is “0”, the third shared terminal is used for the first channel reception in the serial communication circuit 511. 1 channel receiving terminal RXA is set. On the other hand, if the bit value is “1”, the third shared terminal is set to the input port P5 used in the PIP 510. In this embodiment, the bit number [2] of the function setting KFCS is set to “0” and the third shared terminal is set to the first channel reception terminal RXA, but the first channel reception is not used.

  The bit number [1] of the function setting KFCS is an input used by the PIP 510, or a predetermined function shared terminal (fourth shared terminal) in the main control unit 41 is an external non-maskable interrupt terminal XNMI connected to the CPU 505 or the like. This is an NMI connection setting indicating whether to set the port P4. In the example shown in FIG. 8B, if the bit value [1] in the bit number [1] of the function setting KFCS is “0”, the setting of the external non-maskable interrupt terminal XNMI whose fourth shared terminal is connected to the CPU 505 and the like (CPU connection). On the other hand, if the bit value is “1”, the fourth shared terminal is set for the input port P4 used in the PIP 510 (CPU disconnected). In this embodiment, the bit number [1] of the function setting KFCS is set to “1” and the fourth shared terminal is set to the input port P4 used in the PIP 510, but the input port P4 is unused. .

  The bit number [0] of the function setting KFCS is an input used by the PIP 510, or the predetermined function shared terminal (fifth shared terminal) in the main control unit 41 is set to the external maskable interrupt terminal XINT connected to the CPU 505 or the like. This is an XINT connection setting indicating whether the port is P3. In the example shown in FIG. 8B, if the bit value in the bit number [0] of the function setting KFCS is “0”, the setting of the external maskable interrupt terminal XINT in which the fifth shared terminal is connected to the CPU 505 and the like (CPU connection). On the other hand, if the bit value is “1”, the fifth shared terminal is set for the input port P3 used in the PIP 510 (CPU disconnected).

  The first random number initial setting KRS1 and the second random number initial setting KRS2 stored in the program management area indicate the initial setting of the random number circuit 509. FIG. 9A shows an example of the setting contents in the first random number initial setting KRS1. FIG. 9B shows an example of setting contents in the second random number initial setting KRS2.

  The bit number [3] of the first random number initial setting KRS1 is a random number circuit use setting indicating whether to use the random number circuit 509 or not. In the example shown in FIG. 9A, if the bit value in the bit number [3] of the first random number initial setting KRS1 is “0”, the random number circuit 509 is not used (unused), but “1”. "Is set to use the random number circuit 509 (use). In this embodiment, the random number circuit 509 is set to be usable by setting the bit number [3] of the first random number initial setting KRS1 to “1”.

  The bit number [2] of the first random number initial setting KRS1 uses the random number update clock RGK (see FIG. 12) used for updating the numerical data as the random number value in the random number circuit 509 as the internal system clock SCLK or for the random number This is a random number update clock setting indicating whether the clock RCLK is divided by two. In the example shown in FIG. 9A, if the bit value in the bit number [2] of the first random number initial setting KRS1 is “0”, the internal system clock SCLK is set to be used as the random number update clock RGK. If it is 1 ″, the random number clock RCLK is divided by two and used as the random number update clock RGK. In the present embodiment, the bit number [2] of the first random number initial setting KRS1 is set to “1”, and the random number clock RCLK is divided by two to be used as the random number update clock RGK.

  The bit number [1-0] of the first random number initial setting KRS1 is a random number update rule setting indicating whether or not to change the random number update rule in the random number circuit 509 and the change method in the case of the change. In the example shown in FIG. 9A, if the bit value in the bit number [1-0] of the first random number initial setting KRS1 is “00”, the random number update rule is not changed, and if it is “01”. The setting for changing the random number update rule by software is made after the second round, and if it is “10”, the random number update rule is automatically changed after the second round.

  The bit number [3-2] of the second random number initial setting KRS2 is set to a fixed bit value “00”. Note that “B” of “00B” in FIG. 9B indicates binary display. The bit number [1-0] of the second random number initial setting KRS2 indicates the setting relating to the start value in the numerical data that becomes the random value in the random number circuit 509. In the example shown in FIG. 9B, if the bit value in the bit number [1] of the second random number initial setting KRS2 is “0”, the start value is set to a predetermined default value 0001H, while “1”. Is set to a value based on an ID number, which is unique identification information given to each main control unit 41. In the example shown in FIG. 9B, if the bit value in the bit number [0] of the second random number initial setting KRS2 is “0”, the start value is not changed every time the system is reset. When it is 1 ″, the start value is changed every time the system is reset.

  In this embodiment, the bit value at bit number [1] of the second random number initial setting KRS2 is set to “1”, and the bit value at bit number [0] of the second random number initial setting KRS2 is set to “1”. Each time the system is reset, a value based on the ID number is set as the start value.

When the start value is set to a value based on the ID number, a part or all of the calculation for performing a predetermined scramble process on the ID number and the calculation such as addition, subtraction, multiplication, and division using the ID number are performed. It is only necessary to execute and use the calculated value as the start value. When the start value is changed at each system reset, for example, the count value of the free run counter built in the main control unit 41 is set to a predetermined internal register (random number start) provided in the main control unit 41 when the system reset occurs. Value register). Then, by using the stored value of the random number start value register as it is at the time of initial setting or by using the value obtained by substituting the stored value into a predetermined arithmetic function (for example, a hash function), the start value is It may be determined at random. The free-run counter only needs to be backed up using a backup power source common to the backup location on the game control board 40. Alternatively, the free-run counter may be backed up by a power source provided separately from a backup power source used for a backup area in the RAM 507 or the like. Thus, by the free run counter it is backed up by backup power source, even when the power supply stops, the predetermined period will be counted value in the free run counter is stored.

  Further, in the case where two systems (corresponding to the first and second channels) for generating numerical data to be random numbers in the random number circuit 509 are provided, the first shown in FIGS. 9A and 9B. The bit number [3-0] of the random number initial setting KRS1 and the bit number [3-0] of the second random number initial setting KRS2 are used to indicate the initial setting in the first channel. On the other hand, the bit number [7-4] of the first random number initial setting KRS1 and the bit number [7-4] of the second random number initial setting KRS2 (omitted in FIGS. 9A and 9B), the second What is necessary is just to use as a thing which shows the initial setting in a channel.

  The interrupt initial setting KIIS stored in the program management area indicates an initial setting related to handling of maskable interrupts generated in the main control unit 41. FIG. 9C shows an example of setting contents in the interrupt initial setting KIIS.

  In the bit number [7-4] of the interrupt initial setting KIIS, the upper 4 bits of the interrupt vector are set. In the bit number [3-0] of the interrupt initial setting KIIS, a combination of priority levels of maskable interrupt factors is set. In the example shown in FIG. 9C, if any of “00H” to “02H” and “06H” is specified by the bit number [3-0] of the interrupt initial setting KIIS, the maskable interrupt from the CTC 508 A combination of priorities with the factor as the highest priority is set. On the other hand, if any one of “03H” and “07H” is designated, a combination of priorities that gives the highest priority to the maskable interrupt factor from the random number circuit 509 is set. If either “04H” or “05H” is designated, a combination of priorities with the highest priority given to the maskable interrupt factor from the serial communication circuit 511 is set. If the specified value is different even if the priority is a combination of priority with the maskable interrupt factor from the same circuit as the highest priority, the type of maskable interrupt factor with the highest priority and the priority combination in the second or lower order, etc. Is different.

  The security time setting KSES stored in the program management area is the frequency at which an abnormality is detected when monitoring the frequency of the random number clock RCLK, the time of the security mode in which the main control unit 41 starts operation (security time). ). Here, when the operation mode of the main control unit 41 is the security mode, a predetermined security check process is executed to check whether or not the contents stored in the ROM 506 have been changed. FIG. 10A shows an example of setting contents in the security time setting KSES.

  Bit number [7-6] of security time setting KSES is a random number clock abnormality detection setting indicating a frequency at which an abnormality is detected when the frequency of random number clock RCLK is monitored. FIG. 10B shows an example of setting contents in the bit number [7-6] of the security time setting KSES. The bit number [7-6] of the security time setting KSES specifies a reference value (determination value) at which the frequency of the random number clock RCLK is detected as abnormal based on the frequency of the internal system clock SCLK. The bit number “5” of the security time setting KSES is set to a fixed bit value “0”.

  The bit number [4-3] of the security time setting KSES indicates a time setting when the security time is extended by a random time every system reset. FIG. 10C shows an example of setting contents in the bit number [4-3] of the security time setting KSES. In the example shown in FIG. 10C, if the bit value in the bit number [4-3] of the security time setting KSES is “00”, the setting is not performed at random time extension. On the other hand, if the bit value is “01”, the short mode is set, and if the bit value is “10”, the long mode is set. Here, when the short mode or the long mode is designated, for example, the count value of the free run counter built in the main control unit 41 is changed to a predetermined built-in register (variable) included in the main control unit 41 when a system reset occurs. Store in the security time register. Then, the security time can be reduced by using the stored value of the variable security time register as it is at the initial setting or by using the value obtained by substituting the stored value into a predetermined arithmetic function (for example, a hash function). What is necessary is just to determine the extension time at the time of extending at random. As an example, when the frequency of the internal system clock SCLK is 6.0 MHz, the extension time is randomly determined in the range of 0 to 680 μs (microseconds) in the short mode, and in the range of 0 to 348, 160 μs in the long mode. The extension time is determined at random. As another example, when the frequency of the internal system clock SCLK is 10.0 MHz, the extension time is randomly determined in the range of 0 to 408 μs in the short mode, and in the range of 0 to 208,896 μs in the long mode. The extension time is determined at random. The free-run counter used for randomly determining the extension time for extending the security time for each system reset randomly determines the start value of the random number generated by the random number circuit 509 for each system reset. Therefore, the counter may be the same as the free-run counter used for this purpose, or may be a counter provided separately.

Bit number [2-0] of security time setting KSES indicates time setting when the security time is set to one of a plurality of pre-selectable extended times in addition to the fixed time. FIG. 10D shows an example of setting contents in the bit number [2-0] of the security time setting KSES. In the example shown in FIG. 10D, if the bit value in the bit number [2-0] of the security time setting KSES is “000”, there is no extension time added to the fixed time, and no setting is made. On the other hand, if the bit value is a value other than “000”, it is set to one of a plurality of extension times determined using the cycle T _SCLK of the internal system clock SCLK. In this case, a different extension time is set according to the designated bit value. As an example, if the bit value [2-0] of the security time setting KSES is “001” when the frequency of the internal system clock SCLK is 6.0 MHz, about 699.1 ms in addition to the fixed time. (Milliseconds) extension time is set. As another example, when the frequency of the internal system clock SCLK is 10.0 MHz and the bit value in the bit number [2-0] of the security time setting KSES is “001”, in addition to the fixed time An extension time of about 419.4 ms is set.

  Further, the short mode or the long mode is set by the bit value [4-3] of the security time setting KSES, and the bit value in the bit number [2-0] of the security time setting KSES is set to other than “000”. Thus, it is possible to set an extension time to be added to the fixed time. In this case, both the extension time corresponding to the bit value in the bit number [2-0] and the extension time randomly determined based on the bit value in the bit number [4-3] are fixed times. By adding, the security time for the main control unit 41 to be in the security mode is determined.

  The external bus interface 501 provided in the main control unit 41 shown in FIG. 5A is an interface function between the external bus and the internal bus of the chip constituting the main control unit 41, the address bus, the data bus, and the direction of each control signal. A bus interface having a control function and the like. For example, the external bus interface 501 is connected to an external memory or an external input / output device externally attached to the main control unit 41, and transmits / receives address signals, data signals, various control signals, and the like to / from these external devices. Anything to do. In this embodiment, the external bus interface 501 includes an internal resource access control circuit 501A.

  The internal resource access control circuit 501A controls access to internal data of the main control unit 41 from an external device via the external bus interface 501, and stores internal data such as a game control program and fixed data stored in the ROM 506, for example. This is a circuit for limiting inappropriate external reading. Here, a circuit analysis device such as an in-circuit emulator (ICE) may be connected to the external bus interface 501 as an external device.

  As an example, according to the contents of the header KHDR stored in the program management area of the ROM 506, it is possible to switch between prohibiting or permitting reading of stored data in the ROM 506. For example, when the header KHDR is bus output mask invalid data, the ROM 506 can be read by an external device, and external reading of internal data is permitted. On the other hand, if the header KHDR is the bus output mask valid data, the ROM 506 can be read from the external device by masking the address bus output, data bus output and control signal output in the external bus interface 501, for example. Is disabled, and external reading of internal data is prohibited. In this case, when reading of internal data is requested from an external device connected to the external bus interface 501, a predetermined fixed value is output so that internal data cannot be read from the external device. . Further, when the header KHDR is ROM read prohibition data, the ROM 506 itself cannot be read, and reading of stored data in the ROM 506 may be prevented. For example, in a ROM at the manufacturing stage, by making the header KHDR ROM read prohibition data, the ROM itself is made unreadable, and if it is a development ROM, bus output mask invalid data is written in the header KHDR, Allows verification of internal data by an external device. On the other hand, in the case of a mass production ROM, the bus output mask valid data is written in the header KHDR so that the CPU 505 and the like can read out the ROM 506 inside the main control unit 41 while the ROM 506 by an external device. It is only necessary to prevent reading of.

  As another example, the internal resource access control circuit 501A has requested that the internal data of the main control unit 41, such as all or part of the stored data in the ROM 506, be read from an external device connected to the external bus interface 501. Is detected. When detecting this read request, the internal resource access control circuit 501A determines whether or not to allow the main control unit 41 to read internal data. For example, it is assumed that all or part of the stored data in the ROM 506 has been encrypted. In this case, if the read request from the external device is a read request for an encryption processing program or key data stored in the ROM 506, the internal resource access control circuit 501A rejects the read request and sets the main control unit 41. Reading of internal data is prohibited. In the external bus interface 501, a switch element is provided between the output port from which data stored in the ROM 506 is output and the internal bus. When the internal resource access control circuit 501 A prohibits reading of the internal data, the switch element May be controlled to be in an off state. As described above, the internal resource access control circuit 501A reads the internal data depending on whether or not the read request from the external device requests reading of predetermined internal data (for example, a predetermined area of the ROM 506). You may make it determine whether it prohibits or permits.

  Alternatively, the internal resource access control circuit 501A may determine whether or not a predetermined authentication code has been input from an external device when detecting a read request for internal data. In this case, for example, a predetermined code pattern serving as an authentication code may be stored in advance in the internal resource access control circuit 501A or in a predetermined area of the ROM 506. When an authentication code is input from the external device, this authentication code is compared with the internally stored authentication code. If they match, a read request is accepted and the main control unit 41 is allowed to read internal data. . On the other hand, if the authentication code input from the external device does not match the authentication code stored internally, the read request is rejected and the internal control unit 41 is prohibited from reading the internal data. As described above, the internal resource access control circuit 501A determines whether to prohibit or permit reading of the internal data depending on whether or not the authentication code input from the external device matches the authentication code stored internally. You may make it do. As a result, it is possible to read out the internal data of the main control unit 41 using a correct authentication code obtained in advance by an inspection organization or the like, and to check the validity of the internal data appropriately. .

  As yet another example, a read prohibition flag is provided in the internal resource access control circuit 501A, and reading of the ROM 506 by an external device is prohibited if the read prohibition flag is on. On the other hand, when the reading prohibition flag is in the off state, reading of the ROM 506 by the external device is permitted. Here, the read prohibition flag is off in the initial state, but once the read prohibition flag is turned on, the read prohibition flag cannot be cleared and returned to the off state. It ’s fine. That is, the read prohibition flag can be irreversibly changed from the off state to the on state. For example, the internal resource access control circuit 501A does not have a function of clearing the read prohibition flag to turn it off, and is set so that the read prohibition flag cannot be cleared by any instruction. Just do it. Then, the internal resource access control circuit 501A determines whether or not the read prohibition flag is on when the external device requests to read the internal data of the main control unit 41 such as the data stored in the ROM 506. At this time, if the read prohibition flag is on, the read request from the external device is rejected and the main controller 41 is prohibited from reading the internal data. On the other hand, if the read prohibition flag is off, the read request from the external device is accepted and the main controller 41 is allowed to read the internal data. With such a configuration, a provider who creates a game control program and stores it in the ROM 506 reads the program that has been debugged from the ROM 506 into an external device while the read prohibition flag is off. Can do. Then, when shipping after the debugging work is completed, by setting the read prohibition flag to the on state, external reading of the ROM 506 can be restricted thereafter, and the ROM 506 by the user of the slot machine 1 or the like can be restricted. Can be prevented from being read. As described above, the internal resource access control circuit 501A may determine whether to prohibit or permit reading of internal data depending on whether an internal flag such as a read prohibition flag is off or on. .

  Note that the read prohibition flag is not set irreversibly but can be changed from the on state to the off state, while the read prohibition flag is changed from the on state to the off state to permit reading of internal data. In this case, the external reading of the ROM 506 may be restricted by erasing the data stored in the ROM 506 (for example, flash erasure).

  The clock circuit 502 provided in the main control unit 41 is a circuit that generates the internal system clock SCLK by, for example, dividing the oscillation signal input to the control external clock terminal EXC by two. In this embodiment, the control clock CCLK generated by the control clock generation circuit 42 is input to the control external clock terminal EXC. The internal system clock SCLK generated by the clock circuit 502 is supplied to various circuits such as the CPU 505 that control the progress of the game in the main control unit 41. The internal system clock SCLK is also supplied to the random number circuit 509 and used to monitor the frequency of the random number clock RCLK supplied from the random number clock generation circuit 43. Further, the internal system clock SCLK may be output from the system clock output terminal CLKO connected to the clock circuit 502 to the outside of the main control unit 41. It is desirable that the internal system clock SCLK is not output to the outside of the main control unit 41. As described above, by limiting the external output of the internal system clock SCLK, it becomes difficult to specify the operation cycle of the internal circuit (such as the CPU 505) of the main control unit 41 from the outside. In the case of updating by this, it is possible to prevent the random number update cycle from being specified externally.

  The unique information storage circuit 503 included in the main control unit 41 is a circuit that stores a plurality of types of unique information serving as internal information of the main control unit 41, for example. As an example, the unique information storage circuit 503 stores three types of unique information such as a ROM code, a chip individual number, and an ID number. The ROM 506 code is a 4-byte numerical value generated from stored data in a predetermined area of the ROM 506, and four numerical values with different generation methods may be prepared. The chip individual number is a 4-byte number assigned at the time of manufacturing the main control unit 41, and indicates a different numerical value for each chip constituting the main control unit 41. The ID number is an 8-byte number assigned when the main control unit 41 is manufactured, and indicates a different numerical value for each chip constituting the main control unit 41. Here, it is sufficient that the chip individual number can be read from the user program while the ID number cannot be read from the user program. The unique information storage circuit 503 may be included in the ROM 506 by using a predetermined area of the ROM 506, for example. Alternatively, the unique information storage circuit 503 may be included in the CPU 505 by using a built-in register of the CPU 505, for example.

  The reset / interrupt controller 504 provided in the main control unit 41 is for controlling various resets and interrupt requests generated inside or outside the main control unit 41. The reset controlled by the reset / interrupt controller 504 includes a system reset and a user reset. The system reset is a reset that occurs when a low level signal (system reset signal) is input to the external system reset terminal XSRST for a certain period. The user reset is performed when a low level signal (user reset signal) is input to the external user reset terminal XURST for a certain period of time, or when a time-out signal of the built-in watchdog timer (WDT) is generated, or when running outside the specified area. This reset is caused by a predetermined factor such as the occurrence of prohibition (IAT). In this embodiment, as described above, since the watchdog timer (WDT) mounted on the reset circuit 49 is used without using the built-in watchdog timer, a user reset signal is input to the external user reset terminal XURST. Alternatively, a user reset occurs when the out-of-designated area travel prohibition (IAT) occurs.

  In this embodiment, as shown in FIG. 5B, a reset circuit 49 incorporating a watchdog timer 49a is mounted on the game control board 40. The reset circuit 49 outputs a system reset signal to the main control unit 41 until the power supplied to the slot machine 1 becomes a stable voltage and a predetermined time elapses. When the watchdog timer 49a times out, a user reset signal is output to the main control unit 41.

  As shown in FIG. 5 (B), in the game control board 40, among the signal lines connected from the LED drive circuit 47 to the credit display unit 11, the drive signals of the plurality of segments constituting the credit display unit 11 are below. The signal line of the 1 digit B segment signal, the lower 1 digit C segment signal, the upper 1 digit B segment signal, and the upper 1 digit C segment signal is branched and connected to the watchdog timer clear signal terminal of the reset circuit 49 via the or circuit. Has been.

  In the present embodiment, the main control unit 41 controls to dynamically light any one of the lower 1 digit B segment, the lower 1 digit C segment, the upper 1 digit B segment, and the upper 1 digit C segment of the credit indicator 11. In order to dynamically light these segments, if the main control unit 41 is operating normally, one of the drive signals of these four segments should be output periodically. It is possible to determine whether or not the main control unit 41 is operating normally by monitoring whether or not the drive signal of any one of the segments is periodically output.

  A signal obtained by combining the drive signals of these four segments through the or circuit is input to the watchdog timer clear signal terminal of the reset circuit 49 so that the built-in counter value of the watchdog timer 49a is cleared. The output of the drive signals of the four segments is stopped, the internal counter value of the watchdog timer 49a is not cleared, and the user reset signal is output to the main control unit 41 by time-up. It has come to be.

  As described above, in this embodiment, the segment signal of the LED to which the drive signal is periodically given is branched to clear the built-in counter value of the watchdog timer 49a, and the CPU 505 of the main control unit 41 individually This is preferable because it is possible to monitor whether the main control unit 41 is operating normally without performing the process of clearing the built-in counter value of the watchdog timer 49a. The built-in counter value of the watchdog timer 49a may be cleared by inputting individual clear signals to the 49 watchdog timer clear signal terminals.

  In the present embodiment, the watchdog timer 49a is mounted on the reset circuit 49 provided outside the main control unit 41, but the main control unit is used by using the watchdog timer built in the main control unit 41. The operation of 41 may be monitored.

  Interrupts controlled by the reset / interrupt controller 504 include a non-maskable interrupt NMI and a maskable interrupt INT. The non-maskable interrupt NMI is an interrupt that is unconditionally accepted even when the CPU 505 is in an interrupt-disabled state. When a low level signal is input to the external non-maskable interrupt terminal XNMI (also used as the input port P4) for a certain period of time. An interrupt that occurs. The maskable interrupt INT is an interrupt that can permit / prohibit acceptance of an interrupt request by a setting instruction of the CPU 505, and multiple interrupts can be executed by setting priority. The maskable interrupt INT is caused by the fact that a low level signal is input to the external maskable interrupt terminal XINT (also used as the input port P3) for a certain period of time, a time-out occurs in the timer circuit included in the CTC 508, Multiple types of interrupt factors are determined in advance, such as the occurrence of an interrupt factor due to data transmission in the serial communication circuit 511 and the occurrence of an interrupt factor due to the acquisition of numerical data as a random value in the random number circuit 509. It only has to be done.

  The reset / interrupt controller 504 includes an interrupt mask register IMR (address 2028H), an interrupt wait monitor register IRR (address 2029H), among the built-in registers provided in the main control unit 41 as shown in FIG. Interrupt control and reset management are performed using the monitor monitor register ISR (address 202AH) and the internal information register CIF (address 208CH). The interrupt mask register IMR is a register that sets what is used and what is not used among maskable interrupts INT caused by a plurality of different factors. The interrupt wait monitor register IRR is a register for confirming the generation state of a maskable interrupt request signal for each maskable interrupt factor set by the interrupt initial setting KIIS. The interrupt monitor register ISR is a register for confirming the processing state of the maskable interrupt request signal for each maskable interrupt factor set by the interrupt initial setting KIIS. The internal information register CIF is a register for managing the reset factor generated immediately before and recording the frequency abnormality of the random number clock RCLK.

  FIG. 11A shows a configuration example of the internal information register CIF. FIG. 11B shows an example of setting contents in each bit of the internal information data stored in the internal information register CIF. The internal information data CIF4 stored in the bit number [4] of the internal information register CIF is a random number clock abnormality instruction indicating the presence or absence of a frequency abnormality in the random number clock RCLK. In the example shown in FIG. 11B, when the frequency abnormality of the random number clock RCLK is not detected, the bit value of the internal information data CIF4 is “0”, whereas when the frequency abnormality is detected, the bit value is “1”. The internal information data CIF2 stored in the bit number [2] of the internal information register CIF is a system reset instruction indicating whether or not the reset factor generated immediately before is a system reset. In the example shown in FIG. 11B, when the immediately preceding reset factor is not a system reset (system reset has not occurred), the bit value of the internal information data CIF2 is “0”, whereas when the system reset is a system reset (system reset) When the reset occurs), the bit value becomes “1”.

  The internal information data CIF1 stored in the bit number [1] of the internal information register CIF is a WDT timeout instruction indicating whether or not the reset factor generated immediately before is a user reset due to a watchdog timer (WDT) timeout. . In the example shown in FIG. 11B, when the immediately preceding reset factor is not a user reset due to a watchdog timer timeout (timeout has not occurred), the bit value of the internal information data CIF1 becomes “0”, while the watchdog When a user reset is caused by a timer timeout (timeout occurs), the bit value becomes “1”. The internal information data CIF0 stored in the bit number [0] of the internal information register CIF is an IAT generation instruction indicating whether or not the reset factor generated immediately before is a user reset due to prohibition of travel outside the designated area (IAT). . In the example shown in FIG. 11B, when the reset factor immediately before is not a user reset due to the occurrence of traveling outside the designated area (no IAT occurrence), the bit value of the internal information data CIF0 becomes “0”, while When the user reset is caused by the occurrence of out-of-area travel (the occurrence of IAT), the bit value becomes “1”.

  The CPU 505 provided in the main control unit 41 executes processing for controlling the progress of the game in the slot machine 1 by executing the program read from the ROM 506. At this time, the CPU 505 reads out fixed data from the ROM 506, the CPU 505 writes various data to the RAM 507 and temporarily stores the data, and the CPU 505 stores various data temporarily stored in the RAM 507. The CPU 505 receives the input of various signals from the outside of the main control unit 41 via the external bus interface 501 or the PIP 510, and the CPU 505 receives the input of various signals via the external bus interface 501 or the serial communication circuit 511. A transmission operation for outputting various signals to the outside of the main control unit 41 is also performed.

  As described above, in the main control unit 41, the CPU 505 executes control according to the program stored in the ROM 506. Therefore, the main control unit 41 (or CPU 505) executes (or performs processing) below. Specifically, the CPU 505 executes control according to a program. The same applies to microcomputers mounted on boards other than the game control board 40.

  A ROM 506 provided in the main control unit 41 stores a user program for game control, fixed data, and the like. The ROM 506 stores a security check program 506A. The CPU 505 reads the security check program 506A stored in the ROM 506 when the main control unit 41 shifts to the security mode in response to the power-on of the slot machine 1 or the occurrence of a system reset, and whether the storage content of the ROM 506 has been changed. Execute security check processing to check whether or not. The security check program 506A may be stored in a built-in memory different from the ROM 506. Further, the security check program 506A may correspond to a security check process for inspecting the storage content of the external memory externally attached to the main control unit 41 via the external bus interface 501, for example.

  A RAM 507 provided in the main control unit 41 provides a work area for game control. Here, at least a part of the RAM 507 may be a backup RAM backed up by a backup power source. That is, even if the power supply to the slot machine is stopped, at least part of the contents of the RAM 507 is stored for a predetermined period. In this embodiment, all areas of the RAM 507 are backup RAMs, and all contents of the RAM 507 are saved for a predetermined period even when power supply to the slot machine is stopped.

  The CTC 508 provided in the main control unit 41 includes, for example, an 8-bit programmable timer built in 3 channels (PTC0 to PTC2), and includes a timer circuit capable of generating a real-time interrupt and measuring time. Each programmable timer PTC0-PTC2 has a timer value that is updated in response to a change in the count clock signal generated based on the internal system clock SCLK (for example, a falling timing that changes from a high level to a low level). If it is good. In addition, the CTC 508 may incorporate, for example, an 8-bit programmable counter with 4 channels (PCC0 to PCC3). Each of the programmable counters PCC0 to PCC3 is only required to have its count value updated in response to a signal change of the internal system clock SCLK or occurrence of a timeout in any of the programmable counters PCC0 to PCC3. The CTC 508 resets the start time of the random number generated by the free run counter used for randomly determining the extension time (variable setting time) for extending the security time for each system reset or the random number circuit 509. A free-run counter or the like that is used to randomly determine each time may be included. Alternatively, these free-run counters may be included in an internal circuit of the main control unit 41 different from the CTC 508 such as a backup area of the RAM 507, for example.

  A random number circuit 509 included in the main control unit 41 is a circuit that generates numerical data that is a random value having a predetermined update range, such as a 16-bit random number. In the present embodiment, on the game control board 40 side, numerical data indicating a random value for internal lottery to be described later is controlled to be countable. In addition, in order to improve a game effect, random numbers other than these may be used. The CPU 505 uses a random counter different from the random number circuit 509 based on the numerical data extracted from the random number circuit 509 to process or update various numerical data by software, thereby indicating numerical data indicating a random value for internal lottery. May be counted. In the following, it is assumed that numerical data indicating random numbers for internal lottery is not processed by software from numerical data extracted by the CPU 505 from the random number circuit 509 serving as hardware. The random number circuit 509 may be incorporated in the main control unit 41 or may be externally attached to the main control unit 41 as a random number circuit chip different from the main control unit 41. .

  The random number for internal lottery is a value used to determine whether or not to allow a plurality of types of winnings, and takes a value in the range of “0” to “65535” in this embodiment.

  FIG. 12 is a block diagram illustrating a configuration example of the random number circuit 509. As shown in FIG. 12, the random number circuit 509 includes a frequency monitoring circuit 551, a clock flip-flop 552, a random number generation circuit 553, a start value setting circuit 554, a random number sequence change circuit 555, a random number sequence change setting circuit 556, and a latch flip-flop. 557A, 557B, random number latch selectors 558A, 558B, and random number value registers 559A, 559B. Note that the random value register 559A and the random value register 559B are respectively a random value register R1D (address 2038H-2039H) and a random value register R2D (address) included in the built-in register of the main control unit 41 as shown in FIG. 203AH-203BH). In this embodiment, the random numbers to be acquired are only random numbers for internal lottery, and among the latch flip-flops 557A, 557B, the random number latch selectors 558A, 558B, and the random number registers 559A, 559B, the latch flip-flop 557B, The random number latch selector 558B and the random number value register 559B are unused.

  The frequency monitoring circuit 551 is a circuit for monitoring the frequency of the random number clock RCLK generated by the random number clock generating circuit 43 and detecting the occurrence of an abnormality. For example, the frequency monitoring circuit 551 monitors an oscillation signal input to the random number external clock terminal ERC, and sets the contents of the bit number [7-6] of the security time setting KSES based on the internal system clock SCLK (FIG. 10B When the frequency abnormality according to the reference) is detected, the bit number [4] of the internal information register CIF is set to “1”. In this embodiment, the random number clock RCLK generated by the random number clock generation circuit 43 is input to the random number external clock terminal ERC.

  The clock flip-flop 552 is configured using, for example, a D-type flip-flop, and the random number clock RCLK from the random number external clock terminal ERC is input to the clock terminal CK. Further, in the clock flip-flop 552, the negative phase output terminal (inverted output terminal) Q bar is connected to the D input terminal. The random number update clock RGK is output from the positive phase output terminal (non-inverted output terminal) Q, while the latch clock RC0 is output from the negative phase output terminal (inverted output terminal) Q bar. In this case, when the signal state of the random number clock RCLK input to the clock terminal CK changes a predetermined state, the clock flip-flop 552 has a positive phase output terminal (non-inverted output terminal) Q and a negative phase output terminal ( Inverted output terminal) Changes the signal state in the output signal from the Q bar. For example, the clock flip-flop 552 has a rising timing at which the signal state of the random number clock RCLK changes from a low level to a high level, or a rising edge at which the signal state of the random number clock RCLK changes from a high level to a low level. The input signal at the D input terminal is captured at any one of the falling timings. At this time, from the positive phase output terminal (non-inverted output terminal) Q, the input signal captured at the D input terminal is output without being inverted, while the negative phase output terminal (inverted output terminal) Q bar is output. From the input signal captured by the D input terminal is inverted and output. Thus, the random number update clock RGK having an oscillation frequency (for example, 10 MHz) that is ½ of the oscillation frequency (for example, 20 MHz) of the random number clock RCLK from the positive phase output terminal (non-inverted output terminal) Q of the clock flip-flop 552. Is output from the negative phase output terminal (inverted output terminal) Q bar, that is, the reverse phase signal (inverted signal) of the random number update clock RGK, that is, the same frequency as the random number update clock RGK and the phase of the random number update clock RGK is π. A different latch clock RC0 is output by (= 180 °).

  The random number update clock RGK output from the clock flip-flop 552 is input to the clock terminal of the random number generation circuit 553 and used for incrementing the count value in the random number generation circuit 553. The latch clock RC0 output from the clock flip-flop 552 is branched into the latch clock RC1 and the latch clock RC2 at the branch point BR1. Therefore, the latch clock RC1 and the latch clock RC2 have the same oscillation frequency, and the signal state changes with a common cycle. Here, changes in the signal state in the latch clock RC1 and the latch clock RC2 include, for example, a rise that changes from a low level to a high level and a fall that changes from a high level to a low level. The latch clock RC1 is input to the clock terminal CK of the latch flip-flop 557A and becomes a random number acquisition clock used to generate the latch signal SL1 at the start of the game.

  The oscillation frequency of the random number clock RCLK and the oscillation frequency of the control clock CCLK generated by the control clock generation circuit 42 are different from each other, and one of the oscillation frequencies is the other oscillation frequency. It is never an integer multiple of. As an example, while the oscillation frequency of the control clock CCLK is 11.0 MHz, the oscillation frequency of the random number clock RCLK may be 9.7 MHz. Therefore, both the random number update clock RGK and the latch clocks RC1 and RC2 are oscillation signals whose signal states change at a different period from the control clock CCLK supplied to the CPU 505. That is, the clock flip-flop 552 is based on the random number clock RCLK generated by the random number clock generation circuit 43, and the random number update clock RGK for updating the count value, or the latch clock that is used as a plurality of random number acquisition clocks. As RC1 and RC2, oscillation signals whose signal states change with a period different from the control clock CCLK and the internal system clock SCLK (the control clock CCLK divided by two) are generated.

  The random number generation circuit 553 is composed of, for example, a 16-bit counter and the like, and based on an input such as a random number update clock RGK output from the clock flip-flop 552, a predetermined initial value within a predetermined range in which numerical data can be updated. It is a circuit that cyclically updates to a predetermined final value. For example, the random number generation circuit 553 responds to the rising edge of the random number update clock RGK, which is an input signal to a predetermined clock terminal, from the initial value set within the range from “0” to “65535” to “65535”. The numerical data is counted up so that one is added at a time. Then, after counting up to “65535”, the numerical data is updated cyclically by counting up from “0” to a numerical value that becomes a final value that is 1 smaller than the initial value.

  The start value setting circuit 554 sets the start value in the count value generated by the random number generation circuit 553 in accordance with the bit value (see FIG. 9B) in the bit number [1-0] of the second random number initial setting KRS2. Set. For example, the start value setting circuit 554 sets the start value to the default value “0000H” if the bit number [1-0] of the second random number initial setting KRS2 is “00”, and if it is “10”. The value is set based on the ID number. If “01”, the value is changed every time the system is reset. In this embodiment, the bit number [1-0] of the second random number initial setting KRS2 is set to “10”, and a value based on the ID number is set as the start value in the count value generated by the random number generation circuit 553. Is done.

  The random number sequence change circuit 555 is a circuit that allows the permutation, which is the update order of the numerical data, to be changed to a permutation that conforms to a predetermined random number update rule when the numerical data generated by the random number generation circuit 553 makes a round. For example, the random number sequence change circuit 555 executes bit scramble processing such as bit replacement or transposition in numerical data output from the random number generation circuit 553. The random number sequence change circuit 555 can change the permutation, which is the update order of the numerical data, by changing the bit scramble key or the bit scramble table used for the bit scramble process, for example.

  The random number sequence change setting circuit 556 determines the update order of numerical data in the random number sequence change circuit 555 according to the bit value (see FIG. 9A) in the bit number [1-0] of the first random number initial setting KRS1. It is a circuit for performing the setting to change. For example, if the bit number [1-0] of the first random number initial setting KRS1 is “00”, the random number sequence change setting circuit 556 sets the random number update rule not to change after the second round, while “01” If so, the random number update rule is changed in response to a change request by software after the second round, and if it is “10”, the random number update rule is automatically changed. In the present embodiment, the bit number [1-0] of the first random number initial setting KRS1 is set to “10”, and the random number update rule is automatically changed.

  When the random number update circuit 555 changes the random number update rule by software in response to the bit number [1-0] of the first random number initial setting KRS1 being “01”, FIG. Of the built-in registers included in the main controller 41 as shown, the random number update rule RDSC (address 2034H) is used to control the change of the random number update rule. FIG. 13A shows a configuration example of the random number sequence change register RDSC. FIG. 13B shows an example of setting contents in each bit of random number sequence change request data stored in the random number sequence change register RDSC. The random number sequence change request data RDSC0 stored in the bit number [0] of the random number sequence change register RDSC indicates the presence / absence of a random number sequence change request when the random number update rule is changed by software. In the example shown in FIG. 13B, when the random number sequence change request is not made by software, the bit value of the random number sequence change request data RDSC0 is “0”. The bit value is “1”.

  FIG. 14 shows an operation example when the random number update rule is changed by software. In this case, when the count value permutation RCN output from the random number generation circuit 553 is cyclically updated from a predetermined initial value to a predetermined final value, the response is that the random number sequence change request data RDSC0 is “1”. Then, change the random number update rule. In the operation example shown in FIG. 14, the random number sequence RSN output from the random number sequence change circuit 555 is “0 → 1 →... → 65535”. Thereafter, it is assumed that “1” is written to the bit number [0] of the random number sequence change register RDSC at a predetermined timing by the CPU 505 executing the user program stored in the ROM 506.

  In response to the bit number [1-0] of the first random number initial setting KRS1 being “01”, the random number sequence change setting circuit 556 reads the random number sequence change request data RDSC0 and the bit value is “1”. In response to "," a setting for changing the random number update rule is made. At this time, the random number sequence change setting circuit 556, according to the count value permutation RCN output from the random number generation circuit 553 reaching a predetermined final value, for example, any one of a plurality of types of random number update rules prepared in advance. The random number update rule is changed, for example, by selecting. In the operation example shown in FIG. 14, the random number sequence change circuit 555 outputs numerical data “65535” corresponding to the final value in the count value permutation RCN output from the random number generation circuit 553, and then responds to the random number sequence change request data RDSC0. Change the random number update rule. Thereafter, the random number sequence change circuit 555 outputs “65535 → 65534 →... → 0” as the random number sequence RSN according to the changed random number update rule. The random number sequence change register RDSC is initialized when the random number sequence change setting circuit 556 reads the random number sequence change request data RDSC0. Therefore, until the bit value “1” is written to the bit number [0] of the random number sequence change register RDSC again, the random number sequence RSN output from the random number sequence change circuit 555 is “65535 → 65534 →... → 0”. Become.

  When the CPU 505 writes the bit value “1” again to the bit number [0] of the random number sequence change register RDSC, the random number update rule is changed again. In the operation example shown in FIG. 14, when the random number sequence change circuit 555 outputs the numerical data “0” corresponding to the final value in the random number sequence RSN, the bit value “1” is written as the random number sequence change request data RDSC0. Change the random number update rule accordingly. Thereafter, the random number sequence changing circuit 555 outputs “0 → 2 →... → 65534 → 1 →... → 65535” as the random number sequence RSN according to the changed random number update rule.

  FIG. 15 shows an operation example when the random number update rule is automatically changed. In this case, in response to the count value permutation RCN output from the random number generation circuit 553 being cyclically updated from a predetermined initial value to a predetermined final value, the random number sequence change setting circuit 556 automatically changes the random number update rule. To change. In the operation example shown in FIG. 15, the random number sequence RSN output from the random number sequence change circuit 555 first is “0 → 1 →... → 65535”.

  When the random number sequence RSN output from the random number sequence change circuit 555 reaches a predetermined final value, the random number sequence change setting circuit 556 has a predetermined order from among a plurality of types of update rules prepared in advance. The update rule may be changed by selecting the update rule according to the above. Alternatively, the random number sequence change setting circuit 556 may change the update rule by selecting an arbitrary update rule from among a plurality of types of update rules. In the operation example shown in FIG. 15, the random number sequence RSN output from the random number sequence change circuit 555 becomes “65535 → 65534 →. Thereafter, due to the second change in the random number update rule, the random number sequence RSN output from the random number sequence change circuit 555 becomes “0 → 2 →... → 65534 → 1 →. In the operation example illustrated in FIG. 15, the random number sequence RSN output from the random number sequence change circuit 555 is “65534 → 0 →... → 32768” due to the third change in the random number update rule. When the fourth random number update rule change is performed, the random number sequence RSN output from the random number sequence change circuit 555 becomes “16383 → 49151 →... → 49150”. When the fifth random number update rule change is performed, the random number sequence RSN output from the random number sequence change circuit 555 becomes “4 → 3 →... → 465553”.

  The latch flip-flop 557A is configured using, for example, a D-type flip-flop. In the latch flip-flop 557A, a wiring from the input port P0 included in the PIP 510 is connected to the D input terminal, and a wiring for transmitting the latch clock RC1 is connected to the clock terminal CK. In this embodiment, the game start signal SS1 from the start switch 7 is input to the input port P0. The latch flip-flop 557A takes in the game start signal SS1 in response to the rising edge of the latch clock RC1, and outputs it as the game start latch signal SL1. Thus, in the latch flip-flop 557A, the game start signal SS1 is output as the game start latch signal SL1 in synchronization with the rising edge of the latch clock RC1.

The game start signal SS1 is not limited to that transmitted directly from the start switch 7. As an example, a timer circuit is provided that measures the time during which the output signal from the start switch 7 is on and outputs a game start signal SS1 when the measured time reaches a predetermined time (for example, 3 ms). May be.

  The random number latch selector 558A is a circuit that takes in the game start latch signal SL1 transmitted from the latch flip-flop 557A and the software random number latch request signal, and selectively outputs either one as the random number latch signal LL1. The random number latch selector 558A controls the output of the random number latch signal LL1 by using a random value fetch register RDLT (address 2032H) among the built-in registers provided in the main control unit 41 as shown in FIG. 7B. The random value acquisition register RDLT is a register used to acquire numerical data in the random number sequence RSN output from the random number sequence change circuit 555 into the random value register 559A by software. The random number latch selection register RDLS has a method of taking in the numerical data in the random number sequence RSN output from the random number sequence changing circuit 555 into the random value register 559A by software or by inputting a signal to the input port P0. It is a register to show.

  FIG. 16A shows a configuration example of the random value fetch register RDLT. FIG. 16B shows an example of the setting contents in each bit of the random number acquisition specification data stored in the random value acquisition register RDLT. The random value acquisition specification data RDLT0 stored in the bit number [0] of the random value acquisition register RDLT indicates whether or not a random value acquisition specification is given to the random value register 559A serving as the random value register R1D. In the example shown in FIG. 16B, when there is no specification of random number acquisition to the random number register R1D by software, the bit value of the random value acquisition specification data RDLT0 is “0”, while the random value acquisition is not performed. The bit value is “1” when an instruction is included.

  FIG. 17A shows a configuration example of the random number latch selection register RDLS. FIG. 17B shows an example of setting contents in each bit of random number latch selection data stored in the random number latch selection register RDLS. The random number latch selection data RDLS0 stored in the bit number [0] of the random number latch selection register RDLS indicates a method of taking in the random number value register 559A serving as the random number value register R1D. In the example shown in FIG. 17B, the bit value of the random number latch selection data RDLS0 is “ 0 ”. On the other hand, when the numerical value data to be a random number value is taken into the random value register R1D in response to the signal input to the input port P0, the bit value of the random number latch selection data RDLS0 is set to “1”. In this embodiment, the bit value of the random number latch selection data RDLS0 is “1”, and numerical data that becomes a random number value is taken into the random value register R1D in response to a signal input to the input port P0.

  The random value register 559A is a register that stores numerical data in the random number sequence RSN output from the random number sequence change circuit 555 as a random value. 18A and 18B show a configuration example of a random value register 559A serving as the random value register R1D. 18A shows the lower byte R1D (L) of the random value register R1D, and FIG. 18B shows the upper byte R1D (H) of the random value register R1D. The random value register 559A is a 16-bit (2-byte) register, and can store a 16-bit random value.

  The random value register 559A takes in the numerical data in the random number sequence RSN output from the random number sequence change circuit 555 as a random value in response to the random number latch signal LL1 supplied from the random number latch selector 558A being turned on. Store with. When the register read signal RRS1 supplied from the CPU 505 is turned on, the random value register 559A is in a readable (enable) state and outputs stored numerical data to an internal bus or the like. On the other hand, when the register read signal RRS1 is in the OFF state, the same value (for example, “65535H” or the like) is always output, and the reading is disabled (disabled). Further, the random value register 559A may be in a state in which the register read signal RRS1 cannot be received when the random number latch signal LL1 is in the ON state. Further, the random value register 559A may be in a state in which the random number latch signal LL1 cannot be received when the register read signal RRS1 is in the on state before the random number latch signal LL1 is in the on state. good.

  The random value register 559A uses a random number latch flag register RDFM (address 2033H) and a random number interrupt control register RDIC (address 2031H) among the built-in registers provided in the main control unit 41 as shown in FIG. 7B. This enables operation management and interrupt control when latching random numbers. The random number latch flag register RDFM is a register that stores a random number latch flag indicating whether or not numerical data serving as a random number value is latched corresponding to the random value register 559A. The random number interrupt control register RDIC is a register that sets permission / prohibition of an interrupt that occurs when numerical data that becomes a random number value is latched in the random number value register 559A.

  FIG. 19A shows a configuration example of the random number latch flag register RDFM. FIG. 19B shows an example of setting contents in each bit of the random number latch flag data stored in the random number latch flag register RDFM. The random number latch flag data RDFM0 stored in the bit number [0] of the random number latch flag register RDFM is a random number latch flag indicating whether or not numerical data has been taken into the random number value register 559A serving as the random number value register R1D. In the example shown in FIG. 19B, when the numerical value data is not taken into the random value register R1D (no random value is taken), the bit value of the random number latch flag data RDFM0 becomes “0”, while the numerical data Is taken (with random number fetching), the bit value becomes “1”. In the state where the random number latch flag data RDFM0 is “1”, that is, in the state where the numerical data is captured in the random value register R1D, the new numerical data is stored in the random value register even when a new random number capturing request is generated. In such a state, the numerical data in the random value register R1D is read and new numerical data is captured in the random value register R1D until the random number latch flag data RDFM0 is cleared. It becomes impossible.

  FIG. 20A shows a configuration example of the random number interrupt control register RDIC. FIG. 20B shows an example of setting contents in each bit of random number interrupt control data stored in the random number interrupt control register RDIC. The random number interrupt control data RDIC0 stored in the bit number [0] of the random number interrupt control register RDIC allows an interrupt to be generated when numerical data is fetched into the random value register 559A serving as the random value register R1D. This shows the interrupt control setting to enable or disable. In the example shown in FIG. 20B, when interrupting at the time of fetching into the random value register R1D is prohibited (interrupt prohibited), the bit value of the random number interrupt control data RDIC0 is set to “0”, When this interrupt is permitted (interrupt permitted), the bit value is set to “1”. In the present embodiment, the bit value of the random number interrupt control data RDIC0 is set to “0”, and no interrupt is generated even if numerical data is fetched into the random value register 559A serving as the random value register R1D.

  The PIP 510 included in the main control unit 41 is, for example, a 6-bit input dedicated port, and includes an input port P0 to an input port P2 serving as a dedicated terminal and an input port P3 serving as a function shared terminal and an input port P5. . The input port P3 is also used as an external maskable interrupt terminal XINT connected to the CPU 505 or the like. The input port P4 is also used as an external non-maskable interrupt terminal XNMI connected to the CPU 505 or the like. The input port P5 is also used as the first channel reception terminal RXA used by the serial communication circuit 511. The use setting of the input port P3 to the input port P5 is instructed by the function setting KFCS stored in the program management area.

  The PIP 510 manages the state of the input port P0 to the input port P5 using the input port register PI (address 2090H) among the built-in registers included in the main control unit 41 as shown in FIG. 7B. The input port register PI is a register that stores a bit value indicating the input state of the external signal corresponding to each of the input port P0 to the input port P5.

  FIG. 21A shows a configuration example of the input port register PI. FIG. 21B shows an example of setting contents in each bit of the input port data stored in the input port register PI. The input port data PI5 stored in the bit number [5] of the input port register PI indicates the terminal state (ON / OFF) at the input port P5 that is also used as the first channel receiving terminal RXA. The input port data PI4 stored in the bit number [4] of the input port register PI indicates the terminal state (ON / OFF) at the input port P4 that is also used as the external non-maskable interrupt terminal XNMI. The input port data PI3 stored in the bit number [3] of the input port register PI indicates the terminal state (ON / OFF) at the input port P3 that is also used as the external maskable interrupt terminal XINT. The input port data PI2 stored in the bit number [2] of the input port register PI indicates the terminal state (ON / OFF) at the input port P2. The input port data PI1 stored in the bit number [1] of the input port register PI indicates the terminal state (ON / OFF) at the input port P1. The input port data PI0 stored in the bit number [0] of the input port register PI indicates the terminal state (ON / OFF) at the input port P0.

  An address decoding circuit 512 provided in the main control unit 41 shown in FIG. 5 is a circuit for decoding each functional block in the main control unit 41 and a chip select signal that is a decoding signal for an external device. . By the chip select signal, an internal circuit of the main control unit 41 or an external device as a peripheral device is selectively operated effectively and can be accessed from the CPU 505.

  The ROM 506 provided in the main control unit 41 stores various selection data and table data used for controlling the progress of the game, in addition to the game control user program and the security check program 506A. For example, the ROM 506 stores data constituting a plurality of determination tables, determination tables, setting tables, and the like prepared for the CPU 505 to perform various determinations, determinations, and settings. The ROM 506 stores table data constituting a plurality of command tables used for the CPU 505 to transmit control signals serving as various control commands from the game control board 40.

  The RAM 507 provided in the main control unit 41 is provided with a game control data holding area 590 as an area for holding various data used for controlling the progress of the game in the slot machine 1. For example, a DRAM is used as the RAM 507, and a refresh operation is required to maintain the stored data contents. The CPU 505 has a built-in refresh register for performing this refresh operation. For example, the refresh register consists of 8 bits, and the lower 7 bits are automatically incremented each time the CPU 505 fetches an instruction from the ROM 506. Accordingly, the stored value in the refresh register is updated every execution time of one instruction in the CPU 505.

  The main control unit 41 transmits various commands to the sub control unit 91 via the serial communication circuit 511. A command transmitted from the main control unit 41 to the sub control unit 91 is sent in only one direction, and no command is sent from the sub control unit 91 toward the main control unit 41.

  As illustrated in FIG. 22, the serial communication circuit 511 includes a data register 560, a transmission data register 561, a transmission shift register 562, and a status register 563.

  The data register 560 is a register for temporarily buffering command data generated by the CPU 505 and transferred via the internal bus. The command data buffered in the data register 560 is stored in an empty area of the transmission data register 561. The

  The transmission data register 561 is a register that stores command data waiting for transmission. The transmission data register 561 is provided with an area capable of storing a plurality of command data, and can store a maximum of 32 bytes of command data.

  The transmission shift register 562 is a register for storing command data converted into serial data. The command data stored at the earliest stage among the command data stored in the transmission data register 561 is converted into serial data. And stored in the transmission shift register 562. When the command data is stored in the transmission shift register 562, the command data is immediately transferred to the sub-control unit 91.

  The status register 563 stores data indicating the transmission state of the serial communication circuit 511, such as transmission completion indicating whether or not command data is being transmitted, and data empty indicating whether or not command data is stored in the transmission data register 561. Register. When “1” is stored as the value of transmission completion, it indicates that the command data has not been transmitted or the transmission of command data has been completed, and when “0” is stored, Indicates that command data is being transmitted or is waiting for command data transmission. When “1” is set as the data empty value, it indicates that one or more command data waiting for transmission is stored in the transmission data register 561, and when “0” is stored. The transmission data register 561 indicates that command data waiting for transmission is not stored.

  The value of the status register 563 can be referred to by the CPU 505 via the internal bus, and the CPU 505 can check the transmission state of the serial communication circuit 511 by reading the value of the status register 563.

  Next, the operation status of the serial communication circuit 511 will be described with reference to FIG.

  First, when all the areas of the transmission data register 561 are in an empty state and no command data is transmitted by the transmission shift register 562, as shown in FIG. Both empty values are set to “1”.

  As shown in FIG. 23B, when the command data 1 and 2 are stored in the transmission data register 561 according to the transfer instruction of the CPU 505, both the transmission completion and data empty values change to “0”.

  Next, as shown in FIGS. 23C and 23D, the command data 1 stored first among the command data 1 and 2 stored in the transmission data register 561 is converted into serial data, and the transmission shift register 562 is converted. When the transmission of the command data 1 is completed, the next stored command data 2 is converted into serial data and transmitted to the sub control unit 91 by the transmission shift register 562. At the same time, the last command data is converted into serial data and stored in the transmission shift register 562. When the transmission data register 561 becomes empty, the value of the data empty changes to “1”, as shown in FIG. Thus, when the transmission of the last command data stored in the transmission shift register 562 is also completed, Completion value also changes to "1", a state in which transmission is completed for all the command data.

  The main control unit 41 receives the detection state of various switches connected to the game control board 40 from the input port. Then, the main control unit 41 executes basic processing that shifts in stages according to the detection states of various switches input from these input ports.

  Further, the main control unit 41 can execute an interrupt process by interrupting the basic process when an interrupt occurs. In the present embodiment, a timer interrupt process (main), which will be described later, is executed at a certain time interval (about 0.56 ms in the present embodiment) when a timeout occurs in the timer circuit included in the CTC 508.

  The main control unit 41 is set to prohibit other interrupts during the execution of the interrupt process, and when a plurality of interrupts occur at the same time, the main control unit 41 prioritizes according to a predetermined order. An interrupt to be executed is set. If another interrupt factor occurs during the execution of the interrupt process and the interrupt factor continues even after the interrupt process is completed, a new interrupt will occur at that point. It will be.

  The main control unit 41 repeatedly loops the process according to the control state until the detection state of the various switches connected to the game control board 40 changes as a basic process, and changes the detection state of the various switches. Execute a process that moves in stages. Further, the main control unit 41 executes a timer interrupt process (main) at regular time intervals (about 0.56 ms in this embodiment). In addition, the execution interval of the timer interrupt process (main) is set to a time longer than the sum of the time required to complete the repeated process according to the control state in the basic process and the execution time of the timer interrupt process (main) Therefore, the process that is repeated according to the control state between the current and next timer interrupt processes (main) is completed at least once.

  The effect control board 90 is connected to effect devices such as a liquid crystal display 51 (see FIG. 1), an effect LED 52, speakers 53 and 54, and the reel LED 55 described above, which are arranged on the front door 1b of the slot machine 1. These effect devices are driven based on control by a later-described sub-control unit 91 mounted on the effect control board 90.

  In this embodiment, the sub-control unit 91 mounted on the effect control board 90 controls the output of the effect devices such as the liquid crystal display 51, effect effect LED 52, speakers 53 and 54, and reel LED 55. However, in addition to the sub-control unit 91, an output control unit that directly controls the output of the effect device is mounted on the effect control board 90 or another board, and the sub-control unit 91 is based on a command from the main control unit 41. The output control unit may determine the output pattern of the effect device, and the output control unit may control the output of the effect device based on the output pattern determined by the sub control unit 91. In such a configuration, the sub control unit 91 and the output control may be performed. The output control of the rendering device is performed by both of the units.

  Further, in the present embodiment, the liquid crystal display 51, the effect effect LED 52, the speakers 53 and 54, and the reel LED 55 are exemplified as the effect device, but the effect device is not limited to these, for example, a mechanically driven display. A device or a mechanically driven item may be applied as the effect device.

  The effect control board 90 is composed of a microcomputer including a sub CPU 91a, ROM 91b, RAM 91c, I / O port 91d, etc., and a liquid crystal display connected to the sub control unit 91 for effect control and the effect control board 90. Display control circuit 92 for performing display control of the device 51, LED drive circuit 93 for performing drive control of the effect LED 52 and reel LED 55, an audio output circuit 94 for controlling audio output from the speakers 53 and 54, at power-on or power-off A reset circuit 95 that sometimes gives a reset signal to the sub CPU 91a, a clock device 97 that outputs time information including date information and time information, and a power supply voltage supplied to the slot machine 1 are monitored, and when a voltage drop is detected, A power interruption detection circuit 98 that outputs a voltage drop signal indicating that to the sub-control unit 91 is mounted. In response to the command transmitted from the main control unit, the sub-control unit 91 performs various controls for performing an effect, and directly or indirectly controls each part of the control circuit mounted on the effect control board 90. Control.

  The reset circuit 95 has a lower voltage for releasing the reset signal than the reset circuit 49 that gives the system reset signal to the main control unit 41 in the game control board 40. When the power is turned on, the sub control unit 91 It starts at an earlier stage than the unit 41. On the other hand, the power interruption detection circuit 98 has a voltage that outputs a voltage drop signal lower than the power interruption detection circuit 48 that outputs a voltage drop signal to the main control unit 41 in the game control board 40. The sub control unit 91 detects a power failure at a later stage than the main control unit 41, and performs a power interruption process (sub) described later.

  Similar to the main control unit 41, the sub control unit 91 has an interrupt function, generates an interrupt when receiving a command from the main control unit 41, and acquires a command transmitted from the main control unit 41. Execute command reception interrupt processing to be stored in the buffer. Further, the sub control unit 91 executes an interrupt process (sub), which will be described later, by generating an interrupt every time the number of input system clocks reaches a certain number, that is, every certain interval.

  Also, unlike the main control unit 41, the sub control unit 91 interrupts the process even when the timer interrupt process (sub) is being executed when an interrupt is generated based on the reception of the command. The command reception interrupt process is executed at the same time, and the command reception interrupt process is executed with the highest priority even if interrupts that trigger the timer interrupt process (sub) occur at the same time.

  The sub-control unit 91 is also supplied with backup power at the time of a power failure, and the data stored in the RAM 91c is held while the backup power is supplied.

  The slot machine 1 according to the present embodiment outputs an external output signal indicating a gaming state, an error occurrence state, and the like.

  As shown in FIG. 24, these external output signals are output from the game control board 40 under the control of the CPU 505 of the main control unit 41, and provide information on the game store (hall) where the external output board 1000 and the slot machine 1 are installed. The signal is output to a hall device such as a hall computer via a terminal board 1010.

  From the game control board 40 to the external output board 1000, a medal IN signal indicating the number of medals used for setting the number of bets, a medal OUT signal indicating the number of medals given to the player due to the occurrence of a winning, a gaming state RB signal indicating that RB is described later, a BB signal indicating that the gaming state is BB described later, a door opening signal indicating that the front door 1b is open, and a setting change mode described later. A setting change signal indicating that the medals are in error, an insertion error signal indicating an abnormality in the medal selector, and a payout error signal indicating an abnormality in the hopper unit 34 are output.

  In this embodiment, there is no challenge time (a gaming state in which the number of sliding pieces on the reel is limited, but winning is allowed for all small roles) or a challenge bonus with a high probability of challenge time. However, in order to make common with the slot machines equipped with these gaming states, in addition to the signal lines for outputting the above signals, the gaming state is a challenge between the gaming control board 40 and the external output board 1000. A signal line for outputting a CT signal indicating that the time is in progress and a CB signal indicating that the gaming state is in the challenge bonus is connected, and a signal line for error output that may be expanded in the future is connected. Has been.

  The external output board 1000 is provided with a relay circuit 1001, a parallel / serial conversion circuit 1002, a terminal for each output signal, and a connector 1003 to be electrically connected to the circuit of the information providing terminal board 1010. ing.

  Of the signals output from the game control board 40, the medal IN signal, medal OUT signal, RB signal, BB signal, (CT signal, CB signal) are directly used as pulse signals via the relay circuit 1001. The information is output to the information providing terminal board 1010.

  On the other hand, a door opening signal, a setting change signal, a closing error signal, a payout error signal, and a (preliminary signal) are security signals that are serial signals that can be individually identified by the parallel / serial conversion circuit 1002. And output to the information providing terminal board 1010.

  The medal IN signal, medal OUT signal, RB signal, BB signal, (CT signal, CB signal) output from the external output board 1000 are output to the hall device via the information providing terminal board 1010. . On the other hand, the security signal output from the external output board 1000 is again converted into a door opening signal, a setting change signal, a closing error signal, a payout error signal, and a spare signal at the information providing terminal board 1010 and output to the hall device. Will be.

  The external output signal includes a door opening signal, a setting change signal, a closing error signal, and a dispensing error signal, but these door opening signal, setting changing signal, closing error signal, and dispensing error signal are not frequently output signals. Therefore, it is not necessary to provide an external output terminal for each of these signals.

  For this reason, in this embodiment, the external output signal output from the game control board 40 as described above is output to the hall device via the external output board 1000, and the door opening signal and setting among these external output signals are set. The change signal, input error signal, and payout error signal are converted into security signals, which are serial signals that can be individually identified, by the parallel / serial conversion circuit 1002 mounted on the external output board 1000, and output to the outside. Thus, it is possible to output the door opening signal, the setting change signal, the closing error signal, and the dispensing error signal from one terminal, and it is not necessary to provide more terminals than necessary.

  In addition, even if there is a spare signal line that is not currently used but may be used in the future, individual signals can be identified with a single terminal, including the signal output from the spare signal line. It is possible to output as much as possible, and a spare signal line terminal that is not used does not become an empty terminal.

  In this embodiment, the door opening signal, the setting change signal, the making error signal, and the paying error signal are serially identifiable by the parallel / serial conversion circuit 1002 mounted on the external output board 1000. It is converted to a security signal, which is a signal, and output to the outside. For example, any one of a door opening signal, a setting change signal, a closing error signal, and a paying error signal is output by an AND circuit or the like. In such a case, an error signal may be output to the outside through a single terminal. Even in this case, either an error has occurred in the external device, the door is open, or the setting is being changed. Therefore, it is possible to specify that the terminal is being generated, and it is not necessary to provide more terminals than necessary. In this case, since a plurality of signals can be output to the outside with one terminal without being converted into a serial signal, the manufacturing cost can be reduced.

  In the slot machine 1 of this embodiment, the medal payout rate changes according to the set value. Specifically, the medal payout rate is changed by using a winning probability corresponding to a set value in an internal lottery described later. The set value is composed of 6 levels of 1 to 6, with 6 being the highest payout rate and the payout rate being lower as the value is decreased in the order of 5, 4, 3, 2, 1. That is, when 6 is set as the set value, the advantage is highest for the player, and as the value decreases in order of 5, 4, 3, 2, 1, the advantage decreases stepwise.

  In order to change the setting value, it is necessary to turn on the power of the slot machine 1 after the setting key switch 37 is turned on. When the setting key switch 37 is turned on and the power is turned on, the setting value read from the RAM 507 is displayed on the setting value display 24 as a display value, and the setting value can be changed by operating the reset / setting switch 38. Transition to the setting change state. When the reset / setting switch 38 is operated in the setting change state, the display value displayed on the setting value display 24 is updated one by one (when further operation is performed from the setting 6, the display returns to the setting 1). . When the start switch 7 is operated, the display value is determined as the set value. Then, when the setting key switch 37 is turned off, the determined display value (setting value) is stored in the RAM 507 of the main control unit 41, and the state shifts to a state in which the game can proceed.

  In order to check the set value, after the game is over, the setting key switch 37 may be turned on in a state where the bet amount is not set. When the setting key switch 37 is turned on in such a situation, the setting value read out from the RAM 507 is displayed on the setting value display 24, thereby shifting to a setting confirmation state in which the setting value can be confirmed. In the setting confirmation state, the game cannot be progressed, and by setting the setting key switch 37 to the off state, the setting confirmation state is ended and the state in which the game can proceed is returned.

  In the slot machine 1 of the present embodiment, the main control unit 41 determines whether or not the voltage drop signal from the power interruption detection circuit 48 is detected every time the timer interruption process (main) is executed. If the determination process is performed and it is determined that the voltage drop signal is detected in the power failure determination process, the power interruption process (main) is executed. In the power interruption process (main), the register is saved in a stack of a RAM 507, which will be described later, and destructive diagnosis data (in this embodiment, 5AH) in which any bit is 1 is stored in the RAM 507, that is, specific data other than 0 is stored. In addition to the storage, the RAM parity adjustment data is calculated so that the RAM parity based on the data stored in all areas of the RAM 507 becomes 0 and stored in the RAM 507. The RAM parity is a value calculated as an exclusive OR of the values stored in each bit of the corresponding area (all areas in this embodiment) of the RAM 507. For this reason, if the RAM parity based on the data stored in all areas of the RAM 507 is 0, the RAM parity adjustment data is 0, and the RAM parity based on the data stored in all areas of the RAM 507 is 1. In this case, the RAM parity adjustment data is 1.

  The main control unit 41 calculates the RAM parity based on the data stored in all areas of the RAM 507 at the time of activation, regardless of whether the system reset or the user reset, and the value of the data for destructive diagnosis And the processing state of the main control unit 41 is restored to the state before the power interruption based on the data stored in the RAM 507 on the condition that the RAM parity is 0 and the value of the data for destruction diagnosis is also correct. However, if the RAM parity is not 0 (in the case of 1) or the value of the destruction diagnosis data is not correct, it is determined that the RAM is abnormal, and the RAM abnormal error code is set in the register to control the RAM abnormal error state. However, the progress of the game is disabled. Unlike the normal error state, the RAM abnormal error state is not canceled even if the reset switch 23 or the reset / setting switch 38 is operated, and a new set value is set in the above-described setting change state. It will not be released until

  In this embodiment, all data stored in the RAM 507 is held by the backup power source even in the event of a power failure, and the main control unit 41 determines that the data in the RAM 507 is normal when the power is turned on. In addition, the configuration is such that the control state before power interruption is restored based on the data stored in the RAM 507. However, only the data stored in the RAM 507 that is necessary for returning to the control state in the event of a power failure is backed up and turned on. It may be configured to return to the control state before power interruption based on the data backed up at the time.

  In addition, when returning to the control state before the power interruption when the power is turned on, it is not necessary to return all the control states to the control state before the power interruption, and the minimum control state that does not disadvantage the player For example, it is not necessary to restore the state of all input ports to the state before power interruption.

  The sub control unit 91 also determines whether or not the voltage drop signal from the power interruption detection circuit 98 is detected in the timer interrupt process (sub), and if it is determined that the voltage drop signal is detected, Disconnection processing (sub) is executed. In the power interruption process (sub), the register is saved in a stack of a RAM 91c, which will be described later, and destructive diagnosis data in which any bit is 1 is stored in the RAM 91c, and also based on data stored in all areas of the RAM 91c. The RAM parity adjustment data is calculated so that the RAM parity becomes 0 and stored in the RAM 91c.

  Then, the sub-control unit 91 calculates the RAM parity based on the data stored in all the areas of the RAM 91c at the time of activation, and sets the data stored in the RAM 91c on the condition that the RAM parity is 0. Based on this, the processing state of the sub-control unit 91 is restored to the state before the power interruption, but when the RAM parity is not 0 (in the case of 1), it is determined that the RAM is abnormal and the RAM 91c is initialized. . In this case, unlike the main control unit 41, only the RAM 91c is initialized, and the performance is not disabled.

  In this embodiment, all data stored in the RAM 91c is held by the backup power supply even in the event of a power failure, and the sub-control unit 91 determines that the data in the RAM 91c is normal when the power is turned on. In addition, the configuration is such that the control state before power interruption is restored based on the data stored in the RAM 91c, but only the data required to return to the control state during a power failure is backed up among the data stored in the RAM 91c and the power is turned on. It may be configured to return to the control state before power interruption based on the data backed up at the time.

  In addition, when returning to the control state before the power interruption when the power is turned on, it is not necessary to return all the control states to the control state before the power interruption, and the minimum control state that does not disadvantage the player It is not necessary to restore the state of the input port or the progress in the middle of the production when it is interrupted.

  Next, initialization of the RAM 507 of the main control unit 41 will be described. The storage area of the RAM 507 of the main control unit 41 is divided into an important work, a general work, a special work, a set value work, a non-saved work, a non-initialized area, an unused area, and a stack area.

  The important work is a work in which data which is inconvenient if it is initialized at the end of the BB, such as various display devices, LED display data, I / O input / output data, and game time counter. The general work is a work that stores data that can be initialized at the end of the BB, such as a stop control table, a stop symbol, the number of medals paid out, and the total number of medals paid out in the BB. The special work is a work that stores data such as various software random numbers that are initialized only before the setting is started. The unsaved work is a work that holds the state of various switches, and a value is always set regardless of whether or not the data in the RAM 507 is destroyed at the time of activation. The uninitialized work is a work that stores data that is not initialized even when a RAM error or setting is changed. The non-initialized work further includes a set value work for storing a set value used when a lottery is performed in the internal lottery process, and a command buffer (in the command buffer) in which a command transmitted to the effect control board 90 is temporarily stored. This command is maintained until the next command is stored, so the last transmitted command is always stored), so that the medal IN signal, medal OUT signal, and RB output to the external output board 1000 are stored. Of the medium signal, BB signal, door open signal, setting change signal, input error signal, and payout error signal, the door open signal, setting change signal, input error signal, and payout constituting the security signal output from the external output board 1000 A security work for storing the output state (on / off state) of the error signal is assigned. The unused area is an unused area in the storage area of the RAM 507, and is initialized if any one of a plurality of initialization conditions described later is satisfied. The stack area is an area in which data saved from the register of the main control unit 41 is stored, and the unused stack area is one of a plurality of initialization conditions to be described later, like the unused area. However, if it is established, it will be initialized, but the in-use stack area is not initialized because the program continues.

  In this embodiment, the main control unit 41 stores the data in the RAM 507 when the setting key switch 37 is turned on, when a RAM error occurs, when the BB ends, and when the setting key switch 37 is turned off. When not being destroyed, when five initialization conditions at the end of one game are satisfied, four types of initializations that are initialized in accordance with each initialization condition are performed.

  Initialization 1 is an initialization performed when the setting key switch 37 is turned on at the time of startup and transitions to a setting change state, or initialization performed when a RAM abnormality error occurs. In the storage area of the RAM 507, all areas (including the unused area and the unused stack area) other than the used stack area and the non-initialized area are initialized. Initialization 2 is initialization performed at the end of the BB. In initialization 2, a general work, an unused area, and an unused stack area are initialized in the storage area of the RAM 507. Initialization 3 is an initialization performed when the setting key switch 37 is in an off state at the time of startup and the data in the RAM 507 is not destroyed. In the initialization 3, the unsaved work, the unused area, and the The used stack area is initialized. Initialization 4 is initialization performed at the end of one game. In initialization 4, an unused area and an unused stack area in the storage area of the RAM 507 are initialized.

  In this embodiment, initialization 1 is performed before the change of the setting change state. However, the initialization 1 is performed at the end of the setting change state, or both before the change of the setting change state and at the end of the setting change state. Also good.

  As described above, in this embodiment, when a RAM abnormality error occurs at the time of power-on or the like, initialization 1 is executed and the control state before that is initialized. The data stored in the command buffer, setting value work, and security work allocated to the data area is not initialized but is retained. At this time, the command buffer has the command sent last when the RAM abnormality error occurred, the set value work has the set value when the RAM abnormal error occurs, and the security work has the door when the RAM abnormal error occurs. Since the output status of the release signal, setting change signal, input error signal, and payout error signal is held in a stored state, whether any error command is transmitted from these data when a RAM error occurs, It is possible to specify whether the value has not been changed, the output state of the door open signal, setting change signal, input error signal, and payout error signal, and the cause of the RAM abnormality can be specified Furthermore, it is possible to identify the possibility that some kind of fraud has been performed.

  Furthermore, in order to eliminate the RAM abnormality error, the uninitialized area is not initialized even if the setting value is changed, and the stored data in the uninitialized area is intentionally initialized. Since it is impossible, even if a RAM abnormality error occurs due to fraud, the stored data of the command buffer, setting value work, and security work can be left as a trace.

  In the slot machine 1 according to the present embodiment, as described above, the specified number of bets that can be set according to the gaming state is determined, and the specified number of bets determined according to the gaming state is set. It becomes possible to start the game on the condition. In the present embodiment, all the pay lines L1 to L5 are activated when a specified number of bets corresponding to the gaming state are set.

  In the slot machine 1 of this embodiment, when all the reels 2L, 2C, 2R are stopped, the activated pay line (in the present embodiment, all the pay lines are always enabled. The activated winning line is simply referred to as a winning line). When a combination of symbols called a combination is arranged on the winning line, a winning is achieved. The combination may be a combination of the same symbols or a combination including different symbols. The type of winning combination is determined according to the game state, but it can be roughly divided into a small role with payout of medals and a replay that can start the next game without the need to set the number of bets. There are a game combination and a special combination with a transition to a game state advantageous to the player. Below, a small role and a re-playing role are collectively called a general role. In order to win each winning combination determined according to the game state, it is necessary to win an internal lottery described later and set a winning flag for the winning combination in the RAM 507.

  Of the winning flags for each of these combinations, the winning flag for the small role and the re-playing role is valid only in the game in which the flag is set, and is invalid in the next game. It is valid until a combination of combinations permitted by the flag is completed, and is invalid in a game having a combination of combinations permitted. In other words, once the special combination winning flag is won, even if the combination of the combinations permitted by the flag cannot be made, the winning flag is not invalidated and is carried over to the next game. It becomes.

  As the role in the slot machine 1, as shown in FIG. 25, as a special role, big bonuses (1) to (3) (hereinafter, big bonuses (1) to (3) are changed to BB (1) to (3). Yes), a regular bonus (hereinafter referred to as a regular bonus RB) is defined as one small role, watermelon, cherry, and bell are defined as replay roles (1) to (3).

  Cherry is awarded when the symbol “white cherry” is derived on any of the winning lines for the right reel in any gaming state, and one medal is paid out in any gaming state. In addition, when the symbol of “white cherry” stops at the upper or lower stage of the right reel, the combination of cherries is aligned on the two winning lines of the winning lines L2, L5 or the winning lines L3, L4. Since winning a cherry on the winning line, two medals will be paid out.

  A watermelon is awarded when a combination of “Watermelon-Watermelon-Watermelon” or “Watermelon-Watermelon-BAR” is aligned on any of the winning lines in any gaming state. Medals are paid out, and 12 medals are paid out in a gaming state other than RB. One coin is awarded when the combination of “Bell-Net 7-Net 7” is aligned on any of the winning lines in any gaming state, and one medal is paid out in any gaming state. In any gaming state, the bell is awarded when a combination of “bell-bell-bell” is arranged on any of the winning lines, and 15 medals are paid out in the RB. Then 10 medals are paid out.

  Replay (1) is a combination of “Replay-Replay-Replay”, “BAR-Replay-Replay”, or “Black 7-Replay-Replay” in any of the winning lines in a gaming state other than RB to be described later. A prize is awarded when any of the combinations is completed. Replay (2) is awarded when a combination of “watermelon-replay-replay” is arranged on any of the winning lines in a gaming state other than RB, which will be described later. Replay (3) is awarded when a combination of “black cherry-replay-replay” is arranged on any of the winning lines in a gaming state other than RB, which will be described later. When replays (1) to (3) win, there is no payout of medals, but the next game can be started again without setting the number of bets, so 3 corresponding to the number of bets that need not be set in the next game. This is essentially the same as a medal being paid out.

  The RB is awarded when a combination of “net 7-net 7-black 7” is aligned on any of the winning lines in a gaming state other than RB, which will be described later, and the gaming state shifts to RB. The RB is a gaming state that is advantageous to the player over other gaming states by increasing the winning probability of the small role, particularly the bell, and when the 12 games are digested after the RB starts, or when an 8-game winning ( When the type of a combination is allowed), it ends either whichever comes first.

  BB (1) is awarded when a combination of “black 7-black 7-black 7” is aligned on any of the winning lines in a gaming state other than RB. BB (2) wins when a combination of “network 7-network 7-network 7” is aligned on any of the winning lines in a gaming state other than RB. BB (3) is awarded when a combination of “white 7-white 7-white 7” is aligned on any of the winning lines in a gaming state other than RB.

  If any one of BB (1), BB (2), and BB (3) wins, the gaming state shifts to BB and simultaneously shifts to RB. When RB ends, BB ends. If not, the process proceeds to RB again, and is controlled to RB repeatedly until BB ends. That is, during BB, it is always controlled to RB. Then, BB (1) or BB (2) ends when the total number of medals paid out to the player in the BB exceeds 465, and BB (3) is paid out to the player in the BB. The process ends when the total number of medals exceeds 300. At the end of the BB, the RB is also ended regardless of whether or not the RB end condition is satisfied.

  In the present embodiment, the gaming state is controlled to one of the normal gaming state, RT (1), RT (2), RT (3), RT (4), RB. As shown, depending on whether the gaming state is a normal gaming state, RT (1), RT (2), RT (3), RT (4), or RB. The combination and combination of combinations that are subject to lottery are different. Further, in the normal gaming state where the gaming state is RT (4), the combination of the combination and combination that is the subject of the internal lottery varies depending on whether or not the special combination is being carried over.

  When the gaming state is the normal gaming state or RT (1) and no special role is carried over, BB (1), BB (1) + Replay A (Replay (1)), BB (1) + Watermelon A (Watermelon), BB (1) + Watermelon B (Watermelon + 1 sheet), BB (1) + Cherry, BB (1) + Bell, BB (2), BB (2) + Replay A, BB (2) + Replay B (replay (2) + replay (1)), BB (2) + replay C (replay (3) + replay (1)), BB (2) + watermelon A, BB (2) + watermelon B, BB (2) + Cherry, BB (2) + Bell, BB (3), BB (3) + Replay A, BB (3) + Replay B, BB (3) + Replay C, BB (3) + Watermelon A , BB (3) + Watermelon B, BB (3) + Cherry, BB (3) + Bell, RB, RB Replay A, RB + watermelon A, RB + watermelon B, RB + cherry, RB + Bell, Replay A, Replay B, replay C, watermelon A, watermelon B, cherry, bell are sequentially read as a target combination of the internal lottery.

  When the gaming state is the normal gaming state and any special role is carried over, Replay A, Replay B, Replay C, Watermelon A, Watermelon B, Cherry, and Bell are sequentially read out as the internal lottery target roles. .

  When the gaming state is RT (2), BB (1), BB (1) + Replay A, BB (1) + Watermelon A, BB (1) + Watermelon B, BB (1) + Cherry, BB (1) + Bell, BB (2), BB (2) + Replay A, BB (2) + Replay B, BB (2) + Replay C, BB (2) + Watermelon A, BB (2) + Watermelon B, BB (2 ) + Cherry, BB (2) + Bell, BB (3), BB (3) + Replay A, BB (3) + Replay B, BB (3) + Replay C, BB (3) + Watermelon A, BB ( 3) + Watermelon B, BB (3) + Cherry, BB (3) + Bell, RB, RB + Replay A, RB + Watermelon A, RB + Watermelon B, RB + Cherry, RB + Bell, Replay A, Replay C, Watermelon A, Watermelon B, cherry, and bell are sequentially read out as the subject combination of the internal lottery.

  When the gaming state is RT (3), BB (1), BB (1) + Replay A, BB (1) + Watermelon A, BB (1) + Watermelon B, BB (1) + Cherry, BB (1) + Bell, BB (2), BB (2) + Replay A, BB (2) + Replay B, BB (2) + Replay C, BB (2) + Watermelon A, BB (2) + Watermelon B, BB (2 ) + Cherry, BB (2) + Bell, BB (3), BB (3) + Replay A, BB (3) + Replay B, BB (3) + Replay C, BB (3) + Watermelon A, BB ( 3) + Watermelon B, BB (3) + Cherry, BB (3) + Bell, RB, RB + Replay A, RB + Watermelon A, RB + Watermelon B, RB + Cherry, RB + Bell, Replay A, Watermelon A, Watermelon B, Cherry The bells are sequentially read out as the target combination of the internal lottery.

  When the gaming state is RT (4) and no special role is carried over, BB (1), BB (1) + Replay A, BB (1) + Watermelon A, BB (1) + Watermelon B , BB (1) + Cherry, BB (1) + Bell, BB (2), BB (2) + Replay A, BB (2) + Replay B, BB (2) + Replay C, BB (2) + Watermelon A, BB (2) + Watermelon B, BB (2) + Cherry, BB (2) + Bell, BB (3), BB (3) + Replay A, BB (3) + Replay B, BB (3) + Replay C, BB (3) + Watermelon A, BB (3) + Watermelon B, BB (3) + Cherry, BB (3) + Bell, RB, RB + Replay A, RB + Watermelon A, RB + Watermelon B, RB + Cherry, RB + Bell, Replay A, Watermelon A, Watermelon B, Cherry, Bell It is read out in the order as the target role.

  When the gaming state is RT (4) and any special role is carried over, Replay A, Replay B, Replay C, Watermelon A, Watermelon B, Cherry, and Bell are sequentially read out as the internal lottery target roles. It is.

  When the gaming state is RB, watermelon A, watermelon B, cherry, and bell are sequentially read out as the subject combination of the internal lottery.

  In the internal lottery, the combination or combination of roles that are the targets of the internal lottery, the number of judgment values determined according to the current gaming state and set value are sequentially added to the random number for internal lottery, and the result of the addition overflows It is determined that the winning combination or combination of winning combinations is won. For this reason, a combination or combination of combinations is won with a probability (number of determination values / 65536) according to the size of the number of determination values.

  When a winning combination of any combination or combination of combinations is determined, a winning flag corresponding to the combination of combinations or combinations determined to be winning is set in the internal winning flag storing work assigned to the RAM 41c. The internal winning flag storage work consists of a 2-byte storage area, of which the upper byte is assigned as the special role storing work in which the winning flag for the special role is set, and the lower byte is the winning of the general role It is assigned as a general role storage work for which a flag is set. Specifically, when a special combination is won, a special combination winning flag indicating that the special combination is won is set in the special combination storing work, and the winning flag set in the general combination storing work is cleared. If a special role + general role is won, a special role winning flag indicating that the special role has been won is set in the special role storage work, and a general role win indicating that the general role has been won. Set the flag in the general role storage work. When a general combination is won, a winning flag for the general combination indicating that the general combination is won is set in the general combination storing work. If no winning combination is selected, only the general winning combination work is cleared.

  Next, stop control of the reels 2L, 2C, 2R will be described.

When one of the stop switches 8L, 8C, and 8R corresponding to the rotating reel is effectively detected, the main control unit 41 stores the table index and table creation data stored in the ROM 506. , The stop position is specified, and control is performed to stop the rotation of the reels 2L, 2C, and 2R corresponding to the operated stop switches 8L, 8C, and 8R at the specified stop position.

  In the table index, an index that indicates the start address of the area in which the data for table creation is stored, from the reference address when referring to the table index, according to the setting state of the winning flag by internal lottery (hereinafter referred to as the internal winning state) Differences up to the address where the data is stored are registered. As a result, a difference corresponding to the internal winning state is acquired, and the corresponding index data can be acquired by adding the difference to the reference address. Even when the winning combinations are different, when the same control is applied, the same address is stored as the index data. In such a case, the same table creation data is referred to. Thus, a stop control table is created.

  The table creation data includes the number of sliding symbols according to the stop operation position, a stop table indicating whether or not each stop position can be stopped, the number of sliding symbols to be referred to according to the reel stop status, or the address of the stop table.

  The number of sliding frames or stop table referenced according to the reel stop status is whether all reels are rotating, only the left reel is stopped, only the middle reel is stopped, or only the right reel is stopped Depending on whether the left and middle reels are stopped, the left and right reels are stopped, the middle and right reels are stopped, and any one of the reels is stopped May differ depending on the stop position of a stopped reel. For each situation, the address of the stop control table to be referenced is registered for each rotating reel, and is based on the top address of the table creation data. Thus, the number of sliding frames to be referred to or the address of the stop table can be specified according to each situation. And to be able to identify the sliding frame number or stop table required in accordance with the respective circumstances. If the same stop control table is applied, even if the reel stop status and the stopped reel stop position are different, the same address is registered as the number of sliding frames or the address of the stop table. In such a case, the same sliding frame number or stop table is referred to.

  In this embodiment, as shown in FIG. 3, stepping motors that make one turn at a cycle of 168 steps (0 to 167) are used for the reel motors 32L, 32C, and 32R. That is, when the reel motors 32L, 32C, and 32R are driven for 168 steps, the reels 2L, 2C, and 2R make one round. Then, 21 areas (frames) divided every 16 steps (the number of steps that one symbol moves) are defined for one reel, and these areas are areas 0 to 20 from the reel reference position. A number is assigned. On the other hand, the number of symbols arranged on one reel is 21, and symbol numbers 0 to 20 from the reel reference position are assigned to symbols on each reel, so symbols 0 to 20 are assigned to each reel. , Area numbers 0 to 20 are assigned in order.

  As shown in FIG. 27, the number of sliding frames is a value indicating the amount of movement from the stop operation position that is the area number where the stop operation is performed to the area number that is the stop position.

As shown in FIG. 28, the stop table is data indicating whether or not stopping is possible for each area number as a stop position, and 1 is stored corresponding to the area number that can be stopped. 0 is stored for the area number. As will be described later, the number of sliding frames can be stored in only 3 sliding frames per byte even after compression, whereas the stop table only requires a storage capacity of 1 bit for each area number. Data of up to 8 areas can be stored in 1 byte, and the data capacity is significantly smaller than the number of sliding frames.

  In this embodiment, only the left reel that is rotating all reels is controlled to stop the reel using the number of sliding frames, and in other situations, control is performed to stop the reel using a stop table. . For this reason, the number of sliding frames is also determined for each winning combination only for the left reel while all reels are rotating. For other situations, the stop table is determined according to the winning combination and the status of the reels that have been stopped. It has been.

  Next, when the main control unit 41 effectively detects any one of the stop switches 8L, 8C, and 8R corresponding to the rotating reel, the control when the display result is derived to the corresponding reel is described. To explain, when any operation corresponding to the rotating reel is detected effectively among the stop switches 8L, 8C, 8R, the stop operation position is based on the number of steps from the reel reference position when the stop operation is detected. Specify the region number.

  When stop control is performed using the number of sliding symbols, the number of sliding symbols stored corresponding to the winning combination and the stop operation position is acquired, and the reel is rotated and stopped by the acquired number of sliding symbols. Take control. Specifically, from the number of steps from the reel reference position at the time when the stop operation is detected, the number of steps from the acquired number of sliding frames to the stop is calculated, and the reel is rotated and stopped by the calculated number of steps. Take control. As a result, the area corresponding to the area number that is the stop position ahead of the number of sliding frames from the area corresponding to the area number of the stop operation position where the stop operation is detected is the stop reference position (in this embodiment, the perspective window 3 It will stop in the lower symbol area).

  On the other hand, when stop control is performed using a stop table, if there is a winning combination and a reel that has already been stopped, the corresponding stop table is acquired based on the stop position and moved from the area number of the stop operation position. A position that can be stopped in the direction is searched, the number of sliding symbols up to the first specified stopping position is calculated, and the reel is rotated by the calculated number of sliding frames and stopped. Specifically, from the number of steps from the reel reference position at the time when the stop operation is detected, the number of steps from the calculated number of sliding frames to the stop is calculated, and the reel is rotated and stopped by the calculated number of steps. Take control. As a result, the area corresponding to the area number that is the stop position that can be stopped closest to the area corresponding to the area number of the stop operation position where the stop operation is detected stops at the stop reference position.

  In this embodiment, as described above, the number of sliding frames is determined only for the left reel when the left reel is in the first stop, and corresponds to three different winning combinations as shown in FIGS. Compressed data in which the number of sliding frames of the same area number is compressed to 1 byte is stored for each area number. The 21-byte compressed data corresponding to the area numbers 0 to 20 is stored in consecutive address areas as a sliding frame number table.

  As shown in FIG. 29, stop data selection values of 0 to 11 are determined for the winning combination in the internal lottery, and among these, the lost, cherry, and watermelon A wins corresponding to the stop data selection values 0 to 2 are determined. The number of sliding frames is stored in the sliding frame number table 0, and the number of sliding frames when winning the watermelon B, bell, and replay A corresponding to the stop data selection values 3 to 5 is stored in the sliding frame number table 1, and the stop data Replay B, Replay C, and BB (1) corresponding to the selection values 6 to 8 are stored in the sliding frame number table 2, and BB (2) corresponding to the stop data selection values 9 to 11 are stored. The number of sliding frames at the time of winning BB (3) and RB is stored in the sliding frame number table 3. In the present embodiment, the number of sliding symbols corresponding to the general combination is used when the BB or RB and the general combination are simultaneously selected or when the general combination is won while the BB or RB is being carried over.

  The sliding frame number table corresponding to the winning combination of the internal lottery and the use data position in the sliding frame number table can be obtained by calculating from the stop data selection value. The storage address can be obtained by calculating from the area number of the stop operation position.

  Specifically, as shown in FIG. 30 (1), the number of the sliding frame number table to be used can be acquired by dividing the stop data selection value of the winning combination by 3, and the remainder is acquired as the use data position. can do. For example, in the case of the watermelon B, that is, the stop data selection value 2, 2 ÷ 3 = 0 remainder 2, and the number of sliding frames at the use data position 2 in the sliding frame number table 0 may be referred to.

  Next, as shown in FIG. 30 (2), the storage address of the use data on the sliding frame number table to be used is obtained by adding the area number of the stop operation position to the head address of the corresponding sliding frame number table. Can be acquired. For example, if the reference address “add” and the stop operation position are “20”, “add + 20” is the storage address of the use data.

  The number of sliding frames is a value from 0 to 4 as will be described later, and if it is stored normally, a 3-bit storage area is required, and only two sliding frames can be stored in one byte. 27, three use data positions 2, 1, 0 are assigned to the three sliding frame numbers, and among these, a value obtained by multiplying the number of sliding frames corresponding to the use data position 2 by 32; By adding the value obtained by multiplying the number of sliding frames corresponding to the use data position 1 by 5 and the number of sliding frames corresponding to the use data position 0, the calculation is performed on these three numbers of sliding frames. Compressed and stored so that it fits in 1 byte.

  As shown in FIG. 30 (3), the data compressed to 1 byte can be obtained by dividing by 32 to obtain the number of sliding frames at use data position 2, and the remainder obtained by dividing by 32 is further increased by 5. By dividing the number, the number of sliding frames at the use data position 1 can be obtained, and by dividing the remainder divided by 32 by 5, the remainder can be obtained as the number of sliding frames at the use data 0.

  A method of compressing and storing a plurality of sliding frame number data has been conventionally used. However, in the conventional method, the number of sliding frames corresponding to a plurality of changing reels applied to the same winning combination is used. Since these are compressed and stored, when the number of sliding frames is not used for all reels among a plurality of reels that are changing as in this embodiment, the number of sliding frames is not stored. As a result, there is a problem that the number of sliding frames cannot be efficiently compressed.

  In contrast, in this embodiment, the number of sliding frames corresponding to a plurality of different winning combinations by internal lottery is compressed and stored. The stop control is performed using the number of sliding frames only for the reels of the part, but for other reels the stop control is performed without using the number of sliding frames. When there is no need to specify, it is possible to efficiently compress and store a plurality of sliding frames, and to save the storage capacity of the ROM 506 for storing the number of sliding frames.

  In the present embodiment, the number of sliding symbols for a plurality of winning combinations is stored in the same order in the data constituting the sliding frame number table, and the stop data selection value is determined corresponding to the winning combination. By simply dividing the stop data selection value by the number of sliding frames stored in one sliding frame number table, the number of the sliding frame number table storing the number of sliding frames corresponding to the winning combination, the sliding frame number table It is possible to specify both the use data position indicating which position of the sliding frame to be used is to be used. That is, the storage position of the number of sliding frames can be specified only by performing a simple calculation on the stop data selection value. Then, it is possible to easily specify the target number of sliding frames only by performing a calculation according to the storage position (usage data position) of the specified number of sliding frames.

  Further, in this embodiment, when all the reels are rotating, the number of sliding frames is determined only for the left reel, and the number of sliding frames is not determined for the middle reel and the right reel. A stop table that requires a small amount of data is defined, and the stop positions of the reels when the stop operation is performed in the recommended stop order (in this embodiment, the stop order in which the left reel is the first stop) are diversified. In addition, the data capacity related to the stop control can be reduced. On the other hand, although the stop position becomes monotonous except in the recommended stop order, there are few opportunities for the stop operation to be performed in the recommended stop order, and the influence thereof is also small.

  In the present embodiment, only one address is stored as index data corresponding to one internal winning state in one gaming state in the table index, and one table creation data includes one table data. Only one address is stored as the number of sliding frames corresponding to the stop status of the reel (and the stop position of the stopped reel) or the address of the storage area of the stop table. That is, the table creation data corresponding to one internal winning state in one gaming state and the number of sliding symbols or the stop table corresponding to the reel stop status (and the stop position of the stopped reel) are uniquely determined. Yes. Therefore, when all of the gaming state, the internal winning state, and the reel stop status (and the stop position of the stopped reel) are the same, the same number of sliding symbols or stop tables, that is, the same control pattern Based on this, reel stop control is performed.

  Further, in this embodiment, a value of 0 to 4 is determined as the number of sliding frames, and a stoptable position is determined so that the number of sliding frames is in a range of 0 to 4 for the stop table, After detecting the stop operation, the reel can be stopped by drawing a maximum of 4 frame symbols. In other words, the stop position of the symbol can be designated from a range of a maximum of 5 frames including the stop operation position where the stop operation is detected. In addition, since it is necessary to move one frame to move the reel for one symbol, it is possible to stop the reel by pulling in a maximum of four symbols after detecting the stop operation. The symbol stop position can be designated from a range of up to five symbols including the operation position.

  In this embodiment, if any of the winning combinations is won, when the stop operation is performed, the winning combination can be stopped on the winning line within a drawing range of up to four frames. If possible, control is performed to stop all of them, and the winning combination is controlled to be stopped within a maximum of 4 frames.

  When a special role and a small role are elected at the same time, such as when a special role is elected while the special role has been carried over from before the previous game, the maximum on the winning line when the stop operation is performed If it is possible to align and stop the winning small roles in the 4-frame draw range, control them to align them and stop them, and draw the selected small roles in the draw range of up to 4 frames on the winning line. If it is not possible to do so, if the winning combination can be stopped by aligning the special roles that have been selected in the drawing range of a maximum of 4 frames, the control is performed to stop them. Controls to stop and stop within the drawing range of the frame. That is, in such a case, priority is given to the control for aligning the small combination on the winning line over the special combination, and the special combination can be won only when the small combination cannot be drawn. When a special combination and a small combination can be withdrawn at the same time, only the small combination is drawn in, and the small combination is not aligned on the winning line at the same time as the special combination.

  In this example, when a special role is elected while the special role has been carried over from before the previous game, or when a special role and a small role are simultaneously elected, the special role and the small role are won simultaneously. If the selected special role is given priority over the selected special role, the special role is controlled on the winning line only when the small role cannot be withdrawn. When winning simultaneously, priority is given to the control for aligning the special role on the winning line over the small role, and the control for aligning the small role on the winning line may be performed only when the special role cannot be drawn.

  If a special player and a replaying player are elected at the same time, such as when a replaying player is elected while the special role has been carried over from before the previous game, when the stop operation is performed, In addition, the control for stopping the game by aligning the symbols of the re-gamer within a maximum of 4 frames. In this case, the symbols constituting the re-gamer or the symbols constituting the re-gamer to be simultaneously elected are arranged at intervals of 5 symbols or less, that is, within 4 frames, for any of the reels 2L, 2C, and 2R. Since it can always be stopped at any position within the 4-frame pull-in range, if the special combination and the re-playing combination are elected at the same time, the timing of the operation of the stop switches 8L, 8C, 8R by the player Without fail, the re-playing role will always be won. That is, in such a case, the control for aligning the re-games on the winning line has priority over the special game, and the re-games will always win. In the case where the special combination and the re-playing combination can be withdrawn at the same time, only the re-playing combination is drawn in and the special combination is not arranged on the winning line simultaneously with the re-playing combination.

  In this embodiment, after the rotation of the reels 2L, 2C, and 2R is started, the main control unit 41 rotates the reels for which the stop operation has not been detected yet until the operation of the stop switches 8L, 8C, and 8R is detected. Continuously, on the condition that the operation of the stop switches 8L, 8C, and 8R is detected, control is performed to stop the display result on the corresponding reel. Even if the reel rotation temporarily stops due to the occurrence of a reel rotation error, the stop operation is still detected until the operation of the stop switches 8L, 8C, and 8R is detected after the reel rotation is restarted. Control is performed to stop the display result of the corresponding reels on the condition that the rotation of the reels that have not been continued is continued and the operation of the stop switches 8L, 8C, and 8R is detected.

  In this embodiment, control is performed to stop the display result on the corresponding reel on condition that the operation of the stop switches 8L, 8C, and 8R is detected. However, the rotation of the reel is started. When a predetermined automatic stop time has elapsed, even if the reel stop operation is not performed, it is assumed that the stop operation has been performed, and automatic stop control is performed to automatically stop each reel. May be. In this case, since the reels are stopped without the player's operation, it is preferable to derive a display result that does not constitute any combination even if any combination is won.

  Next, various control contents executed by the main control unit 41 in the present embodiment will be described below with reference to FIGS.

  When the system reset signal is input from the reset circuit 49, the main control unit 41 performs the startup process (main) shown in the flowchart of FIG. When a user reset signal is input, the process starts from the step Sa2 of the startup process (main). That is, while starting from the security mode in which the security check process is performed only in the case of activation upon power-on, the user program stored in the ROM 506 is executed by omitting the security check process in the case of activation due to the time-up of the watchdog timer 49a. It starts from the user mode to execute.

  In the startup process (main) accompanying the input of the system reset signal, first, the CPU 505 executes the security check process shown in FIG. 32 based on the security check program 506A read from the ROM 506 (Sa1). At this time, the main control unit 41 enters the security mode, and the game control user program stored in the ROM 506 is not yet executed.

  In the security check process, as shown in FIG. 32, first, a process for determining a time (security time) for controlling to the security mode is executed. At this time, the CPU 505 reads the bit value in the bit number [2-0] of the security time setting KSES stored in the program management area of the ROM 506 (Sa101). Then, it is determined whether or not the read value is “000” (Sa102).

  If the read value is determined to be “000” in Sa102, the steady set time is set to a predetermined fixed time (Sa103). Here, the steady setting time is a constant time component of the security time regardless of the number of executions of the security check process based on the occurrence of a system reset or the like (the number of times the main control unit 41 enters the security mode). The fixed time is an invariant time component determined in advance based on the specification of the main control unit 41 in the security time, and may be a minimum value that can be set as the security time, for example.

  If it is determined in Sa102 that the read value is other than “000”, the extension time selected according to the setting contents shown in FIG. The time is set (Sa104). In this way, when the bit value in the bit number [2-0] of the security time setting KSES is a value other than “000”, the security time as the execution time of the security check process can be selected in advance in addition to the fixed time. It can be set to any one of a plurality of extension times.

  After executing one of the processes of Sa103 and Sa104, the bit value in the bit number [4-3] of the security time setting KSES is read (Sa105). Then, it is determined whether or not the read value is “00” (Sa106).

  If the read value is determined to be “00” in Sa106, the steady setting time is set as the security time (Sa107). On the other hand, if it is determined that the read value is other than “00”, the variable set time determined corresponding to the read value is added to the steady set time and set as the security time (Sa108). . Here, the variable setting time is a time component that changes every time the security check process is executed, and the bit value in the bit number [4-3] of the security time setting KSES is “01” (short). Mode) or “10” (long mode), and changes in different predetermined time ranges. For example, when the count value in a predetermined free-run counter is stored in the variable security time register built in the main control unit 41 when the system reset occurs, the variable security time register is stored in the processing of Sa108. By using the value as it is, or by using the value obtained by substituting the stored value for a predetermined arithmetic function (for example, a hash function), the variable set time is random within a predetermined time range at each system reset. What is necessary is just to be determined so that it may change. Thus, when the bit value in the bit number [4-3] of the security time setting KSES is a value other than “00”, the security time that is the execution time of the security check process is set as the security based on the occurrence of the system reset or the like. Each time the check process is executed, it can be changed within a predetermined time range.

  Here, the bit value in the bit number [2-0] of the security time setting KSES is a value other than “000”, and the bit value in the bit number [4-3] of the security time setting KSES is other than “00”. In this case, the security time is determined by adding both the extension time set in step Sa104 and the variable setting time set in step Sa108 to the fixed time. become.

  After executing one of the processes of Sa107 and Sa108, the security code stored in the predetermined area of the ROM 506 is read (Sa109). Here, in a predetermined area of the ROM 506, a security code of a calculation result obtained by calculating the data of the stored content by a predetermined calculation formula is stored in advance. As a security code generation method, for example, a hash value is generated using a hash function, an error detection code (CRC code) is used, or an error correction code (ECC code) is used. A generation method may be used. In a predetermined area different from the security code storage area of the ROM 506, an arithmetic expression for specifying the security code by calculation is encrypted and stored in advance.

  Following the processing of step Sa109, the encrypted arithmetic expression is decrypted and restored (Sa110). Thereafter, the storage code in the predetermined area of the ROM 506 is calculated by the arithmetic expression decrypted in Sa110 to specify the security code (Sa111). At this time, the storage data used for the calculation for specifying the security code is, for example, program data corresponding to all or part of the user program different from the security check program 506A among the storage data of the ROM 506, or predetermined table data May be all or a part of the fixed data constituting the. Then, the security code read in Sa109 is compared with the security code specified in Sa111 (Sa112). At this time, it is determined whether or not the security codes match in the comparison result (Sa113).

  If the security codes do not match at Sa113, it is determined that an unauthorized change has been made to the ROM 506, and the operation of the CPU 505 is shifted to the halt state (HALT). On the other hand, if the security codes match in Sa113, the first random number initial setting KRS1 and the second random number initial setting KRS2 stored in the program management area are read out, and the random number circuit setting process shown in FIG. 34 is executed (Sa114), the random number circuit abnormality inspection process shown in FIG. 34 is executed in order to check whether the random number circuit 509 is operating abnormally (Sa115).

  In the random number circuit setting process shown in FIG. 33, first, setting for using the random number circuit 509 is performed based on the bit value in the bit number [3] of the first random number initial setting KRS1 (Sa201). In the present embodiment, the bit value in the bit number [3] of the first random number initial setting KRS1 is set to “1” in advance, and setting to use the random number circuit 509 is performed corresponding to this bit value. Subsequently, the random number update clock RGK in the random number circuit 509 is set based on the bit value in the bit number [2] of the first random number initial setting KRS1 (Sa202). In the present embodiment, the random number clock RCLK generated by the random number clock generation circuit 43 is determined in response to the bit value [2] of the first random number initial setting KRS1 being “1” in advance. Setting is performed by dividing the frequency by two to be the random number update clock RGK.

  After the setting in Sa202, the random number update rule is set in the random number circuit 509 based on the bit value [1-0] of the first random number initial setting KRS1 (Sa203). In this embodiment, “10” is set in advance as the bit value in the bit number [1-0] of the first random number initial setting KRS1, and the random number update rule in the random number sequence RSN is automatically changed after the second round. Settings are made.

  Subsequently, based on the bit value in the bit number [1] of the second random number initial setting KRS2, a start value at start-up in numerical data to be a random value is determined (Sa204). In this embodiment, “1” is set in advance as the bit value in the bit number [1] of the second random number initial setting KRS2, and the start value of the random number is set to a value based on the ID number.

  Further, based on the bit value in the bit number [0] of the second random number initial setting KRS2, it is set whether or not to change the start value of the numerical data to be a random value at every system reset (Sa205). In this embodiment, the bit value at the bit number [0] of the second random number initial setting KRS2 is set to “0” in advance, and the start value at start-up set in Sa204 is used as it is, and the start value in the random number circuit 509 is used. It is said. When the setting by the processing of Sa205 is completed, the random number circuit 509 starts a random value generation operation. When the bit value [0] of the second random number initial setting KRS2 is set to “1” in advance, the random number start value is changed every time the system is reset. In this case, for example, when the count value in a predetermined free-run counter is stored in the random number start value register built in the main control unit 41 when the system reset occurs, the random number start is performed in the processing of Sa205. By using the stored value of the value register as it is, or by using the value obtained by substituting the stored value into a predetermined arithmetic function (for example, a hash function), the random number start value is predetermined at each system reset. (For example, a range including all or part of the numerical data included in the count value permutation RCN generated by the random number generation circuit 553) may be determined at random.

  Note that the setting by the random number circuit setting process may be performed autonomously by the random number circuit 509 based on the stored data in the program management area without the processing of the CPU 505 being involved. In this case, the random number circuit 509 may be configured not to perform initialization and not to generate a random value when the main control unit 41 is in the security mode. Then, when the CPU 505 reads the user program stored in the ROM 506 in the main control unit 41 and the user mode is started, for example, a control signal for instructing the initial setting to the random number circuit 509 is transmitted from the CPU 505. In response to the above, the random number generation operation may be started after the random number circuit 509 performs the initial setting. In particular, when the random number circuit 509 is externally attached to the main control unit 41, even when the main control unit 41 is in the security mode, the random number circuit 509 performs program management independently of the processing in the CPU 505. The random number generation operation may be started after initial setting based on the storage data of the area.

  In the random number circuit abnormality inspection process shown in FIG. 34, first, the random number clock abnormality determination counter is cleared, and the random number clock abnormality determination count value, which is the count value, is initialized to “0” (Sa301). Subsequently, the internal information data CIF4 stored in the bit number [4] of the internal information register CIF is read (Sa302). Then, it is determined whether or not the read value at Sa302 is “1”. At this time, if the frequency monitoring circuit 551 provided in the random number circuit 509 detects a frequency abnormality in the random number clock RCLK from the random number external clock terminal ERC, the bit value “1” is written as the internal information data CIF4. .

  Therefore, when the read value is determined to be “1” in Sa303, the random number clock abnormality determination count value is updated to be incremented by 1 (Sa304). At this time, it is determined whether or not the count value after the update in Sa304 has reached a predetermined clock abnormality determination value (Sa305). Here, the clock abnormality determination value may be a numerical value determined in advance in order to determine that the clock abnormality is detected when the frequency monitoring circuit 551 continuously detects the frequency abnormality of the random number clock RCLK. If the clock abnormality determination value has not been reached in Sa305, the processing returns to Sa302, and determination based on the bit value of the internal information data CIF4 is performed again.

  When the clock abnormality determination value is reached in Sa305, it is determined that the random number clock is not functioning normally, and the operation of the CPU 505 is shifted to the halt state (HALT).

  If the read value is determined to be “0” in Sa303, the random value abnormality determination counter is cleared, and the random value abnormality determination count value that is the count value is initialized to “0” (Sa306). In the process of Sa303, it is determined that the read value is “0” when the bit value of the internal information data CIF4 read in Sa302 becomes “0” continuously for a plurality of times (for example, twice). You may do it.

  Subsequent to the processing of Sa306, a check value used for checking whether there is an abnormality in the random number value is set to an initial value “0000H” (Sa307). Then, the stored numerical data as the random value is read out from the random value register 559A as the random value register R1D included in the random number circuit 509 (Sa308). For example, in the processing of Sa308, the bit value of the random number latch selection data RDLS0 stored in the bit number [0] of the random number latch selection register RDLS is set to “0”, and fetching of the random number value by software is designated. Subsequently, the bit value of the random value fetch specification data RDLT0 stored in the bit number [0] of the random value fetch specification register RDLT is set to “1”, and fetching to the random value register R1D is designated. Note that setting the bit value in the bit number [0] of the random value fetch specification register RDLT to “1” outputs a latch signal instructing the random number circuit 509 to fetch (latch) numerical data from the CPU 505. It corresponds to that. Thereafter, the numerical value data to be stored as the random number value may be read by turning on the register read signal RRS1 supplied to the random number value register R1D.

  After reading the numerical data in Sa308, the read value is set as the random number inspection reference value (Sa309). Subsequently, the numerical value data to be the random number value is further read from the random value register 559A (Sa310). Note that the read operation at Sa310 may be performed in the same procedure as the read operation at Sa308. In addition, a sufficient delay time may be provided between the read operation at Sa308 and the read operation at Sa310 because the numerical data in the random number sequence RSN generated by the random number circuit 509 changes. After the numerical data is read in Sa310, an exclusive OR operation between the random number inspection reference value and the read value in Sa310 is executed (Sa311). Further, a logical sum operation between the calculation result in Sa311 and the check value is executed, and the calculation result is updated to be a new check value (Sa312). For example, the check value may be stored in a predetermined area of the RAM 507, and each time the process of Sa312 is executed, the calculation result obtained by the process may be saved as a new check value. As a result, changes in all the bits in the numerical data read from the random value register 559A are recorded. If the bit has changed at least once during a plurality of readings, the corresponding bit value in the check value is “1”. "

  Therefore, it is determined whether or not the check value is “FFFFH” (Sa 313), and if it is, since the change of the bit value is recognized for all the bits, it is determined that the random number value is normally updated. Then, the random number circuit abnormality inspection process ends. If it is confirmed that the random number value has been updated normally, the bit value of the random number latch selection data RDLS0 stored in the bit number [0] of the random number latch selection register RDLS is set to “1”. It is set to instruct the random value fetching to the random value register R1D according to the signal input to the port P0. In this embodiment, a wiring for transmitting the game start signal SS1 from the start switch 7 is connected to the input port P0. Thereby, when the game start signal SS1 is turned on, the random number value can be taken into the random value register R1D.

  If the check value is determined to be other than “FFFFH” in Sa313, the random number abnormality determination count value is updated to be incremented by 1 (Sa314). At this time, it is determined whether or not the count value after the update in Sa314 has reached a predetermined random value abnormality determination value (Sa315). Here, if the random number circuit 509 is operating normally, the random value abnormality determination value is determined so that all the bits of the numerical data read from the random value register 559A are changed at least once. Any predetermined numerical value may be used. If the random value abnormality determination value has not been reached in Sa315, the process returns to the processing of Sa310, and determination for reading numerical data as a random value from the random number circuit 509 again and checking for abnormality is performed.

  When the random value abnormality determination value is reached in Sa315, it is determined that the random number clock is not functioning normally, and the operation of the CPU 505 is shifted to the stop state (HALT).

  The random number circuit abnormality inspection process is not limited to that executed by the CPU 505, and the random number circuit abnormality inspection process may be executed by a built-in circuit in the main control unit 41 other than the CPU 505. As an example, the random number circuit 509 has a function of executing a random number circuit abnormality inspection process. When a frequency abnormality of the random number clock RCLK is detected or when an abnormality of the random number value is detected, the CPU 505 May be notified. In addition, the random number circuit abnormality inspection process is not limited to that executed at the time of startup, and for example, every time a timer interrupt occurs in the main control unit 41, a part or all of the random number circuit abnormality inspection process is executed. Anyway.

  Returning to FIG. 32, after the random circuit setting process of Sa114 and the random circuit abnormality inspection process of Sa115, it is determined whether or not the security time set in the process of Sa107 or Sa108 has passed (Sa116). At this time, if the security time has not elapsed, the processing of Sa116 is repeatedly executed and waits until the security time elapses. If it is determined in Sa116 that the security time has elapsed, the security check process is terminated, and the value of the program counter built in the CPU 505 is set to the start address (address 0000H) of the user program in the ROM 506. As a result, the operation state of the main control unit 41 shifts from the security mode to the user mode, and execution of the user program stored in the ROM 506 is started. As described above, at the time of start-up accompanying the input of the user reset signal, the user mode is started without going through the security mode.

  In the user mode, first, built-in devices such as the serial communication circuit 511, peripheral IC, interrupt mode, stack pointer, etc. are initialized (Sa2), and then the values of the I register and IY register are initialized (Sa3). By initialization of the I register and the IY register, an interrupt table address to be referred to when an interrupt occurs is set in the I register, and a reference address for referring to the storage area of the RAM 507 is set in the IY register. . These values are fixed values and are always initialized at startup.

Next, access to the RAM 507 is permitted (Sa4), and RAM parities of all storage areas (including unused areas and unused stack areas) of the RAM 507 are calculated (Sa5). Next, the states of the stop switch 36 a and the automatic checkout switch 36 b are acquired, and after setting the stop function and the automatic checkout function valid / invalid in a specific register of the main control unit 41 (Sa6) , the port input described later The input data of each switch acquired in the process, the confirmation data of each switch indicating that the previous and current input data are in the same state, and the edge data of each switch indicating that the previous and current determined data are different are each cleared (Sa7). Further, the power interruption flag indicating that a power failure has been detected is cleared (Sa8). Further, the value of the door monitoring timer for measuring the monitoring interval of the detection state of the door opening detection switch 25 and the history of the input state of the detection signal from the door opening detection switch 25 are cleared (Sa9), the operation detection command transmission request and the door are cleared. The command transmission request 2 is cleared and the door command transmission request 1 is set (Sa10).

  Next, it is determined whether or not the random number value is latched based on the value of the random number latch flag register, that is, whether or not the numerical value data is captured in the random number value register 559A (Sa11), and the random number value must be latched. If the random number value is latched in the Sa11 step, the random number value for internal lottery is read from the random value register 559A (Sa12), and the process proceeds to the Sa13 step. When the random number value for internal lottery is read from the random value register 559 in the step of Sa12, the random number latch flag register is cleared and new numerical data can be taken in. In the step of Sa12, although the random number value for internal lottery is read, the read random number value is not used, but as a dummy in order to make it possible to take in a new random value according to the operation of the start switch 7. It is to read.

  In step Sa13, it is determined whether the RAM parity calculated in step Sa5 is zero. If the power interruption interrupt processing (main) is normally performed, the RAM parity should be 0. If the RAM parity is not 0 in the step of Sa13, the data stored in the RAM 507 is not normal. In this case, after executing the initialization 1 for initializing all the storage areas except the used stack area and the non-initialization area among the storage areas of the RAM 507 (Sa26), is the setting key switch 37 turned on? If the setting key switch 37 is on, a setting command indicating setting start is generated and stored in the command buffer (Sa23), and the command stored in the command buffer is transmitted to the serial communication circuit 511. The command storage process to be transferred to the transmission data register 561 is performed (Sa24), the interrupt is permitted (Sa25), and the setting change process That is to shift to a setting change state.

  In the command storage process of Sa24, as shown in FIG. 35A, the first byte of the command data stored in the command buffer is transferred to the transmission data register 561 (Sx1), and then stored in the command buffer. The second byte of the stored command data is transferred to the transmission data register 561 (Sx2). The command data transferred to the transmission data register 561 is converted into serial data in the order of transfer to the transmission data register 561 as described above, stored in the transmission shift register 562, and transmitted to the sub-control unit 91. Will be.

  If the setting key switch 37 is off in step Sa24, an error code indicating RAM abnormality is set in the register (Sa28), an error command indicating RAM abnormality is generated and stored in the command buffer (Sa29), and the command is stored. Processing is performed to transfer the error command in the command buffer to the transmission data register 561 (Sa30), interrupt is permitted (Sa31), and the process proceeds to error processing, that is, a RAM abnormal error state.

  If the RAM parity is 0 in step Sa13, it is further determined whether or not the destructive diagnosis data is normal (Sa14). If the power interruption processing (main) is normally performed, the data for destruction diagnosis should be set. If the data for failure diagnosis is not normal in step Sa14 (the data for destruction diagnosis is stored at the time of power interruption) In the case other than 5A (H), the data in the RAM 507 is not normal. Therefore, the process proceeds to step Sa26 and initialization 1 is executed, and then the setting key switch 37 is turned on in step Sa27. For example, after the generation of the setting command indicating the start of setting (Sa23) and the command storing process (Sa24), the interrupt is permitted (Sa25) and the process proceeds to the setting changing process. If the setting key switch 37 is off in step Sa27, an error code indicating a RAM abnormality is set (Sa28), an error command indicating a RAM abnormality is generated (Sa29), and a command storing process (Sa30) is performed. Is permitted (Sa31), and the process proceeds to error processing.

  If it is determined in step Sa14 that the destructive diagnosis data is normal, the data in the RAM 507 is normal. Therefore, the destructive diagnosis data is cleared (Sa15), and the unstored work, the unused area, and the unused area in the RAM 507 are cleared. After initialization 3 for initializing the used stack area (Sa16), it is determined whether or not the setting key switch 37 is on (Sa17). If the setting key switch 37 is on, the process proceeds to step Sa22. Initialization 1 is executed, and after setting command generation (Sa23) and command storage processing (Sa24) indicating the start of setting, interrupt is permitted (Sa25) and the processing shifts to setting change processing.

  If the setting key switch 37 is OFF in the step of Sa17, each register is restored to the state before power interruption, that is, the state saved in the stack (Sa18), and a return command is generated and stored in the command buffer ( Sa19), a command storage process is performed, the return command in the command buffer is transferred to the transmission data register 561 (Sa20), the interrupt is permitted, Sa21), and the process that was executed last before the power interruption is returned.

  As described above, in the start-up process, after the security mode is switched to the user mode only at the time of system reset, the security mode is omitted and the user mode is started at the time of user reset.

  In the security mode at the time of system reset, random number circuit setting processing for setting the random number circuit 509 is performed, and in the random number circuit setting processing, setting of a random number update rule, setting of a random number start value, and the like are performed. The security mode is omitted, and the user mode is started. For this reason, the initial value of the random number is reset at the time of system reset, whereas the random number circuit 509 is not set at the time of user reset, and the numerical data that becomes the random number is continuously updated as it was before the reset. Will be. Also, interrupts are not permitted during security mode, and interrupts are permitted after shifting to user mode. Therefore, when resetting the system, before interrupts are permitted, The random number circuit 509 is set.

  Regardless of whether the reset is a system reset or a user reset, first, after the access to the RAM 507 is permitted, all the storage areas (unused areas and unused stacks) of the RAM 507 are processed without performing other processes. Before the determination of whether the stored data is normal or not from the calculated RAM parity, it is necessary to perform the same regardless of whether the stored data of the RAM 507 is normal or not. As a certain process, setting of enabling / disabling of stop function, automatic settlement function, input data of each switch, finalized data, clearing of edge data, clearing of power-off flag, detection interval of detection state of door opening detection switch 25 are set. The value of the door monitoring timer to be counted, the history of the input state of the detection signal from the door opening detection switch 25, the door command transmission request 2 Rear and door command transmission request 1 setting, read the random number from the random number register 559a, a do, then the data stored in the RAM507 is adapted to make a determination of whether normal or not based on the RAM parity.

  FIG. 36 is a flowchart showing the control content of error processing executed by the main control unit 41.

  In the error processing, first, the current display state of the game auxiliary display 12 is saved in the stack (Sb1), the error code stored in the register is displayed on the game auxiliary display 12 (Sb2), and the error code is stored in the RAM. It is determined whether or not it is an abnormal error (Sb3). If the error code indicates a RAM abnormal error, the process proceeds to a loop process in which no process is performed.

  If it is determined in step Sb3 that the error code does not indicate a RAM abnormal error, an error command indicating the occurrence of the error state and its type is generated, stored in the command buffer (Sb4), and command storage processing is performed. Then, the error command in the command buffer is transferred to the transmission data register 561 (Sb5).

  Next, it is determined whether or not an on change is detected from the reset / setting switch 38 off (Sb6). If no on change is detected from the reset / setting switch 38 off, the reset switch 23 is further turned off. It is determined whether or not a change in on is detected (Sb7). If no change in on is detected from off of the reset switch 23, the process returns to step Sb6. That is, the game waits in a state where the progress of the game is impossible until a change of on from the off of the reset / setting switch 38 or the reset switch 23 is detected.

  If a change from on to off of the reset / setting switch 38 is detected in step Sb6 or a change from on to off from the reset switch 23 is detected in step Sb7, the switch detection state is changed. Edge data indicating that it has changed from off to on or that it has changed from on to off (called a rising edge when it changes from off to on, and a falling edge when it changes from on to off) Clear (Sb8), clear the error code stored in the register (Sb9), return the display state of the auxiliary game display 12 to the display state saved in the stack in the step of Sb1 (Sb10), An error command indicating the cancellation is generated and stored in the command buffer (Sb 1), after transferring the error command in the command buffer to the transmit data register 561 performs command storage processing (Sb12), it returns to the original processing.

  As described above, in the error processing, if the error processing is not due to the RAM abnormality, the reset / setting switch 38 or the reset switch 23 is operated to return to the original processing even if the error state is canceled. In the case of error processing due to an abnormality, even if the reset / setting switch 38 or the reset switch 23 is operated, the error state is canceled and the original state is not restored.

  FIG. 37 is a flowchart showing the control content of the setting change process executed by the main control unit 41.

  In the setting change process, first, the setting value stored in the setting value work of the RAM 507 is read out, and the read value is set as a display value (Sc1), and whether or not the display value is out of a settable range (1 to 6). (Sc2), if the display value is within the settable range, the process proceeds to step Sc4. If the display value is outside the settable range, the display value is corrected to 1, and the process proceeds to step Sc5.

  In the step of Sc5, after the display value is displayed on the setting value display 24, the reset / setting switch 38 and the start switch 7 are turned off to wait for detection of an on change (Sc5, Sc6). When a change from on to off of the reset / setting switch 38 is detected, the edge data is cleared (Sc9), the display value is incremented by 1 (Sc10), and the process returns to the step Sc2.

  Further, when a change from on to off of the start switch 7 is detected in the step of Sc6, the edge data is cleared (Sc9), and the other switches are turned on by referring to finalized data to be described later. (Sc10), if any switch is in the on state, the process returns to the step of Sc5, and if any switch is not in the on state, the value displayed on the set value display 24 is set to 0. (Sc11), and waits until the setting key switch 37 is turned off (Sc12).

  When the setting key switch 37 is turned off in the step of Sc11, the display value is stored in the setting value work (Sc13), and the setting command indicating the end of setting and the new setting value is generated and stored in the command buffer. (Sc14), a command storing process is performed, the setting command in the command buffer is transferred to the transmission data register 561 (Sc15), and the process proceeds to the game process.

  FIG. 38 is a flowchart showing the control contents of the game process executed by the main control unit 41.

  In the game process, a BET process (Sd1), an internal lottery process (Sd2), a reel rotation process (Sd3), a winning determination process (Sd4), a payout process (Sd5), and a game end process (Sd6) are sequentially executed. When the end-time process ends, the process returns to the BET process again.

  In the BET process in the step of Sd1, the process waits in a state where a bet number can be set, and a process for starting a game when a specified number of bets is set according to the gaming state and the start switch 7 is operated is executed. .

  In the internal lottery process in the step of Sd2, it is determined whether or not the above winning combination is allowed based on the internal lottery random value latched simultaneously with the start of the game by the detection of the start switch 7 in the step of Sd1. Process. In this internal lottery process, a winning flag is set in the RAM 507 based on each lottery result.

  In the reel rotation process in the step of Sd3, the process of rotating each reel 2L, 2C, 2R and the operation of the corresponding reel 2L, 2C, 2R in response to the operation of the stop switch 8L, 8C, 8R detected by the player are detected. A process for stopping the rotation is executed.

  In the winning determination process in the step Sd4, when it is determined in the step Sd3 that the rotation of all the reels 2L, 2C, and 2R is stopped, the winning is determined according to the display result derived for each reel 2L, 2C, and 2R. A process of determining whether or not it has occurred is executed.

  In the payout process in step Sd5, when it is determined that a prize is generated in step Sd4, processing such as addition of credits and payout of medals is performed based on the number of payouts according to the win.

  In the game end process in the step of Sd6, a process of setting a gaming state in preparation for the next game is executed.

  In the game process, a command is generated in accordance with the progress control of the game, set in the command buffer, and immediately after executing the command storage process, the command stored in the command buffer is transmitted to the transmission data register of the serial communication circuit 511. 561 and transmitted to the sub-control unit 91.

  39 to 41 are flowcharts showing the control content of the BET process executed by the main control unit 41 in step Sd1.

  In the BET process, first, the value of the BET counter in which the value of the betting number is stored in the RAM 507 is cleared (Se1), a specified number corresponding to the gaming state is set in the RAM 507 (Se2), and the RAM 507 is a replay game. Whether or not the game is a replay game is determined on the basis of whether or not the replay game flag indicating is set (Se3).

  If it is determined in step Se3 that the game is a replay game, a BET command indicating that 3 bets have been added is generated and stored in the command buffer (Se4), and command storage processing is performed. The BET command in the command buffer is transferred to the transmission data register 561 (Se5), the value of the BET counter is incremented by 1 (Se6), the specified number of bets set in the RAM 507 is referred, and the value of the BET counter is specified. It is determined whether or not the number is a bet, that is, whether or not the number of bets serving as a game start condition is set (Se7), and if the BET counter value is not a specified number, the process returns to the step of Se6 and the value of the BET counter If is a prescribed number, the insertion prohibition flag indicating that the medal cannot be inserted is set in the RAM 507 (Se8), and the process proceeds to Step Se10.

  If it is determined in step Se3 that the game is not a replay game, settings before waiting to be made are performed (Se9), and the process proceeds to step Se10. In the setting before waiting for insertion, the insertion disable flag set in the RAM 507 is cleared, and a medal can be inserted.

  In step Se10, it is determined whether or not an error code is set in the register, that is, whether or not an error is detected. If an error code is set, the process proceeds to error processing shown in FIG.

  If no error code is set in the step of Se10, it is determined whether or not a medal can be inserted based on whether or not the insertion prohibition flag is set in the RAM 507 (Se11). When it is determined in step Se11 that the medal can be inserted, the flow path switching solenoid 30 is turned on, and the medal can be inserted using the medal flow path as a path on the hopper tank side. (Se12), the process proceeds to step Se14, and if it is determined that the medal cannot be inserted, the flow path switching solenoid 30 is set to the off state, and the medal flow path is the path on the medal payout exit 9 side. As a result, the insertion of a new medal is prohibited (Se13), and the process proceeds to the step Se14.

  In the step of Se14, it is determined whether or not the setting key switch 37 is on. If the setting key switch 37 is on, it is determined whether or not the value of the BET counter is 0 (Se15). If the value of the BET counter is 0 in step Se15, a setting confirmation command indicating the start of setting confirmation is generated and stored in the command buffer (Se16). Is transferred to the transmission data register 561 (Se17), and the setting confirmation process (Se18), that is, the setting confirmation state is entered. After the setting confirmation process in the step Se18 is completed, the process returns to the step Se10.

  If the setting key switch 37 is not on in step Se14 or if the value of the BET counter is not 0 in step Se15, the process proceeds to step Se19, and whether or not the inserted medal sensor 31 has detected passage of the inserted medal. That is, it is determined whether or not there is a inserted medal flag indicating that the passage of the inserted medal is detected. If the passage of the inserted medal is not detected in the step of Se19, the process proceeds to the step of Se31, and if the passage of the inserted medal is detected, the inserted medal flag is cleared (Se20), and the non-insertable flag is set in the RAM 507. Whether or not a medal can be inserted is determined based on whether or not a medal can be inserted (Se21). If the medal cannot be inserted, the process proceeds to Step Se31.

  If the medal can be inserted in the step of Se21, the prescribed number of bets set in the RAM 507 is referred to determine whether or not the value of the BET counter is the prescribed number (Se22), If the value is not the specified number, the value of the BET counter is incremented by 1 (Se23), a BET command indicating that the bet number is incremented by 1 is generated and stored in the command buffer (Se24), and command storage processing is performed. The BET command in the command buffer is transferred to the transmission data register 561 (Se25), and the process returns to the Se9 step.

  If the value of the BET counter is the prescribed number in the step of Se22, the credit counter value in which the credit value is stored in the RAM 507 is incremented by 1 (Se26), and a credit command indicating the current credit counter value is generated. The command is stored in the command buffer (Se27), the command storage process is performed, the credit command in the command buffer is transferred to the transmission data register 561 (Se28), and it is determined whether the value of the credit counter is 50 which is the upper limit value. If the value of the credit counter is not 50, the process returns to the step of Se9. If the value of the credit counter is 50, the insertion disable flag is set in the RAM 507 (Se30), and the process returns to the step of Se9.

  In step Se31, it is determined whether or not a change from on to off of the start switch 7 is detected, that is, whether or not a rising edge indicating a rising edge of the start switch 7 is set.

  If it is determined in step Se31 that no change from on to off of the start switch 7 has been detected, the process proceeds to step Se41, and if a change from on to off in the start switch 7 is detected, an interrupt will occur. Is prohibited (Se32), the edge data is cleared (Se33), and it is determined whether or not another switch is on based on finalized data described later (Se34). If interrupt is permitted (Se35), the process returns to the step of Se9.

  If none of the other switches are in the on state in step Se34, the bet number that is set in the RAM 507 is further referred to and the BET counter value is the specified number, that is, a bet that becomes a game start condition. It is determined whether or not the number is set (Se36).

  If the value of the BET counter is not the specified number in the step of Se36, the interrupt is permitted (Se35), and the process returns to the step of Se9. If the value of the BET counter is the specified number, the value of the random number storage work is internally stored. A random value for lottery is set in a lottery work (Se37), interrupt is permitted (Se38), an unloadable flag is set in the RAM 507, the flow path switching solenoid 30 is turned off, and the flow path of the medal Is set to be set at the start of the game (Se40). Then, after the step of Se40, the BET process is terminated and the process returns to the flowchart of FIG.

  After the change of the start switch 7 from off to on is detected in this way, it is determined that the operation of the start switch 7 is invalid or valid, and the value of the random value storage work is set as the lottery work. In the meantime, interrupts are prohibited and timer interrupt processing (main) is executed during this period to prevent rewriting of the random value storage work value. .

  In the step of Se41, it is determined whether or not a change from on to off of the single BET switch 5 is detected, that is, whether or not a rising edge indicating the rising of the single BET switch 5 is set. If a change of on from the off of the single BET switch 5 is not detected in the step of Se41, the process proceeds to a step of Se49, and if the change of on from the off of the single BET switch 5 is detected, the edge data is cleared. (Se42) With reference to the prescribed number of bets set in the RAM 507, it is determined whether or not the value of the BET counter is the prescribed number (Se43). If the value of the BET counter is the specified number in the step of Se46, the process returns to the step of Se9. If the value of the BET counter is not the specified number, it is determined whether or not the value of the credit counter is 0 (Se44). If the counter value is 0, the process returns to step Se9. If the value of the credit counter is not 0 in the step of Se47, 1 is subtracted from the value of the credit counter (Se45), 1 is added to the value of the BET counter (Se46), and BET indicating that 1 is added to the bet number A command is generated and stored in the command buffer (Se47), command storage processing is performed, the BET command in the command buffer is transferred to the transmission data register 561 (Se48), and the process returns to Se9.

  In step Se49, it is determined whether or not a change from on to off of the MAXBET switch 6 is detected, that is, whether or not a rising edge indicating the rising of the MAXBET switch 6 is set. If a change of on from the off of the MAXBET switch 6 is not detected in the step of Se49, the process proceeds to a step of Se58. If a change of on from the off of the MAXBET switch 6 is detected, the edge data is cleared (Se50). Referring to the prescribed number of bets set in the RAM 507, it is determined whether or not the value of the BET counter is the prescribed number (Se51). If the value of the BET counter is the specified number in the step of Se51, the process proceeds to the step of Se55, and if the value of the BET counter is not the specified number, it is determined whether or not the value of the credit counter is 0 (Se52). If the value of the credit counter is 0, the process proceeds to step Se55. If the value of the credit counter is not 0 in the step of Se52, 1 is subtracted from the value of the credit counter (Se53), 1 is added to the value of the BET counter (Se54), and the process returns to the step of Se51. In the step of Se55, it is determined whether or not the BET counter has been added. If the BET counter has not been added, the process returns to the step of Se9, and if the BET counter has been added, the bet number is added by the added number. A BET command indicating this is generated and stored in the command buffer (Se56), command storage processing is performed, the BET command in the command buffer is transferred to the transmission data register 561 (Se57), and the process returns to the Se9 step.

In the step of Se58, it is determined whether or not a change from on to off of the settlement switch 10 is detected, that is, whether or not a rising edge indicating the rise of the settlement switch 10 is set. If the change of on from the off of the settlement switch 10 is not detected in the step of Se58, the process returns to the step of Se9, and if the change of on from the off of the settlement switch 10 is detected, the edge data is cleared (Se59). Then, based on whether or not the replay game flag is set in the RAM 507, it is determined whether or not the game is a replay game (Se60), and if the game is a replay game, the process returns to Se9. If the game is not a replay game in the step of Se60, it is determined whether or not the value of the BET counter is 0 (Se61). If the value of the BET counter is 0, the process proceeds to the step of Se63, and the value of the BET counter is 0. Otherwise, a bet amount settlement flag indicating that the already set bet amount is to be settled is set in the RAM 507 (Se62), and the process proceeds to Step Se63. In Se63 step, they were used in the hopper motor 34 b drives the pay out the credit counter or medals value amount stored in the BET counter control, that medals or betting amount set is stored as a credit medal Settlement process is performed in which the control to return is performed. Then, after the settlement process in the step of Se63, the input impossible flag set in the RAM 507 is cleared (Se64), and the process returns to the step of Se9.

  42 and 43 are flowcharts showing the control contents of the reel rotation process executed by the main control unit 41 in step Sd3.

  In the reel rotation process, first, a freeze lottery is executed (Si1). In the freeze lottery, whether to control the freeze state based on the result of the internal lottery or the like is determined, and in the case of controlling to the freeze state, the execution time is determined.

  After the freeze lottery in the Si1 step, it is determined whether or not a wait time (approximately 4.1 seconds in this embodiment) has elapsed since the reel rotation start time of the previous game (Si2), and the wait time has elapsed. If not, wait until the wait time elapses.

  If the wait time has elapsed in the Si2 step, a new wait time is set (Si3).

  Next, the setting at the time of starting the rotation of the reel motor is performed, the rotation of the reel is started (Si4), and then the setting at the time of completion of the stop preparation is performed (Si5). As a result, the stop operation can be validated, and then the stop operation becomes valid when the constant speed rotation of the reel is detected in the origin interruption process of the timer interrupt process (main). .

  Next, it is determined whether or not the freeze condition is satisfied, that is, whether it is time to control the freeze state in the freeze lottery (Si6), and the freeze condition is satisfied. If not, the process proceeds to the Si8 step. If the freeze condition is satisfied, a prescribed value is set in the freeze timer counter assigned to the RAM 507 to measure the time of the freeze state (Si7), and the process proceeds to the Si8 step. . The value of the freeze timer counter is decremented by 1 every time the timer interrupt process (main) is executed four times.

  In the step of Si8, it is determined whether or not the value of the freeze timer counter is 0, that is, whether or not the freeze state is controlled. If the value of the freeze timer counter is not 0 in the step of Si8, that is, if it is controlled to the freeze state, the process waits until the value of the freeze timer counter becomes 0.

  When the value of the freeze timer counter is 0 in the Si8 step, that is, when the freeze state is not controlled (when the freeze state is not controlled from the beginning or when the freeze state ends), either stop It is determined whether or not a change from on to off of the switch is detected, that is, whether or not a rising edge indicating the rising of any stop switch is set (Si9), and a change from off to on of any stop switch is changed. If no reel rotation error is detected, it is determined whether or not a reel rotation error (error determined when the reel reference position is not detected by the reel sensor 33 for a certain period or more) has occurred (Si10), and a reel rotation error occurs. If not, then there will be an insertion error (other than the period during which medal insertion is permitted) , An error determined when the insertion of a medal is detected) and a payout error (an error determined when a medal payout is detected in a period other than the period during which medal payout is permitted). Is determined (Si11, Si12). If any error is not determined in the steps Si10 to Si12, the process returns to the step Si9.

  If it is determined that an insertion error has occurred in the Si11 step, or if a payout error is determined in the Si12 step, an error code indicating the insertion / discharge error during reel rotation is set in the register (Si13). ), The process proceeds to the error processing shown in FIG. 36 (Si16). When the error is released, the process returns to the Si8 step again.

  If it is determined in step Si10 that a reel rotation error has occurred, an error code indicating a reel rotation error is set in the register (Si15), and the process proceeds to error processing shown in FIG. 36 (Si16). Along with this, the rotation of the reels is also temporarily stopped. When the error is released, the process returns to the Si4 step again and the reel rotation is resumed.

  If a change of on is detected from the off of one of the stop switches in the step of Si9, the edge data is cleared (Si17), and it is determined whether or not the other switch is on (Si18). If at least one of the other switches is on, the process returns to the Si9 step.

  If all the other switches are in the OFF state in the step of Si18, the number of steps from the reel reference position at that time in the reel motor corresponding to the stop switch in which the change from off to on is detected (becomes the stop operation position). Step number) is acquired and set to the work corresponding to the stop reel (Si19), and stop position specifying processing is performed (Si20).

  In the stop position specifying process, the number of sliding symbols or the stop table is acquired according to the stop status of the reels, and the region number serving as the stop position is specified based on the number of sliding symbols or the stop table. In this embodiment, only when the first stop is performed and the stop operation of the left reel is detected, the number of sliding symbols is acquired to identify the stop position, and the stop operation other than the left reel is performed in the first stop. When detected, in the case of the second stop or the third stop, the corresponding stop table is acquired and the stop position is specified.

  Next, a reel stop command is generated and stored in the command buffer (Si21), command storage processing is performed, the BET command in the command buffer is transferred to the transmission data register 561 (Si22), and the reel rotation corresponding to the stop operation is performed. The system waits until it stops (Si23).

  When the rotation of the reels corresponding to the stop operation stops, it is determined whether or not all the reels have stopped (Si24). If all the reels have not stopped, the process returns to the Si5 step, and all the reels are If it has stopped, the reel rotation process is terminated and the process returns to the flowchart of FIG.

  44 and 45 are flowcharts showing the control content of the timer interrupt process (main) executed by the main control unit 41 by interrupting and executing the activation process and the game process at regular intervals (0.56 ms interval). Note that other interrupts are automatically prohibited during the execution period of the timer interrupt process (main).

  In the timer interrupt process (main), first, after saving the register in use to the stack area (Sk1), the transmission completion value of the status register 563 of the serial communication circuit 511 is acquired, and based on the acquired value. The transmission completion flag stored in the RAM 507 is updated (Sk2). Specifically, if the value of the status register 563 is 1 indicating that command data transmission has not been performed or that command data transmission has been completed, the value of the transmission completion flag is updated to 1, and the status register 563 If the value is 0 indicating that a command is being transmitted or a command is waiting to be transmitted, the value of the transmission completion flag is updated to 0.

  Next, a power failure determination process is performed (Sk3). In the power failure determination process, it is determined whether or not a voltage drop signal is input from the power failure detection circuit 48. If a voltage drop signal is input, whether or not the voltage drop signal is input in the previous power failure determination process as well. If a voltage drop signal has been input in the previous power failure determination process, it is determined that a power failure has occurred, and a power interruption flag indicating that is set.

  After the power failure determination process in the step of Sk3, it is determined whether or not the power interruption flag is set (Sk4). If the power interruption flag is not set, the process proceeds to Sk5 and the power interruption flag is set The process proceeds to a power interruption process (main) described later.

  In step Sk5, port input processing for inputting detection data of various switches from the input port is performed.

  Next, the branch counter for identifying the timer interrupt to be executed in the timer interrupt process (main) is advanced by 1 from the four types of timer interrupts 1 to 4 (Sk6). In the step of Sk6, 1 is added when the branch counter value is 0 to 2, and is updated to 0 when the counter value is 3. That is, the branch counter value loops in the order of 0 → 1 → 2 → 3 → 0... Each time the timer interrupt process (main) is executed.

  Next, referring to the counter value for branching, it is determined whether it is 2 or 3, ie, timer interrupt 3 or timer interrupt 4 (Sk7), and if it is not timer interrupt 3 or timer interrupt 4, that is, timer interrupt In the case of 1 or timer interrupt 2, it is checked whether the reel motors 32L, 32C, 32R are started or whether they are rotating at a constant speed, and whether the reel motors 32L, 32C, 32R are started or are rotating at a constant speed. For example, the motor phase signal output process for outputting the phase signal data changed in the motor step process of Sk11 described later and the phase signal data changed in the final stop process of Sk24 described later is executed (Sk8).

  Next, referring to the counter value for branching, it is determined whether or not it is 1, that is, timer interrupt 2 (Sk9). If it is not timer interrupt 2, that is, timer interrupt 1, reel motor Reel starting process (Sk10) for controlling the step time interval when starting 32L, 32C, 32R, motor step process (Sk11) for changing phase signal data of the reel motors 32L, 32C, 32R, reel motors 32L, 32C After the stop of 32R, motor phase signal standby processing (Sk12) for changing the phase signal to one-phase excitation after a certain time has been sequentially executed, and then the process proceeds to step Sk26.

  In the case of timer interrupt 2 in the step of Sk9, LED dynamic display processing (Sk13) for dynamically lighting various indicators, and output processing of control signals and the like for outputting data such as lighting signals of various LEDs to the output port (Sk14), a time counter update process (Sk15) for updating various time counters, a door monitoring process (Sk16) for monitoring the detection state of the door opening detection switch 25, a door command transmission request, etc., a door command and an operation detection command The command transmission process (Sk17) for performing transfer to the serial communication circuit 511 and the like and the external output signal update process (Sk18) for updating the external output signal are sequentially executed, and then the process proceeds to step Sk26.

  If the timer interrupt 3 or the timer interrupt 4 is found in the step of Sk7, it is further determined by referring to the branch counter value whether it is 3 or not, that is, the timer interrupt 4 (Sk19). If it is not interrupt 4, that is, if it is timer interrupt 3, the passing of the origin of the rotating reels 2L, 2C, 2R (pass of the reel reference position) is checked, and the occurrence of a reel rotation error is detected and stopped. Check if the preparation is complete (whether the stop preparation completion code is set). If the stop preparation is complete and the motor is rotating at a constant speed, operate the stop switch corresponding to the rotating reel. Processing to pass through origin (Sk20), switch input determination processing (Sk21) for determining whether or not the detection state of switches has changed, operation detection command transmission request, etc. After executing random number reading process to be stored in the random number storing work the (SK22) sequentially reads numeric data from Staphylococcus R1D, the process proceeds to step Sk26.

  If the timer interrupt is 4 in the step of Sk19, a stop switch process (Sk23) for calculating the number of steps after which it is necessary to stop at the stop position specified in the stop position specifying process; Count the number of steps until the stop calculated in the process, and when it is time to stop, stop process to start the brake by two-phase excitation (Sk24), three-phase excitation after a certain time after starting the brake in the stop process After the final stop process (Sk25) is sequentially executed, the process proceeds to step Sk26.

  In the step of Sk26, the register saved in the stack area in Sk1 is restored, and the processing before the interruption is returned.

  As described above, in this embodiment, the timer interrupt process (main) is executed by interrupting the basic process at regular intervals, and the process counter is updated each time the timer interrupt process (main) is executed. In addition to distributing the load required for one timer interrupt process (main), the power interruption condition based on the voltage drop signal regardless of the process counter value. A power failure determination process is performed to determine whether or not the power failure is satisfied.If the power interruption condition is satisfied, the power interruption processing is performed. Disconnection processing can be performed.

  In the timer interrupt process (main), it is determined whether or not the power interruption condition is satisfied. If the power interruption condition is satisfied, the process proceeds to the power interruption process. Since interruptions due to power interruptions do not occur during execution of interrupt processing (main), interruption processing can be interrupted during execution of timer interruption processing (main), or timer interruption processing (main) Since it is not necessary to wait for the end of the interruption to perform an interruption process associated with power interruption, the process associated with establishment of the power interruption condition is not complicated.

  FIG. 46 is a flowchart showing the control content of the switch input determination process executed by the main control unit 41 in the timer interrupt 3 of the timer interrupt process (main) described above.

  In the switch input determination process, the input data of each switch acquired in the port input process is updated (Sk101), and it is determined whether the detection state indicated by the previous input data is the same as the detection state indicated by the current input data. If the determination is made (Sk102) and the detection state indicated by the previous input data is not the same as the detection state indicated by the current input data, the flow returns to the flowchart of FIG.

  In the step of Sk102, when the detection state indicated by the previous input data is the same as the detection state indicated by the current input data, that is, when the same detection state is indicated for 2.24 ms, the determined data of the corresponding switch. Is updated (Sk103), and the process proceeds to Step S104. In step Sk103, the current confirmed data is moved to the previous confirmed data, and the detection state indicated by the input data determined to be the same as the previous time is set as the current confirmed data.

  In step Sk104, it is determined whether or not the previous confirmed data after the update and the current confirmed data are the same. If the previous confirmed data and the current confirmed data are the same for all the switches, the edge data is determined. Clear (Sk105) and return to the flowchart of FIG.

  In any one of the switches in Sk104, if the previous confirmed data and the current confirmed data are not the same in any one switch, it is determined whether the switch in which the previous confirmed data and the current confirmed data are different from off to on. (Sk106) If there is no switch changed from off to on, the process proceeds to step Sk108. If there is a switch changed from off to on, a rising edge indicating that the corresponding switch has changed from off to on is set. (Sk107), the process proceeds to step Sk108.

  In the step of Sk108, it is determined whether or not the switch in which the final confirmed data and the final confirmed data have changed from on to off, and if there is no switch changed from on to off, the process proceeds to Sk110, and changes from on to off. If there is a switch, a falling edge indicating that the corresponding switch has changed from on to off is set (Sk109), and the process proceeds to Step S110.

  In the step of Sk110, it is determined whether or not there is a switch in which the previous finalized data and the current finalized data are the same. If there is a switch in which the previous fixed data and the current fixed data are the same, only the edge data of the corresponding switch is cleared (Sk111), and the process proceeds to Step Sk112.

  In Sk112, an operation detection command transmission request is set, a switch whose detection state has changed (a switch for which edge data is set), whether the switch has changed from off to on, or from on to off (rising edge) Or a falling edge), an operation detection command storage area (operation) assigned to the RAM 507 by generating an operation detection command indicating a detection state (on / off) of another switch (a switch whose detection state has not changed). The operation detection command is temporarily stored until the detection command is transmitted (Sk113), thereby instructing the transmission of the operation detection command, and then the process returns to the flowchart of FIG.

  FIG. 47 is a flowchart showing the control content of the random number reading process executed by the main control unit 41 in the timer interrupt 3 of the timer interrupt process (main) described above.

  In the random value reading process, it is determined whether or not the numerical data is latched based on the value of the random number latch flag register, that is, whether or not the numerical data is taken into the random value register 559A (Sk201). If not latched, the random number reading process is terminated and the process returns to the flowchart shown in FIG.

  If the numerical data is latched in the step of Sk201, the numerical data is read from the random value register 559A (Sk202), and the value stored in the random value storage work is updated to the numerical data read in Sk202 (Sk203). The random number reading process is terminated and the process returns to the flowchart shown in FIG.

  When numerical data is read from the random value register 559 in the step of Sk202, the random number latch flag register is cleared and new numerical data is accepted into the random value register 559.

  FIG. 48 is a flowchart showing the control contents of the door monitoring process executed by the main control unit 41 in the timer interrupt 2 of the timer interrupt process (main) described above.

  In the door monitoring process, first, a history of the input state of the door opening detection switch 25 (a value obtained by continuing to logically OR the determination state of the positive detection signal of the door opening detection switch 25 acquired in the port input process for about 100 ms). The door sensor history is updated (Sk301). That is, a logical sum of the positive detection signal detection state of the door opening detection switch 25 and the door sensor history is taken as a new door sensor history.

  Next, it is determined whether or not the value of the door monitoring timer is 0, that is, whether or not about 100 ms has elapsed since the previous monitoring (Sk302). If the value of the door monitoring timer is not 0, the value of the door monitoring timer is set. 1 is subtracted (Sk303), the door monitoring process is terminated, and the process returns to the flowchart of FIG.

  If the value of the door monitoring timer is 0 in the step of Sk302, 44 is set as the value of the door monitoring timer (Sk304), and a new time measurement of 100 ms is started. After the door sensor history is acquired in the register and the door sensor history in the RAM 507 is cleared (Sk305), the door open detection switch 25 indicated by the door sensor history acquired in the register and the door command storage area (door) assigned to the RAM 507 are displayed. This is an area where the door command is temporarily stored until the command is transmitted, and is updated to a door command indicating a new detection state when the detection state of the door opening detection switch 25 changes). The detection state of the door opening detection switch 25 indicated by the door command is compared to determine whether or not there is a change in the detection state of the door opening detection switch 25 (Sk306).

  If there is no change in the detection state of the door opening detection switch 25 in the step of Sk306, whether or not the door command transmission request 1 is set, that is, the door command transmission is requested when the main control unit 41 is activated or the game is ended. (Sk307), and if the door command transmission request 1 is not set, the door monitoring process is terminated and the process returns to the flowchart of FIG.

  When there is a change in the detection state of the door opening detection switch 25 in the step of Sk306, or when the door command transmission request 1 is set in the step of Sk307, the door command transmission request 1 is cleared and the door command transmission is performed. Request 2 is set (Sk308), and a door command based on the acquired door sensor history (detected state of the door open detection switch 25 after the change) is generated and stored in the door command storage area (Sk309). After instructing the transmission of the door command, the door monitoring process is terminated and the process returns to the flowchart of FIG.

  FIG. 49 is a flowchart showing the control content of the command transmission process executed by the main control unit 41 in the timer interrupt 2 of the timer interrupt process (main) described above.

  In the command transmission process, first, whether or not the value of the transmission completion flag updated in the step Sk2 of the timer interrupt process (main) in which the command transmission process is performed is 0, that is, the serial number at the start of the timer interrupt process. It is determined whether the communication circuit 511 is transmitting command data or is waiting for command data transmission (Sk401). If the value of the transmission completion flag is 0, that is, the serial communication circuit 511 is transmitting command data, Alternatively, if the command data is waiting to be transmitted, the command transmission process is terminated and the process returns to the flowchart shown in FIG.

  If the value of the transmission completion flag is not 0 in the step of Sk401, it is determined whether the door command transmission request 2 is set, that is, whether the transmission of the door command is instructed (Sk402).

  When the door command transmission request 2 is set in the step of Sk402, the door command transmission request 2 is cleared (Sk403), the door command set in the door command storage area is read and stored in the command buffer ( (Sk404), command storage processing is performed, the door command in the command buffer is transferred to the transmission data register 561 (Sk408), and the process returns to the flowchart shown in FIG.

  If the door command transmission request 2 is not set in the step of Sk402, it is determined whether or not an operation detection command transmission request is set, that is, whether or not an operation detection command transmission is instructed (Sk405). .

  If the operation detection command transmission request is not set in the step of Sk405, the process returns to the flowchart shown in FIG. 44. If the operation detection command transmission request is set, the operation detection command transmission request is cleared ( (Sk406), the operation detection command set in the operation detection command storage area is read out and stored in the command buffer (Sk407), command storage processing is performed, and the operation detection command in the command buffer is transferred to the transmission data register 561 ( Sk408), the process returns to the flowchart shown in FIG.

  FIG. 50A is a flowchart showing the control contents of the power interruption process (main) executed when the main control unit 41 determines that the power interruption flag is set in the timer interrupt process (main) described above. is there.

  In the power interruption process (main), first, all registers that may be in use are saved in the stack area (Sm1). Note that the values of the I register and IY register described above are used, but are not saved here because the same fixed value is always set with the initialization at the time of startup.

  Next, destruction diagnosis data (5A (H) in this embodiment) is set (Sm2), and all output ports are initialized (Sm3). Next, the RAM parity adjustment data is calculated and set so that the exclusive OR of all the storage areas (including the unused area and the unused stack area) of the RAM 507 becomes 0 (Sm4), and access to the RAM 507 is performed. Prohibited (Sm5).

  Thereafter, the CPU 505 is stopped due to a decrease in voltage, or a user reset signal is input to restart the system. In this standby state, it is determined whether or not the random number value is latched based on the value of the random number latch flag register, that is, whether or not numerical data is taken into the random number value register 559A (Sm6), and the random number value is latched. If it is, the random number value for internal lottery is read from the random value register 559A (Sm7), and no other processing is performed. When the random number value for internal lottery is read from the random number value register 559 in the step of Sm7, the random number latch flag register is cleared, and the acquisition of new numerical data is permitted. In the step of Sm7, the random number value for internal lottery is read, but the read random number value is not used, but a dummy value is taken in order to enable a new random value to be taken in response to the operation of the start switch 7. Is read out.

  When the voltage drops in this standby state, the operation is stopped internally. Therefore, the main control unit 41 reliably stops operation when power is interrupted. Further, in this standby state, when the user reset signal is input without the voltage being lowered, the above-described activation process (main) is executed from the user mode, and if the stored data in the RAM 507 is normal, the process returns to the original process. Will be.

  In this embodiment, after prohibiting access to the RAM 507, it is monitored whether or not the random number value is latched, and when the random number value is latched, processing other than the process of reading the latched random value is performed. As shown in FIG. 50 (b), the output state of the voltage drop signal is monitored (Sm6-), and when the voltage drop signal is not input, the voltage recovery is determined, and the startup process ( The program may be started from the main user mode (step Sa2).

  Regardless of whether the reset is a system reset or a user reset, the main control unit 41 according to the present embodiment first performs all the storage areas of the RAM 507 without performing other processes after the access to the RAM 507 is permitted. Before calculating the RAM parity of the RAM 507 (including the unused area and the unused stack area) and then determining whether the stored data is normal from the calculated RAM parity, it is determined whether the stored data in the RAM 507 is normal. Regardless of the process that needs to be performed in common, it is determined whether or not the data stored in the RAM 507 is normal based on the RAM parity.

  For this reason, processing that needs to be performed in common regardless of whether the stored data in the RAM 507 is normal or not is executed separately when the stored data in the RAM 507 is determined to be normal and when it is determined to be abnormal. Since it is not necessary, the capacity of the program used for processing at the time of activation can be reduced.

  In addition, after the main control unit 41 is activated, after the access to the RAM 507 is permitted, the RAM parity is calculated before other processing is performed, so the state before any access to the RAM 507 is performed. Since it is determined whether the stored data is normal based on the calculated RAM parity, it is possible to improve the reliability of the determination of whether the data is normal.

  In the power interruption process, the RAM parity adjustment data is calculated and stored so that the RAM parity based on all the data including the unused area and the unused stack area of the RAM 507 becomes 0, and the RAM 507 is restored at the time of restoration. It is determined whether or not the data in the RAM 507 is normal by determining whether or not the RAM parity calculated based on the data stored in all areas including the unused area and the unused stack area is 0. Therefore, the determination can be performed accurately and easily, and even if an illegal program or data is stored in an unused area or an unused stack area, the illegal program or data is restored while being stored. Can be prevented.

  In addition, after calculating the RAM parity and before determining whether or not the stored data is normal from the calculated RAM parity, the RAM 507 is stored in the RAM 507 as a common process regardless of whether or not the stored data is normal. Each switch input data, confirmation data, edge data, that is, data indicating the detection status of each switch is cleared, and the data in the RAM 507 is normal when the main control unit 41 is started. Whether returning to the control state or not returning to the previous control state, it is possible to immediately start checking the detection state of the switch after the interruption is permitted.

  In the slot machine 1 of the present embodiment, the CPU 505 reads the security check program 506A stored in the ROM 506 or the like when the system is reset, that is, when a system reset signal is input upon power-on. By executing, it becomes a security mode.

  At this time, a security check process is executed as a process corresponding to the security check program 506A. Here, the security time when the main control unit 41 enters the security mode is stored in advance in the bit number [2-0] or the bit number [4-3] of the security time setting KSES stored in the program management area of the ROM 506. Depending on the bit value, a time component different from the fixed time can be included.

  For example, if the bit value in the bit number [2-0] of the security time setting KSES is a value other than “000”, it can be selected in advance in addition to the fixed time corresponding to the setting contents shown in FIG. Any one of a plurality of extended times can be set as a time component included in the security time. If the bit value in the bit number [4-3] of the security time setting KSES is a value other than “00”, the system reset or power-on is performed corresponding to the short mode or the long mode shown in FIG. A variable setting time that changes in a predetermined time range each time is performed can be set as a time component included in the security time.

  Until the security time set in this way elapses, the execution of the user program stored in the ROM 506 is not started. Then, the operation of generating numerical data to be a random number value by the random number circuit 509 should not be started during the period in which the main control unit 41 is in the security mode. As a result, it becomes difficult to specify the operation start timing of the random number circuit 509 or the numerical data to be updated from the operation start timing due to system reset such as power-on, and so on. By connecting the “board” and inputting an illegal signal at a predetermined timing, it is possible to reliably prevent acts such as illegally winning a special role.

  As an example, the bit value in the bit number [2-0] of the security time setting KSES is set to a different value for each model of the slot machine 1. In this case, the extension time of the security mode can be made different for each model of the slot machine 1, and it becomes difficult to specify the operation start timing of the random number circuit 509 from the operation start timing of the slot machine 1. Further, by setting the bit value in the bit number [4-3] of the security time setting KSES to “01” or “10”, the variable setting time can be varied for each system reset. This makes it extremely difficult to specify the operation start timing of the random number circuit 509 from the operation start timing of the slot machine 1.

  FIG. 51 is a timing chart for explaining the operation of the random number circuit 509 built in the main control unit 41. FIG. 51A shows a control clock CCLK generated by the control clock generation circuit 42 mounted on the game control board 40. FIG. 51B shows the random number clock RCLK generated by the random number clock generation circuit 43. As shown in FIGS. 51A and 51B, the oscillation frequency of the control clock CCLK and the oscillation frequency of the random number clock RCLK are different from each other. It does not become an integral multiple of the other oscillation frequency.

As shown in FIG. 51B, the random number clock RCLK rises from a low level to a high level at timings T10, T11, T12,. The random number clock RCLK is supplied to the random number external clock terminal ERC of the main control unit 41 and is input to the clock terminal CK in the clock flip-flop 552 provided in the random number circuit 509 shown in FIG. The clock flip-flop 552 responds to the rising edge of the random number clock RCLK input to the clock terminal CK with the latch clock RC0 fed back from the negative phase output terminal (inverted output terminal) Q bar to the D input terminal. Are taken in (latched) and output as a random number update clock RGK from the positive phase output terminal (non-inverted output terminal) Q. Thereby, as shown in FIG. 51C, the random number update clock RGK rises from the low level to the high level at the timing T10, T12, T14,..., And is half the oscillation frequency of the random number clock RCLK. The signal has an oscillation frequency. For example, if the oscillation frequency of the random number clock RCLK is 20 MHz, the oscillation frequency of the random number update clock RGK is 10 MHz. Then, since the oscillation frequency of the random number clock RCLK is not even 1 to an integer multiple of an integer fraction of the oscillation frequency of the control clock CCLK, the oscillation frequency of the random number update clock RGK is the oscillation frequency of the control clock CCLK Have different frequencies. The random number generation circuit 553 updates the numerical data in the count value permutation RCN in response to, for example, the rising edge of the random number update clock RGK. The random number sequence changing circuit 555 changes the numerical data update order in the count value permutation RCN output from the random number generation circuit 553 based on the setting of the random number update rule by the random number sequence change setting circuit 556 as a random number sequence RSN. Output. Thus, the numerical data in the random number sequence RSN is updated in response to the rising edge of the random number update clock RGK, for example, as shown in FIG.

Thus, the random number clock RCLK generated by the random number clock generation circuit 112.
And the oscillation frequency of the control clock CCLK generated by the control clock generation circuit 42 are different from each other, and one oscillation frequency does not become an integral multiple of the other oscillation frequency. Therefore, the oscillation frequency of the random number update clock RGK and the latch clock RC0 generated by the clock flip-flop 552 of the random number circuit 509 is ½ of the oscillation frequency of the random number clock RCLK, but the oscillation of the control clock CCLK. The frequency and the oscillation frequency of the internal system clock SCLK that is ½ of the oscillation frequency of the control clock CCLK are different. In this way, the control clock CCLK, the internal system clock SCLK, and the random number update clock RGK are prevented from being synchronized. From the operation timing of the CPU 505, the random number circuit 509 generates the random number generation circuit 553 and the random number sequence change circuit 555. It becomes difficult to specify the update timing of the numerical data in the random number sequence RSN to be performed. As a result, it is possible to reliably prevent aiming and the like based on the result of analyzing the update operation of the numerical data serving as the random number value in the random number circuit 509 from the operation timing of the CPU 505.

Furthermore, the oscillation frequency of the control clock CCLK, to compare the oscillation frequency of the random number update clock RGK, when monitors whether both oscillation frequencies are synchronized, both the oscillation frequency is synchronized random number It is preferable to determine that an abnormality has occurred in the input state of the update clock PGK and disable the progress of the game, and in this way, an abnormality has occurred in the update operation of numerical data that is a random value Thus, it is possible to prevent the progress control of the game from being performed.

  The latch clock RC0 output from the clock flip-flop 552 is an inverted signal of the random number update clock RGK, the oscillation frequency is the same as the oscillation frequency of the random number update clock RGK, and its phase is the same as the phase of the random number update clock RGK and π It differs by (= 180 °). The latch clock RC0 is branched into a latch clock RC1 and a latch clock RC2 at a branch point BR1. Therefore, for example, as shown in FIG. 51E, each of the latch clocks RC0, RC1, and RC2 becomes an oscillation signal whose signal state changes in a common cycle. The latch clock RC1 is input to the clock terminal CK of the latch flip-flop 557A. The latch clock RC2 is input to the clock terminal CK of the latch flip-flop 557B.

  Thus, the oscillation frequencies of the latch clocks RC1 and RC2 generated by branching the latch clock RC0 are different from the oscillation frequencies of the control clock CCLK and the internal system clock SCLK. Therefore, the control clock CCLK, the internal system clock SCLK, and the latch clocks RC1 and RC2 are prevented from being synchronized, and the random number circuit 509 takes in numerical data as a random value from the operation timing of the CPU 505. It becomes difficult to specify the timing. As a result, it is possible to reliably prevent aiming and the like based on the result of analyzing the operation of fetching numerical data as a random value in the random number circuit 509 from the operation timing of the CPU 505.

  The latch flip-flop 557A takes in (latches) the game start signal SS1 transmitted from the start switch 7 and supplied to the input port P0 in response to the rising edge of the latch clock RC1, and latches the game start signal. Output from the output terminal Q as SL1. If the fetching method in random number latch selector 558A is designated as signal input to input port P0, game start latch signal SL1 is output as random number latch signal LL1. Thereby, for example, a game start signal SS1 whose signal state changes between an off state (low level) and an on state (high level) at the timing shown in FIG. 51F is a timing T11 at which the latch clock RC1 rises. After being fetched into the latching flip-flop 557A at T13, T15,..., The random number latch signal LL1 whose signal state changes between the off state and the on state at timings T11 and T13 as shown in FIG. And output from the random number latch selector 558A.

  The random value register 559A serving as the random value register R1D responds to the rising edge of the random number latch signal LL1 input from the random number latch selector 558A to the clock terminal with the numerical data in the random number sequence RSN output from the random number sequence change circuit 555. Then, the numerical data serving as stored data is updated (latched).

  For example, as shown in FIG. 51 (G), when a rising edge occurs in which the random number latch signal LL1 changes from the OFF state to the ON state at timing T11, the random number sequence change circuit 555 outputs the timing edge T11. As shown in FIG. 51H, the numerical data in the random number sequence RSN is taken into the random value register R1D and acquired as numerical data that becomes a random value. Accordingly, the random value register 559A serving as the random value register R1D can acquire and store numerical data used as a random number value based on the detection of the operation of the start switch 7.

  In this way, the latch flip-flop 557A takes in (latches) the game start signal SS1 transmitted from the start switch 7 and supplied to the input port P0 in response to the rising edge of the latch clock RC1 to play the game The start latch signal SL1 is output from the output terminal Q. At this time, regardless of whether the operation of the start switch 7 is valid or not, the game start transmitted from the start switch 7 and supplied to the input port P0 is started. The signal SS1 is captured (latched), and output from the output terminal Q as a game start latch signal SL1, and accordingly, the random number latch selector 558A receives the numerical data in the random number sequence RSN output from the random number sequence change circuit 555. The numerical data of the random value register 559A that is latched and becomes the random value register R1D So that the update. That is, the latch flip-flop 557A only needs to detect the rise of the start switch 7 regardless of whether or not the operation of the start switch 7 is in a valid state, and thus the detection circuit for the signal that triggers the latch has a simple configuration. it can.

  Further, if the bit value in the bit number [0] of the second random number initial setting KRS2 as shown in FIG. 9B is “1”, for example, numerical data that becomes a random value generated by the random number circuit 509 is displayed. The start value can be changed at every system reset. Thereby, even if the operation start timing of the random number circuit 509 can be specified, it becomes difficult to specify the numerical data read from the random value register 559A included in the random number circuit 509, and based on the analysis result of the program By connecting a so-called “hanging board” and inputting a fraud signal at a predetermined timing, it is possible to reliably prevent an act such as illegally winning a special role.

  As described above, in this embodiment, by setting the bit value in the bit number [4-3] of the security time setting KSES to a value other than “00”, it changes within a predetermined time range every time the system is reset due to power-on or the like. The variable setting time to be set can be set as a time component included in the security time. As a result, it becomes difficult to specify the operation start timing of the random number circuit 509 or the numerical data to be updated from the operation start timing due to system reset accompanying power-on or the like. By connecting the “hanging board” and inputting an illegal signal at a predetermined timing, it is possible to reliably prevent an act such as illegally winning a special role.

  Also, by setting the bit value in the bit number [2-0] of the security time setting KSES to a value other than “000”, any one of a plurality of extension times that can be selected in advance in addition to the fixed time is set as the security time. It can be set as an included time component. As a result, it becomes difficult to specify the operation start timing of the random number circuit 509 or the numerical data to be updated from the operation start timing due to system reset accompanying power-on or the like. By connecting the “hanging board” and inputting an illegal signal at a predetermined timing, it is possible to reliably prevent an act such as illegally winning a special role.

  Further, the oscillation frequency of the random number clock RCLK generated by the random number clock generation circuit 43 and the oscillation frequency of the control clock CCLK generated by the control clock generation circuit 42 are different from each other. The oscillation frequency does not become an integral multiple of the other oscillation frequency. Therefore, the oscillation frequency of the random number update clock RGK and the latch clock RC0 generated by the clock flip-flop 552 of the random number circuit 509 is ½ of the oscillation frequency of the random number clock RCLK, but the oscillation of the control clock CCLK. The frequency and the oscillation frequency of the internal system clock SCLK that is ½ of the oscillation frequency of the control clock CCLK are different. In this way, the control clock CCLK, the internal system clock SCLK, and the random number update clock RGK are prevented from being synchronized. From the operation timing of the CPU 505, the random number circuit 509 generates the random number generation circuit 553 and the random number sequence change circuit 555. It becomes difficult to specify the update timing of the numerical data in the random number sequence RSN to be performed. As a result, it is possible to reliably prevent aiming and the like based on the result of analyzing the update operation of the numerical data serving as the random number value in the random number circuit 509 from the operation timing of the CPU 505. Also, the oscillation frequencies of the latch clocks RC1 and RC2 generated by branching the latch clock RC0 are different from the oscillation frequencies of the control clock CCLK and the internal system clock SCLK. In this way, synchronization between the control clock CCLK and the internal system clock SCLK and the latch clocks RC1 and RC2 is prevented, and the random number circuit 509 takes in numeric data as a random value from the operation timing of the CPU 505. It becomes difficult to specify the timing. As a result, it is possible to reliably prevent aiming and the like based on the result of analyzing the operation of fetching numerical data as a random value in the random number circuit 509 from the operation timing of the CPU 505.

  The random number circuit 509 built in or externally attached to the main control unit 41 outputs from the random number generation circuit 553 in response to the bit value [0] of the second random number initial setting KRS2 being “1”. The start value of the numerical data in the count value permutation RCN and the random number sequence RSN output from the random number sequence change circuit 555 can be changed every time the system is reset. Thereby, even if the operation start timing of the random number circuit 509 can be specified, it becomes difficult to specify the numerical data read from the random value register 559A included in the random number circuit 509, and based on the analysis result of the program It is possible to surely prevent an aiming signal or an illegal signal from being input by connecting a so-called “hanging board”.

  In the external bus interface 501 provided in the main control unit 41, the internal resource access control circuit 501A restricts external reading by internal components other than the internal circuit such as the CPU 505 with respect to internal data of the main control unit 41 such as data stored in the ROM 506, for example. Thereby, for example, a program for controlling a game, such as a user program stored in the ROM 506, can be prevented from being read from the outside of the main control unit 41 and provided for analysis or the like. Further, it is possible to reliably prevent aiming based on the analysis result of the game control processing program and input of an illegal signal due to connection of a so-called “hanging board”.

  In the random number circuit 509 built in or externally attached to the main control unit 41, when the frequency monitoring circuit 551 detects a frequency abnormality in the random number clock RCLK, the random number circuit 509 is stored in the bit number [4] of the internal information register CIF. The bit value of the information data CIF4 is set to “1”. Then, when the CPU 505 determines that the number of times that the read value of the internal information data CIF4 is continuously determined to be “1” has reached the clock abnormality determination value, the operation state of the random number circuit 509 is abnormal. Is determined to have occurred. When it is determined that an abnormality has occurred in the operation state of the random number circuit 509, the operation of the main control unit 41 is stopped. Thereby, it is possible to reliably prevent an illegal act by inputting an illegal signal as the random number clock RCLK.

  The CPU 505 built in the main control unit 41 writes the bit value “1” to the random value fetch specification register RDLT corresponding to the output of the latch signal to the random number circuit 509, and reads the random value register 559A a plurality of times. Then, all the bits of the read numerical data are monitored, and it is determined that an abnormality has occurred in the operation state of the random number circuit 509 based on the presence / absence of bit data that does not change. When it is determined that an abnormality has occurred in the operation state of the random number circuit 509, the operation of the main control unit 41 is stopped. As a result, it is possible to reliably and easily detect that an abnormality has occurred in the operating state of the random number circuit 509 and prevent fraud. In particular, by performing the internal lottery while the numerical data is not normally updated by the random number circuit 509, that is, while the numerical data is fixed, it is possible to prevent fraud such as always winning a special combination.

  The random number circuit 509 built in or externally attached to the main control unit 41 is a numerical data that becomes a random value every time the system is reset when the bit value [0] of the second random number initial setting KRS2 is “1”. Change the start value of. At this time, for example, a start value that is changed at each system reset may be determined using a count value of a free-run counter built in the main control unit 41, for example. As a result, the initial value can be determined by using different initial value determination data depending on the timing of system reset or the like, and illegal acts due to shooting or the like can be prevented.

  In this embodiment, the extension time of the security mode is one of a plurality of extension times that can be selected in advance, corresponding to the bit value [2-0] of the security time setting KSES. Was not changed at each system reset, but the extension time added to the fixed time is determined as one of a plurality of extension times at each system reset, for example, by setting in the user program stored in the ROM 506 You may do it. In this case, the extension time is defined to be longer than the longest variable setting time. Then, after determining a rough extension time, a detailed extension time may be determined. As a result, the security time for entering the security mode at the time of system reset due to power-on or the like can be greatly changed for each system reset, and the operation start timing of the random number circuit 509 is updated or updated from the operation start timing of the slot machine 1. It becomes more difficult to specify the numerical data.

  Further, the extension time of the security mode may be determined using an ID number assigned to each chip constituting the main control unit 41. As an example, an extension time corresponding to the calculated value is executed by executing a part or all of an operation for performing a predetermined scramble process on the ID number and an operation such as addition / subtraction / multiplication / division using the ID number. May be set. In this case, the extension time may be randomly determined for each system reset, for example, by changing an arithmetic expression used for determining the extension time for each system reset. Furthermore, the count value of the free run counter, the ID number, and the like, for example, the arithmetic expression for determining the extension time using the ID number is determined corresponding to the count value of the free run counter stored at the time of system reset. The extended time may be determined randomly at each system reset by using a combination of In addition, when changing the start value of the random number generated by the random number circuit 509 at every system reset, the start value of the random number can be changed by using a combination of the count value of the free run counter and the ID number. You may decide.

  At the time of system reset, random number circuit setting processing for starting the security mode and setting the random number circuit 509 is performed, and in the random number circuit setting processing, setting of a random number update rule, setting of a random number start value, and the like are performed. When the user is reset, the security mode is omitted and the user mode is started. That is, at the time of system reset, the initial value of the random number is reset, but at the time of user reset, the random number circuit 509 is not set, and the numerical data that becomes the random number is continuously updated as it was before the reset. The Rukoto. As a result, a user reset can be performed by intentionally recognizing a power outage state by intentionally causing a momentary power failure by lowering the voltage by temporarily short-circuiting the electric circuit by discharge using an electronic lighter or the like. Even if it is performed, it becomes difficult to specify the numerical data to be the random number value in the random number circuit 509 from the user reset timing, and it is possible to more effectively prevent fraudulent acts such as aiming.

  In addition, the random number circuit including the setting of the random number start value is set in the security mode, the update of the numerical data is started, and then the execution of the timer interrupt process is permitted after the transition to the user mode. It has become. In other words, the start value of the random number is set before the execution of the timer interrupt process is permitted, and the update of numerical data starts from the set start value of the random number. Therefore, it is executed during the timer interrupt process. Although it can be specified to some extent from the determination status of the switches to the timing when the timer interrupt processing is permitted, the timing at which the update of the numerical data of the random number circuit 509 cannot be specified cannot be specified. It is difficult to specify the numerical data that is the random number value in, and it is possible to more effectively prevent fraudulent acts such as aiming.

  In this embodiment, a random number clock having an oscillation frequency different from the oscillation frequency of the control clock CCLK generated by the control clock generation circuit 42 by the random number clock generation circuit 43 provided outside the main control unit 41. Although RCLK is generated and supplied to the random number circuit 509, the clock signal supplied to the CPU 505 of the main control unit 41 and the clock signal supplied to the random number circuit 509 are shared by the common clock generation circuit. You may make it produce | generate using the oscillation signal produced | generated by one included oscillator. In this case, for example, a frequency divider for generating the random number clock RCLK and the control clock CCLK is provided, and the latch clocks RC0, RC1, RC2 are synchronized with the control clock CCLK or the internal system clock SCLK. What is necessary is just to set the frequency division ratio etc. in each frequency divider so that it may become difficult to produce. The control clock generation circuit 42 and the random number clock generation circuit 43 may be provided in whole or in part inside the main control unit 41 or outside the main control unit 41.

  In the present embodiment, the random number circuit 509 is supplied with the random number clock RCLK generated by the random number clock generation circuit 43, and the random number update clock RGK and the latch clock RC0 are generated by the clock flip-flop 552. However, an oscillation signal that becomes the random number update clock RGK or the latch clock RC0 may be generated outside the random number circuit 509, such as the random number clock generation circuit 43, for example. Alternatively, a circuit for generating the random number update clock RGK and a circuit for generating the latch clock RC0 may be separately provided in the random number circuit 509. As an example, while generating a random number update clock RGK by a flip-flop similar to the clock flip-flop 552, an inversion circuit for inverting the signal state of the random number update clock RGK is provided, and a signal output from the inversion circuit is latched. It may be used as the clock RC0.

  In the random number circuit 509 applied to the present embodiment, when the random number latch flag data RDFM0 is “1”, that is, when the numerical value data is captured in the random value register R1D, a new random value capture request is generated. Even in this case, new numerical data is not taken into the random value register R1D. In such a state, the numerical data in the random value register R1D is read and the random number latch flag data RDFM0 is cleared. It becomes impossible to load new numerical data into the random value register R1D.

  Therefore, as shown in FIG. 52, the game start signal SS1 is input by operating the start switch 7, the numerical data is latched and stored in the random value register R1D, and then the stored numerical data is read out. Until the numerical data of the random value storage work is updated, the random number latch flag data RDFM0 is in a state of “1”, so that the stored numerical data is held, and the game start signal SS1 is input during that time. However, since the new numerical data is not overwritten, the numerical data does not change even if noise is applied to the signal line of the game start signal SS1 due to static electricity or the like.

  Note that the configuration in which new numerical data is not captured in the random value register R1D while the numerical data is captured in the random value register R1D may be configured to prohibit latching of the new numerical data. However, although new numerical data is latched, writing to the random value register R1D may be prohibited.

  As described above, in the present embodiment, in a state where the numerical data is taken into the random value register R1D, a configuration is adopted in which the stored numerical data is held until the stored numerical data is read out. However, in this case, even if the operation of the start switch 7 is performed during a period in which the game is not effective, the data is latched and numerical data is held in the random value register R1D. When the operation is enabled and the start switch 7 is operated, an internal lottery is performed based on numerical data latched at a timing different from the timing at which the start switch 7 was originally operated to start the game. New problems will arise.

  On the other hand, in the present embodiment, the random number value register in the random value reading process executed once every four times (about 2.24 ms) of the timer interrupt process which is executed by interrupting the basic process every about 0.56 ms. It is confirmed whether or not the numerical data is latched in R1D, that is, whether or not the random number latch flag is set. If the numerical data is latched in the random value register R1D, the numerical data in the random value register R1D is stored. It is designed to read. As a result, the random number latch flag is cleared, and new numerical data can be taken in. That is, at predetermined time intervals (about 2.24 ms), it is confirmed whether or not numerical data is latched in the random value register R1D, and if it is latched, the numerical data in the random value register R1D is read out, The state where the numerical data is held in the register R1D is released, and a new numerical data can be taken into the random value register R1D.

  For this reason, as shown in FIG. 53, the start switch 7 is operated in a state where the start of the game is not permitted, and the numerical data is stored in the random value register R1D. Since the numerical data newly latched in the random value register R1D can be stored within about 2.24 ms, which is the execution interval of the random value reading process, the start switch 7 before the start of the game is permitted. Even if the numerical data latched by the operation is held in the random value register R1D, the numerical data newly latched can be obtained at the timing when the start switch 7 is operated after the start of the game is permitted.

  Further, in the random value reading process, when numerical data is latched in the random value register R1D, not only the numerical data is read, but also the value of the random value storage work in the RAM 507 is updated to the read numerical data. Each time new numerical data is latched in the random value register R1D, the latched numerical data is read in the subsequent random value reading process, and the numerical data stored in the random value storage work is newly latched. It is designed to be updated to numerical data.

  At the start of the game, instead of the numerical data stored in the random value register R1D, the numerical data stored in the random value storage work of the RAM 507 is acquired and the internal lottery is performed. After the data is read, even if the numerical data changes due to noise on the signal line of the start switch, it will not affect the numerical data of the random number storage work used for internal lottery. Even in such a case, the internal lottery can be performed using the numerical data latched at the timing when the start switch 7 is operated.

  In this embodiment, the value of the random value register R1D is not retained when the power is interrupted, but the RAM 507 to which the random value storage work is assigned retains the stored data even when the power is interrupted. Therefore, even after the operation of the start switch 7 is detected and before the internal lottery starts, even if the value of the random value register R1D disappears due to a momentary power interruption or the like, the numerical data of the random value storage work is maintained. Numerical data latched at the timing when the start switch 7 is operated can be used for the internal lottery.

  In this embodiment, when the operation of the start switch 7 is detected, the numerical data stored in the random value storage work of the RAM 507 is set in the lottery work assigned to the RAM 507, and the internal lottery thereafter. In this case, it is determined whether or not the winning combination has been won by performing an operation on the numerical data set in the lottery work, and the internal lottery ends when the operation of the start switch 7 is detected. Even if the numerical data stored in the random number storage work is updated by the time, the numerical data acquired at the time when the operation of the start switch 7 is detected is not changed until the internal lottery ends. However, when the operation of the start switch 7 is detected, the numerical data stored in the random value storage work of the RAM 507 is transferred to the CPU 505. Set the work register, it may be to determine whether or not the player wins the role by performing an operation on numerical values set in the work register data in the subsequent internal lottery.

  Further, it may be determined whether or not the winning combination is obtained by performing an operation on the numerical data stored in the random value storage work. In this case, the operation of the start switch 7 is performed. The numerical data stored in the random number storage work is updated with the newly latched numerical data, for example, by prohibiting timer interrupt processing (main) during the period from the time of detection until the end of the internal lottery By preventing this from happening, it is possible to prevent the numerical data acquired when the operation of the start switch 7 is detected from being changed before the internal lottery is completed.

  In this embodiment, when the detection signals of the switches are input at a rate of once every four times of the timer interrupt processing (main) and the states of the detection signals coincide with each other twice, that is, about 2.24 ms. When the state of the period detection signal is the same, the detection state of the corresponding switch is determined. For this reason, it takes about 2.24 ms to detect the operation of the start switch 7 (change from off to on). However, if the random number reading process is shorter than this time, the start switch is turned from off to on. There is a possibility that the numerical data of the random number storage work is updated to the newly latched numerical data due to noise or the like between the time of the change and the detection. On the other hand, if the random number reading process is longer than this time, the numerical data latched at the timing of operating the start switch 7 may not be reflected in the numerical data of the random number storage work.

  On the other hand, the random number value reading process is also executed at a rate of once every four times of the timer interrupt process (main), and the minimum time required for updating the numerical data of the random number value storing work is about 2.24 ms. Yes, the numerical data of the random number storage work is not updated to the newly latched numerical data from when the start switch 7 changes from off to on, and the start switch 7 is operated. The numerical data latched at this timing can be reflected in the numerical data of the random value storage work.

  In this embodiment, the start switch 7 is operated in a state where the start of the game is not permitted, and numerical data is stored in the random value register R1D. Since the numerical data newly latched in the random value register R1D can be stored within the processing execution interval of about 2.24 ms), the operation of the start switch 7 before the start of the game is permitted. Even if the latched numerical data is held in the random number value register R1D, the newly latched numerical data can be acquired at the timing when the start switch 7 is operated after the start of the game is permitted. However, when the numerical data is taken into the random value register R1D, the random number interrupt is generated, and the random value register is generated when the random number interrupt is generated. By reading the numerical data stored in R1D and making it possible to store the numerical data newly latched in the random value register R1D, it is latched by the operation of the start switch 7 before the start of the game is permitted. Even if the numerical data is held in the random value register R1D, the numerical data newly latched at the timing when the start switch 7 is operated after the start of the game is permitted may be obtained.

  In order to generate a random number interrupt, the bit value of the random number interrupt control data RDIC0 may be set to “1”. When the data is taken in, random number interruption occurs.

  Then, the main control unit 41 may execute the random value latch interrupt process by interrupting the basic process when the random number interrupt occurs. If another interrupt process is being executed when a random interrupt occurs, the random value latch interrupt process may be executed after the interrupt process being executed is completed.

  FIG. 54 is a flowchart showing the control contents of the above-described random value latch interrupt process executed by the main control unit 41 in response to the generation of a random number interrupt. Note that other interrupts are automatically prohibited during the execution period of the random value latch interrupt process.

  In the random value latch interrupt process, first, after saving the register in use to the stack area (Sk1001), the numerical data is read from the random value register 559A (Sk1002), and the value stored in the random number value storage work is The numerical data read in Sk1002 is updated (Sk1003), the register saved in the stack area is restored in Sk1001 (Sk1004), and the process before the interrupt is returned.

  In this way, when the numerical data is taken into the random value register R1D, a random interrupt is generated, and the main control unit 41 interrupts the basic process and executes the random value latch interrupt process. By reading the numerical data in the register R1D, the random number latch flag is cleared, and a new numerical data can be taken in. That is, every time numerical data is fetched into the random value register R1D, the random value latch interrupt processing is executed to read the numerical data in the random value register R1D, so that the numerical data is held in the random value register R1D. The state is released, and new numerical data can be taken into the random value register R1D.

  Therefore, as shown in FIG. 55, the start switch 7 is operated in a state where the start of the game is not permitted, and the numerical data is stored in the random value register R1D. Even if this state is maintained, the numerical data is latched. Since the numerical data of the random number register R1D is read out by the occurrence of an interrupt due to the occurrence of the interruption, it becomes possible to store the newly latched numerical data, so the start switch 7 before the start of the game is permitted Even if the numerical data latched by the above operation is held in the random value register R1D, it is possible to acquire the newly latched numerical data at the timing when the start switch 7 is operated after the start of the game is permitted. .

  Further, in the random value latch interrupt processing, not only the numerical data latched in the random value register R1D but also the random value storage work value in the RAM 507 is updated to the read numerical data, so that the random value register R1D Each time new numerical data is latched, the numerical data stored in the random value storage work is updated to the latest latched numerical data.

  At the start of the game, instead of the numerical data stored in the random value register R1D, the numerical data stored in the random value storage work of the RAM 507 is acquired and the internal lottery is performed. After the data is read, even if the numerical data changes due to noise on the signal line of the start switch, it will not affect the numerical data of the random number storage work used for internal lottery. Even in such a case, the internal lottery can be performed using the numerical data latched at the timing when the start switch 7 is operated.

  In this modified example, when the operation of the start switch 7 is detected, the numerical data stored in the random value storage work of the RAM 507 is set as the lottery work assigned to the RAM 507, and the internal lottery thereafter. In this case, it is determined whether or not the winning combination has been won by performing an operation on the numerical data set in the lottery work, and the internal lottery ends when the operation of the start switch 7 is detected. Even if the numerical data stored in the random number storage work is updated by the time, the numerical data acquired at the time when the operation of the start switch 7 is detected is not changed until the internal lottery ends. However, when the operation of the start switch 7 is detected, the numerical value data stored in the random value storage work of the RAM 507 is transferred to the CPU 50. The set in the work register, may be to determine whether or not the player wins the role by performing an operation on numerical values set in the work register data in the subsequent internal lottery.

  Further, it may be determined whether or not the winning combination is obtained by performing an operation on the numerical data stored in the random value storage work. In this case, the operation of the start switch 7 is performed. The numerical data stored in the random value storage work is newly latched, for example, by prohibiting random value interrupt processing that accompanies the generation of random number interrupts during the period from the time of detection until the end of the internal lottery. By preventing the numerical data from being updated, it is possible to prevent the numerical data acquired when the operation of the start switch 7 is detected from being changed before the internal lottery is completed.

  In this modification, the numerical value data in the random value register R1D is read in the random value latch interrupt process. However, in the random value latch interrupt process, the numerical data is latched in the random value register R1D. A latch flag indicating that is set in the RAM 507, whether or not the latch flag is set in the RAM 507 in a basic process such as a BET process or a timer interrupt process (main) is determined, and it is determined that the latch flag is set in the RAM 507 In such a case, the numerical data in the random value register R1D may be read out. Even in such a configuration, the start switch 7 is operated in a state where the start of the game is not permitted, and the numerical value is stored in the random value register R1D. The data is stored and the state is not retained and the game Started newly becomes possible to obtain the numerical data latched at the timing of the start switch 7 has been operated after being allowed.

  Further, in this embodiment, the user reset signal is returned even if the control state of the main control unit 41 is restored to the control state before the power interruption when the power is turned on or the operation of the main control unit 41 is temporarily stopped at the momentary power failure. , It is possible to return to the control state before the operation is stopped, and the state may return to a state where a prescribed number of bets satisfying the game start condition are set.

  On the other hand, the power supply voltage is unstable during power interruption or instantaneous power failure. In such a situation, the input of the game start signal SS1 is detected by noise or the like, and numerical data is latched, and the random value register R1D. There is a risk that it will be stored and held as it is.

  On the other hand, in this embodiment, after completion of the power interruption process (main), it is confirmed whether or not numerical data is latched in the random value register R1D, that is, whether or not the random number latch flag is set. When numerical data is latched in the numerical register R1D, the process of reading the numerical data in the random number register R1D as a dummy is stopped by the operation of the main control unit 41 due to a voltage drop or by the input of a user reset signal. Until it starts, it repeats. As a result, the random number latch flag is cleared, and new numerical data can be taken in.

  For this reason, after power interruption processing (main) is performed due to a momentary power interruption or the like, when restarting by input of a user reset signal, numerical data is latched in the random value register R1D due to noise or the like in the meantime. (In particular, when the power interruption process starts at a voltage higher than the voltage of the switches and the voltage recovers after the voltage drops below the switch voltage, all the switches are in the same state as the ON state. However, the numerical data may be latched in the random value register R1D.) However, since the numerical data newly latched in the random value register R1D can be stored by being read immediately, Numerical data latched by noise or the like during stoppage, that is, a switch in which the start switch 7 is operated in a state where the game can be started. Never internal lottery will be performed using numerical data latched at a timing different from that of the timing.

  In this embodiment, after the power interruption process (main) is completed, it is confirmed whether or not the numerical data is latched in the random value register R1D, that is, whether or not the numerical data is stored in the random value register R1D. Only when the random number latch flag is set, the numerical data stored in the random value register R1D is read. However, after the power interruption process (main) is finished, the numerical data is stored in the random value register R1D. Regardless of whether it is stored or not, the process of reading the numerical data stored in the random value register R1D may be performed repeatedly.

  In the above description, an example in which the main control unit 41 is restarted by the input of a user reset signal has been described. However, as shown in FIG. 50B, in a standby state after the end of the power interruption process (main). The main control unit 41 may be restarted by monitoring the input of the voltage drop signal and jumping to the head of the user mode when the input of the voltage drop signal is no longer detected.

  Furthermore, in this embodiment, after the main control unit 41 is activated, the random number latch flag is set before the game progress control is started, regardless of whether or not the control state before power interruption or user reset is restored. Whether the numerical data is stored in the random value register R1D. If the numerical data is stored in the random value register R1D, the numerical data stored in the random value register R1D Since the numerical data newly latched can be stored in the random value register R1D, it is latched and held in the random value register R1D before the game progress control is started after starting. Numerical data, that is, numerical data latched at a timing different from the timing at which the start switch 7 is operated in a state where the game can be started. There is no possibility that internal lottery will be performed using the data.

  In this embodiment, after the main control unit 41 is activated, before the game progress control is started, whether or not the random number latch flag is set, that is, the latched numerical data is stored in the random value register R1D. Only when the random number latch flag is set, the numerical data stored in the random value register R1D is read out, but the numerical value stored in the random value register R1D is uniformly read. Data may be read out.

  If the random number latch flag is set regardless of whether or not the main control unit 41 is activated and then returns to the control state before power interruption or user reset, the numerical data stored in the random number register R1D However, the numerical data stored in the random value register R1D may be read only when returning to the control state before power interruption or before user reset. The numerical data stored in the random value register R1D may be read out only when the control state before the user reset is restored and when the return control state is a state where the game can be started.

  In this embodiment, after the access to the RAM 507 is prohibited in the power interruption process (main), the operation stop state or the user reset is waited. However, as described above, the output state of the voltage drop signal is monitored. Thus, the voltage recovery signal may be determined when the voltage drop signal is no longer input, and the program may be started from the user mode of the startup process (main). When the random number latch flag is set, it is determined whether or not the random number latch flag is set. When the random number latch flag is set, the numerical value stored in the random number value register R1D is read and then the startup process (main) It is preferable to have a configuration in which the program is started from the user mode of the game. The numerical data held in the random value register R1D before the start of the control can be surely read, and the numerical data newly latched in the random value register R1D can be stored. Numerical data latched and held in the random value register R1D before the progress control of the game is started, that is, a numerical value latched at a timing different from the timing when the start switch 7 is operated in a state where the game can be started. No internal lottery is performed using data.

  Further, in this embodiment, even after the activation of the main control unit 41 and before the progress control of the game starts, the operation is stopped or the user reset is waited for after the completion of the electric processing. The numerical value data held in the numerical value register R1D can be read and the numerical value data newly latched in the random number value register R1D can be stored, but only one of the random number value registers R1D can be stored. It is possible to read the numerical data held in the memory and store the numerical data newly latched in the random value register R1D. Even in such a configuration, the game can be started. The internal lottery is prevented from being performed using numerical data latched at a timing different from the timing at which the start switch 7 is operated. It can be.

The main control unit 41 of the present embodiment is set rising edge indicating the rise of the start switch 7 whether or not the start switch 7 has been operated in a state capable of starting the game determines based on whether Tei Luke not.

  The rising edge of the start switch 7 is detected by the start switch 7 in the switch input determination process that is executed once every four times (about 2.24 ms). It is set on condition that the definite data based on the state has changed from off to on. Since the deterministic data is data that is updated only when the previous detection state and the current state match each time the switch input determination processing is performed, the rising edge of the start switch 7 is detected when the detection state of the start switch 7 is off. When the switch is in the state, it is set by detecting that the start switch 7 is turned on twice in succession in the switch input determination process.

  On the other hand, since the execution interval of the switch input determination process is about 2.24 ms, the start switch 7 is provided on the condition that at least about 2.24 ms or more is continuously detected after the start switch 7 is turned on. Rising edge is set, and the operation of the start switch 7 is detected.

  As described above, in this embodiment, as shown in FIG. 56, on condition that the start switch 7 is continuously detected for a certain period (at least about 2.24 ms) in a state where the game can be started, The operation of the start switch 7 is detected and the game is started, and the game is prevented from starting even if the start switch 7 is erroneously detected due to noise such as static electricity. it can.

  In this embodiment, the operation of the start switch 7 is detected on the condition that the start switch 7 is continuously turned on for a certain period (at least about 2.24 ms) in a state where the game can be started. The game is started. For example, the detection state of the start switch 7 is confirmed a plurality of times in one switch input determination process, and on the condition that all are determined to be on, The operation may be detected and the game may be started. Even in such a configuration, the game starts when the start switch 7 is erroneously detected due to noise such as static electricity. Can be prevented.

  In this embodiment, as shown in FIG. 56, when the rising edge of the start switch 7 is detected in a state where the game can be started, whether or not the random number latch flag is set, that is, the start switch 7 The numerical data is latched by the above operation, and it is checked whether or not the numerical data is stored in the random value register R1D, and the game is started only when the numerical data is stored in the random value register R1D. Yes.

  Therefore, the numerical value data is not stored in the random number value register R1D, that is, the random number value used for the internal lottery is not latched, but the game is started and the internal lottery is not performed. The internal lottery can be reliably performed using the numerical data latched at the timing when the switch 7 is operated.

  Next, commands that the main control unit 41 transmits to the sub control unit 91 will be described.

  In this embodiment, the main control unit 41 sends a BET command, a credit command, an internal winning command, a freeze command, a reel rotation start command, a reel stop command, a winning determination command, a payout start command, a payout end to the sub control unit 91. A plurality of types of commands including commands, gaming state commands, standby commands, stop commands, error commands, return commands, setting commands, setting confirmation commands, door commands, and operation detection commands are transmitted.

  These commands consist of 1-byte type data indicating the command type and 1-byte extension data indicating the command content, and the sub-control unit 91 can determine the command type from the type data.

  The BET command is a command that can specify the number of inserted medals, that is, the number of medals used to set the bet number, and is a state from the end of the game (after setting change) to the start of the game. Sent when a medal is inserted or the bet number is set by operating the single BET switch 5 or the MAXBET switch 6 in a state where is not set. Further, since the BET command is transmitted when the betting number setting operation is performed, it is possible to specify that the betting number setting operation has been performed by receiving the BET command.

  The credit command is a command that can specify the number of medals stored as credits, and is a state from the end of the game (after setting change) to the start of the game, and in a state where a predetermined number of bets is set, Sent when a medal is inserted and credits are added.

  The internal winning command is a command that can specify the winning status of the internal winning flag and the type of the internal winning flag that has been established, and is transmitted when the start switch 7 is operated to start the game. Further, since the internal winning command is transmitted when the start switch 7 is operated, it is possible to specify that the start switch 7 has been operated by receiving the internal winning command.

  The freeze command is a command indicating whether or not to control the freeze state when it is determined to control to the freeze state, which will be described later, and the timing in the case of controlling to the freeze state. Sometimes sent.

  The reel rotation start command is a command for notifying the start of reel rotation, and is transmitted when rotation of the reels 2L, 2C, and 2R is started.

  The reel stop command is a command that can specify whether the reel to be stopped is the left reel, the middle reel, or the right reel, the area number of the corresponding reel stop operation position, and the area number of the corresponding reel stop position. And is transmitted each time stop control is performed in accordance with the stop operation of each reel. Since the reel stop command is transmitted when the stop switches 8L, 8C, and 8R are operated, it is possible to specify that the stop switches 8L, 8C, and 8R are operated by receiving the reel stop command. .

  The winning determination command is a command that can specify the presence / absence of winning, the type of winning, and the number of medals to be paid out at the time of winning, and is transmitted after all the reels are stopped and the winning determination is performed.

  The payout start command is a command for notifying the start of payout of medals, and is transmitted when the payout of medals is started by paying out a prize or credit (including medals used for setting the number of bets). The payout end command is a command for notifying the end of payout of medals, and is transmitted when the payout of medals by winning and winning a credit is completed.

  The game state command is a command that can specify the game state of the next game, and is transmitted at the end of the game.

  The standby command is a command indicating a transition to the standby state, and after one game is over, a credit (which was used for setting the bet number) is set when the transition to the standby state is made after a predetermined time without setting the bet number. (Including medals) is sent out after the medal payout is completed and the payout end command is sent.

  The stop command is a command indicating the occurrence or release of the stop state, and after the end of the BB, the stop command indicating the occurrence of the stop state is transmitted when the ending effect waiting time has elapsed, and the reset operation is performed. When the stop state is released, a stop command indicating the release of the stop state is transmitted.

  An error command is a command that indicates the occurrence or cancellation of an error condition and the type of error condition. When an error is determined and controlled to an error condition, an error command indicating the occurrence and type of the error condition is sent and reset. When the error state is canceled after the operation is performed, an error command indicating the cancellation of the error state is transmitted.

  The return command is a command indicating that the main control unit 41 has returned to the control state before the power interruption, and is transmitted when the main control unit 41 returns to the control state before the power interruption.

  The setting command is a command indicating the start or end of the setting change state and the setting value after the setting change. At the time of transition to the setting change state, a setting command indicating the start of the setting change state is transmitted, and when the setting change state ends. A setting command indicating the end of the setting change state and the setting value after the setting change is transmitted. Further, since the control state of the main control unit 41 is initialized with the transition to the setting change state, it can be specified that the control state of the main control unit 41 has been initialized by the setting command indicating the start of setting. .

  The setting confirmation command is a command that indicates the start or end of the setting confirmation state. A setting confirmation command that indicates the start of setting confirmation is transmitted when entering the setting confirmation state, and the setting confirmation end is indicated when the setting confirmation state ends. A confirmation command is sent.

  The door command is a command indicating the detection state of the door opening detection switch 25, that is, on (open state) / off (closed state), when the power is turned on, at the end of one game (after the game is over, the bet number of the next game) Sent before the setting of ”can be started), and when the detection state of the door opening detection switch 25 changes (from on to off, from off to on).

  The operation detection command is an operation switch (one BET switch 5, MAXBET switch 6, start switch 7, stop switch 8L, 8C, 8R) of which the detection state (on / off) has changed, from the detection state off. This command indicates whether it has changed to on or from on to off, and the detection state (on / off) of another switch, and is transmitted when the detection state of any of these operation switches has changed.

  Of these commands, commands other than the door command and the operation detection command are generated in the basic process, and the command data in the command buffer assigned to the non-initialized area is updated to the newly generated command data, and the serial communication circuit The data is transmitted to the sub-control unit 91 by being transferred to the transmission data register 561 of 511.

  On the other hand, the door command is generated in the door monitoring process of the timer interrupt process (main) and stored in the door command storage area. The door command storage area stores a door command indicating the detection state of the door opening detection switch 25 at the time of power-on or at the end of one game, and when the detection state of the door opening detection switch 25 changes, A door command indicating the detection state is stored. Further, the door command stored in the door command storage area is not cleared even after the door command is transmitted, and is then overwritten by a newly stored door command. When the power is turned on or one game is finished, a door command transmission request 1 for requesting transmission of a door command stored in the door command storage area is set, and whether the door command transmission request 1 is set or whether the door is open is detected. When the detection state of the switch 25 changes, the door command transmission request 2 is set. When the door command transmission request 2 is set, the door command stored in the door command storage area is set. In the command transmission process of the timer interrupt process (main) executed after transmission is instructed, it is stored in the command buffer and transferred to the transmission data register 561 of the serial communication circuit 511 to be transmitted to the sub-control unit 91. The

The operation detection command is used when a change in the detection state of any switch is detected in the switch input determination process of the timer interrupt process (main) (when edge data of any switch is set). is generated, together with Ru stored in the operation detection command storage area, the transmission of the operation detection command operation detection command transmission request is stored in the operation detection command storage area by being set is an instruction, the timer split to be subsequently executed In the command transmission processing of the main processing (main), the data is stored in the command buffer and transferred to the transmission data register 561 of the serial communication circuit 511 to be transmitted to the sub-control unit 91.

  As described above, both the door command and the operation detection command are stored in the command buffer in the command setting process of the timer interrupt process (main), and transferred to the transmission data register 561 of the serial communication circuit 511 so that the sub-control unit 91 If the door command transmission request 2 is set, that is, if the door command transmission is requested, even if the operation detection command is requested to be transmitted, the door command is transmitted. Since the operation detection command is transmitted only when the door command transmission request 2 is not set, both the door command transmission request 2 and the operation detection command transmission request are set. If the command is sent, the command transmission process sends a door command and sends the next command. Operation detection command in the processing is to be transmitted.

  As shown in FIG. 57A, the serial communication circuit 511 completes transmission of the status register 563 when untransmitted command data remains in the transmission data register 561 or command data is being transmitted. When the transmission of the command data stored in the transmission data register 561 is completed, the transmission completion value of the status register 563 is set to 1. The value of the status register 563 can be referred to by the CPU 505. The CPU 505 first acquires the transmission completion value from the status register 563 after saving the register in the timer interrupt process (main). Based on the value, the value of the transmission completion flag in the RAM 507 is updated.

  In the command transmission process, first, the value of the transmission completion flag stored in the RAM 507 is confirmed. As shown in FIG. 57B, when the value of the transmission completion flag is 1, that is, command data is not transmitted. Or only when it indicates that the transmission of the command data is completed, the transfer of the door command or the operation detection command to the transmission data register 561 is permitted, and when the value of the transmission completion flag is 0, That is, when there is untransmitted command data remaining in the transmission data register 561 or when command data is being transmitted, even if the door command transmission request 2 is set, the transmission to the door command transmission data register 561 is performed. Transfer is prohibited, and even if an operation detection command transmission request is set, the operation detection command transmission data register Transfer to 561 is adapted to be inhibited.

  In particular, the operation detection command is requested to be transmitted when the switch detection state changes regardless of whether it is invalid or valid. Although the transmission of the command accompanying the game progress control will be delayed, the operation detection command is transmitted only when the command data has not been transmitted or the command data has been transmitted as described above. Since transfer to 561 is permitted, it is possible to prevent the effects related to the progress control of the game from being delayed with the transmission of the operation detection command.

  In this embodiment, a command (hereinafter referred to as a first command) triggered by an event associated with the progress control of the game is generated in the basic process and transferred to the transmission data register 561 to transfer the serial communication circuit 511. Is transmitted to the sub-control unit 91, but a command (hereinafter referred to as a second command) triggered by an event that may occur regardless of the progress of the game, such as a door command or an operation detection command, is basically It is generated by a timer interrupt process (main) executed by interrupting the process periodically. In addition, since the command is composed of 2-byte data, if the configuration is such that the second command is immediately transferred to the transmission data register 561 when the second command is generated, it may be accompanied by game progress control in the basic process. After transferring the first byte of command data, the timer interrupt process is interrupted and executed before transferring the second byte, and the second command is inserted between the first byte and the second byte of the first command data. May be received and cannot be received as a regular command on the sub-control unit 91 side.

  On the other hand, in the present embodiment, as described above, the transmission completion value in the status register 563 of the serial communication circuit 511 is acquired at the beginning of the timer interrupt process (main), the transmission completion flag in the RAM 507 is updated, and transmission is performed. When 0 is set as the completion flag, that is, when any command remains in the transmission data register 561 or a command is being transmitted, the transfer of the second command to the transmission data register 561 is prohibited. Thus, the second command does not enter between the command data of a plurality of bytes constituting the first command.

  In the present embodiment, in the timer interrupt process (main), the value of the completion of transmission in the status register 563 is not checked immediately before the second command is transferred to the transmission data register 561, but the timer interrupt process ( The transmission completion flag of the status register 563 acquired at the beginning of the main) is acquired to update the transmission completion flag, and the value of the transmission completion flag is referenced immediately before the transfer of the second command to the transmission data register 561. It is determined whether the transfer of the second command to the transmission data register 561 is prohibited or permitted.

  As shown in FIG. 57B, after the command data of the first byte constituting the first command is transferred to the transmission data register 561, the command data of the second byte constituting the first command is changed. When the timer interrupt process (main) is executed at the stage before transfer, before determining whether to prohibit or permit the transfer of the second command to the transmission data register in this timer interrupt process (main), Transmission of the command data of the first byte constituting the first command is completed, the value of transmission completion of the status register 563 becomes 1, and the command data of the second byte constituting the first command is transmitted. 1st byte command data and 2nd byte command data constituting the first command on the assumption that there is no untransmitted first command data. This is because the second command data may be transmitted in the meantime, and the transmission completion value of the status register 563 acquired at the beginning of the timer interrupt processing (main) is acquired as in this embodiment. Then, the transmission completion flag is updated, and the transfer of the second command to the transmission data register 561 is prohibited by referring to the value of the transmission completion flag immediately before the transfer of the second command to the transmission data register 561. Before determining whether to prohibit or permit the transfer of the second command to the transmission data register in the timer interrupt process (main). Even if the transmission of the command is completed and the transmission completion value of the status register 563 becomes 1, the transfer of the second command to the transmission data register is surely prohibited. It becomes possible, during the first byte of command data and 2 bytes of the command data constituting the first command, it is possible to the second command data reliably prevented from being transmitted.

  In this embodiment, the timer interrupt process (main) starts, and after saving the register, the transmission completion value of the status register 563 is acquired immediately. At least the timer interrupt process (main) Is the stage before the transfer of the second command to the transmission data register, and after the timer interrupt processing (main) starts, the serial communication circuit 511 completes the transmission of the command data of the first byte. The transmission completion value of the status register 563 may be acquired before the time required for updating the transmission completion value elapses.

  In the present embodiment, the drive control of the reel motors 32L, 32C, and 32R configured by the stepping motor is performed in the timer interrupt process (main), and the first command is transferred to the transmission data register 561. In the timer interrupt process (main), the transfer of the second command is prohibited in the timer interrupt process (main). Since the second command is prevented from entering, the excitation time of the phases of the reel motors 32L, 32C, 32R is constant, and the reel motors 32L, 32C, 32R can be driven stably.

  In this embodiment, the door command and the operation detection command are applied as commands triggered by an event that can occur regardless of the progress of the game. Any command that is required to be transmitted in the interrupt process (main) may be used, and a command indicating that an error that may occur unexpectedly, such as vibration of a gaming machine, may be applied as the second command.

  In this embodiment, when any command remains in the transmission data register 561 or when a command is being transmitted, the transfer of the second command to the transmission data register 561 is uniformly prohibited. As shown in FIG. 35B, in the command storing process for transferring the command data to the transmission data register 561 in the basic process, the command transfer assigned to the RAM 507 before transferring the command data for the first byte (Sx1). Set the value of the completion flag area to 0 (Sx0), set the value of the command transfer completion flag area to 1 after completing the transfer of the second byte of command data (Sx2) (Sx3), and timer interrupt processing Only when the command transfer completion flag value is set to 1 in the (main) command setting process Transfer of the second command to the transmission data register 561 is permitted, and when the command transfer completion flag value is set to 0, transfer of the second command to the transmission data register 561 is prohibited. With this configuration, as shown in FIG. 57C, after all the command data composing the first command is transferred to the transmission data register 561, the last command data ( Even if the second byte) still remains in the transmission data register or transmission shift register 562 and transmission is not completed (the transmission completion value in the status register 563 is 0), the second command Transfer to the transmission data register 561 is permitted, the second data is transmitted between the command data of a plurality of bytes constituting the first command. On top never intrudes command data constituting a command, a period during which transmission of the second command is prohibited can be minimized.

  The main control unit 41 monitors the detection state of the door opening detection switch 25 about every 100 ms. Specifically, in any of the timer interrupts 1 to 4 of the timer interrupt process (main), that is, in the port input process performed every 0.56 ms, an input state (door) in which the detection signal from the door open detection switch 25 is converted to a positive logic Open detection switch 25on = 1, 0 is acquired when the door is closed, and is performed by timer interrupt 2 of the timer interrupt process (main), that is, in the door monitoring process performed every 2.24 ms, in the port input process described above The acquired state of the detection signal of the door opening detection switch 25 (the input state that has been the same for two consecutive times) continues to be logically ORed for about 100 ms (45 times of door monitoring processing), and the door opening detection switch is used using the result. 25 detection states are determined. When the calculation result is 1 when about 100 ms elapses, that is, when the door opening detection switch 25 is turned on (opened) even once during that time, it is determined that the door opening detection switch 25 is on. If the calculation result is 0, that is, if the door opening detection switch 25 is not turned on (opened) during that time, it is determined that the door opening detection switch 25 is off. If the result of this determination and the detection state of the door opening detection switch 25 indicated by the door command stored in the door command storage area match, it is determined that the detection state of the door opening detection switch 25 has not changed. Otherwise, it is determined that the detection state of the door opening detection switch 25 has changed, the door command stored in the door command storage area is updated to a door command indicating the detection state after the change, and the door command transmission request 2 is set. Then, the transmission of the door command is instructed. Further, when the main control unit 41 determines that the detection state of the door opening detection switch 25 has changed, the main control unit 41 updates the output state of the door opening signal to the external output board 1000 in addition to the door command transmission command.

  The main control unit 41 sets the door command transmission request 1 in the activation process or the game process when the power is turned on or at the end of one game, and requests transmission of the door command stored in the door command transmission buffer. On the other hand, in the door monitoring process, it is determined whether or not the door command transmission request 1 is set. If the door command transmission request 1 is set, it is determined that there is a door command transmission request and the door command transmission is performed. Request 2 is set to command transmission of the door command stored in the door command storage area. Further, when the door command transmission request 1 is set, the main control unit 41 updates the output state of the door opening signal to the external output board 1000 in addition to the door command transmission command.

  As described above, the output state of the door opening signal to the external output board 1000 is updated by linking to the door command transmission command.

  The slot machine 1 of the present embodiment includes a single BET switch 5, a MAXBET switch 6, a start switch 7, and stop switches 8L, 8C, and 8R as operation switches for the main control unit 41 to control the progress of the game. Of these operation switches, the start switch 7 is also used for setting value setting in a setting change state.

  The operation of these switches is not always related to the progress control of the game in all control states constituting from the end of the game to the end of the next game, but is related to the progress control of the game according to the control state. Sometimes it may not be involved.

  In the control state from the end of the game (after changing the setting) to the start of the game, the operation of the single BET switch 5, the MAXBET switch 6, and the start switch 7 is involved in the progress control of the game, and the stop switches 8L, 8C, 8R The operation is not related to the progress control of the game. Furthermore, even in the control state from the end of the game (after setting change) to the start of the game, the bet number has not reached the specified number, that is, the bet number can be further added, and the game start condition is In a state where it is not established, the operation of the single BET switch 5 and the MAXBET switch 6 is involved in the game progress control, but the operation of the start switch 7 is not involved in the game progress control, while the bet number is defined. In the state where the number has been reached, that is, in the state where the bet number cannot be added and the game start condition is satisfied, the operation of the start switch 7 is involved in the game progress control. 5. The operation of the MAXBET switch 6 is not related to the progress control of the game.

  In the control state from the start of the game to the end of the game, the operation of the stop switches 8L, 8C, 8R is involved in the game progress control, and the operation of the single BET switch 5, the MAXBET switch 6, and the start switch 7 Not involved in progress control. Furthermore, even in the control state from the start of the game to the end of the game, if all the reels are rotating, all the operations of the stop switches 8L, 8C, 8R are involved in the progress control of the game. In the stop state, only the stop switch corresponding to the rotating reel among the stop switches 8L, 8C, and 8R is involved in the progress control of the game, and the stop switch corresponding to the stopped reel is the game switch. Not involved in progress control.

  The control state in the present invention is not limited to the control state from the end of the game (after changing the setting) to the start of the game, or the control state from the start of the game to the end of the game, but from the end of the game (after changing the setting). In the control state up to the start, the bet number has not reached the specified number, that is, the bet number can be further added and the game start condition is not satisfied, the bet number has reached the specified number A control state in which the number of bets cannot be added and a game start condition is satisfied, a control state in which all reels are rotating among control states from the start of the game to the end of the game, left Control state in which only the reel is stopped, Control state in which only the middle reel is stopped, Control state in which only the right reel is stopped, Control state in which the left and middle reels are stopped, Left and right reels Sealed and has control state, right, control state middle reel is stopped, the wait period state, applicable also for each of the states of the payout period medal. Furthermore, even if the operation of the single BET switch 5 or the MAX BET switch 6 is not involved in the progress control of the game in the control state from the end of the game (after the setting change) to the start of the game, the specified number of bets has already been obtained. The control state in which the operation of the single BET switch 5 or the MAXBET switch 6 is not involved in the progress control of the game and the specified number of bets has not been set yet, but no credit remains. In other words, it can be said that the control state is different from the control state in which the operation of the single BET switch 5 or the MAXBET switch 6 is not related to the progress control of the game.

  In the setting change state, the operation of the start switch 7 is involved in the change control of the setting value, and the operations of the single BET switch 5, the MAXBET switch 6, and the stop switches 8L, 8C, 8R are not involved in the game progress control. Even in the setting change state, the operation of the start switch 7 is involved in the change control of the set value before the set value is determined. However, after the set value is determined, all the operation switches Not involved in change control. Further, in the setting confirmation state, any operation of the single BET switch 5, the MAXBET switch 6, the start switch 7, the stop switches 8L, 8C, and 8R is not involved in the game progress control.

  The main control unit 41 detects these operation switches in a switch input determination process executed during a timer interrupt process (main) executed by interrupting at regular time intervals. In the switch input determination process, the detection state of the operation switch is monitored, and when any operation switch changes from off to on, edge data (rising edge) indicating that the corresponding operation switch changes from off to on Is set, edge data (falling edge) indicating that the corresponding operation switch has changed from on to off is set.

  Then, the main control unit 41 determines whether or not the operation switch has been operated based on whether or not the rising edge of the operation switch related to the progress control of the game is set according to the control state at the current stage in the game process. If it is determined that the operation switch is operated, all the edge data is cleared, and the game progress control is executed according to the operation switch operation, and the game progress control is performed. The accompanying commands (BET command, internal winning command, reel stop command, etc.) are transferred to the transmission data register 561 of the serial communication circuit 511 and transmitted to the sub-control unit 91. Even if the operation of any one of the operation switches is detected and the edge data is set, if it is not cleared by the next switch input determination process, it is cleared by the next switch input determination process.

  When determining that the rising edge of the stop switch corresponding to the rotating reel is set in the reel rotation processing, the main control unit 41 determines whether the detection state of the other operation switches is on. When it is determined that the detection state of the other operation switch is on, that is, when the operation of the stop switch corresponding to the rotating reel is detected while the other operation switch is being operated, this is effective. The stop operation of the corresponding reel is not performed without the stop operation.

  This is because, when two or more operations are detected among the stop switches 8L, 8C, and 8R, if priority is given to the stop control based on one of the operations, the other stop control is delayed, and the stop mode of the reel This is because there is a possibility that a problem such as unnaturalness may occur, and even if the operation of the stop switch corresponding to the rotating reel is detected while the other operation switches are operated as described above, By not performing the stop control of the reel to be performed, the stop control of the other reel is not delayed by the stop control of the one reel.

  Further, when the main control unit 41 determines that the rising edge of the stop switch corresponding to the rotating reel is set in the reel rotation processing, the detection state of the other operation switch is not limited to the other stop switch. If the detection state of any of the other operation switches is determined to be on, the effective stop operation is not performed and the corresponding reel stop control is not performed. Without extracting only the detection state of the stop switch from the detection state of the operation switch, for example, when on is set to 1 and off is set to 0, the sum of the detection states of all the operation switches is calculated. If the number is two or more, the detection states of all the operation switches can be collectively determined, for example, the other operation switches are determined to be in the detection state.

  When the main control unit 41 determines that the rising edge of the start switch 7 for determining the setting value is set at a stage where the setting value has not yet been determined in the setting change state, When it is determined whether or not the detection state of the operation switch is on, and it is determined that the detection state of any of the other operation switches is on, control to confirm the set value is not performed. Yes.

  This is because, as will be described later, the operation switch used by the main control unit 41 for controlling the progress of the game is diverted as an operation unit in the administrator mode that is controlled on the sub-control unit 91 side in the setting change state. Even when the start switch 7 for confirming the setting value is operated in a state where the other operation switches are being operated at the stage where the setting value has not yet been confirmed as described above, the setting value confirmation control is performed. By not doing so, even if the start switch 7 is mistakenly operated simultaneously with the operation of the administrator mode, the set value is not fixed and the setting value is not set. However, it is possible to reduce the annoyance of having to change the setting from the beginning by turning off the power again due to an erroneous operation. To have.

  When the main control unit 41 determines a change in the detection state of any of the operation switches in the above-described switch input determination process, the main control unit 41 sets the edge data, and is a switch in which the edge data is set, a rising edge, An operation detection command indicating whether it is a falling edge or a detection state of another switch is generated, stored in the operation detection command storage area, and an operation detection command transmission request is set.

  When the operation detection command transmission request is set, the operation detection command stored in the operation detection command storage area is read out in the command transmission process in the timer interrupt process (main), and the serial communication circuit 511 The data is transferred to the transmission data register 561 and transmitted to the sub-control unit 91.

  As described above, in this embodiment, the main control unit 41 sub-controls an operation detection command that can specify that the single BET switch 5, the MAXBET switch 6, the start switch 7, and the stop switches 8L, 8C, and 8R are operated. The operation switch detected by the main control unit 41 is transmitted to the unit 91 regardless of whether or not the sub control unit 91 is an operation switch related to the game progress control in each control state. It is possible to specify that an operation has been performed, and an effect can be executed in accordance with the operation of an operation switch that is not involved in the progress control of the game.

  In the present embodiment, the main control unit 41 transmits an operation detection command indicating that only when the detection state (on / off) of any one of the operation switches changes, and the operation detection The transmission of commands can be reduced as much as possible, the control load related to the transmission of operation detection commands can be reduced, and the sub-control unit 91 does not need to receive operation detection commands more than necessary.

  Further, not only when the detection state of any of the operation switches changes from off to on, but also when the detection state changes from on to off, an operation detection command indicating the change is transmitted, so the sub-control unit 91 side Therefore, since it is possible to identify in real time the detection state of the operation switch that is not involved in the game progress control, the operation is released not only at the timing when the operation switch operation not involved in the game progress control is started. It is also possible to perform different presentations according to the timing that has continued for a certain period of time without releasing the timing and operation, and to change the start timing and end timing of the presentation, according to the operation of the operation switch that is not involved in the game progress control Various productions can be performed.

  In this embodiment, when the change of the detection state of any operation switch is detected from the detection of the change of the operation switch from the detection state off to the on state or from the on to the off state, An operation detection command that identifies the detection state of the operation switch is sent, but only the fact that the detection state of any of the operation switches has changed from off to on is detected, and the fact that it has changed from off to on is indicated. When detected, an operation detection command capable of specifying the operation of the corresponding operation switch is transmitted, or only that the detection state of any operation switch has changed from on to off is detected, and from on to off When it is detected that the operation has changed, an operation detection command that can specify the operation of the corresponding operation switch may be transmitted. It is, it is possible to further reduce the transmission of the operation detection command, on top which can reduce the load of the control according to the transmission of the operation detection command, can also reduce the operation detection command received by the sub-control section 91 side.

  In this embodiment, when the detection state (on / off) of any operation switch changes, an operation detection command that can specify the detection state of another operation switch in addition to the detection state of the operation switch is provided. The sub-control unit 91 is configured to transmit to the sub-control unit 91. With such a configuration, it is possible to reduce the transmission of the operation detection command as much as possible. Not only the detection state of the operation switch whose detection state has changed, but also the detection state of other operation means can be specified. On the sub-control unit 91 side, a plurality of operations such as simultaneous operation of a plurality of switches and operation of only a specific switch are possible. It is possible to produce an effect that reflects the operation status of the operation switch, and it is possible to produce a variety of effects using the operation of the operation switch. Furthermore, even when the sub-control unit 91 misses the operation detection command, the latest detection state can be specified for all the operation switches based on the operation detection command transmitted next time, and the game progress control is performed. An effect according to the operation of the operation switch not involved in the operation can be reliably executed.

  In this embodiment, only when the detection state (on / off) of one of the operation switches is changed, an operation detection command indicating that is transmitted. Regardless of whether the switch 5, the MAXBET switch 6, the start switch 7, or the stop switches 8L, 8C, 8R has been operated, the one-sheet BET switch 5, the MAXBET switch 6, the start switch 7, the stop switches 8L, 8C , 8R may be configured to transmit an operation detection command that can specify the on / off state at regular intervals. Even in such a configuration, the sub-control unit 91 side detects the operation detection command. It is possible to identify the operation switch that has been operated, and the operation switch that is not involved in game progress control It is possible to perform the production in accordance with the work.

  In the present embodiment, an operation command transmission request is set in the timer interrupt processing (main) switch input determination processing, and is transferred to the transmission data register 561 in the subsequent command transmission processing and transmitted to the sub-control unit 91. In the basic process, it is determined whether or not an operation switch that does not participate in the game progress control is operated, that is, whether or not edge data of the operation switch that does not participate in the game progress control is set. When an operation switch not involved in the progress control is operated, an operation detection command indicating that may be transferred to the transmission data register 561 and transmitted to the sub-control unit 91. In addition, it is specified that the operation switch detected by the main control unit 41 is operated on the sub control unit 91 side. It has become so that, it is possible to perform the production in response to the operation of the operation switch that is not involved in the progression control of the game.

  In this embodiment, a command associated with the progress control of the game is generated in the basic process, transferred to the transmission data register 561, and transmitted to the sub-control unit 91, but is not involved in the progress control of the game. The operation detection command accompanying the operation of the operation switch is generated in the switch input determination process of the timer interrupt process (main), transferred to the transmission data register 561 in the subsequent command transmission process of the timer interrupt process (main), Although it is a structure transmitted to the control part 91, it is determined whether operation of the operation switch in connection with game progress control was detected in the basic process, and operation of the operation switch in connection with game progress control was detected. Control the game in the event that the It is temporarily stored in the buffer, and it is also determined whether or not an operation not involved in the game progress control is detected in the basic process, and the operation of the operation switch is detected when the operation switch operation not involved in the game progress control is detected. An operation detection command indicating that an operation not involved in the control has been detected is generated, temporarily stored in the command buffer in the same manner as the command accompanying the game progress control, and then waiting for transmission in the timer interrupt process (main) When the command is stored in the command buffer, the command may be transferred to the transmission data register 561 and transmitted to the sub-control unit 91. With such a configuration, the control state of the basic process is related. Therefore, it is possible to share command transmission control.

  In addition, when such a configuration is adopted, there is a possibility that a plurality of transmission waiting commands may be stored before the command stored in the command buffer is transmitted in the next timer interrupt process (main). If a plurality of commands are transmitted continuously, the sub-control unit 91 may be missed, and the processing time of the timer interrupt process (main) becomes long, and the basic process is stagnant. Therefore, when there are a plurality of commands stored in the command buffer, it is preferable to transmit only one command per timer interrupt process (main). However, if only one command is transmitted per timer interrupt process (main), the command transmission timing will be delayed.

  On the other hand, in the case of adopting the above configuration, when the operation switch operation involved in the game progress control and the operation switch operation not involved in the game progress control are detected at the same time, There is a possibility that an operation detection command accompanying the operation of the operation switch not involved in the game progress control is generated at the same time and stored in the command buffer. In this case, in the subsequent timer interrupt process (main), it is preferable to prioritize the transmission of the command associated with the game progress control over the operation detection command. The transmission is not delayed, and it is possible to prevent the presentation according to the operation related to the game progress control from being delayed due to the influence of the operation not related to the game progress control.

  The main control unit 41 executes a start-up process when power is turned on, and an interrupt is permitted at the end of the start-up process. Thereafter, a timer interrupt process (main) is executed at regular intervals. When the main control unit 41 can return to the state before the power interruption, a return command is transmitted to the sub-control unit 91 before interruption is permitted in the startup process. Also, if the main control unit 41 cannot return to the state before the power interruption due to an abnormality in the data stored in the RAM 507, an error command indicating a RAM abnormality is issued before the interrupt is permitted in the startup process. Sent to. If the setting key switch 37 is in the on state and the RAM 507 is initialized and does not return to the state before the power interruption, the setting command indicating the setting start is issued before the interruption is permitted in the starting process. It is transmitted to the control unit 91. Of the commands transmitted in the startup process, the return command specifies that the main control unit 41 returns to the state before the power interruption. The error command indicating a RAM abnormality and the setting command indicating the start of setting It is specified that the control unit 41 does not return to the state before the power interruption.

  As described above, the operation detection command is transmitted in the timer interrupt process (main), and the interrupt process is not permitted until the end of the start process. Therefore, after the main control unit 41 is started, the main control unit 41 is started. An error command indicating a RAM abnormality that indicates that the main control unit 41 does not return to the state before the power failure or a setting start is specified. After the setting command is transmitted, the transmission of the operation detection command is permitted.

  As described above, after the power is turned on, the main control unit 41 determines that the state before power interruption is not restored and transmits an error command indicating a RAM abnormality to the sub-control unit 91 or returns to the state before power interruption. Since the operation detection command is not transmitted to the sub-control unit 91 until the return command is transmitted to the sub-control unit 91, whether or not to return the main control unit 41 is not yet determined. Therefore, the sub-control unit 91 does not execute an effect according to the operation specified from the operation detection command, and prevents an effect that is inconsistent with the state of the main control unit 41 from being executed when the power is turned on. it can.

  In addition, the main control unit 41 transmits a return command, an error command indicating a RAM abnormality, and a setting command indicating start of setting to the sub-control unit 91 in the startup process, and then permits a timer interrupt by permitting the interrupt. Processing (main) is executed, and the operation detection command is transmitted in the command transmission process. In the command transmission process, the return command, the error command indicating the RAM abnormality, and the setting command indicating the setting start are already present. It is possible to transmit the return command, the error command indicating the RAM abnormality, and the setting command indicating the start of setting prior to the operation detection command without determining whether or not it is transmitted.

  Further, the main control unit 41 determines whether or not a voltage drop signal is input at the beginning of the timer interrupt process (main), and executes the power interruption process (main) only when the voltage drop signal is input. Therefore, the operation detection command transmission request is set in the switch input determination processing of the previous timer interrupt processing (main), and the power interruption processing (main) is performed without transmitting the operation detection command based on the operation detection command transmission request. Although the operation may stop, the main control unit 41 clears the operation detection command transmission request at the time of activation, so that the operation detection command that has not been transmitted in the state before the power interruption is detected. After returning, an operation detection command that does not reflect the detection state of the operation switch after the return is not transmitted. For this reason, after the power is turned on, it is possible to prevent an effect corresponding to an operation not related to the progress control of the game from being executed even though the operation switch is not operated at all.

  Next, the control of the effect performed by the sub control unit 91 based on the command transmitted from the main control unit 41 to the effect control board 90 will be described.

  When the sub control unit 91 receives a command from the main control unit 41, the sub control unit 91 executes a command reception interrupt process. In the command reception interrupt process, the command acquired from the command transmission line is stored in the reception buffer provided in the RAM 91c.

  The reception buffer is provided with an area capable of storing a maximum of 16 commands so that a plurality of commands can be accumulated.

  In the timer interrupt process (sub), the sub-control unit 91 determines whether or not an unprocessed command is stored in the reception buffer. If an unprocessed command is stored, the sub-control unit 91 is the earliest. The control pattern table stored in the ROM 91b is referred to based on the command received in the stage, and the liquid crystal display 51, effect effect LED 52, speakers 53, 54, reel LED 55, etc. are controlled based on the control contents registered in the control pattern table. Performs output control of various rendering devices.

  In the control pattern table, the display pattern of the liquid crystal display 51 corresponding to the type of command, the lighting mode of the lighting effect LED 52, the output mode of the speakers 53 and 54, the lighting mode of the reel LED, etc. Control patterns of these effect devices are registered, and when the sub-control unit 91 receives a command, the sub-control unit 91 stores the control patterns registered corresponding to the effect patterns set in the RAM 91c in the game of the control pattern table. Among these, the control pattern corresponding to the type of the received command is referred to, and the output control of the rendering device is performed based on the control pattern. Thereby, the production according to the production pattern and the progress of the game is executed.

  If the sub-control unit 91 receives a new command during execution of an effect triggered by the reception of a certain command, the sub-control unit 91 stops the effect based on the control pattern being executed, and changes to the newly received command. An effect based on the corresponding control pattern is executed. In other words, even if the production is not finished to the end, when a new command is received, the production that was being executed is canceled and a new command is received unless the received new command is not a command that triggers a new production. An effect based on the command is executed.

  In particular, in this embodiment, when the betting number setting operation is performed during the execution of the effect, that is, when the sub-control unit 91 receives a BET command indicating that the bet number has been set, Is to be canceled. For this reason, if the player wants to proceed to the next game rather than seeing the production to the end, the production is canceled and the next game can be started. There is no. Further, when a credit or betting amount adjustment operation is performed during the performance, that is, after the sub-control unit 91 receives a game state command indicating the end of the game, it receives an internal winning command indicating the start of the game. When the payout start command is received before, the effect being executed is stopped. Credits and bets are settled when the game is terminated. In such a case, by terminating the performance that is being executed, there is an intention to end the game, but the performance continues unnecessarily. It is designed not to be overwhelmed.

  When the internal winning command is received, the effect pattern is selected at a selection rate corresponding to the result of the internal lottery indicated by the internal winning command, and is set in the RAM 91c. The selection rate of the effect pattern is registered in the effect table stored in the ROM 91b, and when the sub control unit 91 receives the internal winning command, the sub control unit 91 stores the effect pattern in the effect table according to the result of the internal lottery indicated by the internal winning command. With reference to the registered selection rate, one of the effect patterns is selected from a plurality of types of effect patterns according to the selection rate, and the selected effect pattern is set in the RAM 91c as the effect pattern of the game. Even if the same command is received, a different control pattern is selected depending on the effect pattern selected when the internal winning command is received. As a result, different effects may be performed depending on the effect pattern.

  In the RAM 91c of the sub-control unit 91, a detection state storage area in which the change state of the detection state of the operation switch is stored for each operation switch, and an operation detection flag indicating that the operation state of the operation switch has changed are provided for each operation switch. An operation detection flag storage area to be stored is allocated. Furthermore, the detection state storage area is assigned with a detection state before receiving the operation detection command (previous) and a detection state after receiving the operation detection command (this time). The detection state of each operation switch before and after reception is stored.

  The sub-control unit 91 performs the operation detection process 1 when it is determined in the timer interrupt process (sub) that an unprocessed command is stored in the reception buffer. In the operation detection process 1, it is determined whether or not an unprocessed command is an operation detection command. If it is determined that the command is an operation detection command, the current detection state stored in the detection state storage area is changed to the previous detection state. , And the detection state of each operation switch indicated by the operation detection command is stored as the current detection state, and when there is an operation switch in which the previous detection state and the current detection state are different, it is changed from off to on. In this case, a rising flag is set as an operation detection flag corresponding to the operation switch, and when it changes from on to off, a falling flag is set as an operation detection flag corresponding to the operation switch.

  Thus, in this embodiment, when the detection state of any of the operation switches changes, the main control unit 41 transmits an operation detection command that can specify the detection states of all the operation switches, and the sub-control unit. 91, when an operation detection command is received, the detection state of each operation switch before and after receiving the operation detection command stored in the detection state storage area is updated. An operation detection flag corresponding to the operation switch is set, and the sub-control unit 91 confirms the presence or absence of the operation detection flag, so that the detection state of the operation switch has changed and the operation detection command How the detection state of each operation switch has changed before and after reception, that is, whether it has changed from off to on, or from on to off, So that the it can be determined.

  For this reason, the sub-control unit 91 can perform an effect or change the effect according to not only the timing when the operation of the operation switch is started but also the timing when the operation is released. Various effects can be performed according to the operation mode of the operation switches not involved.

  In the present embodiment, how the sub-control unit 91 changes the detection state of each operation switch from the detection state of each operation switch before and after receiving the operation detection command stored in the detection state storage area. In this embodiment, when the detection state of any of the operation switches changes, the main control unit 41 switches the detection state from changing to off to on. Or an operation detection command that can specify whether the change is from on to off, so that the detection state of each operation switch before and after receiving the operation detection command is determined from the operation detection command itself. It is good also as a structure which discriminate | determines whether it changed or not. By setting it as such a structure, the control load of the sub control part 91 accompanying operation of the operation switch which does not affect progress control of a game It can be reduced.

  The detection state storage area stores the detection state of each operation switch, and the sub-control unit 91 sets one of the operation detection flags and indicates the detection state of the operation switch corresponding to the operation detection flag. When a change is identified, it is possible to identify not only the operation switch whose detection state has changed but also the detection state of another operation switch by checking the detection state of the other operation switch in the detection state storage area. ing.

  For this reason, it becomes possible to specify the state in which a plurality of operation switches are operated at the same time, and for example, it is possible to produce an effect by operating a plurality of operation switches simultaneously, such as the operation effect of pattern 1 or pattern 3 Thus, various effects can be performed depending on how the plurality of operation switches are operated.

  Further, the sub control unit 91 detects the left stop switch when performing the effect by operating the operation switches of the left stop switch and the middle stop switch at the same time as in the operation effect of the pattern 1, and If the middle stop switch operation is detected when the right stop switch is not detected, the stage change effect is performed, but both the left stop switch and the right stop switch are detected. When the operation is detected, the operation of the left stop switch and the middle stop switch is detected at the same time as described above. In this case, the stage change effect is not performed.

  That is, when performing a specific operation effect in response to an operation of a specific operation switch, if an operation switch other than the specific operation switch is operated together with the specific operation switch, the specific operation effect is not performed. ing.

  For this reason, a specific operation effect based on an operation of a specific operation switch is performed when the specific operation switch is operated simultaneously with another operation switch or when the other operation switch is operated. Since it is not executed and a specific operation effect is not executed by an erroneous operation, the specific operation effect can be executed only for a player who desires the specific operation effect.

  In addition, when an operation switch other than a specific operation switch is operated together with the specific operation switch as described above, by not performing a specific operation effect, for example, the operation effects of pattern 1 and pattern 3 Even when some of the operation switches for executing each effect overlap, different effects can be executed. That is, the operation effect of pattern 1 is executed by operating the left stop switch and the middle stop switch simultaneously, and the operation effect of pattern 2 is executed by operating the middle stop switch and the right stop switch simultaneously. When the middle stop switch is operated while the left stop switch and right stop switch are operated at the same time, the left stop switch and middle stop switch are operated simultaneously, or the middle stop switch and right stop switch are operated simultaneously. However, it is not possible to determine whether or not it is possible to assign an effect only to one of the simultaneous operations, but an operation switch other than the specific operation switch is operated together with the specific operation switch. If a specific operation effect is not performed, And even cases like operation effect of the pattern 2, can be assigned an effect for each of the simultaneous operation as it can be performed more diverse effect by way of the operation of a plurality of operation switches.

  When the detection state of any operation switch changes from off to on in the operation detection process 1, that is, when the operation of the operation switch starts, the sub control unit 91 corresponds to the operation time counter assigned to the RAM 91c. The operation time counter value of the operation switch to be initialized is initialized. The value of the operation time counter is incremented every time the timer interrupt process (sub) is executed, and the elapsed time since the operation switch operation started by referring to the value of the operation time counter Time can be determined.

  The sub-control unit 91 executes the operation detection process 2 every time the timer interrupt process (sub) is executed. In the operation detection process 2, it is determined for each operation switch whether or not the current detection state stored in the detection state storage area is on. If it is on, that is, if the operation of the operation switch continues. Refers to the value of the operation time counter of the corresponding operation switch, and if a predetermined time has elapsed, sets a time elapse flag indicating that to the operation switch. In this embodiment, a 3 second elapsed flag, a 5 second elapsed flag, and a 10 second elapsed flag are set as a time elapsed flag when 3 seconds have elapsed, 5 seconds have elapsed, and 10 seconds have elapsed.

  For this reason, the sub-control unit 91 can perform an effect when a certain time has elapsed since the operation switch has been operated continuously by confirming whether or not the time lapse flag is set. Become.

  In the present embodiment, the sub-control unit 91 counts the time that has elapsed since the detection state of the operation switch has not changed from on to off after the detection state of the operation switch has changed from off to on. The sub-control unit 91 side can grasp the continuous operation time of the operation switch, and the main control unit 41 side does not have a timer for measuring the continuous operation time for each individual switch. It is possible to detect the continuous operation time of the operation switch only by changing the value, but after the operation switch operation changed from off to on on the main control unit 41 side, the operation switch did not change from on to off. By measuring the time and transmitting a command indicating that the operation switch has been operated continuously for the specified time when this time reaches the specified time, the sub-control unit 91 side , It may be able to identify that the operation of the operation switch is operated continuously.

  In addition, when the detection state of any one of the operation switches is changed from off to on in the operation detection process 1, that is, when the operation of the operation switch is started, the sub-control unit 91 sets the continuous operation counter assigned to the RAM 91c. 1 is added to the value of the continuous operation counter of the corresponding operation switch. The value of the continuous operation counter is cleared by a command from the sub-control unit 91 such as when the detection state of another operation switch changes from off to on or at the start of production. It is possible to determine the number of times that a specific operation switch has been operated continuously from the starting point. Then, the sub-control unit 91 can confirm the value of the continuous operation counter, and can produce an effect when the number of continuous operation of the operation switch from a certain starting point has reached the specified number.

  In this embodiment, the sub-control unit 91 counts the number of times that the detection state of the operation switch has changed from off to on, so that the sub-control unit 91 can grasp the number of consecutive operation switch operations. The main controller 41 does not have a counter for counting the number of continuous operations for each individual switch, and it is possible to detect the number of operation switches by simply changing the program of the sub controller 91. By counting the number of times the operation switch operation has changed from off to on on the main control unit 41 side, and sending the command indicating that the operation switch has been operated the specified number of times when this number reaches the specified number of times, On the side of the sub-control unit 91, it may be possible to specify that the operation switch has been operated a specified number of times.

  Although the embodiments of the present invention have been described with reference to the drawings, the present invention is not limited to these embodiments, and modifications and additions within the scope of the present invention are included in the present invention. Needless to say.

1 slot machine 2L, 2C, 2R reel 6 MAXBET switch 7 start switch 8L, 8C, 8R stop switch 41 main control unit 91 sub control unit 505 CPU
506 ROM
507 RAM
509 Random number circuit 559A Random value register

Claims (2)

Each comprising a plurality of variable display unit capable variable display by moving a plurality of types of identification information capable of identifying periodically,
After variable display of said variable display unit, in the variable variable display of the display unit derives a display result by stopping, a plurality of variable display portions of the display result combination winning can occur depending on the slot machine,
A game control microcomputer incorporating a control CPU for executing game control in the gaming machine based on the game control processing program;
A random number circuit that is built in or externally attached to the game control microcomputer and generates numerical data to be a random value;
Data storage means having a backup area in which stored data is retained even if power supply is stopped;
With
The random number circuit includes:
Numeric value updating means for updating and outputting numerical data according to a predetermined procedure;
Random value storage means for capturing and storing numerical data output from the numerical value updating means as a random number value;
Including
The game control microcomputer is:
Control determining means for making a predetermined determination by the control CPU based on a random number value generated by the random number circuit;
While the numerical data output from the numerical value updating means based on the input of a predetermined signal is stored in the random number storage means, the random number storage means is turned on to restrict the storage of new numerical data, while the random value storage means A predetermined flag that is turned off when the numerical value data stored in is read by the control CPU at the read timing of the random number value and permits storage of new numerical data;
Power interruption processing execution means for executing power interruption processing for enabling recovery based on data held in the backup area when a power interruption condition is satisfied;
A start command means for performing a start command when the power supply does not stop after execution of the power interruption process;
Control state return means for returning to the control state before the power interruption process based on the data held in the backup area triggered by the start command,
After executing the power interruption process, when waiting for the power supply to stop, the power interruption standby time processing means for turning off the predetermined flag,
Including
The slot machine is
A derivation operation means for operating for a player to derive a display result,
When the derivation operation means is operated, a movement value indicating a movement amount from the position where the derivation operation means is operated to a stop of the movement in a variable display unit corresponding to the derivation operation means is obtained by a predetermined compression method. Stored is the compressed compressed data, which is a compressed value obtained by compressing a plurality of movement values composed of movement values corresponding to a plurality of different determination results as to whether or not winning is permitted, by the predetermined compression method. Compressed data storage means;
A movement value acquisition means for acquiring a movement value according to a determination result as to whether or not to allow the generation of a prize from the movement value compressed data stored in the compressed data storage means;
Derivation control means for performing control for deriving a display result on the variable display unit corresponding to the operation of the derivation operation means based on the movement value acquired by the movement value acquisition means when the derivation operation means is operated;
A slot machine, further comprising: Each comprising a plurality of variable display unit capable variable display by moving a plurality of types of identification information capable of identifying periodically,
After variable display of said variable display unit, in the variable variable display of the display unit derives a display result by stopping, a plurality of variable display portions of the display result combination winning can occur depending on the slot machine,
A game control microcomputer incorporating a control CPU for executing game control in the gaming machine based on the game control processing program;
A random number circuit that is built in or externally attached to the game control microcomputer and generates numerical data to be a random value;
With
The random number circuit includes:
Numeric value updating means for updating and outputting numerical data according to a predetermined procedure;
Random value storage means for capturing and storing numerical data output from the numerical value updating means as a random number value;
Including
The game control microcomputer is:
Control determining means for making a predetermined determination by the control CPU based on a random number value generated by the random number circuit;
While the numerical data output from the numerical value updating means based on the input of a predetermined signal is stored in the random number storage means, the random number storage means is turned on to restrict the storage of new numerical data, while the random value storage means A predetermined flag that is turned off when the numerical value data stored in is read by the control CPU at the read timing of the random number value and permits storage of new numerical data;
Control start time processing means for turning off the predetermined flag when game control is started with the activation of the control CPU;
Including
The slot machine is
A derivation operation means for operating for a player to derive a display result,
When the derivation operation means is operated, a movement value indicating a movement amount from the position where the derivation operation means is operated to a stop of the movement in a variable display unit corresponding to the derivation operation means is obtained by a predetermined compression method. Stored is the compressed compressed data, which is a compressed value obtained by compressing a plurality of movement values composed of movement values corresponding to a plurality of different determination results as to whether or not winning is permitted, by the predetermined compression method. Compressed data storage means;
A movement value acquisition means for acquiring a movement value according to a determination result as to whether or not to allow the generation of a prize from the movement value compressed data stored in the compressed data storage means;
Derivation control means for performing control for deriving a display result on the variable display unit corresponding to the operation of the derivation operation means based on the movement value acquired by the movement value acquisition means when the derivation operation means is operated;
A slot machine, further comprising:

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