JP4776316B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachinko gaming machine, and more specifically, based on the fact that a game is played by driving game media into a gaming area, and a variable display start condition is satisfied after a variable display execution condition is satisfied. And a variable display device that variably displays a plurality of types of identification information that can be individually identified. The game medium is paid out based on the winning of the game medium in the winning area in the gaming area, and the display result of the variable display is predetermined. The present invention relates to a gaming machine that controls a specific gaming state advantageous to a player when a specific display result is obtained.

  As a gaming machine such as a pachinko gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and a predetermined number of prize balls are awarded when the game medium wins a prize area such as a prize opening provided in the game area. There are many things that can be paid out to players. Further, variable display is performed by updating or scrolling display of predetermined identification information (hereinafter referred to as display symbol) on a display device such as a liquid crystal display (hereinafter referred to as LCD: Liquid Crystal Display), and a predetermined game based on the display result. There is a game that enhances the game interest by a so-called variable display game that determines whether or not to add value.

  A special figure game that is performed as one of the variable display games is a variable display of a display symbol based on the detection of a game ball that passes through the start winning opening (that the variable display start condition is satisfied). In the game, the “hit” is defined as a case where the stop symbol form when the display is completely stopped is a predetermined specific display form. In this special figure game, when a “hit” is made, a special electric accessory called a big prize opening or an attacker is opened, and a state in which a game ball can be won extremely easily is provided to a player for a certain period of time. . Such a state is referred to as a “specific game state” or a “hit game state”.

The progress of the game in such a gaming machine is controlled by game control means including a microcomputer or the like. And when power supply to the gaming machine is started, it is generated periodically after setting to update the random number value used to determine whether or not to make the random number circuit “big hit” Has been proposed that permits execution of timer interrupt processing (for example, Patent Document 1).
Japanese Patent Laying-Open No. 2005-103166

In addition, the payout of prize balls performed when a game medium is won in a prize area provided in the game area is generally divided for each prize, but recently, the prize balls are divided for each prize. There has also been proposed a gaming machine that is continuously performed (for example, Patent Document 2).
JP 2001-212321 A

  The gaming machine described in Patent Document 2 includes game control means for controlling the progress of a game, payout means for paying out game media, and payout control means for controlling the payout operation of the payout means. In response to the winning of the game medium in the winning area, a control command for designating the number of prize balls is transmitted to the payout control means. The payout control means also stores a game medium detection means for detecting the game medium paid out from the payout means, and the sum of the number of prize balls indicated by the received control command. The game medium is detected by the game medium detection means. A total prize ball counter that decrements the total number of prize balls by 1 each time it is played, and each time a control command transmitted from the game control means is received, the number of prize balls indicated by the control command is total prize Sequentially add to the value of the ball counter. The payout control means continuously executes payout of prize balls until the value of the total prize ball number counter becomes zero.

  According to the technique described in Patent Document 1, the initial value (start value of the first round) of a random number that is set when power supply to a gaming machine is started is different even in different game control microcomputers. I can't. Therefore, there is a problem in that a “big hit” may be illegally generated by generating a signal for taking in a random number value at a timing when a predetermined time has elapsed from the start of power supply.

  Further, according to the technique described in Patent Document 2, since the payout of the winning ball is continuously executed by directly referring to the value of the total winning ball number counter, the last winning ball has been paid out. When this prize ball is not detected by the detection means, the value of the total prize ball number counter does not become zero. As a result, the payout control means continues the payout operation even though the last prize ball has been paid out, and there is a possibility that extra prize balls will be paid out.

  This invention is made in view of the said actual condition, and makes it a subject to enable generation | occurrence | production of the random number with high randomness. Another object of the present invention is to improve the certainty of payout control of game media and realize a quick payout operation.

In order to solve the above-described problem, a gaming machine according to claim 1 of the present application performs a game by driving a game medium (for example, a game ball) into a game area, and executes a variable display execution condition (for example, a normal variable winning ball apparatus) (The game ball wins at the start winning opening provided in FIG. 6) is established, and then the variable display start condition (for example, the previous special figure game by the special symbol display device 4 or the big hit game state is finished) is established. And a variable display device (for example, the special symbol display device 4 or the image display device 5) that variably displays a plurality of types of identification information (for example, special symbols or decorative symbols) that can be identified based on The game media wins in the winning areas (for example, the start winning opening provided in the normal variable winning ball apparatus 6, the large winning opening provided in the special variable winning ball apparatus 7, the winning openings 42A to 42D, etc.). The game medium is paid out based on the fact that the specific display is advantageous to the player when the display result of the variable display becomes a predetermined specific display result (for example, a jackpot symbol or a combination of jackpot symbols) A gaming machine (for example, pachinko gaming machine 1 or the like) that is controlled to a state (for example, a big hit gaming state), and a launching means (for example, launching device 19 or the like) for launching a game medium and driving it into the game area; Shooting operation means (such as operation knob 30) operated by the player to drive the firing means, and contact detection means (such as touch sensor 75) that detects whether or not the player is in contact with the firing operation means. ), And a winning detection means (for example, start port switch 22, count switch) that detects that the game medium has won in the winning area and outputs a winning detection signal. 24, winning port switches 25A to 25D, etc.), payout means (for example, payout motor 51) for performing a game medium payout operation, and payout detection means for detecting the game media paid out by the payout operation of the payout means ( For example, a payout count switch 72) and whether or not a predetermined amount or more of game media is stored in a storage portion (for example, the lower plate 33) in which the game media paid out by the payout operation of the payout means is stored. A storage state detection means for detecting (for example, a full switch 26) and a random number circuit (for example, a random number circuit 103) for generating random numbers are incorporated, and a winning detection signal is input from the winning detection means, and the progress of the game is progressed. A game control process to be controlled (for example, the processing of S71 to S85 by timer interruption) is executed, and a payout control signal (for example, payout) is used to control the payout means. A game control board (for example, the main board 11) on which a game control microcomputer (for example, the game control microcomputer 100, etc.) for transmitting a control signal that becomes an output control command, and the game control microcomputer is used. A payout control microcomputer (e.g., payout control microcomputer 150) that executes a payout control process (e.g., the processing of S531 to S538 by timer interruption) in accordance with the sent payout control signal. ) Is mounted, and the random number circuit has a predetermined range from a predetermined initial value within a predetermined range in which numerical data can be updated based on an input of a predetermined signal. Numeric value that is updated cyclically according to a predetermined sequence up to the final value. Means (for example, random number generation circuits 173A, 173B, etc.) and random number storage means (for example, random value registers 181A, 181B, etc.) for storing numerical data updated by the numerical value updating means as random number values. In response to the input of the winning detection signal, the microcomputer for payout uses the payout number signal indicating the number of game media to be paid out (for example, first to third payout number designation commands) as the payout control signal for the payout control. The number-of-payout signal transmission means to be transmitted to the microcomputer (for example, the part that executes the payout command control process in step S81 after the CPU 104 executes one of the processes in steps S408, S410, and S411) and the gaming machine After power supply is started, the random number circuit is set to generate the random number. The circuit setting unit (for example, the part that executes the 12-bit random number initial setting process or the 16-bit random number initial setting process in step S22 after the CPU 104 executes the process of step S21) and the random number circuit setting unit perform setting. Timer interrupt process execution permitting means (for example, the part where the CPU 104 executes the process of step S25) that permits the execution of the timer interrupt process that occurs periodically, and the variable display during the execution of the timer interrupt process. It is determined that the execution condition for the variable display is satisfied by the execution condition determination means (for example, the part where the CPU 104 executes the process of step S351) and the execution condition determination means for determining whether or not the execution condition is satisfied. The random number value reading means for reading the random number value stored by the random number value storage means (for example, For example, the CPU 104 executes a winning process in step S352) and whether the random number value read by the random value reading means matches a predetermined determination value data. Display result determining means for determining whether or not the display result is a specific display result (for example, a portion where the CPU 104 executes the variable display start processing in step S361), and the game control board includes the contact detection means The game device launches the game medium on the condition that the player's contact is detected and the storage state detection device detects that a predetermined amount or more of game media is not stored in the storage unit. The emission permission signal output means for outputting the emission permission signal for allowing the operation (for example, the part where the CPU 104 executes the processing of steps S201 to S207) The random number circuit setting means sets a value based on unique identification information assigned to each game control microcomputer to the predetermined initial value. An initial value setting means (for example, a portion where the CPU 104 executes the processes of steps S104 and S126), and the payout control microcomputer receives the payout number signal transmitted by the payout number signal transmission means. The signal receiving means (for example, the part where the CPU 214 executes the processing of steps S601 to S607) and the number of game media specified from the payout number signal received by the payout number signal receiving means are cumulatively stored as the unpaid number. Unpaid number storage means (for example, a prize ball unpaid counter and the CPU 214 performs processing in step S608). ), A payout operation amount storage means (for example, a payout motor rotation counter) that stores a payout operation amount that can specify the end of the payout operation by the payout means, and the payout detection means An unpaid-out number updating means for updating the unpaid-out number stored in the unpaid-out number storage means according to the number of game media (for example, a portion where the CPU 214 executes the processes of steps S805 and S814), and the unpaid-out Based on the fact that the unpaid number is stored in the number storage means, the payout operation amount setting means (for example, the CPU 214 performs steps S805, S806, S843, and S844) that stores the payout operation amount in the payout operation amount storage means. Etc.) and the payout stored in the payout operation amount storage means according to the progress of the payout operation by the payout means The payout operation amount update means for updating the operation amount (for example, the part where the CPU 214 executes the process of step S829) and the payout operation amount stored in the payout operation amount storage means match the predetermined end value data. A payout operation amount determination means (for example, a portion where the CPU 214 executes the process of step S825) and the payout operation amount setting means store the payout operation amount in the payout operation amount storage means. In response to the payout means, the payout means continuously executes the payout operation until the payout operation amount determination means determines that the predetermined end value data is matched. Is a part for executing the process of step S828 until the CPU 214 determines Yes in step S825. The payout operation amount setting means determines whether or not the unpaid number stored in the unpaid number storage means has increased during execution of the payout operation by the payout means. An increase in the unpaid number is specified when it is determined that the unpaid number has increased by means (for example, the part where the CPU 214 executes the process of step S842) and the increase determination unit during payout The payout operation amount storage means stores the payout operation amount corresponding to the increase specified by the increase amount specifying means (for example, the part where the CPU 214 executes the process of step S843) and the increase specified by the increase amount specifying means. see containing payout operation amount adding means (e.g. CPU214 portions such as to perform the processing of step S844) to be added to the amount and, further, the game control microphone The computer uses a random number circuit (for example, an initial value setting circuit 172A, a random number generation circuit 173A, a selector 174A, an ARSC 175A, a random number sequence change circuit 176A, a maximum value comparison, and the predetermined update range of numerical data that can be updated by the numerical value updating means. A component for generating a 12-bit random number including a circuit 177A and a random value register 181A, a clock signal output circuit 171, an initial value setting circuit 172A, a random number generation circuit 173B, a selector 174B, a BRSC 175B, a random number sequence change circuit 176B, a maximum value comparison Circuit 177B, inversion circuit 178, timer circuit 179, latch signal generation circuit 180, random number value register 181B, and the like. Set the random number circuit to use from Use random number circuit setting means (for example, when bits 4 and 3 of KRSS1 and the read value in step S21 by the CPU 104 are other than “00”, 12-bit random number initial setting processing and 16-bit random number initial setting in step S22) A part for executing at least one of the processes) and random number circuit stop means for stopping the function of a random number circuit other than the set random number circuit when used by the used random number circuit setting means (for example, bits 4 and 3 of KRSS1) When the read value in step S21 by the CPU 104 is other than “11”, a portion in which at least one of the 12-bit random number initial setting process and the 16 random number initial setting process is not executed in step S22 is included.

  The present invention has the following effects.

According to the gaming machine of the first aspect, after the gaming control microcomputer starts to supply power to the gaming machine and before the timer interruption processing execution permission means is permitted to execute the timer interruption processing, Random number circuit setting means for performing settings for generating random numbers in the random number circuit is included. The random number circuit setting means includes an initial value setting means for setting a value based on the unique identification information assigned to each game control microcomputer to an initial value when the numerical data is updated by the numerical value updating means. It is configured.
Thereby, the initial value of the random number that starts updating after the power supply is started can be made different for each gaming machine, and is used for determining whether or not the display result in the variable display is the specific display result. It is possible to increase the randomness of the generated random number and prevent the specific display result from being illegally generated.
Further, the payout control microcomputer is provided in an unpaid number update means for updating the unpaid number stored in the unpaid number storage means according to the number of game media detected by the payout detection means, and an unpaid number storage means. The payout operation amount setting means for storing the payout operation amount in the payout operation amount storage means based on the storage of the unpaid number, and the payout operation amount storage means according to the progress of the payout operation by the payout means. The payout operation amount update means for updating the payout operation amount, and after the payout operation by the payout means is started, the payout operation amount stored in the payout operation amount storage means by the payout operation amount determination means is the predetermined end value data. It is configured to include continuous payout control means for continuously executing a payout operation until it is determined that they match. Then, the payout operation amount setting means increases the increase amount when the payout increase determination means determines that the unpaid number stored in the unpaid number storage means has increased during execution of the payout operation by the payout means. The payout operation amount adding means for adding the payout operation amount corresponding to the increase in the unpaid number specified by the specifying means to the payout operation amount stored in the payout operation amount storage means is included.
Thus, when the payout operation by the payout means is being executed, the payout operation amount corresponding to the number of game media specified from the received payout number signal is set as the payout operation amount stored in the payout operation amount storage means. The payout operation is continuously executed until the payout operation amount matches the predetermined end value data, so that a quick payout operation can be realized.
In addition, the payout operation amount stored in the payout operation amount storage means is updated as the payout operation proceeds by the payout means, and the payout operation by the payout means stops when the payout operation amount matches the predetermined end value data. On the other hand, the number of unpaid numbers stored in the unpaid number storage means is updated based on the number of game media detected by the payout detecting means after the payout operation by the payout means is completed. Can be prevented from being paid out. Further, since the payout operation amount is stored in the payout operation amount storage means based on the fact that the unpaid number is stored in the unpaid number storage means, the payout operation by the payout means is resumed when there is an unpaid game medium. It is possible to prevent the game medium from being paid out in short. In this way, the certainty of the payout control can be improved.
Further, the game control microcomputer is configured to incorporate a plurality of random number circuits having different predetermined update ranges of numerical data that can be updated by the numerical value updating means. The random number circuit setting means includes: a random number circuit setting means for setting a random number circuit to be used from among a plurality of random number circuits; and a random number circuit stopping means for stopping a function of a random number circuit other than the set random number circuit when used. It is comprised so that it may contain.
This makes it possible to set the random number circuit corresponding to the random number used according to various determinations, such as determining whether or not the display result of variable display is the specific display result, and reduce the processing load required for the determination. can do.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a front view of a pachinko gaming machine 1 according to the present embodiment, and shows an arrangement layout of main members. The pachinko gaming machine (gaming machine) 1 is roughly composed of a gaming board (gauge board) 2 constituting a gaming board surface and a gaming machine frame (base frame) 3 for supporting and fixing the gaming board 2. The game board 2 is formed with a substantially circular game area surrounded by guide rails.

  A special symbol display device 4 for variably displaying a special symbol as identifiable identification information is provided above the central position of the game area. Below the special symbol display device 4, there is provided an image display device 5 capable of performing variable display of decorative symbols different from the special symbol, image display for a predetermined effect display, and the like. Below the image display device 5, an ordinary variable winning ball device 6 that forms a start winning opening is arranged. Below the ordinary variable winning ball apparatus 6, a special variable winning ball apparatus 7 that forms a large winning opening and a normal symbol display 40 are provided.

  The special symbol display device 4 includes, for example, 7-segment or dot matrix LEDs. The special symbol display device 4 is, for example, “0” to “9” in a special game as a variable display game performed based on the fact that the start condition is established by winning a game ball in the normal variable winning ball device 6. The special symbol which consists of the number etc. which show and functions as several types of identification information which can identify each is variably displayed. Each special symbol is assigned a symbol number corresponding to each special symbol, for example, the same number as the number indicated by each symbol. The special symbol display device 4 is configured to variably display more types of symbols such as numbers indicating “00” to “99” in order to make it difficult for the player to grasp a specific stop symbol. It may be.

  In the special symbol game performed by the special symbol display device 4, when a predetermined time elapses after the variation of the special symbol is started, the fixed special symbol that is a variable symbol display result is stopped (derived display). At this time, if a special symbol (big hit symbol) is stopped and displayed as a confirmed special symbol in the special symbol game on the special symbol display device 4, it becomes a “big hit” as a specific display result, and a special symbol other than the big bonus symbol is displayed. If it is stopped, it will be “lost”. When the variation display result in the special figure game is “big hit”, the big hit game state as the specific game state is controlled by opening and closing the opening / closing plate of the special variable winning ball apparatus 7. In the pachinko gaming machine 1 according to this embodiment, as a specific example, a special symbol indicating “7” is a jackpot symbol, and a special symbol indicating other numerical values is a lost symbol.

  In the jackpot gaming state based on the special symbol indicating “7” which is a jackpot symbol as a confirmed special symbol in the special symbol game by the special symbol display device 4, by the opening / closing plate of the special variable winning ball device 7, A game ball that drops on the surface of the game board 2 during a predetermined opening period (for example, 29 seconds) or a period until a predetermined number (for example, 10) of winning balls are generated and the large winning opening is opened. Is received, and it becomes possible to enter the grand prize opening, and then the round is closed by closing the grand prize opening. The round as the open / close cycle can be repeated up to a predetermined upper limit number (for example, 15 rounds).

  The image display device 5 is composed of, for example, an LCD or the like, and may be any device that performs screen display by a dot matrix method using a large number of pixels (pixels). On the display screen of the image display device 5, each can be identified by, for example, a variable display section as a display area divided into three corresponding to the special symbol variation display in the special symbol game by the special symbol display device 4. A variable display that displays various types of decorative designs in a variable manner is performed. As a specific example, variable display portions “left”, “middle”, and “right” are arranged on the image display device 5, and decorative symbols are variably displayed on the variable display portions. When the special symbol variation display on the special symbol display device 4 is started, the decorative symbol variation display (for example, switching) is displayed on each of the “left”, “middle”, and “right” variable display portions in the image display device 5. Display and scroll display) is started, and thereafter, when the confirmed special symbol is stopped and displayed as a special symbol variation display result in the special symbol display device 4, "left", "middle", "right" in the image display device 5 ”Is stopped and displayed on each variable display section, and the combination of decorative designs that are variable display results is stopped and displayed (derived display).

  For example, in each of the “left”, “middle”, and “right” variable display portions, symbols representing ten types of numbers “0” to “9” are displayed as decorative symbols in a variable manner. Each decorative symbol is given a symbol number corresponding to each decorative symbol, for example, the same number as the number indicated by each symbol. Then, in each of the “left”, “middle”, and “right” variable display sections, when the decorative symbol variation display is started, for example, the display from which the number indicated by the symbol is changed to the larger one is switched or scrolled. When the decorative symbol indicating “9” is displayed, the decorative symbol indicating “0” is displayed next. Then, when the special symbol determined in the special symbol game on the special symbol display device 4 is a big hit symbol, that is, when a big hit occurs, a fixed combination of “left”, “middle” and “right” is determined by a predetermined combination. The decorative design is stopped and displayed. Specifically, when the confirmed special symbol in the special symbol game is a special symbol indicating “7” as a jackpot symbol, the same decorative symbol is displayed on the “left”, “middle”, and “right” variable display portions. Is stopped.

  In this embodiment, the decorative symbols “1”, “3”, “5”, “7” or “9” whose symbol numbers are odd numbers are used as decorative symbols (probable variable symbols) for probability variation big hits. The decorative pattern “0”, “2”, “4”, “6” or “8” in which is an even number is usually used as a decorative pattern for a big hit (normal pattern). When the same probability variation symbol (decorative symbol combination symbol ornament) is stopped and displayed on the variable display portion of “left”, “middle”, and “right” as a variable symbol display result, a probability variation big hit is obtained. When a promising big hit is reached, after the big hit gaming state based on the probable big hit is finished, until a special number of games (for example, 100 times) is executed or until a variable display result in the special figure game becomes a big hit As one of the special game states, a high probability state (probability improvement state) in which probability variation control (probability variation control) is continuously performed is obtained. In this high probability state, the probability that the jackpot symbol is stopped and displayed as a variable display result in the special figure game and is controlled to the jackpot gaming state is improved as compared with the normal gaming state. The normal gaming state is a gaming state other than the big hit gaming state or the special gaming state, and the probability that the big hit symbol is stopped and displayed as a confirmed special symbol in the special figure game, such as immediately after the power is turned on. It is controlled in the same way as the initial setting state.

  When the same normal symbol (decorative symbol of a combination of normal jackpots) is stopped and displayed on the variable display portions “left”, “middle”, and “right” as a variable display result of the decorative symbols, a normal big hit is obtained. Since the probability change control is not performed when the normal big hit, the probability that the variable display result in the special figure game becomes a big hit and is controlled to the big hit gaming state is not improved. On the other hand, when a big hit is made, a high probability state is until a predetermined number of times (for example, 100 times) the execution of a special figure game is started, or until the execution of a special figure game that is a big hit is started. As one of the different special game states, a time reduction state in which time reduction control (time reduction control) is continuously performed may be set. In the time reduction state where the time reduction control is performed, the probability of being a big hit in each special figure game and being controlled to the big hit gaming state is the same as the normal gaming state, but the special symbol variable display is started in the special figure game. The variable display time, which is the time from when the displayed special symbol as the display result is stopped and displayed, is controlled to be shorter than the normal gaming state.

  In each of the “left”, “middle”, and “right” variable display portions, a plurality of types of symbols representing alphabets may be displayed as decorative designs in a variable manner, or a plurality of types of character designs related to a predetermined motif May be variably displayed as a decorative pattern. Further, in the image display device 5, during the execution of the special symbol game by the special symbol display device 4, it is possible to perform effect display in any of various effect modes. The variable display unit may be a fixed area, but may move or change in size in the display area of the image display device 5 while the game is in progress.

  In addition, the image display device 5 has a special symbol start memory display area for displaying the number of effective winning balls, that is, the number of reserved memories (starting winning memory number) entered into the starting winning opening provided in the normal variable winning ball device 6. It may be provided. In the special symbol start memory display area, a winning display is performed in response to an effective start winning when the number of reserved memories is less than a predetermined upper limit (for example, “4”). As a specific example, the display that is normally blue is changed to a red display. In this case, by providing the decorative symbol display area (variable display portion) and the special symbol start memory display area separately, the number of reserved memories can be displayed during variable display of decorative symbols. The special symbol start memory display area may be provided in a part of the decorative symbol display area. In this case, the display of the reserved storage number may be interrupted during the variable display of the decorative design. In this way, when the number of reserved memories is displayed in the special symbol start memory display area provided in the image display device 5, the special effect control microcomputer 120 (FIG. 5) mounted on the effect control board 12 performs a special operation. The display operation of the number of reserved memories in the symbol start memory display area is controlled. On the other hand, even when the reserved memory number is displayed in the special symbol start memory display area, an indicator (special memory) that displays the reserved memory number under the control of the game control microcomputer 100 (FIG. 5) mounted on the main board 11. A symbol start memory display) may be provided separately from the image display device 5.

  The normal variable winning ball apparatus 6 is a tulip-type accessory (ordinary electric motor) having a pair of movable wing pieces that are movable and controlled between a vertical (normally open) position and a tilt (enlarged open) position by a solenoid 81 (FIG. 5). (Community). The normal variable winning ball apparatus 6 is configured to wait until a predetermined time elapses when the display result is “winning” in the variable symbol display (ordinary symbol game) on the normal symbol indicator 40. By controlling to the tilting position, it becomes easier for the game ball to win the start winning opening than when the movable wing piece is set to the vertical position. The game ball that has won the normal variable winning ball device 6 is detected by the start port switch 22 (FIGS. 2 and 5). Based on the detection of the game ball by the start port switch 22, a predetermined number (for example, four) of prize balls are paid out.

  The special variable winning ball apparatus 7 includes an opening / closing plate that opens and closes a large winning opening by a solenoid 82 (FIG. 5). This opening / closing plate is used for a predetermined period or a period until a predetermined number of winning balls are generated when a big hit gaming state is obtained based on a variation display result in a special symbol game by the special symbol display device 4. As a first state which is advantageous to the user, the large winning a prize opening is opened by the solenoid 82 and then closed. On the other hand, at a normal time, for example, before the big hit gaming state occurs after the power of the pachinko gaming machine 1 is turned on, the prize winning opening is closed by the solenoid 82 as a second state disadvantageous to the player. When the special variable winning ball device 7 opens the big winning opening when the open / close plate opens, the gaming ball is detected by the count switch 24 (FIGS. 2 and 5). Based on this, a predetermined number (for example, 15) of prize balls are paid out. Of the game balls that were won at the grand prize opening and led to the back of the game board 2, those that entered one area (V winning area; special area) were detected by the V winning switch 23 (FIG. 5). A game ball that is later detected by the count switch 24 and enters the other area may be detected by the count switch 24 as it is. In this case, a solenoid for switching the route in the special winning opening may be provided on the back of the game board 2. Alternatively, it may be possible to always shift to the next round in a round other than the final round in the big hit gaming state without providing the V winning area.

  The game board 2 is provided with a plurality of winning holes 42A to 42D, and winning of game balls to the winning holes 42A to 42D is detected by winning hole switches 25A to 25D (FIGS. 2 and 5), respectively. . Based on the detection of the game balls by the winning ports 42A to 42D, a predetermined number (for example, 7) of payout balls is paid out. That is, each of the winning openings 42A to 42D constitutes a winning area provided in the game board 2 as an area for accepting a game ball as a game medium and allowing winning. In addition, the start winning opening formed in the normal variable winning ball apparatus 6 and the large winning opening formed in the special variable winning ball apparatus 7 constitute a winning area that accepts a game ball as a game medium and allows winning. .

  FIG. 2 is an explanatory diagram showing the relationship of each switch for detecting a game ball won in a winning area such as a winning opening provided on the game board 2. As shown in FIG. 2, the game balls detected by the start port switch 22, the count switch 24, and the winning port switches 25 </ b> A to 25 </ b> D are, for example, the installation positions of the all winning ball detection switches 29 on the back of the game board 2. Is detected by the all winning ball detection switch 29. Here, the installation position of the all winning ball detection switch 29 may be, for example, a position where the winning ball paths meet or a predetermined position downstream of the position.

  The normal symbol display 40 is composed of, for example, an LED or the like, and in a normal diagram game in which a game ball that has passed through a passing gate 41 provided in the gaming area is detected by the gate switch 21 (FIG. 5). , Lighting, blinking, coloring, etc. are controlled. When display is performed with a predetermined hit pattern in the normal game, the display result in the normal game is “win”. Here, in the above-described high probability state and time reduction state, the variable display time in the normal game by the normal symbol display device 40 is shorter than that in the normal game state, and the display result is the winning symbol in each normal game. May be improved. At this time, the tilting time of the movable wing piece in the normal variable winning ball apparatus 6 may be longer than that in the normal gaming state, and the number of tilts may be increased compared to that in the normal gaming state. As described above, in the high probability state and the time reduction state, the gaming state is advantageous to the player, which is different from the big hit gaming state. Here, in the time shortening state, probability variation control is not performed, and the probability of being in the big hit gaming state is the same as in the normal gaming state, so the high probability state is more advantageous for the player than the time shortening state.

  In addition to the above-described configuration, the game area of the game board 2 is provided with a windmill having a decorative lamp, an outlet, and the like. Two speakers 8L and 8R that emit sound effects are provided on the left and right upper portions outside the game area. A game effect lamp 9 that is lit or blinks is provided on the outer periphery of the game area. In addition, a prize ball lamp that is turned on when there is a remaining number of prize balls may be provided on the outer left side of the game area. An out-of-ball lamp may be provided on the outer top of the game area, which is turned on when the supply ball is cut.

  An upper plate 32 as a hitting ball supply tray is provided on the lower surface of the game area. The game balls stored in the upper plate 32 are supplied to the launching device 19 (FIG. 5) when the ball feeding device 62 (FIG. 5) is driven. Below the upper plate 32, a lower plate 33 is provided as an extra ball receiving tray for storing game balls that cannot be accommodated in the upper plate 32. An operation knob 30 that is operated by a player or the like to drive the launching device 19 to launch a game ball toward the game area is provided at the lower right position outside the game area. The operation knob 30 includes a touch sensor 75 (FIG. 5) for detecting that the player is touching the operation knob 30 based on a change in capacitance, and single-shot control for playing a game ball at a predetermined interval. A single firing switch (not shown) for switching to is provided. Single shot control is control which discharges a game ball according to the input timing of the signal from a single shot switch.

  Further, FIG. 1 also shows a prepaid card unit (hereinafter referred to as a card unit) 70 that is installed adjacent to the pachinko gaming machine 1 and enables lending of a ball by inserting a prepaid card. The card unit 70 includes a usable indicator lamp that indicates whether or not the card unit 70 is in a usable state, a connection table direction indicator that indicates which side of the pachinko gaming machine 1 corresponds to the card unit 70, and the card unit 70. When checking the card insertion indicator lamp indicating that a card is inserted in the card, the card insertion slot into which the card as a recording medium is inserted, and the card reader / writer mechanism provided on the back of the card insertion slot A card unit lock or the like for opening the card unit 70 is provided.

  FIG. 3 is a rear view of the pachinko gaming machine 1. Above the back of the pachinko gaming machine 1, there are provided a storage tank 65 for storing game balls as supply balls and a guide rail 66 for guiding the game balls stored in the storage tank 65 to the payout case 17. The downstream side of the guide rail 66 communicates with the two rows of ball passages 80a and 80b via a curve rod. A ball break switch 27 is installed upstream of the ball passages 80a and 80b. As an example, the ball break switch 27 is locked by a locking piece at a position where it can be detected that 27 to 28 game balls are present in the ball passages 80a and 80b, and the maximum payout number of one unit of ball lending It is possible to confirm that at least (for example, 25 pieces corresponding to 100 yen) is secured.

  A payout case 17 is fixed to the lower part of the ball passages 80a and 80b. A launching device 19 for launching a game ball and driving it into the game area is provided near the back of the operation knob 30. In addition, a full tank switch 26 is provided on the side wall of the surplus ball passage that communicates between the upper plate 32 as the hitting ball supply tray and the lower plate 33 as the surplus ball receiving tray below the back of the pachinko gaming machine 1. Yes. For example, when a large number of game balls based on award balls or ball lending requests are paid out and the upper plate 32 is full and the game balls reach the contact port, and the game balls are further paid out, After that, it is guided to the lower plate 33. When a game ball is paid out and a predetermined amount or more of game balls are stored in the lower plate 33, for example, a predetermined sensing lever is pressed by pressing the full switch 26.

  FIG. 4 is an exploded perspective view showing a configuration example of the dispensing device covered with the dispensing case 17. In this example, a payout device is formed inside three cases 91, 92, 93 as the payout case 17. The upper portions of the cases 91 and 92 are provided with holes 85 and 86 communicating with the ball passages 80a and 80b, respectively, and the game balls flow into the payout device through the holes 85 and 86. The payout device pays out a winning ball or a game ball based on a ball rental request, and includes a payout motor 51 serving as a drive source. The payout motor 51 may be configured using, for example, a stepping motor. In this case, the rotation operation of the dispensing motor 51 is controlled by exciting the first to fourth phases (φ1 to φ4) according to the dispensing drive signal sent from the dispensing control board 15.

  A gear 87 is fitted on the rotation shaft of the payout motor 51, and a gear 88 that meshes with the gear 87 and a cam that has a ball placement portion that fits on the central axis of the gear 88 inside the payout case 17. 89 and a ball passage 90 below the cam 89 are provided. For example, the game balls that have flowed in through the holes 85 and 86 fall one by one alternately through the ball passage 90 every time the ball mounting portion of the cam 89 rotates 1/3. Further, inside the dispensing case 17, a dispensing motor position sensor 71 composed of, for example, a light emitting element (LED) and a light receiving element is provided. The payout motor position sensor 71 is a sensor for detecting the rotational position of the payout motor 51, and is used for detecting the clogging of game balls in the payout motor 51, so-called ball biting. At the lower part of the ball passage 90 provided inside the payout case 17, for example, a payout count switch 72 by a proximity switch is arranged. The payout count switch 72 is turned on every time one game ball falls from the ball passage 90 and transmits a predetermined detection signal to the payout control board 15.

  In addition, on the back of the pachinko gaming machine 1, main boards such as a power supply board 10, a main board 11, an effect control board 12, an audio control board 13, a lamp control board 14, a payout control board 15, and an information terminal board 16 are provided at appropriate positions. Is arranged. FIG. 5 is a block diagram illustrating a system configuration example centering on various control boards such as the power supply board 10, the main board 11, the effect control board 12, the sound control board 13, and the lamp control board 14. Between the main board 11 and the effect control board 12, a relay board 18 for relaying various control signals transmitted from the main board 11 to the effect control board 12 is also provided. The interface board 20 is interposed between the payout control board 15 and the card unit 70. Note that the audio control board 13 and the lamp control board 14 may be configured as independent boards that are separate from the effect control board 12, or may be integrated into the effect control board 12 and configured as one board.

  The power supply board 10 is installed independently of each control board such as the main board 11, the effect control board 12, and the payout control board 15, and generates a voltage used by each control board and mechanism component in the pachinko gaming machine 1. For example, as shown in FIG. 6, the power supply substrate 10 generates AC 24 V, VLP (DC +24 V), VSL (DC +30 V), VDD (DC +12 V), VCC (DC +5 V), and VBB (DC +5 V). For example, as illustrated in FIG. 6, the power supply substrate 10 includes a transformer circuit 301, a DC voltage generation circuit 302, a power supply monitoring circuit 303, and a clear switch 304. Further, the power supply substrate 10 may be provided with a capacitor serving as a backup power supply. For example, this capacitor may be charged from a power supply line of VBB (DC + 5V). In addition, the power supply board 10 may be provided with a power switch for executing or shutting off power supply to each control board and the mechanical components in the pachinko gaming machine 1. Alternatively, the power switch may be provided outside the power supply board 10 in the pachinko gaming machine 1.

  For example, the transformer circuit 301 may be configured to include a transformer to which commercial power is applied to the input side (primary side), a varistor as an overvoltage protection circuit provided on the input side of the transformer, and the like. Here, the transformer included in the transformer circuit 301 may be any one that electrically insulates the commercial power supply from the power supply substrate 10. The transformer circuit 301 generates AC 24V as its output voltage. The DC voltage generation circuit 302 includes, for example, a rectifying / smoothing circuit that generates VSL by rectifying and boosting AC 24V with a rectifying element. VSL is used as a power supply voltage for driving the solenoid. Further, the DC voltage generation circuit 302 includes a rectifier circuit that generates VLP by rectifying AC24V with a rectifier, for example. VLP is used as a power supply voltage for lighting the lamp. In addition, the DC voltage generation circuit 302 includes a DC-DC converter that generates VDD and VCC based on, for example, VSL. This DC-DC converter includes, for example, one or a plurality of switching regulators and a relatively large capacitor connected to the input side of the switching regulator, and power supply to the pachinko gaming machine 1 from the outside is stopped. Sometimes, it may be configured so that the direct current voltage such as VSL, VDD, VBB, etc. decreases relatively slowly. The VDD is supplied to various switches for detecting game media such as the gate switch 21, the start port switch 22, the V winning switch 23, the count switch 24, the winning port switches 25A to 25D, and the all winning ball detection switch 29. Used to activate the switch.

  As shown in FIG. 6, AC24V output from the transformer circuit 301 is transmitted to the payout control board 15 via a predetermined connector or a power supply line, for example. The VLP is transmitted to the lamp control board 14 via, for example, a predetermined connector or a power supply line. The VSL is transmitted to the main board 11, the lamp control board 14, the payout control board 15, the launching device 19, and the ball feeding device 62 through, for example, a predetermined connector and a power supply line. The VSL transmitted to the launcher 19 is used as a drive voltage (solenoid drive voltage) for driving (exciting) the launch solenoid 19C (FIG. 8) to launch a game ball. The VSL transmitted to the ball feeding device 62 is used as a driving voltage for driving a ball feeding solenoid or motor to supply a game ball to the launching device 19. The drive voltage supplied to the launching device 19 and the ball feeding device 62 may be supplied directly from the power supply board 10 or may be supplied via another control board such as the main board 11. VDD and VCC are transmitted to the main board 11, the lamp control board 14, and the payout control board 15 through, for example, predetermined connectors and power supply lines. The VBB is transmitted to the main board 11 and the payout control board 15 through, for example, a predetermined connector and a power supply line. Note that each voltage may be supplied to the effect control board 12 and the sound control board 13 via the lamp control board 14.

  The power monitoring circuit 303 is configured by using, for example, a power failure monitoring reset module IC, and is a circuit that realizes a power monitoring unit that outputs a power interruption signal. For example, the power supply monitoring circuit 303 has a predetermined period of time (56 milliseconds as an example) during which the predetermined voltage (VLP as an example) used in the pachinko gaming machine 1 is equal to or lower than a predetermined value (+20 V as an example). When the above is continued, a power-off signal is output. Alternatively, the power monitoring circuit 303 may output a power-off signal immediately when a predetermined voltage used in the pachinko gaming machine 1 becomes a predetermined value or less. The power-off signal may be an electrical signal that is turned on when it is at a low level, for example. The power-off signal output from the power supply monitoring circuit 303 is amplified by, for example, an output driver circuit mounted on the power supply board 10 and then transmitted to the payout control board 15 via a predetermined connector or signal line. The condition for detecting the stop of the supply of power supplied to the pachinko gaming machine 1 from the outside is not limited to the fact that the predetermined voltage used in the pachinko gaming machine 1 has become a predetermined value or less. Any condition can be used as long as it is possible to detect that has stopped. For example, the AC wave such as AC 24V may be monitored to detect that the AC wave has stopped, or the signal obtained by digitizing the AC wave may be monitored and the AC signal may be generated when the digital signal becomes flat. It may be a detection condition for the interruption.

  The power supply monitoring circuit 303 may output a reset signal when, for example, a predetermined voltage (VCC as an example) becomes equal to or lower than a predetermined value (as an example, + 5V or more). The reset signal may be an electric signal that is turned on when the reset signal becomes low level, for example. The reset signal output from the power supply monitoring circuit 303 is amplified by, for example, an output driver circuit mounted on the power supply board 10, and then, via a predetermined connector or signal line, the main board 11, the lamp control board 14, and the payout control board. 15 is transmitted. It should be noted that a reset signal may be transmitted to the effect control board 12 via the lamp control board 14. Furthermore, the circuit that outputs the reset signal may be configured by using a watchdog timer built-in IC provided separately from the power supply monitoring circuit 303, a system reset IC, or the like.

  When the power supply to the pachinko gaming machine 1 is stopped, the power monitoring circuit 303 outputs a reset signal (sets to a low level) when a predetermined period has elapsed since the power-off circuit 303 outputs a power-off signal (sets to a low level) ) In this predetermined period, for example, the game control microcomputer 100 mounted on the main board 11 and the payout control microcomputer 150 mounted on the payout control board 15 may perform predetermined power-off processing (for example, in FIG. 27). It is sufficient that the time is sufficient to execute the main-side power-off process in step S27 shown, the payout-side power-off process in step S522 shown in FIG. That is, the power monitoring circuit 303 outputs a power-off signal as a power failure signal, and after the game control microcomputer 100 and the payout control microcomputer 150 complete execution of predetermined power-off processing, Output the reset signal (set to low level). The game control microcomputer 100 and the payout control microcomputer 150 that have received the reset signal output from the power supply monitoring circuit 303 are in an operation stop state, and execution of various control processes is stopped. In addition, when the power supply to the pachinko gaming machine 1 is started, for example, when a predetermined voltage (VCC as an example) exceeds a predetermined value (+5 V as an example), the power monitoring circuit 303 stops outputting the reset signal (high Level).

  FIG. 7 is a timing diagram schematically showing the states of the AC 24 V, VLP, VCC, reset signal, and power-off signal when power supply to the pachinko gaming machine 1 is started and when power supply is stopped. is there. As shown in FIG. 7, when power supply to the pachinko gaming machine 1 is started, VLP and VCC gradually reach specified values (DC + 24V and DC + 5V). At this time, when VLP exceeds the first predetermined value, the power supply monitoring circuit 303 stops outputting the power-off signal (sets it to a high level) and turns it off. When VCC exceeds the second predetermined value, the power supply monitoring circuit 303 stops outputting the reset signal (sets it to a high level) and turns it off. On the other hand, when the power supply to the pachinko gaming machine 1 is stopped, VLP and VCC gradually decrease. At this time, when the VLP drops to the first predetermined value, the power supply monitoring circuit 303 outputs the power-off signal as an ON state (sets it to a low level). When VCC decreases to the second predetermined value, the power supply monitoring circuit 303 outputs the reset signal as an ON state (sets it to a low level).

  The clear switch 304 included in the power supply substrate 10 illustrated in FIG. 6 has a push button structure, for example, and outputs a clear signal in response to an operation such as pressing. The clear signal may be an electric signal that is turned on when the clear signal is at a low level, for example. The clear signal output from the clear switch 304 is transmitted to the main board 11 via, for example, a predetermined connector or signal line. When the clear switch 304 is not operated, the output of the clear signal is stopped (set to a high level). Note that the clear switch 304 may have a configuration other than a push button structure (for example, a slide switch structure, a toggle switch structure, a dial switch structure, or the like).

  A main board 11 shown in FIG. 5 is a main-side control board on which various circuits for controlling the progress of the game in the pachinko gaming machine 1 are mounted. The main board 11 is a sub-side mainly composed of a random number setting function used in a special game, a function of inputting a signal from a switch arranged at a predetermined position, an effect control board 12, a payout control board 15, and the like. A control board is provided with a function of outputting and transmitting a control command as an example of command information as a control signal, and a function of outputting various information to a hall management computer. In addition, the main board 11 controls the special symbol display on the special symbol display device 4 by controlling the lighting / extinguishing of each segment constituting the special symbol display device 4, while the normal symbol display 40 is turned on. By controlling / flashing / coloring control, the normal symbol display on the normal symbol display 40 is controlled.

  In addition, the main board 11 has a function of executing a determination process for driving or stopping the launching device 19 and the ball feeding device 62 and transmitting a predetermined permission signal when driving. For example, when driving the launching device 19, an on-state launch permission signal is transmitted from the main board 11 to the launching device 19. Further, when the ball feeding device 62 is driven, an on-state supply permission signal is transmitted from the main board 11 to the ball feeding device 62.

  FIG. 8 is a block diagram showing a configuration example of the launching device 19 used in this embodiment. The launching device 19 shown in FIG. 8 includes an AND circuit 19A, a solenoid drive voltage generation circuit 19B, and a launching solenoid 19C. The AND circuit 19 </ b> A receives a launch permission signal transmitted from the main board 11 and a VL signal, which is a connection signal transmitted from the card unit 70 via the interface board 20, at its input terminals. The output signal from the AND circuit 19A is input to the solenoid drive voltage generation circuit 19B. When the output signal from the AND circuit 19A is on, the solenoid drive voltage generation circuit 19B uses the VSL supplied from the power supply board 10 to generate a solenoid drive voltage corresponding to the operation amount detection signal from the operation knob 30. Generate. On the other hand, when the output signal from the AND circuit 19A is in the OFF state, no solenoid drive voltage is generated. The firing solenoid 19C is excited by receiving the solenoid drive voltage supplied from the solenoid drive voltage generation circuit 19B, and the center excitation magnetic force, for example, directly accelerates the game ball or accelerates the hit ball to accelerate the game ball. The game ball is fired toward the game area by hitting.

  The solenoid drive voltage generation circuit 19B is not limited to the one that generates the solenoid drive voltage according to the operation amount detection signal from the operation knob 30. When the output signal from the AND circuit 19A is on, A constant solenoid drive voltage may be generated using VSL supplied from the substrate 10. And, for example, according to the operation amount of the operation knob 30, the shooting speed of the game ball can be changed by mechanical control such as adjusting the launch position of the game ball or adjusting the movement amount of the hitting ball. You may do it. Further, the VL signal output from the card unit 70 may be directly input from the interface board 20 to the launching device 19 or may be input to the launching device 19 via a control board such as the payout control board 15. .

  As shown in FIG. 5, the main board 11 receives detection signals from the gate switch 21, start port switch 22, V winning switch 23, count switch 24, winning port switches 25 </ b> A to 25 </ b> D, and all winning ball detection switches 29. Wiring to connect is connected. Note that the gate switch 21, the start port switch 22, the V winning switch 23, the count switch 24, the winning port switches 25A to 25D, and the all winning ball detection switch 29 are used as game media such as a sensor. What is necessary is just to have the arbitrary structures which can detect this game ball. Here, each of the start port switch 22, the count switch 24, and the winning port switches 25A to 25D is provided corresponding to each of a plurality of winning regions provided in the gaming region, and the game ball to each winning region is provided. A winning opening switch that detects a winning and outputs a winning detection signal. Further, even if a game ball that has passed through the passing gate 41 such as the gate switch 21 is detected, if the payout of the winning ball is performed, the winning of the gaming ball to the winning area is detected and won. It will be included in the winning opening switch that outputs the detection signal. Further, the start port switch 22 detects that the game ball has won the start winning port, and outputs a start winning signal indicating that a start condition for executing the special game by the special symbol display device 4 is satisfied. It becomes a start winning detection switch.

  In addition, on the main board 11, wiring for transmitting a command signal for performing tilt control of the movable blade piece in the normal variable winning ball apparatus 6 to the solenoid 81, and opening / closing of the opening / closing plate in the special variable winning ball apparatus 7 A wiring for transmitting a command signal for performing control to the solenoid 82 is connected. Further, wiring for transmitting a command signal for performing display control of the special symbol display device 4 and the normal symbol display 40 and wiring for receiving a detection signal from the error release switch 31 are provided on the main board 11. Is connected. Here, the error release switch 31 is a switch for releasing the error state by software reset when the game control microcomputer 100 is controlled to a predetermined error state. In addition, a touch sensor detection signal from a touch sensor 75 that detects whether or not the player is touching the operation knob 30 is input to the main board 11. The touch sensor 75 outputs to the main board 11 a touch sensor detection signal that is turned on when the player's contact with the operation knob 30 is detected by the touch ring.

  A control signal output from the main board 11 toward the effect control board 12 is relayed by the relay board 18. Here, the main board 11 is provided with a main board side connector corresponding to the relay board 18, for example, and an output buffer circuit is connected between the main board side connector and the game control microcomputer 100. May be. This output buffer circuit can pass a control signal only in the direction from the main board 11 to the effect control board 12 via the relay board 18, for example, and prevents the signal input from the relay board 18 to the main board 11. . Therefore, there is no room for signals to be transmitted from the production control board 12 or the relay board 18 side to the main board 11 side.

  The relay board 18 only needs to be provided with a transmission direction regulating circuit for each wiring for transmitting a control signal output from the main board 11 to the effect control board 12, for example. Each transmission direction regulating circuit has an anode connected to a main board connector provided corresponding to the main board 11 and a cathode connected to an effect control board connector provided corresponding to the effect control board 12. The diode is composed of a resistor having one end connected to the cathode of the diode and the other end connected to the ground (GND). With this configuration, each transmission direction regulating circuit can prevent the signal input from the effect control board 12 to the relay board 18 and allow the signal to pass only in the direction from the main board 11 to the effect control board 12. Therefore, there is no room for signals to be transmitted from the production control board 12 side to the main board 11 side. In order to prevent illegal signal input to the main board, a one-way data transfer means for restricting signal input from the sub board to the main board between the main board and the sub board has already been proposed. (For example, see JP-A-8-224339). However, since there is nothing that restricts signal input to the main board between the main board and the one-way data transfer means, it is possible to input illegal signals to the main board by modifying the one-way data transfer means. Was possible. In this embodiment, a transmission direction regulating circuit is provided for each wiring for transmitting a control signal in the relay board 18, and an output buffer circuit is provided between the game control microcomputer 100 and the main board side connector on the main board 11. By providing, illegal signal input from the outside to the main board 11 can be more reliably prevented.

  The effect control board 12 is a sub-side control board independent of the main board 11, receives a control command transmitted from the main board 11 via the relay board 18, and receives the image display device 5, speakers 8L, 8R. In addition, various circuits for controlling electric parts for production such as the game effect lamp 9 are mounted. That is, the effect control board 12 has a function of controlling the display operation in the image display device 5, the sound output operation from the speakers 8 </ b> L and 8 </ b> R, the lamp lighting operation and the light-off operation in the game effect lamp 9, and the like. The effect control board 12 is connected to wiring for transmitting a control signal to the sound control board 13 and the lamp control board 14, wiring for transmitting an image data signal to the image display device 5, and the like.

  Various control commands and notification signals are transmitted between the main board 11 and the payout control board 15 by, for example, bidirectional serial communication. The payout control board 15 is a sub-side control board independent of the main board 11, receives a control command and a notification signal transmitted from the main board 11, and controls the payout operation of the game ball by the payout motor 51. Various circuits are installed. That is, the payout control board 15 has a function of controlling the award ball payout operation by the payout motor 51. Further, the payout control board 15 has a function of controlling the ball lending operation by controlling the driving of the payout motor 51 according to the communication result with the card unit 70 via the interface board 20. The payout control board 15 is connected with wiring for receiving detection signals from the payout motor position sensor 71, the payout count switch 72, and the error release switch 73. In addition, a wiring for transmitting a command signal for performing payout control of the game ball in the payout motor 51 and a command signal for performing display control in the error display LED 74 are transmitted to the payout control board 15. Are connected to the card unit 70 via the interface board 20. Further, the payout control board 15 may be connected to a wiring for branching a VL signal, which is a connection signal from the card unit 70, and transmitting the branched signal to the launching device 19.

  The error release switch 73 is a switch for releasing the error state by software reset when the payout control microcomputer 150 is controlled to a predetermined error state. The error display LED 74 is composed of, for example, a 7-segment LED, and is used to display error codes corresponding to various errors based on an error flag set by the payout control microcomputer 150.

  The control command transmitted from the main board 11 to the effect control board 12 via the relay board 18 is, for example, an effect control command transmitted as an electric signal. The effect control command includes, for example, a display control command used for controlling an image display operation in the image display device 5, a voice control command used for controlling sound output from the speakers 8L and 8R, and a game effect lamp 9. And a lamp control command used for controlling the lighting operation of the decoration LED and the like. FIG. 9 is an explanatory diagram showing an example of the contents of the display control command used in this embodiment. The display control command has, for example, a 2-byte structure, and the first byte indicates MODE (command classification), and the second byte indicates EXT (command type). The first bit (seventh bit [bit 7]) of the MODE data is always “1”, and the first bit of the EXT data is “0”. The form of the display control command shown in FIG. 9 is an example, and other command forms may be used. In this example, the display control command has a 2-byte configuration, but the number of bytes constituting the display control command may be 1 or a plurality of 3 or more. In this embodiment, as a display control command, a variable display start command, a display result notification command, a jackpot start command, a jackpot end command, a demo display command, a prize ball excessive notification command, a prize ball shortage notification command, a full tank notification start command A full tank notification end command and the like are prepared in advance.

  In the example shown in FIG. 9, the command 80XXh is a variable display start command that is transmitted when the special symbol display device 4 starts the variable symbol special symbol display in the special symbol game. XXh indicates an unspecified hexadecimal number, and may be a value that is arbitrarily set according to the instruction content by the display control command. The variable display start command is, for example, a special symbol variable display time (total variation time), which is a time from when the special symbol display device 4 starts the variable symbol variable display to when the fixed special symbol is stopped and displayed, or a decorative symbol. EXT data indicating whether or not the variable display mode is a reach loss that is lost after reaching, or a normal loss that is lost without reaching, is included.

  Here, the reach means that a decorative display (referred to as a reach variation pattern) that has not yet been derived and displayed when the decorative pattern derived and displayed on the image display device 5 forms a part of the jackpot combination is a variable display. It is a display mode that is being performed, or a display mode in which all or some of the decorative symbols are synchronously displayed while constituting all or part of the jackpot symbol. Specifically, on the combination effective line that has not been stopped yet when the symbols constituting the predetermined jackpot combination are stopped and displayed on some of the variable display portions on the predetermined combination effective line. Display mode in which variable display is performed in the variable display section (for example, "left", "right" variable display sections among "left", "middle", "right" variable display sections provided in the display area Is a display mode in which part of the big hit symbol (for example, “7”) is stopped and displayed, and the “middle” variable display section is still displaying a variable display) or variable on the effective line A display mode (for example, “left”, “middle”, “ The state of change is displayed on all the `` Right '' variable display sections. Is but display mode in variable display is being performed aspects be displayed have all the same decorative pattern). Also, during the reach, unusual effects may be performed with lamps or sounds. This production is called reach production. Further, during the reach, the image display device 5 displays a character (an effect display imitating a person or the like, which is different from the decorative design), changes the display mode of the background, or changes the decorative design. The display mode may be changed. This change in character display, background display mode, and decorative pattern variation mode is referred to as reach effect display.

  The command 90XXh is a display result notification command indicating a confirmed special symbol in the special symbol game on the special symbol display device 4 and whether or not the game state is a probable big hit that becomes a high probability state. As a specific example, the command 9000h is a command indicating that the confirmed special symbol in the special game is a lost symbol. The command 9001h is a command indicating that the confirmed special symbol in the special symbol game is a special symbol indicating “7” as a jackpot symbol, and that the gaming state is a normal jackpot that does not become a high probability state. . Further, the command 9002h is a command indicating that the confirmed special symbol in the special symbol game is a special symbol indicating “7” as a jackpot symbol, and that the game state is a probabilistic big hit in which the gaming state becomes a high probability state. Based on such a display result notification command, on the side of the effect control board 12, the type of display result of the decorative symbol that is stopped and displayed after the variable display of the decorative symbol is performed is lost or normal or big hit, It becomes possible to decide what to do.

  The command A000h is a big hit start command indicating that the big hit gaming state is started when a big hit is made in the special symbol game by the special symbol display device 4 or the variable display of the decorative symbols on the image display device 5. The command A100h is a jackpot end command indicating that the jackpot gaming state is ended. The command B000h is a demonstration display command indicating that demonstration display (demo display) by image display or the like in the image display device 5 is possible.

  The command D000h is a prize ball excessive notification command for notifying that an excessive prize ball, which is an excessive payout of prize balls, has occurred. The command D001h is a prize ball shortage notification command for notifying that a shortage of prize balls, which is an excessive payout of prize balls, has occurred. The command D004h is a full tank notification start command for notifying that the predetermined amount or more of the game balls are stored in the lower plate 33. The command D005h is a full tank notification end command for ending the notification started based on the full tank notification start command.

  The control command transmitted from the main board 11 to the payout control board 15 is, for example, a payout control command transmitted as an electrical signal. The payout control command is set to transmit the payout control command by the CPU 104 (FIG. 11) provided in the game control microcomputer 100 mounted on the main board 11, and the game control micro computer is based on the setting. It is transmitted to the payout control board 15 by the serial communication circuit 108 (FIG. 11) provided in the computer 100. In the following description, the transmission operation of the payout control command from the main board 11 to the payout control board 15 includes a series of operations by the CPU 104 and the serial communication circuit 108 provided in the game control microcomputer 100. To do. Also, for example, a payout notification command as an electrical signal is transmitted from the payout control board 15 to the main board 11. The payout notification command is set so that the payout notification command is transmitted by the CPU included in the payout control microcomputer mounted on the payout control board 15, and the payout control microcomputer 150 is provided based on the setting. It is transmitted to the main board 11 by the serial communication circuit. In the following description, it is assumed that the transmission operation of the payout notification command from the payout control board 15 to the main board 11 includes a series of operations by the CPU and serial communication circuit provided in the payout control microcomputer 150. . In addition, in the following description, not only a command for a predetermined operation from one of the main board 11 and the payout control board 15 to the other, but also a notification signal for notifying the other of the operation state of the other is a payout control command or a payout It shall be included in the notification command.

  FIG. 10 is an explanatory diagram showing a configuration example of commands transmitted / received between the main board 11 and the payout control board 15. As shown in FIG. 10A, the payout control command transmitted from the main board 11 to the payout control board 15 and the payout notification command sent from the payout control board 15 to the main board 11 are both It is configured to be 2 bytes, and is configured to be the second byte by inverting the first byte. Then, the first bit (7th bit [bit 7]) of each byte is used as a header, and the header is made different so that the first byte and the second byte can be distinguished. For example, the header in the first byte is set to a fixed value of “0”, while the header in the second byte is set to a fixed value of “1”.

  The payout control command transmitted from the main board 11 to the payout control board 15 includes a payout number designation command and an ACK feedback command. The payout number designation command is a command indicating the number of prize balls to be paid out, and is composed of, for example, a bit value as shown in FIG. Here, the 3rd to 0th bits [bits 3-0] of the first byte and the second byte in the payout number designation command may be values set according to the number of prize balls to be paid out. FIG. 10C shows a payout number designation command used in this embodiment in hexadecimal notation. A command E11Eh shown in FIG. 10C is a first payout number designation command indicating that the number of prize balls to be paid out is fifteen. The command E916h is a second payout number designation command indicating that the number of prize balls to be paid out is seven. The command EC13h is a third payout number designation command indicating that the number of prize balls to be paid out is four. In this embodiment, four game balls are paid out when a game ball is detected by the start port switch 22, and seven game balls are paid out when a game ball is detected by any of the game port switches 25A to 25D. When a game ball is detected by the count switch 24, 15 prize balls are paid out.

  A command F00Fh shown in FIG. 10C is an ACK feedback command serving as a reception confirmation acceptance signal indicating that the prize ball ACK command transmitted from the payout control board 15 to the main board 11 is received on the main board 11 side. It is.

  FIG. 10D is an explanatory diagram showing a configuration example of a payout notification command transmitted from the payout control board 15 to the main board 11. The payout notification command includes a prize ball ACK command. The award ball ACK command is a command A0F5h serving as a reception confirmation signal indicating that the payout number specifying command transmitted from the main board 11 to the payout control board 15 is received on the payout control board 15 side.

  As shown in FIG. 5, a game control microcomputer 100, a switch circuit 111, and a solenoid circuit 112 are mounted on the main board 11. The switch circuit 111 includes a gate switch 21, a start port switch 22, a V winning switch 23, a count switch 24, winning port switches 25 </ b> A to 25 </ b> D, a full tank switch 26, a ball out switch 27, an all winning ball detection switch 29, and error release. Detection signals from various switches such as the switch 31 and detection signals from various sensors such as the touch sensor 75 are input. The switch circuit 111 takes these detection signals and transmits them to the game control microcomputer 100. The solenoid circuit 112 outputs drive signals for the solenoids 81 and 82 in accordance with a command from the game control microcomputer 100.

  FIG. 11 is a diagram illustrating a configuration example of the game control microcomputer 100 mounted on the main board 11. A game control microcomputer 100 shown in FIG. 11 is, for example, a one-chip microcomputer, and includes a clock circuit 101, a reset / interrupt controller 102, a random number circuit 103, a CPU (Central Processing Unit) 104, and a ROM (Read Only). Memory (RAM) 105, RAM (Random Access Memory) 106, timer circuit (PIT) 107, serial communication circuit (SCI) 108, and external bus interface 109.

  The clock circuit 101 is a circuit that generates a clock signal to be supplied to each circuit in the game control microcomputer 100 such as a CPU 104. As a specific example, the clock circuit 101 divides an external clock input to a predetermined clock input terminal by 4 to generate an internal system clock CLK. This is supplied to each circuit in the computer 100.

  The reset / interrupt controller 102 is for controlling various reset and interrupt requests generated in the game control microcomputer 100. The reset controlled by the reset / interrupt controller 102 includes a system reset and a user reset. The system reset is a reset that occurs when a low level signal is input to a predetermined SRST terminal for a certain period. A user reset has occurred when a low-level signal is input to a predetermined URST terminal for a certain period of time, a watchdog timer (WDT) time-out signal is generated, or an out-of-designated area prohibition (IAT) signal is generated. Or a reset caused by a predetermined factor such as the occurrence of an interval reset signal.

  The interrupts controlled by the reset / interrupt controller 102 include four types of interrupts such as an X class interrupt (XIRQ), an I class interrupt (IRQ), a software interrupt (SWI), and an illegal opcode trap (ILGOP). . The X class interrupt is an interrupt that occurs when a low level signal is input to a predetermined XIRQ terminal for a certain period. The I class interrupt is an interrupt that can allow / prohibit acceptance of an interrupt request by a user program, and a low level signal is input to a predetermined IRQ terminal for a certain period of time, or an interrupt request signal from the timer circuit 107 is received. This is an interrupt generated by various predetermined interrupt factors such as the occurrence of an interrupt request signal from the serial communication circuit 108.

  The random number circuit 103 is a circuit that generates a plurality of types of random numbers having different update ranges, such as a 12-bit random number and a 16-bit random number. FIG. 12 is a block diagram illustrating a configuration example of the random number circuit 103. As shown in FIG. 12, the random number circuit 103 includes a clock signal output circuit 171 having all or part of the function as the clock signal output means, and an initial value setting having all or part of the function as the initial value setting means. Circuits 172A and 172B, random number generation circuits 173A and 173B having a function as numerical value updating means, selectors 174A and 174B having a function as permutation change method selection means, and ARSC 175A and BRSC175B having a function as a numerical permutation change register Random number sequence changing circuits 176A and 176B having functions as numerical permutation changing means, maximum value comparison circuits 177A and 177B, inverting circuits 178 having functions as clock signal inverting means, and functions as timer means. Timer circuit 179 and latch signal output means A latch signal generation circuit 180 with a capability, random number register 181A with the function of the random number storage means, and a 181B. Note that the initial value setting circuit 172A, the random number generation circuit 173A, the selector 174A, the ARSC 175A, the random number sequence change circuit 176A, the maximum value comparison circuit 177A, and the random value register 181A are the first random numbers used to generate a 12-bit random number. Configure the circuit. Also, a clock signal output circuit 171, an initial value setting circuit 172B, a random number generation circuit 173B, a selector 174B, BRSC 175B, a random number sequence change circuit 176B, a maximum value comparison circuit 177B, an inversion circuit 178, a timer circuit 179, a latch signal generation circuit 180, The random value register 181B constitutes a second random number circuit used for generating a 16-bit random number.

  The clock signal output circuit 171 receives the internal system clock CLK supplied from the clock circuit 101 and outputs a clock signal having the same cycle as the internal system clock CLK or a clock signal obtained by dividing the internal system clock CLK by 16. Then, the random number generation circuit 173B and the inverting circuit 178 are input. The initial value setting circuits 172A and 172B are for setting the start value of the generated random number sequence. For example, the initial value setting circuits 172A and 172B are configured to set initial values for the first round when the random number circuit 103 starts generating random values after power supply to the pachinko gaming machine 1 is started, When the numerical data is updated cyclically from a predetermined initial value to a predetermined final value by 173A and 173B, a new initial value is set. The initial value setting circuit 172A outputs an initial value setting signal SK1 indicating the set initial value, and inputs it to the random number generation circuit 173A. The initial value setting circuit 172B outputs an initial value setting signal SK2 indicating the set initial value and inputs it to the random number generation circuit 173B.

  The random number generation circuits 173A and 173B are composed of a counter having a predetermined number of bits, for example, and based on an input such as a clock signal output from the clock signal output circuit 171, a predetermined initial value within a predetermined range in which numerical data can be updated Is a circuit that cyclically updates from a predetermined value to a predetermined final value. For example, the random number generation circuit 173A counts up one by one from the initial value set in the range from “1” to “4095” in response to the rising edge in the input signal to the predetermined clock input terminal. Go. Then, after counting up to “4095”, the numerical data is updated cyclically by counting up from “1” to a numerical value that is one final value smaller than the initial value. In this embodiment, a signal (for example, a storage signal) obtained by synthesizing the stored value update signal KT from the random value register 181A and the reset signal MS1 from the maximum value comparison circuit 177A at the clock input terminal of the random number generation circuit 173A. A sum signal as an output signal from an OR circuit having the value update signal KT and the reset signal MS1 as input signals is input. In addition, for example, the random number generation circuit 173B responds to a rising edge in an input signal to a predetermined clock input terminal, one by one from an initial value set within a range from “1” to “65535” to “65535”. Count up numerical data. Then, after counting up to “65535”, the numerical data is updated cyclically by counting up from “1” to a numerical value that is one final value smaller than the initial value. In this embodiment, a signal (for example, a clock) obtained by synthesizing the clock signal output from the clock signal output circuit 171 and the reset signal MS2 from the maximum value comparison circuit 177B is provided at the clock input terminal of the random number generation circuit 173B. The sum signal as an output signal from the OR circuit using the signal and the reset signal S2 as input signals. When the random number generation circuit 173A updates the numerical data to a predetermined final value, it outputs a random number loop signal RIJ1. Further, when the random number generation circuit 173B updates the numerical data up to a predetermined final value, the random number loop signal RIJ2 is output.

  The selectors 174A and 174B are circuits for selecting a method for changing the permutation, which is the update order of the numerical data, in response to the random number loop signals RIJ1 and RIJ2 being output by the random number generation circuits 173A and 173B, respectively. In this embodiment, a plurality of methods are determined in advance as a method of changing the permutation when the numerical data is updated from a predetermined initial value to a predetermined final value. For example, in the first method, when the numeric data is updated to the final value, the selector 174A and the selector 174B output the random number circuit RIJ1 output from the random number generation circuit 173A and the random number circuit 173B output from the random number generation circuit 173B. By selecting and outputting RIJ2, the permutation is automatically changed. The permutation is changed regardless of the stored value in the ARSC 175A which is a 12-bit random number sequence change register or the BRSC 175B which is a 16-bit random number sequence change register. Is done. The second method is a method of changing the permutation when predetermined numerical permutation change data is set in the ARSC 175A or BRSC 175B when the numerical data is updated to the final value. The third method is a method in which the permutation is not changed even when the numerical data is updated to the final value, and the random number sequence changing circuits 176A and 176B are numerical values that are always random numbers in an order according to a certain rule. Data R1 and R2 are output.

  FIG. 13A is a block diagram illustrating a configuration example of the ARSC 175A, and FIG. 13B is a block diagram illustrating a configuration example of the BRSC 175B. The ARSC 175A shown in FIG. 13A is an 8-bit register that can be written by the user program and read by the random number sequence change circuit 176A via the selector 174A, and its initial value is “0” (= 00h). Is set. Note that only “1” writing to the 0th bit [bit 0] is effective for writing to the ARSC 175A by the user program. As a method for changing the permutation, when “1” is written to the 0th bit [bit 0] of the ARSC 175A when the second method described above is selected by the selector 174A, the numerical data reaches the final value. The update rule, which is a rule for determining the order in which the random number sequence change circuit 176A outputs numerical data, can be changed from the beginning of the updated next cycle. The BRSC 175B shown in FIG. 13B is an 8-bit register that can be written by the user program and read by the random number sequence changing circuit 176B via the selector 174B, and its initial value is “0” (= 00h). Is set. As for writing to the BRSC 175B by the user program, only writing “1” to the 0th bit [bit 0] is effective. As a method for changing the permutation, when “1” is written to the 0th bit [bit 0] of the BRSC 175B when the second method described above is selected by the selector 174B, the numerical data reaches the final value. The update rule, which is a rule for determining the order in which the random number sequence change circuit 176B outputs numerical data, can be changed from the beginning of the updated next cycle.

  The random number sequence changing circuits 176A and 176B are circuits that allow the numerical data generated by the random number generating circuits 173A and 173B to be changed to permutations according to a predetermined update rule. For example, the random number sequence change circuit 176A executes bit scramble processing such as bit replacement or transposition in numerical data output from the random number generation circuit 173A, while the random number sequence change circuit 176B is output from the random number generation circuit 173B. Bit scramble processing such as bit replacement and transposition in numeric data is executed. The random number sequence changing circuits 176A and 176B can change the permutation, which is the update order of numerical data, by changing the bit scramble key or the bit scramble table used for the bit scramble process, for example.

  FIG. 14 is an explanatory diagram showing a permutation changing operation when the above-described first method is selected by the selector 174A as an example of the operation in the random number sequence changing circuit 176A provided for 12-bit random numbers. When the first method is selected by the selector 174A, the random number sequence C1 output from the random number generation circuit 173A is cyclically updated from a predetermined initial value to a predetermined final value. The change circuit 176A automatically changes the permutation. In the operation example shown in FIG. 14, the numerical data sequence R1 first output from the random number sequence change circuit 176A is “1 → 2 →... → 4095”.

  Then, when the value of the numerical data sequence C1 output from the random number generation circuit 173A reaches a predetermined final value, the random number loop signal RIJ1 output from the random number generation circuit 173A is sent to the random number sequence change circuit 176A via the selector 174A. Is input. The random number sequence changing circuit 176A changes the update rule of the numerical data in response to the input of the random round signal RIJ1. At this time, the random number sequence changing circuit 176A may change the update rule by selecting the update rule according to a predetermined order from among a plurality of types of update rules prepared in advance. Alternatively, the random number sequence change circuit 176A may change the update rule by selecting an arbitrary update rule from among a plurality of types of update rules. In the operation example shown in FIG. 14, the numerical data sequence R1 output from the random number sequence change circuit 176A is “4095 → 4094 →... → 1” due to the permutation change by the first update rule change. After that, the permutation is changed by the second update rule change, so that the numerical data sequence R1 output from the random number sequence changing circuit 176A becomes “1 → 3 →... → 4095 → 2 →. . In the operation example shown in FIG. 14, the numerical data sequence R1 output from the random number sequence change circuit 176A is “4095 → 1 →... → 2047” by performing the permutation change by the third update rule change. . When the permutation is changed by the fourth update rule change, the numerical data sequence R1 output from the random number sequence changing circuit 176A becomes “1023 → 3072 →... → 3071”. When the permutation is changed by changing the update rule for the fifth time, the numerical data sequence R1 output from the random number sequence changing circuit 176A becomes “5 → 4 →... → 4091”. Further, when the initial value setting circuit 172A sets a new initial value when the random number generation circuit 173A cyclically updates the numerical data from a predetermined initial value to a predetermined final value, the random number sequence is changed. The circuit 176A changes the update rule of numerical data in response to the input of the random number round signal RIJ1, and the initial value setting circuit 172A sets a new initial value in the random number generation circuit 173A in response to the input of the random number round signal RIJ1. To do. Thereafter, the random number generation circuit 173A cyclically updates the numerical data from the initial value changed by the initial value setting circuit 172A, and the random number sequence change circuit 176A outputs the numerical data output from the random number generation circuit 173A according to the updated update rule. The arrangement of the column C1 is changed.

  The random number sequence change circuit 176B provided for the 16-bit random number also performs the same processing as the random number sequence change circuit 176A on the numeric data sequence R2 for 16-bit random number generation output from the random number generation circuit 173B. The numerical data string R2 is output in the order according to the update rule. When the first method described above is selected by the selector 174B, the numerical data string C2 output from the random number generation circuit 173B is cyclically updated from a predetermined initial value to a predetermined final value. Thus, the random number sequence changing circuit 176B automatically changes the permutation. Further, when the initial value setting circuit 172B sets a new initial value when the random number generation circuit 173B cyclically updates the numerical data from a predetermined initial value to a predetermined final value, the random number sequence is changed. The circuit 176B changes the update rule of numerical data in response to the input of the random number round signal RIJ2, and the initial value setting circuit 172B sets a new initial value in the random number generation circuit 173B in response to the input of the random number round signal RIJ2. To do. Thereafter, the random number generation circuit 173B cyclically updates the numerical data from the initial value after the change by the initial value setting circuit 172B, and the random number sequence change circuit 176B outputs the numerical data output from the random number generation circuit 173B according to the updated update rule. The arrangement of the column C2 is changed.

  FIG. 15 is an explanatory diagram showing a permutation changing operation when the second method described above is selected by the selector 174A as another example of the operation in the random number sequence changing circuit 176A provided for 12-bit random numbers. . When the second method is selected by the selector 174A, the numerical data sequence C1 output from the random number generation circuit 173A is cyclically updated from a predetermined initial value to a predetermined final value, and the 12-bit random number sequence is changed. In response to the setting of “1” (= 01h), which is the numerical permutation change data, in the ARSC 175A that is a register, the update rule of the numerical data is changed. In the operation example shown in FIG. 15, the numerical data sequence R1 first output from the random number sequence change circuit 176A is “1 → 2 →... → 4095”. Thereafter, it is assumed that the CPU 104 executes the user program stored in the ROM 105 to write and set “1” (= 01h) as numerical permutation change data to the ARSC 175A at a predetermined timing.

  When the second method is selected by the selector 174A, the numerical permutation change data set in the ARSC 175A is read out by the random number sequence change circuit 176A, and setting for changing the update rule of the numerical data is performed. . At this time, the random number sequence change circuit 176A selects, for example, one of a plurality of types of update rules in response to the value of the numerical data sequence C1 output from the random number generation circuit 173A reaching a predetermined final value. The update rule is changed by, for example. In the operation example shown in FIG. 15, after the random number sequence change circuit 176A outputs the numerical data “4095” corresponding to the final value in the numerical data sequence C1 output from the random number generation circuit 173A, the numerical permutation change data is set. Change the update rules accordingly. Thereafter, the random number sequence changing circuit 176A outputs “4095 → 4094 →... → 1” as the numerical data sequence R1 in accordance with the updated update rule. The ARSC 175A is initialized when the numerical permutation change data is read by the random number sequence change circuit 176A. Therefore, until the numerical permutation change data is set again in the ARSC 175A, the numerical data sequence R1 output from the random number sequence change circuit 176A is “4095 → 4094 →... → 1”.

  When the CPU 104 executes the user program stored in the ROM 105 and “1” (= 01h), which is the numerical permutation change data, is set again in the ARSC 175A, the update rule of the numerical data is changed again. In the operation example shown in FIG. 15, after the random number sequence change circuit 176A outputs the numerical data “1” corresponding to the final value in the numerical data sequence C1 output from the random number generation circuit 173A, the numerical permutation change data is set. Change the update rules accordingly. Thereafter, the random number sequence changing circuit 176A outputs “1 → 3 →... → 4095 → 2 →... 4094” as the numerical data sequence R1 in accordance with the updated update rule.

  In the random number sequence changing circuit 176B provided for 16-bit random numbers, when the second method described above is selected by the selector 174B, the numerical data sequence C2 output from the random number generation circuit 173B is predetermined from a predetermined initial value. In response to the fact that “1” (= 01h), which is the numerical permutation change data, is set in BRSC175B, which is a 16-bit random number sequence change register, is updated cyclically to the final value of Change the rules. In this way, the random number sequence change circuit 176B can output the numerical data sequence R2 in accordance with the updated update rule.

  The maximum value comparison circuits 177A and 177B shown in FIG. 12 compare the numerical data sequences R1 and R2 output from the random number sequence change circuits 176A and 176B with a predetermined maximum value, respectively, so that the numerical data sequences R1 and R2 This circuit outputs only numeric data within the use range. The maximum value comparison circuit 177A compares the numerical data output from the random number sequence changing circuit 176A with the 12-bit random number maximum value (KRMS) set in the user program management area of the ROM 105. When the numerical data is equal to or less than the maximum value, the numerical value data is output by the maximum value comparison circuit 177A and input to the random value register 181A. On the other hand, when the numerical data is larger than the maximum value, the maximum value comparison circuit 177A outputs the reset signal MS1. The reset signal MS1 output from the maximum value comparison circuit 177A is input to the clock input terminal of the random number generation circuit 173A, whereby the numerical data output from the random number generation circuit 173A and the random number sequence change circuit 176A are output. Numeric data is changed. If the numerical data output from the random number sequence changing circuit 176A after this change is larger than the maximum value, the output of the reset signal MS1 is repeated until it becomes equal to or less than the maximum value. By performing such an output operation of the reset signal MS2 within a period sufficiently shorter than the cycle of the stored value update signal KT output from, for example, the random value register 181A, only numerical data that is equal to or less than the maximum value is stored in the random value register. It can be output as a 12-bit random value stored in 181A.

  The maximum value comparison circuit 177B compares the numerical data output from the random number sequence change circuit 176B with the 16-bit maximum random value (KRXS) set in the user program management area of the ROM 105. When the numerical data is less than or equal to the maximum value, the numerical value data is output by the maximum value comparison circuit 177B and input to the random value register 181B. On the other hand, when the numerical data is larger than the maximum value, the maximum value comparison circuit 177B outputs the reset signal MS2. The reset signal MS2 output from the maximum value comparison circuit 177B is input to the clock input terminal of the random number generation circuit 173B, whereby the numerical data output from the random number generation circuit 173B and the random number sequence change circuit 176B are output. Numeric data is changed. If the numerical data output from the random number sequence changing circuit 176B after this change is larger than the maximum value, the output of the reset signal MS2 is repeated until it becomes equal to or less than the maximum value. By performing such an output operation of the reset signal MS2 within a period sufficiently shorter than the cycle of the clock signal S1 output from the clock signal output circuit 171, only numerical data that is equal to or less than the maximum value is stored in the random value register 181B. It can be output as a stored 16-bit random value.

  FIG. 16 is an explanatory diagram showing a numerical data resetting operation by the maximum value comparison circuit 177A provided for 12-bit random numbers. In the operation example shown in FIG. 16, as shown in FIG. 16A, the 12-bit random number maximum value (KRMS) is set to “512”, and the numerical data sequence R1 output from the random number sequence change circuit 176A is “ 1 → 2 → ... → 4096 ”.

  In this case, the maximum value comparison circuit 177A outputs the numerical data and inputs it to the random value register 181A during the period in which the numerical data output from the random number sequence change circuit 176A is “1” to “512”. On the other hand, when the numerical data output from the random number sequence change circuit 176A becomes larger than “512”, the maximum value comparison circuit 177A outputs the reset signal MS1 to be input to the random number generation circuit 173A. By repeating the output operation of the reset signal MS1, the maximum value comparison circuit 177A continuously changes the numerical data output from the random number sequence change circuit 176A from “513” to “4095”, and thereafter “1”. To return. At this time, the numerical data output from the maximum value comparison circuit 177A remains “512”. When the output operation of the reset signal MS1 is performed within a period sufficiently shorter than the normal update period of the random number value and the numerical data “1” is output from the random number sequence changing circuit 176A, the maximum value comparison circuit 177A outputs this numerical data as it is and inputs it to the random value register 181A. By such numerical value resetting operation by the maximum value comparison circuit 177A, only numerical data equal to or less than the maximum value set as the 12-bit random number maximum value (KRMS) can be input to the random value register 181A.

  The inversion circuit 178 shown in FIG. 12 inverts the clock signal S1 input from the clock signal output circuit 171 to generate an inversion clock signal S2. The inverting circuit 178 outputs the generated inverted clock signal S2 and inputs it to the latch signal generating circuit 180. The timer circuit 179 measures the time during which the start winning signal SS is input from the start port switch 22, and outputs the start winning signal SS when the measured time reaches a predetermined time (for example, 3 milliseconds). , Input to the latch signal generation circuit 180. For example, the timer circuit 179 is configured by an up counter or a down counter, and starts in response to the start winning signal SS being turned on. In this case, the timer circuit 179 counts up or down the internal system clock CLK during the period in which the start winning signal SS is in the ON state. Then, when the count value obtained by counting up or down reaches a value corresponding to 3 milliseconds, the timer circuit 179 determines that the input signal is the start winning signal SS, and sets the start winning signal SS as the start winning signal SS. The data is output and input to the latch signal generation circuit 180.

  The latch signal generation circuit 180 is configured using, for example, a flip-flop. For example, when the latch signal generation circuit 180 is configured using a D flip-flop, the D input terminal is connected to the output terminal of the timer circuit 179 and the clock input terminal is connected to the output terminal of the inverting circuit 178. That's fine. The latch signal generation circuit 180 generates the latch signal SL by outputting the start winning signal SS output from the timer circuit 179 in synchronization with the rising edge of the inverted clock signal S2 output from the inversion circuit 178.

  The random value registers 181A and 181B store numerical data output from the maximum value comparison circuits 177A and 177B, respectively, as random values. FIG. 17A is a block diagram illustrating a configuration example of a random value register 181A serving as a 12-bit random value register (ARND), and FIG. 17B illustrates a random value serving as a 16-bit random value register (BRND). It is a block diagram which shows the structural example of the register | resistor 181B. The random value registers 181A and 181B are both 16-bit registers. However, for the random value register 181A serving as a 12-bit random value register (ARND), the seventh to fourth of the higher-order 8-bit register ARND (H) are used. The stored value in bits [bit 7-4] is invalid, and is used as a register for storing a 12-bit random number.

  In this embodiment, the random value register 181A provided for the 12-bit random number is input from the maximum value comparison circuit 177A in response to the register read signal supplied from the CPU 104 being turned on, for example. Numeric data that is stored as a random value. When the random value register 181A stores a random value, for example, the stored value update signal KT is turned on for a predetermined period and then turned off. Thus, the random number generation circuit 173A only needs to be able to update the numerical data in response to the rising edge of the stored value update signal KT output from the random value register 181A. On the other hand, the random value register 181B provided for the 16-bit random number is a numerical value input from the maximum value comparison circuit 177B in response to the latch signal SL output from the latch signal generation circuit 180 being turned on. Capture and store data as random values.

  The random number circuit 103 is provided with a 12-bit random number maximum value read register (ARMX) as shown in FIG. 17C and a 16-bit random number maximum value read register (BRMX) as shown in FIG. It may be done. The 12-bit random number maximum value reading register (ARMX) shown in FIG. 17C is a register that enables confirmation of the 12-bit random number maximum value (KRMS) set in the user program management area of the ROM 105, and is a 16-bit register. Among them, the stored value in the seventh to fourth bits [bit 7-4] of the register ARMX (H) for the upper 8 bits is invalidated, and used as a register for storing a 12-bit numerical value. A 16-bit random number maximum value reading register (BRMX) shown in FIG. 17D is a 16-bit register that enables confirmation of the 16-bit random number maximum value (KRXS) set in the user program management area of the ROM 105.

  The CPU 104 shown in FIG. 11 reads the user program and data stored in the ROM 105, and uses the RAM 106 as a work area to perform a control operation according to the program. FIG. 18 is a diagram showing an example of an address map in the game control microcomputer 100. As shown in FIG. 18, the area from address 0000h to address 01FFh is a work area assigned to the RAM 106. An area of addresses 1000h to 101Ch is a built-in register area allocated to built-in registers such as the random number circuit 103, the timer circuit 107, and the serial communication circuit 108. The area from address 2000h to address 200Fh is a chip select signal decode area assigned to an address decoder built in the game control microcomputer 100. The area from address E000h to FFFFh is allocated to the ROM 105, and includes a user program management area and a user program / data area.

  A user program and user data created in advance by the user are stored in the user program / data area that is an area from addresses E080h to FFFFh in the ROM 105. The user program management data that is used when the CPU 104 executes the user program and sets the operation content of the pachinko gaming machine 1 is stored in the user program management area that is an area from addresses E000h to E07Fh in the ROM 105. .

  FIG. 19 is a diagram showing an example of an address map in the user program management area shown in FIG. As shown in FIG. 19, in the area of E01Bh, among the plurality of types of I class interrupt (IRQ) factors generated by the game control microcomputer 100, the highest priority is set. Data indicating the priority interrupt setting (KHPR) is stored. FIG. 20A is an explanatory diagram showing a setting example of the highest priority interrupt setting data stored in the area of address E01Bh. FIG. 20B shows, as an example of specific setting of the highest priority interrupt setting data, the priority order of interrupt factors in default and the priority order of interrupt factors when “05h” is set in the area of E01Bh. It shows.

  As shown in FIG. 20B, in the default state in which the highest priority interrupt setting data is not set in the area of E01Bh, the interrupt factor due to the signal input to the predetermined IRQ terminal has the highest priority, and then the timer circuit The priority of interrupt requests from the 107 channels (CH0 to CH3) is high, and the priority is set to be low in the order of error interrupt request, reception interrupt request, and transmission interrupt request from the serial communication circuit 108. . That is, even in the default state, among the interrupt requests from the serial communication circuit 108, the error interrupt request has a higher priority than other interrupt factors such as a reception interrupt request and a transmission interrupt request. Therefore, interrupt processing based on an error interrupt request from the serial communication circuit 108 is executed with priority over interrupt processing based on a reception interrupt request or transmission interrupt request that is different from the error interrupt request from the serial communication circuit 108. Will be.

  When “05h” is set as the highest priority interrupt setting data in the area of address E01Bh, the priority of the error interrupt request from the serial communication circuit 108 is determined by the interrupt factor due to the signal input to the IRQ terminal, the timer circuit It becomes higher than the priority of the interrupt request from 107, and has the highest priority among the factors of a plurality of types of I class interrupts (IRQ) generated in the game control microcomputer 100. In this way, by setting the highest priority interrupt setting data in the area of address E01Bh, the priority order of the factors of a plurality of types of I class interrupts (IRQ) can be changed from the default setting.

  In the area of E01Ch address and the area of E01Dh shown in FIG. Data indicating KRSS2) is stored. FIG. 21A is an explanatory diagram illustrating the contents of data indicating the first random number initial setting (KRSS1) stored in the area of E01Ch address. FIG. 21B is an explanatory diagram illustrating the contents of data indicating the second random number initial setting (KRSS2) stored in the area of E01Dh address.

  As shown in FIGS. 21A and 21B, each of the first and second random number initial setting data is composed of 8-bit data, but the seventh to fifth of the first random number initial setting data. Bits [bits 7-5] are unused. The fourth and third bits [bit 4-3] of the first random number initial setting data shown in FIG. 21A are random numbers to be used among the 12-bit random number and the 16-bit random number generated by the random number circuit 103. Show. In the example shown in FIG. 21A, when the fourth and third bits [bit 4-3] of the first random number initial setting data are “00”, neither the 12-bit random number nor the 16-bit random number is used. "01" indicates that only a 12-bit random number is used, "10" indicates that only a 16-bit random number is used, and "11" indicates that a 12-bit random number and a 16-bit random number are used. It shows that both are used. The second bit [bit 2] of the first random number initial setting data indicates the setting for the update cycle of the 16-bit random number generated by the random number circuit 103. In the example shown in FIG. 21A, when the second bit [bit 2] of the first random number initial setting data is “0”, the 16-bit random number is updated at the cycle of the internal system clock CLK. "" Indicates that a 16-bit random number is updated at a cycle 16 times the internal system clock CLK.

  The first and 0th bits [bits 1-0] of the first random number initial setting data indicate settings for the start values after the second round in the 12-bit random number. In the example shown in FIG. 21A, when the first and 0th bits [1-0] of the first random number initial setting data are “00”, the start value is not changed. In some cases, the value is changed to a value based on an ID number which is unique identification information assigned to each game control microcomputer 100. In the case of "10", the value is changed to an addition value of stored data in the RAM 106 as a user RAM. "11" indicates that the value is changed to the value stored in the designated address in the RAM 106 which is the user RAM.

  The seventh bit [bit 7] of the second random number initial setting data shown in FIG. 21B indicates the setting for the start value of the first round in the 12-bit random number. In the example shown in FIG. 21B, when the seventh bit [bit 7] of the second random number initial setting data is “0”, the start value of the first round in the 12-bit random number is “001h” (the default value). When the value is “1”, the value is based on an ID number that is unique identification information assigned to each game control microcomputer 100.

  The sixth and fifth bits [bits 6-5] of the second random number initial setting data indicate settings for a method for changing a random number sequence in a 12-bit random number. In the example shown in FIG. 21B, when the sixth and fifth bits [bits 6-5] of the second random number initial setting data are “00”, the permutation is not changed (the third method is used). When it is “10”, it indicates that the user program can be changed after the second lap (the second method), and when it is “11”, it is automatically changed after the second lap. (The first method).

  The fourth bit [bit 4] of the second random number initial setting data indicates the setting for the start value of the first round in the 16-bit random number. In the example shown in FIG. 21B, when the fourth bit [bit 4] of the second random number initial setting data is “0”, the start value of the first round in the 16-bit random number is the default value “0001h” ( When the value is “1”, the value is based on an ID number that is unique identification information assigned to each game control microcomputer 100.

  The third and second bits [bit 3-2] of the second random number initial setting data indicate the setting for the start value after the second round in the 16-bit random number. In the example shown in FIG. 21B, when the third and second bits [bit 3-2] of the second random number initial setting data are “00”, it indicates that the start value is not changed, and “01” Indicates that the value is changed to a value based on an ID number that is unique identification information assigned to each game control microcomputer 100, and if “10”, the value is added to the added value of the stored data in the RAM 106 as the user RAM. In the case of “11”, it indicates that the value is changed to the value stored in the designated address in the RAM 106 which is the user RAM.

  The first and 0th bits [bits 1-0] of the second random number initial setting data indicate settings for a method for changing a random number sequence in a 16-bit random number. In the example shown in FIG. 21B, when the first and 0th bits [bits 1-0] of the second random number initial setting data are “00”, the permutation is not changed (the third method). When it is “10”, it indicates that the user program can be changed after the second lap (the second method), and when it is “11”, it is automatically changed after the second lap. (The first method).

  In the area of E01Eh address and the area of E01Fh shown in FIG. 19, data indicating a 12-bit random number maximum value (KRMS) used to set the maximum value of the 12-bit random number generated by the random number circuit 103 is stored. Remembered. In the example shown in FIG. 19, the upper byte (8 bits) of the data indicating the 12-bit random number maximum value (KRMS) is stored in the area of E01Eh address, and the 12-bit random number maximum value (KRMS) is stored in the area of E01Fh address. The lower byte (8 bits) of the indicated data is stored.

  Data indicating the maximum 16-bit random number (KRXS) used to set the maximum value of the 16-bit random number generated by the random number circuit 103 is stored in the area of the address E020h and the area of the address E021h. In the example shown in FIG. 19, the upper byte (8 bits) of the data indicating the maximum 16-bit random number (KRXS) is stored in the area of address E020h, and the maximum 16-bit random number (KRXS) is stored in the area of address E021h. The lower byte (8 bits) of the indicated data is stored.

  In addition to the game control user program, the ROM 105 provided in the game control microcomputer 100 shown in FIG. 11 stores various data tables used for controlling the progress of the game. For example, the ROM 105 stores table data constituting a plurality of determination tables and determination tables prepared for the CPU 104 to perform various determinations and determinations. The determination table includes a big hit determination table that is referred to for determining whether or not the variable display result is a big hit by using the confirmed special symbol in the special symbol game by the special symbol display device 4 as a big hit symbol, or a big hit. Probability change determination table that is referred to determine whether to make a promiscuous big hit or a normal big hit, reach determination that is referred to in order to determine whether or not the variable display mode of decorative symbols is to be reached when lost Includes tables and the like. For example, the jackpot determination table is composed of determination data for associating a determination result as to whether or not the variable display result is a jackpot with a random value read from the random number circuit 103 (for example, a 16-bit random number value). It only has to be done.

  In addition, the determination table stored in the ROM 105 includes a confirmed special symbol determination table for determining a confirmed special symbol to be derived and displayed as a variable display result in the special symbol game, a special symbol game or an image by the special symbol display device 4. A variable display pattern determination table for determining a variable display pattern such as a symbol during variable display of decorative symbols on the display device 5, an effect display execution determination table for determining whether or not to perform various effect displays, etc. It is included. In addition, the ROM 105 included in the game control microcomputer 100 stores predetermined fixed information such as an ID number that is unique identification information assigned to each game control microcomputer 100.

  In the RAM 106 provided in the game control microcomputer 100, for example, a game control data holding area 130 as shown in FIG. 22 is provided as an area for holding various data used for controlling the game state and the like in the pachinko gaming machine 1. Is provided. Further, at least a part of the RAM 106 is a backup RAM that is backed up by a backup power source created in the power supply substrate 10. That is, even if the power supply to the pachinko gaming machine 1 is stopped, at least a part of the contents of the RAM 106 is stored for a predetermined period. In this embodiment, it is assumed that the entire RAM 106 is a backup RAM that is backed up. The game control data holding area 130 shown in FIG. 22 includes a special figure storage unit 131, a confirmed special symbol storage unit 132, a game control flag setting unit 133, a game control timer setting unit 134, and a game control counter setting unit. 135 and a game control buffer setting unit 136.

  The special figure storage unit 131 has a start condition for executing the special figure game by the special symbol display device 4 when the game ball wins the start winning opening provided in the ordinary variable winning ball device 6 and the special symbol display device 4 is executed. The hold information relating to the special figure game in which the start condition for starting the variable display is not satisfied due to the reason that the special figure game is being executed is stored. For example, the special figure hold storage unit 131 associates with the hold numbers in the order of winning to the start winning opening, and shows the random value for jackpot determination extracted from the random number circuit 103 by the CPU 104 based on the establishment of the starting condition by the winning. Numerical data is stored as pending data until the number reaches a predetermined upper limit (eg, “4”).

  The confirmed special symbol storage unit 132 stores data indicating a confirmed special symbol derived and displayed as a variable display result in the special symbol game by the special symbol display device 4. The game control flag setting unit 133 sets a plurality of types of flags that are set or cleared in accordance with the gaming state in the pachinko gaming machine 1 and signals transmitted from the winning prize switch or the like via the switch circuit 111. For storing data. The game control timer setting unit 134 stores data indicating a plurality of types of timer values used for game control in the pachinko gaming machine 1. The game control counter setting unit 135 stores data indicating a plurality of types of count values used for game control in the pachinko gaming machine 1. The game control buffer setting unit 136 temporarily stores various data used for game control in the pachinko gaming machine 1. The circuit used for flag setting and counter / timer may be constituted by a register circuit provided separately from the RAM 106.

  The game control flag setting unit 133 includes, for example, a clear flag, a main backup flag, a payout communication error detection flag, a serial communication error flag, a full notification flag, a demo display flag, a 12-bit random number start value change flag, 16 Bit random number start value change flag, 12-bit random number permutation change flag, 16-bit random number permutation change flag, special symbol process flag, jackpot flag, probable change flag, prize ball process flag, retransmission flag, prize ball ACK reception flag, payout An error notification flag, a payout error notification flag, a payout error release flag, and the like are provided.

  The clear flag indicates whether or not a clear signal from the clear switch 304 included in the power supply board 10 is in an ON state when power supply to the pachinko gaming machine 1 is started. That is, if the clear signal is in the on state at the start of power supply, the clear flag is set in the on state, while if the clear signal is in the off state, the clear flag is held in the off state. The main backup flag indicates whether or not a predetermined memory protection process has been executed by the gaming control microcomputer 100 when power supply to the pachinko gaming machine 1 is stopped. For example, when “55H” is set as the value of the main backup flag, backup is present (ON state), while when a value other than “55H” is set, backup is not present (OFF state).

  The payout communication error detection flag indicates that an error has occurred in the communication operation between the main board 11 and the payout control board 15. That is, when a predetermined error occurs during execution of processing for performing communication with the payout control board 15 in the main board 11, the payout communication error detection flag is set to the on state. The serial communication error flag indicates that an error has occurred in the communication operation in the serial communication circuit 108. For example, the serial communication error flag is set to an on state in response to an error interrupt request from the serial communication circuit 108. The full tank notification flag is used when notification that the lower plate 33 is full is started by display on the image display device 5 in response to the detection signal from the full switch 26 being in an on state. Is set to the on state. The demo display flag is set to an on state when a demo display command is transmitted from the main board 11 to the effect control board 12, while the special symbol display device 4 starts a special figure game and displays an image. It is cleared and turned off when variable display of decorative symbols in the device 5 is started. Alternatively, the demo display flag may be a predetermined predetermined value such as when a lost symbol is stopped and displayed as a confirmed special symbol in the special symbol game by the special symbol display device 4 or when the big hit gaming state is ended. It may be cleared at the timing and be in an off state.

  The 12-bit random number start value change flag indicates whether the user program changes the start value after the second round of the 12-bit random number generated by the random number circuit 103. For example, when the random number round circuit RIJ1 from the random number generation circuit 173A provided in the random number circuit 103 is output to the CPU 104, the CPU 104 responds to the fact that the random round circuit RIJ1 is turned on by the CPU 104 to 12 bits. The random value start value change flag may be set to the on state. Alternatively, when the CPU 104 detects the elapse of a predetermined time during execution of the predetermined timer interrupt process, the 12-bit random number start value change flag may be set to an on state. When the 12-bit random number start value change flag is in the ON state, the CPU 104 executes processing for changing the start value of the next cycle in the 12-bit random number generated by the random number circuit 103.

  The 16-bit random number start value change flag indicates whether or not the user program changes the start value after the second round of the 16-bit random number generated by the random number circuit 103. For example, when the random number round circuit RIJ2 from the random number generation circuit 173B provided in the random number circuit 103 is output to the CPU 104, the CPU 104 uses the random number round circuit RIJ2 for the 16-bit random number in response to the ON state. The start value change flag may be set to the on state. Alternatively, the 16-bit random number start value change flag may be set to the on state when the CPU 104 detects the elapse of a predetermined time during execution of the predetermined timer interruption process. When the 16-bit random number start value change flag is in the ON state, the CPU 104 executes a process for changing the start value of the next period in the 16-bit random number generated by the random number circuit 103.

  The 12-bit random number permutation change flag indicates whether or not the permutation in the second and subsequent rounds of the 12-bit random number generated by the random number circuit 103 is changed by the user program. For example, when the random number round circuit RIJ1 from the random number generation circuit 173A provided in the random number circuit 103 is output to the CPU 104, the CPU 104 responds to the fact that the random round circuit RIJ1 is turned on by the CPU 104 to 12 bits. The random number permutation change flag may be set to the on state. Alternatively, the 12-bit random number permutation flag may be set to the on state when the CPU 104 detects the elapse of a predetermined time during execution of the predetermined timer interrupt process. When the 12-bit random number permutation change flag is in the ON state, the CPU 104 executes processing for changing the permutation of the next cycle in the 12-bit random number generated in the random number circuit 103.

  The 16-bit random number permutation flag indicates whether or not the permutation in the second and subsequent rounds of the 16-bit random number generated by the random number circuit 103 is changed by the user program. For example, when the random number round circuit RIJ2 from the random number generation circuit 173B provided in the random number circuit 103 is output to the CPU 104, the CPU 104 responds to the fact that the random round circuit RIJ2 is turned on by the CPU 104 to 16 bits. The random number permutation change flag may be set to the on state. Alternatively, the CPU 104 may set the 16-bit random number permutation change flag to the ON state when it detects the elapse of a predetermined time during execution of the predetermined timer interrupt process. When the 16-bit random number permutation change flag is in the ON state, the CPU 104 executes processing for changing the permutation of the next cycle in the 16-bit random number generated in the random number circuit 103.

  The special symbol process flag indicates which process should be selected and executed in the special symbol process (step S80 in FIG. 31 and FIG. 43) executed corresponding to the special symbol display device 4. The big hit flag is set to the on state when it is determined that the variable display result in the special figure game is a big hit when the special symbol display device 4 starts the special figure game. After that, when the big hit gaming state based on the big win in the special figure game is finished, the big hit flag is cleared and turned off. The probable change flag is set to the on state when the variable display result in the special symbol game by the special symbol display device 4 becomes the probable big hit and the big hit gaming state based on the big hit is ended. On the other hand, the flag during probability change is cleared, for example, when the number of executions of the special figure game in the high probability state reaches a predetermined probability change end reference value or when the variable display result in the special figure game is a normal big hit. Turns off.

  The prize ball process flag indicates which process should be selected and executed in the prize ball process (step S77 in FIG. 31 and FIG. 37A) for setting the number of prize balls. After the re-transmission flag is set to transmit a payout control command to the payout control board 15, a predetermined prize ball ACK waiting time elapses without receiving a prize ball ACK command from the payout control board 15 Is set to the on state. On the other hand, the retransmission flag is cleared and turned off, for example, when a prize ball ACK command is received before the prize ball ACK waiting time elapses. The prize ball ACK reception flag indicates whether or not a prize ball ACK command from the payout control board 15 has been received. That is, the prize ball ACK reception flag is set to the on state when the prize ball ACK command is received.

  The payout error notification flag indicates whether a payout error notification command from the payout control board 15 has been received. That is, the payout error notification flag is set to the on state when the payout error notification command is received. The payout error notification flag is set to the on state when notification that an abnormality has occurred due to the display on the image display device 5 is started in response to the payout error notification flag being turned on. The payout error cancel flag indicates whether or not a payout error cancel command from the payout control board 15 has been received. That is, the payout error release flag is set to the on state when the payout error release command is received.

  The game control timer setting unit 134 is provided with, for example, a launch control timer, a launch permission control timer, a supply permission control timer, a prize ball control timer, a variable display time timer, and the like. The firing control timer is for measuring a firing control time for periodically controlling the operations of the launching device 19 and the ball feeding device 62. The firing permission control timer is for measuring a period during which the firing permission signal is transmitted to the launching device 19. The supply permission control timer is for measuring a period during which the supply permission signal in the on state is transmitted to the ball feeder 62. The prize ball control timer is used to measure various times when various processes related to the prize ball payout are executed on the main board 11. The variable display time timer is for measuring the variable display time (total variation time) of special symbols in the special game.

  The game control counter setting unit 135 includes, for example, a wait counter, a total prize ball number counter, first to third payout number instruction counters, a command transmission number counter, a command reception number counter, a command transmission waiting counter, and the like. . In addition, the game control counter setting unit 135 may be provided with a variable display number counter for counting the number of executions of the special figure game in the high probability state or the time reduction state.

  When the power supply to the pachinko gaming machine 1 is started and the game control process (process for controlling the progress of the game) can be executed by the game control microcomputer 100, the weight counter It is used to delay the timing for starting execution of the control process. For example, when the power supply to the pachinko gaming machine 1 is started and the game control microcomputer 100 is activated, an initialization wait number designation value corresponding to a predetermined delay time is set in the wait counter. Thereafter, an update process such as sequentially subtracting the weight count value which is the value of the wait counter is performed, and when the value reaches a predetermined delay end determination value, the execution of the game control process is started.

  The total award ball counter has not yet completed a payout instruction from the main board 11 to the payout control board 15 among the winning balls to be paid out based on the detection of the game ball by each winning opening switch. This is for counting the total number of prize balls. For example, when the game control microcomputer 100 determines that the winning detection signal from the count switch 24 is in the ON state, 15 is added to the total prize ball count value which is the value of the total prize ball counter. When it is determined that the winning detection signal from any of the winning opening switches 25A to 25D is in the on state, the total winning ball count value is incremented by 7, and the winning detection signal from the start opening switch 22 is in the on state. 4 is added to the total prize ball count value. On the other hand, for example, when a prize ball ACK command transmitted from the payout control board 15 is received by the game control microcomputer 100 after the first payout number specifying command is transmitted from the main board 11 to the payout control board 15, The prize ball count value is decremented by 15. For example, when the prize ball ACK command is received after the second payout number designation command is transmitted from the main board 11 to the payout control board 15, the total prize ball number count value is subtracted by 7, for example, the third payout number. When the prize ball ACK command is received after the designation command is transmitted, 4 is subtracted from the total prize ball count value. The timing for subtracting the total prize ball count value is when a prize ball ACK command is received after any one of the first to third payout number designation commands is transmitted from the main board 11 to the payout control board 15. It is not limited, and may be a stage before setting for transmitting the first to third payout number designation commands. As described above, the total number of winning balls to be paid out by the total winning ball counter should be paid out in accordance with the winning detection signals from the start port switch 22, the count switch 24, and the winning port switches 25A to 25D. Data indicating the progress of the game, including the number of prize game media data that can specify the number of prize balls, is stored in the RAM 106.

  The first to third payout number instruction counters issue respective first to third payout number designation commands from the main board 11 to the payout control board 15 based on the detection of the game ball by each winning a prize opening switch. This is for counting the number of times to be transmitted. For example, when the game control microcomputer 100 determines that the winning detection signal from the count switch 24 is in the ON state, 1 is added to the first payout number instruction count value which is the value of the first payout number instruction counter. . When it is determined that the winning detection signal from any of the winning opening switches 25A to 25D is in the ON state, the second payout number instruction count value which is the value of the second payout number instruction counter is incremented by 1, and the start is started. When it is determined that the winning detection signal from the mouth switch 22 is in the ON state, the third payout number instruction count value that is the value of the third payout number instruction counter is incremented by one. On the other hand, for example, when the game control microcomputer 100 receives the prize ball ACK command after the first payout number designation command is transmitted from the main board 11 to the payout control board 15, the first payout number instruction count value is 1. Subtracted. Further, for example, when the game control microcomputer 100 receives a prize ball ACK command after the second payout number designation command is transmitted from the main board 11 to the payout control board 15, the second payout number instruction count value is 1. For example, when the game control microcomputer 100 receives a prize ball ACK command after the third payout number specifying command is transmitted from the main board 11 to the payout control board 15, for example, the third payout number instruction count value is calculated. 1 is subtracted. The timing for subtracting each of the first to third payout number instruction count values is, for example, after each of the first to third payout number designation commands is transmitted from the main board 11 to the payout control board 15. It may be a stage before receiving the prize ball ACK command.

  The command transmission number counter counts the number of times any one of the first to third payout number designation commands is transmitted to the payout control board 15, and the game detected according to the detection signal from the all winning ball detection switch 29 This is to specify the difference from the number of balls as a winning number difference. For example, a predetermined initial count value (for example, “200”) is set in the command transmission count counter when power supply to the pachinko gaming machine 1 is started. Then, when a prize ball ACK command is received after one of the first to third payout number designation commands is sent from the main board 11 to the payout control board 15, a command transmission which is the value of the command transmission number counter is transmitted. While the count value is incremented by 1, when the detection signal from the all winning ball detection switch 29 is turned on, the command transmission count count value is decremented by 1.

  The command reception number counter is used to count the number of commands received from the sub-side control board such as the payout control board 15 in an identifiable manner. The command transmission waiting counter is used to count the number of commands waiting to be transmitted to the sub control boards such as the effect control board 12 and the payout control board 15 so as to be specified.

  The game control buffer setting unit 136 is provided with, for example, a main checksum buffer, a reception command buffer, a transmission command buffer, and the like. The main checksum buffer is for storing a checksum calculated using stored data in a specific area of the RAM 106 when power supply to the pachinko gaming machine 1 is stopped.

  The reception command buffer is used for temporarily storing a command received from the sub-side control board by the main board 11. FIG. 23 is a diagram illustrating a configuration example of the payout reception command buffer 191 included in the reception command buffer. The payout reception command buffer 191 is for temporarily storing a command received from the payout control board 15. The payout receive command buffer 191 shown in FIG. 23 includes 12 receive command buffers # 1 to # 12, and the receive command buffer for storing the command received from the payout control board 15 is designated by the command reception number counter. Is done. Each reception command buffer # 1 to # 12 is composed of, for example, 1 byte (8 bits), and a plurality of reception command buffers can be used as ring buffers to store six reception commands of 2 bytes. .

  The transmission command buffer is used to temporarily store a command to be transmitted from the main board 11 to the sub control board. FIG. 24 is a diagram illustrating a configuration example of the payout transmission command buffer 192 included in the transmission command buffer. The payout transmission command buffer 192 is for temporarily storing a command to be transmitted from the main board 11 to the payout control board 15. The payout transmission command buffer 192 shown in FIG. 24 includes twelve transmission command buffers # 1 to # 12, and a command buffer for storing a command waiting for transmission from the main board 11 to the payout control board 15 is provided. , Specified by the command transmission waiting counter. Each of the transmission command buffers # 1 to # 12 is composed of, for example, 1 byte (8 bits), and can store six transmission commands of 2 bytes by using a plurality of transmission command buffers as ring buffers. . The transmission command buffer may include an effect transmission command buffer for temporarily storing a command to be transmitted from the main board 11 to the effect control board 12.

  In addition, in the game control data holding area 130, although a game ball that has passed through the passing gate 41 is detected by the gate switch 21, a start condition for executing the normal diagram game by the normal symbol display 40 is satisfied. And a normal diagram hold storage unit for storing hold information related to the normal diagram game in which the start condition for starting variable display is not satisfied due to the reason that the conventional normal diagram game is being executed, etc. Also good. As described above, the hold information related to the special figure game or the normal figure game is stored in the game control data holding area 130 provided on the main board 11 and used for the control of the special figure game or the normal figure game by the CPU 104.

  The timer circuit 107 included in the game control microcomputer 100 shown in FIG. 11 is a circuit that includes, for example, four channels (CH0 to CH3) of 8-bit programmable counters, and is capable of generating real-time interrupts and measuring time. is there. For example, the timer circuit 107 starts counting down at a predetermined cycle from a preset count value for each channel, and when there is a channel whose count value is “00”, the interrupt flag corresponding to the channel is turned on. set. At this time, if the interrupt is permitted, the timer circuit 107 generates an interrupt request to the CPU 104.

  The serial communication circuit 108 included in the game control microcomputer 100 is a circuit that handles communication data in, for example, full duplex, asynchronous, standard NRZ (Non Return to Zero) format. For example, the serial communication circuit 108 includes a reception operation unit, a transmission operation unit, a serial communication data register, a serial status register, and a serial control register.

  The reception operation unit of the serial communication circuit 108 samples and acquires the reception data transmitted by serial communication by the reception operation based on the setting in the predetermined bit of the serial control register, and stores the acquired reception data in the serial communication data register. Enable transfer. In addition, the reception operation unit sets a predetermined bit of the serial status register to “0” or “1” according to an operation state in the reception operation. Furthermore, in the reception operation unit, for example, a reception shift register that stores received data sequentially transmitted by serial communication while shifting, a reception data register that temporarily stores reception data read from the reception shift register, It suffices if an interrupt control circuit for controlling the generation of interrupt factors related to the reception operation in serial communication is provided.

  The transmission operation unit of the serial communication circuit 108 generates transmission data corresponding to the read data from the serial communication data register by transmission operation based on the setting in the predetermined bit of the serial control register, and enables transmission by serial communication. . Further, the transmission operation unit sets a predetermined bit of the serial status register to “0” or “1” according to an operation state in the transmission operation. Furthermore, in the transmission operation unit, for example, a transmission data register that temporarily stores data read from the serial communication data register, or a transmission shift register that stores and shifts transmission data sequentially transmitted by serial communication and outputs the data An interrupt control circuit or the like for controlling the generation of an interrupt factor related to a transmission operation in serial communication may be provided.

  The serial communication data register of the serial communication circuit 108 stores the reception data acquired by the reception operation unit or stores the data supplied to the transmission operation unit, so that the serial communication circuit 108 and the CPU 104 can store data. Is a circuit that makes it possible to exchange communication data of, for example, 1 byte (8 bits).

  The serial status register of the serial communication circuit 108 is a register for confirming the operation state in the serial communication circuit 108. For example, bits indicating a plurality of flags that are set or cleared according to the operation state in the serial communication circuit 108, for example. What is necessary is just to be comprised so that a value can be memorize | stored.

  The serial control register of the serial communication circuit 108 is a register for setting the communication format in the serial communication circuit 108, permission / prohibition of various error interrupt requests, and the like. It suffices if the control data used in the configuration is stored.

  An external bus interface 109 included in the game control microcomputer 100 shown in FIG. 11 is an interface circuit that performs direction control and drive control of an address bus, a data bus, and each control signal.

  As shown in FIG. 5, an effect control microcomputer 120 is mounted on the effect control board 12. The effect control board 12 may be equipped with a VDP (Video Display Processor) that generates image data in accordance with a drawing command from the effect control microcomputer 120. The effect control microcomputer 120 is a one-chip microcomputer, for example, and includes a ROM 121, a RAM 122, a CPU 123, and an I / O port 124. In addition, the production control microcomputer 120 may include a random number circuit that generates numerical data indicating random values independently of the CPU 123. A control signal transmitted from the main board 11 via the relay board 18 is input to the CPU 123 via a predetermined connector or an input port in the I / O port 124. A control signal for the audio control board 13 is output from the CPU 123 to the audio control board 13 via an output port in the I / O port 124 or a predetermined connector. A control signal for the lamp control board 14 is output from the CPU 123 to the lamp control board 14 via an output port in the I / O port 124 or a predetermined connector.

  A scaler circuit for converting the resolution in the image data may be provided between the effect control board 12 and the image display device 5. In this case, the image data generated by the VDP mounted on the effect control board 12 according to the drawing command from the effect control microcomputer 120 is supplied to the image display device 5 after the resolution is converted by the scaler circuit. . As a specific example, the scaler circuit inputs the image data with the first resolution generated by the VDP and performs the following processing on one or both of the vertical direction and the horizontal direction. The converted image data is converted to a second resolution different from the first resolution.

  For example, when converting the resolution in the vertical direction, after performing upsampling at a first sample rate along the vertical direction of the input image data, a filtering process using a filter (for example, an FIR filter) prepared in advance. Apply. Thereafter, downsampling may be performed at a second sample rate corresponding to a predetermined scaling coefficient along the vertical direction. When converting the resolution in the horizontal direction, upsampling, filtering, and downsampling similar to those in the vertical direction may be performed along the horizontal direction of the input image data. As a specific example, when image data in VGA mode (640 × 480 pixels) is generated by VDP, the image data is converted into SXGA mode (1280 × 1024 pixels) or other modes by conversion processing in the scaler circuit. Can be converted to

  As shown in FIG. 5, a payout control microcomputer 150 and a switch circuit 161 are mounted on the payout control board 15. The switch circuit 161 receives detection signals from various switches and sensors such as a payout motor position sensor 71, a payout count switch 72, and an error release switch 73. The switch circuit 161 takes in these detection signals and transmits them to the payout control microcomputer 150.

  FIG. 25 is a diagram showing a configuration example of the payout control microcomputer 150 mounted on the payout control board 15. A payout control microcomputer 150 shown in FIG. 25 is a one-chip microcomputer similar to the game control microcomputer 100, for example, and includes a clock circuit 211, a reset / interrupt controller 212, a random number circuit 213, a CPU 214, and a ROM 215. A RAM 216, a timer circuit (PIT) 217, a serial communication circuit (SCI) 218, and an external bus interface 219. The random number circuit 213 only needs to have the same configuration as the random number circuit 103 included in the game control microcomputer 100, and the serial communication circuit 218 is similar to the serial communication circuit 108 included in the game control microcomputer 100. What is necessary is just to have the structure of. The payout control microcomputer 150 may not include the random number circuit 213.

  The ROM 215 provided in the payout control microcomputer 150 stores a payout control program. In the payout control microcomputer 150, for example, the CPU 214 reads out a payout control program stored in the ROM 215, and performs various processes based on the payout control command transmitted from the main board 11 and the communication result with the card unit 70. Is executed to control the game ball payout operation.

  In the RAM 216 provided in the payout control microcomputer 150, for example, a payout control data holding area 140 as shown in FIG. 26 is provided as an area for holding various data used for controlling the payout operation of the game ball. It has been. Further, at least a part of the RAM 216 is a backup RAM that is backed up by a backup power source created in the power supply substrate 10. That is, even if the power supply to the pachinko gaming machine 1 is stopped, at least a part of the contents of the RAM 216 is saved for a predetermined time. In this embodiment, it is assumed that the entire RAM 216 is a backup RAM that is backed up. The payout control data holding area 140 illustrated in FIG. 26 includes a payout control flag setting unit 141, a payout control timer setting unit 142, a payout control counter setting unit 143, and a payout control buffer setting unit 144.

  The payout control flag setting unit 141 includes, for example, a payout backup flag, a payout control process flag, a prize ball payout operation process flag, a ball lending operation process flag, a prize ball ACK transmission flag, a feedback reception flag, a reception confirmation flag, and an error flag. Etc. are provided.

  The payout control process flag indicates which process should be selected and executed in the payout operation control process (step S535 in FIG. 47 and FIG. 50) for controlling the payout operation of the game ball by the payout motor 51. The prize ball payout operation process flag indicates which process in the prize ball payout operation process (step S663 in FIG. 50 and FIG. 53) executed to drive the payout motor 51 to pay out a game ball as a prize ball. Indicates whether to select and execute. The ball lending operation process flag selects which process in the ball lending / dispensing operation processing (steps S664 and FIG. 57 in FIG. 50) executed to drive the payout motor 51 to pay out the game balls to be lent.・ Indicates whether to execute.

  The prize ball ACK transmission flag indicates that a prize ball ACK command is transmitted when a payout number designation command from the main board 11 is received. That is, the winning ball ACK transmission flag is set to the ON state when any of the first to third payout number designation commands is received. The feedback reception flag indicates whether or not an ACK feedback command from the main board 11 has been received. That is, the feedback reception flag is set to an on state when an ACK feedback command is received.

  The reception confirmation flag indicates that the reception of the ACK feedback command from the main board 11 is being confirmed after the award ball ACK command is transmitted to the main board 11. In other words, the reception confirmation flag is set to the ON state when the winning ball ACK command is transmitted, and then when the ACK feedback command is received or when a predetermined period has elapsed without receiving the ACK feedback command. Cleared and turned off.

  An error flag provided in the payout control flag setting unit 141 causes a predetermined error to occur based on a payout operation state of the game ball by driving the payout motor 51, a command transmission / reception state with the main board 11, and the like. It is configured to include a plurality of types of flags that are set to the ON state when detected. For example, the error flags are: main board communication error flag, large amount unpaid error flag, card unit unconnected error flag, ball clogged error flag, ball biting error flag, idle cut (back) error flag, empty cut (front) error flag Including serial communication error flag.

  Here, the main board communication error flag is set to the ON state when an error occurs in the communication state with the main board 11. The large amount unpaid error flag is set to an on state when the number of unpaid award balls that have not been paid out after the payout is instructed by the payout number designation command from the main board 11 exceeds a predetermined number. . The card unit unconnected error flag is set to ON when an error occurs in the communication state with the card unit 70. The ball clogging error flag is set to an on state, for example, when a detection signal from the payout count switch 72 is continuously on for a predetermined time (as a specific example, 0.5 seconds). . For example, when the dispensing motor 51 is driven, the ball biting error flag is set to the on state when the dispensing motor position sensor 71 is continuously on or off for a predetermined time or longer. For example, when the payout motor 51 is driven, the idle cut (back) error flag indicates that the game ball on the back side of the ball passage 90 in the payout device as shown in FIG. When the passage cannot be detected by the payout count switch 72, the on state is set. For example, when the payout motor 51 is driven, the idle cut (front) error flag indicates that the game ball on the front side of the ball passage 90 in the payout device as shown in FIG. When the passage cannot be detected by the payout count switch 72, the on state is set. The serial communication error flag is set to an on state in response to an error interrupt request from the serial communication circuit 218.

  The payout control timer setting unit 142 is provided with, for example, a communication control timer, a transmission operation control timer, and the like. The communication control timer is used for measuring various times in the communication operation for transmitting / receiving commands to / from the main board 11. The transmission operation control timer is used for measuring an elapsed time after transmission of communication data by serial communication by the serial communication circuit 218.

  The payout control counter setting unit 143 includes, for example, a prize ball unpaid counter, a previous unpaid counter, a ball lending unpaid counter, a payout counter, a payout operation failure counter, a payout motor rotation counter, a command reception counter, and command transmission. A waiting counter is provided.

  Based on the first to third payout number designation commands transmitted from the main board 11, the prize ball unpaid counter stores the number of game balls to be paid out as prize balls in an updatable manner as a prize ball unpaid count value. Therefore, it is for counting. The previous unpaid counter is paid out by the payout motor 51 when, for example, the award ball unpaid count value is updated by receiving any of the first to third payout number designation commands transmitted from the main board 11. In response to the payout motor rotation count value indicating the operation amount being stored in the payout motor rotation counter, the prize ball unpaid count value stored by the prize ball unpaid counter is stored as the previous unpaid count value. Is.

  The ball lending unpaid counter is for counting the number of game balls to be paid out as lending balls based on a ball lending request from the card unit 70 by storing it as a ball lending unpaid count value. It is. The payout number counter counts the number of game balls detected by the payout count switch 72 by driving the payout motor 51 by storing the number of game balls as a payout number count value. The payout operation failure frequency counter counts the number of times when a payout operation failure is detected when the payout motor 51 is driven to pay out a game ball by storing it updatable as a payout operation failure frequency count value. Is for. The payout motor rotation counter stores, in an updatable manner, a payout motor rotation count value corresponding to the number of game balls to be paid out as prize balls or rental balls, and sets the drive amount (rotation amount) of the payout motor 51 Used.

  The command reception number counter is for counting the number of commands received from the main board 11 in an identifiable manner. The command transmission waiting counter is used to count the number of commands waiting to be transmitted to the main board 11 in an identifiable manner.

  The payout control buffer setting unit 144 is provided with, for example, a payout checksum buffer, a reception command buffer, a transmission command buffer, and the like. The payout checksum buffer is for storing a checksum calculated using stored data in a specific area of the RAM 216 when power supply to the pachinko gaming machine 1 is stopped. The reception command buffer is used for temporarily storing commands received from the main board 11 by the payout control board 15. The transmission command buffer is used to temporarily store a command transmitted from the payout control board 15 to the main board 11.

  Next, the operation (action) of the pachinko gaming machine 1 in this embodiment will be described. In the main board 11, when the power supply from the power supply board 10 is started and the reset signal to the game control microcomputer 100 becomes high level (off state), the game control microcomputer 100 is activated, A game control main process as shown in the flowchart of FIG. 27 is executed. Note that each process described below is executed by the CPU 104 provided in the game control microcomputer 100. An interrupt request based on various interrupt factors generated by the timer circuit 107 and the serial communication circuit 108 provided in the game control microcomputer 100 is for causing the CPU 104 to execute predetermined interrupt processing. The concept including the CPU 104 and various circuits other than the CPU 104 is sometimes referred to as a game control microcomputer 100. When the game control main process shown in FIG. 27 is started, the game control microcomputer 100 first sets the interrupt prohibition (step S1) and sets the interrupt mode (step S2). For example, in step S2, the value (1 byte) of the specific register (I register) of the game control microcomputer 100 and the interrupt vector (1 byte: the least significant bit is “0”) output by the built-in device are synthesized. This sets an interrupt mode for maskable interrupts in which interrupt addresses are generated. When an interrupt that can be masked occurs, the microcomputer 100 for game control is automatically set to be in an interrupt disabled state, and the contents of the program counter may be saved in the stack.

  Subsequently, settings relating to the stack pointer such as setting of a stack pointer designation address are performed (step S3). The built-in device register is set (initialized) (step S4). For example, when the game control microcomputer 100 has a built-in CTC (counter / timer) and PIO (parallel input / output port), the processing in step S4 is executed, whereby a built-in device (built-in peripheral circuit). CTC or PIO setting (initialization) or the like may be performed.

  After executing the process of step S4, for example, by checking the state of a predetermined bit at the input port provided in the gaming control microcomputer 100, it is determined whether or not the power-off signal is in an off state. (Step S5). When power supply to the pachinko gaming machine 1 is started, various power supply voltages such as VCC gradually increase and reach a specified value. In the process of step S5, it is confirmed that the power-off signal is not output and is in an off state (high level). Here, the game control microcomputer 100 may confirm the state of the power-off signal only once through the input port, but may confirm the state of the power-off signal a plurality of times. For example, if it is confirmed once that the power-off signal is in the OFF state, the power-off signal is confirmed once again after a predetermined time (for example, 0.1 second) has elapsed. At this time, if the power-off signal is off, it is determined that the power-off signal is off. On the other hand, if the state of the power-off signal is on at this time, the state of the power-off signal may be confirmed again after a predetermined time has elapsed. In addition, the number of times of reconfirming the state of the power-off signal may be one time or a plurality of times. Further, it is possible to check twice and check again when the check results do not match.

  When the power-off signal is in the ON state in step S5 (step S5; No), after waiting for a predetermined time (for example, 0.1 second) to elapse (step S6), the process returns to step S5, and the power It is determined again whether or not the disconnection signal is off. Thereby, the game control microcomputer 100 can confirm that the power supply voltage is stable. When the power-off signal is off in step S5 (step S5; Yes), for example, a clear signal is generated by checking the state of a predetermined bit in the input port provided in the game control microcomputer 100. It is determined whether or not it is on (step S7). At this time, if the clear signal is on (step S7; Yes), for example, the clear flag provided in the game control flag setting unit 133 is set to the on state (step S8). On the other hand, when the clear signal is in the off state (step S7; No), the process of step S8 is skipped and the clear flag remains in the off state.

  Here, the game control microcomputer 100 may confirm the state of the clear signal only once through the input port, but may confirm the state of the clear signal a plurality of times. For example, once it is confirmed that the state of the clear signal is off, the state of the clear signal is confirmed once again after a predetermined time (for example, 0.1 second) has elapsed. At this time, if the clear signal is off, it is determined that the clear signal is off. On the other hand, if the state of the clear signal is on at this time, the state of the clear signal may be confirmed again after a predetermined time has elapsed. Note that the number of times of reconfirming the state of the clear signal may be one time or may be a plurality of times. Further, it is possible to check twice and check again when the check results do not match.

  Thereafter, a delay process for delaying the start timing of the game control process for controlling the progress of the game by executing the software is set (step S9). As a specific example, an initialization weight number designation value is set in a wait counter provided in the game control counter setting unit 135. Subsequently, the delay process based on the setting in step S9 is started, and the setting relating to the execution of the delay process is updated, for example, by subtracting 1 from the count value in the wait counter (step S10). Then, for example, it is determined whether or not a predetermined delay time has elapsed by determining whether or not the count value in the wait counter has reached a predetermined delay end determination value (step S11). Here, the data indicating the delay end determination value may be stored in advance in the ROM 105 or the like. For example, the delay end determination value is from when the game control process becomes executable until at least execution of various processes for payout control by the payout control microcomputer 150 mounted on the payout control board 15 is started. A predetermined reference value may be used so that the delay time becomes longer than the time.

  If the delay time has not elapsed in step S11 (step S11; No), the process returns to step S10. If the delay time has elapsed (step S11; Yes), the RAM 106 is set to be accessible (step S11). S12). Subsequently, the game control microcomputer 100 determines whether or not the clear flag is on (step S13). When the clear flag is off (step S13; No), data check of the RAM 106 is performed to determine whether or not the check result is normal (step S14). In the process of step S14, for example, a checksum is calculated using data stored in a specific area of the RAM 106, and the calculated checksum is compared with the checksum stored in the main checksum buffer. Here, the main checksum buffer stores a checksum calculated by the same processing when the power supply was stopped last time. If the comparison results do not match, the data in the specific area of the RAM 106 is different from the data at the time of stopping the power supply, and therefore it is determined that the check result is not normal.

  When the check result in step S14 is normal (step S14; Yes), it is determined whether or not the main backup flag provided in the game control flag setting unit 133 is on (step S15). The state of the main backup flag is set in the game control flag setting unit 133 when the power supply is stopped. The main backup flag setting location is backed up by the backup power source, so that the state of the main backup flag is saved even when the power supply is stopped. In step S15, for example, if “55H” is set in the game control flag setting unit 133 as the value of the main backup flag, it is determined that there is a backup (ON state). On the other hand, if a value other than “55H” is set, it is determined that there is no backup (OFF state). Note that the determination as to whether or not the main backup flag is turned on as in step S15 is performed prior to the determination of the check result as in step S14, and the data check of the RAM 106 is performed when the main backup flag is turned on. You may make it determine whether a result is normal.

  If the main backup flag is on in step S15 (step S15; Yes), after the main backup flag is cleared and turned off (step S16), the internal state of the game control microcomputer 100 is supplied with power. Settings at the time of recovery for returning to the state when stopped are performed (step S17). As a specific example, in the process of step S17, the start address of the backup setting table stored in the ROM 105 is set as a pointer, and the contents of the backup setting table are sequentially set in the work area in the RAM 106. Here, the work area of the RAM 106 is backed up by a backup power source, and initialization data for an area that may be initialized among the work areas may be set in the backup time setting table.

  Further, when the clear flag is on in step S13 (step S13; Yes), when the check result is not normal in step S14 (step S14; No), or the main backup flag is off in step S15. If there is (step S15; No), the RAM 106 is initialized (step S18). Subsequent to the processing of step S18, settings at the time of initialization for setting the internal state and the like of the game control microcomputer 100 to the initial state are performed (step S19). As a specific example, in the process of step S19, the head address of the initialization setting table stored in the ROM 105 is set as a pointer, and the contents of the initialization setting table are sequentially set in the work area in the RAM 106. . In the process of step S19, a predetermined initial count value (for example, “200”) is set in the command transmission number counter provided in the game control counter setting unit 135.

  After executing the processing of step S17 or step S19, a timer interrupt is generated every predetermined time (for example, 2 milliseconds) by setting a register of the timer circuit 107 provided in the game control microcomputer 100, for example. The internal setting of the game control microcomputer 100 is performed (step S20). Thereafter, the CPU 104 reads the fourth and third bits [bits 4-3] of the first random number initial setting data (KRSS1) stored in the ROM 105 (step S21), and performs random number generation operation based on the read values. Initial setting is performed (step S22). FIG. 28 is an explanatory diagram showing an example of the processing content executed in step S22.

  When the read value in step S21 is “00”, no processing is performed as the processing in step S22, and the process proceeds to step S23. At this time, as a process of step S22, a process for stopping the generation operation of both the 12-bit random number and the 16-bit random number in the random number circuit 103 may be executed. When the read value in step S21 is “01”, 12-bit random number initial setting processing is executed as processing in step S22. At this time, processing for stopping the generation operation of the 16-bit random number in the random number circuit 103 may be executed. When the read value in step S21 is “10”, 16-bit random number initial setting processing is executed as processing in step S22. At this time, a process for stopping the generation operation of the 12-bit random number in the random number circuit 103 may be executed. When the read value in step S21 is “11”, a 12-bit random number initial setting process and a 16-bit random number initial setting process are executed as the process in step S22.

  Subsequent to the process of step S22, a serial communication initial setting process is executed as a process for initial setting of the serial communication operation (step S23). In the serial communication initial setting process in step S23, for example, the CPU 104 reads serial communication initial setting data which is stored in a predetermined area of the ROM 105 and used for setting the operation of the serial communication circuit 108, and based on the read value, the serial communication circuit A process of setting the serial control register included in 108 to a predetermined initial operation state is executed. After executing the serial communication initial setting process, the interrupt initial setting process is executed as a process for performing an initial setting related to the interrupt process executed based on the interrupt request (step S24). In the interrupt initial setting process in step S24, for example, the CPU 104 reads the highest priority interrupt setting (KHPR) stored in the area of E01Bh in the ROM 105 as shown in FIG. 19, and sets the highest priority interrupt based on the read value. Execute processing. More specifically, the value of the highest priority interrupt setting (KHPR) read out by the CPU 104 is specified from “00h” to “07h”, and the I class interrupt (IRQ) corresponding to the specified value is specified. It is only necessary to set the reading order of stored data in a predetermined register so that the factor becomes the interrupt factor with the highest priority. Data indicating the setting of the reading order may be stored in an internal register of the CPU 104, for example. In this case, the CPU 104 preferentially checks the data stored in the internal register when an interrupt request signal input from the reset / interrupt controller 102 to the I class interrupt (IRQ) terminal or the like is turned on. The interrupt process to be executed can be specified.

  Subsequently, the game control microcomputer 100 sets the interrupt permitted state (step S25), and waits for the occurrence of various interrupts. At this time, it is determined whether or not the power-off signal has been turned on (whether or not it has been output) (step S26). When the power-off signal is turned on (step S26; Yes), after executing the main-side power-off process (step S27), a predetermined loop process is executed to control the game by stopping power supply. Wait until the microcomputer 100 stops operating. In the process of step S26, the state of the power-off signal may be confirmed only once via the input port, but the state of the power-off signal may be confirmed a plurality of times. For example, if it is confirmed once that the power-off signal is in the OFF state, the power-off signal is confirmed once again after a predetermined time (for example, 0.1 second) has elapsed. At this time, if the power-off signal is off, it is determined that the power-off signal is off. On the other hand, if the state of the power-off signal is on at this time, the state of the power-off signal may be confirmed again after a predetermined time has elapsed. In addition, the number of times of reconfirming the state of the power-off signal may be one time or a plurality of times. Further, it is possible to check twice and check again when the check results do not match. Thus, when confirming the state of the power-off signal a plurality of times, for example, when the confirmation operation is started or when the first confirmation result and the second confirmation result are compared and there is a mismatch, Retriggering is performed to clear the WDT (watchdog timer) built in the control microcomputer 100. When the retrigger does not occur within a predetermined time for some reason (for example, program runaway), a user reset is generated based on a timeout signal output from the WDT, and the reset / interrupt controller 102, CPU 104, timer circuit After initializing each circuit such as 107 and the serial communication circuit 108, execution of the user program may be started from an address indicated by a predetermined vector table to perform automatic recovery.

  In the main-side power-off process in step S27, for example, after the CPU 104 is set to prohibit the interrupt, the clear data is set in a predetermined bit of the output port provided in the game control microcomputer 100, for example, the solenoids 81 and 82. Initialize the settings related to drive control. At this time, clear data may be set for an output port to be cleared in addition to a predetermined bit of the output port. Subsequently, for example, check data is created by calculating a checksum using data stored in a specific area of the RAM 106, and the main backup flag provided in the game control flag setting unit 133 is set to an on state. . The check data created at this time is stored in a predetermined area of the RAM 106 such as a main checksum buffer provided in the game control buffer setting unit 136, for example. Then, in the game control microcomputer 100, for example, the CPU 104 prohibits access to the RAM 106 by setting an access prohibition value in a predetermined RAM access register. As a result, even if a program runaway occurs with the stop of power supply, the stored contents of the RAM 106 can be prevented from being damaged. After such main-side power-off processing is executed, a standby state (loop processing) is entered.

  In addition, after executing the main-side power-off process in step S27, for example, it is periodically determined whether or not the power-off signal is turned off. When the power-off signal is turned off, the CPU 104 performs steps shown in FIG. The processing may be resumed in response to the momentary interruption, for example, by proceeding again from S1. Alternatively, after the main-side power-off process is executed in step S27, for example, even if a predetermined time elapses that is longer than the time required until the time-out signal is output from WDT, the power supply board 10 When the power supply is continued, the CPU 104 may restart the process in response to the instantaneous interruption, for example, by proceeding again from step S1 shown in FIG.

  FIG. 29 is a flowchart illustrating an example of a 12-bit random number initial setting process included in the process executed in step S25. In the 12-bit random number initial setting process shown in FIG. 29, in the game control microcomputer 100, first, the CPU 104 reads the seventh bit [bit 7] of the second random number initial setting data (KRSS2) stored in the ROM 105 ( In step S101), it is determined whether or not the read value is “0” (step S102). At this time, if the read value in step S101 is “0” (step S102; Yes), the start value for the first round for generating a 12-bit random number in the random number circuit 103 is “001h” which is a default value. Is determined to be set to (step S103). On the other hand, if the read value in step S101 is “1” (step S102; No), the start value for the first round for generating a 12-bit random number in the random number circuit 103 is set for each game control microcomputer 100. A determination is made based on the ID number which is the unique identification information given (step S104). Here, in the process of step S104, for example, the ID number of the game control microcomputer 100 read out from the ROM 105 by the CPU 104 may be set as the start value for the first round for generating a 12-bit random number as it is. . Alternatively, a value calculated by executing a predetermined calculation using the ID number of the game control microcomputer 100 may be set as a start value for the first round for generating a 12-bit random number. . For example, the CPU 104 calculates the ID number of the game control microcomputer 100 read from the ROM 105 by performing a predetermined scramble process, or an operation such as addition / subtraction / multiplication / division using the ID number. A value may be used.

  The start value determined in step S103 or step S104 is input to an initial value setting circuit 172A included in the random number circuit 103, and is set as a start value for the first round for generating a 12-bit random number. Note that the processing in step S103 and step S104 may be executed by the initial value setting circuit 172A included in the random number circuit 103. For example, when the CPU 104 determines that the read value is “0” in step S <b> 102, a predetermined first initial value setting signal is sent to the random number circuit 103. When the random number circuit 103 receives the first initial value setting signal from the CPU 104, the initial value setting circuit 172A reads data stored in a predetermined register and sets the read value in the random number generation circuit 173A. Is set to the default value “001h” (processing corresponding to step S103). On the other hand, when the CPU 104 determines that the read value is “1” in step S102, it sends a second initial value setting signal different from the first initial value setting signal to the random number circuit 103. When the random number circuit 103 receives the first initial value setting signal from the CPU 104, the initial value setting circuit 172A selects data generated based on the ID number stored in a predetermined register, and generates the selected data as a random number. The start value for the first round for generating a 12-bit random number is set to a value based on an ID number that is unique identification information given to each game control microcomputer 100 by setting in the circuit 173A. (Processing corresponding to step S104). Here, as the ID number stored in the predetermined register, only the numerical value of the digit that is equal to or less than the maximum value of the 12-bit random number may be extracted and set in the random number generation circuit 173A. Alternatively, an ID number stored in a predetermined register is input to an arithmetic circuit (for example, a multiplier circuit) built in the initial value setting circuit 172A, so that a predetermined calculation using a numerical value in each digit of the ID number is performed, for example. Data that is executed and indicates a value calculated by this calculation may be set in the random number generation circuit 173A. Further, the CPU 104 may directly control the operation of the initial value setting circuit 172A to execute the processing corresponding to steps S103 and S104. For example, the CPU 104 is provided inside or outside the random number circuit 103 for initial value setting control. Then, the operation of the initial value setting circuit 172A may be indirectly controlled by setting control data corresponding to the read value in step S101 in a predetermined register that can be referred to by the initial value setting circuit 172A. . When the CPU 104 sets control data in the initial value setting control register, for example, when the random number circuit 103 starts generating a 12-bit random number, the initial value setting circuit 172A is stored in the initial value setting register. The initial value setting operation according to the control data is performed to generate a start value for the first round corresponding to the read value in step S101 and set it in the random number generation circuit 173A. be able to.

  After executing one of the processes in steps S103 and S104, the CPU 104 reads out the sixth and fifth bits [bits 6-5] of the second random number initial setting data (KRSS2) stored in the ROM 105 (step S105). ) Based on the read value, the selection operation is set in the selector 174A provided in the random number circuit 103 as a selector for a 12-bit random number (step S106). For example, when the read value in step S105 is “00”, the output signal of the selector 174A is set to be always off. As a result, a third method that does not change the permutation, which is the update order of the 12-bit random number, is set. When the read value in step S105 is “10”, the selector 174A is set to select and output the output signal from the ARSC 175A. At this time, the selector 174A only needs to output the output signal from the ARSC 175A in synchronization with the random number loop signal RIJ1 output from the random number generation circuit 173A. As a result, a second method is set that allows the user program to change the permutation in the second and subsequent rounds of the 12-bit random number. When the read value in step S105 is “11”, the selector 174A is set to select and output the random number loop signal RIJ1 output from the random number generation circuit 173A. As a result, the first method for automatically changing the permutation in the second and subsequent rounds of the 12-bit random number is set. In the process of step S106, the CPU 104 may directly set the signal output operation of the selector 174A to output a signal corresponding to the read value in step S105. The signal output operation of the selector 174A may be indirectly controlled by setting control data corresponding to the read value in step S105 in a predetermined register that is provided outside and can be referred to by the selector 174A. . When the control data is set in the register in step S106, for example, when the random number loop signal RIJ1 is output from the random number generation circuit 173A, the selector 174A refers to the control data stored in the register, and the control data By performing the signal output operation according to this, a signal corresponding to the setting in step S106 can be output to the random number sequence change circuit 176A, and the permutation for generating the 12-bit random number can be changed or held.

  Following the processing in step S106, the CPU 104 reads the 12-bit random number maximum value (KRMS) stored in the ROM 105 (step S107), and sets the read value in the maximum value comparison circuit 177A included in the random number circuit 103 (step S107). S108). At this time, it is determined whether or not the read value in step S107 is within a range that can be set as the maximum value for 12-bit random numbers (step S109). For example, if the maximum value of the 12-bit random number can be arbitrarily set within the range from “256” to “4095”, is the read value at step S107 within the range from “256” to “4095”? Determine whether or not.

  When it is determined in step S109 that the read value is not within the settable range (step S109; No), the predetermined value within the range that can be set as the maximum value for the 12-bit random number is reset as the maximum value. The random number circuit 103 is set in the maximum value comparison circuit 177A (step S110). For example, when the read value in step S107 is not within the range from “256” to “4095”, the value “4095” within the range may be reset as the maximum value. In the processing of steps S108 and S110, the CPU 104 may directly control the operation of the maximum value comparison circuit 177A to set the maximum value for 12-bit random numbers. For example, it is provided inside or outside the random number circuit 103. Then, the operation of the maximum value comparison circuit 177A may be indirectly controlled by setting control data indicating the maximum value for 12-bit random numbers in a predetermined register that can be referred to by the maximum value comparison circuit 177A. . When the control data is set in the register in steps S108 and S110, for example, the maximum value comparison circuit 177A is stored in the register every time the value of the numerical data sequence R1 output from the random number sequence change circuit 176A is updated. By referring to the control data and comparing the maximum value for the 12-bit random number indicated by the control data with the numerical data output from the random number sequence changing circuit 176A, only the numerical data that is less than or equal to the maximum value is a random value. It can be output as a 12-bit random value stored in the register 181A. If it is determined in step S109 that the read value is within the settable range (step S109; Yes), the process of step S110 is skipped.

  Thereafter, the CPU 104 reads the first and 0th bits [bits 1-0] of the first random number initial setting data (KRSS1) stored in the ROM 105 (step S111). Then, based on the read value in step S111, initial setting is made regarding the start value after the second round in the 12-bit random number (step S112). As a specific example, in the process of step S112, the read data indicating the first and 0th bits [bits 1-0] of the first random number initial setting data (KRSS1) read by the CPU 104 from the ROM 105 is stored in the random number circuit 103 or Setting related to the start value for the second and subsequent rounds in the 12-bit random number while the CPU 104 is executing the timer interrupt processing for game control by storing in a predetermined register built into the CPU 104 or a predetermined area of the RAM 106 It suffices if an initial setting is made so that reference can be made.

  FIG. 30 is a flowchart illustrating an example of a 16-bit random number initial setting process included in the process executed in step S22. In the 16-bit random number initial setting process shown in FIG. 30, in the game control microcomputer 100, the CPU 104 first reads the second bit [bit 2] of the first random number initial setting data (KRSS1) stored in the ROM 105 ( In step S121), operation setting in the clock signal output circuit 171 provided in the random number circuit 103 is performed based on the read value (step S122). For example, when the read value in step S121 is “0”, the clock signal S1 output from the clock signal output circuit 171 is output in the same cycle as the internal system clock CLK input to the clock input terminal of the clock signal output circuit 171. Set to be a clock signal. When the read value in step S121 is “1”, the clock signal S1 output from the clock signal output circuit 171 is 16 times the internal system clock CLK input to the clock input terminal of the clock signal output circuit 171. The clock signal is set to have a period. In the process of step S122, the CPU 104 may directly set the operation of the clock signal output circuit 171 to output the clock signal corresponding to the read value in step S121. The operation of the clock signal output circuit 171 is indirectly controlled by setting control data corresponding to the read value in step S121 in a predetermined register which is provided inside or outside and can be referred to by the clock signal output circuit 171. You may make it do. When the control data is set in the register in step S122, for example, the clock signal output circuit 171 refers to the control data stored in the register when the random number circuit 103 starts generating the 16-bit random number, By performing a clock signal output operation according to the control data, a clock signal according to the setting in step S121 can be output.

  Subsequent to step S122, the CPU 104 reads the fourth bit [bit 4] of the second random number initial setting data (KRSS2) stored in the ROM 105 (step S123), and whether or not the read value is “0”. Is determined (step S124). At this time, if the read value in step S123 is “0” (step S124; Yes), the start value for the first round for generating a 16-bit random number in the random number circuit 103 is “0001h” which is a default value. Is determined to be set (step S125). On the other hand, if the read value in step S123 is “1” (step S124; No), the start value for the first round for generating a 16-bit random number in the random number circuit 103 is set for each game control microcomputer 100. A determination is made based on the ID number which is the unique identification information given (step S126). Here, in the process of step S126, for example, the ID number of the game control microcomputer 100 read out from the ROM 105 by the CPU 104 may be set as the start value for the first round for generating a 16-bit random number as it is. . Alternatively, a value calculated by executing a predetermined calculation using the ID number of the game control microcomputer 100 may be set as a start value for the first round for generating a 16-bit random number. . For example, the CPU 104 calculates the ID number of the game control microcomputer 100 read from the ROM 105 by performing a predetermined scramble process, or an operation such as addition / subtraction / multiplication / division using the ID number. A value may be used.

  The start value determined in step S125 or step S126 is input to an initial value setting circuit 172B included in the random number circuit 103, and is set as a start value for the first round for generating a 16-bit random number. Note that the processing of step S125 and step S126 may be executed by the initial value setting circuit 172B included in the random number circuit 103. For example, when the CPU 104 determines that the read value is “0” in step S <b> 124, it sends a predetermined third initial value setting signal to the random number circuit 103. When the random number circuit 103 receives the third initial value setting signal from the CPU 104, the initial value setting circuit 172B reads data stored in a predetermined register, sets the read value in the random number generation circuit 173B, etc. Is set to the default value “0001h” (processing corresponding to step S125). On the other hand, when the CPU 104 determines that the read value is “1” in step S <b> 124, it sends a fourth initial value setting signal different from the third initial value setting signal to the random number circuit 103. When the random number circuit 103 receives the fourth initial value setting signal from the CPU 104, the initial value setting circuit 172B selects data generated based on the ID number stored in a predetermined register, and generates the selected data as a random number. The start value for the first round for generating a 16-bit random number is set to a value based on an ID number that is unique identification information given to each game control microcomputer 100 by setting the circuit 173B. (Processing corresponding to step S126). Here, the ID number stored in the predetermined register may be set in the random number generation circuit 173B by extracting only the numerical value of the digit that is equal to or less than the maximum value of the 16-bit random number. Alternatively, the ID number stored in the predetermined register is input to an arithmetic circuit (for example, a multiplier circuit) built in the initial value setting circuit 172B, so that a predetermined calculation using a numerical value in each digit of the ID number is performed. Data that is executed and indicates a value calculated by this calculation may be set in the random number generation circuit 173B. Further, the CPU 104 may directly control the operation of the initial value setting circuit 172B to execute processing corresponding to steps S125 and S126. For example, the CPU 104 may be provided inside or outside the random number circuit 103 for initial value setting control. Then, the operation of the initial value setting circuit 172B may be indirectly controlled by setting control data corresponding to the read value in step S123 in a predetermined register that can be referred to by the initial value setting circuit 172B. . When the CPU 104 sets control data in the initial value setting control register, for example, when the random number circuit 103 starts generating a 16-bit random number, the initial value setting circuit 172B is stored in the initial value setting register. The initial value setting operation according to the control data is performed, and the start value for the first round corresponding to the read value in step S123 is generated and set in the random number generation circuit 173B. be able to.

  After executing one of the processes in steps S125 and S126, the CPU 104 reads the first and 0th bits [bits 1-0] of the second random number initial setting data (KRSS2) stored in the ROM 105 (step S127). ), A selection operation is set in the selector 174B provided in the random number circuit 103 as a selector for a 16-bit random number based on the read value (step S128). For example, when the read value in step S127 is “00”, the output signal of the selector 174B is set to be always in the off state. As a result, a third method that does not change the permutation, which is the update order of 16-bit random numbers, is set. When the read value in step S127 is “10”, the selector 174B is set to select and output the output signal from the BRSC 175B. At this time, the selector 174B only needs to output the output signal from the BRSC 175B in synchronization with the random number round signal RIJ2 output from the random number generation circuit 173B. As a result, a second method is set that allows the user program to change the permutation of the 16-bit random number after the second round. Further, when the read value in step S127 is “11”, the selector 174B is set to select and output the random number loop signal RIJ2 output from the random number generation circuit 173B. Thus, the first method for automatically changing the permutation in the second and subsequent rounds of the 16-bit random number is set. In the process of step S128, the CPU 104 may directly set the signal output operation of the selector 174B to output a signal corresponding to the read value in step S127. The signal output operation of the selector 174B may be indirectly controlled by setting control data corresponding to the read value in step S127 in a predetermined register that is provided outside and can be referred to by the selector 174B. . When the control data is set in the register in step S127, for example, when the random number round trip signal RIJ2 is output from the random number generation circuit 173B, the selector 174B refers to the control data stored in the register, and the control data By performing the signal output operation according to this, a signal corresponding to the setting in step S128 can be output to the random number sequence change circuit 176B, and the permutation for generating a 16-bit random number can be changed or held.

  Following the processing of step S128, the CPU 104 reads the maximum 16-bit random number (KRXS) stored in the ROM 105 (step S129), and sets the read value in the maximum value comparison circuit 177B included in the random number circuit 103 (step S129). S130). At this time, it is determined whether or not the read value in step S129 is within a range that can be set as the maximum value for 16-bit random numbers (step S131). For example, if the maximum value of the 16-bit random number can be arbitrarily set within the range from “512” to “65535”, is the read value at step S129 within the range from “512” to “65535”? Determine whether or not.

  When it is determined in step S131 that the read value is not within the settable range (step S131; No), a predetermined value within the range that can be set as the maximum value for 16-bit random numbers is reset as the maximum value. Then, the maximum value comparison circuit 177B included in the random number circuit 103 is set (step S132). For example, when the read value in step S129 is not within the range from “512” to “65535”, “65535” that is the value within the range may be reset as the maximum value. In the processing of steps S130 and S132, the CPU 104 may directly control the operation of the maximum value comparison circuit 177B to set the maximum value for 16-bit random numbers. For example, it is provided inside or outside the random number circuit 103. Then, the operation of the maximum value comparison circuit 177B may be indirectly controlled by setting control data indicating the maximum value for 16-bit random numbers in a predetermined register that can be referred to by the maximum value comparison circuit 177B. . When the control data is set in the register in steps S130 and S132, for example, the maximum value comparison circuit 177B is stored in the register every time the value of the numerical data sequence R2 output from the random number sequence change circuit 176B is updated. By referring to the control data and comparing the maximum value for the 16-bit random number indicated by the control data with the numerical data output from the random number sequence change circuit 176B, only the numerical data that is less than or equal to the maximum value is a random value. It can be output as a 16-bit random value stored in the register 181B. When it is determined in step S131 that the read value is within the settable range (step S131; Yes), the process of step S132 is skipped.

  Thereafter, the CPU 104 reads out the third and second bits [bit 3-2] of the second random number initial setting data (KRSS2) stored in the ROM 105 (step S133). Then, based on the read value in step S133, initial setting is made regarding the start value after the second round in the 16-bit random number (step S134). As a specific example, in the process of step S134, the read data indicating the third and second bits [bit 3-2] of the second random number initial setting data (KRSS2) read by the CPU 104 from the ROM 105 is stored in the random number circuit 103 or Setting related to the start value for the second and subsequent rounds in the 16-bit random number while the CPU 104 is executing the timer interrupt processing for game control by storing in a predetermined register built in the CPU 104 or a predetermined area of the RAM 106 It is only necessary to perform an initial setting so that can be referred to.

  After entering the interrupt enabled state by executing the processing of step S25 shown in FIG. 27, for example, when a plurality of interrupt factors occur simultaneously in the timer circuit 107, the serial communication circuit 108, etc., the processing is executed in step S24. Based on the setting in the interrupt initial setting process or the like, the reset / interrupt controller 102 accepts an interrupt factor with a high priority. When the reset / interrupt controller 102 receives an interrupt factor, it outputs an interrupt request signal in an on state to, for example, an I class interrupt (IRQ) terminal provided in the CPU 104. When the interrupt request signal in the on state is input to the IRQ terminal by the CPU 104, for example, based on the result of checking the data stored in the internal register, the reading order is set based on the setting in the interrupt initial setting process executed in step S24. The bit value of the stored data in a predetermined register such as the timer control register included in the timer circuit 107 or the serial status register 204 included in the serial communication circuit 108 may be read in the order according to the order. From the stored data in the register thus read, the interrupt factor that occurred is identified, and the interrupt processing based on each interrupt factor is started by executing a program that starts with the vector address corresponding to the identified interrupt factor. Can do.

  As a specific example, when the highest priority interrupt setting (KHPR) is “05h”, first, the third to zeroth bits [bits 3-0] of the first register SIST1 included in the serial status register 204 are read. It is determined whether the bit value is “1”. At this time, if any bit value is “1”, it is determined that an interrupt process corresponding to the error interrupt factor generated in the serial communication circuit 108 is executed, and stored in a predetermined area of the ROM 105, for example. Get the interrupt vector being executed, and execute the program with the vector address as the start address. When all the bit values in the third to 0th bits [bits 3-0] of the first register SIST1 are “0”, an interrupt request in an on state is sent to the IRQ terminal provided in the gaming control microcomputer 100. It is determined whether or not an external interrupt factor has occurred due to the signal being input for a certain period. At this time, if an external interrupt factor has occurred, the interrupt processing corresponding to the external interrupt factor is executed. If no external interrupt factor has occurred, the stored data in the timer control register included in the timer circuit 107 is read. Based on the read value, the timer circuit 107 determines whether or not a timer interrupt factor has occurred. At this time, if a timer interrupt factor has occurred in the timer circuit 107, a timer interrupt process corresponding to the timer interrupt factor is executed. If no timer interrupt factor has occurred, the serial status register 204 includes The fifth and fourth bits [bits 5-4] of one register SIST1 are read, and it is determined whether or not any bit value is “1”. At this time, if any bit value is “1”, the reception interrupt process corresponding to the reception interrupt factor generated in the serial communication circuit 108 is executed, while any bit value is “0”. For example, the seventh and sixth bits [bit 7-6] of the first register SIST1 included in the serial status register 204 are read to determine whether any of the bit values is “1”. At this time, if any bit value is “1”, transmission interrupt processing corresponding to the transmission interrupt factor generated in the serial communication circuit 108 is executed.

  As described above, by checking whether or not the interrupt factors are generated in the order corresponding to the priority order based on the setting in the interrupt initial setting process executed in step S24 shown in FIG. When the error occurs, for example, based on the priority at the time of default as shown in FIG. 20B or the priority changed by the highest priority interrupt setting (KHPR) stored in the ROM 105, based on an interrupt factor having a higher priority. Interrupt processing is executed with higher priority than interrupt processing based on an interrupt factor having a low priority.

  For example, when the highest priority interrupt setting (KHPR) stored in the ROM 105 is “06h”, the default as shown in FIG. 20B is set by the setting in the interrupt initial setting process executed in step S24. The priority order at that time is changed to a priority order that gives the highest priority to the reception interrupt request from the serial communication circuit 108 as shown in FIG. In this case, the interrupt process based on the reception interrupt request from the serial communication circuit 108 is executed with priority over the interrupt process based on the error interrupt request from the serial communication circuit 108. As shown in FIG. 20B, at the time of default, the interrupt process based on the interrupt request from the timer circuit 107 is executed with priority over the interrupt process based on the interrupt request from the serial communication circuit 108. It is set. On the other hand, when the highest priority interrupt setting (KHPR) stored in the ROM 105 is “05h”, “06h”, or “07h”, each is based on an error interrupt request from the serial communication circuit 108. Interrupt processing, interrupt processing based on a reception interrupt request, and interrupt processing based on a transmission interrupt request are executed with higher priority than interrupt processing based on an interrupt request from the timer circuit 107.

  For example, when an error interrupt occurs in the serial communication circuit 108 provided in the game control microcomputer 100, a predetermined process is executed as the serial communication error interrupt process. Here, in the serial communication circuit 108, predetermined error interrupt factors such as an overrun error, a noise error, a framing error, or a parity error have occurred based on the setting in the serial control register. Sometimes an error interrupt can be generated. The overrun error occurs when the reception shift register provided in the reception operation unit of the serial communication circuit 108 receives the next data before the reception data in the serial communication circuit 108 is read by the user program. Error. The noise error is an error that occurs when noise of data received by the serial communication circuit 108 is detected. The framing error is an error that occurs when “0” is detected in the stop bit of the data received by the serial communication circuit 108. The parity error is an error that occurs when the parity of the data received by the serial communication circuit 108 does not match the parity bit in the received data. For example, when an error interrupt factor occurs in the serial communication circuit 108, an interrupt request is transmitted from the serial communication circuit 108 to the reset / interrupt controller 102, and the reset / interrupt controller 102 receives the interrupt factor as described above. The CPU 104 is notified of the occurrence of an interrupt by inputting an on-state interrupt request signal to the IRQ terminal of the CPU 104.

  When the serial communication error interrupt process is started, in the game control microcomputer 100, for example, the CPU 104 sets the transmission operation unit and the reception operation unit provided in the serial communication circuit 108 to the unused state, and the serial communication circuit 108 What is necessary is just to set not to perform the transmission / reception operation by. Further, when the serial communication error interrupt process is executed, for example, the CPU 104 may set the serial communication error flag provided in the game control flag setting unit 133 to the on state.

  In addition, when a reception interrupt occurs in the serial communication circuit 108 provided in the game control microcomputer 100, a predetermined process is executed as a serial reception interrupt process. By executing the serial reception interrupt process, the command received from the payout control board 15 by the serial communication circuit 108 is stored in the payout reception command buffer 191 provided in the game control buffer setting unit 136. Furthermore, when a transmission interrupt occurs in the serial communication circuit 108 provided in the game control microcomputer 100, a predetermined process is executed as a serial transmission interrupt process. In this serial transmission interrupt process, various types corresponding to the type of transmission interrupt, such as specifying the type of transmission interrupt generated in the serial communication circuit 108 and setting or clearing the flag according to the specified type of interrupt. It is sufficient if the process is executed.

  FIG. 31 is a flowchart showing an example of a game control timer interrupt process executed each time a timer interrupt occurs in the game control microcomputer 100. In the game control timer interrupt process shown in FIG. 31, the game control microcomputer 100 first saves the internal register (step S71), and then executes a predetermined switch process to perform each switch via the switch circuit 111. The state of the detection signal input from the switch is determined (step S72). Next, based on the detection signal input from the full switch 26 via the switch circuit 111 and the touch sensor detection signal input from the touch sensor 75, the launching device 19 and the ball feeding device 62 are driven or stopped to play a game. A launch control process for controlling the launch of the sphere is executed (step S73). After that, by executing a predetermined information output process, for example, data such as jackpot information, starting information, probability variation information supplied to a hall management computer installed outside the pachinko gaming machine 1 is output (step S74). ). Further, in the information output process of step S74, settings for transmitting a firing permission signal to the launching device 19 and transmitting a supply permission signal to the ball feeding device 62 are performed.

  Subsequent to the information output process in step S74, the game control microcomputer 100 executes a random number start value change setting process for changing the start value in the second and subsequent rounds of the random number by the user program read out from the ROM 105 by the CPU 104, for example. (Step S75). Further, for example, the CPU 104 executes a random number permutation change setting process for changing the permutation in the second and subsequent rounds of random numbers by the user program read from the ROM 105 (step S76).

  After executing the random number permutation change setting process in step S76, the game control microcomputer 100 sets the number of prize balls according to the input of the winning detection signal based on the execution result of the switch process in step S72. Sphere processing is executed (step S77). Further, the game control microcomputer 100 performs an abnormal operation notification setting process for performing settings for notifying the occurrence of an abnormal operation in response to excessive prize balls, insufficient prize balls, or other operation errors. Execute (Step S78). Subsequently, a main-side reception process for receiving a command transmitted from the payout control board 15 by serial communication is executed (step S79).

  Thereafter, the game control microcomputer 100 executes a special symbol process (step S80). In the special symbol process, the value of the special symbol process flag provided in the game control flag setting unit 133 is updated according to the progress of the game in the pachinko gaming machine 1, and the display operation control or special in the special symbol display device 4 is performed. Various processes are selected and executed in order to set the special winning opening / closing operation in the variable winning ball apparatus 7 in a predetermined procedure. Following the special symbol process, the normal symbol process is executed (step S81). The game control microcomputer 100 executes the normal symbol process, thereby controlling the display operation (for example, turning on / off the LED) of the normal symbol display 40 to change the normal symbol variable display (for example, turning on / off). Flashing display, etc.) and the tilt control of the movable blade piece in the normal variable winning ball apparatus 6 can be set.

  Furthermore, the game control microcomputer 100 transmits a payout control command from the main board 11 to the payout control board 15 by executing a payout command control process (step S82). In addition, the game control microcomputer 100 transmits an effect control command from the main board 11 to the effect control board 12 by executing an effect command control process (step S83). Thereafter, the game control microcomputer 100 executes a main-side error canceling process and enables a predetermined error to be cancelled when the detection signal from the error canceling switch 31 is turned on (step S84). . Then, after the contents of the register saved in step S71 are restored (step S85), the game control timer interrupt process is terminated.

  In the main-side error canceling process in step S83, for example, the CPU 104 determines whether or not the detection signal from the error canceling switch 31 is on based on the execution result of the switch process in step S72. At this time, if the detection signal from the error release switch 31 is on, it is determined whether, for example, a payout communication error detection flag is on. If the payout communication error detection flag is on, the payout communication error detection flag is cleared and turned off. When the detection signal from the error release switch 31 is on, it is determined whether or not the serial communication error flag is on. When the serial communication error flag is on, for example, the serial communication initial setting process similar to step S23 shown in FIG. 27 is executed to initialize the serial communication circuit 108, and then the serial communication error flag is set. Clear to turn off. Further, in the main-side error canceling process in step S83, it is determined whether or not the payout error canceling flag is on. If it is on, a payout error canceling command indicating that the error has been cancelled from the payout control board 15. The payout error notification flag may be cleared and set to the off state.

  FIG. 32 is a flowchart showing an example of the firing control process executed in step S73 shown in FIG. When the launch control process is started, in the game control microcomputer 100, for example, the CPU 104 first determines whether or not the touch sensor detection signal input from the touch sensor 75 via the switch circuit 111 is in an ON state. (Step S201). At this time, if the touch sensor detection signal is on (step S201; Yes), it is determined whether the detection signal input from the full switch 26 via the switch circuit 111 is on (step). S202).

  When the detection signal from the full switch 26 is in the OFF state in step S202 (step S202; No), for example, it is determined whether or not the firing control timer provided in the game control timer setting unit 134 has timed out ( Step S203). Note that, in step S208, which will be described later, a timer initial value that is an initial value for launch control is set in the launch control timer. If the firing control timer has not timed out in step S203 (step S203; No), the timer value of the firing control timer is updated by subtracting, for example, 1 (step S204). Thereafter, for example, by determining whether or not the firing control timer has timed out due to the update in step S204, it is determined whether or not the firing control time has elapsed (step S205).

  If the firing control time has not elapsed in step S205 (step S205; No), the firing control process is terminated. On the other hand, when the emission control time has elapsed in step S205 (step S205; Yes), a timer predetermined as a supply output initial value is set in the supply permission control timer provided in the game control timer setting unit 134. An initial value is set (step S206). Here, the initial value for supply output is a timer initial value determined in advance corresponding to the output time (for example, 12 milliseconds) of the supply permission signal periodically output every time the firing control time elapses. Good. Following the processing of step S206, a timer initial value set in advance as a firing output initial value is set in the firing permission control timer provided in the game control timer setting unit 134 (step S207). Here, the initial value for launch output is a timer initial value determined in advance corresponding to the output time (for example, 74 milliseconds) of the launch permission signal that is periodically output every time the launch control time elapses. Good.

  When the touch sensor detection signal input from the touch sensor 75 is OFF in step S201 (step S201; No), when the detection signal from the full switch 26 is ON in step S202 (step S202; Yes) When the firing control timer times out in step S203 (step S203; Yes), or after executing the processing of step S207, a timer initial value set in advance as the firing control initial value is set in the firing control timer. Setting is made (step S208). Note that the initial value for launch control is a control time (for example, 602) for periodically transmitting a launch permission signal from the main board 11 to the launching device 19 and a supply permission signal from the main board 11 to the ball feeding device 62. It may be a timer initial value determined in advance corresponding to (milliseconds).

  As described above, when the touch sensor detection signal input from the touch sensor 75 in step S201 is in the OFF state, or when the detection signal from the full switch 26 is in the ON state in step S202, the process in step S206. Otherwise, the process proceeds to step S208 without performing the process in step S207. Therefore, if the touch sensor detection signal from the touch sensor 75 is in the on state and the detection signal from the full switch 26 is in the off state, a launch permission signal from the main board 11 to the launching device 19 or the main board 11 is detected. Can be output to the ball feeding device 62, while the touch sensor detection signal from the touch sensor 75 is in the OFF state, or the detection signal from the full switch 26 is in the ON state. Sometimes, a firing permission signal from the main board 11 to the launching device 19 and a supply permission signal from the main board 11 to the ball feeding device 62 are not output.

  FIG. 33 is a flowchart showing an example of the information output process executed in step S74 shown in FIG. When the information output process is started, in the game control microcomputer 100, for example, the CPU 104 first determines whether or not the firing permission control timer has timed out (step S221). At this time, if the firing permission control timer has not timed out (step S221; No), the timer value of the firing permission control timer is updated by subtracting, for example, 1 (step S222). Subsequent to the processing in step S222, setting for outputting a firing permission signal to the launching device 19 is performed (step S223). As a specific example, in step S223, control data for turning on the firing permission signal is set to a predetermined bit provided for outputting the firing permission signal at the output port of the game control microcomputer 100. do it.

  When the firing permission control timer has timed out in step S221 (step S221; Yes), after executing the process of step S223, it is determined whether or not the supply permission control timer has timed out (step S224). . At this time, if the supply permission control timer has not timed out (step S224; No), the timer value of the supply permission control timer is updated by subtracting, for example, 1 (step S225). Subsequent to the process of step S225, setting for outputting a supply permission signal to the ball feeder 62 is performed (step S226). As a specific example, in step S226, control data for turning on the supply permission signal is set to a predetermined bit provided for output of the supply permission signal at the output port of the game control microcomputer 100. do it. When the supply permission control timer has timed out in step S224 (step S224; Yes), after executing the process of step S226, settings for outputting various information in the pachinko gaming machine 1 may be performed ( Step S227).

  34 and 35 are flowcharts showing an example of the random number start value change setting process executed in step S73 shown in FIG. When the random number start value change setting process is started, in the game control microcomputer 100, first, for example, the CPU 104 determines whether or not the 12-bit random number start value change flag provided in the game control flag setting unit 133 is on. Is determined (step S241 in FIG. 34). At this time, if the start value change flag for the 12-bit random number is on (step S241; Yes), the CPU 104 reads the setting related to the start value after the second round in the 12-bit random number (step S242), and the read value is “01. Is determined (step S243). As a specific example of the processing in step S242, setting data relating to a start value for the second and subsequent rounds in a predetermined register built in the random number circuit 103 or the CPU 104, or a 12-bit random number stored in a predetermined area of the RAM 106, What is necessary is just the process which CPU104 reads.

  When it is determined in step S203 that the read value is “01” (step S243; Yes), the random number circuit 103 generates a start value (start value after the second round) for generating a 12-bit random number. A determination is made based on the ID number, which is unique identification information given to each control microcomputer 100 (step S244). Here, in the process of step S244, the ID number of the game control microcomputer 100 may be set to the start value for generating a 12-bit random number as it is. Alternatively, a value calculated by executing a predetermined calculation using the ID number of the game control microcomputer 100 may be set as a start value for generating a 12-bit random number. For example, an operation for performing a predetermined scramble process on the ID number of the game control microcomputer 100 or an operation such as addition / subtraction / multiplication / division using the ID number is performed to use the calculated value. That's fine.

  If it is determined in step S243 that the read value is not “01” (step S243; No), it is determined whether or not the read value is “10” (step S245). When it is determined that the read value is “10” (step S245; Yes), the random number circuit 103 stores a start value (start value for the second and subsequent rounds) in the RAM 106 for generating a 12-bit random number. A process for determining a value based on the data is executed. That is, the CPU 104 reads the stored value at each address in the RAM 106 (step S246), and sequentially adds the read stored values (step S247). Then, the start value for generating the 12-bit random number is changed to the addition value calculated by the addition process in step S247 (step S248). In the process of step S248, it is determined whether or not the addition value calculated by the addition process in step S247 exceeds the maximum value. If not, the addition value is set as the start value as it is. In such a case, a predetermined value (for example, “1” or the like) that is equal to or less than the maximum value may be reset as the start value.

  When it is determined in step S245 that the read value is not “10” (step S245; No), it is determined whether or not the read value is “11” (step S249). When it is determined that the read value is “11” (step S249; Yes), the stored value of the designated address (designated RAM address) in the RAM 106 is read (step S250), and a start for generating a 12-bit random number is performed. The value is changed to the read value in step S250 (step S251).

  Note that the processes of steps S244, S246 to S248, S250, and S251 may be executed by the initial value setting circuit 172A included in the random number circuit 103. For example, when the CPU 104 determines that the read value is “01” in step S 243, a predetermined first initial value change signal is sent to the random number circuit 103. When the random number circuit 103 receives the first initial value change signal from the CPU 104, the initial value setting circuit 172A selects data generated based on the ID number stored in a predetermined register and generates the selected data as a random number. By setting the circuit 173A or the like, the start value for the second and subsequent rounds for generating a 12-bit random number is changed to a value based on an ID number that is unique identification information assigned to each game control microcomputer 100. Set (processing corresponding to step S244). On the other hand, if the CPU 104 determines that the read value is not “01” in step S203 and then determines that the read value is “10” in step S205, the random number circuit 103 is supplied with a predetermined second initial value change signal. Send. When the random number circuit 103 receives the second initial value change signal from the CPU 104, the initial value setting circuit 172A reads the stored value at each address of the RAM 106, and sequentially adds the read stored values. By setting the random number generation circuit 173A or the like, the start value for the second and subsequent rounds for generating a 12-bit random number is set to a value based on the data stored in the RAM 106 (processing corresponding to steps S246 to S248). When the CPU 104 determines that the read value is not “10” in step S245 and then determines that the read value is “11” in step S249, the random number circuit 103 is supplied with a predetermined third initial value change signal. Send. When the random number circuit 103 receives the third initial value change signal from the CPU 104, the initial value setting circuit 172A reads the stored value at the designated address in the RAM 106, sets the read stored value in the random number generation circuit 173A, etc. The start value for the second and subsequent cycles for generating the bit random number is set to be changed to the read stored value (processing corresponding to steps S250 and S251). Further, the CPU 104 may directly control the operation of the initial value setting circuit 172A to execute processing corresponding to steps S244, S246 to S248, S250, and S251. For example, the initial value may be set inside or outside the random number circuit 103. Control data corresponding to the read value in step S202 is set in a predetermined register provided for change control and which can be referred to by initial value setting circuit 172A (this data setting process is performed in step S111 shown in FIG. 29). After reading the first and 0th bits [bit 1-0] of the first random number initial setting data (KRSS1) from the ROM 105, it may be executed as the process of step S112). The operation may be indirectly controlled. When the CPU 104 sets control data in the initial value change control register, for example, when the random number generation circuit 173A outputs the random number loop signal RIJ1 in the random number circuit 103, the initial value setting circuit 172A uses the initial value change control. By referring to the control data stored in the register and performing an initial value changing operation according to the control data, a start value for the second and subsequent rounds corresponding to the read value in step S242 is generated, and a random number is generated. It can be set in the generation circuit 173A.

  After executing one of the processes of steps S244, S248, and S251, or when it is determined in step S249 that the read value is not “11” (step S249; No), a 12-bit random number start value change flag is set. It is cleared and turned off (step S252). After executing the processing of step S252 or when it is determined in step S241 that the 12-bit random number start value change flag is off (step S241; No), the 16 bits provided in the game control flag setting unit 133 It is determined whether or not the random number start value change flag is on (step S253 in FIG. 35). At this time, if the 16-bit random number start value change flag is off (step S253; No), the random number start value change setting process ends. On the other hand, if the start value change flag for the 16-bit random number is on (step S253; Yes), the setting related to the start value after the second round in the 16-bit random number is read (step S254), and the read value is “01”. Whether or not (step S255). As a specific example of the processing in step S254, setting data related to the start value for the second and subsequent rounds in a predetermined register built in the random number circuit 103 or the CPU 104, or a 16-bit random number stored in a predetermined area of the RAM 106, What is necessary is just the process which CPU104 reads.

  When it is determined in step S255 that the read value is “01” (step S255; Yes), the random number circuit 103 generates a start value (start value after the second round) for generating a 16-bit random number. This is determined based on the ID number which is unique identification information assigned to each control microcomputer 100 (step S256). Here, in the process of step S256, the ID number of the game control microcomputer 100 may be set to the start value for generating a 16-bit random number as it is. Alternatively, a value calculated by executing a predetermined calculation using the ID number of the game control microcomputer 100 may be set as a start value for generating a 16-bit random number. For example, an operation for performing a predetermined scramble process on the ID number of the game control microcomputer 100 or an operation such as addition / subtraction / multiplication / division using the ID number is performed to use the calculated value. That's fine.

  When it is determined in step S255 that the read value is not “01” (step S255; No), it is determined whether or not the read value is “10” (step S257). When it is determined that the read value is “10” (step S257; Yes), the random number circuit 103 stores the start value (start value after the second round) in the RAM 106 for generating a 16-bit random number. A process for determining a value based on the data is executed. That is, the CPU 104 reads the stored value at each address in the RAM 106 (step S258), and sequentially adds the read stored values (step S259). Then, the start value for generating the 16-bit random number is changed to the addition value calculated by the addition process in step S259 (step S260). In the process of step S260, it is determined whether or not the addition value calculated by the addition process in step S259 exceeds the maximum value. If not, the addition value is set as the start value as it is, In such a case, a predetermined value (for example, “1” or the like) that is not more than the maximum value may be reset as the start value.

  When it is determined in step S257 that the read value is not “10” (step S257; No), it is determined whether or not the read value is “11” (step S261). When it is determined that the read value is “11” (step S261; Yes), the stored value at the specified address (specified RAM address) in the RAM 106 is read (step S262), and a start for generating a 16-bit random number is started. The value is changed to the read value in step S262 (step S263). After executing any of the processes of steps S256, S260, and S263, or when it is determined in step S261 that the read value is not “11” (step S261; No), a 16-bit random number start value change flag is set. Clear and turn off (step S264).

  Note that the processes of steps S256, S258 to S260, S262, and S263 may be executed by the initial value setting circuit 172B included in the random number circuit 103. For example, when the CPU 104 determines in step S 255 that the read value is “01”, a predetermined fourth initial value change signal is sent to the random number circuit 103. When the random number circuit 103 receives the fourth initial value change signal from the CPU 104, the initial value setting circuit 172B selects data generated based on the ID number stored in a predetermined register, and generates the selected data as a random number. By setting the circuit 173B or the like, the start value for the second and subsequent cycles for generating a 16-bit random number is set to a value based on the ID number that is unique identification information assigned to each game control microcomputer 100. Set (processing corresponding to step S256). On the other hand, when the CPU 104 determines that the read value is not “01” in step S255 and then determines that the read value is “10” in step S257, the random number circuit 103 receives a predetermined fifth initial value change signal. Send. When the random number circuit 103 receives the fifth initial value change signal from the CPU 104, the initial value setting circuit 172B reads out the stored value at each address of the RAM 106, and adds the obtained stored value sequentially. By setting the random number generation circuit 173B, the start value for the second and subsequent cycles for generating a 16-bit random number is set to a value based on the data stored in the RAM 106 (processing corresponding to steps S258 to S260). When the CPU 104 determines that the read value is not “10” in step S257 and then determines that the read value is “11” in step S261, the random number circuit 103 is supplied with a predetermined sixth initial value change signal. Send. When the random number circuit 103 receives the sixth initial value change signal from the CPU 104, the initial value setting circuit 172B reads the stored value at the designated address in the RAM 106, sets the read stored value in the random number generation circuit 173B, etc. The start value after the second round for generating the bit random number is set to be changed to the read stored value (processing corresponding to steps S262 and S263). Further, the CPU 104 may directly control the operation of the initial value setting circuit 172B to execute processing corresponding to steps S256, S258 to S260, S262, and S263. For example, the initial value may be set inside or outside the random number circuit 103. Control data corresponding to the read value in step S254 is set in a predetermined register provided for change control and which can be referred to by initial value setting circuit 172B (this data setting process is performed in step S133 shown in FIG. 30). After the third and second bits [bit 3-2] of the second random number initial setting data (KRSS2) are read from the ROM 105, the initial value setting circuit 172B may execute the process in step S134. The operation may be indirectly controlled. When the CPU 104 sets control data in the initial value change control register, for example, when the random number generation circuit 173B outputs the random number loop signal RIJ2 in the random number circuit 103, the initial value setting circuit 172B uses the initial value change control. By referring to the control data stored in the register and performing an initial value changing operation according to the control data, a start value for the second and subsequent rounds corresponding to the read value in step S254 is generated, and a random number is generated. It can be set in the generation circuit 173B.

  FIG. 36 is a flowchart showing an example of the random number permutation change setting process executed in step S76 shown in FIG. When the random number permutation change setting process is started, in the game control microcomputer 100, first, for example, the CPU 104 stores the sixth and fifth bits [bits 6-5] of the second random number initial setting data (KRSS2) stored in the ROM 105. ] Is read (step S271), and it is determined whether or not the read value is “10” (step S272).

  When it is determined in step S272 that the read value is “10” (step S272; Yes), it is determined whether or not the 12-bit random number permutation change flag provided in the game control flag setting unit 133 is on. (Step S273). At this time, if the 12-bit random number permutation change flag is on (step S273; Yes), for example, the CPU 104 sets “0” to the 0th bit [bit 0] of the ARSC 175A provided in the random number circuit 103 (step S274). ). At this time, the 12-bit random number permutation flag is cleared and turned off (step S275).

  When it is determined in step S272 that the read value is not “10” (step S272; No), or when it is determined in step S273 that the 12-bit random number permutation flag is off (step S273; No). Alternatively, after executing the process of step S275, for example, the CPU 104 reads the first and 0th bits [bits 1-0] of the second random number initial setting data (KRSS2) stored in the ROM 105 (step S276), It is determined whether or not the read value is “10” (step S277). At this time, if the read value is other than “10” (step S277; No), the random number permutation change setting process is terminated.

  On the other hand, when it is determined in step S277 that the read value is “10” (step S277; Yes), whether or not the 16-bit random number permutation change flag provided in the game control flag setting unit 133 is turned on. Is determined (step S278). At this time, if the 16-bit random number permutation change flag is off (step S278; No), the random number permutation change setting process is terminated. On the other hand, if the 16-bit random number permutation change flag is on (step S278; Yes), for example, the CPU 104 sets “1” to the 0th bit [bit 0] of the BRSC 175B provided in the random number circuit 103 ( Step S279). At this time, the 16-bit random number permutation change flag is cleared and turned off (step S280).

  FIG. 37A is a flowchart showing an example of the prize ball process executed in step S77 shown in FIG. In the prize ball processing shown in FIG. 37A, in the game control microcomputer 100, first, for example, the CPU 104 based on the execution result of the switch processing in step S72 shown in FIG. It is checked whether or not a prize detection signal from each prize opening switch such as the prize opening switches 25A to 25D is ON (step S291). Subsequently, based on the check result in step S291, the count values in the first to third payout number instruction counters and the total prize ball number counter provided in the game control counter setting unit 135 are set (step S292).

  FIG. 37B is an explanatory diagram showing an example of the processing content in step S292. In the process of step S292, it is determined whether or not a winning detection signal from each winning opening switch is in an on state (whether or not it is input). When the winning detection signal from the count switch 24 is on, the value of the first payout number instruction counter provided in the game control counter setting unit 135 is incremented by 1, and the value of the total prize ball number counter is set to 15. to add. In addition, when the winning detection signal from any of the winning opening switches 25A and 25B serving as the left and right sleeve winning opening switches is ON, the value of the second payout number instruction counter provided in the game control counter setting unit 135 is set. 1 is added and 7 is added to the value of the total prize ball counter. The value of the second payout number instruction counter provided in the game control counter setting unit 135 is also used when the winning detection signal from any of the winning opening switches 25C and 25D serving as the left and right winning winning opening switches is ON. 1 is added and 7 is added to the value of the total prize ball counter. Further, when the winning detection signal from the start port switch 22 is in the ON state, the value of the third payout number instruction counter provided in the game control counter setting unit 135 is incremented by 1 and the value of the total winning ball number counter is set. Add 4 After the processing in step S292 is executed, in the game control microcomputer 100, for example, the CPU 104 performs the following step S293 according to the value of the prize ball process flag provided in the game control flag setting unit 133, for example. Each process of S295 is executed.

  The prize ball transmission process in step S293 is executed when the value of the prize ball process flag is “0”. FIG. 38 is a flowchart showing an example of processing executed in step S293 shown in FIG. 37A as the prize ball transmission processing. In the prize ball transmission process shown in FIG. 38, in the game control microcomputer 100, first, for example, the CPU 104 determines whether or not the serial communication error flag provided in the game control flag setting unit 133 is on (step). S401). At this time, if the serial communication error flag is on (step S401; Yes), the prize ball transmission process is terminated as it is.

  When it is determined in step S401 that the serial communication error flag is off (step S401; No), it is determined whether the retransmission flag provided in the game control flag setting unit 133 is on (step). S402). Here, the re-transmission flag is set to the on state when the process of step S436 shown in FIG. 39 to be described later is executed, while it is cleared to the off state when the process of step S423 shown in FIG. 39 is executed. It becomes. When the retransmission flag is OFF in step S402 (step S402; No), the variable N used for checking the value of the first to third payout number instruction counters provided in the game control counter setting unit 135 is set. The value is set to “1” as an initial value (step S403).

  Subsequently, it is determined whether or not the value corresponding to the value of the variable N among the first to third payout number instruction counters is “0” (step S404). For example, when the value of the variable N is “1”, it is determined whether the value of the first payout number instruction counter is “0”, and when the value of the variable N is “2”, the second It is determined whether or not the value of the payout number instruction counter is “0”. When the value of the variable N is “3”, whether or not the value of the third payout number instruction counter is “0”. Determine. When the value of the number-of-payout instruction counter that has been determined in step S404 is “0” (step S404; Yes), it is determined whether the value of the variable N is “3” (step S405). , “3” (step S405; Yes), the prize ball transmission process is terminated. On the other hand, when the value of the variable N is a value other than “3” in step S405 (step S405; No), 1 is added to the value of the variable N (step S406), and the process returns to step S404. .

  When the re-transmission flag is ON in step S402 (step S402; Yes), or when the value of the payout number instruction counter that is the object of determination in step S404 is a value other than “0” (step S404; No), it is determined whether or not the value of the variable N is “1” (step S407). When the value of the variable N is “1” (step S407; Yes), a setting for transmitting the first payout number designation command to the payout control board 15 is performed (step S408). As a specific example, in the process of step S408, the start address of the first payout number designation command setting table stored in the ROM 105 is set as a pointer, and command transmission is performed based on the contents of the first payout number designation command setting table. The trust control data is set in the payout transmission command buffer 192 included in the transmission command buffer of the game control buffer setting unit 136. When the value of the variable N is a value other than “1” in step S407 (step S407; No), it is determined whether or not the value of the variable N is “2” (step S409).

  If the value of the variable N is “2” in step S409 (step S409; Yes), a setting for transmitting the second payout number designation command to the payout control board 15 is performed (step S410). As a specific example, in the process of step S410, the start address of the second payout number designation command setting table stored in the ROM 105 is set as a pointer, and a command is sent based on the contents of the second payout number designation command setting table. The credit control data is set in the payout transmission command buffer 192. If the value of the variable N is not “2” in step S409 (step S409; No), it is determined that the value of the variable N is “3”, and the third payout is made to the payout control board 15. Settings for transmitting the number designation command are performed (step S411). As a specific example, in the process of step S411, the start address of the third payout number designation command setting table stored in the ROM 105 is set as a pointer, and command transmission is performed based on the contents of the third payout number designation command setting table. The credit control data is set in the payout transmission command buffer 192.

  After executing any of the processes of steps S408, S410, and S411, in the game control microcomputer 100, for example, the CPU 104 preliminarily stores a prize ball control timer provided in the game control timer setting unit 134 as an initial value for a prize ball ACK. A predetermined timer initial value is set (step S412). Then, the value of the winning ball process flag is updated to “1” (step S413).

  The prize ball ACK waiting process in step S294 shown in FIG. 37A is executed when the value of the prize ball process flag is “1”. FIG. 39 is a flowchart showing an example of the process executed in step S294 shown in FIG. In the prize ball ACK waiting process shown in FIG. 39, in the game control microcomputer 100, first, for example, the CPU 104 determines whether or not a prize ball ACK reception flag provided in the game control flag setting unit 133 is on. (Step S421).

  When it is determined in step S421 that the prize ball ACK reception flag is on (step S421; Yes), the prize ball ACK reception flag is cleared and turned off (step S422), and the retransmission flag is cleared. To turn it off (step S423). Subsequently, one of the values corresponding to the value of the variable N among the first to third payout number instruction counters is decremented by 1 (step S424), and the command transmission number counter provided in the game control counter setting unit 135 is also subtracted. 1 is added to the command transmission count value which is the value at (step S425).

  After executing the process of step S425, it is determined whether or not the value of the variable N is “1” (step S426). At this time, if the value of the variable N is “1” (step S426; Yes), it is determined that the instruction for paying out 15 prize balls has been completed by transmitting the first payout number designation command. The value of the prize ball number counter is decremented by 15 (step S427). When the value of the variable N is a value other than “1” in step S426 (step S426; No), it is determined whether or not the value of the variable N is “2” (step S428).

  If the value of the variable N is “2” in step S428 (step S428; Yes), it is determined that the instruction for paying out seven prize balls has been completed by transmitting the second payout number designation command. Then, 7 is subtracted from the value of the total prize ball counter (step S429). If the value of the variable N is not “2” in step S428 (step S428; No), the transmission of the third payout number designation command corresponding to the value of the variable N being “3” results in four pieces. It is determined that the instruction for paying out the winning ball has been completed, and 4 is subtracted from the value of the total winning ball counter (step S430).

  After performing any of the processes of steps S427, S429, and S430, settings for transmitting an ACK feedback command to the payout control board 15 are performed (step S431). As a specific example, in the process of step S431, the start address of the ACK feedback command setting table stored in the ROM 105 is set as a pointer, and control data for command transmission is issued based on the contents of the ACK feedback command setting table. Set in the transmission command buffer 192. Subsequent to step S431, for example, the CPU 104 sets a predetermined timer initial value as an initial value for feedback in the prize ball control timer (step S432). Then, the value of the winning ball process flag is updated to “2” (step S433).

  If it is determined in step S421 that the prize ball ACK reception flag is off (step S421; No), the timer value in the prize ball control timer is updated by, for example, subtracting 1 (step S434). Then, it is determined whether or not the award ball ACK waiting time has elapsed by determining whether or not the award ball control timer has timed out due to the update in step S434 (step S435). At this time, if the prize ball ACK waiting time has not elapsed (step S435; No), the prize ball ACK waiting process is terminated. On the other hand, when the winning ball ACK waiting time has elapsed (step S435; Yes), the retransmission flag is set to the on state (step S436), and the value of the winning ball process flag is updated to “0” (step S436). Step S437).

  The prize ball transmission completion process of step S295 shown in FIG. 37A is executed when the value of the prize ball process flag is “2”. FIG. 40 is a flowchart illustrating an example of a process executed in step S295 illustrated in FIG. 37A as the prize ball transmission completion process. In the prize ball transmission completion process shown in FIG. 40, in the game control microcomputer 100, first, for example, the CPU 104 updates the timer value in the prize ball control timer by subtracting 1 (step S441). Subsequently, it is determined whether or not the feedback transmission waiting time has elapsed by determining whether or not the prize ball control timer has timed out due to the update in step S441 (step S442).

  When the feedback transmission waiting time has not elapsed in step S442 (step S442; No), the prize ball transmission completion process is terminated. In contrast, when the feedback transmission waiting time has elapsed (step S442; Yes), the prize ball control timer is initialized (step S443), and the value of the prize ball process flag is updated to “0” (step S444). ).

  FIG. 41 is a flowchart showing an example of the abnormal operation notification setting process executed in step S78 shown in FIG. When the abnormal operation notification setting process is started, the game control microcomputer 100 first turns on the detection signal from the all winning ball detection switch 29 based on the execution result of the switch process in step S72 shown in FIG. It is determined whether it is in a state (step S301).

  When the detection signal from the all winning ball detection switch 29 is on in step S301 (step S301; Yes), 1 is subtracted from the value of the command transmission number counter (step S302). On the other hand, when the detection signal from the all winning ball detection switch 29 is OFF in step S301 (step S301; No), the process of step S302 is skipped. Thereafter, for example, the CPU 104 determines whether or not the value of the command transmission number counter is equal to or greater than a predetermined excessive number of prize balls (eg, “250”) (step S303). When the value of the command transmission count counter is equal to or greater than the award ball excess reference value (step S303; Yes), a setting for transmitting an award ball excess notification command to the effect control board 12 is performed (step S304). As a specific example, in the process of step S304, the head address of the excessively rich prize ball notification command setting table stored in the ROM 105 is set as a pointer, and the command transmission is performed based on the content of the excessively rich ball alarm notification command setting table. The control data is set in the production transmission command buffer. On the other hand, when the value of the command transmission number counter is less than the excessive ball reference value in step S303 (step S303; No), the command ball number counter value is a predetermined prize ball shortage reference value (for example, “0”). ) Is determined (step S305).

  When the value of the command transmission count counter reaches the prize ball shortage reference value in step S305 (step S305; Yes), a setting for sending a prize ball shortage notification command to the effect control board 12 is performed (step S305). S306). As a specific example, in the process of step S306, the head address of the winning ball shortage notification command setting table stored in the ROM 105 is set as a pointer, and based on the content of the winning ball shortage notification command setting table, the command transmission The control data is set in the production transmission command buffer. After executing one of the processes in steps S304 and S306, a predetermined initial count value (for example, “200”) is set in the command transmission number counter (step S307).

  When the value of the command transmission number counter does not reach the winning ball shortage reference value in Step S305 (Step S305; No), after the processing of Step S307 is executed, the detection signal from the full switch 26 is turned on. It is determined whether or not (step S308). If the detection signal from the full tank switch 26 is in the on state in step S308 (step S308; Yes), whether or not the full tank notification flag provided in the game control flag setting unit 133 is on. Is determined (step S309). The full tank notification flag is set to an on state when a process of step S311 described later is executed, and is cleared to an off state when the process of step S314 is executed.

  When the full tank notification flag is on in step S309 (step S309; Yes), it is determined that the notification that the full tank state has already been made is made, and the abnormal operation notification setting process is terminated. On the other hand, when the full tank notification flag is OFF in step S309 (step S309; No), a setting for transmitting a full tank notification start command to the effect control board 12 is performed (step S310). As a specific example, in the process of step S310, the start address of the full tank notification start command setting table stored in the ROM 105 is set as a pointer, and the command transmission is performed based on the content of the full tank notification start command setting table. The control data is set in the production transmission command buffer. When the process of step S310 is executed, the full tank notification flag is set to the on state (step S311).

  When the detection signal from the full tank switch 26 is in the OFF state in step S308 (step S308; No), it is determined whether the full tank notification flag is on (step S312). When the full tank notification flag is off (step S312; No), the abnormal operation notification setting process is terminated. On the other hand, when the full tank notification flag is ON in step S312 (step S312; Yes), a setting for transmitting a full tank notification end command to the effect control board 12 is performed (step S313). As a specific example, in the process of step S313, the start address of the full tank notification end command setting table stored in the ROM 105 is set as a pointer, and the command transmission is performed based on the content of the full tank notification end command setting table. The control data is set in the production transmission command buffer. After executing the process of step S313, the full tank notification flag is cleared and turned off (step S314).

  In the abnormal operation notification setting process, it is determined whether or not the retransmission flag is on. If the retransmission flag is off, it is determined whether or not the payout communication error detection flag is on. You may do it. When either the retransmission flag or the payout communication error detection flag is on, it is determined whether or not a predetermined flag (for example, a payout abnormality notification flag) provided in the game control flag setting unit 133 is on. However, when it is off, a setting for transmitting a predetermined command as a main-side payout abnormality notification start command to the effect control board 12 may be performed. When the setting for transmitting the main-side payout abnormality notification start command is performed, the payout abnormality notification flag provided in the game control flag setting unit 133 is set to the on state. On the other hand, when both the re-transmission flag and the payout communication error detection flag are off, it is determined whether or not the payout abnormality notification flag is on. A setting for transmitting a predetermined command to be a main-side payout abnormality notification end command may be performed. On the side of the effect control board 12, in response to receiving the main side payout abnormality notification start command from the main board 11, for example, by displaying a predetermined image on the image display device 5, on the main board 11 side. While processing for performing main-side payout abnormality notification for notifying that an error relating to payout control has occurred is executed, the main-side payout is performed in response to reception of a main-side payout abnormality notification end command from the main board 11 What is necessary is just to make it perform the process for complete | finishing abnormality alert | report.

  FIG. 42 is a flowchart illustrating an example of the main-side reception process executed in step S79 illustrated in FIG. When the main-side reception process is started, in the game control microcomputer 100, for example, the CPU 104 first determines whether or not the payout communication error detection flag is on (step S331). The payout communication error detection flag may be set to an on state when a process of step S336 described later is executed, and may be cleared to an off state according to an operation of the error release switch 31 or the like. When the payout communication error detection flag is on in step S331 (step S331; Yes), the main-side reception process is terminated as it is. Thus, when an error relating to communication with the payout control board 15 occurs in the main board 11, the receiving control of the payout notification command transmitted from the payout control board 15 is controlled. .

  On the other hand, when the payout communication error detection flag is OFF in step S331 (step S331; No), for example, the value of the command reception number counter provided in the game control counter setting unit 135 by the CPU 104 is other than “0”. It is determined whether or not there is a reception command by determining whether or not there is (step S332). At this time, if it is determined that there is no reception command (step S332; No), the main-side reception process is terminated.

  When it is determined in step S332 that there is a received command (step S332; Yes), the command reception number counter value is set in the received command buffers # 1 to # 12 provided in the payout received command buffer 191. The stored data is read from the corresponding one (step S333), and the value of the command reception number counter is updated by subtracting, for example, the number of stored data read in step S333 (step S334). Subsequently, it is checked whether or not the received command read in step S333 is an appropriate command transmitted from the payout control board 15 (step S335). As a specific example, the exclusive command of the first byte and the second byte of the received command is calculated, and it is determined whether the calculated result is a normal value. It is possible to check whether the command is correct. In this embodiment, since the command transmitted from the payout control board 15 to the main board 11 is configured to be the second byte by reversing the first byte, one byte of the received command. As a result of calculating the exclusive OR of the first and second bytes, if all the bit values are “1”, it can be determined that the received command is an appropriate command.

  As a result of the check in step S335, when it is determined that the received command is not an appropriate command (step S335; No), the payout communication error detection flag is set to the on state (step S336), and the main-side reception process is performed. finish. On the other hand, when it is determined as a result of the check in step S335 that the received command is an appropriate command (step S335; Yes), it is determined whether or not the received command is a prize ball ACK command (step S335). S337). When the received command is a prize ball ACK command (step S337; Yes), the prize ball ACK reception flag is set to an on state (step S338).

  On the other hand, when it is determined in step S337 that the received command is not the prize ball ACK command (step S337; No), it is determined whether or not the received command is a payout error notification command (step S339). When the received command is a payout error notification command (step S339; Yes), the payout error notification flag is set to an on state (step S340). When it is determined in step S339 that the received command is not a payout error notification command (step S339; No), it is determined whether or not the received command is a payout error cancel command (step S341). When the received command is a payout error cancel command (step S341; Yes), the payout error cancel flag is set to an on state (step S342). When it is determined in step S341 that the received command is not a payout error cancel command (step S341; No), the command reception flag corresponding to the type of the received command may be set to an on state (step S343).

  FIG. 43 is a flowchart showing an example of the special symbol process executed in step S80 shown in FIG. When the special symbol process is started, in the game control microcomputer 100, first, for example, the CPU 104 determines that the start winning signal from the start port switch 22 is turned on based on the execution result of the switch process in step S72 shown in FIG. It is determined whether or not (step S351). Here, in the process of step S351, for example, a timer value in a start port switch timer for measuring a period during which the start winning signal from the start port switch 22 is in an on state is loaded, and the loaded timer value is set to a predetermined value. It is compared with a switch-on determination value (for example, “2”). Here, the switch-on determination value may be determined in advance corresponding to the number of executions of the game control timer interrupt process shown in FIG. 41 (for example, “2”). Accordingly, whether or not the start winning signal from the start port switch 22 is continuously on during a period (for example, 4 milliseconds) in which a predetermined number (for example, two times) of game control timer interrupt processing is executed. Can be determined. As described above, the switch-on determination value is a period (3) required for the output signal to rise from the low level to the high level after the timer circuit 179 included in the random number circuit 103 starts measuring the input time of the start winning signal SS. It is only necessary to be determined so that it can be determined that the start winning signal is on for a period longer than (millisecond). In the process of step S351, when the loaded timer value has reached the switch-on determination value, it may be determined that the start winning signal is on.

  When it is determined in step S351 that the start winning signal is in the ON state (step S351; Yes), a predetermined winning process is executed to extract numerical data indicating a random value for jackpot determination. This is performed (step S352). On the other hand, when it is determined in step S351 that the start winning signal is in the OFF state (step S351; No), the winning process in step S352 is skipped.

  In the winning process of step S352, the reserved storage number, which is the number of numerical data indicating the random value for jackpot determination stored in the special figure storage unit 131, becomes a predetermined upper limit value (eg, “4”). It is determined whether or not. At this time, if the number of stored memories is the upper limit value, the start detection by the current winning is invalidated, and the winning process is ended as it is. On the other hand, when the reserved storage number is less than the upper limit value, for example, the CPU 104 extracts numerical data indicating a random number value for jackpot determination from the random value register 181B provided for the 16-bit random number in the random number circuit 103 or the like. The numerical data indicating the extracted random number value is set at the head of the empty entry in the special figure storage unit 131.

  Thereafter, in the game control microcomputer 100, for example, the CPU 104 executes the following steps S360 to S366 according to the value of the special symbol process flag provided in the game control flag setting unit 133.

  The special symbol normal process in step S360 is executed when the value of the special symbol process flag is “0”. FIG. 45 is a flowchart showing an example of the special symbol normal process executed in step S340. When the special symbol normal process is started, the game control microcomputer 100 first determines, for example, whether or not the number of reserved memories in the special figure storage unit 131 is “0” (step S461). . Then, when the number of reserved storage is “0” (step S461; Yes), it is determined whether or not the demonstration display flag provided in the game control flag setting unit 133 is on (step S462). The demonstration display flag is set to an on state when a process of step S465 described later is executed, and is cleared to an off state when the process of step S466 is executed. If the demonstration display flag is on in step S462 (step S462; Yes), it is determined that the demonstration display command has already been transmitted to the effect control board 12, and the special symbol normal process is terminated.

  When the demonstration display flag is off in step S462 (step S462; No), it is determined whether or not the touch sensor detection signal from the touch sensor 75 is on (step S463). At this time, if the touch sensor detection signal is in the on state (step S463; Yes), it is determined that the demo display on the image display device 5 is not performed because the player touches the operation knob 30 and plays the game. The special symbol normal processing is terminated. On the other hand, when the touch sensor detection signal is in the OFF state in step S463 (step S463; No), setting for transmitting a demonstration display command to the effect control board 12 is performed (step S464). As a specific example, in the process of step S464, the start address of the demo display command setting table stored in the ROM 105 is set as a pointer, and control data for command transmission is set based on the contents of the demo display command setting table. Set in the production send command buffer. When the process of step S464 is executed, the demonstration display flag is set to the on state (step S465).

  If the number of stored storage is other than “0” in step S461 (step S461; No), it is determined that the start condition for executing the special game is satisfied, and the demonstration display flag is cleared and turned off. A state is set (step S466). Then, the value of the special symbol process flag is updated to “1” (step S467).

  The variable display start process in step S361 shown in FIG. 43 is executed when the value of the special symbol process flag is “1”. The variable display start process includes a process for determining a confirmed special symbol in the special symbol game by the special symbol display device 4, a variable symbol display time (total variation time) for the special symbol, and a variable symbol display mode for the decorative symbol on the image display device 5. It includes the process of determining. As a specific example, in the variable display start process in step S361, first, numerical data indicating the jackpot determination random number value stored in correspondence with the holding number “1” is read from the special figure holding storage unit 131. At the same time, the numerical data indicating the random number values stored in the entries lower than the holding number “1” (for example, the entries corresponding to the holding numbers “2” to “4”) are shifted up by one entry.

  Based on the numerical data indicating the random number value read from the special figure storage unit 131 in this way, for example, by referring to the big hit determination table stored in the ROM 105, the display result in the special display game or variable display of the decorative symbols is a big hit. It is determined whether or not. At this time, if it is determined that a big hit is made, the big hit flag provided in the game control flag setting unit 133 is set to an on state, and numerical data indicating a random number value for probability change determination is extracted. Subsequently, based on the extracted numerical data indicating the probability change determination random number value, for example, by referring to a probability change determination table stored in the ROM 105, the gaming state after the end of the big hit gaming state is high probability by probability change control. It is determined whether or not to enter a state. Then, when it is determined that the high probability state is set, the probability variation confirmation flag provided in the game control flag setting unit 133 is set to the on state. In the variable display start process in step S361, for example, the special symbol display device 4 is set to start variable symbol variable display in the special symbol display device 4, such as starting the lighting / extinguishing operation of each segment or each dot in the special symbol display device 4. I do. Thereafter, the value of the special symbol process flag is updated to “2”.

  The variable display control process of step S362 is executed when the value of the special symbol process flag is “2”. This variable display control process includes a process of measuring the remaining variable display time of the special symbol in the special symbol game by the special symbol display device 4 based on the value of the variable display time timer. When the special symbol variable display time (total variation time) has elapsed, the value of the special symbol process flag is updated to “3”.

  The variable display stop process in step S363 is executed when the value of the special symbol process flag is “3”. In the variable display stop process, it is determined whether the variable display result of the special symbol or the decorative symbol is a big hit or a loss. Further, when the pachinko gaming machine 1 is in a high probability state, it is determined whether or not the gaming state is returned from the high probability state to the normal gaming state, and if it is determined to return, the gaming state in the pachinko gaming machine 1 has a high probability. Transition from state to normal gaming state. As a specific example, when the number of special figure games executed in the high probability state reaches a predetermined probability variation end reference value (for example, “100”), it is determined to return from the high probability state to the normal game state. When the variable display result is a big hit, the value of the special symbol process flag is updated to “4”, while when the variable display result is lost, the value of the special symbol process flag is updated to “0”.

  The pre-opening process for the special winning opening in step S364 is executed when the value of the special symbol process flag is “4”. In the pre-opening process for the big winning opening, setting of the longest opening period of the big winning opening in each round in which the big winning opening is opened by the opening / closing plate provided in the special variable winning ball apparatus 7 in the big hit gaming state is performed. Thereafter, a setting for transmitting a big hit start command to the effect control board 12 is performed, and the value of the special symbol process flag is updated to “5”.

  The special winning opening opening process in step S365 is executed when the value of the special symbol process flag is “5”. In this special prize opening opening process, the solenoid 82 is driven and controlled according to the setting in the special prize opening pre-processing, thereby opening and closing the special prize opening by the opening / closing plate of the special variable winning ball apparatus 7. When the final round in the big hit gaming state is completed, the value of the special symbol process flag is updated to “6”. The big hit end process of step S366 is executed when the value of the special symbol process flag is “6”. In this jackpot end process, after setting for transmitting a jackpot end command to the effect control board 12, the value of the special symbol process flag is updated to “0”. In the big hit end process, it is determined whether or not the probability change confirmation flag is on. When the probability change confirmation flag is on, the probability change confirmation flag is cleared and turned off, and the game control flag setting unit 133 is provided. Set the probable change flag to ON.

  FIG. 45 is a flowchart showing an example of a payout command control process executed in step S81 shown in FIG. When the payout command control process is started, the game control microcomputer 100 first determines whether or not the elapsed time is measured by a payout communication control timer provided in the game control timer setting unit 134 (timer Whether or not the value is other than “0”) is determined, for example, to determine whether or not the completion of the transmission of the payout control command is on standby (step S371). When it is determined in step S371 that transmission is not waiting (step S371; No), for example, the value of the command transmission waiting counter provided in the game control counter setting unit 135 by the CPU 104 is other than “0”. It is determined whether or not there is a transmission command by determining whether or not there is (step S372). At this time, if it is determined that there is no transmission command (step S372; No), the payout command control process is terminated.

  When it is determined in step S372 that there is a transmission command (step S372; Yes), for example, by determining whether or not the serial communication error flag is OFF, the payout control command is issued by the serial communication circuit 108. It is determined whether or not transmission is possible (step S373). At this time, if it is determined that the transmission is not possible because the serial communication error flag is on (step S373; No), the payout command control process is terminated and the payout control command is not transmitted. . On the other hand, when it is determined in step S373 that transmission is possible (step S373; Yes), command transmission waiting is performed among the transmission command buffers # 1 to # 12 provided in the payout transmission command buffer 192. The stored data is read from the one corresponding to the counter value (step S374), and the read data is set in the serial communication circuit 108 (step S375). More specifically, in step S375, the data read in step S374 may be set in the serial communication data register included in the serial communication circuit 108. At this time, the value of the command transmission waiting counter is updated by subtracting, for example, the number of stored data read in step S374 (step S376). Subsequently, a predetermined timer initial value is set as a transmission completion waiting initial value in the payout communication control timer (step S377), and the payout command control process is terminated.

  Further, when it is determined in step S371 that transmission is in a standby state (step S371; Yes), for example, a predetermined flag provided in the game control flag setting unit 133 is turned on as a transmission completion flag. It is determined whether or not the transmission operation by the serial communication circuit 108 has been completed (step S378). When the transmission operation is completed in step S378 (step S378; Yes), the payout communication control timer is initialized (step S379), and then the process proceeds to the above-described step S372.

  When the transmission operation is not completed in step S378 (step S378; No), the value of the payout communication control timer is updated by subtracting, for example, 1 (step S380). Then, for example, it is determined whether or not the transmission completion waiting time has elapsed by determining whether or not the payout communication control timer has timed out due to the update in step S380 (step S381). At this time, if the transmission completion waiting time has elapsed (step S381; Yes), it is determined that transmission of the payout control command to the payout control board 15 could not be completed within the transmission completion waiting time, for example, a payout communication error. Processing at the time of command transmission error, such as processing for setting the detection flag to the ON state, is executed (step S382). On the other hand, if the transmission completion waiting time has not elapsed in step S381 (step S381; No), the process of step S382 is skipped and the payout command control process is terminated.

  Next, the operation in the payout control board 15 will be described. In the payout control board 15, the payout control microcomputer 150 is activated in response to the start of power supply from the power supply board 10 and the reset signal to the payout control microcomputer 150 becoming high level (off state). A payout control main process as shown in the flowchart of FIG. 46 is executed. Note that each process described below is executed by the CPU 214 provided in the payout control microcomputer 150. An interrupt request based on various interrupt factors generated by the timer circuit 217, serial communication circuit 218, etc. provided in the payout control microcomputer 210 is for causing the CPU 214 to execute predetermined interrupt processing. The concept including the CPU 214 and various circuits other than the CPU 214 is sometimes referred to as a payout control microcomputer 150. When the payout control main process shown in FIG. 46 is started, the payout control microcomputer 150 first sets the interrupt prohibition (step S501) and sets the interrupt mode (step S502). Subsequently, settings related to the stack pointer, such as setting of a stack pointer designation address, are performed (step S503). In addition, the built-in device register is set (initialized) (step S504). For example, when the payout control microcomputer 150 has a built-in CTC (counter / timer) and PIO (parallel input / output port), the processing in step S504 is executed, whereby a built-in device (built-in peripheral circuit). CTC or PIO setting (initialization) or the like may be performed.

  After executing the process of step S504, it is determined whether or not the power-off signal is in an off state by checking the state of a predetermined bit at an input port provided in the payout control microcomputer 150, for example. (Step S505). For example, in the process of step S505, it is confirmed that the power-off signal is not output and is in an off state (high level).

  When the power cut-off signal is on in step S505 (step S505; No), after waiting for a predetermined time (for example, 0.1 second) to elapse (step S506), the process returns to step S505, and the power It is determined again whether or not the disconnection signal is off. Thereby, the payout control microcomputer 150 can confirm that the power supply voltage is stable. If the power-off signal is off in step S505 (step S505; Yes), the RAM 216 is set to be accessible (step S507).

  After executing the processing of step S507, it is determined whether or not the clear signal is in an ON state by checking the state of a predetermined bit at an input port provided in the payout control microcomputer 150, for example (step S507). Step S508). Here, the payout control microcomputer 150 may confirm the state of the clear signal only once through the input port, but may confirm the state of the clear signal a plurality of times. For example, once it is confirmed that the state of the clear signal is off, the state of the clear signal is confirmed once again after a predetermined time (for example, 0.1 second) has elapsed. At this time, if the clear signal is off, it is determined that the clear signal is off. On the other hand, if the state of the clear signal is on at this time, the state of the clear signal may be confirmed again after a predetermined time has elapsed. Note that the number of times of reconfirming the state of the clear signal may be one time or may be a plurality of times. Further, it is possible to check twice and check again when the check results do not match.

  When it is determined in step S508 that the clear signal is in the OFF state (step S508; No), the data in the RAM 216 is checked to determine whether the check result is normal (step S509). In the process of step S509, for example, a checksum is calculated using data stored in a specific area of the RAM 216, and the calculated checksum is compared with the checksum stored in the payout checksum buffer. Here, the payout checksum buffer stores a checksum calculated by the same processing when the power supply was stopped last time. If the comparison results do not match, the data in the specific area of the RAM 216 is different from the data at the time of stopping the power supply, and therefore it is determined that the check result is not normal.

  When the check result in step S509 is normal (step S509; Yes), it is determined whether or not the payout backup flag provided in the payout control flag setting unit 141 is on (step S510). The state of the payout backup flag is set in the payout control flag setting unit 141 when the power supply is stopped. Then, the place where the payout backup flag is set is backed up by the backup power source, so that the state of the payout backup flag is saved even when the power supply is stopped. Whether the payout backup flag is turned on as in step S510 is determined before the check result is checked as in step S509. When the payout backup flag is on, the data check of the RAM 216 is performed. You may make it determine whether a result is normal.

  If the payout backup flag is on in step S510 (step S510; Yes), the payout backup flag is cleared and turned off (step S511), and then the internal power supply of the payout control microcomputer 150 is supplied. Settings at the time of recovery for returning to the state when stopped are performed (step S512). For example, when the power supply to the pachinko gaming machine 1 is stopped, if the value of the award ball non-payout counter provided in the payout control counter setting unit 143 is stored in the backup area of the RAM 216, the process of step S512 In the processing, the stored data in the backup area of the RAM 216 may be read out and set in the winning ball unpaid counter.

  Further, when the clear signal is on in step S508 (step S508; Yes), when the check result is not normal in step S509 (step S509; No), or in step S510, the payout backup flag is off. If there is (step S510; No), the RAM 216 is initialized (step S513). Subsequently, a setting at the time of initialization for setting the internal state of the payout control microcomputer 150 to an initial state is performed (step S514). For example, in the process of step S 514, various flags provided in the payout control flag setting unit 141, various timers provided in the payout control timer setting unit 142, or various types provided in the payout control counter setting unit 143. What is necessary is just to set each initial value to a counter etc. As a specific example, in the process of step S514, the value of the initialization command reception number counter provided in the payout control counter setting unit 143 is set to a predetermined count initial value (eg, “1”).

  After executing the processing of step S512 or step S514, for example, by setting a register of the timer circuit 217 included in the payout control microcomputer 150, a timer interrupt is generated every predetermined time (for example, 2 milliseconds). The internal setting of the payout control microcomputer 150 is performed (step S515). Thereafter, the CPU 214 reads the fourth and third bits [bit 4-3] of the first random number initial setting data (KRSS1) stored in the ROM 215 (step S516), and performs random number generation operation based on the read value. Initial setting is performed (step S517). For example, when the random number circuit 213 included in the payout control microcomputer 150 is not used on the payout control board 15 side, both the 12-bit random number and the 16-bit random number in the random number circuit 213 are generated in the process of step S517. It is only necessary to execute a process for stopping the operation.

  Subsequent to the process in step S517, the CPU 214 executes a serial communication initial setting process as a process for performing an initial setting of the serial communication operation (step S518). The serial communication initial setting process may be the same process as the process of step S23 shown in FIG. 27 executed by the game control microcomputer 100 on the main board 11 side. Further, the CPU 214 executes an interrupt initial setting process as a process for performing an initial setting related to the interrupt process executed based on the interrupt request (step S519). This interrupt initial setting process may be a process similar to the process of step S24 shown in FIG. 27 executed by the game control microcomputer 100 on the main board 11 side. Then, the CPU 214 sets the interrupt permitted state (step S520), and waits for various interrupts to occur. At this time, it is determined whether or not the power-off signal has been turned on (whether or not it has been output) (step S521). If it is off (step S521; No), the generation of various interrupts is awaited. When the power-off signal is turned on (step S521; Yes), the payout-side power cut-off process is executed (step S522), and then a predetermined loop process is executed for the payout control by stopping the power supply. Wait until the microcomputer 150 stops operating. In the process of step S521, the state of the power-off signal may be confirmed only once via the input port, but the state of the power-off signal may be confirmed a plurality of times. For example, if it is confirmed once that the power-off signal is in the OFF state, the power-off signal is confirmed once again after a predetermined time (for example, 0.1 second) has elapsed. At this time, if the power-off signal is off, it is determined that the power-off signal is off. On the other hand, if the state of the power-off signal is on at this time, the state of the power-off signal may be confirmed again after a predetermined time has elapsed. In addition, the number of times of reconfirming the state of the power-off signal may be one time or a plurality of times. Further, it is possible to check twice and check again when the check results do not match. Thus, when confirming the state of the power-off signal multiple times, for example, when the confirmation operation is started or when the first confirmation result is compared with the second confirmation result and there is a mismatch, etc. Retriggering is performed to clear the WDT (watchdog timer) built in the control microcomputer 150. When the retrigger does not occur within a predetermined time due to some cause (for example, program runaway), a user reset is generated based on a timeout signal output from the WDT, and the reset / interrupt controller 212, CPU 214, timer circuit After initializing each circuit such as 217 and serial communication circuit 218, execution of the user program may be started from an address indicated by a predetermined vector table to perform automatic recovery.

  In the payout-side power cut-off process in step S522, for example, after the CPU 214 sets the interrupt prohibition, the clear data is set in a predetermined bit of the output port provided in the payout control microcomputer 150. Set to stop the operation. At this time, clear data may be set for an output port to be cleared in addition to a predetermined bit of the output port. Subsequently, for example, check data is created by calculating a checksum using data stored in a specific area of the RAM 216, and the payout backup flag provided in the payout control flag setting unit 141 is set to an on state. . The check data created at this time is stored in a predetermined area of the RAM 216 such as a payout checksum buffer provided in the payout control buffer setting unit 144, for example. The payout control microcomputer 150 then prohibits access to the RAM 216, for example, by setting an access prohibition value in a predetermined RAM access register.

  The payout control microcomputer 150 is adapted to the payout control microcomputer 150 for interrupt processing executed by the game control microcomputer 100 mounted on the main board 11 in response to the interrupt factor generated in the serial communication circuit 218. It is only necessary that the processed process is executed. For example, every time an error interrupt occurs in the serial communication circuit 218 provided in the payout control microcomputer 150, a process predetermined as the serial communication error interrupt process may be executed by the CPU 214. For example, the serial communication error interrupt process executed by the CPU 214 includes, for example, a process for setting the transmission operation unit and the reception operation unit provided in the serial communication circuit 218 to an unused state, and a process for setting the payout control flag setting unit 141. It only needs to include processing for setting the serial communication error flag to the ON state.

  In addition, every time a reception interrupt occurs in the serial communication circuit 218, a process predetermined as the serial reception interrupt process may be executed by the CPU 214. If the serial reception interrupt process executed by the CPU 214 includes a process for storing a command received from the main board 11 in the serial communication circuit 218 in a reception command buffer provided in the payout control buffer setting unit 144. Good. Further, every time a transmission interrupt occurs in the serial communication circuit 218, a process predetermined as a serial transmission interrupt process may be executed by the CPU 214. The serial transmission interrupt process executed by the CPU 214 includes a transmission interrupt such as a process of specifying the type of transmission interrupt generated in the serial communication circuit 218 and setting or clearing a flag according to the specified type of interrupt. It is only necessary to include various types of processing corresponding to the types.

  FIG. 47 is a flowchart showing an example of a payout control timer interrupt process executed each time a timer interrupt occurs in the payout control microcomputer 150. This payout control timer interruption process is a process that becomes a payout control process for controlling the payout motor 51 in accordance with the payout control command transmitted from the main board 11. In the payout control timer interrupt process shown in FIG. 47, the payout control microcomputer 150 executes a predetermined input / output process (step S531), for example, a predetermined bit at an input port provided in the payout control microcomputer 150. Or a predetermined control data is set for a predetermined bit in an output port provided in the payout control microcomputer 150.

  Subsequently, the payout control microcomputer 150 executes prepaid card unit processing and performs communication with the card unit 70 connected via the interface board 20 (step S532). Further, a payout side reception process for receiving the payout control command transmitted from the main board 11 by serial communication is executed (step S533). Then, a prize ball reception confirmation process is performed for performing a setting for transmitting a prize ball ACK command when a payout number designation command from the main board 11 is received (step S534). Further, in accordance with a ball lending request from the card unit 70 or a payout number designation command from the main board 11, a payout operation control process for controlling the payout operation of the game ball is executed (step S535).

  Subsequent to the processing in step S535, the payout control microcomputer 150 performs, for example, a 7-segment display process for performing a predetermined display on the error display LED 74 in accordance with the state of various error flags provided in the payout control flag setting unit 141. Is executed (step S536). Further, a payout side transmission process for transmitting a payout notification command to the main board 11 is executed (step S537). For example, in the payout-side transmission process, it is determined whether or not the serial communication error flag provided in the payout control flag setting unit 141 is on. When the serial communication error flag is on, the serial communication circuit 218 is used to connect to the main board 11. On the other hand, it determines that the payout notification command cannot be transmitted, and ends the payout side transmission process. On the other hand, when the serial communication error flag is off, it is determined whether or not an error flag other than the serial communication error flag provided in the payout control flag setting unit 141 is on. At this time, if any one of the error flags is on, for example, setting control data for command transmission in the transmission command buffer provided in the payout control buffer setting unit 144, the main board 11 is set. Set up to send out a payout error notification command. Thereafter, it is determined whether or not a command to be transmitted is stored in the transmission command buffer. When the command is stored, the stored data corresponding to the command is read and the serial communication data provided in the serial communication circuit 218 is read. Set to register. At this time, by checking the transmission setting enable flag and the transmission completion flag provided in the payout control flag setting unit 141, it is determined whether the data set is possible, whether the command transmission is completed, etc. May be performed.

  Thereafter, the payout control microcomputer 150 executes a payout side error canceling process to enable a predetermined error to be canceled when the detection signal from the error canceling switch 73 is turned on (step S538). The payout control timer interrupt process is terminated. In the payout side error canceling process in step S538, for example, the CPU 214 determines whether or not the detection signal from the error canceling switch 73 is on based on the execution result of the input / output process in step S531. At this time, if the detection signal from the error release switch 73 is in the on state, for example, it is determined whether or not the main board communication error flag is on. If the main board communication error flag is on, the main board communication error flag is cleared and turned off. Further, when the detection signal from the error release switch 73 is on, it is determined whether or not the serial communication error flag is on. If it is on, a predetermined serial communication initial setting process is executed. Thus, the serial communication circuit 218 may be initialized. The serial communication initial setting process executed at this time may be a process in which, for example, the serial communication initial setting process executed in step S23 shown in FIG. 27 is adapted to the payout control microcomputer 150. When serial communication initial setting processing is executed, the serial communication error flag is cleared and turned off. Further, when the detection signal from the error cancel switch 73 is in the on state, it is determined whether or not any other error that can be canceled has occurred, and if it has occurred, a setting for canceling the error is made. It may be broken. As a specific example, it is determined whether or not a predetermined error flag such as a ball biting error flag, a ball clogging error flag, or an empty error flag is on, and any of the error flags may be on. For example, it is determined that an error that can be canceled by operating the error cancellation switch 73 has occurred. In this case, for example, a setting for canceling the generated error may be performed, such as clearing a corresponding error flag or performing drive control of the payout motor 51.

  FIG. 48 is a flowchart showing an example of the payout side reception process executed in step S533 shown in FIG. When the payout side reception process is started, the payout control microcomputer 150 first determines, for example, whether the main board communication error flag is on (step S601). When the main board communication error flag is on in step S601 (step S601; Yes), the payout side reception process is terminated as it is. Accordingly, when an error relating to communication with the main board 11 occurs in the payout control board 15, the receiving control command transmitted from the main board 11 is controlled to be stopped.

  On the other hand, when the main board communication error flag is OFF in step S601 (step S601; No), for example, whether the value of the command reception number counter provided in the payout control counter setting unit 143 is other than “0” or not. The CPU 214 determines whether or not there is a received command (step S602). At this time, if it is determined that there is no reception command (step S602; No), the payout side reception process is terminated.

  When it is determined in step S602 that there is a received command (step S602; Yes), the received command buffers provided in the payout control buffer setting unit 144 are stored from the one corresponding to the value of the command reception number counter. Data is read (step S603), and the value of the command reception number counter is updated by subtracting, for example, the number of stored data read in step S603 (step S604). Subsequently, it is checked whether or not the received command read in step S603 is an appropriate command transmitted from the main board 11 (step S605). As a specific example, the exclusive command of the first byte and the second byte of the received command is calculated, and it is determined whether the calculated result is a normal value. It is possible to check whether the command is correct. In this embodiment, since the command transmitted from the main board 11 to the payout control board 15 is configured to be the second byte by inverting the first byte, one byte of the received command. As a result of calculating the exclusive OR of the first and second bytes, if all the bit values are “1”, it can be determined that the received command is an appropriate command.

  As a result of the check in step S605, when it is determined that the received command is not an appropriate command (step S605; No), the main board communication error flag is set to the on state (step S606), and the payout side receiving process is terminated. To do. On the other hand, when it is determined that the received command is an appropriate command as a result of the check in step S605 (step S605; Yes), it is determined whether or not the received command is a payout number designation command (step S605). S607). If the received command is a payout number designation command (step S607; Yes), the award ball payout number designated by the command is added to the value of the prize ball unpaid counter and stored (step S608). As a result, the number of game media payouts indicated in the payout number designation command is cumulatively stored in the award ball non-payout counter. When the processing of step S608 is executed, the prize ball ACK transmission flag provided in the payout control flag setting unit 141 is set to an on state (step S609), and the number of payout operation failures provided in the payout control counter setting unit 143 is set. A predetermined initial count value (eg, “0”) is set in the counter (step S610).

  If it is determined in step S607 that the received command is not a payout number designation command (step S607; No), it is determined whether the received command is an ACK feedback command (step S611). When the received command is an ACK feedback command (step S611; Yes), the feedback reception flag provided in the payout control flag setting unit 141 is set to an on state (step S612). When it is determined in step S611 that the received command is not an ACK feedback command (step S611; No), a command reception flag corresponding to the type of the received command may be set to an on state (step S613).

  FIG. 49 is a flowchart showing an example of the winning ball reception confirmation process executed in step S534 shown in FIG. When the winning ball reception confirmation process is started, for example, the CPU 214 determines whether or not the main board communication error flag is turned on in the payout control microcomputer 150 (step S631). When the main board communication error flag is ON in step S631 (step S631; Yes), the prize ball reception confirmation process is ended as it is.

  On the other hand, when the main board communication error flag is off in step S631 (step S631; No), it is determined whether or not the reception confirmation flag provided in the payout control flag setting unit 141 is on (step). S632). Here, the reception confirmation in progress flag is set to the on state when the process of step S637 described later is executed, and is cleared to the off state when any of the processes of steps S641 and S646 is executed. Become.

  When the reception confirmation flag is off in step S632 (step S632; No), it is determined whether or not the prize ball ACK transmission flag is on (step S633). When the prize ball ACK transmission flag is OFF in step S633 (step S633; No), the prize ball reception confirmation process is terminated. On the other hand, when the prize ball ACK transmission flag is ON in step S633 (step S633; Yes), a setting for transmitting a prize ball ACK command to the main board 11 is performed (step S634). As a specific example, in the process of step S634, the start address of the prize ball ACK command setting table stored in the ROM 215 is set as a pointer, and control for command transmission is performed based on the contents of the prize ball ACK command setting table. Data is set in a transmission command buffer provided in the payout control buffer setting unit 144. When the process of step S634 is executed, a timer initial value set in advance as a feedback standby initial value is set in the communication control timer provided in the payout control timer setting unit 142 (step S635). At this time, the winning ball ACK transmission flag is cleared and turned off (step S636), and the reception confirmation flag is set on (step S637).

  If the reception confirmation flag is on in step S632 (step S632; Yes), it is determined whether the feedback reception flag is on (step S638). When the feedback reception flag is on (step S638; Yes), the feedback reception flag is cleared and turned off (step S639), the communication control timer is initialized (step S640), and the reception confirmation flag is set. Clear and turn off (step S641).

  When the feedback reception flag is OFF in step S638 (step S638; No), the value of the communication control timer is updated by, for example, subtracting 1 (step S642). Then, for example, it is determined whether or not the feedback waiting time has elapsed by determining whether or not the communication control timer has timed out due to the update in step S642 (step S643). At this time, if the feedback waiting time has not elapsed (step S643; No), the winning ball reception confirmation process is terminated. On the other hand, when the feedback standby time has elapsed in step S643 (step S643; Yes), the main board communication error flag is set to the on state (step S644), and the payout number designation command received from the main board 11 is received. It is determined that it is invalid, and the number of payouts indicated by the payout number designation command is subtracted from the winning ball non-payout counter (step S645). That is, in the process of step S645, the number of payouts added to the value of the prize ball unpaid counter in step S608 shown in FIG. 48 is subtracted from the value of the prize ball unpaid counter and stored. At this time, the reception confirmation flag is cleared and turned off (step S646).

  FIG. 50 is a flowchart showing an example of the payout operation control process executed in step S535 shown in FIG. When the payout operation control process shown in FIG. 50 is started, the payout control microcomputer 150 first, for example, the payout number storage abnormality for the CPU 214 to determine whether or not an abnormality has occurred in the memory regarding the number of unpaid prize balls. A determination process is executed (step S661). After executing the payout number storage abnormality determination process in step S661, the processes in steps S662 to S664 as shown in FIG. 50 are performed according to the value of the payout control process flag provided in the payout control flag setting unit 141. Execute. Here, the payout control normal process in step S662 is executed when the value of the payout control process flag is “0”. The prize ball payout operation processing in step S663 is executed when the value of the payout control process flag is “1”. The ball lending payout operation process in step S664 is executed when the value of the payout control process flag is “2”.

  FIG. 51 is a flowchart showing an example of the payout amount storage abnormality determination process executed in step S661 shown in FIG. In this payout number storage abnormality determination process, first, an increment in the count value stored in the prize ball non-payout counter is specified (step S701). For example, in the process of step S701, the increment in the count value can be specified by taking the difference between the value of the previous unpaid counter and the value of the prize ball unpaid counter.

  Subsequently, it is determined whether or not the increment of the count value specified in step S701 is equal to or less than a predetermined prize ball increase upper limit (step S702). In this embodiment, the maximum value of the number of payouts specified by the payout control command transmitted from the main board 11 to the payout control board 15 is specified by the first payout number specifying command shown in FIG. “15”. When it is determined by the payout control microcomputer 150 that there has been a timer interruption, the payout side reception process in step S533 shown in FIG. 47 is executed once. On the other hand, the value of the previous unpaid counter is set to the same value as the value of the unpaid prize ball counter when the process of step S815 shown in FIG. 54 described later or the process of step S845 shown in FIG. 56 is executed. Is done. Therefore, when it is determined in step S702 that the increment of the count value exceeds a predetermined value that is predetermined as the award ball increase upper limit (step S702; No), the count value in the award ball unpaid counter abnormally increases. Therefore, it is determined that the value is invalid, the prize ball unpaid counter is cleared, and the count value is initialized (step S703). Alternatively, in the process of step S703, only the portion corresponding to the abnormally increased count value may be invalidated, for example, by setting the value of the previously unpaid counter in the prize ball unpaid counter. In this case, for example, when an error occurs in the data stored in the award ball unpaid counter, it is possible to prevent the player from being disadvantaged by invalidating the number of unpaid game balls more than necessary.

  When the increment of the count value is less than or equal to the upper limit value of the prize ball in step S702 (step S702; Yes), the increment in the count value stored in the ball lending unpaid counter provided in the payout control counter setting unit 143 Minutes are specified (step S704). Then, it is determined whether or not the increment of the count value specified in step S704 is equal to or less than a predetermined ball lending increase upper limit (eg, “25”) (step S705). At this time, if the increment of the count value exceeds the ball lending increase upper limit (step S705; No), it is determined that the value is invalid because the count value in the ball lending unpaid counter has increased abnormally. The ball lending unpaid counter is cleared and the count value is initialized (step S706).

  When the increment of the count value is equal to or less than the ball lending increase upper limit value in step S705 (step S705; Yes), or after executing any one of steps S703 and S706, the value of the winning ball unpaid counter is It is determined whether or not it is less than a predetermined large amount unpaid upper limit value (eg, “50”) (step S707). At this time, if it is determined that it is less than the large amount unpaid upper limit (step S707; Yes), the large amount unpaid error flag provided in the payout control flag setting unit 141 is cleared and turned off (step S708). . On the other hand, when it is not less than the large amount unpaid upper limit (step S707; No), the large amount unpaid error flag is set to the on state (step S709).

  FIG. 52 is a flowchart showing an example of the payout control normal process executed in step S662 shown in FIG. When this payout control normal process is started, in the payout control microcomputer 150, for example, the CPU 214 first determines whether or not the main board communication error flag is on (step S721). When the main board communication error flag is on in step S721 (step S721; Yes), the payout control normal process is terminated as it is. As a result, when an error relating to communication with the main board 11 occurs in the payout control board 15, the payout control of the game ball that becomes a prize ball or a rental ball is controlled to stop. .

  On the other hand, when the main board communication error flag is OFF in step S721 (step S721; No), it is determined whether or not the value of the winning ball unpaid counter is a value other than “0” (step S722). . At this time, if the value of the award ball unpaid counter is a value other than “0” (step S722; Yes), for example, it is determined whether or not a predetermined command (for example, a ball break notification command) from the main board 11 has been received. By checking or the like, it is determined whether or not the ball is in a broken state (step S723). When the ball is out of play (step S723; Yes), the payout control normal process is terminated. On the other hand, if the ball is not out of state in step S723 (step S723; No), the value of the payout control process flag is updated to “1” which is a value corresponding to the prize ball payout operation process (step S723). S724).

  Further, when the value of the winning ball non-payout counter is “0” in step S722 (step S722; No), it is determined whether or not the BRDY signal transmitted from the card unit 70 is in an on state (step S722). S725). At this time, if the BRDY signal is in an OFF state (step S725; No), the payout control normal process is terminated. On the other hand, when the BRDY signal is in the on state in step S725 (step S725; Yes), it is determined whether or not the ball lending request signal (BRQ signal) transmitted from the card unit 70 is in the on state. (Step S726). When the ball lending request signal is in the off state (step S726; No), the payout control normal process is terminated.

  When the ball lending request signal is on in step S726 (step S726; Yes), for example, whether a predetermined command (for example, a ball break notification command) from the main board 11 has been received or the payout control flag setting unit 141 It is determined whether or not it is possible to lend the ball, for example, by checking a card unit unconnected error flag provided in (Step S727). When it is determined that the ball lending is not possible due to, for example, receiving a ball-out notification command or because the card unit unconnected error flag is on (step S727; No), payout control is performed. Normal processing ends. On the other hand, when it is possible to lend a ball in step S727 (step S727; Yes), a count initial value (for example, “25”) determined in advance as a ball lending initial value in the ball lending unpaid counter. ) Is set (step S728). Then, the value of the payout control process flag is updated to “2” which is a value corresponding to the ball lending payout operation process (step S729).

  FIG. 53 is a flowchart showing an example of a prize ball payout operation process executed in step S663 shown in FIG. When the winning ball payout operation process is started, in the payout control microcomputer 150, first, for example, the CPU 214 detects that the detection signal from the payout count switch 72 is in the ON state based on the execution result of the input / output process in step S531 shown in FIG. It is determined whether or not (step S741). When the detection signal from the payout count switch 72 is on (step S741; Yes), the value of the payout number counter provided in the payout control counter setting unit 143 is incremented by 1 (step S742). On the other hand, when the detection signal from the payout count switch 72 is OFF in step S741 (step S741; No), the process of step S742 is skipped. Thereafter, according to the value of the prize ball payout operation process flag provided in the payout control flag setting unit 141, one of the processes of steps S743 and S744 shown in FIG. 53 is selected and executed. Here, the prize ball payout number calculation process in step S743 is executed when the value of the prize ball payout operation process flag is “0”. The prize ball payout driving process in step S744 is executed when the value of the prize ball payout operation process flag is “1”.

  FIG. 54 is a flowchart showing an example of a prize ball payout number calculation process executed in step S743 shown in FIG. When the winning ball payout number calculation process is started, the payout control microcomputer 150 first determines, for example, whether the main board communication error flag is on (step S801). If the main board communication error flag is ON in step S801 (step S801; Yes), the award ball payout number calculation process is terminated as it is. As a result, when an error relating to communication with the main board 11 occurs in the payout control board 15, the payout control of the game balls that are unpaid prize balls is controlled to stop. .

  On the other hand, when the main board communication error flag is OFF in step S801 (step S801; No), it is determined whether or not the value of the award ball non-payout counter is larger than the value of the payout number counter ( Step S802). Here, when the value of the prize ball non-payout counter is equal to or smaller than the value of the number-of-payout counter in step S802 (step S802; No), it corresponds to the value of the prize ball non-payout counter. It is determined that the game ball payout operation has been completed. At this time, the payout operation failure frequency counter provided in the payout control counter setting unit 143 is cleared to initialize the count value (step S803), and the award ball non-payout counter is cleared to initialize the count value ( Step S804).

  If the value of the award ball non-payout counter is larger than the value of the payout number counter in step S802 (step S802; Yes), the number of game balls counted by the award ball non-payout counter is It is determined that the payout operation has not been completed yet. Therefore, the number of game balls that have not yet been paid out is identified by subtracting the number of payouts that is the value of the payout number counter from the number of payouts that is the value of the award ball unpaid counter (step S805). . Subsequently, the subtraction value as the value specified by the subtraction process in step S805 is set in the payout motor rotation counter provided in the payout control counter setting unit 143 (step S806).

  Following the processing in step S806, it is determined whether or not the value of the payout operation failure frequency counter exceeds a predetermined failure frequency upper limit (eg, “9”) (step S807). At this time, if the upper limit value of the number of failures is exceeded (step S807; Yes), the ball clogging error flag provided in the payout control flag setting unit 141 is set to the on state (step S808), and the payout operation failure frequency counter Is cleared and the count value is initialized (step S809). On the other hand, if it is equal to or less than the upper limit value of the number of defects in step S807 (step S807; No), it is determined whether or not a game ball payout operation as a prize ball is possible (step S810). As a specific example, in the process of step S810, a ball clogging error flag, a blanking error flag, a ball biting error flag, etc. are checked, and if any of the error flags is on, a winning ball is obtained. It is determined that the game ball payout operation is impossible. On the other hand, when any of the error flags is in the off state, it is determined that the game ball as a prize ball can be paid out.

  After executing the process of step S804 or when the payout operation is impossible in step S810 (step S810; No), the value of the payout control process flag is updated to “0” (step S811). The payout number counter is cleared and the count value is initialized (step S812). Further, the payout motor rotation counter is cleared and the count value is initialized (step S813). On the other hand, when the payout operation is possible in step S810 (step S810; Yes), the winning ball is not paid out by setting the subtraction value obtained in step S805 in the winning ball non-payout counter. The counter value is updated (step S814). Further, the value of the previous unpaid counter is updated by setting the subtraction value obtained in step S805 in the previous unpaid counter (step S815). By executing the processing of step S815, the same value as the value of the award ball non-payout counter is set to the previous value on condition that the count value indicating the payout operation amount is stored in the payout motor rotation counter in step S806. It will also be set in the unpaid counter. After executing the process of step S815, the value of the prize ball payout operation process flag is updated to “1” which is a value corresponding to the prize ball payout driving process (step S816).

  55 and 56 are flowcharts showing an example of the prize-ball payout driving process executed in step S744 shown in FIG. When the winning ball payout driving process is started, for example, the CPU 214 determines whether or not the main board communication error flag is on in the payout control microcomputer 150 (step S821 shown in FIG. 55). When the main board communication error flag is OFF in step S821 (step S821; No), it is determined whether or not the value of the award ball non-payout counter is larger than the value of the payout number counter (step S822). ). Here, when the value of the award ball non-payout counter is larger than the value of the number-of-payout counter in step S822 (step S822; Yes), a normal payout operation of the game ball serving as a prize ball is performed. It is judged that At this time, for example, by determining whether or not the elapsed time is measured by the payout operation control timer provided in the payout control timer setting unit 142 (whether or not the timer value is other than “0”). Then, it is determined whether or not the completion of the winning ball payout operation is on standby (step S823).

  When it is determined in step S823 that the award ball payout operation is not in a standby state (step S823; No), the winning ball is determined based on, for example, the excitation time of the payout motor 51 or the detection result by the payout motor position sensor 71. It is determined whether or not a payout operation for paying out one game ball is in progress (step S824). When the payout operation for paying out one game ball is not in progress (step S824; No), it is determined whether or not the value of the payout motor rotation counter is “0” (step S825). When the value of the payout motor rotation counter is “0” in step S825 (step S825; Yes), setting is made to stop driving of the payout motor 51 (step S826), and payout is completed in the payout operation control timer. A predetermined timer initial value is set as the waiting initial value (step S827), and the winning ball payout driving process is terminated. The payout completion waiting initial value corresponds in advance to the maximum time required for the game ball payout to be detected by the payout count switch 72 after the game ball payout operation is performed by driving the payout motor 51. Any predetermined timer initial value may be used.

  When the value of the payout motor rotation counter is a value other than “0” in step S825 (step S825; No), for example, one game ball is set such that the start address of a predetermined excitation pattern table is set as a pointer. Settings relating to a payout operation for payout are performed (step S828). At this time, the value of the payout motor number counter is updated by subtracting 1 (step S829). Thus, since the setting relating to the payout operation is performed in step S828 when the value of the payout motor rotation counter is a value other than “0” in step S825, a value other than “0” is set in the payout motor rotation counter. By setting, a game ball payout operation is actually executed.

  Further, when the payout operation for paying out one game ball is being performed in step S824 (step S824; Yes), for example, the state of various error flags provided in the payout control flag setting unit 141 is confirmed. Thus, it is checked whether or not an error has occurred in the payout operation by the payout motor 51 (step S830). At this time, if an error has occurred in the payout operation (step S830; No), for example, a setting for stopping the drive of the payout motor 51 is performed in the same manner as in step S826. Settings corresponding to the generated error are made (step S831).

  When it is determined in step S823 that the award ball payout operation is waiting to be completed (step S823; Yes), the value of the payout operation control timer is updated, for example, by 1 (step S832). . Subsequently, it is determined whether or not the value of the payout number counter has reached the value of the award ball non-payout counter (step S833). At this time, if the value of the payout number counter has not reached the value of the award ball non-payout counter (step S833; No), for example, it is determined whether or not the payout operation control timer has timed out due to the update in step S832. Thus, it is determined whether or not the payout completion waiting time has elapsed (step S834). At this time, if the payout completion waiting time has elapsed (step S834; Yes), the number of game balls counted by the payout number counter as game balls already paid out by driving the payout motor 51 is calculated as the payout amount counter. It is determined that the waiting time for waiting for the completion of the prize ball payout operation has passed before the number of game balls counted by the prize ball non-payout counter is reached. Therefore, the value of the payout operation failure number counter is incremented by 1 and updated (step S836).

  When the value of the payout number counter reaches the value of the award ball non-payout counter in step S833 (step S833; Yes), after executing the processing of step S835, the payout operation control timer is cleared and initialized. At the same time (step S836), the previous unpaid counter is cleared and initialized (step S837). Thereafter, the value of the winning ball payout control process flag is updated to “0” (step S838). FIG. 48 shows a stage before the execution of the prize ball payout number calculation process in step S743 shown in FIG. 53 after the value of the payout number counter reaches the value of the prize ball non-payout counter in step S833. If it is determined in step S607 that the payout number designation command has been received, it is determined in step S802 shown in FIG. 54 that the value of the award ball non-payout counter is larger than the value of the payout number counter. May be. In this embodiment, the upper limit value of the number of failures to be compared with the value of the payout operation failure number counter in step S807 shown in FIG. 54 is set to an appropriate value (for example, “9”), which is shown in FIG. After the value of the number-of-payout counter reaches the value of the award ball non-payout counter in step S833, a payout number designation command is received at a stage before the award ball payout number calculating process in step S743 shown in FIG. 53 is executed. Even in such a case, it is possible to appropriately detect a defect in the payout operation due to occurrence of a clogged ball or the like in the payout motor 51 or the payout case 17 while preventing the error from being immediately determined.

  When the main board communication error flag is ON in step S821 (step S821; Yes), the value of the award ball non-payout counter is equal to or smaller than the value of the payout number counter in step S822. (Step S822; No), the setting for stopping the driving of the payout motor 51 is performed similarly to Step S826 (Step S839), and the value of the prize ball payout operation process flag is updated to “0”. (Step S840). As described above, when the main board communication error flag is ON in step S821, the process proceeds to step S839 to stop driving of the payout motor 51, so that the payout control board 15 is connected to the main board 11. When an error relating to communication has occurred, the payout control of game balls that are unpaid prize balls can be controlled to be stopped.

  Further, after executing the process of step S829, when no error has occurred in the payout operation in step S830 (step S830; Yes), or when the payout completion waiting time has not elapsed in step S834 (step S834; No), the value of the winning ball unpaid counter is compared with the value of the previous unpaid counter (step S841 shown in FIG. 56). Subsequently, based on the comparison result in step S841, it is determined whether or not the value of the prize ball non-payout counter has increased (step S842). For example, in the process of step S842, when it is determined from the comparison result in step S841 that the value of the winning ball unpaid counter is larger than the value of the previously unpaid counter, the value of the winning ball unpaid counter is It is determined that the number has increased. When the value of the winning ball unpaid counter has not increased in step S842 (step S842; No), the winning ball payout driving process is terminated.

  If it is determined in step S842 that the value of the winning ball unpaid counter has increased (step S842; Yes), the value of the previously unpaid counter is subtracted from the value of the winning ball unpaid counter (step S843). The subtraction value obtained by executing the subtraction process in step S843 is an increase in the value of the award ball unpaid counter, and an increase in the unpaid number indicating the number of game balls to be paid out as a prize ball. Become. Then, the subtraction value obtained by the subtraction process in step S843 is added to the count value in the payout motor rotation counter (step S844), and the count value in the payout motor rotation counter is updated. Thereafter, the value of the winning ball unpaid counter is set in the previously unpaid counter (step S845), the payout operation control timer is cleared and initialized (step S846), and the winning ball payout driving process is terminated. To do.

  FIG. 57 is a flowchart showing an example of the ball lending / dispensing operation process executed in step S664 shown in FIG. When the ball lending / dispensing operation process is started, in the payout control microcomputer 150, first, for example, the CPU 214 detects that the detection signal from the payout count switch 72 is on based on the execution result of the input / output process in step S531 shown in FIG. It is determined whether or not (step S761). When the detection signal from the payout count switch 72 is on (step S761; Yes), 1 is added to the value of the payout number counter provided in the payout control counter setting unit 143 (step S762). On the other hand, when the detection signal from the payout count switch 72 is OFF in step S761 (step S761; No), the process of step S762 is skipped. Thereafter, according to the value of the ball lending operation process flag provided in the payout control flag setting unit 141, one of the processes of steps S763 and S764 shown in FIG. 57 is selected and executed. Here, the ball lending / dispensing number calculation processing in step S763 is executed when the value of the ball lending operation process flag is “0”. The ball lending payout driving process in step S764 is executed when the value of the ball lending operation process flag is “1”.

  FIG. 58 is a flowchart showing an example of the ball lending / dispensing number calculation process executed in step S763 shown in FIG. When the ball lending / dispensing number calculation process is started, the payout control microcomputer 150 first determines, for example, whether or not the value of the ball lending unpaid counter is larger than the value of the number-of-payout counter. (Step S861). Here, when the value of the unpaid ball lending counter is equal to or smaller than the value of the number-of-payout counter in step S861 (step S861; No), it corresponds to the value of the lending unpaid counter. It is determined that the game ball payout operation has been completed. At this time, the payout operation failure number counter is cleared and the count value is initialized (step S862), and the ball lending unpaid counter is cleared and the count value is initialized (step S863).

  On the other hand, when the value of the ball lending unpaid counter is larger than the value of the number-of-payout counter in step S861 (step S861; Yes), out of the number of game balls counted by the ball lending unpaid counter It is determined that the payout operation has not been completed yet. Therefore, the number of game balls that have not yet been paid out is identified by subtracting the number of payouts, which is the value of the payout number counter, from the number of payouts, which is the value of the ball lending unpaid counter (step S864). . Subsequently, the subtraction value as the value specified by the subtraction process in step S864 is set in the payout motor rotation counter (step S865).

  Following the process of step S865, it is determined whether or not the value of the payout operation failure frequency counter exceeds a predetermined failure frequency upper limit (eg, “9”) (step S866). At this time, if the upper limit value of the number of defects is exceeded (step S866; Yes), the ball clogging error flag is set to the on state (step S867), and the payout operation defect number counter is cleared and the count value is initialized. (Step S868). On the other hand, if it is equal to or less than the upper limit value of the number of defects in step S866 (step S866; No), it is determined whether or not a payout operation of the game ball to be rented is possible (step S869). As a specific example, in the process of step S869, a ball clogging error flag, a blanking error flag, a ball biting error flag, a card unit unconnected error flag, and the like are checked, and one of the error flags is turned on. If it is, it is determined that the game ball to be rented out cannot be paid out. Further, when a predetermined command (for example, a full tank notification command) for notifying that the main board 11 is full or a predetermined command (for example, a ball full notification command) for notifying that the ball is out is received. Also, it is determined that the operation of paying out the game ball as a rental ball is impossible. On the other hand, when any of the error flags is in an off state and a full tank notification command or a ball out notification command is not received from the main board 11, a payout operation of a game ball to be rented is possible It is judged that.

  After executing the process of step S863 or when the payout operation is impossible in step S869 (step S869; No), the value of the payout control process flag is updated to “0” (step S870). The payout number counter is cleared and the count value is initialized (step S871). Further, the payout motor rotation counter is cleared and the count value is initialized (step S872). On the other hand, when the payout operation is possible in step S869 (step S869; Yes), the subtracted value obtained in step S864 is set in the award ball non-payout counter, thereby not lending the ball. The counter value is updated (step S873). Then, the value of the ball lending operation process flag is updated to “1” which is a value corresponding to the ball lending payout driving process (step S874).

  FIG. 59 is a flowchart showing an example of the ball lending / dispensing drive process executed in step S764 shown in FIG. When this ball rental payout driving process is started, the payout control microcomputer 150 first determines, for example, whether or not the value of the ball loan unpaid counter is larger than the value of the payout number counter. (Step S881). Here, when the value of the ball lending unpaid counter is larger than the value of the number-of-payout counter in step S881 (step S881; Yes), a normal payout operation of the game ball serving as the lending ball is performed. It is judged that At this time, for example, by determining whether or not the elapsed time is measured by the payout operation control timer provided in the payout control timer setting unit 142 (whether or not the timer value is other than “0”). Then, it is determined whether or not waiting for completion of the payout operation in the ball lending (step S882).

  When it is determined in step S882 that the payout operation is not waiting (step S882; No), for example, a game ball to be rented from the excitation time of the payout motor 51 or a detection result by the payout motor position sensor 71. It is determined whether or not a payout operation for paying out one item is in progress (step S883). When the payout operation for paying out one game ball is not in progress (step S883; No), it is determined whether or not the value of the payout motor rotation counter is “0” (step S884). When the value of the payout motor rotation counter is “0” in step S884 (step S884; Yes), the setting for stopping the driving of the payout motor 51 is performed (step S885), and the payout operation control timer completes payout. A predetermined timer initial value is set as a waiting initial value (step S886), and the ball lending / dispensing driving process is terminated.

  When the value of the payout motor rotation counter is a value other than “0” in step S884 (step S884; No), for example, one game ball is set such that the start address of a predetermined excitation pattern table is set as a pointer. Settings relating to a payout operation for payout are performed (step S887). At this time, after updating by subtracting 1 from the value of the payout motor number counter (step S888), the ball lending payout driving process is terminated.

  Further, when the payout operation for paying out one game ball is being performed in step S883 (step S883; Yes), for example, the status of various error flags provided in the payout control flag setting unit 141 is confirmed. Thus, it is checked whether or not an error has occurred in the payout operation by the payout motor 51 (step S889). At this time, if an error has occurred in the payout operation (step S889; No), for example, a setting for stopping the drive of the payout motor 51 is performed in the same manner as in step S885, during the payout operation by the payout motor 51. Settings corresponding to the generated error are made (step S890). On the other hand, when it is determined in step S889 that no error has occurred in the payout operation (step S889; Yes), the process of step S890 is skipped and the ball lending payout driving process is terminated.

  When it is determined in step S882 that the payout operation in the ball lending is completed (step S882; Yes), the value of the payout operation control timer is updated by, for example, subtracting 1 (step S891). ). Subsequently, it is determined whether or not the value of the payout number counter has reached the value of the ball lending unpaid counter (step S892). At this time, if the value of the payout number counter has reached the value of the ball lending unpaid counter (step S892; Yes), it is determined that the payout of the game ball as the lending ball to be paid out is completed normally. After the value of the lending operation process flag is updated to “0” (step S893), the ball lending / dispensing driving process is terminated. On the other hand, if the value of the payout number counter does not reach the value of the unpaid counter in step S892 (step S892; No), for example, it is determined whether or not the payout operation control timer has timed out due to the update in step S891. It is determined whether or not the payout completion waiting time has elapsed (step S894). At this time, if the payout completion waiting time has not elapsed (step S894; No), the ball lending payout driving process is terminated. On the other hand, when the payout completion waiting time has elapsed in step S894 (step S894; Yes), the game counted by the payout number counter as a game ball already paid out by driving the payout motor 51. It is determined that the waiting time for waiting for completion of the payout operation in the ball lending has elapsed before the number of balls reaches the number of game balls counted by the ball lending unpaid counter as lending balls to be paid out. At this time, the value of the payout operation failure number counter is incremented by 1 (step S895), and then the process proceeds to step S893 to update the value of the ball lending operation process flag to “0”.

  If the value of the unpaid ball lending counter is equal to or smaller than the value of the payout number counter in step S881 (step S881; No), the payout motor 51 is driven in the same manner as in step S885. The setting for stopping is performed (step S896), and the value of the ball lending operation process flag is updated to “0” (step S897).

  In the 7-segment display process executed in step S536 shown in FIG. 47, for example, the CPU 214 provided in the payout control microcomputer 150 checks the states of various error flags provided in the payout control flag setting unit 141. Then, control data for controlling the lighting operation of the error display LED 74 corresponding to the error flag in the on state is set in a predetermined output port provided in the payout control microcomputer 150. FIG. 60 is an explanatory diagram showing the relationship between the type of error and the display of the LED 74 for error display.

  As shown in FIG. 60, when the main board communication error flag is turned on, the payout control microcomputer 150 performs control to display “0” on the error display LED 74 as the main board communication error. . When the ball biting error flag is turned on, control is performed to display “1” on the error display LED 74 as a ball biting error. When the idle error flag is turned on, control is performed to display “2” on the error display LED 74 as an idle error. When the serial communication error flag is turned on, control is performed to display “3” on the error display LED 74 as a serial communication error. When the ball clogging error flag is turned on, control is performed to display “4” on the error display LED 74 as a ball clogging error. When the card unit unconnected error flag is turned on, control is performed to display “5” on the error display LED 74 as a card unit unconnected error. When the large amount unpaid error flag is turned on, control is performed to display “6” on the error display LED 74 as a large amount unpaid error.

  Next, the operation in the effect control board 12 will be described. In the effect control board 12, when the power supply from the power supply board 10 is started and the reset signal to the effect control microcomputer 120 becomes high level (off state), the effect control microcomputer 120 is activated. The effect control main process as shown in the flowchart of FIG. 61 is executed. When the effect control main process shown in FIG. 61 is started, the effect control microcomputer 120 first initializes the RAM 122, sets various initial values, initializes a timer to determine the execution interval of effect control, and the like. Processing is executed (step S901). Thereafter, the effect control microcomputer 120 determines whether or not a timer interrupt has occurred, for example, by monitoring a timer interrupt flag (step S902). Until a timer interrupt occurs (step S902; No), the process enters a loop process that repeatedly executes the process of step S902. When a timer interrupt occurs (step S902; Yes), after clearing the timer interrupt flag to turn it off (step S903), the following effect control process is executed.

  Here, the timer interruption in the production control microcomputer 120 occurs, for example, every 2 milliseconds. That is, the effect control process is executed every 2 milliseconds, for example. In this embodiment, when a predetermined timer interrupt process is executed in response to the occurrence of a timer interrupt, the timer interrupt flag is set to the on state, and the specific effect control process is executed in the effect control main process. Is done. On the other hand, the effect control process may be executed in the timer interrupt process.

  In the effect control process, the effect control microcomputer 120 first executes an effect command analysis process for analyzing, for example, the effect control command received by the CPU 123 from the main board 11 via the relay board 18 (step S904). Subsequently, in the effect control microcomputer 120, for example, the CPU 123 executes effect control process processing (step S905). In the effect control process, various processes are selected and executed in accordance with the control state of the image display device 5, the speakers 8L and 8R, the game effect lamp 9, and the like that are electric parts for effects. Thereafter, a random number update process for updating various random numbers counted in the production control microcomputer 120 is executed (step S906). Further, a notification process for controlling a notification operation based on a notification instruction by a production control command from the main board 11 is executed (step S907).

  FIG. 62 is a flowchart showing an example of the effect control process executed in step S905 shown in FIG. In the effect control process 120, in the effect control microcomputer 120, for example, the CPU 123 performs the following step S920 in accordance with the value of the effect control process flag provided in a predetermined area (such as an effect control flag setting area) of the RAM 122. Each process of S925 is executed.

  The variable display start command reception waiting process in step S920 is executed when the value of the effect control process flag is “0”. In the variable display start command reception waiting process, the effect control microcomputer 120 determines whether, for example, the CPU 123 has received a variable display start command transmitted from the main board 11. Then, when the variable display start command is not received, it is determined whether or not the demo display command is received. At this time, if a demo display command has been received, the display operation of the image display device 5 is controlled to perform a predetermined demo display when a predetermined time has elapsed since the reception of the demo display command. When it is determined that the variable display start command is received in the variable display start command reception waiting process, the demonstration display in the image display device 5 is terminated and the value of the effect control process flag is updated to “1”. To do.

  The effect display control setting process in step S921 is executed when the value of the effect control process flag is “1”. This effect display control setting processing corresponds to the fact that the special symbol is variably displayed in the special symbol game by the special symbol display device 4, and the effect by various displays including the variable display of the decorative symbol in the image display device 5. In order to perform the above, processing for setting the display operation of the image display device 5 is included. As a specific example, in the effect display control setting process in step S921, first, it is determined whether or not the variable display pattern designated by the variable display start command from the main board 11 is a big hit pattern, and is not a big hit pattern. Is determined, it is determined whether or not it is a reach loss pattern. When it is determined that the pattern is not the reach loss pattern, it is determined that the normal loss pattern has been designated, and a normal lose symbol determination process for determining a definite decorative symbol for a normal loss combination is executed. Further, when the variable display pattern designated by the variable display start command is a reach lose pattern, a reach lose symbol determination process for determining a definite decorative symbol to be a reach lose combination is executed.

  Further, when the variable display pattern designated by the variable display start command is a big hit pattern, a big hit symbol determination process for determining a confirmed decorative symbol to be a big hit combination is executed. At this time, for example, the CPU 123 reads a display result notification command transmitted from the main board 11 to determine whether the gaming state is a probable big hit that becomes a high probability state or a normal big hit that does not become a high probability state. To do. When it is determined that the probability variation is a big hit, for example, the same probability variation among the decorative symbols “1”, “3”, “5”, “7” or “9” as the probability variation symbol having an odd symbol number. The symbol is determined to be a definite ornament symbol that is derived and displayed on each of the “left”, “middle”, and “right” variable display units as a display result in the variable display of the ornament symbol in the image display device 5. On the other hand, when it is determined that it is a normal big hit, for example, the same normal among the decorative symbols “0”, “2”, “4”, “6” or “8” as a normal symbol having an even symbol number The symbol is determined to be a definite ornament symbol that is derived and displayed on each of the “left”, “middle”, and “right” variable display units as a display result in the variable display of the ornament symbol in the image display device 5.

  After determining the final decorative symbol by executing these processes, in the effect display control setting process, the symbol display control pattern corresponding to the variable display pattern designated by the variable display start command is determined, and the symbol display control pattern is determined. For example, a drawing command corresponding to is sent to the VDP, and settings for starting variable display of decorative symbols are performed. At this time, a timer setting for measuring the variable display time of the decorative symbols is also performed corresponding to the symbol display control pattern. Thereafter, the value of the effect control process flag is updated to “2”, and the effect display control setting process ends.

  The decorative symbol variable display process in step S922 is executed when the value of the effect control process flag is “2”. In this decorative symbol variable display processing, for example, the reading position in the symbol display control pattern is switched in accordance with the elapsed time since the decorative symbol variable display was started, and drawing corresponding to the display control data read from the reading position is performed. The display operation in the image display device 5 is controlled by sending a command to the VDP. Then, when the timing to end the variable display of the decorative symbols is reached, the big hit start command reception waiting time is set and the value of the effect control process flag is updated to “3”.

  The decorative symbol stop process in step S923 is executed when the value of the effect control process flag is “3”. In this decorative symbol stop process, it is determined whether or not the jackpot start command transmitted from the main board 11 has been received. Then, when the big hit start command reception waiting time has elapsed without receiving the big hit start command, it is determined that the decorative symbol variable display result is lost, and the value of the effect control process flag is updated to “0”. Also, when it is determined that the jackpot start command is received in the decorative symbol stop process, it is determined that the variable symbol display result is a big bonus, and the value of the effect control process flag is updated to “4”. To do.

  The big hit effect process of step S924 is executed when the value of the effect control process flag is “4”. In the jackpot effect process, the display operation in the image display device 5 is controlled to perform control to display an image corresponding to the jackpot gaming state. Then, it is determined whether or not a big hit end command has been received from the main board 11, and when it is determined that it has been received, the value of the effect control process flag is updated to “5”.

  The big hit end effect process in step S925 is executed when the value of the effect control process flag is “5”. The jackpot end effect process includes a process of performing control for executing an effect display for notifying that the jackpot game state has ended on the image display device 5. Thereafter, when the various effect displays are completed, the value of the effect control process flag is updated to “0”.

  FIG. 63 is a flowchart showing an example of the notification process executed in step S907 shown in FIG. When the notification process is started, the effect control microcomputer 120 first determines whether or not the notification of the excessive number of prize balls or the shortage of prize balls is being made, for example, the value of the notification timer provided in the predetermined area of the RAM 122 by the CPU 123. (Step S941). Here, the notification timer may be a timer used for measuring the elapsed time from the start of notification of excessive prize balls or insufficient prize balls to the end of the notification. If the notification timer has timed out in step S941, it is determined that there is no notification of excessive prize balls or shortage of prize balls. On the other hand, if the notification timer has not timed out, notification of excessive prize balls or insufficient prize balls is issued. What is necessary is just to determine that is performed. When it is determined in step S941 that there is a notification of excessive prize balls or insufficient prize balls (step S941; Yes), the timer value in the notification timer is updated by, for example, subtracting 1 (step S942). ). Then, based on the value of the notification timer updated in step S942, it is determined whether or not it is time to end notification of excessive or insufficient prize balls (step S943). At this time, if the timing to end the notification has not been reached (step S943; No), the notification processing is ended. On the other hand, if the timing to end the notification in step S943 has been reached (step S943; Yes), the notification of excessive or insufficient prize balls, for example, a setting for initializing the display operation in the image display device 5 is ended. Is set (step S944).

  When it is determined in step S941 that there is no notification of excessive prize balls or insufficient prize balls (step S941; No), after executing the process of step S944, excessive prize balls from the main board 11 are performed. It is determined whether a command has been received (step S945). Then, when an excessive prize ball command is received (step S945; Yes), an image of the excessive prize ball notification screen illustrated in FIG. Is set to start (step S946). At this time, the timer initial value indicating the notification time corresponding to the notification of excessive prize balls is set in the notification timer (step S947).

  Further, when the excessive prize ball command is not received in step S945 (step S945; No), it is determined whether or not a prize ball shortage command from the main board 11 is received (step S948). When a prize shortage command is received (step S948; Yes), a prize ball shortage notification is displayed by causing the image display device 5 to display an image serving as a prize ball shortage notification screen as illustrated in FIG. Is set to start (step S949). At this time, the timer initial value indicating the notification time corresponding to the notification of the shortage of prize balls is set in the notification timer (step S950). When the winning ball shortage command is not received in step S948 (step S948; No), whether or not the full flag is being notified is checked by the CPU 123, for example, by checking a predetermined full tank notifying flag. Determination is made (step S951). At this time, if full tank notification has been performed (step S951; Yes), it is determined whether a full tank notification end command from the main board 11 has been received (step S952). If the full tank notification end command has not been received (step S952; No), the notification processing is ended. On the other hand, when a full tank notification end command is received in step S952 (step S952; Yes), a notification that the lower plate 33 is full, for example, a setting for initializing the display operation in the image display device 5 is given. Settings for termination are performed (step S953).

  When it is determined in step S951 that the full tank notification is not performed (step S951; No), after executing the process of step S953, a full tank notification start command is received from the main board 11. Whether or not (step S954). At this time, if the full tank notification start command has not been received (step S954; No), the notification processing is terminated. On the other hand, when a full tank notification start command is received (step S954; Yes), a setting is performed to display on the image display device 5 an image that becomes a full tank notification screen as illustrated in FIG. S955).

  Next, a specific operation example of the random number circuit 103 provided in the game control microcomputer 100 will be described. FIG. 65 is a timing chart for explaining the operation of the random number circuit 103. An internal system clock CLK as shown in FIG. 65A is input to the clock input terminal of the clock signal output circuit 171 and the clock input terminal of the timer circuit 179 provided in the random number circuit 103. The internal system clock CLK may be generated by the clock circuit 101 provided in the game control microcomputer 100. As shown in FIG. 65A, the internal system clock CLK is a clock signal that rises from a low level to a high level at timings T11, T21,.

  The clock signal output circuit 171 divides the internal system clock CLK and rises from a low level to a high level at timings T11, T12,..., And falls from a high level to a low level at timings T21, T22,. A clock signal S1 shown in 65 (B) is generated. In the operation example shown in FIG. 65, for the sake of explanation, a case where the clock signal output circuit 171 generates the clock signal S1 by dividing the internal system clock CLK by two is shown. However, in practice, as a cycle for updating the 16-bit random number, either the cycle of the internal system clock CLK or a cycle 16 times the internal system clock CLK is set. Therefore, the clock signal output circuit 171 only has to be able to switch between the case where the internal system clock CLK is output as it is as the clock signal S1 and the case where the signal obtained by dividing the internal system clock CLK by 16 is output as the clock signal S1. . The clock signal S1 output from the clock signal output circuit 171 is input to a random number generation circuit 173B and an inversion circuit 178 provided for generating a 16-bit random number.

  The random number generation circuit 173B updates the numerical data C2 in response to the rising edge of the clock signal S1 input to the clock input terminal, and outputs the numerical data C2 to the random number sequence change circuit 176B. The inversion circuit 178 inverts the signal level of the clock signal S1 output from the clock signal output circuit 171 to fall from a high level to a low level at timings T11, T12,..., And at timings T21, T22,. An inverted clock signal S2 as shown in FIG. 65C that rises from a low level to a high level is generated. The inverted clock signal S2 generated by the inverter circuit 178 is output from the inverter circuit 178 and input to the latch signal generator circuit 180.

  When the start winning signal SS shown in FIG. 65D is input to the timer circuit 179, when the elapsed time from the rising edge reaches a predetermined time (for example, 3 milliseconds), the output signal from the timer circuit 179 is low. Rise from level to high level. The output signal from the timer circuit 179 is input to the latch signal generation circuit 180, and is output as a latch signal SL as shown in FIG. 65 (E) in synchronization with the rising edge of the inverted clock signal S2. As a result, the random number generation circuit 173B updates the numerical data C1 at timings T11, T12,..., While the latch signal generation circuit 180 outputs a latch signal SL that rises at a timing T22 different from the timings T11, T12,. Can do. Here, the operation in which the random number sequence change circuit 176B changes the arrangement of the numerical data C2 output from the random number generation circuit 173B, and the numerical value data R2 that becomes the random value output from the random number sequence change circuit 176B by the maximum value comparison circuit 177B. Is performed within a period sufficiently shorter than the cycle of the internal system clock CLK by performing the operation of repeating the resetting until a value equal to or less than the maximum value is compared with the predetermined maximum value, from the maximum value comparison circuit 177B. In the random value register 181B, the numerical data R2 that is the updated random value is output within a sufficiently short elapsed time from the rising edge of the clock signal S1. Then, the latch signal SL rises from the low level to the high level in synchronization with the inverted clock signal S2, so that the numerical data R2 that becomes the updated random number value can be reliably and stably acquired.

  As described above, in the pachinko gaming machine 1 according to the above-described embodiment, when power supply to the pachinko gaming machine 1 is started, the CPU 104 provided in the gaming control microcomputer 100 in, for example, step S21 shown in FIG. The fourth and third bits [bits 4-3] of the first random number initial setting data (KRSS1) stored in the ROM 105 are read, and the process of step S22 is executed based on the read value, and the random number circuit 103 receives a random number. Set to generate. Thereafter, the game control microcomputer 100 is set to the interrupt-permitted state, for example, by the CPU 104 executing the process of step S25. The processes executed in step S22 include a 12-bit random number initial setting process as shown in FIG. 29 and a 16-bit random number initial setting process as shown in FIG. In the 12-bit random number initial setting process shown in FIG. 29, the CPU 104 reads the seventh bit [bit 7] of the second random number initial setting data (KRSS2) stored in the ROM 105 in step S101, and the read value is “1”. In this case, the start value for the first round for generating the 12-bit random number in the random number circuit 103 by executing the process of step S104 is the unique identification information assigned to each game control microcomputer 100. It is determined based on a certain ID number. In the 16-bit random number initial setting process shown in FIG. 30, the CPU 104 reads the fourth bit [bit 4] of the second random number initial setting data (KRSS2) stored in the ROM 105 in step S123, and the read value is “ When it is 1 ″, the unique identification given to each game control microcomputer 100 is the first round start value for generating a 16-bit random number in the random number circuit 103 by executing the processing of step S126. It is determined based on the ID number that is information. Thereby, the initial value of the random number that is updated after the power supply is started can be made different in each of the plurality of pachinko gaming machines 1, and the special symbol display device using the random value generated in this way By determining whether or not the variable display result in a special game such as 4 is a big hit, it is possible to improve randomness of random numbers and prevent a big hit from being generated illegally.

  In step S608 shown in FIG. 48, the number of prize balls paid out specified by the number-of-payout designation command is added to the value of the prize ball unpaid counter, and in step S814 shown in FIG. 54, it is obtained by the subtraction process in step S805. By setting the subtraction value in the award ball unpaid counter, the unpaid number corresponding to the number of game balls to be paid out as a prize ball is stored in the award ball unpaid counter. On the other hand, in step S806 shown in FIG. 54, the subtraction value obtained by the subtraction process in step S805 is set in the payout motor rotation counter. In step S844 shown in FIG. 56, the subtraction value obtained by the subtraction process in step S843 is set. By setting the payout motor rotation counter, the payout operation amount that is the drive amount of the payout motor 51 is stored in the payout motor rotation counter in response to the number of unpaid out being stored in the prize ball non-payout counter. The value of the payout motor rotation counter is decremented by 1 every time the process of step S829 shown in FIG. 55 is executed, and it is determined in step S825 that the value of the payout motor rotation counter is “0”. Until the game ball is set to be paid out in the process of step S828, the payout motor 51 starts the payout of the game ball as a prize ball after the payout motor 51 starts, and the payout motor in step S825. Until the determination that the value of the rotation counter is “0” is made, continuous payout that causes the payout motor 51 to execute the payout operation of the game ball is continuously performed. Here, when it is determined in step S842 shown in FIG. 56 that the value of the prize ball unpaid counter has increased, the increment in the unpaid number specified by executing the subtraction process in step S843 is calculated as follows: By adding to the value of the payout motor rotation counter in step S844, the drive amount of the payout motor 51 corresponding to the payout number of the game balls indicated by the payout number designation command received during execution of the payout operation by the payout motor 51 Is added to the value of the payout motor rotation counter, and then the game is continuously performed on the payout motor 51 until it is determined in step S825 that the value of the payout motor rotation counter is “0”. Execute the ball dispensing operation. As a result, it is possible to continuously perform the award ball payout operation including the game ball payout number indicated by the payout number designation command received during the payout operation of the payout motor 51. Can be paid out.

  When it is determined in step S825 shown in FIG. 55 that the value of the payout motor rotation counter is “0”, the payout operation by the payout motor 51 is stopped by the setting in step S826. On the other hand, the value of the award ball non-payout counter is cleared when the process of step S804 shown in FIG. 54 is executed based on the value of the payout number counter, or is executed when the process of step S814 is executed. It is updated to the subtraction value obtained in S805. At this time, since the payout operation by the payout motor 51 is stopped, it is possible to prevent the game balls as the winning balls from being paid out excessively. In the process of step S806, a subtraction value obtained by subtracting the value of the number-of-payout counter from the value of the award ball unpaid counter in step S805 is set. The payout operation by the motor 51 can be resumed, and it is possible to prevent the number of payout balls from being insufficient. In this way, certainty in the payout control of prize balls can be improved.

  In step S841 shown in FIG. 56, the value of the winning ball unpaid counter is compared with the value of the previously unpaid counter, and based on the comparison result, in step S842, whether or not the value of the winning ball unpaid counter has increased. Judgment is made. Here, for example, the value of the previous unpaid counter is the same as that in step S845 when step S815 is executed following step S806 shown in FIG. 54, or after step S844 shown in FIG. When the count value indicating the driving amount of the payout motor 51 is stored in the payout motor rotation counter as when executed, the value is set to be the same as the value of the award ball non-payout counter. When it is determined in step S842 shown in FIG. 56 that the value of the prize ball unpaid counter has increased, the value of the previous unpaid counter is subtracted from the value of the prize ball unpaid counter in step S843. Thus, the increment in the value of the prize ball unpaid counter is specified. In this way, it is possible to determine whether or not the value of the award ball unpaid counter has increased during the execution of the payout operation by the payout motor 51, by providing a previous unpaid counter separately from the award ball unpaid counter, When the value of the unpaid counter is increased, it is possible to specify the increment, and it is possible to reliably identify the increment in the number of game balls to be awarded with a simple configuration and simple operation.

  When it is determined in step S833 shown in FIG. 55 that the value of the number-of-payout counter has reached the value of the award ball non-payout counter, the payout of the game ball to be a prize ball is completed, and in step S837 The value of the previously unpaid counter is cleared. Thereby, when the determination process of step S842 shown in FIG. 56 is executed or when the subtraction process of step S843 is executed, an inappropriate past numerical value is not stored in the previous unpaid counter. Thus, it is possible to reliably prevent malfunctions in paying out the game balls serving as prize balls.

  In the game control microcomputer 100 mounted on the main board 11, for example, the CPU 104 executes the processes of steps S201 and S202 shown in FIG. 32, the touch sensor detection signal from the touch sensor 75 is on, and When the detection signal from the tongue switch 26 is in the off state, the processing of steps S206 and S207 shown in FIG. 32 and steps S222 and S225 shown in FIG. The game ball can be supplied to the launching device 19 by the ball feeding device 62 or the ball feeding device 62. With such a configuration, it is possible to output a permission signal permitting the launch of the game ball on condition that the player or the like is in contact with the operation knob 30 and that the lower plate 33 is not full. it can. On the other hand, when a player or the like is not in contact with the operation knob 30 or when the lower plate 33 is in a full tank state, the game ball is not allowed to be launched. For example, the gap between the rotating portion of the operation knob 30 and the support portion When a foreign object such as a coin is inserted and the operation knob 30 is fixed, the game ball is fired by an illegal act such that the game ball is fired without operating the operation knob 30 by the player himself. It can prevent paying out exceeding the allowable amount of the lower plate 33.

  The ball feeding device 62 is driven when the supply permission signal from the main board 11 is in an ON state, and supplies the game balls stored in the upper plate 32 to the launching device 19. Then, in the game control microcomputer 100 mounted on the main board 11, for example, the CPU 104 executes the process of step S225 shown in FIG. 33, thereby causing the ball feeder 62 to output an on-state supply permission signal. . Thereby, the launch of the game ball can be stopped by the control of the ball feeding device 62 that supplies the game ball to the launch device 19, and the control in the game control microcomputer 100 is compared to the case where the drive of the launch device 19 is controlled. The burden can be reduced.

  If it is determined in step S308 that the full tank notification flag is OFF in step S308 when the detection signal from the full switch 26 is in the ON state in step S308 shown in FIG. 41, the setting in step S310 is performed. A full tank notification start command is transmitted to the effect control board 12. Then, when it is determined in step S954 shown in FIG. 63 that the production control microcomputer 120 has received a full tank notification start command from the main board 11, the setting in step S955 is illustrated in FIG. 64C. By displaying on the image display device 5 an image that becomes such a full tank notification screen, it is notified that the lower plate 33 is in a full state. Thereby, it can be easily recognized outside the pachinko gaming machine 1 that the storage amount of the game balls in the lower tray 33 has reached a predetermined amount.

  The random number circuit 103 provided in the game control microcomputer 100 is configured to include a plurality of circuits for generating random numbers having different numerical data update ranges, such as a 12-bit random number and a 16-bit random number. ing. In the gaming control microcomputer 100, when power supply to the pachinko gaming machine 1 is started, for example, the CPU 104 stores first random number initial setting data (KRSS1) stored in the ROM 105 in step S21 shown in FIG. 4 and 3rd bits [bits 4-3] are read out, and the process in step S22 based on the read value includes the 12-bit random number initial setting process shown in FIG. 29 and the 16-bit random number initial setting process shown in FIG. Make it executable. Then, the 12-bit random number initial setting process shown in FIG. 29 is executed, so that the random number circuit 103 can generate the 12-bit random number. The 16-bit random number initial setting process shown in FIG. The circuit 103 can generate a 16-bit random number. On the other hand, when the 12-bit random number initial setting process is not executed as the process in step S22, the process for stopping the generation operation for the 12-bit random number in the random number circuit 103 is executed, and the 16-bit random number initial setting process is executed as the process in step S22. Is not executed, the processing of stopping the generation operation for the 16-bit random number in the random number circuit 103 is executed, thereby stopping the function of the circuit that generates a random number having a different update range from the set random number. it can. Thereby, the circuit corresponding to the random number used according to various determinations is set, for example, whether or not the variable display result in the special symbol game by the special symbol display device 4 is a big hit, and the determination is made. Can reduce the processing load required.

  In the gaming control microcomputer 100, when power supply to the pachinko gaming machine 1 is started, for example, the CPU 104 reads the 12-bit random number maximum value (KRMS) stored in the ROM 105 in step S107 shown in FIG. After the read value is set in the maximum value comparison circuit 177A included in the random number circuit 103 in step S108, whether or not the read value is within a range that can be set as the maximum value for the 12-bit random number is determined in step S109. Judgment. If it is determined in step S109 that it is not within the settable range, a predetermined value within the range that can be set as the maximum value for 12-bit random numbers is reset in step S110. Further, for example, the CPU 104 reads the maximum 16-bit random number (KRXS) stored in the ROM 105 in step S129 shown in FIG. 30, and sets the read value in the maximum value comparison circuit 177B included in the random number circuit 103 in step S130. Thereafter, it is determined in step S131 whether or not the read value is within a range that can be set as the maximum value for a 16-bit random number. When it is determined in step S131 that it is not within the settable range, a predetermined value within the range that can be set as the maximum value for 16-bit random numbers is reset in step S132.

  By making it possible to arbitrarily set the maximum value for 12-bit random numbers and 16-bit random numbers within a predetermined range, it is possible to set the use range of random values in detail, and to reduce the processing load required for determination. it can. As a specific example, when generating a random value that matches a predetermined determination value data with a probability of 1/400 (1/400), the use range of the random value is fixed to “1” to “4000”. If it is determined, data indicating 10 numerical values included in “1” to “4000” is prepared in advance as determination value data, and whether the extracted random number value matches any of the 10 numerical values. It is necessary to execute a determination of whether or not (execute a maximum of 10 determinations). On the other hand, if the use range of the random number value can be set from “1” to “400”, data indicating one numerical value is prepared in advance as the determination value data, and the extracted random number value is the single numerical value. It is only necessary to execute the determination of whether or not it matches. In addition, it is possible to prevent random numbers from being updated within an extremely narrow range due to malfunctions or fraud.

  In the random number circuit 103, for example, the random number generation circuit 173A provided for the 12-bit random number responds to the fact that the stored value update signal KT from the random number register 181A rises from the low level to the high level, and the numerical data C1 Update. On the other hand, the random number generation circuit 173B provided for the 16-bit random number updates the numerical data C2 in response to the rise of the clock signal S1 from the clock signal output circuit 171 from the low level to the high level. . The cycle of the clock signal S1 output from the clock signal output circuit 171 is set according to the setting in the second bit [bit 2] of the first random number initial setting data (KRSS1) stored in the ROM 105. By setting either the cycle of CLK or a cycle 16 times the internal system clock CLK, the cycle in which the random number generation circuit 173B updates the numerical data C2 can be set to any of a plurality of types of cycles. As described above, the random number circuit 103 can update the numerical data C1 used to generate a 12-bit random number and the numerical data C2 used to generate a 16-bit random number by any of a plurality of update methods. it can. In the game control microcomputer 100, for example, the CPU 104 reads the second bit [bit 2] of the first random number initial setting data (KRSS1) stored in the ROM 105 in step S121 shown in FIG. 30, and based on the read value. Operation setting in the clock signal output circuit 171 provided in the random number circuit 103 is performed in step S122. As a result, the randomness update method can be made different to improve the randomness of the random numbers.

  In the processing of step S104 shown in FIG. 29 and the processing of step S126 shown in FIG. The calculated value can be set as a start value for generating a 12-bit random number or a 16-bit random number by executing the operations such as addition / subtraction / multiplication / division used. Thereby, the initial value of the random number that is updated after the power supply is started can be made different in each of the plurality of pachinko gaming machines 1, and the special symbol display device using the random value generated in this way By determining whether or not the variable display result in a special game such as 4 is a big hit, it is possible to improve randomness of random numbers and prevent a big hit from being generated illegally. In addition, since it becomes difficult to specify the start value from the unique identification information given to each game control microcomputer 100, it is possible to more reliably prevent the jackpot from being illegally generated. .

  The start port switch 22 detects that a game ball has won a start winning port, and outputs a start winning signal indicating that a start condition for executing the special symbol game by the special symbol display device 4 is satisfied. In the random number circuit 103, the start winning signal output from the start port switch 22 is input to the timer circuit 179, and the output signal from the timer circuit 179 is input to the latch signal generation circuit 180, whereby the start winning signal is generated. The latch signal SL can be output in response to the output. The timer circuit 179 measures the input time of the start winning signal SS, and when the measured time reaches a preset time (3 milliseconds), the output signal is raised from the low level to the high level. The latch signal generation circuit 180 outputs the output signal from the timer circuit 179 as the latch signal SL in synchronization with the inverted clock signal S2 output from the inverter circuit 178. For this reason, the pachinko gaming machine 1 can prevent the latch signal generation circuit 180 from erroneously outputting the latch signal SL to the random value register 181B due to the influence of noise or the like. In addition, since the timer circuit 179 is set to “3 milliseconds” shorter than the execution period “4 milliseconds” of the two timer interruption processes, the random number value read by the CPU 104 from the random value register 181B this time is set. Can be prevented from becoming the same value as the previously read random number value.

  In the gaming control microcomputer 100, for example, the CPU 104 reads the first and 0th bits [bits 1-0] of the first random number initial setting data (KRSS1) stored in the ROM 105 in step S111 shown in FIG. Based on the read value, the process of step S112 is executed to set the start value for the second and subsequent rounds in the 12-bit random number. Then, the setting is read out in step S242 shown in FIG. 34, and is used to generate a 12-bit random number in the random number circuit 103 when any of the processes in steps S244, S248, and S251 is executed based on the read value. The setting for changing the start value in the numerical data C1 to be performed is performed. Further, for example, the CPU 104 reads out the third and second bits [bit 3-2] of the second random number initial setting data (KRSS2) stored in the ROM 105 in step S133 shown in FIG. 30, and performs steps based on the read value. The process of S134 is executed to set the start value for the second and subsequent rounds in the 16-bit random number. Then, the setting is read out in step S254 shown in FIG. 35, and is used to generate a 16-bit random number in the random number circuit 103 when any of the processes in steps S256, S260, and S263 is executed based on the read value. The setting for changing the start value in the numerical data C2 to be performed is performed. In the random number circuit 103, when the random number generation circuit 173A provided for the 12-bit random number updates the numerical data to a predetermined final value, the random number cyclic circuit RIJ1 is output, while the random number generation circuit 173B provided for the 16-bit random number. When the numerical data is updated to a predetermined final value, a random number round-trip signal RIJ2 is output. When the random number generation circuit 173A outputs the random number loop signal RIJ1, for example, the initial value setting circuit 172A sets the start value set by the CPU 104 in the random number generation circuit 173A, while the random number generation circuit 173B sets the random number loop signal RIJ2 When the data is output, for example, the initial value setting circuit 172B sets the start value set by the CPU 104 in the random number generation circuit 173B, whereby the start value for generating a 12-bit random number or a 16-bit random number can be changed. As a result, when the numerical data C1 and the numerical data C2 are updated from a predetermined initial value to a predetermined final value, the start value that is the initial value in the next cycle is changed to increase the randomness of the random number. it can.

  In the gaming control microcomputer 100, when power supply to the pachinko gaming machine 1 is started, for example, the CPU 104 stores the second random number initial setting data (KRSS2) stored in the ROM 105 in step S105 shown in FIG. 6 and the fifth bit [bits 6-5] are read, and the processing of step S106 is executed based on the read value, thereby setting the selection operation in the selector 174A provided in the random number circuit 103 as a selector for 12-bit random numbers. I do. Accordingly, in the first method in which the permutation, which is the update order when the random number sequence changing circuit 176A updates the numerical data R1 for the 12-bit random number, is automatically changed after the second round, and after the second round. It can be changed by the second method that can be changed by the user program. Or it can also be set as the 3rd system which is not changed after the 2nd round. Further, for example, the CPU 104 reads the first and 0th bits [bits 1-0] of the second random number initial setting data (KRSS2) stored in the ROM 105 in step S127 shown in FIG. 30, and performs steps based on the read value. By performing the processing of S128, the selection operation is set in the selector 174B provided in the random number circuit 103 as a selector for 16-bit random numbers. Accordingly, in the first method in which the permutation, which is the update order when the random number sequence changing circuit 176B updates the numerical data R2 for 16-bit random numbers, is automatically changed in the second and subsequent rounds, and in the second and subsequent rounds. It can be changed by the second method that can be changed by the user program. Or it can also be set as the 3rd system which is not changed after the 2nd round. Then, when the second method that can be changed by the user program is set in the second round and thereafter, for example, the CPU 104 sets “0” to the 0th bit [bit 0] of the ARSC 175A in step S274 shown in FIG. Alternatively, numerical permutation change data is set by setting “0” to the 0th bit [bit 0] of BRSC 175B in step S279 shown in FIG. In the random number circuit 103, for example, when the second method is selected by the selector 174A, the numerical value permutation change data set in the ARSC 175A is read by the random number sequence change circuit 176A, and the numerical data output from the random number generation circuit 173A In response to the value of the column C1 reaching a predetermined final value, the update rule for determining the permutation of the numerical data C1 is changed. For example, when the second method is selected by the selector 174B, the numerical permutation change data set in the BRSC 175B is read by the random number sequence change circuit 176B, and the numerical data sequence C2 output from the random number generation circuit 173B is read. In response to the value reaching a predetermined final value, the update rule that determines the permutation of the numerical data C2 is changed. Thereby, when the numerical data C1 and the numerical data C2 are updated from a predetermined initial value to a predetermined final value, the permutation can be changed variously to increase randomness of random numbers.

  In addition, when the power supply is started, after the game control microcomputer 100 determines whether or not the clear signal is in the on state in step S7 shown in FIG. 27, based on the setting in step S9, After waiting for a predetermined delay time to elapse in steps S10 and S11, it is possible to execute a game control process for controlling the progress of the game. The delay time here is set to be delayed from when the game control process can be executed until at least the execution of various payout control processes by the payout control microcomputer 150 is started. ing. In this way, by executing the determination process in step S7 and waiting until a predetermined delay time elapses in steps S10 and S11, in the game control microcomputer 100 and the payout control microcomputer 150, the clear switch Since there is no difference in the timing for determining whether or not the detection signal from 304 is in the ON state, the game control microcomputer 100 and the payout control are in accordance with the operation on the clear switch 304 mounted on the power supply board 10. It is possible to execute initialization processing for surely performing settings at the time of initialization with the microcomputer 150, and it is possible to prevent the control state from being lost. In addition, when power supply to the pachinko gaming machine 1 is started, the game control microcomputer 100 and the payout control microcomputer 150 can be operated without continuing to operate the clear switch 304 until a predetermined delay time elapses. The initialization process can be surely executed by both. In addition, since the execution of the game control process by the game control microcomputer 100 is started after the various processes for the payout control by the payout control microcomputer 150 are started, the payout control microcomputer 150 is used for the game control microcomputer. The payout control command from the computer 100 can be reliably received.

  In addition, similarly to the payout control microcomputer 150, the effect control microcomputer 120 mounted on the effect control board 12 does not execute delay processing when power supply to the pachinko gaming machine 1 is started. Therefore, the game control process is started after the control by the production control microcomputer 120 is started. Therefore, when the effect control command is transmitted from the main board 11 to the effect control board 12, the effect control microcomputer 120 can reliably receive the command and execute notification processing based on the received command. it can.

  Further, in the game control microcomputer 100, for example, the CPU 104 confirms the state of the clear signal in step S7 before executing the delay processing based on the setting in step S9. It is possible to reduce the possibility that the control states cannot be matched.

  In the gaming control microcomputer 100, when power supply to the pachinko gaming machine 1 is started, for example, before the CPU 104 determines whether or not the clear signal is on in step S7 shown in FIG. It is determined whether or not the power-off signal output from the power supply monitoring circuit 303 mounted on the power supply substrate 10 has been turned off in the process of step S5 executed at step S5. Then, after the power-off signal is turned off, it is determined whether or not the clear signal is turned on in step S7. In addition, when the supply of power to the pachinko gaming machine 1 is started, the payout control microcomputer 150 also, for example, before determining whether or not the clear signal is in the on state in step S508 shown in FIG. In the process of step S505 to be executed, it is determined whether or not the power-off signal from the power supply board 10 has been turned off, and the process proceeds to step S508 after being turned off. Thus, by checking the state of the clear signal after the stability of the power supply voltage supplied from the power supply substrate 10 is confirmed, the output state of the clear signal (on state or off state) is ensured. For example, it can be detected that the clear signal is on even though the clear signal is off, or it can be detected that the clear signal is off even though the clear signal is on. It is possible to prevent erroneous detection such as.

  As shown in FIG. 6, the power supply monitoring circuit 303 is mounted on the power supply board 10. Then, the power-off signal output from the power supply monitoring circuit 303 is input to the payout control board 15 and then transmitted from the payout control board 15 to the main board 11, so that the payout control board 15 and the main control board 15 and the main control board 15 are transmitted. The wiring configuration can be simplified and the cost of the pachinko gaming machine 1 can be reduced as compared with the case where the wiring for transmitting the power-off signal is connected to both the boards 11. The power supply board 10 and the payout control board 15 are installed in the gaming machine frame 3, while the main board 11 is installed in the game board 2 to transmit a power-off signal from the power supply board 10. Can be simplified, and the wiring length can be shortened to make it less susceptible to noise.

  In the game control microcomputer 100, for example, when the CPU 104 determines that the prize ball ACK reception flag is ON in step S421 shown in FIG. 39, the command transmission number counter is incremented by 1 in step S425. When it is determined in step S301 shown in FIG. 41 that the detection signal from the all winning ball detection switch 29 is on, the command transmission counter is decremented by 1 in step S302. Based on the value of the number counter, the difference between the number of times one of the first to third payout number designation commands is transmitted and the number of game balls detected according to the detection signal from the all winning ball detection switch 29 Specify as a difference. When the process of step S303 shown in FIG. 41 is executed and it is determined that the difference in the number of winnings has reached the excessive ball reference value, which is one of the abnormality determination values, the process of step S304 is executed and the excessive number of winning balls A notification command is transmitted to the effect control board 12. Also, when it is determined that the winning number difference has reached the shortage reference value, which is one of the abnormality determination values, by executing the process of step S305 shown in FIG. A notification command is transmitted to the effect control board 12. On the side of the effect control board 12, when it is determined that the process of step S945 shown in FIG. 63 is performed and the award ball excessive notification command has been received, the process of step S946 is performed to indicate that excessive award balls have occurred. Notification. Also, when it is determined that the winning ball shortage notification command has been received by executing the processing of step S948 shown in FIG. 63, the processing of step S949 is executed to notify that the shortage of winning balls has occurred. Accordingly, it is possible to detect that an abnormality has occurred in the number of game balls to be paid out as prize balls without directly counting the number of game balls to be paid out as prize balls. In addition, since the number of game balls won in the winning opening is smaller than the number of game balls paid out as prize balls, the amount of data stored can be reduced. Further, it is possible to specify the difference between the number of payout number designation command transmissions and the number of game balls detected by the all winning ball detection switch 29 as a winning number difference by simply updating the count value in one command transmission number counter. Therefore, it is possible to determine whether an abnormality has occurred in the number of game balls to be paid out as prize balls while suppressing an increase in control burden. In addition, since it is only necessary to store the count value in one command transmission number counter, the data storage amount can be reduced as compared with the case where the count values in a plurality of counters are used.

  The game control microcomputer 100 includes the serial communication circuit 108 and the payout control microcomputer 150 includes the serial communication circuit 218, so that bidirectional serial communication can be performed. Then, between the game control microcomputer 100 and the payout control microcomputer 150, for example, as shown in FIG. 10A, a payout control command in which the first byte of the 2-byte structure is inverted to the second byte, A payout notification command is generated and transmitted / received. In the game control microcomputer 100, for example, the CPU 104 calculates the exclusive OR of the first byte and the second byte of the received command in step S335 shown in FIG. It is determined whether or not the payout notification command transmitted from the mounted payout control board 15 has been correctly received. On the other hand, in the payout control microcomputer 150, for example, the CPU 214 calculates the exclusive OR of the first byte and the second byte of the received command in step S605 shown in FIG. It is determined whether the payout control command transmitted from the mounted main board 11 has been correctly received. Thereby, the management of commands transmitted and received between the main board 11 and the payout control board 15 becomes easy and reliable, and it is possible to easily and reliably detect an error during command transmission and reception and receive an erroneous command. The game control microcomputer 100 and the payout control microcomputer 150 can be easily matched.

  As shown in FIG. 6, the clear switch 304 is mounted on the power supply substrate 10. The clear signal output from the clear switch 304 is input to the main board 11 and then transmitted from the main board 11 to the payout control board 15, so that the main board 11 and the payout control board 15 are transmitted from the power supply board 10. The wiring configuration can be simplified and the cost of the pachinko gaming machine 1 can be reduced as compared with the case where the wiring for transmitting the clear signal is connected to both sides, and the wiring length is shortened and hardly affected by noise. can do.

  In the random number circuit 103, for example, from the predetermined initial value to the predetermined final value in a predetermined range in which the numerical data C2 can be updated based on the input of the clock signal S1 input from the clock signal output circuit 171 by the random number generation circuit 173B. The data is updated cyclically according to a predetermined order (for example, an order of “1 → 2 →... → 65535”). On the other hand, the latch signal generation circuit 180 synchronizes the output signal from the timer circuit 179 according to the input of the start winning signal SS as the latch signal SL in synchronization with the inverted clock signal S2 output by the inverter circuit 178. Output. Thereby, acquisition of a random number value can be performed reliably and stably.

  Further, when an error interrupt request corresponding to the occurrence of an error in the serial communication circuit 108 such as an overrun error, noise error, framing error, parity error, or the like is notified to the CPU 104, for example, the CPU 104 preliminarily executes serial communication error interrupt processing. A predetermined process is executed to set the transmission operation unit and the reception operation unit provided in the serial communication circuit 108 to an unused state. In addition, if the highest priority interrupt setting (KHPR) stored in the ROM 105 is a value other than “06h” and “07h”, as shown in FIGS. 20A and 20B, the serial communication circuit 108 When a plurality of types of interrupt requests are generated at the same time, the error interrupt request is notified to the CPU 104 with priority over other interrupt requests such as a reception interrupt request and a transmission interrupt request. Thus, when an error occurs in the serial communication circuit 108, the serial communication operation is immediately stopped, and it is possible to prevent erroneous information from being transmitted due to the occurrence of an abnormality in the serial communication.

  When power supply to the pachinko gaming machine 1 is started, for example, the CPU 104 provided in the gaming control microcomputer 100 executes the interrupt initial setting process in step S24 shown in FIG. The highest priority interrupt setting (KHPR) is read, and the highest priority interrupt is set based on the read value. By executing this process, the priority order of the interrupt process can be changed from the default setting shown in FIG. Thereafter, for example, when the CPU 104 executes the process of step S25 shown in FIG. 27, the game control microcomputer 100 is set to the interrupt-permitted state. Also in the payout control microcomputer 150, when power supply to the pachinko gaming machine 1 is started, for example, the CPU 214 executes the same processing as step S24 in step S519 shown in FIG. Changing the priority order of interrupt processing from the default setting shown in FIG. 20B by reading the stored highest priority interrupt setting (KHPR) and setting the highest priority interrupt based on the read value. Can do. Thereafter, the payout control microcomputer 150 is set to an interrupt-permitted state, for example, by executing the process of step S520 shown in FIG. Thereby, after the execution of the interrupt process is permitted, the interrupt process can be surely executed according to the changed priority order. In addition, by changing the priority of interrupt processing from the initial setting before the execution of interrupt processing is permitted, a program that controls interrupt processing to be executed according to a predetermined priority every time various types of interrupts occur Since there is no need to execute, the degree of freedom of design can be increased.

  In the setting of the highest priority interrupt by executing the interrupt initial setting process in steps S24 and S519, for example, the interrupt process based on the timer interrupt request corresponding to the highest priority interrupt setting data as shown in FIG. The priority order with respect to the interrupt processing based on the interrupt request notified from the serial communication circuits 108 and 218 can be set. Thereby, after the execution of the interrupt process is permitted, the interrupt process can be surely executed according to the set priority order. In addition, by enabling the priority of interrupt processing to be arbitrarily set before execution of interrupt processing is permitted, a program that controls interrupt processing to be executed according to a predetermined priority every time various interrupts occur Since it is possible to preferentially execute any predetermined interrupt processing, the degree of freedom in design can be increased.

  In the payout control microcomputer 150, for example, after the CPU 214 transmits the prize ball ACK command to the main board 11 by the setting in step S634 shown in FIG. 49, it is determined in step S643 that the feedback waiting time has elapsed. In step S644, the main board communication error flag is set to ON. When the main board communication error flag is turned on in this way, the processing in step S721 shown in FIG. 52 is executed, so that the processing in step S722 and subsequent steps is not executed, and the payout control normal processing ends. When the process of step S801 shown in FIG. 5 is executed, the award ball payout number calculation process is terminated without executing the processes after step S802. Therefore, when it is determined that the ACK feedback command from the main board 11 has not been received, the value of the award ball non-payout counter becomes a value other than “0” and a game ball that becomes an unpaid award ball Even if it shows that there exists, it will be controlled to the state which stops payout control. Thereby, reliable payout control is executed, and it is possible to prevent excessively paying out game balls as prize balls when, for example, an abnormality due to a communication error or an illegal act on a communication line occurs.

  Further, in the payout control microcomputer 150, for example, when the CPU 124 sets the main board communication error flag to the ON state in step S644 shown in FIG. 49, the process of step S601 shown in FIG. The payout side reception process is terminated without executing the processes after S602. For this reason, when it is determined that the ACK feedback command from the main board 11 has not been received, control is performed to stop receiving the payout number designation command transmitted from the main board 11. Thereby, reliable payout control is executed, and it is possible to prevent excessively paying out game balls as prize balls when, for example, an abnormality due to a communication error or an illegal act on a communication line occurs.

  In the payout-side error canceling process in step S538 shown in FIG. 47, it is determined whether or not the detection signal from the error canceling switch 73 is in the on state. Thus, the state in which the payout control is prohibited can be canceled by turning it off. Thereby, for example, after a game store clerk inspects for an abnormality, the game can be continued while maintaining the control state before the inspection.

  In the embodiment described above, the clock signal S1 output from the clock signal output circuit 171 included in the random number circuit 103 is input to the inversion circuit 178, and the inversion circuit 178 inverts the signal level of the clock signal S1. By inputting the generated inverted clock signal S2 to the latch signal generating circuit 180, the latch signal generating circuit 180 synchronizes the output signal from the timer circuit 179 with the inverted clock signal S2 and outputs it as the latch signal SL. It is configured. On the other hand, a delayed clock signal generated by delaying the clock signal S1 output from the clock signal output circuit 171 by a period different from an integer multiple of the period of the clock signal S1 is generated as a latch signal generation circuit 180. You may make it input into. FIG. 66 is a block diagram illustrating an example of a configuration in which a delayed clock signal is input to the latch signal generation circuit 180.

  In the configuration shown in FIG. 66, the delay circuit 182 delays the clock signal S1 output from the clock signal output circuit 171 by a period that is different from a period that is an integral multiple of the period of the clock signal S1, thereby delaying the delayed clock signal S3. Is generated. The delay circuit 182 outputs the generated delayed clock signal S3 to the latch signal generation circuit 180. The latch signal generation circuit 180 generates the latch signal SL by outputting the output signal from the timer circuit 179 in synchronization with the rising edge of the delayed clock signal S3 output from the delay circuit 182.

  FIG. 67 is a timing chart for explaining the operation of random number circuit 103 having the configuration shown in FIG. An internal system clock CLK as shown in FIG. 67A is input to the clock input terminal of the clock signal output circuit 171 and the clock input terminal of the timer circuit 179 provided in the random number circuit 103. The internal system clock CLK may be generated by the clock circuit 101 provided in the game control microcomputer 100.

  The clock signal output circuit 171 divides the internal system clock CLK to generate a clock signal S1 shown in FIG. 67B that rises from a low level to a high level at timings T31, T32,. Here, the period of the clock signal S1 output from the clock signal output circuit 171 is T. In the operation example shown in FIG. 67, for the sake of explanation, a case where the clock signal output circuit 171 generates the clock signal S1 by dividing the internal system clock CLK by two is shown. However, in practice, as a cycle for updating the 16-bit random number, either the cycle of the internal system clock CLK or a cycle 16 times the internal system clock CLK is set. Therefore, the clock signal output circuit 171 only has to be able to switch between the case where the internal system clock CLK is output as it is as the clock signal S1 and the case where the signal obtained by dividing the internal system clock CLK by 16 is output as the clock signal S1. . The clock signal S1 output from the clock signal output circuit 171 is input to a random number generation circuit 173B and a delay circuit 182 provided for generating a 16-bit random number.

  The random number generation circuit 173B updates the numerical data C2 in response to the rising edge of the clock signal S1 input to the clock input terminal, and outputs the numerical data C2 to the random number sequence change circuit 176B. The delay circuit 182 delays the clock signal S1 output from the clock signal output circuit 171 by ΔT (≠ nT: n is an integer) and, for example, a period T rising from a low level to a high level at timings T41, T42,. The delayed clock signal S3 shown in FIG. 67 (C) is generated. The delayed clock signal S3 generated by the delay circuit 182 is output to the latch signal generation circuit 180.

  When the start winning signal SS shown in FIG. 67D is input to the timer circuit 179, when the elapsed time from the rising edge reaches a predetermined time (for example, 3 milliseconds), the output signal from the timer circuit 179 is low. Rise from level to high level. The output signal from the timer circuit 179 is input to the latch signal generation circuit 180, and is output as a latch signal SL as shown in FIG. 67 (E) in synchronization with the rising edge of the delayed clock signal S3. As a result, the random number generation circuit 173B updates the numerical data C1 at timings T31, T32,..., While the latch signal generation circuit 180 outputs a latch signal SL that rises at a timing T43 different from the timings T31, T32,. Can do.

  According to the above configuration, in the random number circuit 103, for example, the random number generation circuit 173B is predetermined within a predetermined range in which the numerical data C2 can be updated based on the input of the clock signal S1 input from the clock signal output circuit 171. Are updated cyclically according to a predetermined order (for example, an order of “1 → 2 →... → 65535”) from the initial value to a predetermined final value. On the other hand, the latch signal generation circuit 180 synchronizes the output signal from the timer circuit 179 according to the input of the start winning signal SS with the delay clock signal S3 output by the delay circuit 182 as the latch signal SL. Output. Thereby, acquisition of a random number value can be performed reliably and stably.

  The present invention is not limited to the above embodiment, and various modifications and applications are possible. For example, in the random number circuit 103 configured as shown in FIG. 12, the clock signal S1 output from the clock signal output circuit 171 is input to the random number generation circuit 173B and the inverting circuit 178, and the inverting circuit 178 has the signal level of the clock signal S1. Inverted clock signal S2 generated by inverting is input to latch signal generation circuit 180. In contrast, the clock signal S1 output from the clock signal output circuit 171 is input to the latch signal generation circuit 180 and a predetermined inversion circuit, and the inversion clock generated by the inversion circuit inverting the signal level of the clock signal S1. The signal may be input to the random number generation circuit 173B. In this case, the random number generation circuit 173B is predetermined from a predetermined initial value to a predetermined final value within a predetermined range in which the numerical data C2 can be updated based on the input of the inverted clock signal output from the inverting circuit. Update cyclically according to order. On the other hand, the latch signal generation circuit 180 synchronizes the output signal from the timer circuit 179 in response to the input of the start winning signal SS in synchronization with the clock signal S1 output from the clock signal output circuit 171. Output as. Such a configuration also makes it possible to reliably and stably acquire a random value.

  For example, in the random number circuit 103 configured as shown in FIG. 66, the clock signal S1 output from the clock signal output circuit 171 is input to the random number generation circuit 173B and the delay circuit 182, and the delay circuit 182 receives the clock signal S1. The delayed clock signal S3 generated by the delay is input to the latch signal generation circuit 180. In contrast, the clock signal S1 output from the clock signal output circuit 171 is input to the latch signal generation circuit 180 and a predetermined delay circuit, and the delay clock signal generated by the delay circuit delaying the clock signal S1 is a random number. You may comprise so that it may input into the production | generation circuit 173B. In this case, the random number generation circuit 173B is predetermined from a predetermined initial value to a predetermined final value within a predetermined range in which the numerical data C2 can be updated based on the input of the delayed clock signal output from the delay circuit. Update cyclically according to order. On the other hand, the latch signal generation circuit 180 synchronizes the output signal from the timer circuit 179 in response to the input of the start winning signal SS in synchronization with the clock signal S1 output from the clock signal output circuit 171. Output as. Such a configuration also makes it possible to reliably and stably acquire a random value.

  In the above embodiment, the stored value update signal KT from the random value register 181A is input to the clock input terminal of the random number generation circuit 173A provided for the 12-bit random number, and the stored value update signal KT is changed from the low level to the high level. In the description, the numerical data C1 is updated in response to the rise. However, the present invention is not limited to this. For example, the numerical data C1 may be updated at a constant period by inputting a clock signal having a predetermined period to the clock input terminal of the random number generation circuit 173A. As an example, the clock signal S1 output from the clock signal output circuit 171 is also input to the random number generation circuit 173A, and has the same configuration as the inverting circuit 178, timer circuit 179, and latch signal generation circuit 180 provided for 16-bit random numbers. May be provided for a 12-bit random number. Further, a clock signal output from a clock signal output circuit provided separately from the clock signal output circuit 171 may be input to the random number generation circuit 173A. In this case, the clock signal output circuit that generates the clock signal input to the random number generation circuit 173A inputs the internal system clock CLK supplied from the clock circuit 101, similarly to the clock signal output circuit 171 in the above embodiment. Thus, a clock signal having the same cycle as the internal system clock CLK or a clock signal obtained by dividing the internal system clock CLK by 16 may be output. As a result, for the 12-bit random number, for example, the random number generation circuit 173A is predetermined from a predetermined initial value to a predetermined final value within a predetermined range in which the numerical data C1 can be updated based on the input of a predetermined clock signal. The latch signal generation circuit provided for the 12-bit random number is updated in accordance with the order of the external signals such as the start winning signal SS. The output signal from the timer circuit according to the input can be output as a latch signal in synchronization with the inverted clock signal output from the inverting circuit, and the 12-bit random number can be acquired reliably and stably. . In this case, similarly to the configuration for 16-bit random numbers, the inversion circuit for 12-bit random numbers may be replaced with a delay circuit, or an inversion circuit or the like between the clock signal output circuit and the random number generation circuit 173A may be used. A delay circuit may be provided. In addition, the configuration for generating the 12-bit random number in the above embodiment may have the same function as the configuration for generating the 16-bit random number, or the configuration for generating the 16-bit random number. May have the same function as the configuration for generating a 12-bit random number.

  In the above-described embodiment, the game control microcomputer 100 includes the serial communication circuit 108 and the payout control microcomputer 150 includes the serial communication circuit 218. The game control microcomputer 100 and the payout control microcomputer It has been described that both computers 150 perform serial communication. However, the present invention is not limited to this, and it is sufficient that at least one of the game control microcomputer 100 and the payout control microcomputer 150 has a configuration for performing serial communication. In the following, one of the game control microcomputer 100 and the payout control microcomputer 150 having a serial communication circuit is referred to as a first microcomputer, and the other microcomputer having no serial communication circuit is referred to as a second microcomputer. A microcomputer. In this case, the second microcomputer may include, for example, a serial-parallel conversion circuit (for example, a shift register) that converts data transmitted from the first microcomputer via a serial communication line into parallel data. Alternatively, the second microcomputer may sample the data transmitted from the first microcomputer at a predetermined period to obtain the data transmitted via the serial communication line.

  Communication data may be transmitted from the second microcomputer to the first microcomputer by parallel communication using a plurality of data communication lines. The first microcomputer may be provided with input ports corresponding to a plurality of data communication lines so as to acquire communication data transmitted by parallel communication. In this case, in the serial communication circuit included in the first microcomputer, only the transmission operation unit may be used, and the reception operation unit may be set to an unused state.

  In the above embodiment, the maximum value comparison circuits 177A and 177B compare the numerical data sequences R1 and R2 output from the random number sequence change circuits 176A and 176B with the predetermined maximum value, respectively, and the numerical data is less than the maximum value. By performing the operation of repeating the output of the reset signals MS1 and MS2 until a short time, a numerical value that becomes the updated random value within a sufficiently short elapsed time from the rising edge of the stored value update signal KT or the clock signal S1 In the above description, the data R1 and R2 are output. However, the present invention is not limited to this, and random number generation circuits 173A and 173B may be cleared (initialized) by output signals from maximum value comparison circuits 177A and 177B.

  For example, the maximum value comparison circuit 177A can refer to the maximum value and start value set for the 12-bit random number, and the random number sequence change circuit 176A uses the numerical data C1 output from the random number generation circuit 173A as the 12-bit random number. Are rearranged so as to be in a predetermined permutation within a range equal to or less than the maximum value set for use. Then, the maximum value comparison circuit 177A specifies the difference between the maximum value and the start value, and determines whether or not the number of updates of the numerical data sequence R1 output from the random number sequence change circuit 176A matches the difference. . At this time, when the number of updates of the numerical data string R1 reaches the difference between the maximum value and the start value, the value of the numerical data C1 output from the random number generation circuit 173A reaches the maximum value set for the 12-bit random number. Therefore, the maximum value comparison circuit 177A inputs a predetermined count clear signal to the random number generation circuit 173A, and clears (initializes) the numerical data C1 generated by the random number generation circuit 173A. Thereafter, the random number generation circuit 173A sequentially counts up from the minimum value of the numerical data C1 output after clearing, for example, when the final value 1 smaller than the start value is reached, for example, the random number round trip signal RIJ1. Output.

  Further, the maximum value comparison circuit 177B can refer to the maximum value and start value set for 16-bit random numbers, and the random number sequence change circuit 176B uses the 16-bit random number data C2 output from the random number generation circuit 173B. Are rearranged so as to be in a predetermined permutation within a range equal to or less than the maximum value set for use. Then, the maximum value comparison circuit 177B specifies the difference between the maximum value and the start value, and determines whether or not the number of updates of the numerical data sequence R2 output from the random number sequence change circuit 176B matches the difference. . At this time, when the number of updates of the numerical data string R1 reaches the difference between the maximum value and the start value, the value of the numerical data C2 output from the random number generation circuit 173B reaches the maximum value set for 16-bit random numbers. Therefore, the maximum value comparison circuit 177B inputs a predetermined count clear signal to the random number generation circuit 173B, and clears (initializes) the numerical data C2 generated by the random number generation circuit 173B. Thereafter, the random number generation circuit 173B sequentially counts up from the minimum value of the numerical data C2 output after clearing, for example, when the final value that is 1 smaller than the start value is reached, for example, Output.

  In such a configuration, the start value is set so that the start value for the 12-bit random number is less than or equal to the maximum value for the 12-bit random number, and the start value for the 16-bit random number is less than or equal to the maximum value for the 16-bit random number. And set the maximum value. Further, when the permutation is changed by any one of the random number sequence changing circuits 176A and 176B, numerical data sequences R1 and R2 including a value larger than the maximum value for 12-bit random numbers and the maximum value for 16-bit random numbers are output. Set not to be done.

  In the above embodiment, the power supply monitoring circuit 303 is mounted on the power supply board 10. However, the present invention is not limited to this. For example, even if the power supply monitoring circuit is mounted on the dispensing control board 15. Good. In this case, the payout control board 15 inputs at least part of the power supply voltage (for example, VSL and VCC) supplied from the power supply board 10 to the power supply monitoring circuit, and when a drop in the power supply voltage is detected, a power-off signal is generated. Configure to be on. The power cut-off signal output from the power supply monitoring circuit is input to a predetermined input port provided in the payout control microcomputer 150 and can be transmitted to the main board 11 via, for example, a predetermined output circuit. do it. According to such a configuration, it is not necessary to provide a wiring for transmitting a power-off signal from the power supply board 10 to the payout control board 15, so that the wiring configuration can be further simplified. In addition, since the overall length of the wiring for transmitting the power-off signal is shortened, the possibility of noise on the power-off signal can be reduced.

  In the above-described embodiment, the clear switch 304 is mounted on the power supply board 10. However, the present invention is not limited to this, and for example, the clear switch may be mounted on the main board 11. In this case, the clear signal output from the clear switch is input to a predetermined input port provided in the game control microcomputer 100 and can be transmitted to the payout control board 15 via, for example, a predetermined output circuit. That's fine. According to such a configuration, it is not necessary to provide a wiring for transmitting a clear signal from the power supply substrate 10 to the main substrate 11, and therefore the wiring configuration can be further simplified. In addition, since the overall length of the wiring for transmitting the clear signal is shortened, the possibility of noise on the clear signal can be reduced.

  In the above embodiment, the power supply monitoring circuit 303 mounted on the power supply board 10 has been described as outputting a reset signal. However, the present invention is not limited to this. For example, the reset is performed on each control board including the main board 11. A reset circuit that outputs a signal may be mounted. Alternatively, a reset circuit is mounted on any one (one or a plurality of control boards) of a plurality of control boards, and a reset signal output from the reset circuit is sent to another control board that is not mounted with a reset circuit. You may make it supply. When the reset circuit is mounted on each control board, the voltage value when the reset signal becomes high level may be made different depending on each reset circuit. For example, when the reset signal output from the reset circuit mounted on the main board 11 is at a high level, the voltage value when the reset signal output from a reset circuit mounted on another control board is at a high level. It may be set so that the timing at which the reset signal input to the game control microcomputer 100 is turned off is the latest so as to be higher than the voltage value.

  In the above embodiment, when the supply of power to the pachinko gaming machine 1 is started, the clear signal is turned on in response to an operation such as pressing on the clear switch 304 mounted on the power supply board 10. In the above description, the game control microcomputer 100 and the payout control microcomputer 150 are set at initialization. However, the present invention is not limited to this, and when power supply to the pachinko gaming machine 1 is started, for example, an initialization command signal input from the outside of the pachinko gaming machine 1 is turned on. When a predetermined condition such as being present is established, the game control microcomputer 100 and the payout control microcomputer 150 may be set at initialization. As a specific example, the initialization command signal may be output from the hall management computer and input to the pachinko gaming machine 1, or detects an intruder or contact with the pachinko gaming machine 1. It may be output from a sensor or the like and input to the pachinko gaming machine 1.

  In the above embodiment, the DC voltage VLP (DC + 24V) obtained after rectifying and smoothing the AC power supply (AC24V) is monitored as a power supply monitoring means for detecting power supply interruption, and the monitored DC voltage is Exemplified what outputs a power-off signal when it is detected that the voltage is lower than a predetermined voltage, but is not limited to this, monitors the presence or absence of a full-wave rectified waveform in the middle of converting AC power (AC24V) to DC, A power-off signal may be output when the waveform cannot be detected for a predetermined period. Further, the AC power supply may be directly monitored, and a power-off signal may be output when the AC waveform cannot be detected for a predetermined period. In other words, the target to be monitored is not limited to the voltage, but may be a full-wave rectified waveform or a half-wave rectified waveform, as long as it can detect that the power supplied to the gaming machine is decreasing. The DC voltage to be monitored is not limited to VLP (DC + 24V), but may be VSL (DC + 30V), VDD (DC + 12V), or the like.

  The power-off signal may be input to an input port of the game control microcomputer and the payout control microcomputer, and the power-off process may be executed when it is determined that the power-off signal is on. Alternatively, a power-off signal may be input to the NMI terminal and the power-off process may be executed by a non-maskable interrupt process. Also, a power-off signal is input to the NMI terminal, a power-off flag is set according to the input of the power-off signal, and the state of the power-off flag is monitored by timer interrupt processing or main processing. A power-off process may be executed.

  In the above embodiment, the checksum data is created and the backup flag is set in the power-off process, and those are checked when the power is turned on. A process for clearing the port and a process for monitoring whether the power state has been restored (a process for restoring at the momentary power failure) may be executed. Further, the order of these processes is not limited to the present embodiment.

  In the above embodiment, the game control counter setting unit 135 is provided with the total prize ball number counter and the first to third payout number instruction counters. In the process of step S292 shown in FIG. A predetermined value is added to the value of the counter and any one of the first to third payout number instruction counters to be updated. In step S424 shown in FIG. 39, one of the values of the first to third payout number instruction counters corresponding to the value of the variable N is updated by 1 while any of steps S427, S429, and S430 is updated. By executing such processing, a predetermined value corresponding to the value of the variable N is subtracted from the value of the total prize ball counter and updated. Thus, in the above embodiment, when the game control microcomputer 100 determines that the prize ball ACK command from the payout control board 15 has been received, the first to third payout number instruction counters. Update and update of the total prize ball counter. However, the present invention is not limited to this. For example, when a payout number designation command is transmitted, the first to third payout number instruction counters and the total prize ball number counter are updated. Good. In this case, the first to third payout number instruction counters are updated and the total award is made before the setting for transmitting the payout number designation command is performed by any of the processes of steps S408, S410, and S411 shown in FIG. The ball counter may be updated, or after performing the setting of transmitting a payout number designation command by executing any of the processes of steps S408, S410, and S411 shown in FIG. Prior to determining whether or not the prize ball ACK command from the board 15 has been received, the first to third payout number instruction counters or the total prize ball number counter may be updated.

  Further, the game control counter setting unit 135 is not limited to the one having the total prize ball number counter and the first to third payout number instruction counters, and the number of game balls that the game control microcomputer 100 should pay out as a prize ball. Any data can be used as long as it can store data that can be specified. For example, the game control counter setting unit 135 is provided with the total prize ball number counter, but the first to third payout number instruction counters may not be provided. In this case, the number of game balls to be paid out is “1” based on the bit values of the third to 0th bits [bits 3-0] in the first and second bytes of the payout number designation command shown in FIG. "To" 15 "can be specified. Then, the number of prize balls to be paid out is specified from the value of the total prize ball number counter, and a payout number designation command for instructing the specified number of prize balls as the number of payouts is sent from the main board 11 to the payout control board 15. What is necessary is just to make it transmit. At this time, if the value of the total prize ball counter is larger than the maximum number of payouts (for example, “15”) that can be instructed by the payout number designation command, the maximum payout number is indicated. The payout number designation command may be transmitted, the value of the total prize ball number counter may be updated, and the payout number designation command may be further transmitted based on the updated total prize ball number counter value.

  Alternatively, the game control counter setting unit 135 is provided with the first to third payout number instruction counters, but the total prize ball number counter may not be provided. In this case, the value of any of the first to third payout number instruction counters may be updated corresponding to the ON switch in step S292 shown in FIG. 37A, and step S425 shown in FIG. After executing the process of step S431, the process may proceed to step S431.

  In the above embodiment, when it is determined in step S421 shown in FIG. 39 that the prize ball ACK command is received from the payout control board 15 because the prize ball ACK reception flag is ON, the process of step S425 is performed. The process is executed and the value of the command transmission counter is incremented by one. However, the present invention is not limited to this. For example, when a payout number designation command is transmitted, the value of the command transmission number counter may be incremented by one. In this case, the value of the command transmission number counter is incremented by 1 before setting for transmitting the payout number designation command by any of the processes of steps S408, S410, and S411 shown in FIG. Alternatively, after performing any of the processes of steps S408, S410, and S411 shown in FIG. 38 and performing the setting for transmitting the payout number designation command, the prize ball ACK command from the payout control board 15 is received. Before the determination of whether or not, the value of the command transmission counter may be incremented by one. Thus, even when the value of the command transmission counter is incremented by 1 when the payout number designation command is transmitted, the number of game balls to be paid out as prize balls is not counted directly, and the game balls to be paid out as prize balls are counted directly. It is possible to detect that an abnormality has occurred in the number. In addition, since the number of game balls won in the winning opening is smaller than the number of game balls paid out as prize balls, the amount of data stored can be reduced. Further, it is possible to specify the difference between the number of payout number designation command transmissions and the number of game balls detected by the all winning ball detection switch 29 as a winning number difference by simply updating the count value in one command transmission number counter. Therefore, it is possible to determine whether an abnormality has occurred in the number of game balls to be paid out as prize balls while suppressing an increase in control burden. In addition, since it is only necessary to store the count value in one command transmission number counter, the data storage amount can be reduced as compared with the case where the count values in a plurality of counters are used. A counter for counting the number of transmissions of the first to third payout number designation commands and a counter for counting the number of game balls detected by the all winning ball detection switch 29 are provided separately. The difference between the values of the counters may be specified as a winning number difference.

  In the above embodiment, the switch process of step S72 and the special symbol process process of step S80 are executed in the game control timer interrupt process as shown in FIG. Here, for example, when the detection signal from the start port switch 22 is in the ON state in the switch process of step S72, the timer value in the start port switch timer is incremented by one. In the special symbol process in step S80, for example, in step S351 shown in FIG. 43, it is determined that the timer value in the start switch timer is a predetermined switch-on determination value (for example, “2”). Sometimes, the random number value is read from the random number value register 181B included in the random number circuit 103 in the winning process in step S352. On the other hand, in the timer interrupt processing for game control, the start port switch timer is updated according to whether or not the detection signal from the start port switch 22 is in an on state, and the timer value is set to a predetermined switch. When a predetermined start winning flag is set to the on state when the on determination value is reached, the random number value is read from the random number circuit 103 when the power-off signal is in the off state in step S26 shown in FIG. It may be performed in a loop process executed in step (b).

  In this case, in the game control timer interrupt process, for example, only the processes of steps S71, S72, and S85 among the processes shown in FIG. 31 are executed. In the switch process of step S72, when the detection signal from the start port switch 22 is in the ON state, the timer value in the start port switch timer is updated to be incremented by one, while the detection from the start port switch 22 is performed. When the signal is off, the start port timer is cleared. When the timer value in the start port switch timer reaches the switch-on determination value, the start winning flag provided in the game control flag setting unit 133 is set to the on state. On the other hand, when the power-off signal is in the OFF state in step S26 shown in FIG. 27, the processes in steps S73 to S84 shown in FIG. 31 are executed and then the process returns to step S26. Here, in the special symbol process in step S80, the process for determining whether or not the start winning flag is on is executed as the process in step S351 shown in FIG. Then, when the start winning flag is on, the winning process of step S352 may be executed, and the random number value may be read from the random number circuit 103 and stored in the special figure storage unit 131. Thereby, it is possible to prevent an increase in the processing amount of the CPU 104 included in the game control microcomputer 100 when a timer interrupt occurs, and to reduce the control burden when the timer interrupt occurs.

  In the above embodiment, when it is determined that the production control microcomputer 120 has received the full tank notification start command in step S954 shown in FIG. 63, the full tank notification screen as illustrated in FIG. After the displayed image is displayed on the image display device 5, the full tank notification screen is continuously displayed until it is determined in step S952 shown in FIG. 63 that the full tank notification end command has been received. However, the present invention is not limited to this. For example, as in the case of displaying the excessively high prize ball notification screen illustrated in FIG. 64 (A) or the shortage of bonus ball notification screen illustrated in FIG. 64 (B), When the timing to end the notification is reached, the display of the full notification screen or the like may be ended. In this case, since it is not necessary to transmit a command for instructing the end of notification from the main board 11 to the effect control board 12, the control burden on the game control microcomputer 100 can be reduced.

  In the above embodiment, it is determined whether or not the main board communication error flag is on in step S801 in the prize ball payout number calculation process shown in FIG. finish. Further, in step S821 in the prize ball payout driving process shown in FIG. 55, it is determined whether or not the main board communication error flag is turned on. If it is turned on, the process proceeds to step S839 to play the game by the payout motor 51. The ball dispensing operation is stopped. On the other hand, in the ball lending / dispensing number calculation process shown in FIG. 58 and the ball lending / dispensing drive process shown in FIG. 59, it is not determined whether or not the main board communication error flag is on. However, the present invention is not limited to this. For example, when the ball lending / dispensing number calculation process shown in FIG. 58 is started, it is first determined whether or not the main board communication error flag is turned on. In some cases, the ball lending / dispensing number calculation processing may be terminated as it is. When the ball lending / dispensing drive process shown in FIG. 59 is started, it is first determined whether or not the main board communication error flag is turned on. If it is turned on, the process proceeds to step S896 to play the game by the payout motor 51. The ball payout operation may be stopped. Thus, when it is determined that the ACK feedback command from the main board 11 has not been received, the value of the ball lending unpaid counter becomes a value other than “0” and becomes a non-paid lending ball. Even if it indicates that there is, there is a control to stop the payout control. Thereby, reliable payout control is executed, and it is possible to prevent excessively paying out the game balls to be rented when, for example, an abnormality due to a communication error or an illegal act on the communication line occurs.

  In the above embodiment, the detection signal output from the start port switch 22 is input to the timer circuit 179 provided in the random number circuit 103 as the start winning signal SS. The timer circuit 179 measures the time during which the start winning signal SS is input. When the measured time reaches a predetermined time (for example, 3 milliseconds), the start winning signal SS is latched. Was output. However, the present invention is not limited to this. The detection signal from the start port switch 22 is input to the CPU 104, and the CPU 104 executes a game control timer interrupt process a predetermined number of times (for example, twice) (for example, The latch start winning signal SN may be sent to the latch signal generation circuit 180 when the detection signal from the start port switch 22 is continuously on for 4 milliseconds). In this case, the timer circuit 179 included in the random number circuit 103 as shown in FIG. 12 is not necessary. For example, the latch start winning signal SN output from the CPU 104 is input to the D input terminal included in the latch signal generation circuit 180. Then, the inverted clock signal S2 output from the inverter circuit 178 and the delayed clock signal S3 output from the delay circuit 182 may be input to the clock input terminal included in the latch signal generation circuit 180. The latch signal generation circuit 180 outputs the latch start winning signal SN input to the D input terminal in synchronization with the rising edge of the inverted clock signal S2 or the delayed clock signal S3 input to the clock input terminal. A latch signal SL is generated and output. In addition, in the process of step S341 shown in FIG. 43, the period required from when the detection signal from the start port switch 22 is turned on until the latched start winning signal SN for the on state is sent to the latch signal generation circuit 180. When the detection signal from the start port switch 22 is in the on state for a longer time, it may be determined that the start winning signal from the start port switch 22 is in the on state. As a specific example, when the detection signal from the start port switch 22 is continuously on for 4 milliseconds, which is a period for executing two game control timer interrupt processes, the start winning for the latch in the on state is performed. When the signal SN is sent to the latch signal generation circuit 180, the switch-on determination value to be compared with the timer value in the start-up switch timer in step S341 is set in advance to a value larger than “2” (eg, “3”). Set it up. When the timer value in the start port switch timer has reached the switch-on determination value, it is determined that the start winning signal is in the on state, and the winning process in step S342 is executed. Thus, the special symbol display is performed when the detection signal from the start port switch 22 is continuously on until the number of times of execution of the game control timer interrupt process reaches a predetermined number corresponding to the switch-on determination value. It is determined that the execution condition of the special figure game by the device 4 is established. On the other hand, the start start signal SN for latch is the start port switch 22 for 4 milliseconds, which is shorter than the time until the number of executions of the game control timer interrupt process reaches the predetermined number corresponding to the switch-on determination value. The on-state is set on condition that the detection signal from is continuously on.

  In the above embodiment, the timer circuit 179 measures the input time of the start winning signal SS using the internal system clock CLK. However, the present invention is not limited to this, and the clock signal obtained by dividing the internal system clock CLK. Alternatively, a clock signal different from the internal system clock CLK generated by the clock circuit 101 may be used. For example, the timer circuit 179 may measure the input time of the start winning signal SS using the clock signal S1 output from the clock signal output circuit 171. Further, in the above embodiment, the timer circuit 179 is set to 3 milliseconds as the predetermined time, but is not limited to this, and is 4 milliseconds which is the execution time of two game control timer interrupt processes. Any time shorter than a second can be set.

  Furthermore, in the above embodiment, the CPU 104 determines that the start winning signal is continuously input over the period (4 milliseconds) in which the two game control timer interruption processes are executed, as shown in FIG. The winning process of step S352 shown in FIG. However, the present invention is not limited to this, and the number of executions of the above-described game control timer interrupt process is arbitrary. For example, the CPU 104 has a period during which three game control timer interrupt processes are executed ( The winning process may be executed on the basis that the start winning signal is continuously input for 6 milliseconds). In this case, the timer circuit 179 may be set to a time shorter than 6 milliseconds, which is the execution time of three game control timer interruption processes.

  In the above embodiment, among the special symbols composed of numbers such as “0” to “9”, the special symbol indicating “7” is the jackpot symbol, and the special symbol indicating other numerical values is the lost symbol. In the above description, it is assumed that whether or not the game state becomes a probable big hit that becomes a high probability state is determined separately from the special symbol. However, the present invention is not limited to this, and the probability variation big hit symbol that is a big hit symbol when the gaming state is a high probability state and the normal big hit when the gaming state does not become a high probability state. The normal big hit symbol which is a big hit symbol may be a different special symbol. For example, a special symbol indicating “3” may be a normal jackpot symbol, and a special symbol indicating “7” may be a probability variation jackpot symbol. In this case, among the commands 90XXh serving as the display result notification command, the command 9001h is a command for notifying that the confirmed special symbol in the special game is a special symbol indicating “3” as a normal jackpot symbol, 9002h may be a command for notifying that the confirmed special symbol in the special symbol game is a special symbol indicating “7” as the probability variation big hit symbol.

  In the above embodiment, when the detection signal from the full switch 26 is on in step S308 shown in FIG. 41, a full tank notification start command is transmitted to the effect control board 12 by the setting in step S310. Then, the effect control microcomputer 120 performs the process of step S955 shown in FIG. 63, whereby the image display device 5 displays an image that becomes a full tank notification screen as illustrated in FIG. It has been described as a notification that 33 is full. However, the present invention is not limited to this, and any operation may be performed as long as it performs an arbitrary operation for recognizing from the outside that the lower plate 33 is full. For example, in the process of step S310, the control data is set in a predetermined bit of the output port provided in the game control microcomputer 100, or the lamp for informing that the lower plate 33 is full or is turned on or It may be blinked or audio may be output.

  In the above embodiment, when the launching device 19 is driven, the main board 11 transmits an on-state launch permission signal to the launching device 19, and when the ball feeding device 62 is driven, the main substrate 11 sends the ball feeding device. An ON-state supply permission signal is transmitted to 62. In the launching device 19, the launch solenoid 19C is driven (excited) using the VSL transmitted from the power supply board 10 on condition that the launch permission signal from the main board 11 is turned on. While the ball can be launched, the ball feeding device 62 uses a VSL transmitted from the power supply board 10 to provide a ball feeding solenoid on condition that the supply permission signal from the main board 11 is on. Alternatively, the game ball can be supplied to the launching device 19 by driving the motor. However, the present invention is not limited to this, and when driving the launching device 19 and the ball feeding device 62, a driving voltage (for example, VSL) is supplied from the main board 11 to the firing device 19 and the ball feeding device 62. On the other hand, when the firing device 19 and the ball feeding device 62 are stopped, the supply of the drive voltage from the main board 11 to the firing device 19 and the ball feeding device 62 may be stopped. In this case, the CPU 104 provided in the game control microcomputer 100 executes a process for supplying a driving voltage to the launching device 19 as a process of step S223 shown in FIG. 33, and a step S226 shown in FIG. As the process, a process for supplying a driving voltage to the ball feeding device 62 may be executed. As a specific example, in the process of step S223, the launch device is set by turning on a launch drive switch provided in a transmission circuit that supplies a drive voltage from the power supply substrate 10 to the launch device 19 via the main substrate 11. When it is determined in step S221 that the firing permission control timer has timed out, the drive voltage is supplied to the launching device 19 by setting the firing drive switch to the OFF state. Can be stopped. Further, in the process of step S226, the supply drive switch provided in the transmission circuit that supplies the drive voltage to the ball feeder 62 from the power supply board 10 through the main board 11 is set to the on state, whereby the ball feeder 62 is turned on. While it is determined that the supply permission control timer has timed out in step S224, the drive voltage is supplied to the ball feeder 62 by setting the supply drive switch to the OFF state. Just stop.

  Moreover, when driving the launching device 19, the main board 11 has been described as transmitting an on-state launch permission signal to the launching device 19. The ball feeding device 62 is driven or stopped by transmitting a supply permission signal to the device 62, while the launching device 19 can drive the launching solenoid 19 </ b> C and launch a game ball without being controlled by the main board 11. You may make it become a state. As a specific example, a VL signal transmitted from the card unit 70 via the interface board 20 and a detection signal transmitted from the touch sensor 75 without passing through the main board 11 are sent to the AND circuit 19A included in the launching device 19. May be input. In this case, the solenoid drive voltage generation circuit 19B included in the launching device 19 uses the VSL supplied from the power supply substrate 10 when the VL signal and the detection signal from the touch sensor 75 are both on. The solenoid drive voltage corresponding to the operation amount detection signal from is generated. Alternatively, the solenoid drive voltage generation circuit 19 </ b> B included in the launching device 19 is configured to supply power when either the VL signal transmitted from the card unit 70 via the interface board 20 or the detection signal from the touch sensor 75 is on. A solenoid drive voltage corresponding to an operation amount detection signal from the operation knob 30 may be generated using VSL supplied from the substrate 10. Even in such a case, the ball feeder 62 does not supply the game ball to the launcher 19 during the period in which the supply permission signal from the main board 11 is in an off state, so that the game ball is not launched by the launcher 19. Can be. That is, when the touch sensor detection signal from the touch sensor 75 is in the on state and the detection signal from the full switch 26 is in the off state, the supply permission signal from the main board 11 to the ball feeder 62 is on. By entering the state, the ball feeding device 62 is driven and the game ball is supplied to the launching device 19, so that the game ball can be launched. Further, since it is not necessary to perform control for driving the launching device 19 on the main board 11, the control burden on the main board 11 can be reduced.

  Further, the launch permission signal sent from the main board 11 to the launching device 19 and the supply permission signal sent from the main board 11 to the ball feeding device 62 are transmitted via the switch circuit 111 on the main board 11. Based on the detection signal from the full switch 26 and the touch sensor detection signal from the touch sensor 75 input to the game control microcomputer 100, the game control microcomputer 100 performs the launch control process or step of step S73 shown in FIG. The description has been made assuming that it is generated by executing the input / output process of S74. However, the present invention is not limited to this. For example, a detection signal from the full switch 26 and a touch from the touch sensor 75 are connected to an AND circuit provided outside the game control microcomputer 100 on the main board 11. A sensor detection signal may be input, and an output signal from the AND circuit may be sent to the launching device 19 or the ball feeding device 62 as a launching permission signal or a supply permission signal.

  In the above embodiment, the wiring for receiving the detection signal from the full switch 26 and the ball break switch 27 is connected to the main board 11, and in step S723 shown in FIG. It has been described that it is determined whether or not the ball is in a broken state by checking whether or not a cut notification command has been received. However, the present invention is not limited to this, and the wiring from the full tank switch 26 and the ball break switch 27 is connected to the payout control board 15, and the full control switch 15 is connected to the main board 11 from the payout control board 15. 26 or a detection signal from the ball break switch 27 may be input. In this case, a detection signal is input to the payout control microcomputer 150 from the full switch 26 or the ball break switch 27 via the switch circuit 161, and a payout notification command corresponding to the state of these detection signals is issued. 15 may be transmitted to the main board 11. Alternatively, the detection signal from the full tank switch 26 or the ball break switch 27 is branched by a branch circuit provided outside the payout control microcomputer 150 on the payout control board 15, and one of them is sent to the payout control microcomputer 150. While inputting, the other may be transmitted to the main board 11. Then, in step S723 shown in FIG. 52, whether or not the ball is out of state by checking whether or not the detection signal input from the ball out switch 27 to the payout control microcomputer 150 is in the on state. What is necessary is just to determine.

  Alternatively, a wiring for receiving a detection signal from the full switch 26 or the ball break switch 27 is connected to the main board 11, and for example, by a branch circuit provided outside the game control microcomputer 100 on the main board 11, The detection signals from the full tank switch 26 and the ball break switch 27 may be branched so that one is input to the game control microcomputer 100 and the other is transmitted to the payout control board 15. Further, the detection signals from the full tank switch 26 and the ball break switch 27 are branched outside the main board 11 and the payout control board 15, and one is transmitted to the main board 11 and the other is transmitted to the payout control board 15. You may do it.

  In the above embodiment, there is no upper limit on the number of prize balls to be paid out continuously. However, the present invention is not limited to this, and the upper limit on the number of prize balls to be paid out continuously. A value (award ball continuous payout upper limit value) may be provided. For example, when “25” which is a value corresponding to the number of lending balls per unit (for example, 25) is set as the prize ball payout upper limit value, in the prize ball payout number calculation process shown in FIG. If the value obtained by the subtraction process in S805 is “25” or less, the process proceeds to step S806, and the subtraction value obtained in step S805 may be set in the payout motor rotation counter. On the other hand, when the value obtained by the subtracting process in step S805 is larger than “25”, “25” which is the winning ball continuous payout upper limit value is set to the winning ball unpaid counter, the previous unpaid counter, and the payout motor. Set to the rotation counter. At this time, a value obtained by further subtracting “25”, which is the upper limit of consecutive winning ball payouts, from the subtraction value obtained in step S805, is used as the carryover unpaid number, for example, a carryover unpaid number storage unit provided in the RAM 216 Are stored in a predetermined storage area. 54, when it is determined in step S801 that the main board communication error flag is off, or in step S802, the value of the prize ball unpaid counter is the number of payouts. When it is determined that the value is equal to or less than the counter value, it is determined whether or not a value other than “0” is stored in the carry-over unpaid-out number storage unit or the like. If a value other than “0” is stored when this determination process is executed, it is further determined whether or not the number of unpaid carry-outs is “25” or less. Here, if the number of unpaid unpaid is “25” or less, the unpaid unpaid number is set in the winning ball unpaid counter, the previous unpaid counter, and the payout motor rotation counter, and the stored unpaid number is cleared. And is initialized to “0”. On the other hand, when the number of unpaid unpaid is larger than “25”, the upper limit value “25”, which is the continuous unpaid prize ball, is set in the unpaid prize ball counter, the previous unpaid counter, and the dispense motor rotation counter, A value obtained by subtracting “25” from the number may be stored as a new carry-out unpaid number.

  In addition, in the prize ball payout driving process shown in FIGS. 55 and 56, the value obtained by the subtraction process in step S843 is added to the value of the payout motor rotation counter, and the obtained addition value is the prize ball continuous. It is determined whether or not the payout upper limit value is “25” or less. At this time, if the addition value is “25” or less, the process proceeds to step S844, and the increment in the value of the award ball non-payout counter is added to the value of the payout motor rotation counter and updated. On the other hand, when the addition value is larger than “25”, the prize ball continuous payout upper limit value “25” is set in the payout motor rotation counter, and the value of the payout motor rotation counter is calculated from the value of the prize ball non-payout counter. The obtained increment value may be set in the award ball unpaid counter.

  In the above embodiment, when the value of the award ball non-payout counter is equal to or smaller than the value of the number-of-payout counter in step S802 shown in FIG. 54, steps S803, S804, S812, It has been described that the process for S813 is executed to initialize the setting for controlling the payout operation of the game ball to be a prize ball. On the other hand, the setting for controlling the payout operation of the game ball serving as the prize ball may be initialized when the payout of the game ball serving as the prize ball ends normally. More specifically, when it is determined in step S833 shown in FIG. 55 that the value of the number-of-payout counter has reached the value of the award ball non-payout counter, this corresponds to steps S803, S804, S812, S813. Processing may be executed.

  In the above embodiment, the step shown in FIG. 55 is performed by setting the upper limit value of the number of failures compared with the value of the payout operation failure number counter in step S807 shown in FIG. 54 to an appropriate value (for example, “9”). After the value of the number-of-payout counter reaches the value of the award ball non-payout counter in S833, the payout number designation command is received at a stage before the prize ball payout number calculation processing in step S743 shown in FIG. 53 is executed. Even in such a case, it has been described that it is possible to appropriately detect a defect in a payout operation due to occurrence of a clogged ball in the payout motor 51 or the payout case 17 while preventing an error from being determined immediately. However, the present invention is not limited to this. For example, when it is determined in step S833 shown in FIG. 55 that the value of the payout number counter has reached the value of the award ball non-payout counter, The defect counter may be cleared and initialized. Thus, when the number of game balls detected by the payout count switch 72 becomes equal to the value of the award ball non-payout counter after the payout operation by the payout motor 51 is finished and before the payout completion waiting time elapses, It is possible to determine that the payout operation of the game ball to be a ball has been properly completed, and to immediately set the value of the payout operation failure number counter to the initial value.

  In the above embodiment, when it is determined in step S824 shown in FIG. 55 that the payout operation for paying out one game ball is not in progress, the value of the payout motor rotation counter is set in step S825. It is determined whether or not it is “0”, and if it is other than “0”, it has been described that the setting relating to the payout operation for paying out one game ball in step S828 is performed. However, the present invention is not limited to this. When it is determined in step S825 that the value of the payout motor rotation counter is other than “0”, the value of the payout motor rotation counter is determined in step S828. Settings relating to a payout operation for paying out game balls corresponding to the number of game balls may be made. In this case, as the processing of step S828, for example, an excitation pattern or an excitation period for causing the dispensing motor 51 to perform a dispensing operation for continuously dispensing gaming balls until the number corresponding to the value of the dispensing motor rotation counter is reached is set. It suffices if processing is executed. As a specific example, first, an excitation pattern corresponding to a payout operation in which the payout motor 51 pays out one game ball is prepared in a predetermined area of the ROM 215 in advance. In the process of step S828, the excitation period or the excitation signal is output so that the excitation signal according to the excitation pattern read from the predetermined area of the ROM 215 is repeatedly output to the payout motor 51 for the number of times corresponding to the value of the payout motor rotation counter. What is necessary is just to set the number of repetitions of the excitation pattern. At this time, the payout motor rotation counter is cleared in step S829, and the count value is set to “0”. In step S824, it may be determined whether or not the payout operation set in step S828 is being executed from the excitation time of the payout motor 51 or the detection result of the payout motor position sensor 71, for example. In addition, when it is determined in step S884 shown in FIG. 59 that the value of the payout motor rotation counter is other than “0”, the number corresponding to the value of the payout motor rotation counter in step S887. You may make it perform the setting regarding payout operation | movement for paying out a game ball. In this case, as a process of step S887, after performing a process for performing the same setting as the above-described setting in step S828, the payout motor rotation counter is cleared in step S888, and the count value is set to “0”. Set to. In step S883, it may be determined whether or not the payout operation set in step S887 is being executed based on, for example, the excitation time of the payout motor 51 or the detection result of the payout motor position sensor 71.

  In the above embodiment, the 12-bit random number maximum value (KRMS) read in step S107 shown in FIG. 29 is once set in the maximum value comparison circuit 177A included in the random number circuit 103 in step S108, and then in step S109. When it is determined that the maximum value for the 12-bit random number is not within the settable range, the predetermined value is reset as the maximum value in step S110. Also, the 16-bit random number maximum value (KRXS) read in step S129 shown in FIG. 30 is once set in the maximum value comparison circuit 177B included in the random number circuit 103 in step S130, and then for 16-bit random number in step S131. When it is determined that the value is not within the range that can be set as the maximum value, the predetermined value is reset as the maximum value in step S132. However, the present invention is not limited to this, and it is determined whether or not the read value from the ROM 105 is within a range that can be set as the maximum value. It may be set to 177A and 177B, and if it is not within the range, a predetermined value may be set as the maximum value. More specifically, after reading the 12-bit random number maximum value (KRMS) in step S107, first, it is determined whether or not the read value is within a range that can be set as the maximum value for the 12-bit random number. If it is within the range, the read value in step S107 is set in the maximum value comparison circuit 177A as it is. On the other hand, if the read value in step S107 is not within the range that can be set as the maximum value for the 12-bit random number, the maximum value comparison circuit using the predetermined value within the range that can be set as the maximum value for the 12-bit random number as the maximum value. It may be set to 177A. After reading the 16-bit random number maximum value (KRXS) in step S129, it is first determined whether or not the read value is within a range that can be set as the maximum value for 16-bit random numbers. If so, the read value in step S129 is set in the maximum value comparison circuit 177B as it is. On the other hand, if the read value in step S129 is not within the range that can be set as the maximum value for the 16-bit random number, the maximum value comparison circuit using the predetermined value within the range that can be set as the maximum value for the 16-bit random number as the maximum value. What is necessary is just to set to 177B. With such a process, once the process for setting the maximum value in the maximum value comparison circuits 177A and 177B is executed once, there is no need to reset it, so the control burden for setting the maximum value can be reduced. it can.

  In the above embodiment, it is determined in step S26 in the game control main process shown in FIG. 27 whether or not the power-off signal has been turned on. Described as being executed. However, the present invention is not limited to this. For example, each time the game control timer interrupt process shown in FIG. 31 is executed, it is determined whether or not the power-off signal is turned on. In such a case, the main-side power-off process may be executed. In this case, for example, whenever the execution of the game control timer interrupt process is started, it is checked whether or not the power-off signal is on. If it is on, the period during which the power-off signal is on is measured. While the timer value in the power-off signal timer for updating is updated by adding 1 or the like, the power-off signal timer may be cleared and initialized if the timer value is off. Then, the timer value in the power-off signal timer is compared with a predetermined power-off determination value (for example, “2”). Thereby, it is determined whether or not the power-off signal is continuously on for a period (for example, 4 milliseconds) during which a predetermined number (for example, 2 times) of game control timer interrupt processing is being executed. it can. At this time, if the timer value in the power-off signal timer has reached the power-off determination value, the main-side power-off process may be executed.

  The determination as to whether or not the power-off signal performed in step S521 in the payout control main process shown in FIG. 46 is turned on and the payout-side power cut-off process executed in step S522 are also limited to this. Instead, for example, each time the payout control timer interrupt process shown in FIG. 47 is executed, it is determined whether or not the power-off signal has been turned on, and when it is in the on-state, the payout-side power-off process is executed. You may do it. In this case, for example, every time execution of the payout control timer interrupt process is started, it is checked whether or not the power-off signal is in the on state. While the timer value in the power-off signal timer for updating is updated by adding 1 or the like, the power-off signal timer may be cleared and initialized if the timer value is off. Then, the timer value in the power-off signal timer is compared with a predetermined power-off determination value (for example, “2”). Thereby, it is determined whether or not the power-off signal is continuously on for a period (for example, 4 milliseconds) during which a predetermined-time (for example, twice) payout control timer interrupt process is being executed. it can. At this time, if the timer value in the power-off signal timer has reached the power-off determination value, the payout-side power-off process may be executed.

  When setting for retransmitting the payout number designation command is performed by setting the retransmission flag to the on state in step S436 shown in FIG. 39, for example, the main display payout abnormality notification screen is displayed on the image display device 5. You may make it alert | report that the payout abnormality occurred by displaying an image. More specifically, in the abnormal operation notification setting process of step S78 shown in FIG. 31, for example, when the re-transmission flag is ON, the payout abnormality notification flag provided in the game control flag setting unit 133 is ON, for example. It is determined whether or not. At this time, if the payout abnormality notification flag is off, a setting for transmitting an effect control command prepared in advance to notify that a payout abnormality has occurred, such as a main-side payout abnormality notification start command, is performed. . On the side of the effect control board 12, for example, in the notification process executed in step S <b> 907 shown in FIG. 61, it is determined whether or not the main-side payout abnormality notification start command from the main board 11 has been received, and the fact that it has been received. When the determination is made, a setting for causing the image display device 5 to display an image serving as a main payout abnormality notification screen is performed. Thereby, the abnormality of communication regarding payout control can be easily recognized outside the pachinko gaming machine 1. In addition, since the setting for retransmitting the payout number designation command is performed in the prize ball transmission process, the payout number designation command is not received by the payout control microcomputer 150 mounted on the payout control board 15. When judged, it is possible to prevent the disadvantage of the player by resending the payout number designation command so as not to hinder the payout control.

  In the above-described embodiment, the gaming machine can execute a variable display start condition (for example, a game ball wins a start winning opening provided in the normal variable winning ball apparatus 6) after a variable display execution condition is satisfied (for example, For example, a variable display device that variably displays a plurality of types of identification information (for example, special symbols) that can each be identified based on the establishment of the previous special symbol game and the end of jackpot gaming state by the special symbol display device 4 For example, a pachinko gaming machine equipped with a special symbol display device 4) that controls to a specific gaming state (for example, a big hit gaming state) advantageous to the player when the display result of variable display becomes a predetermined specific display result. there were.

  However, the present invention is not limited to this, and the gaming machine is disadvantageous for the player due to the detection of the start detection means (for example, the start ball detector) that detects the game medium in the start area provided in the game area. It has a variable winning device (for example, a variable winning ball device) that performs a starting operation (for example, an opening operation) that becomes a first state advantageous to the player from the second state, in a specific area provided in the variable winning device. A specific gaming state (for example, jackpot) that controls the variable winning device to the first state in a specific manner that is more advantageous for the player than the starting operation by detection of a specific detection means (for example, a specific ball detector) that detects the gaming medium It may be a pachinko gaming machine that generates a gaming state.

  In addition, the gaming machine of the present invention is in a state where a right is generated on condition that a game ball is detected by special detection means (for example, a specific ball detection switch or a special region switch) provided in a special region (for example, a special device operation region). During the period in which the right is generated, the game ball is moved by the start detection means (for example, the operation ball detection switch or the start port switch) provided in the start area (for example, the start port in the start winning device or the start winning device). Based on the detection, it is possible to perform control to change the special variable winning device (for example, the big prize opening) from a disadvantageous state (for example, a closed state) to the player (for example, a closed state) for the player (for example, an open state). Possible pachinko machines may be used.

It is a front view of the pachinko gaming machine in the present embodiment. It is explanatory drawing which shows the relationship of each switch for detecting a game ball. It is a rear view of the pachinko gaming machine in the present embodiment. It is a disassembled perspective view which shows the structural example of the payout apparatus in which the payout motor is installed. It is a block diagram which shows the various control boards etc. which were mounted in the pachinko game machine. It is a figure which shows the structural example of a power supply board. It is a timing diagram which shows typically the state of a reset signal and a power-off signal. It is a block diagram which shows the structural example of a launcher. It is explanatory drawing which shows an example of the content of a display control command. It is explanatory drawing which shows the structural example of the command transmitted / received between the main board | substrate and the payout control board. It is a block diagram which shows the structural example of the microcomputer for game control. It is a block diagram which shows the structural example of a random number circuit. It is a figure which shows the structural example of ARSC and BRSC. It is explanatory drawing which shows the change operation | movement of the permutation by a random number sequence change circuit. It is explanatory drawing which shows the change operation | movement of the permutation by a random number sequence change circuit. It is explanatory drawing which shows the reset operation | movement of the random value by a maximum value comparison circuit. It is a figure which shows the structural example of a random value register or a maximum value read register. It is a figure which shows an example of the address map in the microcomputer for game control. It is a figure which shows an example of the address map in ROM. It is explanatory drawing which shows the example of a setting of the highest priority interrupt. It is explanatory drawing which shows the content of random number initialization data. It is a block diagram which shows the structural example of the data holding area for game control. It is a figure which shows the structural example of the reception command buffer for a payout. It is a figure which shows the structural example of the transmission command buffer for payment. It is a block diagram which shows the structural example of the microcomputer for payout control. It is a block diagram which shows the structural example of the data holding area for payout control. It is a flowchart which shows an example of a game control main process. It is a figure which shows an example of the specific process performed within the game control main process. It is a flowchart which shows an example of a 12-bit random number initial setting process. It is a flowchart which shows an example of a 16-bit random number initial setting process. It is a flowchart which shows an example of the timer interruption process for game control. It is a flowchart which shows an example of a discharge control process. It is a flowchart which shows an example of an information output process. It is a flowchart which shows an example of a random number start value change setting process. It is a flowchart which shows an example of a random number start value change setting process. It is a flowchart which shows an example of a random number permutation change setting process. FIG. 6 is a flowchart illustrating an example of a prize ball process, and an explanatory diagram illustrating an example of a specific process executed in the prize ball process. It is a flowchart which shows an example of a prize ball transmission process. It is a flowchart which shows an example of a prize ball ACK waiting process. It is a flowchart which shows an example of a prize ball transmission completion process. It is a flowchart which shows an example of abnormal operation alert setting processing. It is a flowchart which shows an example of the main side reception process. It is a flowchart which shows an example of a special symbol process process. It is a flowchart which shows an example of a special symbol normal process. It is a flowchart which shows an example of the command control process for payout. It is a flowchart which shows an example of payout control main processing. It is a flowchart which shows an example of the timer interruption process for payout control. It is a flowchart which shows an example of a payout side reception process. It is a flowchart which shows an example of a prize ball reception confirmation process. It is a flowchart which shows an example of a payout operation control process. It is a flowchart which shows an example of a payout number memory | storage abnormality determination process. It is a flowchart which shows an example of payout control normal processing. It is a flowchart which shows an example of a prize ball payout operation | movement process. It is a flowchart which shows an example of a prize ball payout number calculation process. It is a flowchart which shows an example of a prize ball payout drive process. It is a flowchart which shows an example of a prize ball payout drive process. It is a flowchart which shows an example of a ball lending / dispensing operation process. It is a flowchart which shows an example of a ball | brick rental payout number calculation process. It is a flowchart which shows an example of a ball rental payout drive process. It is explanatory drawing which shows the relationship between the kind of error, and the display of LED for an error display. It is a flowchart which shows an example of production control main processing. It is a flowchart which shows an example of production control process processing. It is a flowchart which shows an example of alerting | reporting process. It is a figure which shows the example of a display operation in an image display apparatus. It is a timing chart for demonstrating operation | movement of a random number circuit. It is a block diagram which shows an example of a structure in the modification of the random number circuit shown in FIG. 69 is a timing chart for explaining the operation of the random number circuit shown in FIG. 66.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Pachinko machine 2 ... Game board 3 ... Gaming machine frame 4 ... Special symbol display device 5 ... Image display device 6 ... Normal variable winning ball device 7 ... Special variable winning ball device 8L, 8R ... Speaker 9 ... Game effect lamp DESCRIPTION OF SYMBOLS 10 ... Power supply board 11 ... Main board 12 ... Production control board 13 ... Audio | voice control board 14 ... Lamp control board 15 ... Discharge control board 16 ... Information terminal board 17 ... Discharge case 18 ... Relay board 19 ... Launching device 20 ... Interface board 21 ... Gate switch 22 ... Start opening switch 23 ... V winning switch 24 ... Count switches 25A to 25D ... Winning opening switch 26 ... Full tank switch 27 ... Out of ball switch 29 ... All winning ball detection switch 30 ... Operation knobs 31, 73 ... Error Release switch 40… Normal symbol display 41… Passing gate 2A～42D ... winning opening 51 ... payout motor 62 ... spherical feeder 70 ... card unit 71 ... dispensing motor position sensor 72 ... payout count switch 73 ... error release switch 74 ... error display LED
75 ... Touch sensor 81, 82 ... Solenoid 85, 86 ... Hole 87, 88 ... Gear 89 ... Cam 90 ... Ball passage 91-93 ... Case 100 ... Game control microcomputer 101, 211 ... Clock circuit 102, 212 ... Reset / Interrupt controller 103, 213 ... random number circuit 104, 123, 214 ... CPU
105, 121, 215 ... ROM
106, 122, 216 ... RAM
107, 217 ... Timer circuit 108, 218 ... Serial communication circuit 109, 219 ... External bus interface 111, 161 ... Switch circuit 112 ... Solenoid circuit 120 ... Production control microcomputer 124 ... I / O port 130 ... Game control data holding Area 131 ... Special figure holding storage part 132 ... Finalized special symbol storage part 133 ... Game control flag setting part 134 ... Game control timer setting part 135 ... Game control counter setting part 136 ... Game control buffer setting part 140 ... Holding of data for payout control Area 141 ... Discharge control flag setting unit 142 ... Discharge control timer setting unit 143 ... Discharge control counter setting unit 144 ... Discharge control buffer setting unit 150 ... Discharge control microcomputer 171 ... Clock signal output circuits 172A, 172B ... Initial value setting circuits 173A, 173B ... random number generation circuits 174A, 174B ... selector 175A ... ARSC
175B ... BRSC
176A, 176B ... random number sequence change circuit 177A, 177B ... maximum value comparison circuit 178 ... inversion circuit 179 ... timer circuit 180 ... latch signal generation circuit 181A, 181B ... random number value register 182 ... delay circuit 191 ... payout reception command buffer 192 ... Sending command buffer 201 for payout ... Reception operation unit 202 ... Transmission operation unit 203 ... Serial communication data register 204 ... Serial status register 205 ... Serial control register 301 ... Transformer circuit 302 ... DC voltage generation circuit 303 ... Power supply monitoring circuit 304 ... Clear switch

Claims (1)

A variable display that variably displays a plurality of types of identification information that can be identified based on the fact that the variable display start condition is satisfied after the variable display execution condition is satisfied after the game medium is driven into the game area. An apparatus, which is advantageous to the player when the game medium is paid out based on the winning of the game medium in the winning area in the gaming area, and the display result of the variable display becomes a predetermined specific display result. A gaming machine that controls a specific gaming state,
Launching means for firing a game medium and driving it into the game area;
Firing operation means operated by a player to drive the firing means;
Contact detection means for detecting whether or not a player is in contact with the firing operation means;
Winning detection means for detecting that a game medium has won in the winning area and outputting a winning detection signal;
A payout means for performing a game medium payout operation;
A payout detecting means for detecting a game medium paid out by the payout operation of the payout means;
A storage state detection means for detecting whether or not a predetermined amount or more of game media is stored in a storage portion in which the game media paid out by the payout operation of the payout means is stored;
A random number circuit for generating a random number is built in, a winning detection signal from the winning detection means is input, a game control process for controlling the progress of the game is executed, and a payout control signal for controlling the payout means is transmitted A game control board on which a game control microcomputer is mounted;
A payout control board mounted with a payout control microcomputer that executes a payout control process for controlling the payout operation of the payout means in accordance with a payout control signal transmitted by the game control microcomputer;
The random number circuit includes:
Numerical value updating means for cyclically updating from a predetermined initial value to a predetermined final value in a predetermined range in which numerical data can be updated based on an input of a predetermined signal according to a predetermined order;
Random number storage means for storing numerical data updated by the numerical value update means as a random value,
The game control microcomputer is:
In accordance with the input of the winning detection signal, a payout number signal transmitting means for sending a payout number signal indicating the number of game media to be paid out to the payout control microcomputer as the payout control signal;
Random number circuit setting means for setting the random number circuit to generate the random number after power supply to the gaming machine is started;
After the setting by the random number circuit setting means, a timer interrupt process execution permitting means for permitting execution of a timer interrupt process that occurs periodically,
Execution condition determination means for determining whether or not the variable display execution condition is satisfied during execution of the timer interrupt process;
Random value reading means for reading the random value stored by the random value storage means based on the execution condition determining means determining that the execution condition of the variable display is satisfied;
Display result for determining whether or not the display result in the variable display is the specific display result by determining whether or not the random value read by the random value reading means matches a predetermined determination value data Determining means,
The game control board is provided on the condition that the contact of the player is detected by the contact detection means, and that it is detected by the storage state detection means that a predetermined amount or more of game media is not stored in the storage section. A firing permission signal output means for outputting a firing permission signal for permitting the launch of the game medium by the launching means,
The random number circuit setting means includes initial value setting means for setting a value based on unique identification information given to each game control microcomputer to the predetermined initial value,
The dispensing control microcomputer is:
A payout number signal receiving means for receiving a payout number signal transmitted by the payout number signal transmitting means;
Unpaid number storage means for accumulatively storing the number of game media specified from the paid number signal received by the payout number signal receiving means,
A payout operation amount storage means for storing a payout operation amount that can be specified until the end of the payout operation by the payout means;
Unpaid number update means for updating the unpaid number stored in the unpaid number storage means according to the number of game media detected by the payout detection means;
A payout operation amount setting means for storing the payout operation amount in the payout operation amount storage means based on the fact that the unpaid number is stored in the unpaid number storage means;
A payout operation amount update means for updating the payout operation amount stored in the payout operation amount storage means in accordance with the progress of the payout operation by the payout means;
A payout operation amount determination means for determining whether or not the payout operation amount stored in the payout operation amount storage means matches predetermined end value data;
In response to the payout operation amount setting means having stored the payout operation amount in the payout operation amount storage means, the payout operation amount determination means starts the execution of the payout operation, and then the predetermined amount is determined by the payout operation amount determination means. Continuous payout control means for causing the payout means to continuously execute a payout operation until it is determined that it matches the end value data,
The payout operation amount setting means includes:
A payout increase determination means for determining whether or not the unpaid number stored by the unpaid number storage means has increased during execution of a payout operation by the payout means;
An increase specifying means for specifying an increase in the number of unpaid when the determination that the unpaid number has increased is made by the increase determining means during payout;
The payout operation amount corresponding to the increment is the increment specifying means specified, viewing including the payout operation amount adding means for the dispensing operation amount storage means is added to the dispensing operation the amount to be stored,
Further, the game control microcomputer includes a plurality of random number circuits having different predetermined update ranges of numerical data that can be updated by the numerical value updating means,
The random number circuit setting means includes:
Use random number circuit setting means for setting a random number circuit to be used from among the plurality of random number circuits;
Random number circuit stopping means for stopping the function of a random number circuit other than the set random number circuit when used by the used random number circuit setting means,
A gaming machine characterized by that.

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