JP6124468B2 - Game machine and game management device - Google Patents

Description

  The present invention relates to a gaming machine capable of performing a predetermined game.

  As an example of a gaming machine, a gaming medium such as a game ball is launched into a gaming area by a launching device, and a predetermined gaming value is determined based on the winning of a gaming medium in a winning area such as a winning opening provided in the gaming area. There is a pachinko machine that can be granted. As another example of the gaming machine, after setting a predetermined number of bets for one game using a game medium such as a medal, a coin, or a game ball similar to a pachinko gaming machine, the player operates the start lever. Thus, there is a slot machine that starts variable display of display symbols by the variable display device, and can give a predetermined game value based on the derived display result. Here, the predetermined game value is given by paying out premium game media such as prize balls and medals, adding the player's score, executing a re-game without using (digesting) the game media, and a specific game state (for example, a big hit game state) This is a concept that includes a part or all of the control to the gaming state that is more advantageous to the player than the normal gaming state.

  Such a gaming machine has been proposed in which a gaming state such as a probable change state is notified when power is turned on when power supply is started, while a gaming state is not notified except when the power is turned on (for example, a patent). Reference 1).

JP 2006-334035 A

  The one described in Patent Document 1 has a problem that there is a possibility that fraudulent acts performed at the time of power-on cannot be prevented.

  This invention is made in view of the said actual condition, and it aims at providing the gaming machine which can prevent the fraudulent act performed when power supply is started.

In order to achieve the above object, the gaming machine according to the first aspect of the present invention is a gaming machine (for example, a pachinko gaming machine 1 or a slot machine 601) capable of performing a predetermined game, and performs control. Fluctuation data storage means (such as RAM 55) for storing fluctuation data generated at the time, and a memory capable of holding the storage contents of the fluctuation data storage means for a predetermined period even when power supply to the gaming machine is stopped Content holding means (for example, a backup power supply circuit 508 and a RAM 55 as a backup RAM), initialization operation means (for example, a clear switch 914) for outputting an operation signal (for example, a clear signal) according to the operation, and power supply When the operation signal is input from the initialization operation means, the storage contents of the variation data storage means are initialized. Initialization process execution means (for example, the CPU 56 that executes the processes of steps S10 and S11) and error determination means for determining whether a predetermined error has occurred (for example, the processes of steps S121 to S126) CPU 56, etc.) and the control board provided on the gaming machine are located on the side where the control board is provided with respect to the surface of the cover member for covering and protecting the signal, and a signal is sent to the outside of the gaming machine. A terminal board provided with a plurality of terminals for connecting signal lines to be output, and a terminal board provided so as to be detachable from the cover member and covering and protecting the terminal board provided with the terminal board Cover, that at least the initialization process is executed by the initialization process execution means, and the predetermined judgment is performed by the error determination means. A predetermined external output signal (for example, a security signal) is output to the outside of the gaming machine via the terminal based on the establishment of a predetermined signal output condition including that it is determined that an error has occurred. External output means (for example, the CPU 56 that executes the processes of steps S1069 to S1074, S1100, and S1101 after executing one of the processes of steps S13 and S127), and the external output means includes the initialization process A common terminal (for example, the connector CN8 provided on the terminal board 160, etc.) when the initialization process is executed by the execution means and when the error determination means determines that the predetermined error has occurred. ) To output the predetermined external output signal (for example, the CPU 56 performs steps S13, S127, S106). 9 to S1074, S1100, and S1101 are executed to externally output a common security signal from the connector CN8 of the terminal board 160), and the predetermined signal is newly output when the predetermined external output signal is being output. If the output condition is satisfied, the output time for outputting the predetermined external output signal is extended (for example, the CPU 56 executes the processing of steps S121 to S126 and detects an abnormal winning to the start winning opening 14) Regardless of whether the security signal is being output or not, the process of step S127 is executed to overwrite the value of the security signal information timer), and the common terminal is connected to the reference potential input section and the external An output signal input unit, and two terminals are configured as one set, and a knob for opening the signal line is an end. Provided each, the knob portion are mutually are arranged to be staggered, the terminal board cover has an opening for operating the knob, cover the terminal board Is attached to the cover member, the terminal board cover covers the terminal board, and the knob is located in the opening .

  According to such a configuration, a predetermined external output signal is output based on the execution of the initialization process, thereby preventing an illegal act performed when the power supply of the gaming machine is started. it can. Furthermore, since a predetermined external output signal is output from a common terminal when the initialization process is executed and when it is determined that a predetermined error has occurred, the waste of signal lines for external output is reduced. can do.

  A first detection unit (for example, a coil L in the start port switch (proximity switch) 14a) that detects a game medium (for example, a game ball) passing through a passing area (for example, a start winning port 14) provided in the game area And a signal output unit (outputs a detection signal) in first game medium detection means (for example, a start port switch (proximity switch) 14a) that outputs a first detection signal when the first detection unit detects a game medium. Game medium detecting means: corresponding to power source, coil L, resistor R and capacitor C) and the like, and a second detection unit (for example, a game medium detection unit which detects a game medium passing through the passage area, which is arranged downstream from the first detection unit). And the second detection signal when the game medium is detected by the second detection unit. Second game medium detecting means (for example, the output part of the phototransistor 342 in the winning confirmation switch (photosensor) 14b), and the error determining means is the first game medium detecting means input from the first game medium detecting means. Based on the detection signal and the second detection signal input from the second game medium detection means, the number of game media detected by the first detection unit and the game medium detected by the second detection unit If it is determined that the difference from the number exceeds a predetermined threshold value (for example, “10”, etc.), it is determined that an abnormal passage of the game medium to the passing area has occurred as the predetermined error (for example, the CPU 56 determines in step S126). And the first detection unit and the second detection unit are configured by sensors of different detection methods (examples). Situ starting opening switch 14a is configured as a proximity switch, the winning confirmation switch 14b may be configured) as a photo sensor.

  In such a configuration, the first detection unit and the second detection unit are used as sensors of different detection methods, and it is determined whether or not a predetermined error has occurred based on the difference in the number of game media detected by each. By doing so, it is possible to more reliably detect fraudulent acts against the configuration for detecting game media, and to take measures against illegal acts.

  A first detection unit (for example, a coil L in the start port switch (proximity switch) 14a) that detects a game medium (for example, a game ball) passing through a passing area (for example, a start winning port 14) provided in the game area And a signal output unit (outputs a detection signal) in first game medium detection means (for example, a start port switch (proximity switch) 14a) that outputs a first detection signal when the first detection unit detects a game medium. Game medium detecting means: corresponding to power source, coil L, resistor R and capacitor C) and the like, and a second detection unit (for example, a game medium detection unit which detects a game medium passing through the passage area, which is arranged downstream from the first detection unit). And the second detection signal when the game medium is detected by the second detection unit. Second game medium detecting means (for example, the output part of the phototransistor 342 in the winning confirmation switch (photosensor) 14b), the first detection signal inputted from the first game medium detecting means, and the second game medium. Based on the second detection signal input from the detection means, the difference between the number of game media detected by the first detection unit and the number of game media detected by the second detection unit is a predetermined threshold value. Difference determination means for determining whether or not (for example, “10” or the like) has been exceeded (for example, the CPU 56 that executes the process of step S126), and the first detection unit and the second detection unit are detected differently. (For example, the start port switch 14a is configured as a proximity switch, and the winning confirmation switch 14b is configured as a photo sensor). Outputs the predetermined external output signal from the common output terminal when the difference determining means determines that the predetermined threshold is exceeded (for example, the CPU 56 determines Y in step S126 and determines in step S127 When the process is executed, the processes of S1069 to S1074, S1100, and S1101 are executed and the common security signal is externally output from the connector CN8 of the terminal board 160) in the same manner as when the process of step S13 is executed. May be.

  In such a configuration, by using the first detection unit and the second detection unit as sensors of different detection methods, by outputting a predetermined external output signal based on the difference in the number of game media detected by each, It is possible to more reliably detect fraudulent acts against the configuration for detecting game media, and to take reliable measures against fraud. In addition, since a predetermined external output signal is output from the common output terminal when the detected difference in the number of game media exceeds a predetermined threshold, waste of signal lines for external output can be reduced.

  Based on the input of the first detection signal from the first game medium detection means (for example, the input of the detection signal from the start port switch 14a), the variable display is performed after the input of the first detection signal. Execute variable display of the identification information by the variable display means based on the fact that the start condition permitting the start of the game is satisfied (for example, the variable display of the special symbol is not executed and is not in the big hit gaming state) The variable display executing means (for example, the CPU 56 that executes the processes of steps S300 to S303) and the fact that the first detection signal is input from the first game medium detecting means (for example, the detection signal from the start port switch 14a is input) The payout control execution means (for example, the prize ball process in step S32 is executed) for controlling the payout of the premium game medium as a free gift based only on The second detection signal input from the second game medium detection means is used only to determine whether or not an abnormality in passing of the game medium to the passage area has occurred by the error determination means. (For example, the CPU 56 confirms the detection signal from the winning confirmation switch 14b only by the processing of step S124, and uses it for determining whether or not there is an abnormal winning to the start winning opening 14 in step S126).

  In such a configuration, variable display of identification information and payout of premium game media are processed based only on the detection result in the first detection unit, thereby preventing an increase in processing burden due to strengthening countermeasures against fraud. can do.

  The error determination means determines whether the difference between the number of game media detected by the first detection unit and the number of game media detected by the second detection unit is a predetermined threshold value. Detection of game media in the first detection unit when a plurality of game media stays between the detection unit and the second detection unit (for example, when the start winning port 14 is in a ball jammed state). It may be determined whether or not a value greater than the difference between the number and the number of detected game media in the second detection unit (for example, three as shown in FIG. 63) has been exceeded (for example, the CPU 56 performs step S126). In this process, it is determined whether or not “10” or more with a sufficient margin for the three detection errors between the start port switch 14a and the winning confirmation switch 14b).

  In such a configuration, when a plurality of game media stays in the passage area (when a ball is clogged), it is erroneously determined that a game media passage abnormality (winning abnormality) has occurred. Can be prevented. Therefore, it is possible to prevent erroneous determinations associated with strengthening countermeasures against fraud.

  The external output means includes the predetermined output over different times when the initialization process is executed by the initialization process execution means and when the predetermined error is determined by the error determination means. (For example, when the initialization process is executed, the CPU 56 sets “30 seconds” as the security signal output time during the initialization process in step S13 and performs steps S1069 to S1074. When S1100 and S1101 are executed and an abnormal winning to the start winning opening 14 is detected, “4 minutes” is set as the security signal output time at the time of abnormal starting winning in step S127, and steps S1069 to S1074, S1100, and S1101 are performed. Run).

  In such a configuration, by determining the output time of a predetermined external output signal, it is determined whether the initialization process has been performed or a predetermined error has occurred in the external device. can do.

  In order to achieve the above object, the game management device according to the second aspect of the present invention provides a plurality of types of identification information (for example, special symbols, decorative symbols, or outer peripheral portions of reels 602L, 602C, 602R). When the display result in the variable display of the symbol (such as the symbol drawn in Fig. 1) becomes a predetermined specific display result (for example, a symbol design of a big hit symbol, a symbol combination of a big hit combination, or a combination of a special role) In a gaming machine (for example, a pachinko gaming machine 1 or a slot machine 601) that is controlled to a particular gaming state advantageous to the player (for example, a big hit gaming state, a regular bonus, a big bonus, etc.), the gaming state is changed after the particular gaming state has ended. Unlike the normal game state or the specific game state, a special game state advantageous to the player (for example, a probability change state) Alternatively, control for setting an assist time (AT), a replay time (RT), a concentration state, etc.) is performed, and a predetermined initialization process (for example, the processes of steps S10 and S11) is executed when power supply is started. And the predetermined initialization process is executed when the power supply is started, and the first state including the occurrence of a predetermined error (for example, an abnormal winning in the start winning opening 14). A game that occurs in connection with a game in a gaming machine having a second state in which data indicating the special gaming state (for example, data indicating that the probability variation flag is ON) is stored in addition to the absence A game management device (eg, a terminal device 770 or a hall computer 771) that manages related information, and is provided in the game area for the player. Detectable is a variable winning means that can change to an advantageous first state and a second state that is disadvantageous to the player, and that changes to the first state in the specific gaming state, and a game medium that has entered the variable winning means. Variable winning detection means is provided, and the predetermined error occurs when a game medium is detected by the variable winning detection means in a predetermined period other than the specific gaming state, and at least a predetermined initial value is generated in the gaming machine. First state specifying signal receiving means (for example, a security signal or the like) for specifying that the processing has been executed or that the predetermined error has occurred in the gaming machine (for example, security signal) The terminal device 770 and the hall computer 771 that execute the process of step S601) and the predetermined time when power supply is started in the gaming machine. Second state specification for receiving a second state specification signal (for example, a state signal at the time of input) for specifying that data indicating the special gaming state is stored in addition to the initialization process not being executed Based on the signal receiving means (for example, the terminal device 770 or the hall computer 771 that executes the processing of step S603) and the first state specifying signal received by the first state specifying signal receiving means, the first state is First state occurrence recognizing means for recognizing occurrence (for example, the base terminal device 770 or the hall computer 771 when it is determined as Y in the process of step S601) and the second state received by the second state specifying signal receiving means Based on the specific signal, second state occurrence recognizing means for recognizing that the second state has occurred (for example, it is determined as Y in the process of step S603). The first terminal processing 770 and the hall computer 771) and the first processing for executing the predetermined first processing based on the fact that the first state occurrence recognition means recognizes that the first state has occurred. Based on the fact that the second state has been recognized by the execution means (for example, the stand terminal device 770 or the hall computer 771 that executes the process of step S602) and the second state occurrence recognition means, a predetermined 2nd process execution means (for example, the stand terminal device 770, the hall computer 771, etc. which perform the process of step S604) which performs a 2nd process are provided.

  According to such a configuration, it is possible to easily grasp the gaming state when the power supply of the gaming machine is started. Also, by detecting whether a predetermined external output signal based on the execution of the initialization process has been input, it is possible to easily detect fraudulent acts that are performed when the power supply of the gaming machine is started. , Can take certain anti-fraud measures.

  Note that the gaming system according to another aspect of the present invention has a plurality of types of identification information (for example, special symbols, decorative symbols, or symbols drawn on the outer periphery of the reels 602L, 602C, and 602R). When the display result of the variable display becomes a specific display result determined in advance (for example, a jackpot symbol, a finalized combination symbol of a jackpot combination, or a combination of special combinations), a specific gaming state advantageous to the player ( For example, in a gaming machine (for example, a pachinko gaming machine 1 or a slot machine 601) that is controlled to a big hit gaming state or a regular bonus, a big bonus, etc., the gaming state is changed to the normal gaming state or the particular gaming after the particular gaming state has ended. Unlike a state, a special game state that is advantageous to the player (for example, a probability change state or an assist System (AT), replay time (RT), concentration state, etc.), and predetermined initialization processing (for example, processing in steps S10 and S11) is executed when power supply is started. And a first state including a predetermined error (for example, abnormal winning in the start winning port 14) and the predetermined initialization process is not executed when power supply is started. In addition to the gaming machine having a second state in which data indicating the special gaming state (for example, data indicating that the probability variation flag is ON) is stored, and in relation to a game in the gaming machine A game management device (for example, a terminal device 770 or a hall computer 771) that manages game-related information that is generated, and a game system (for example, a game information processing system shown in FIG. 73) And the gaming management device specifies at least that a predetermined initialization process has been executed in the gaming machine or that a predetermined error has occurred in the gaming machine. The first state specifying signal receiving means (for example, the terminal device 770 or the hall computer 771 that executes the process of step S601) that receives the one state specifying signal (for example, a security signal) and the game machine start power supply. A second state specifying signal for specifying that the data indicating the special gaming state is stored in addition to the fact that the predetermined initialization process is not executed when the game is executed (for example, a state signal at the time of input) The second state specifying signal receiving means (for example, the terminal device 770 or the hall computer 771 that executes the process of step S603), and the first state First state occurrence recognizing means for recognizing that the first state has occurred based on the first state specifying signal received by the specific signal receiving means (for example, the terminal device 770 when it is determined as Y in the process of step S601) And a hall computer 771) and second state occurrence recognizing means for recognizing that the second state has occurred based on the second state specifying signal received by the second state specifying signal receiving means (for example, in step S603). Predetermined terminal processing based on the fact that the first state has been recognized by the first state occurrence recognizing means and the terminal device 770, the hall computer 771, etc. First process execution means (for example, a terminal device 770 or a hall computer 771 that executes the process of step S602) and the second state Based on the fact that the second state has been recognized by the raw recognition means, second process execution means for executing a predetermined second process (for example, a terminal device 770 or a hall computer for executing the process of step S604) 771) and the like.

  According to such a configuration, it is possible to easily grasp the gaming state when the power supply of the gaming machine is started. In addition, since the predetermined process is executed based on the execution of the predetermined initialization process, it is possible to easily detect the illegal action performed when the power supply of the gaming machine is started and Measures can be taken.

It is the front view which looked at the pachinko game machine from the front. It is a front view which shows the front surface of the game board in the state which removed the glass door frame. It is the rear view which looked at the gaming machine from the back. It is a block diagram which shows the structural example of a power supply board. It is a timing diagram which shows typically the state of a reset signal and a power-off signal. It is explanatory drawing which shows the specific example of the cross-sectional structure in a start winning opening. It is a circuit diagram for demonstrating the system of the detection means which can detect a game ball. It is a block diagram which shows the structural example of a game control board (main board). It is a circuit diagram which shows the structural example of a door open switch and a backup power supply circuit. It is a block diagram which shows the circuit structural example of a payout control board. It is a block diagram which shows the circuit structural example of a relay board | substrate, an effect control board | substrate, a lamp driver board | substrate, and an audio | voice output board | substrate. It is a block diagram showing a circuit configuration of the main board and a signal line of an effect control command transmitted from the main board to the effect control board. It is explanatory drawing which shows the structural example of game machine specific information. It is a block diagram which shows the structural example of the transmission part of a serial communication circuit. It is a block diagram which shows the structural example of the receiving part of a serial communication circuit. It is explanatory drawing which shows the example of the data format of the data which a serial communication circuit transmits / receives with the microcomputer mounted in each control board. It is explanatory drawing which shows the example of a baud rate register. It is explanatory drawing which shows the example of the control register A and communication format setting data. It is explanatory drawing which shows the example of the control register B and interrupt request setting data. It is a figure which shows the example of status register A and status confirmation data. It is a figure which shows the example of status register B and status confirmation data. It is explanatory drawing which shows the example of the control register C and error interrupt request setting data. It is explanatory drawing which shows the example of the data register with which a serial communication circuit is provided. It is explanatory drawing which shows the example of bit allocation of the output port in a game control means. It is explanatory drawing which shows the bit allocation example of the input port in a game control means. It is explanatory drawing which shows the internal structure etc. of a terminal board | substrate. It is a flowchart which shows a game control main process. It is a flowchart which shows a 4 ms timer interruption process. It is explanatory drawing which shows an example of the content of the control signal output with respect to the payout control means from a game control means. It is explanatory drawing which shows an example of the content of the control command transmitted / received between a game control means and a payout control means. It is explanatory drawing which shows the example of the error information set to a connection OK command and a prize ball preparation command. It is a block diagram which shows the signal line etc. which are used for transmission / reception of a control signal and a control command. It is a sequence diagram showing transmission and reception of signals between the game control microcomputer and the payout control microcomputer during normal operation. FIG. 6 is a sequence diagram showing signal transmission / reception between a game control microcomputer and a payout control microcomputer during a prize ball operation. FIG. 6 is a sequence diagram showing signal transmission / reception between a game control microcomputer and a payout control microcomputer during a prize ball operation. FIG. 10 is a sequence diagram showing signal transmission / reception between a game control microcomputer and a payout control microcomputer when a winning ball operation cannot be executed immediately. FIG. 5 is a timing chart showing signal transmission and reception between a game control microcomputer and a payout control microcomputer during normal operation. FIG. 10 is a timing chart showing signal transmission / reception between a game control microcomputer and a payout control microcomputer when an error occurs during a winning ball. FIG. 5 is a timing chart showing signal transmission / reception between a game control microcomputer and a payout control microcomputer when a communication error occurs during connection confirmation. FIG. 5 is a timing chart showing signal transmission / reception between a game control microcomputer and a payout control microcomputer when a communication error occurs during award ball number notification. It is a flowchart which shows an example of a prize ball process. It is explanatory drawing which shows the example of a prize ball number table. It is a flowchart which shows a prize ball command output counter addition process. It is a flowchart which shows a prize ball control process. It is a flowchart which shows prize ball transmission processing 1. It is a flowchart which shows a prize ball connection confirmation process. It is a flowchart which shows the prize ball transmission process 2. FIG. It is a flowchart which shows a prize ball receipt confirmation process. It is a flowchart which shows a prize ball completion | finish confirmation process. It is a flowchart which shows a prize ball counter subtraction process. It is a flowchart which shows an example of a frame state output process. It is a flowchart which shows an example of a special symbol process process. It is a flowchart which shows a starting port switch passage process. It is a figure which shows the structural example of a special figure display result determination table and a jackpot classification determination table. It is a flowchart which shows an example of a special symbol normal process. It is a flowchart which shows an example of a special symbol stop process. It is a flowchart which shows an example of a jackpot end process. It is explanatory drawing which shows each 2 byte buffer formed in RAM used by switch processing. It is a flowchart which shows the process example of a switch process. It is a flowchart which shows a switch normal / abnormality check process. It is explanatory drawing for demonstrating a switch normal / abnormality check process. It is explanatory drawing for demonstrating a switch normal / abnormality check process. It is explanatory drawing which shows the case where a game ball raise | generates the ball clogged state in the start winning opening. It is a block diagram which shows the various signals output to a terminal board. It is a flowchart which shows an information output process. It is a flowchart which shows an information output process. It is a flowchart which shows an information output process. It is a flowchart which shows an information output process. It is explanatory drawing in the case of outputting game machine specific information from the output terminal shared with a security signal. It is explanatory drawing which shows the output timing of a security signal. It is explanatory drawing which shows output timings, such as game machine specific information. It is explanatory drawing which shows the output timing of a state signal at the time of injection. It is explanatory drawing which shows the external device from which game machine specific information etc. are output. It is a flowchart which shows a communication signal process. It is explanatory drawing in case game machine specific information is output to a hall computer. It is explanatory drawing in case game machine specific information is output to a card unit. It is explanatory drawing which shows the bit allocation example of the output port in a payout control means. It is explanatory drawing which shows the example of bit allocation of the input port in a payout control means. It is a flowchart which shows the main process which CPU for payout control performs. It is a flowchart which shows the timer interruption process which CPU for payout control performs. It is a flowchart which shows a main control communication process. It is a flowchart which shows a main control command reception process. It is a flowchart which shows a main control connection confirmation process. It is a flowchart which shows main control communication normal processing. It is a flowchart which shows main control communication normal processing. It is a flowchart which shows the process during main control communication. It is a flowchart which shows the process during main control communication. It is a flowchart which shows a main control communication end process. It is a flowchart which shows a main control transmission command conversion process. It is a flowchart which shows payout control processing. It is a flowchart which shows the payout start waiting process. It is a flowchart which shows a payout motor stop waiting process. It is a flowchart which shows payout passage waiting processing. It is a flowchart which shows payout passage waiting processing. It is a flowchart which shows payout passage waiting processing. It is explanatory drawing which shows an example of the relationship between the kind of error, and the display of LED for an error display. It is a flowchart which shows an error process. It is a flowchart which shows an error process. It is a flowchart which shows an information output process. It is a flowchart which shows an information output process. It is a flowchart which shows the presentation control main process which CPU for presentation control performs. It is a flowchart which shows the specific example of a command analysis process. It is explanatory drawing which shows the example of a transition of production mode. It is a figure which shows the structural examples, such as an effect control pattern table. It is a figure which shows the structural example etc. of an effect control pattern. It is a flowchart which shows production control process processing. It is a flowchart which shows the waiting process per special figure. It is the flowchart etc. which show the big hit effect processing. It is a figure which shows an example of the background image of each production mode. It is explanatory drawing which shows the modification of the physical structure of a terminal board | substrate. It is explanatory drawing which shows the modification of the physical structure of a terminal board | substrate. It is explanatory drawing which shows the cross-section of the site | part to which the terminal board | substrate of a cover member is attached. FIG. 11 is a front view of a slot machine as a modification of the gaming machine according to the present invention as viewed from the front. It is a block diagram which shows the circuit structural examples, such as a game control board (main board) and an effect control board, in a slot machine.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. First, the overall configuration of a pachinko gaming machine that is an example of a gaming machine will be described. FIG. 1 is a front view of a pachinko gaming machine as viewed from the front, and FIG. 2 is a front view showing the front of the game board. In the following embodiments, a pachinko gaming machine will be described as an example. However, the gaming machine according to the present invention is not limited to a pachinko gaming machine, and can be applied to other gaming machines such as a slot machine.

  The pachinko gaming machine 1 includes an outer frame 2A formed in a vertically long rectangular shape, and a game frame 11 attached to the inside of the outer frame 2A so as to be opened and closed. Further, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape that is provided in the game frame 11 so as to be opened and closed. The game frame 11 includes a front frame (not shown) that can be opened and closed with respect to the outer frame 2A on the back side of the glass door frame 2, and a mechanism plate to which mechanical parts and the like are attached on the back side of the front frame. And a structure including various components (except game boards described later) attached to them.

  As shown in FIG. 1, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2 is a hitting ball supply tray (upper plate) 3. Under the hitting ball supply tray 3, an extra ball receiving tray 4 for storing game balls that cannot be accommodated in the hit ball supply tray 3 and a hitting operation handle (operation knob) 5 for launching the game balls are provided. A game board 6 is detachably attached to the back surface of the glass door frame 2. The game board 6 is a structure including a plate-like body constituting the game board 6 and various components attached to the plate-like body. A game area 7 is formed on the front surface of the game board 6.

  In the vicinity of the center of the game area 7, there is provided an effect display device (decorative symbol display device) 9 including a plurality of variable display portions each variably displaying an effect decorative symbol (effect symbol). The effect display device 9 includes, for example, three variable display portions (symbol display areas) of “left”, “middle”, and “right”. The effect display device 9 performs variable display of the effect symbol as a symbol for decoration (for effect) during the variable display period of the special symbol by the special symbol indicator 8. The effect display device 9 that performs variable display of effect symbols is controlled by an effect control microcomputer mounted on the effect control board.

  Below the effect display device 9, four special symbol hold memory indicators 18 are provided for displaying the number of effective winning balls that have entered the start winning opening 14, that is, the number of hold memories (also referred to as start memory or start prize memory). ing. The special symbol reservation storage display 18 displays up to four reservation storage numbers in the order of winning. The special symbol hold storage display 18 increases the number of LEDs in the lit state by 1 each time there is a start winning in the start winning opening 14. Then, each time the special symbol display 8 starts variable display, the special symbol hold storage indicator 18 reduces the number of LEDs in the lit state by 1 (that is, turns off one LED). Specifically, the special symbol hold storage display 18 shifts the lighting state each time variable display is started on the special symbol display 8. In this example, the upper limit number (up to 4) is provided for the number of starting memories by winning to the start winning opening 14, but the upper limit number may be four or more.

  On the top of the effect display device 9, a special symbol display (variable display for variably displaying a plurality of special symbols, each of which can be identified, and a display result is derived (stopped display)). A special symbol display device 8 is provided. In this embodiment, the special symbol display 8 is realized by a simple and small display (for example, 7-segment LED) that variably displays numbers 0 to 9, for example. The special symbol display 8 may be configured to variably display a larger number of numbers such as 0 to 99 in order to make it difficult for the player to grasp a specific stop symbol. Further, the effect display device 9 performs variable display of the effect symbol as a symbol for decoration (for effect) during the variable display period of the special symbol by the special symbol indicator 8.

  Below the effect display device 9, a variable winning ball device 15 that forms a start winning opening 14 is provided. The variable winning ball device 15 is configured to be able to open and close the wings, and when the wings are open, the game ball is likely to win a prize (open state), and when the wings are not open (closed). The game ball becomes difficult to win (closed state). The winning ball that has entered the starting winning opening 14 is guided to the back of the game board 6 and detected by the starting opening switch 14a (for example, a proximity switch) and detected by the winning confirmation switch 14b (for example, a photo sensor). . In this embodiment, as will be described later, on the basis of the detection of the game ball by the start port switch 14a, the special symbol variation display is started, and the prize ball payout is executed. Further, as will be described later, the presence or absence of an abnormal winning is determined based on the detection result of the winning confirmation switch 14b in addition to the detection result of the start port switch 14a, and the security signal is detected based on the detection of the abnormal winning. Is output externally. The variable winning ball device 15 is opened by a solenoid 16.

  The first winning prize opening may be provided directly above the variable winning ball apparatus 15, and the variable winning ball apparatus 15 may be used as the second starting prize opening. In this case, for each of the first start winning opening and the second starting winning opening, a start opening switch (for example, a proximity switch) and a winning confirmation switch (for example, a photo sensor) may be provided. Then, for each of the first start winning opening and the second starting winning opening, the variation display of the special symbol is started based on the detection of the game ball by the start opening switch as in this embodiment. A ball payout may be executed. Further, for each of the first start winning opening and the second starting winning opening, whether or not an abnormal winning has occurred is determined based on the detection result of the winning confirmation switch in addition to the detection result by the start opening switch, as in this embodiment. A security signal may be output to the outside based on the determination and the occurrence of an abnormal winning.

  Below the variable winning ball apparatus 15, a special variable winning ball apparatus 20 using an opening / closing plate that is controlled to be opened by a solenoid 21 in a specific gaming state (big hit state) is provided. The special variable winning ball apparatus 20 is a means for opening and closing the big winning opening. The winning ball that has won the special variable winning ball device 20 and led to the back of the game board 6 is detected by the count switch 23.

  In this embodiment, a case where a winning confirmation switch 14b is provided only at the starting winning opening 14 in addition to the starting opening switch 14a is shown. However, in addition to the count switch 23, a winning confirmation switch is provided at the large winning opening. You may make it provide. In this case, for example, the count switch 13 may be configured by using a proximity switch and the winning confirmation switch may be configured by using a photosensor as in the case of the start winning opening 14 (in contrast, the count switch 13 May be configured using a photo sensor, and the winning confirmation switch may be configured using a proximity switch, or a mechanical switch such as a micro switch may be used instead of the proximity switch or the photo sensor). In addition, the game control microcomputer 560 may perform the payout of the winning ball based only on the detection result of the count switch 23 in the winning ball payout process based on the winning of the game ball to the big winning opening ( (See step S32). On the other hand, when the gaming control microcomputer 560 performs an abnormal winning to the big winning opening, the determination is made based on both the detection result of the count switch 23 and the detection result of the winning confirmation switch. Good. In this case, for example, the game control microcomputer 560 determines that the difference between the detected number of the count switch 23 and the detected number of the winning confirmation switch is a predetermined value (for example, 10) according to the same process as the switch normal / abnormal check process described later. ) Based on the above, it may be determined that an abnormal winning at the special winning opening has occurred (see steps S121 to S126).

  When the game ball passes through the gate 32 and is detected by the gate switch 32a, the normal symbol variable display on the normal symbol display 10 is started. In this embodiment, variable display is performed by alternately lighting left and right lamps (designs can be visually recognized when lit). For example, if the left lamp is lit at the end of variable display, it is a hit. When the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined number of times. In the vicinity of the normal symbol display 10, a normal symbol start memory display 41 having a display unit with four LEDs for displaying the number of winning balls that have passed through the gate 32 is provided. Each time there is a game ball passing through the gate 32, the normal symbol start memory display 41 increases the number of LEDs to be turned on by one. Each time the variable display on the normal symbol display 10 is started, the number of LEDs to be lit is reduced by one.

  The game board 6 is provided with a plurality of winning holes 29 and 30, and winning of game balls to the winning holes 29 and 30 is detected by winning hole switches 29a and 30a, respectively. Each of the winning ports 29 and 30 constitutes a winning area provided on the game board 6 as an area for accepting game media and allowing winning. The start winning opening 14 and the big winning opening also constitute a winning area that accepts game media and allows winning. In addition, it may be configured to detect with a detection switch that a game ball has passed a predetermined area (for example, a gate), instead of the configuration in which the game ball won in each winning opening 29, 30 is detected with a prize switch. Around the left and right of the game area 7, there are provided decorative lamps 25 blinking and displayed during the game, and at the lower part there is an outlet 26 for absorbing a game ball that has not won a prize. Two speakers 27 that emit sound effects are provided on the left and right upper portions outside the game area 7. On the outer periphery of the game area 7, a top frame lamp 28a, a left frame lamp 28b, and a right frame lamp 28c are provided. Further, a decoration LED is installed around each structure (such as a big prize opening) in the game area 7. The top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, and the decoration LED are examples of a decorative light emitter provided in the gaming machine. In this embodiment, the case where the light emitter provided in the gaming machine is configured by using a lamp or an LED is shown. However, the present invention is not limited to the mode shown in this embodiment. You may make it comprise all the provided light-emitting bodies using LED.

  Although not shown in FIGS. 1 and 2, a prize ball lamp that is turned on during the prize ball payout is provided in the vicinity of the left frame lamp 28b, and a supply ball is provided in the vicinity of the top frame lamp 28a. There is a ball-out lamp that illuminates when it runs out. Note that the award ball lamp and the out-of-ball lamp are controlled to be turned on by the effect control microcomputer mounted on the effect control board when the award ball is being paid out or when the out-of-ball is detected. Further, a prepaid card unit (hereinafter referred to as “card unit”) 50 that enables lending by inserting a prepaid card (including a membership card and a visitor card) is installed adjacent to the pachinko gaming machine 1. Has been. The card unit 50 is a game value use process (lending process) for causing a game value (prepaid frequency) recorded on a game recording medium such as a prepaid card to be used for a game in a gaming machine such as the pachinko gaming machine 1. As long as it is a gaming device that can execute at least.

  The card unit 50 includes, for example, a usable display lamp that indicates whether or not the card unit 50 is in a usable state, a connection table direction indicator that indicates which side of the pachinko gaming machine 1 corresponds to the card unit, and a card unit. When checking the card insertion indicator lamp indicating that a card is inserted in the card, the card insertion slot into which the card as a recording medium is inserted, and the card reader / writer mechanism provided on the back of the card insertion slot A card unit lock for releasing the card unit is provided. The card unit 50 may be integrated with the pachinko gaming machine 1 instead of being installed adjacent to the pachinko gaming machine 1 as a separate body from the pachinko gaming machine 1. In addition, a game ball corresponding to the amount may be lent out in accordance with coin insertion or cash insertion.

  A game ball launched from the ball striking device by the player's operation enters the game area 7 through the hit ball rail, and then descends the game area 7. If the game ball enters the start winning opening 14 and is detected by the start opening switch 14a, if the variable display of the symbol can be started, the special symbol starts variable display (fluctuation) on the special symbol display 8, and the special symbol is displayed. The game starts to run. If it is not in a state where the symbol variable display can be started, the number of reserved memories is increased by 1, and the execution of the special figure game is suspended.

  The special symbol variable display on the special symbol display 8 is stopped when a certain time has elapsed, thereby completing one special symbol game. If the special symbol at the time of stop (referred to as a stop symbol or a confirmed special symbol) is a big hit symbol (specific display result), it shifts to a big hit gaming state, and if it is a small hit symbol, it shifts to a small hit gaming state. In the big hit gaming state, the special variable winning ball device 20 is released until a predetermined time elapses or a predetermined number (for example, ten) of gaming balls wins. The opening of the special variable winning ball apparatus 20 is allowed until the last round of the determined number of rounds (for example, up to 15 rounds). In the pachinko gaming machine 1 in this embodiment, as an example, the special symbol indicating the numbers “3”, “5”, and “7” is the big hit symbol, and the special symbol indicating the number “2” is the small hit symbol. The special symbol indicating the symbol “−” is a lost symbol. It should be noted that each symbol such as a big hit symbol, a small hit symbol, or a lost symbol in the special game can be arbitrarily set according to the specifications of the pachinko gaming machine 1.

  If the special symbol (determined special symbol) in the special symbol display 8 at the time of stoppage is a jackpot symbol (probability variation symbol) with a probability variation, the probability of the next jackpot increases. That is, it becomes a more advantageous state for the player in the probability variation state.

  In this embodiment, among the special symbols indicating the numbers “3”, “5”, and “7” that are jackpot symbols, the special symbols indicating the numbers “3” and “7” are 15R (round) jackpot symbols. And a special symbol indicating the number “5” is a 2R (round) jackpot symbol. In the big hit gaming state (15R big hit state) as the first specific gaming state controlled after the 15R big hit symbol is stopped and displayed as a confirmed special symbol in the special figure game, the opening / closing plate of the special variable winning ball apparatus 20 is the first The special variable winning ball apparatus 20 is opened to the player by opening the large winning opening in a predetermined period (for example, 29 seconds) or a period until a predetermined number (for example, 10) of winning balls are generated. A round to change to an advantageous first state is performed. In this way, the opening / closing plate that opened the grand prize opening during the round receives the game ball falling on the surface of the game board 6 and then closed the grand prize opening, thereby playing the special variable prize winning ball device 20 as a game. One round is completed by changing to a closed state, which is a second state that is disadvantageous to the user. In the 15R big hit state, the number of executions of the round which is the opening cycle of the big winning opening is the first number (for example, “15”). A game in the 15R big hit state in which the number of round executions is “15” is also referred to as a 15-time open game.

  In the big hit gaming state (2R big hit state) as the second specific gaming state controlled after the 2R big hit symbol is stopped and displayed as the confirmed special symbol in the special figure game, the special variable winning ball apparatus 20 is advantageous to the player in the round. The period during which the state is changed to the first state (the period in which the big prize opening is opened by the opening / closing plate) is a second period (for example, 0.5 seconds) shorter than the first period in the 15R big hit state. Further, in the 2R big hit state, the number of executions of the round becomes a second number (for example, “2”) which is smaller than the first number in the 15R big hit state. In the 2R big hit state, at least one of the period in which the big winning opening is opened in the round is the second period and the number of executions of the round is the second number is performed. What is necessary is just to be controlled, and other control may be performed similarly to the 15R big hit state. A game in the 2R big hit state in which the number of round executions is “2” is also referred to as a two-time open game. In the 2R big hit state, the predetermined winning ball apparatus provided separately from the special variable winning ball apparatus 20 in the round is changed from the second state that is disadvantageous to the player to the first state that is advantageous to the player, You may make it return to a 2nd state, after a predetermined period (1st period or 2nd period) passes.

  Among the special symbols indicating the numbers “3” and “7” that will be the 15R jackpot symbol, the 15R jackpot state based on the special symbol indicating the number “3” being stopped and displayed as the confirmed special symbol in the special symbol game After the game is finished, it is controlled as a special game state in the short-time state (also referred to as “low probability high base state”), and special symbols and production symbols compared to the normal state (also referred to as “low probability low base state”). The short time control (time reduction control) is performed in which the variable display time (the time required from the start of variable display of each symbol to the time when the symbol as a display result is derived and displayed) is shortened. Here, the normal state is a game state other than a special game state such as a big hit game state or a special game state such as a short-time state, and an initial setting state of the pachinko gaming machine 1 (for example, when a system reset is performed) Thus, the same control as in the state in which the initialization process is executed after power-on is performed. If the time-short state is terminated when any of the conditions of the special game is executed a predetermined number of times (for example, 100 times) and the variable display result is “big hit” is satisfied first, Good. In addition, after the 15R big hit state based on the special symbol showing the number “3” being stopped and displayed as a special symbol to be confirmed in the special figure game is stopped, the normal state is not entered. You may make it become. Like the special symbol indicating the number “3”, the 15R jackpot symbol controlled to the short-time state or the normal state after the jackpot gaming state based on being stopped and displayed as the confirmed special symbol in the special symbol game is It is called a 15R non-probable variation (also called a 15R normal special figure).

  Among the special symbols indicating the numbers “3” and “7” that will be the 15R jackpot symbol, the 15R jackpot state based on the special symbol indicating the number “7” being stopped and displayed as a confirmed special symbol in the special symbol game After the game is finished, the game is controlled to a probability change state (also referred to as a “high probability high base state”), which is a high probability game state as one of the special game states different from the short-time state. Probability variation control (probability variation control) is continuously performed along with time-shortening control in which the variable display time of the symbol is shortened. In high-probability gaming states such as the probability variation state, in the variable display of each special figure game and production symbol, the probability that the variable display result will be “big hit” and further controlled to the big hit gaming state is higher than in the normal state. To be improved. In this embodiment, such a high-probability gaming state is continued until the next variable display result is “big hit”, regardless of the number of executions of the special figure game. On the other hand, after entering the high-probability gaming state, one of the conditions is that a special-number game is executed a predetermined number of times (for example, 100 times) or the variable display result is “big hit”. You may make it complete | finish, when it establishes previously. In addition, even if a specific number of special figure games are executed in the high probability game state or before the variable display result is “big hit”, the high probability game state is generated at a predetermined rate when the special figure game is started. May be terminated. Alternatively, when the special display game is executed a predetermined number of times (for example, 100 times) after the variable display result does not become “big hit” after the probability change state is entered, the time-shortening control is ended and the special symbol or the production symbol is variable. While the display time is returned to the variable display time similar to the normal state, the probability variation control may be continuously performed. Like the special symbol indicating the number “7”, the 15R jackpot symbol controlled to the high-probability gaming state after the jackpot gaming state based on being stopped and displayed as the confirmed special symbol in the special symbol game is 15R. It is called a probability variation pattern (also called a 15R probability variation special diagram).

  After the 2R jackpot state based on the fact that the special symbol indicating the number “5”, which is the 2R jackpot symbol, is stopped and displayed as the confirmed special symbol in the special figure game, the state is controlled to the probability change state. In addition, as a special gaming state, for example, while the variable display time of the special symbol and the production symbol is the same as the normal state, the high probability gaming state (“high probability low base” in which probability variation control (probability variation control) is continuously performed) (Also referred to as “state”). Like the special symbol indicating the number “5”, the 2R jackpot symbol controlled to the high probability gaming state after the jackpot gaming state based on being stopped and displayed as the confirmed special symbol in the special symbol game is 2R. It is called a probability variation pattern (also called a 2R probability variation special diagram).

  After the special symbol indicating the number “2” as the small hit symbol is stopped and displayed as the confirmed special symbol in the special symbol game, the small hit game state is controlled. In this small hit gaming state, a variable winning operation for changing the special variable winning ball apparatus 20 to the first state advantageous to the player is performed as in the 2R big hit state. That is, in the small hit game state, for example, the operation of opening the large winning opening for the second period by the opening / closing plate provided in the special variable winning ball apparatus 20 is repeatedly executed until the second number of times is reached. In the small hit gaming state, as in the 2R big hit state, the period in which the big prize opening is in the open state is the second period, and the number of executions of the operation in which the big prize opening is in the open state is the second number. It is sufficient to control so that at least one of them is performed. After the small hit gaming state ends, the gaming state is not changed, and the game state before the variable display result becomes “small hit” is continuously controlled. However, if the number of executions of the special figure game in the special gaming state has reached a predetermined number when the special figure game with the variable display result of “small hit” is executed, after the end of the small hit gaming state, The special gaming state may end and return to the normal state. A game in the small hit game state in which the number of times that the big winning opening is opened by the variable winning operation is “2” is also referred to as a two-time open game, similar to the game in the 2R big hit state. When the winning ball device provided separately from the special variable winning ball device 20 in each round in the 2R big hit state is changed to the first state, even in the small hit gaming state, the same manner as in the 2R big hit state The winning ball apparatus may be changed to the first state.

  When the game ball passes through the gate 32, the normal symbol display unit 10 enters a state in which the normal symbol is variably displayed. Further, when the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined time.

  In the probabilistic state and the short time state, the normal symbol display unit 10 controls the normal symbol in the normal symbol game so that the variation time of the normal symbol (ordinary symbol variation time) is shorter than that in the normal state. Control to improve the probability that the display result is “per normal figure” than in the normal state, and tilt control of the movable blade piece in the variable winning ball apparatus 15 based on the fact that the variable display result is “per normal figure”. Executes a special symbol variation display that makes it easier for a game ball to enter the start winning opening 14, such as a control for making the tilt control time to be longer than in the normal state, and a control for increasing the number of tilts compared to the normal state. Control that is advantageous to the player is performed by increasing the possibility that the condition (starting condition) to be satisfied is established. It should be noted that any one of these controls may be performed in the probability variation state or the short time state, or a plurality of controls may be performed in combination. Thus, the control that facilitates the entry of the game ball into the start winning opening 14 in the probability changing state or the short time state and is advantageous to the player is also referred to as high opening control. By performing the high opening control, the start winning opening 14 is more frequently opened than when the high opening control is not being performed. The period during which the high opening control can be executed is also referred to as a high opening control period, and this period may be the same as the period during which the gaming state in the pachinko gaming machine 1 is controlled to either the certain change state or the short-time state. .

  Corresponding to the start of a special symbol game in which special symbols are variably displayed by the special symbol display 8, the “left”, “middle”, and “right” symbol display areas provided in the effect display device 9 are displayed. Then, the change of the effect design (for example, vertical scroll display) is started. Thereafter, when the confirmed special symbol is stopped and displayed as a variable display result in the special symbol game, the variable symbol display is performed in the “left”, “middle”, and “right” symbol display areas in the effect display device 9. The resulting definite effect symbol (final stop symbol) is stopped and displayed.

  There are, for example, eight types of symbols (alphanumeric characters “1” to “8” or Chinese numerals “1” to “1” to “left”, “middle”, and “right”). 8 ”, English letters“ A ”to“ H ”, 8 types of character images related to a predetermined motif, combinations of numbers, letters or symbols, and character images, etc. Any other object, a symbol such as a character, or an effect image showing any other figure may be used. In addition to these eight types of effect symbols, a blank symbol (a symbol that does not constitute a jackpot combination) may be included. A corresponding symbol number is attached to each of the effect symbols. For example, the symbol numbers “1” to “8” only need to be attached to the production symbols indicating alphanumeric characters “1” to “8”. Note that the types of production symbols are not limited to eight, and any number may be used as long as an appropriate number of combinations such as a jackpot combination or a combination that is lost can be configured (for example, seven types or nine types). .

  During the variation display of the production symbol, in the symbol display areas of “left”, “middle”, and “right”, for example, the production symbols that flow from top to bottom sequentially from the smallest to the largest When the effect symbol having the largest symbol number (for example, “8”) is displayed, the effect symbol having the smallest symbol number (for example, “1”) is subsequently displayed. Alternatively, in at least one of the symbol display areas (for example, the “left” symbol display area), the effect symbol is scrolled from the largest symbol number to the smallest symbol symbol, and the symbol number is the smallest. When the symbol is displayed, the effect symbol having the largest symbol number may be displayed. Note that the direction in which the effect symbols are scrolled is not limited to the direction from the top to the bottom, for example, from the right side to the left side, from the left side to the right side, or from the bottom to the top. It may be heading.

  In the period from the start of variable display of the effect symbol to the end of variable display due to the stop display of the confirmed effect symbol in the “left”, “middle”, and “right” symbol display areas, There may be a predetermined reach. Here, the reach state is an effect design ("reach fluctuation design") that is not yet stopped when the effect design that is stopped and displayed on the display screen of the effect display device 9 constitutes a part of the jackpot combination. Is also a display state in which the fluctuation continues, or a display state in which all or part of the design symbols change synchronously while constituting all or part of the jackpot combination. Specifically, a part of the “left”, “middle”, and “right” symbol display areas (for example, “left” and “right” symbol display areas, etc.) produces a predetermined jackpot combination. In the remaining symbol display area (for example, “medium” symbol display area, etc.) that has not been stopped and displayed yet (for example, the symbol that indicates the alphanumeric character “7”) is stopped, Display state, or a display state in which the production symbols in the “left”, “middle”, and “right” symbol display areas are all or part of the jackpot combination and change synchronously It is.

  In response to the reach state, the fluctuation speed of the effect symbol is reduced, or a character image (effect image imitating a person) different from the effect symbol is displayed on the display screen of the effect display device 9. Or changing the display mode of the background image or changing the changing mode of the effect pattern, an effect operation different from that before reaching the reach state may be executed. Such effect operations such as display of the character image, change of the display mode of the background image, and change of the variation pattern of the effect pattern are referred to as reach effect display (or simply reach effect). In the reach effect, not only the display operation on the display screen of the effect display device 9, but also the sound output operation by the speaker 27, the lighting operation (flashing operation) of the frame LED 28, and the like are the operation modes before reaching the reach state. May be included in different modes of operation. As an effect operation in the reach effect, a plurality of types of effect patterns (also referred to as “reach patterns”) having different operation modes (reach modes) may be prepared in advance. Each reach mode has a different possibility of “big hit” (also referred to as “reliability”).

  When a special symbol that becomes a lost symbol is stopped and displayed as a confirmed special symbol in the special symbol game, after the variable display of the production symbol is started, the variable display state of the production symbol does not become the reach state, but the predetermined design. There are cases where the finalized design that is a non-reach combination is stopped and displayed. Such a variable display mode of the effect symbol is referred to as a variable display mode of “non-reach” (also referred to as “unreachless loss”) when the variable display result is “losing”.

  When a special symbol that becomes a losing symbol is stopped and displayed as a confirmed special symbol in the special symbol game, it corresponds to the fact that the variable symbol display state has reached the reach state after the variable symbol symbol display has started. Then, after the reach effect is executed, the confirmed effect symbol that becomes a predetermined reach-losing combination may be stopped and displayed. Such a variable display result of the effect symbol is referred to as a variable display mode of “reach” (also referred to as “reach lose”) when the variable display result is “losing”.

  When a special symbol indicating the number “3”, which is a 15R non-probable variable symbol, is stopped and displayed as a special symbol to be confirmed in the special symbol game as a 15R jackpot symbol, the variable display state of the effect symbol is reached. In response to the state being reached, after a predetermined reach effect is executed, a predetermined effect symbol that is a predetermined normal jackpot combination is stopped and displayed. Here, the confirmed effect symbols that are usually the big hit combinations are, for example, symbol numbers “1” to “8” that are variably displayed in the symbol display areas of “left”, “middle”, and “right” in the effect display device 9. Of the effect symbols, any one of the effect symbols whose symbol numbers are an even number “2”, “4”, “6”, “8” is the symbol display area of “left”, “middle”, “right” As long as they are stopped and displayed on a predetermined effective line. In this way, the effect symbols having the even number “2”, “4”, “6”, “8” constituting the normal jackpot combination are referred to as normal symbols (also referred to as “non-probable variation symbols”). Then, in response to the confirmed special symbol in the special figure game becoming the 15R non-probable variable symbol, after the predetermined reach effect is executed, the variable effect display mode of the effect symbol in which the confirmed effect symbol of the normal jackpot combination is stopped and displayed Is referred to as a variable display mode (also referred to as a jackpot type) of “15R uncertain change” when the variable display result is “big hit”. Thus, after the variable display result is “big hit” by the variable display mode of “15R uncertain change”, it is controlled to the 15R big hit gaming state, and when the 15R big hit state is finished, it is controlled to the short time state or the normal state. become.

  When the special symbol indicating the number “7”, which is the 15R probability variation symbol, is stopped and displayed as the special symbol to be determined as the special symbol game in the special symbol game, the variable symbol display state of the effect symbol is the reach state. Corresponding to the fact that the reach effect is the same as when the jackpot type is “normal”, or the reach effect is different from the case where the jackpot type is “normal” In some cases, a definite effect symbol that is a predetermined probability variation big hit combination is stopped and displayed. Here, the confirmed effect symbols that are the probable big hit combinations are, for example, symbol numbers “1” to “8” that are variably displayed in the “left”, “middle”, and “right” symbol display areas in the effect display device 9. Of the effect symbols, any one of the effect symbols whose symbol numbers are odd numbers “1”, “3”, “5”, “7” is the symbol display area of “left”, “middle”, “right”. As long as they are stopped and displayed on a predetermined effective line. The effect symbols whose odd number “1”, “3”, “5”, “7” constituting the probability variation big hit combination are called probability variation symbols. Then, in response to the confirmed special symbol in the special figure game becoming the 15R probability variable symbol, after the reach effect is executed, the variable effect display mode of the effect symbol in which the confirmed effect symbol of the probability variable big hit combination is stopped is variable. This is referred to as a variable display mode (also referred to as a big hit type) of “15R probability change” when the display result is “big hit”.

  When the 15R probability variation symbol is stopped and displayed as a special symbol for special game, the fixed effect symbol that is a normal jackpot combination may be stopped and displayed as a variable display result of the effect symbol. In this way, even when the confirmed effect symbol that is a normal jackpot combination is stopped and displayed, if the 15R probability variable symbol is stopped and displayed as the confirmed special symbol in the special game, it is included in the variable display mode of “15R probability variation”. . Thus, after the variable display result is “big hit” by the variable display mode of “15R positive change”, the 15R big hit state is controlled, and when the 15R big hit state ends, the variable change state is controlled to the positive change state.

  The re-lottery effect may be executed during the variable display of the effect symbol in which the determined effect symbol is a normal jackpot combination or a probable variation jackpot combination. In the redraw lottery effect, after the effect symbols of the normal big hit combination are temporarily stopped and displayed on the effective lines in the symbol display areas of “left”, “middle”, and “right” in the effect display device 9, for example, “left”, “ In the middle and right symbol display areas, the same effect symbols are changed and then changed again, the effect symbol (probability variation symbol) that becomes the probability variation jackpot combination, and the effect symbol (normal symbol) that becomes the normal jackpot combination Is stopped and displayed (derived display) as a confirmed effect design. Here, when the re-lottery effect is executed when the big hit type is “15R uncertain change”, as the re-lottery effect, the fixed effect that becomes the normal big hit combination after re-changing the temporarily stopped display effect symbol A re-lottery failure effect for deriving and displaying symbols is performed. On the other hand, when the re-lottery effect is executed when the big hit type is “15R probability change”, the re-lottery effect is confirmed to be the probability change big hit combination after re-changing the temporarily stopped display effect symbol. A re-lottery success effect that derives and displays an effect symbol may be executed, or a re-lottery failure effect may be executed.

  Whether or not to control to a high-probability gaming state such as a probable change state during the period until the end of the 15R big hit state after the definite effect symbol that is usually a big hit combination is derived and displayed ) May be executed in the probability change promotion effect (also referred to as a jackpot promotion effect). Here, the timing when the probability variation promotion effect is executed may be a period before the first round in the 15R big hit state is started after the variable display result (final stop symbol) is derived and displayed, or 15R It may be a period during which any round is being executed in the jackpot state, or may be a period from the end of any round in the 15R jackpot state until the start of the next round, or 15R It may be a period from the end of the final round in the big hit state to the start of the next variable display. Alternatively, during the first special symbol or effect symbol variation display after the end of the 15R big hit state, an effect operation corresponding to the probability change promotion effect may be performed. The probability change promotion effect that is executed after the final round in the 15R big hit state is sometimes referred to as an “ending promotion effect”.

  In the probable change promotion effect, the probable change promotion success effect informing that there is a promotion in which the game state becomes a probable change state even though the final effect symbol is a normal jackpot combination, and informing that there is no promotion in the probable change state There is a certain change promotion failure production. For example, in the probability change promotion effect, the effect symbol is variably displayed in the display area of the effect display device 9 and either the normal symbol or the probability variable symbol is stopped and displayed as the effect display result, or the effect symbol variable display is What is necessary is just to alert | report so that a player can recognize the presence or absence of the promotion which will be in a probability change state by displaying a different production image. In the 15R big hit state based on the big hit type being “15R non-probable change”, the probable change promotion failure effect may be executed. On the other hand, in the 15R big hit state based on the big hit type being “15R probability change”, the probability change promotion success effect may be executed or the probability change promotion failure effect may be executed. Even if the jackpot type is “15R probability change”, when the probability change promotion failure production is executed, the game state becomes the probability change state even though the game state becomes the probability change state after the jackpot game state ends. The notification to that effect is not performed.

  When the special symbol indicating the number “5” that is the 2R big hit symbol is stopped and displayed as the final special symbol in the special game, the special symbol indicating the number “2” that is the small hit symbol is stopped and displayed. In such a case, the variable display state of the effect symbol does not reach the reach state, and any one of combinations of a plurality of types of finalized effect symbols predetermined as the second opening chance is stopped and displayed. In response to the special symbol in the special symbol game being a special symbol indicating the number “5”, which is a 2R probability variation symbol, the variable display mode of the effect symbol in which various final effect symbols are stopped and displayed is a variable display result. Is a variable display mode (also called a big hit type) of “2R accuracy” (also called “sudden probability change big hit”).

  In addition, when a special symbol that is a 2R big hit symbol or a small hit symbol is stopped and displayed as a confirmed special symbol in the special symbol game, a predetermined display corresponding to the fact that the variable display state of the effect symbol has reached the reach state. After the reach effect is executed, a confirmed effect symbol that becomes a predetermined reach-losing combination may be stopped and displayed. In addition, when a special symbol that becomes a 2R big hit symbol or a small hit symbol is stopped and displayed as a confirmed special symbol in the special symbol game, the variable display state of the effect symbol does not reach the reach state, and the second chance of opening is displayed. A finalized design symbol that is a predetermined non-reach combination different from the above may be stopped and displayed.

  Thus, after the variable display result becomes “big hit” by the variable display mode of “2R hit accuracy”, the 2R big hit state is controlled, and when the 2R big hit state ends, the probability change state is controlled. After the variable display result becomes “small hit”, the game state before the variable display result becomes “small hit” continues after the variable winning operation is performed under the control of the small hit gaming state. However, if it is determined that the special game state is to be ended corresponding to the special game whose variable display result is “small hit”, the normal state is controlled after the small hit game state is ended. .

  Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. FIG. 3 is a rear view of the gaming machine as seen from the back side. As shown in FIG. 3, on the back side of the pachinko gaming machine 1, a variable display control unit including an effect control board 80 on which an effect control microcomputer 100 for controlling the effect display device 9 is mounted, a game control microcomputer 560, etc. Various boards such as a game control board (main board) 31 on which is mounted, an audio output board 70, a lamp driver board 35, and a payout control board 37 on which a payout control microcomputer for performing ball payout control is mounted. ing. The game control board 31 is stored in the board storage case 200.

  Further, on the back side of the pachinko gaming machine 1, a power supply is mounted with a power supply circuit for creating various power supply voltages such as VSL (DC30V), VLP (DC24V), VDD (DC12V), VBB (DC5V) and VCC (DC5V). A substrate 910 and a touch sensor substrate 91 are provided. The power supply board 910 is supplied with the game control board 31 and each electrical component control board (the effect control board 80 and the payout control board 37) in the pachinko gaming machine 1 and each electrical component (power is supplied) provided in the pachinko gaming machine 1. A power switch or the like is provided as a power supply permission means for executing or shutting off power supply to a component that operates as a result. Further, a replaceable fuse is provided inside the power switch (inside the substrate).

  FIG. 4 shows various circuits mounted on the power supply substrate 910. For example, the power supply board 910 includes a transformer circuit 911, a DC voltage generation circuit 912, a power supply monitoring circuit 913, and a clear switch 914. The power supply substrate 910 may be provided with a capacitor serving as a backup power supply. For example, this capacitor may be charged from a power supply line of VBB (DC5V).

  For example, the transformer circuit 911 may be configured to include a transformer to which commercial power is applied to the input side (primary side), a varistor as an overvoltage protection circuit provided on the input side of the transformer, and the like. Here, the transformer included in the transformer circuit 911 may be any one that electrically insulates the commercial power supply from the power supply board 910. The transformer circuit 911 generates AC 24V as its output voltage. The DC voltage generation circuit 912 includes a rectifying / smoothing circuit that generates VSL by, for example, rectifying and boosting AC 24V with a rectifying element. VSL is used as a power supply voltage for driving the solenoid. In addition, the DC voltage generation circuit 912 includes a rectification circuit that generates VLP by rectifying, for example, AC 24V with a rectification element. The VLP is used as a power supply voltage for lighting a light emitter such as a game effect lamp (for example, a decoration lamp 25, a top frame lamp 28a, a left frame lamp 28b, and a right frame lamp 28c). In addition, the DC voltage generation circuit 912 includes a DC-DC converter that generates VDD and VCC based on, for example, VSL. This DC-DC converter includes, for example, one or more switching regulators and a relatively large capacity capacitor connected to the input side of the switching regulator, and power supply to the pachinko gaming machine 1 from the outside is stopped. Sometimes, it may be configured so that the direct current voltage such as VSL, VDD, VBB, etc. decreases relatively slowly. The VDD is supplied to various switches for detecting game media such as the gate switch 32a, the start port switch 14a, the winning confirmation switch 14b, the count switch 23, and the winning port switches 29a and 30a, and is used to operate these switches. It is done.

  As shown in FIG. 4, AC24V output from the transformer circuit 911 is transmitted to the payout control board 37 via, for example, a predetermined connector or a power supply line. The VLP is transmitted to the lamp driver board 35 via, for example, a predetermined connector or a power supply line. VSL, VDD, and VCC are transmitted to the main board 31, the lamp driver board 35, and the payout control board 37 through, for example, predetermined connectors and power supply lines. The VBB is transmitted to the main board 31 and the payout control board 37 via, for example, a predetermined connector and a power supply line. Note that each voltage may be supplied to the effect control board 80 and the sound control board 70 via the lamp driver board 35. Alternatively, each voltage may be directly supplied to the effect control board 80 and the audio control board 70 from the power supply board 910 without going through the lamp driver board 35.

  The power monitoring circuit 913 is configured by using, for example, a power failure monitoring reset module IC, and is a circuit that realizes power monitoring means for outputting a power interruption signal. For example, when a predetermined power supply voltage (VSL as an example) used in the pachinko gaming machine 1 exceeds a predetermined value (+22 V as an example), the power supply monitoring circuit 913 outputs a power-off signal in an off state (high level). On the other hand, when the period during which the predetermined power supply voltage is equal to or lower than the predetermined value continues for a predetermined time (for example, 56 ms), an on-state (low level) power-off signal is output. Alternatively, the power supply monitoring circuit 913 may output a power-off signal in an on state immediately when a predetermined power supply voltage used in the pachinko gaming machine 1 becomes a predetermined value or less. For example, the power-off signal may be a negative logic electric signal that is turned on when it is low and turned off when it is high. The power-off signal output from the power supply monitoring circuit 913 is amplified by, for example, an output driver circuit mounted on the power supply board 910 and then transmitted to the main board 31 or the payout control board 37 via a predetermined connector or signal line. Is done. The power-off signal may be transmitted to the main board 31 through the payout control board 37.

  The predetermined power supply voltage to be monitored for outputting the power-off signal is preferably a voltage higher than a specified value (for example, +12 V) in the power supply voltage VDD for operating the switch, such as the power supply voltage VSL. As a result, the power supply voltage VDD for operating the switch decreases, and the operation states of various switches (for example, the gate switch 32a, the start port switch 14a, the winning confirmation switch 14b, the count switch 23, the winning port switches 29a, 30a, etc.) are unstable. Before it becomes, by outputting a power-off signal (turning on), it is possible to prevent the progress of game control based on erroneous detection by various switches. That is, when the power supply voltage VDD for operating the switch is lowered, the switch output of the negative logic (turned on at a low level) is turned on, but the power supply voltage VSL that drops earlier than the power supply voltage VDD is monitored to supply power By recognizing the stop, it becomes possible to enter a state of waiting for power supply recovery and not detecting the switch output before the switch output is turned on.

  A large capacity capacitor may be connected to a power supply line for transmitting the power supply voltage VSL and the like to the main board 31, the lamp driver board 35, and the payout control board 37. On the other hand, such a capacitor may not be connected to the input line that transmits to the power supply monitoring circuit 913 in order to monitor the power supply voltage VSL. In this case, the power supply voltage VSL on the input line to the power supply monitoring circuit 913 to be monitored drops earlier than the power supply voltage VSL on the power supply line to which the capacitor is connected. That is, even after the monitored power supply voltage VSL starts to decrease, the supply state of the power supply voltage VSL in the power supply line supplied to the solenoid, the motor, or the like is maintained for a predetermined period. Therefore, even when the power supply voltage VSL to be monitored starts to decrease, the solenoid, the motor, and the like can be driven for a predetermined period. Further, it is possible to recognize the stop of the power supply before the power supply voltage VSL in the power supply line starts to decrease.

  In place of the solenoid drive power supply voltage VSL, for example, a power cut-off signal is generated by monitoring an arbitrary power supply voltage higher than a specified value in the switch operation power supply voltage VDD, for example, the power supply voltage VLP for lighting the light emitter. You may make it output. In addition, the condition for detecting the stop of the supply of power supplied to the pachinko gaming machine 1 from the outside is not limited to the fact that the predetermined power supply voltage used in the pachinko gaming machine 1 has become a predetermined value or less. Any condition can be used as long as it is possible to detect that the power has been cut off. For example, the AC wave such as AC 24V may be monitored to detect that the AC wave has stopped, or the signal obtained by digitizing the AC wave may be monitored and the AC signal may be generated when the digital signal becomes flat. It may be a detection condition for the interruption.

  For example, the power supply monitoring circuit 913 may output a reset signal when a predetermined power supply voltage (VCC as an example) becomes a predetermined value (+4.5 V as an example) or less. The reset signal may be an electric signal that is turned on when the reset signal becomes low level, for example. The reset signal output from the power supply monitoring circuit 913 is amplified by, for example, an output driver circuit mounted on the power supply board 910, and then, via a predetermined connector or signal line, the main board 31, the lamp driver board 35, and the payout control board. 37. A reset signal may be transmitted to the effect control board 80 via the lamp driver board 35. Alternatively, the reset signal may be transmitted directly to the effect control board 80 without going through the lamp driver board 35. Further, the circuit that outputs the reset signal may be configured using a watchdog timer built-in IC provided separately from the power supply monitoring circuit 913, a system reset IC, or the like.

  When the power supply to the pachinko gaming machine 1 is stopped, the power monitoring circuit 913 outputs a reset signal (sets to a low level) when a predetermined period elapses after the power-off signal is output (set to a low level). ) In this predetermined period, for example, the game control microcomputer 560 mounted on the main board 31 and the payout control microcomputer 370 mounted on the payout control board 37 execute predetermined power-off processing. It is sufficient if the time is sufficient. That is, the power monitoring circuit 913 outputs a power-off signal as a power supply stop signal, and after the game control microcomputer 560 and the payout control microcomputer 370 complete execution of predetermined power-off processing, the operation stop signal The reset signal is output (set to low level). The game control microcomputer 560 and the payout control microcomputer 370 that have received the reset signal output from the power monitoring circuit 913 are in an operation stop state, and execution of various control processes is stopped. In addition, when power supply to the pachinko gaming machine 1 is started, for example, when a predetermined power supply voltage (VCC as an example) exceeds a predetermined value (+4.5 V as an example), the power supply monitoring circuit 913 stops the output of the reset signal (Set to high level).

  FIG. 5 is a timing diagram schematically showing the states of the AC 24 V, VSL, VCC, reset signal, and power-off signal when power supply to the pachinko gaming machine 1 is started and when power supply is stopped. is there. As shown in FIG. 5, when power supply to the pachinko gaming machine 1 is started, VSL and VCC gradually reach specified values (DC +30 V and DC +5 V). At this time, when VCC exceeds the first predetermined value, the power supply monitoring circuit 913 stops the output of the reset signal (sets it to a high level) and turns it off. Further, when VSL exceeds the second predetermined value, the power supply monitoring circuit 913 stops (sets to a high level) the output of the power-off signal and turns off. On the other hand, when the power supply to the pachinko gaming machine 1 is stopped, VSL and VCC gradually decrease. At this time, when VSL falls to the second predetermined value, the power monitoring circuit 913 outputs the power-off signal as an ON state (sets it to a low level). When VCC decreases to the first predetermined value, the power monitoring circuit 913 outputs a reset signal as an ON state (sets it to a low level).

  The clear switch 914 provided in the power supply board 910 illustrated in FIG. 4 has a push button structure, for example, and outputs a clear signal that is turned on in response to a predetermined operation such as a press operation. The clear signal may be an electrical signal that is turned on when it becomes low level in response to a predetermined operation such as a pressing operation. Alternatively, the clear signal may be an electric signal that is turned on when the clear signal becomes a high level in response to a predetermined operation such as a pressing operation. The clear signal output from the clear switch 914 is transmitted to the main board 31 via, for example, a predetermined connector or signal line, and is transmitted from the main board 31 to the dispensing control board 37. When the clear switch 914 is not operated, the output of the clear signal is stopped (set to a high level or a low level). Note that the clear switch 914 may have a configuration other than the push button structure (for example, a slide switch structure, a toggle switch structure, a dial switch structure, or the like).

  In this embodiment, the main board 31 is provided on the game board side, and the payout control board 37 is provided on the game frame side. Even in such a configuration, as will be described later, the communication between the main board 31 and the payout control board 37 is performed by serial communication, thereby facilitating the routing of the wiring when replacing the game board. .

  Each control board is equipped with control means including a control microcomputer. The control means is an electrical component (game device: ball payout device 97, effect display device 9, light emission from a lamp, LED, etc.) provided in the gaming machine according to a command signal (control signal) as a command from the game control means or the like. Body, speaker 27, etc.). Hereinafter, the main board 31 may be included in the control board for explanation. In that case, the control means mounted on the control board refers to each of the game control means and the means for controlling the electrical components provided in the gaming machine in accordance with a command signal from the game control means or the like. A substrate on which a microcomputer other than the main substrate 31 is mounted may be referred to as a sub-substrate. The ball payout device 97 is a device for paying out a game ball guided by a passage for guiding the game ball and a sprocket driven by a stepping motor or the like to an upper plate or a lower plate. A payout number counting switch for counting prize balls and rental balls is also configured as part of the unit. In this embodiment, the payout detection means is realized by the payout number count switch 301 and has a function of detecting that a winning ball or a lending ball is actually paid out from the ball payout device 97. In this case, the payout number count switch 301 outputs a detection signal every time one payout of prize balls or rental balls is detected.

  On the back side of the pachinko gaming machine 1, a terminal board 160 having terminals for outputting various information to the outside of the pachinko gaming machine 1 is installed above. On the terminal board 160, for example, an information output signal such as jackpot information indicating the occurrence of a jackpot gaming state (starting port signal, symbol determination number 1 signal shown in FIG. 64, gaming machine specific information, jackpot 1 signal, jackpot 2 signal, An information output terminal is provided for externally outputting three jackpot signals, a short time signal, a security signal, a throwing state signal, a prize ball signal 1, a gaming machine error state signal, and a door opening signal.

  The game ball stored in the storage tank 38 passes through a guide rail (not shown), and reaches a ball payout device 97 covered with a payout case 40A through a curve rod. Above the ball payout device 97, a ball break switch 187 is provided as a game medium break detection means. When the ball break switch 187 detects a ball break, the payout operation of the ball payout device 97 stops. The ball break switch 187 is a switch that detects the presence or absence of a game ball in the game ball passage. (Proximate part). When the ball break detection switch 167 detects a shortage of game balls, the game balls are replenished to the pachinko gaming machine 1 from the replenishment mechanism provided on the gaming machine installation island.

  When a large number of game balls as prizes based on winning a prize or a game ball based on a ball lending request are paid out and the hitting ball supply tray 3 is full, the game balls are guided to the surplus ball receiving tray 4 through the surplus ball guiding path. Further, when the game ball is paid out, a sensing lever (not shown) presses the full tank switch as the storage state detection means, and the full tank switch as the storage state detection means is turned on. In this state, the rotation of the payout motor in the ball payout device is stopped, the operation of the ball payout device is stopped, and the driving of the ball hitting device is also stopped.

  In this embodiment, a door opening switch 155a for detecting that the glass door frame 2 or the mechanism plate is opened with respect to the front frame is attached above the game frame 11. The glass door frame 2 is attached to the front frame of the game frame 11 so that it can be opened and closed on the front side. The mechanism plate of the game frame 11 is attached so as to be openable and closable on the back side with respect to the front frame. When at least one of the mechanical doors of the glass door frame 2 or the game frame 11 is opened with respect to the front frame, the door open switch 155a detects the door open state and outputs a door open signal. As a specific example, the door opening switch 155a is attached in such a manner that a bar-like member with a spring penetrates the front frame. When the rod-like member is detected by the detection switch provided on the mechanism plate, a signal indicating that the door is not opened is output. In this case, if the glass door frame 2 and the mechanism plate are both closed, the rod-shaped member is pressed from the front by the glass door frame 2 and protrudes rearward from the front frame, and the detection switch opens the door. The state is not detected (off state). When the glass door frame 2 is opened, the rod-like member pops out to the front side of the front frame due to the elasticity of the spring, and the detection switch is not pressed by the rod-like member. A state where either one or both of them is detected to be open is output (ON state). Further, if the mechanism plate is opened, the rod-shaped member is projected to the back side of the front frame by the elasticity of the spring, but the detection switch is not pressed by the rod-shaped member. A state in which a signal that detects that one of or both the frame 2 and the mechanism plate is open is output (ON state).

  A door opening switch 155b for detecting that the gaming frame 11 itself has been opened with respect to the outer frame 2A is attached to the right side of the mechanism plate of the gaming frame 11. The game frame 11 is attached to the outer frame 2A so as to be openable and closable. When the gaming frame 11 is opened with respect to the outer frame 2A, the door opening switch 155b detects the opened state of the gaming frame 11 and outputs a door opening signal. As a specific example, the door opening switch 155b is provided on the mechanism plate of the gaming frame 11, and when the gaming frame 11 is opened with respect to the outer frame 2A, it is detected that the gaming frame 11 has been opened. The signal shown in FIG. When the game frame 11 is not opened with respect to the outer frame 2A, a signal indicating that the game frame 11 is not opened is output (off state).

  FIG. 6 is an explanatory diagram showing a specific example of a cross-sectional structure in the start winning opening 14. As shown in FIG. 6, in the start winning opening 14, two switches (start opening switch 14 a and winning confirmation switch 14 b) capable of detecting a game ball won in the start winning opening are provided. In this embodiment, as shown in FIG. 6, the start opening switch 14a and the winning confirmation switch 14b are arranged vertically in the start winning opening 14 (in this example, the start opening switch 14a is arranged on the upper side. And a winning confirmation switch 14b is arranged on the lower side). Therefore, in this embodiment, the game ball won in the start winning opening 14 is guided to the back of the game board 6 and is first detected by the start opening switch 14a and then detected by the winning confirmation switch 14b.

  Also, different detection system switches are used as the start port switch 14a and the winning confirmation switch 14b. In this embodiment, a case where a proximity switch is used as the start port switch 14a and a photo sensor is used as the winning confirmation switch 14b is shown.

  In this embodiment, as will be described later, on the basis of the fact that a game ball is detected by the start port switch 14a, a special symbol variation display is started and a prize ball payout is executed. Further, as will be described later, the presence or absence of an abnormal winning is determined based on the detection result of the winning confirmation switch 14b in addition to the detection result of the start port switch 14a, and the security signal is detected based on the detection of the abnormal winning. Is output externally. Therefore, in this embodiment, the winning confirmation switch 14b is used only for determining an abnormal winning.

  The detection method of the start port switch 14a and the winning confirmation switch 14b is not limited to that shown in this embodiment. For example, if the detection method is different between the starting port switch 14a and the winning confirmation switch 14b, the detection method is reversed. A photo sensor may be used as the start port switch 14a, and a proximity switch may be used as the winning confirmation switch 14b. In this case, a special symbol change display and a winning ball payout process are executed based on the detection result of the start opening switch 14a which is a photosensor, and the detection result of the winning confirmation switch 14b which is a proximity switch indicates that the start winning opening 14 is abnormal. It will be used only for winning decisions. Further, for example, instead of a proximity switch or an optical photosensor that is an electromagnetic switch, a mechanical switch (such as a micro switch) may be used as the start port switch 14a or the winning confirmation switch 14b.

  FIG. 7 is a circuit diagram for explaining a method of detection means capable of detecting a game ball. FIG. 7A shows a start port switch 14a (proximity switch). The + 12V power supply voltage is supplied from the power supply board 910 to one terminal of the start port switch 14a. A detection signal that is the voltage level of the other terminal of the start port switch 14 a is input to the main board 31. In the main board 31, the detection signal is input from the input driver circuit to the input port of the game control microcomputer 560. A resistor R and a capacitor C, one end of which is grounded, are connected to the output side of the start port switch 14a.

  When a metal game ball passes through a hole provided in the start port switch 14a which is a proximity switch, a counter electromotive force is generated in the coil L, and the equivalent resistance value of the coil L becomes extremely large. Accordingly, the output of the start port switch 14a becomes a low level close to 0V. That is, the detection signal is at a low level. When the metal game ball does not pass through the hole provided in the start port switch 14a, the output of the start port switch 14a is a value obtained by dividing + 12V by the resistance value of the coil L and the resistance R. Exceed a threshold level, which is considered to be high. That is, the detection signal is at a high level. Therefore, in this embodiment, the game control microcomputer 560 can determine that the start port switch 14a is in the OFF state if the output from the start port switch 14a is at a high level. Can be determined that the start port switch 14a is in the ON state (that is, the output of the start port switch 14a is negative logic). The detection signal level may be logically inverted by the input driver circuit and then input to the game control microcomputer 560.

  FIG. 7B shows a winning confirmation switch 14b (photo sensor). The photosensor illustrated in FIG. 7B includes a light-emitting diode (LED) 341 that emits light and a phototransistor 342 that receives light and outputs current. When the game ball passes in the vicinity of the light-emitting diode 341 and the phototransistor 342, the phototransistor 342 receives light from the light-emitting diode 341 reflected by the game ball and causes a current to flow to the output side. In this case, since a current flows from the collector terminal of the phototransistor 342 toward the emitter terminal, the detection signal of the photosensor is negative logic as in the proximity switch. The output side of the photosensor is connected to the main board 31, and the detection signal of the photosensor is input to the input port of the game control microcomputer 560 from the input driver circuit in the main board 31. When a current flows to the output side of the photosensor (specifically, the output side of the phototransistor 342), the input driver circuit outputs a high level detection signal to the game control microcomputer 560. As with the proximity switch, the level of the detection signal may be logically inverted by an input driver circuit and then input to the game control microcomputer 560.

  When the detection signal from the input driver circuit is at a low level, the game control microcomputer 560 can determine that the game ball has passed the photo sensor.

  In this embodiment, a reflective photosensor is used as a photosensor. As shown in the upper part of FIG. 7C, a light-emitting element (LED 341) and a light-receiving element (phototransistor 342) are used as winning balls. The game balls that have been installed so as to face each other and the game ball blocks light from the light emitting element and the light receiving element does not detect the light, thereby detecting the game ball that has passed between the light emitting element and the light receiving element. A transmissive photosensor may be used. When a transmissive photosensor is used, as shown in the lower part of FIG. 7C, the optical axis of the light emitting element (illustrated by a black circle in FIG. 7C) is a game ball path (winning ball). It is preferable to install the light emitting element and the light receiving element so as to deviate from the center of the game ball passing through the route. Compared with the case where the optical axis is set so as to correspond to the center of the game ball, a portion where the interval between two game balls passing through is relatively wide (the portion of “void” in FIG. 7C) This is because the game ball can be detected at, and the two game balls can be easily detected separately. For the same reason, when using the reflective photosensor illustrated in FIG. 7B, the light emitting element and the light receiving element are installed so that the reflection point of the light from the light emitting element is deviated from the center of the game ball. It is preferable to do.

  FIG. 8 is a block diagram showing an example of a circuit configuration in the main board (game control board) 31. FIG. 8 also shows a payout control board 37, an effect control board 80, and the like. A game control microcomputer (corresponding to game control means) 560 for controlling the pachinko gaming machine 1 according to a program is mounted on the main board 31. The game control microcomputer 560 includes a ROM 54 for storing a game control (game progress control) program and the like, a RAM 55 as storage means used as a work memory, a CPU 56 for performing control operations in accordance with the program, and an I / O port unit 57. including. In this embodiment, the ROM 54 and the RAM 55 are built in the game control microcomputer 560. That is, the game control microcomputer 560 is a one-chip microcomputer. The one-chip microcomputer only needs to include at least the RAM 55, and the ROM 54 may be external or internal. The I / O port unit 57 may be externally attached.

  In the game control microcomputer 560, the CPU 56 executes control in accordance with the program stored in the ROM 54, so that the game control microcomputer 560 (or CPU 56) executes (or performs processing) hereinafter. Specifically, the CPU 56 executes control according to a program. The same applies to microcomputers mounted on substrates other than the main substrate 31.

  The game control microcomputer 560 includes a random number circuit 503. The random number circuit 503 is a hardware circuit that is used to generate a random number for determination to determine whether or not to win a jackpot based on a display result of variable symbol special display. The random number circuit 503 updates numerical data in accordance with a set update rule within a numerical range in which an initial value (for example, 0) and an upper limit value (for example, 65535) are set, and starts at a random timing Based on the fact that the winning time is the reading (extraction) of the numerical data, it has a random number generation function in which the numerical data to be read becomes a random value.

  The random number circuit 503 includes a numeric data update range selection setting function (initial value selection setting function and upper limit value selection setting function), numeric data update rule selection setting function, and numeric data update rule selection. It has various functions such as a switching function. With such a function, the randomness of the generated random numbers can be improved.

  Further, the game control microcomputer 560 has a function of setting an initial value of numerical data updated by the random number circuit 503. For example, the ID number of the game control microcomputer 560 stored in a predetermined storage area such as the ROM 54 (such as a chip individual number as an ID number assigned to each product of the game control microcomputer 560). The numerical data obtained by performing a predetermined calculation using the data is set as an initial value of the numerical data updated by the random number circuit 503. By performing such processing, the randomness of the random number generated by the random number circuit 503 can be further improved.

  The game control microcomputer 560 reads numerical data from the random number circuit 503 when a start winning to the start port switch 14a occurs, stores the random number value in a predetermined area of the RAM 55 such as a special figure holding memory, At the start of the variation of the effect symbol, it is determined whether or not to make the jackpot display result as a specific display result based on the stored random number value, that is, whether or not to make the jackpot. Then, when it is determined to be a big hit, the gaming state is shifted to a big hit gaming state as a specific gaming state advantageous to the player.

  Further, the game control microcomputer 560 inputs / outputs (transmits / receives) signals to / from the payout control board 37 (the payout control microcomputer 370) and the effect control board 80 (the effect control microcomputer) by serial communication. Serial communication circuit 505 is incorporated. The payout control microcomputer 370 and the effect control microcomputer also incorporate a serial communication circuit for inputting / outputting signals to / from the game control microcomputer 560 through serial communication (the payout control microcomputer 370 includes (See FIG. 10 for the built-in serial communication circuit). The game control microcomputer 560 includes a two-channel serial communication circuit 505, and can perform serial communication with the payout control microcomputer 370 and also performs serial communication with the effect control microcomputer 100. It is possible. However, in this embodiment, for serial communication with the production control microcomputer 100, a signal is output only from the game control microcomputer 560 to the production control microcomputer, and the production control microcomputer 100 No signal is output to the game control microcomputer 560. Note that the communication between the game control microcomputer 560 and the effect control microcomputer is not limited to the serial communication configuration, and may be configured to perform parallel communication.

  The RAM 55 is a backup RAM as a non-volatile storage means that is partly or wholly backed up by a backup power source created on the power supply board 910, and changes that occur when various controls are performed in the pachinko gaming machine 1. Store data. Accordingly, a part or all of the contents of the RAM 55 is stored for a predetermined period (until the backup power supply is discharged and the backup power supply cannot be supplied) even if the power supply to the gaming machine is stopped. . In particular, at least data corresponding to the game state, that is, the control state of the game control means (such as the value of the special symbol process flag and the pending storage number counter) and data indicating the number of unpaid prize balls (specifically, prize balls described later) The value of the command output counter) is stored in the backup RAM. The data corresponding to the control state of the game control means is data necessary for restoring the control state before the occurrence of a power failure or the like based on the data when the power is restored after a power failure or the like occurs. Further, data corresponding to the control state and data indicating the number of unpaid prize balls are defined as data indicating the progress state of the game. The variation data stored in the RAM 55 includes data indicating whether or not the gaming state of the pachinko gaming machine 1 is a special gaming state such as a probability variation state. In this embodiment, it is assumed that the entire RAM 55 is backed up.

  A reset signal from the power supply board 910 is input to the reset terminal of the game control microcomputer 560. The power supply board 910 is equipped with a reset circuit that generates a reset signal supplied to the game control microcomputer 560 and the like. When the reset signal becomes high level, the game control microcomputer 560 and the like are in an operable state, and when the reset signal becomes low level, the game control microcomputer 560 and the like are in an operation stop state. Therefore, an allowable signal that allows the operation of the game control microcomputer 560 or the like is output during a period when the reset signal is at a high level, and a game control microcomputer is output when the reset signal is at a low level. An operation stop signal for stopping the operation of 560 or the like is output. Note that the reset circuit may be mounted on each electric component control board (a board on which a microcomputer for controlling the electric parts is mounted).

  Furthermore, a power-off signal indicating that the power supply voltage from the power supply board 910 has dropped below a predetermined value is input to the input port of the game control microcomputer 560. That is, the power supply board 910 monitors the voltage value of a predetermined voltage (for example, VSL (DC30V), VCC (DC5V), etc.) used in the gaming machine, and the voltage value is reduced to a predetermined value. Then (when a drop in the power supply voltage is detected), a power supply monitoring circuit that outputs a power-off signal indicating that fact is mounted. Note that the power supply monitoring circuit may be mounted not on the power supply board 910 but on a board (for example, the main board 31) backed up by a backup power supply. A clear signal indicating that the clear switch 914 for instructing to clear the contents of the RAM 55 is operated is input to the input port of the game control microcomputer 560.

  A gate switch 32a, a start port switch 14a, a winning confirmation switch 14b, a count switch 23, and an input driver circuit 58 that supplies detection signals from the winning port switches 29a and 30a to the basic circuit 53 are also mounted on the main board 31. A solenoid 16 that opens and closes the variable winning ball device 15 and an output circuit 59 that drives the solenoid 21 that opens and closes the special variable winning ball device according to a command from the basic circuit 53 are also mounted on the main board 31, and the game control micro is turned on when the power is turned on. A system reset circuit (not shown) for resetting the computer 560 and an information output signal such as jackpot information indicating the occurrence of the jackpot gaming state are output to an external device such as a hall computer via the terminal board 160. An information output circuit 64 is also mounted on the main board 31.

  In this embodiment, the effect control means (configured by the effect control microcomputer) mounted on the effect control board 80 receives the effect control command from the game control microcomputer 560 via the relay board 77. The display control of the effect display device 9 that receives and displays the effect symbol variably is performed.

  In addition, a door open signal is input to the input port of the game control microcomputer 560 from the backup power supply circuit 508 via the door open switch 155a and the door open switch 155b. The backup power supply circuit 508 may be provided at a predetermined position on the main board 31 outside the game control microcomputer 560, for example. Alternatively, the backup power supply circuit 508 may be provided at a predetermined position on a board different from the main board 31 such as the payout control board 37 or the power supply board 910. Further, the substrate provided with the backup power supply circuit 508 may be configured as a substrate independent of the power supply substrate 910, the main substrate 31, or the payout control substrate 37. When the door opening switch 155a detects that the glass door frame 2 or the mechanism plate is opened with respect to the front frame of the game frame 11, the door opening switch 155a outputs a door opening signal indicating that the door is open. When the door opening switch 155b detects that the game frame 11 itself is opened with respect to the outer frame 2A, the door opening switch 155b outputs a door opening signal indicating that the door is opened.

  FIG. 9 is a circuit diagram showing a connection configuration example of the backup power supply circuit 508, the door opening switch 155a, and the door opening switch 155b. As shown in FIG. 9, a voltage from a backup power source (for example, a battery or a capacitor) 507 provided in the backup power supply circuit 508 is applied to the door opening switch 155a and the door opening switch 155b. Even when the power supply is stopped, the door open state can be detected and the door open signal can be output. The backup power supply 507 may be shared with the backup power supply that supplies the RAM 55 or the like. As a result, the configuration of the backup power supply can be simplified and the cost can be reduced. Alternatively, the backup power supply 507 may be provided separately from the backup power supply supplied to the RAM 55 or the like. As a result, when the power supply to the pachinko gaming machine 1 is stopped, the power supply voltage of the backup power supply decreases due to the output of the door open signal based on the door open detection state, so that the stored information such as the RAM 55 is lost. Can prevent the situation.

  The door opening signal from the door opening switch 155a or the door opening switch 155b is generated by a wiring pattern on a predetermined substrate, wiring connection outside the substrate, or wiring or bus configuration in a predetermined IC chip. After being branched into two, they are transmitted to the input port of the game control microcomputer 560 and the terminal board 160, respectively. The door opening signal may be transmitted to the terminal board 160 via the input port and the output port of the game control microcomputer 560. When the backup power supply circuit 508 is provided outside the main board 31, the door opening signal may be transmitted to the terminal board 160 via the main board 31. Alternatively, the door opening signal may be transmitted to the dispensing control board 37 and then input to the terminal board 160 via the main board 31. The door opening signal may be branched when passing through the main board 31 and transmitted to the input port of the game control microcomputer 560.

  The signal line for transmitting the door opening signal from the door opening switch 155a or the door opening switch 155b may be physically connected from the backup power supply circuit 508 to the terminal board 160. Thereby, even when the power supply to the pachinko gaming machine 1 is stopped, the door opening signal from the door opening switch 155a and the door opening switch 155b is supplied to the terminal board 160. In addition, power from a backup power supply 507 provided in the backup power supply circuit 508 is supplied to the terminal board 160. Thereby, even when the power supply to the pachinko gaming machine 1 is stopped, the terminal board 160 transmits the door opening signal transmitted from the backup power supply circuit 508 to the external device (for example, the hall computer or the card unit 50). Can be output.

  In the backup power supply circuit 508, a backflow prevention diode 508 a is provided on the input side of “+5 V” as a reference potential. As a result, it is possible to prevent the current from the backup power supply 507 from flowing backward to each circuit and each circuit element other than the semiconductor relay PC11 provided on the terminal board 160 and receiving the door opening signal. In the circuit configuration shown in FIG. 9, a detection signal from one or both of the door opening switch 155 a and the door opening switch 155 b is input to the terminal board 160 or the like via the backup power supply circuit 508.

  The door opening signal is not limited to one that outputs a common detection signal indicating that the door opening is detected by one or both of the door opening switch 155a and the door opening switch 155b, and the door opening switch 155a. A plurality of types of door opening signals may be output by separately using the detection signal obtained by the above and the detection signal obtained by the door opening switch 155b as a door opening signal. Alternatively, the door opening switch 155a and the door opening switch 155b are configured as a common door opening switch, and the glass door frame 2 and the mechanism plate are opened with respect to the front frame of the game frame 11, or the outer frame 2A On the other hand, it may be detected in common by one door opening switch that the game frame 11 itself is opened. Alternatively, only one of the opening of the glass door frame 2 and the mechanism plate with respect to the front frame of the gaming frame 11 or the opening of the gaming frame 11 itself with respect to the outer frame 2A is detected. The door opening signal from the door opening switch may be transmitted to the terminal board 160, and the door opening signal from the door opening switch for detecting the other may not be transmitted to the terminal board 160, or the door for detecting the other. The opening switch itself may not be provided. A door opening switch that only detects that the glass door frame 2 is opened with respect to the front frame of the gaming frame 11 may be provided, or only that the mechanism plate is opened with respect to the front frame of the gaming frame 11. A door opening switch for detection may be provided. When only the glass door frame 2 is opened with respect to the front frame of the game frame 11, when only the mechanism plate is opened with respect to the front frame of the game frame 11, and with respect to the front frame of the game frame 11 A combination of door opening switches may be provided so that different door opening signals are output when both the door frame 2 and the mechanism plate are opened. The state where one or both of the glass door frame 2 and the mechanism plate are opened with respect to the front frame of the gaming frame 11 or the state where neither is opened, and the gaming frame 11 is opened with respect to the outer frame 2A. The door opening switch may be provided in combination so that a different door opening signal is output according to the combination of the opened state or the unopened state.

  The door opening switch 155a and the door opening switch 155b are in an off state (non-energized state) when the glass door frame 2, the mechanism plate, or the game frame 11 is not opened, and are on ( Energized state). Therefore, power consumption can be reduced as compared with a case where it is configured to be in an on state when not opened and in an off state when opened. The door opening switch 155a and the door opening switch 155b are turned on when the glass door frame 2, the mechanism plate, or the game frame 11 is not opened, and are turned off when opened. May be.

  FIG. 10 is a block diagram showing components related to payout, such as the payout control board 37 and the ball payout device 97. As shown in FIG. 10, a payout control microcomputer 370 including a payout control CPU 371 is mounted on the payout control board 37. In this embodiment, the payout control microcomputer 370 is a one-chip microcomputer and incorporates at least a RAM. The payout control microcomputer 370, the RAM (not shown), the ROM (not shown) storing the payout control program, the I / O port, and the like constitute the payout control means. That is, the payout control means is realized by a payout control CPU 371, a payout control microcomputer 370 having a RAM and a ROM, and an I / O port. The I / O port may be built in the payout control microcomputer 370. Note that, unlike the game control microcomputer 560, the RAM built in the payout control microcomputer 370 has not been backed up by a backup power source. Therefore, if the power supply to the gaming machine is stopped, the stored contents of the RAM built in the payout control microcomputer 370 are lost.

  The payout control microcomputer 370 performs control to pay out the game ball based on a predetermined payout condition being satisfied. Note that the predetermined payout condition is that a game ball has won a prize area (ordinary prize opening 29, 30, large prize opening, start prize opening 14) provided in the game area, or a rental ball request has been made. To establish. In addition, for example, when applied to a gaming machine such as a parrot machine or a slot machine, the predetermined payout condition is also satisfied when a game ball or medal return request is made. Further, for example, when applied to a gaming machine such as a parrot machine or a slot machine, the predetermined payout condition is also established when the symbol stop symbol becomes a predetermined winning symbol.

  Detection signals from the ball break switch 187, the full switch 48, and the payout count switch 301 are input to the I / O port 372 f of the payout control board 37 via the relay board 72. In this embodiment, the detection signal from the payout number count switch 301 is input to the payout control microcomputer 370 and then output to the main board 31 via the I / O port 372a and the output circuit 373B. .

  The detection signal from the payout motor position sensor 295 is input to the I / O port 372e of the payout control board 37 via the relay board 72. The payout motor position sensor 295 is a sensor composed of a light emitting element (LED) and a light receiving element for detecting the rotational position of the payout motor 289, and is used for detecting that the game ball is clogged, that is, so-called ball biting. . In the payout control microcomputer 370 mounted on the payout control board 37, the detection signal from the ball break switch 187 indicates that the ball is out of ball, or the detection signal from the full tank switch 48 indicates that the ball is full. Then, the ball payout process is stopped.

  Further, when the detection signal from the full tank switch 48 indicates a full state, the payout control microcomputer 370 has a low level with respect to the launch board 90 in order to stop the ball launch from the hitting ball launcher. A full tank signal is output. A launch motor signal output from the AND circuit 91 of the launch board 90 to the launch motor 94 is transmitted from the launch board 90 to the launch motor 94. A full tank signal from the payout control microcomputer 370 is input to one of the input sides of the AND circuit 91 mounted on the launch board 90, and a drive signal from the drive signal generation circuit 92 (for driving the launch motor 94). Is a signal that plays a role of supplying power from the power supply board 910.) is input to the other input side of the AND circuit 91. Then, the firing motor signal of the AND circuit 91 is input to the firing motor 94. That is, while the payout control microcomputer 370 is outputting the full tank signal, the output of the firing motor signal to the firing motor 94 is stopped. Even when the payout control microcomputer 370 is outputting a full tank signal, the output of the launch motor signal to the launch motor 94 is not stopped, and the ball launch from the hitting ball launcher is not stopped. May be.

  The payout control microcomputer 370 incorporates a serial communication circuit 380 for inputting / outputting (transmitting / receiving) signals with the game control microcomputer 560 through serial communication. In this embodiment, the game control microcomputer 560 and the payout control microcomputer 370 are connected between the game control microcomputer 560 and the payout control microcomputer 370 via serial communication circuits 505 and 380. In order to confirm, payout control commands (connection confirmation command, connection OK command) are exchanged (transmitted / received) at regular intervals (for example, 1 second). For example, the game control microcomputer 560 transmits a connection confirmation command for performing connection confirmation at regular intervals via the serial communication circuit 505, and the payout control microcomputer 370 receives the game control microcomputer 560 from the game control microcomputer 560. When the connection confirmation command is received, a connection OK command notifying that is transmitted to the game control microcomputer 560. Also, for example, when a winning occurs, the game control microcomputer 560 sets data indicating the number of winning balls to be paid out in the lower 4 bits of the winning ball number command, and the number of winning balls set in the setting. The command is transmitted to the payout control microcomputer 370. Then, the payout control microcomputer 370 transmits a prize ball number reception command indicating that the prize ball number has been received to the game control microcomputer 560. Furthermore, when the payout control microcomputer 370 finishes the prize ball payout operation, it transmits a prize ball end command indicating the completion of the prize ball to the game control microcomputer 560. The payout control microcomputer 370 transmits a prize ball preparing command to the game control microcomputer 560 at regular intervals until the prize ball payout operation is completed. In addition, when a predetermined error (an error such as ball lending, full tank, or out of ball) has occurred, the lower 4 bits of the connection OK command or the winning ball preparation command should be made different from the data indicating the error content. The connection OK command and the winning ball preparation command in which the setting is made are transmitted to the game control microcomputer 560. Note that specific signal exchange by serial communication between the game control microcomputer 560 and the payout control microcomputer 370 will be described in detail with reference to FIGS.

  Also, the payout control microcomputer 370 outputs an error signal to the error display LED 374 using a 7-segment LED via the output port 372c. A detection signal from an error release switch 375 for releasing the error state is input to the input port 372f of the payout control board 37. The error cancel switch 375 is used to cancel the error state by software reset.

  Further, a drive signal from the payout control microcomputer 370 to the payout motor 289 is transmitted to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the output port 372a and the relay board 72. A driver circuit (motor drive circuit) is provided outside the output port 372a, but is not shown in FIG.

  A card unit control microcomputer is mounted on the card unit 50 installed adjacent to the gaming machine. In addition, the card unit 50 is provided with a usable display lamp, a connecting table direction indicator, a card insertion display lamp, and a card insertion slot. A frequency display LED 60, a ball lending LED 61, a ball lending switch 62, and a return switch 63 provided in the vicinity of the hitting ball supply tray 3 are connected to the interface board (relay board) 66.

  A card lending switch signal indicating that the ball lending switch 62 has been operated and a return switch signal indicating that the return switch 63 has been operated are given to the card unit 50 from the interface board 66 in accordance with the player's operation. . Further, a card balance display signal indicating a prepaid card balance and a ball lending display signal are given from the card unit 50 to the interface board 66. Between the card unit 50 and the payout control board 37, a connection signal (VL signal), a unit operation signal (BRDY signal), a ball lending request signal (BRQ signal), a ball lending completion signal (EXS signal) and a pachinko machine operation signal ( PRDY signal) is transmitted / received via the input port 372f and the output port 372d. An interface board 66 is interposed between the card unit 50 and the payout control board 37. Therefore, a signal such as a connection signal (VL signal) is transmitted and received between the card unit 50 and the payout control board 37 via the interface board 66 as shown in FIG.

  When the power of the pachinko gaming machine 1 is turned on, the payout control microcomputer 370 mounted on the payout control board 37 outputs a PRDY signal to the card unit 50. The card unit control microcomputer outputs a VL signal when the power is turned on. The payout control microcomputer 370 determines the connected / unconnected state of the card unit 50 according to the input state of the VL signal. When a card is received in the card unit 50, the ball lending switch is operated and a ball lending switch signal is input, the card unit control microcomputer outputs a BRDY signal to the payout control board 37. When a predetermined delay time elapses from this point, the card unit control microcomputer outputs a BRQ signal to the payout control board 37.

  Then, the payout control microcomputer 370 raises the EXS signal to the card unit 50 and, when detecting the fall of the BRQ signal from the card unit 50, drives the payout motor 289 to give a predetermined number of rental balls to the player. Pay out. When the payout is completed, the payout control microcomputer 370 causes the EXS signal to the card unit 50 to fall. Thereafter, on the condition that the BRDY signal from the card unit 50 is not in the ON state, the winning ball payout control is executed when a payout command signal is received from the game control means.

  The power supply voltage AC24V used in the card unit 50 is supplied from the payout control board 37. That is, power supply from the power supply board 910 to the card unit 50 is performed via the payout control board 37 and the interface board 66. In this example, a fuse for protecting the card unit 50 is provided in a 24 V AC power supply line for the card unit 50 arranged in the interface board 66, and a voltage higher than a predetermined voltage is supplied to the card unit 50. It is prevented.

  Further, in this embodiment, the case where the card unit 50 is installed adjacent to the gaming machine as a separate body from the gaming machine is taken as an example, but the card unit 50 may be integrated with the gaming machine. . Further, the present invention can be applied even in the case where game balls corresponding to the amount of money are lent out in accordance with coin insertion.

  FIG. 11 is a block diagram illustrating a circuit configuration example of the relay board 77, the effect control board 80, the lamp driver board 35, and the audio output board 70. In the example shown in FIG. 11, the lamp driver board 35 and the audio output board 70 are not equipped with a microcomputer, but may be equipped with a microcomputer. Further, without providing the lamp driver board 35 and the audio output board 70, only the effect control board 80 may be provided for effect control.

  The effect control board 80 includes an effect control microcomputer 101 including an effect control CPU 101a and a RAM for storing information related to effects such as effect symbol process flags. The RAM may be externally attached. In this embodiment, the RAM in the production control microcomputer 100 is not backed up. In the effect control board 80, the effect control CPU 101a operates according to a program stored in a built-in or external ROM (not shown). The effect control microcomputer 100 has a built-in serial communication circuit 101b that inputs / outputs (transmits / receives) signals with the game control microcomputer 560 through serial communication. In addition, the effect control CPU 101a causes the VDP (video display processor) 109 to perform display control of the effect display device 9 based on the effect control command.

  In this embodiment, a VDP 109 that performs display control of the effect display device 9 in cooperation with the effect control microcomputer 100 is mounted on the effect control board 80. The VDP 109 has an address space independent of the production control microcomputer 100, and maps a VRAM therein. VRAM is a buffer memory for developing image data. Then, the VDP 109 outputs the image data in the VRAM to the effect display device 9 via the frame memory.

  The effect control CPU 101a outputs to the VDP 109 a command for reading out necessary data from a CGROM (not shown) in accordance with the received effect control command. The CGROM stores character image data and moving image data displayed on the effect display device 9, specifically, a person, characters, figures, symbols (including effect symbols), and background image data in advance. ROM. The VDP 109 reads the image data from the CGROM in response to the instruction from the effect control CPU 101a. The VDP 109 executes display control based on the read image data.

  Further, the effect control CPU 101 a outputs a signal for driving the LED to the lamp driver board 35 via the output port 105. In addition, the production control CPU 101 a outputs sound number data to the audio output board 70 via the output port 104.

  In the lamp driver board 35, a signal for driving the LED is input to the LED driver 352 via the input driver 351. The LED driver 352 supplies a current to a light emitter provided on the frame side such as the frame LED 28 based on a signal for driving the LED. Further, an electric current is supplied to the decoration LED 25 provided on the game board side.

  In the voice output board 70, the sound number data is input to the voice synthesis IC 753 via the input driver 752. The voice synthesizing IC 753 generates voice and sound effects corresponding to the sound number data and outputs them to the amplifier circuit 755. The amplifier circuit 755 outputs an audio signal obtained by amplifying the output level of the voice synthesis IC 753 to a level corresponding to the volume set by the volume 756 to the speaker 27. The voice data ROM 754 stores control data corresponding to the sound number data. The control data corresponding to the sound number data is a collection of data showing the output form of the sound effect or sound in a time series in a predetermined period (for example, the changing period of the effect design).

  FIG. 12 is a block diagram showing a circuit configuration of the main board 31 and signal lines of an effect control command transmitted from the main board 31 to the effect control board 80. As shown in FIG. 12, in this embodiment, the game control microcomputer 560 mounted on the main board 31 uses a single signal line for effect control signal transmission to produce an effect control command (effect control signal). Is transmitted to the effect control board 80.

  As shown in FIG. 12, wiring from the start port switch 14a and the winning confirmation switch 14b is connected to the main board 31. The main board 31 is also connected with wiring from the special variable winning ball apparatus 20 which is a big winning opening, and various switches 29a and 30a for detecting the winning of game balls to other winning openings. . Further, the main board 31 is connected to a solenoid 16 that opens and closes the variable winning ball device 15 and wirings to the solenoid 21 that opens and closes the special variable winning ball device 20.

  The main board 31 includes a game control microcomputer 560, an input driver circuit 58, and an output circuit 59. The game control microcomputer 560 operates in accordance with a clock circuit 501, a reset controller 502 that functions as a system reset means, a random number circuit 503a, 503b, a ROM 54 that stores a game control program, a RAM 55 that is used as a work memory, and a program. CPU 56, CTC 504 for sending an interrupt request signal (interrupt request signal by timer interrupt) to CPU 56, serial communication circuit 505 for performing asynchronous serial communication with the microcomputer provided in payout control board 37 and effect control board 80, pachinko game For each product of the machine 1 or for each product (each chip) of the game control microcomputer 560, a chip individual number record for storing a chip individual number or the like included in game machine specific information given in advance individually is stored. A built-in static 506 and I / O ports unit 57.

  In this embodiment, the microcomputer on a board (for example, the payout control board 37 or the effect control board 80) different from the board (for example, the main board 31) on which the microcomputer incorporating the serial communication circuit 505 is mounted. Although the case where the serial communication circuit 505 is used for communication will be described, the serial communication circuit 505 may perform serial communication with another microcomputer included in the board on which the microcomputer incorporating the serial communication circuit 505 is mounted. For example, when two microcomputers having the same configuration are mounted on the same substrate, serial communication circuits built in the microcomputers may perform serial communication with each other.

  The clock circuit 501 outputs a reference clock signal CLK having a predetermined cycle generated by dividing the system clock signal by 27 (= 128) to the random number circuits 503a and 503b. When a low level signal is input for a predetermined period, the reset controller 502 outputs a predetermined initialization signal to the CPU 56 and the random number circuits 503a and 503b to reset the game control microcomputer 560.

  Further, in this embodiment, as shown in FIG. 12, the game control microcomputer 560 is equipped with two random number circuits 503a and 503b having different ranges of random value values that can be generated. The random number circuit 503a is a random number circuit (hereinafter also referred to as a 12-bit random number circuit) that generates a 12-bit pseudo-random number. The 12-bit random number circuit 503a has a function of generating a random number having a value within a range that can be generated by 12 bits (that is, a range from 0 to 4095). The random number circuit 503b is a random number circuit (hereinafter also referred to as a 16-bit random number circuit) that generates a 16-bit pseudo-random number. The 16-bit random number circuit 503b has a function of generating a random number having a value in a range that can be generated in 16 bits (that is, a range from 0 to 65535). In this embodiment, the case where the game control microcomputer 560 includes two random number circuits is described. However, the game control microcomputer 560 may include three or more random number circuits. In this embodiment, when the 12-bit random number circuit 503a and the 16-bit random number circuit 503b are comprehensively expressed, or when indicating either the 12-bit random number circuit 503a or the 16-bit random number circuit 503b, This is called a random number circuit 503.

  FIG. 13 is an explanatory diagram showing a configuration example of the gaming machine specific information used in this embodiment. In this embodiment, in addition to the chip individual number stored in the chip individual number register 506, for example, a manufacturer code assigned in advance for each manufacturer of the pachinko gaming machine 1 and each type of the pachinko gaming machine 1 The model name code assigned in advance is used by being included in the gaming machine specific information. The manufacturer code is ASCII data having a data length (number of bytes) of 3 bytes, and is stored in a program management area of the ROM 54, for example. The chip individual number is hexadecimal data having a data length (number of bytes) of 4 bytes, and is stored in the chip individual number register 506. The model name code is ASCII data having a data length (number of bytes) of 32 bytes, and is stored in the program data area of the ROM 54, for example. When the model name is indicated by data of 32 bytes or less, for example, “20H” of hexadecimal data (subscript H indicates that it is a hexadecimal number) is added to the end by the number of missing bytes. The entire code may be adjusted so that the data length is 32 bytes.

  The chip individual number only needs to be stored in the chip individual number register 506 and then not erased unless the chip individual number register 506 is physically destroyed. The chip individual number register 506 may be a dedicated circuit built in the game control microcomputer 560 as a separate configuration from the ROM 54. Alternatively, the chip individual number may be stored in a predetermined area of the ROM 54 to function as the chip individual number register 506. Even when the chip individual number is stored in the ROM 54, it is not erased once stored.

  In this embodiment, the game machine specific information read from the ROM 54, the chip individual number register 506, etc. by the CPU 56 of the game control microcomputer 560 is set to a predetermined bit at the output port of the game control microcomputer 560 bit by bit. To do. That is, the CPU 56 causes the game machine specific information to be output from the output port of the game control microcomputer 560 by software in a serial signal system. Note that the CPU 56 is not limited to outputting the game machine specific information from the output port of the game control microcomputer 560 in a serial signal system by software. As an example, by using a serial output circuit (for example, a shift register) as hardware built in the game control microcomputer 560, the game machine specific information read as parallel data is converted into serial data, and the terminal board 160 May be transmitted. In this case, the CPU 56 of the game control microcomputer 560 uses the manufacturer code stored in the program management area of the ROM 54, the chip individual number stored in the chip individual number register 506, and the model stored in the program data area of the ROM 54. The name code is sequentially read as parallel data in units of a predetermined number of bytes (for example, 1 byte), and the read data is supplied to the serial output circuit. The serial output circuit converts the supplied read data of the gaming machine specific information from parallel data to serial data in units of a predetermined number of bytes (for example, 1 byte) and sequentially outputs the converted data.

  Note that the serial output circuit for converting the gaming machine specific information into serial data is not limited to the one built in the gaming control microcomputer 560, and is externally attached to the gaming control microcomputer 560 on the main board 31. It may be a thing. Alternatively, at the output port of the gaming control microcomputer 560, a plurality of bits for outputting gaming machine specific information as parallel data in units of a predetermined number of bytes (for example, 1 byte) are allocated, and between the main board 31 and the terminal board 160, The gaming machine specific information may be transmitted as parallel data. In this case, for example, a serial output circuit may be provided on the terminal board 160 so that the gaming machine specific information can be converted from parallel data to serial data and then output to an external device. Alternatively, the gaming machine specific information may be output as parallel data to an external device without providing a serial output circuit on the terminal board 160.

  Here, one serial output circuit for converting the parallel data into the serial data in a predetermined order may be provided for the entire manufacturer code, chip individual number, and model name code included in the gaming machine specific information. A plurality of serial output circuits for individually converting the code, the chip individual number, and the model name code from parallel data to serial data may be provided. In this case, output data from each serial output circuit may be combined sequentially, and the game machine specific information may be output as a serial signal from a single bit in the output port of the game control microcomputer 560, or each serial output Output data from the circuit as individual serial signals, and the manufacturer code, chip individual number, and model name code included in the gaming machine specific information are converted into serial signals from a plurality of bits at the output port of the gaming control microcomputer 560. You may make it output separately.

  The game machine specific information is a hardware using any one of a wiring pattern on the board of the main board 31 or the terminal board 160, wiring connection outside the board, wiring in a predetermined IC chip, or a bus configuration. The data may be output to a plurality of external devices after being branched into a plurality according to the hardware configuration. The gaming machine specific information read in units of a predetermined number of bytes (for example, 1 byte) is supplied to the serial output circuit and output in a serial signal system in units of a predetermined number of bytes (for example, 1 byte). Using a configuration including a part or all of the control microcomputer 560, which is built in or externally attached and output after the gaming machine specific information is branched into a plurality of hardware configurations, The machine specific information may be output to an external device.

  The game machine specific information may be information including all of the manufacturer code, the chip individual number, and the model name code, or at least each product (each chip) of the game control microcomputer 560 such as the chip individual number. May include information including different ID numbers. A product management number (identification number) assigned in advance to each product of the pachinko gaming machine 1 together with a chip individual number that is different for each product (each chip) of the game control microcomputer 560 or instead of the chip individual number ) Etc. may be used as gaming machine specific information.

  Next, the configuration of the serial communication circuit 505 will be described. The serial communication circuit 505 is a data format using a full duplex method, an asynchronous method, and standard NRZ (non-return zero) encoding, Perform serial communication. The serial communication circuit 505 includes a transmission unit that transmits various data (for example, a prize ball number command and an effect control command) to the microcomputer of each control board, and various data (for example, a prize ball ACK) from the microcomputer of each control board. Command).

  FIG. 14 is a block diagram illustrating a configuration example of the transmission unit of the serial communication circuit 505. FIG. 15 is a block diagram illustrating a configuration example of the receiving unit of the serial communication circuit 505. The serial communication circuit 505 includes a baud rate register 702, a baud rate generation circuit 703, two status registers 705 and 706, three control registers 707, 708, and 709, a transmission data register 710, a reception data register 711, a transmission shift register 712, and a reception. Shift register 713, interrupt control circuit 714, transmission format / parity generation circuit 715, and reception format / parity check circuit 716. As shown in FIG. 14, the transmission unit of the serial communication circuit 505 includes a baud rate register 702, a baud rate generation circuit 703, a status register A 705, control registers 707, 708, and 709, and a transmission data register 710. , A transmission shift register 712, an interrupt control circuit 714, and a transmission format / parity generation circuit 715. As shown in FIG. 15, the receiving unit of the serial communication circuit 505 includes a baud rate register 702, a baud rate generation circuit 703, status registers 705 and 706, control registers 707, 708, and 709, received data, among these components. The register 711, the reception shift register 713, the interrupt control circuit 714, and the reception format / parity check circuit 716 are configured.

  In the serial communication circuit 505, the transmission unit and the reception unit are actually configured using a common circuit. As described above, the serial communication circuit 505 functions as a transmission circuit or a reception circuit by properly using each component of the serial communication circuit 505.

  First, the data format of data transmitted and received by the serial communication circuit 505 with the microcomputer mounted on each control board will be described. FIG. 16 is an explanatory diagram illustrating an example of a data format of data transmitted and received by the serial communication circuit 505 with a microcomputer mounted on each control board. As shown in FIG. 16, the data format of data transmitted and received by the serial communication circuit 505 is configured with a start bit, data, and stop bits as one frame. Further, the data length of data transmitted / received by the serial communication circuit 505 can be set to either 8 bits or 9 bits by performing an initial setting in a serial communication circuit setting process described later. FIG. 16A shows an example of a data format when the data length is set to 8 bits. FIG. 16B shows an example of a data format when the data length is set to 9 bits.

  As shown in FIG. 16, the data format of data transmitted and received by the serial communication circuit 505 is a start bit (logic “0”) indicating the start of one frame after an idle line of high level (logic “1”). ")including. The data format includes 8-bit or 9-bit transmission / reception data after the start bit. The data format includes a stop bit (logic “1”) indicating the end of one frame after transmission / reception data.

  The serial communication circuit 505 transmits / receives data first from the least significant bit (bit 0) of the transmission / reception data according to the data format shown in FIG. Further, if initial setting is performed in a serial communication circuit setting process described later, it is possible to set so that a parity bit is added to transmission / reception data. When a setting is made to add a parity bit, the most significant bit of the transmission / reception data is used as a parity bit (odd parity or even parity). For example, when the data length is set to 8 bits, bit 7 of transmission / reception data is used as a parity bit. For example, when the data length is set to 9 bits, bit 8 of transmission / reception data is used as a parity bit.

  The baud rate generation circuit 703 generates a baud rate used by the serial communication circuit 505 based on a clock signal output from the clock circuit 501 and a setting value (also referred to as a baud rate setting value) set in the baud rate register 702. In this case, the baud rate generation circuit 703 obtains the baud rate using a predetermined calculation formula based on the clock signal and the baud rate setting value. For example, the baud rate generation circuit 703 obtains the baud rate used by the serial communication circuit 505 using equation (1).

Baud rate = clock frequency / (baud rate set value x 16) Equation (1)

  FIG. 17 is an explanatory diagram showing an example of the baud rate register 702. The baud rate register 702 is a register that sets a predetermined setting value for designating a baud rate value generated by the baud rate generation circuit 703. For example, it is assumed that the baud rate register 702 obtains the baud rate using the equation (1) and the clock frequency is 3 MHz. In this case, if the desired target baud rate is 1200 bps, the setting value “156” is set in the baud rate register 702. Then, the baud rate generation circuit 703 generates the baud rate “1201.92 bps” using the equation (1) based on the clock frequency “3 MHz” and the baud rate set value “156”. The baud rate register 702 is a 16-bit register, and an initial value is set to “0 (= 00h)”. The baud rate register 702 is configured such that bits 0 to 12 can be written and read. Further, the baud rate register 702 is configured such that bits 13 to 15 cannot be written or read. Therefore, even if a control for writing a value to bits 13 to 15 of the baud rate register 702 is performed, it is invalid, and all the values read from the bits 13 to 15 are “0 (= 000b)”.

  FIG. 18A is an explanatory diagram illustrating an example of the control register A707. The control register A 707 is a register for setting the communication format of the serial communication circuit 505. In this embodiment, the communication format of the serial communication circuit 505 is set by setting the value of each bit of the control register A707. In the control register A707, communication format setting data for setting a communication format such as a data format of transmission / reception data and various communication methods is set. As shown in FIG. 18A, the control register A707 is an 8-bit register, and the initial value is set to “0 (= 00h)”. Control register A 707 is configured such that bits 0 to 4 can be written and read. Control register A 707 is configured such that bits 5 to 7 cannot be written or read. Therefore, even if control is performed to write a value to bits 5 to 7 of the control register A707, it is invalid, and all the values read from bits 5 to 7 are “0 (= 000b)”.

  FIG. 18B is an explanatory diagram of an example of communication format setting data set in the control register A707. As shown in FIG. 18B, setting data for setting the data length of data to be transmitted and received is set in bit 4 (bit name “M”) of the control register A707. As shown in FIG. 18B, by setting bit 4 to “0”, the data length of the transmission / reception data is set to 8 bits. Further, by setting bit 4 to “1”, the data length of the transmission / reception data is set to 9 bits.

  In bit 3 (bit name “WAKE”) of the control register A707, setting data for setting a wake-up method for waking up the receiver circuit (the receiving unit of the serial communication circuit 505) in the standby state. Is set. As shown in FIG. 18 (B), by setting bit 3 to “0”, an idle line wakeup method for wakeup when an idle line is recognized is set. In addition, by setting bit 3 to “1”, an address mark wakeup method for wakeup by recognizing a predetermined address mark is set.

  In bit 2 (bit name “ILT”) of the control register A707, setting data for selecting an idle line detection method of received data is set. As shown in FIG. 18B, by setting bit 2 to “0”, a detection method for detecting an idle line after the start bit included in the received data is set. In addition, by setting bit 2 to “1”, a detection method for detecting an idle line after a stop bit included in received data is set.

  Setting data for setting whether to use the parity function is set in bit 1 (bit name “PE”) of the control register A707. As shown in FIG. 18B, the parity function is not used by setting bit 1 to “0”. Further, by setting bit 1 to “1”, the parity function is set to be used.

  Setting data for setting the type of parity when the parity function is used is set in bit 0 (bit name “PT”) of the control register A707. As shown in FIG. 18B, even parity is set as the parity type by setting bit 0 to “0”. Also, by setting bit 0 to “1”, odd parity is set as the parity type.

  FIG. 19A is an explanatory diagram illustrating an example of the control register B708. The control register B 708 is a register for setting whether to permit an interrupt request from the serial communication circuit 505. In this embodiment, whether the interrupt request from the serial communication circuit 505 is permitted or prohibited is set by setting the value of each bit of the control register B708. In the control register B708, interrupt request setting data indicating whether or not various interrupt requests are permitted is mainly set. In addition to the interrupt request setting data, setting data for performing various settings of the serial communication circuit 505 is also set in the control register B708. As shown in FIG. 19A, the control register B 708 is an 8-bit register, and the initial value is set to “0 (= 00h)”. Control register B 708 is configured such that bits 0 to 7 can be written and read.

  FIG. 19B is an explanatory diagram showing an example of interrupt request setting data set in the control register B708. As shown in FIG. 19B, setting data indicating whether or not a transmission interrupt request, which is an interrupt request to be performed at the time of data transmission, is permitted is set in bit 7 (bit name “TIE”) of the control register B708. Is done. As shown in FIG. 19B, by setting bit 7 to “0”, the transmission interrupt request is set to be prohibited. Also, by setting bit 7 to “1”, the transmission interrupt request is set to be permitted.

  Bit 6 (bit name “TCIE”) of the control register B708 is set with setting data indicating whether or not to permit a transmission completion interrupt request, which is an interrupt request to be made when data transmission is completed. As shown in FIG. 19B, by setting bit 6 to “0”, the transmission completion interrupt request is set to be prohibited. Also, by setting bit 6 to “1”, the transmission completion interrupt request is set to be permitted.

  Bit 5 (bit name “RIE”) of the control register B 708 is set with setting data indicating whether or not a reception interrupt request, which is an interrupt request performed when data is received, is permitted. As shown in FIG. 19B, by setting bit 5 to “0”, the reception interrupt request is set to be prohibited. Further, by setting bit 5 to “1”, the reception interrupt request is set to be permitted.

  Bit 4 (bit name “ILIE”) of the control register B708 is set with setting data indicating whether or not an idle line interrupt request that is an interrupt request to be performed when an idle line of received data is detected is permitted. As shown in FIG. 19B, by setting bit 4 to “0”, an idle line interrupt request is set to be prohibited. Further, by setting bit 4 to “1”, it is set to permit an idle line interrupt request.

  In bit 3 (bit name “TE”) of the control register B708, setting data indicating whether to use the transmission circuit (the transmission unit of the serial communication circuit 505) is set. As shown in FIG. 19B, by setting bit 3 to “0”, the transmission circuit is set not to be used. Further, by setting bit 3 to “1”, the transmission circuit is set to be used. In this embodiment, setting to use the transmission circuit is performed by setting bit 3 to “1”. Such setting is performed in the initial setting (for example, step S15a) of the game control main process.

  In bit 2 (bit name “RE”) of the control register B708, setting data indicating whether or not to use the receiving circuit is set. As shown in FIG. 19B, by setting bit 2 to “0”, the receiving circuit is set not to be used. Further, by setting bit 2 to “1”, the receiving circuit is set to be used. In this embodiment, setting to use the receiving circuit is performed by setting bit 2 to “1”. Such setting is performed in the initial setting (for example, step S15a) of the game control main process.

  Setting data indicating whether or not to use the wakeup function of the receiving circuit is set in bit 1 (bit name “RWU”) of the control register B708. As shown in FIG. 19B, by setting bit 1 to “0”, the wakeup function is set not to be used. Further, by setting bit 1 to “1”, the wakeup function is set to be used.

  Setting data indicating whether or not to use a predetermined break code transmission function is set in bit 0 (bit name “SBK”) of the control register B708. As shown in FIG. 19B, by setting bit 1 to “0”, the break code transmission function is set not to be used. Further, by setting bit 1 to “1”, the break code transmission function is set to be used. When bit 1 is set to “1”, the serial communication circuit 505 causes the microcomputer on which the control board (the payout control board 37 and the effect control board 80) is mounted with a break code (for example, a signal including “0” continuously). Send to.

  FIG. 20A is an explanatory diagram illustrating an example of the status register A705. The status register A 705 is a register for confirming various statuses of the serial communication circuit 505. In this embodiment, the CPU 56 can confirm various statuses of the serial communication circuit 505 by confirming the value of each bit of the status register A 705. As shown in FIG. 20A, the status register A705 is an 8-bit register, and the initial value is set to “0 (= 00h)”. In addition, the status register A705 is configured so that bits 0 to 7 can only be read. Therefore, even if control is performed to write a value to bit 0 to bit 7 of the status register A705, it is invalidated.

  In the present embodiment, as will be described later, when transmission data is not stored in the transmission data register 710 (transmission data empty) or transmission of transmission data stored in the transmission shift register 712 is completed, interrupt control is performed. Circuit 714 sets the corresponding bit in status register A705. Then, the CPU 56 reads the value of each bit set in the status register A705.

  FIG. 20B is a diagram illustrating an example of status confirmation data stored in the status register A705. As shown in FIG. 20B, transmission data indicating that transmission data is not stored in transmission data register 710 in bit 7 (bit name “TDRE”) of status register A705 (transmission data empty). Stores an empty flag. As shown in FIG. 20B, when “0” is stored in bit 7, the transmission data is not yet transferred from the transmission data register 710 to the transmission shift register 712, and transmitted to the transmission data register 710. Indicates that the data is still stored. In addition, when “0” is stored in bit 7, data is not written to the transmission data register. For example, in steps S5211 (FIG. 45) and S52305 (FIG. 47), transmission data is set on condition that “0” is not stored in bit 7. When “1” is stored in bit 7, the transmission data is transferred from the transmission data register 710 to the transmission shift register 712, and there is no transmission data in the transmission data register 710 (transmission data empty). ).

  Bit 6 (bit name “TC”) of the status register A 705 stores a transmission completion flag indicating that transmission of transmission data from the serial communication circuit 505 has been completed. As shown in FIG. 20B, when “0” is stored in bit 6, the transmission data stored in the transmission shift register 712 is being transmitted, and the transmission data from the serial communication circuit 505 is not transmitted. Indicates that transmission has not been completed. Further, when “1” is stored in bit 6, the transmission data stored in the transmission shift register 712 has been transferred, and transmission of transmission data from the serial communication circuit 505 has been completed. It shows that. When the command storage area is in the ring buffer format, if “1” is stored in bit 6, the command read pointer is updated.

  Note that the transmission of the transmission data is completed, and the game control microcomputer 560 waits for a reception confirmation signal from the transmission destination microcomputer. In this embodiment, when a transmission interrupt is set as will be described later, the serial communication circuit 505 sets the bit 6 of the status register A 705 to “1” and confirms reception when detecting the completion of transmission of transmission data. An interrupt request (referred to as an interrupt request during transmission) is made to the CPU 56 as a signal waiting state.

  Bit 5 (bit name “RDRF”) of status register A 705 stores a reception data full flag indicating that reception data is stored in reception data register 711 (reception data full). As shown in FIG. 20B, when “0” is stored in bit 5, it indicates that the reception data register 711 contains no reception data. When “1” is stored in bit 5, the value of the reception shift register 713 is transferred to the reception data register 711, and reception data is stored in the reception data register 711 (reception data Full). Whether or not the command from the payout control microcomputer 370 has been received is confirmed by whether or not “1” is stored in bit 5. For example, in steps S5221 (FIG. 46), S52401 (FIG. 48), and S52501 (FIG. 49), it is determined that the command is received on condition that “0” is not stored in bit 5. In this embodiment, bit 5 (RDRF) of status register A 705 is cleared when reception data is read from reception data register 711 by game control microcomputer 560. If the bit 5 (RDRF) of the status register A 705 is not automatically cleared when the received data is read, the game control microcomputer 560 reads the received data from the received data register 711. Every time reception data is read, it is necessary to perform processing for clearing bit 5 (RDRF) of the status register A705.

  When the reception data is stored in the reception data register 711, the CPU 56 is ready to perform reception processing by reading the reception data from the reception data register 711. In this embodiment, when the reception interrupt is set, the serial communication circuit 505 sets the bit 5 of the status register A 705 to “1” when reception data full is detected, and enables reception processing. As an example, an interrupt request is made to the CPU 56 (referred to as an interrupt request upon reception).

  Bit 4 (bit name “IDLE”) of status register A705 stores an idle line detection flag indicating that the receiving circuit has detected an idle line. As shown in FIG. 20B, when “0” is stored in bit 4, it indicates that the receiving unit of the serial communication circuit 505 has not detected an idle line. When “1” is stored in bit 4, it indicates that the receiving unit of the serial communication circuit 505 has detected an idle line.

  In bit 3 (bit name “OR”) of the status register A 705, the reception shift register 713 has received the next data before the CPU 56 reads the reception data stored in the reception data register 711 (overload). An overrun flag indicating (run) is stored. As shown in FIG. 20B, when “0” is stored in bit 3, it indicates that the receiving circuit has not detected an overrun. If “1” is stored in bit 3, it indicates that the receiving circuit has detected an overrun.

  If an overrun occurs, the next received data is stored in the receiving shift register 713 before the received data in the received data register 711 is read, so that the received data is overwritten and the CPU 56 receives the received data. It cannot be read correctly. For this reason, communication with the microcomputer mounted on each control board cannot be performed correctly, causing the CPU 56 to malfunction. In this embodiment, when detecting an overrun, the serial communication circuit 505 sets bit 3 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 as an error has occurred during communication.

  Bit 2 (bit name “NF”) of status register A 705 stores a noise error flag indicating that noise has been detected in the received data. As shown in FIG. 20B, when “0” is stored in bit 2, it indicates that the receiving circuit is not detecting noise in the received data. Further, when “1” is stored in bit 2, it indicates that the receiving circuit has detected noise in the received data.

  For example, when detecting each bit of the received data, the serial communication circuit 505 detects “1” or “0” having a predetermined bit length using the baud rate generated by the baud rate generation circuit 703. In this case, when the detected length of “1” or “0” is less than the predetermined bit length, the serial communication circuit 505 detects a noise error as noise generated in the received data. When a noise error occurs, there is a high possibility that correct received data cannot be received due to the noise, which causes the CPU 56 to malfunction. In this embodiment, when detecting a noise error, the serial communication circuit 505 sets bit 2 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 as an error has occurred during communication.

  Bit 1 (bit name “FE”) of the status register A 705 indicates that it is detected that the position of the stop bit of the received data is “0” (originally, the stop bit is “1”) (framing error). A framing error flag is stored. As shown in FIG. 20B, when “0” is stored in bit 1, it indicates that the receiving circuit has not detected a framing error in the received data. When “1” is stored in bit 1, it indicates that the receiving circuit has detected a framing error.

  When a framing error occurs, it is in a state where the stop bit of the received data has not been correctly received, and therefore there is a high possibility that correct received data cannot be received, causing the CPU 56 to malfunction. In this embodiment, when detecting a framing error, the serial communication circuit 505 sets bit 1 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 as an error has occurred during communication.

  Bit 0 (bit name “PF”) of the status register A 705 has a parity error flag indicating that the parity value obtained from the received data does not match the parity value included in the received data (parity error). Is stored. As shown in FIG. 20B, when “0” is stored in bit 0, this indicates that the receiving circuit has not detected a parity error in the received data. Further, when “1” is stored in bit 0, it indicates that the receiving circuit has detected a parity error.

  When a parity error occurs, it is in a state where each data bit or parity bit of the received data has not been correctly received, so there is a high possibility that correct received data cannot be received, causing the CPU 56 to malfunction. In this embodiment, when the serial communication circuit 505 detects a parity error, the serial communication circuit 505 sets bit 0 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 on the assumption that an error has occurred during communication.

  FIG. 21A is an explanatory diagram illustrating an example of the status register B706. The status register B 706 is a register for confirming the reception state (reception status) of the serial communication circuit 505. In this embodiment, the CPU 56 can confirm the reception status of the serial communication circuit 505 by confirming the value of the bit of the status register B 706. As shown in FIG. 21B, the status register B 706 is an 8-bit register, and the initial value is set to “0 (= 00h)”. Further, the status register B 706 is configured so that bit 0 can only be read. Therefore, even if control is performed to write a value to bit 0 of status register A 705, it is invalid. Status register B 706 is configured such that bits 1 to 7 cannot be written or read. Therefore, even if control is performed to write a value to bits 1 to 7 of the status register A 705, the value is invalid and all the values read from bits 1 to 7 are “0 (= 0000b)”.

  FIG. 21B is a diagram showing an example of status confirmation data stored in the status register B706. As shown in FIG. 21B, a reception active flag indicating that the reception circuit is receiving reception data (reception active) is stored in bit 0 (bit name “RAF”) of the status register B706. . As shown in FIG. 21B, when “0” is stored in bit 0, it indicates that the reception circuit is not receiving reception data. Further, when “1” is stored in bit 0, it indicates that the reception circuit is receiving reception data. Even when “1” is stored in bit 0, command data is not written or command data cannot be written. When the serial communication circuit 505 detects the start bit, it assumes that reception of received data has started, and sets bit 0 of the status register B 706 to “1”.

  FIG. 22A is an explanatory diagram illustrating an example of the control register C709. The control register C709 is a register for setting whether to permit an interrupt request when a communication error occurs in the serial communication circuit 505. In this embodiment, by setting the value of each bit of the control register C709, it is set whether to permit or prohibit an interrupt request during communication from the serial communication circuit 505. In the control register C709, error interrupt request setting data indicating whether or not various interrupt requests at the time of a communication error are permitted is mainly set. In addition to the error interrupt request setting data, the control register C709 stores 9th bit data when the data length is set to 9 bits. As shown in FIG. 22A, the control register C709 is an 8-bit register, and the initial value is set to “0 (= 00h)”. Control register C709 is configured such that bits 0 to 3 and bits 6 and 7 can be written and read. Further, the control register C709 is configured such that bits 4 and 5 cannot be written or read. Therefore, even if a control for writing a value to bits 4 and 5 of the control register C709 is performed, it is invalid, and all the values read from the bits 4 and 5 are “0 (= 0000b)”.

  FIG. 22B is an explanatory diagram showing an example of error interrupt request setting data set in the control register C709. As shown in FIG. 22B, the bit 7 (bit name “R8”) of the control register C709 stores the 9th bit of the received data when the data length is set to 9 bits. Further, bit 6 (bit name “T8”) of the control register C709 stores the 9th bit data of the transmission data when the data length is set to 9 bits.

  In bit 3 (bit name “ORIE”) of the control register C709, setting data indicating whether or not to permit an overrun flag interrupt request, which is an interrupt request to be performed when an overrun is detected, is set. As shown in FIG. 22B, by setting bit 3 to “0”, the overrun flag interrupt request is set to be prohibited. Further, by setting bit 3 to “1”, the overrun flag interrupt request is set to be permitted.

  Bit 2 (bit name “NEIE”) of the control register C709 is set with setting data indicating whether or not to permit a noise error flag interrupt request, which is an interrupt request to be performed when a noise error is detected. As shown in FIG. 22B, by setting bit 2 to “0”, the noise error flag interrupt request is set to be prohibited. Also, by setting bit 2 to “1”, the noise error flag interrupt request is set to be permitted.

  Bit 1 (bit name “FEIE”) of the control register C709 is set with setting data indicating whether or not to permit a framing error flag interrupt request, which is an interrupt request to be performed when a framing error is detected. As shown in FIG. 22B, by setting bit 1 to “0”, the framing error flag interrupt request is set to be prohibited. Further, by setting bit 1 to “1”, the framing error flag interrupt request is set to be permitted.

  Bit 0 (bit name “PEIE”) of the control register C709 is set with setting data indicating whether or not to permit a parity error flag interrupt request which is an interrupt request to be performed when a parity error is detected. As shown in FIG. 22B, by setting bit 0 to “0”, the parity error flag interrupt request is set to be prohibited. Further, by setting bit 0 to “1”, the parity error flag interrupt request is set to be permitted.

  FIG. 23 is an explanatory diagram illustrating an example of a data register included in the serial communication circuit 505. The data register 701 is a register that stores data transmitted and received by the serial communication circuit 505. As shown in FIG. 23, the data register is an 8-bit register, and the initial value is set to “0 (= 00h)”. Data register 701 is configured such that bits 0 to 7 can be written and read.

  In this embodiment, when the serial communication circuit 505 transmits transmission data, the data register is used as the transmission data register 710. When the data length is set to 9 bits, bit 6 of the data register and control register C709 is used as the transmission data register 710. In this case, bits 0 to 7 of the data register are used as bits 0 to 7 of the transmission data register 710, and bit 6 of the control register C709 is used as bit 8 of the transmission data register 710.

  When the serial communication circuit 505 receives received data, the data register is used as the received data register 711. When the data length is set to 9 bits, bit 7 of the data register and control register C709 is used as the reception data register 711. In this case, bits 0 to 7 of the data register are used as bits 0 to 7 of the reception data register 711, and bit 7 of the control register C709 is used as bit 8 of the reception data register 711.

  The interrupt control circuit 714 makes various interrupt requests to the CPU 56. In this embodiment, when the bit 6 (TCIE) of the control register B 708 is set to “1”, the interrupt control circuit 714 notifies the CPU 56 when transmission of transmission data to the transmission data register 710 is completed. In addition to outputting an interrupt signal, an interrupt request is made by setting bit 6 (TC) of status register A705 to “1”. The interrupt control circuit 714 may output a different interrupt signal to the CPU 56 for each interrupt factor, instead of making the interrupt factor identifiable by the set value of the bit of the status register A705.

  In addition, when the bit 5 (RIE) of the control register B 708 is set to “1”, the interrupt control circuit 714 enters a state where the reception data is stored in the reception data register 711 (when reception data full is detected). ), An interrupt signal is output to the CPU 56, and an interrupt request is made by setting bit 5 (RDRF) of the status register A705 to “1”.

  Further, when any of the bits 0 to 3 of the control register C709 is set to “1”, the interrupt control circuit 714 outputs an interrupt signal to the CPU 56 and also indicates the type of communication error. In response to this, an interrupt request is made by setting "1" to bits 0 to 3 of the status register A705. For example, if bit 3 (ORIE) of the control register C709 is set to “1”, “1” is set to bit 3 (OR) of the status register A705 when an overrun is detected and an interrupt request is made. To do. For example, when bit 2 (NEIE) of the control register C709 is set to “1”, when a noise error is detected and an interrupt request is made, “1” is set to bit 2 (NF) of the status register A705. Set. For example, when bit 1 (FEIE) of the control register C709 is set to “1”, when a framing error is detected and an interrupt request is made, “1” is set to bit 1 (FE) of the status register A705. Set. For example, when bit 0 (PEIE) of the control register C709 is set to “1”, when a parity error is detected and an interrupt request is made, “1” is set to bit 0 (PF) of the status register A705. Set. When a plurality of communication errors are detected, the interrupt control circuit 714 makes an interrupt request based on the plurality of communication errors and sets the corresponding bits of the status register A 705 to “1”.

  The transmission format / parity generation circuit 715 generates a data format of transmission data. In this embodiment, the transmission format / parity generation circuit 715 generates a data format by adding a start bit and a stop bit to the transmission data stored in the transmission data register 710 and transfers the data format to the transmission shift register 712. When bit 1 (PE) of the control register A707 is set to “1” and the parity function is set to be used, the transmission format / parity generation circuit 715 adds a parity bit to the transmission data. Generate a data format.

  The reception format / parity check circuit 716 detects the data format of the reception data. In this embodiment, the reception format / parity check circuit 716 detects the start bit and the stop bit from the reception data stored in the reception shift register 713, detects the data portion included in the reception data, and receives the reception data register. Forward to 711. When bit 1 (PE) of the control register A707 is set to “1” and the parity function is set to be used, the reception format / parity check circuit 716 obtains the parity of the reception data and receives the reception data. It is detected whether or not it matches the parity included in. If the obtained value does not match the parity included in the received data, the reception format / parity check circuit 716 detects a parity error. If it is set in the serial communication circuit setting process to be described later that an interrupt request at the time of communication error is permitted, the interrupt control circuit 714 interrupts the CPU 56 with the occurrence of the communication error as a cause of interruption when detecting a parity error. Make a request.

  FIG. 24 is an explanatory diagram showing an example of output port assignment in the game control means. As shown in FIG. 24, the output port 0 outputs a payout control signal (in this example, a connection signal) transmitted to the payout control board 37. Further, a solenoid (large winning port door solenoid) 21 for opening and closing a variable winning ball device 20 for opening and closing the big winning port, and a solenoid (ordinary electric accessory solenoid) 16 for opening and closing the variable winning ball device 15 are driven. The signal is also output from output port 0. Further, an on-state signal is output from the output port 0 via the terminal board 160 to an external device (for example, a hall computer). The on-time state signal is included in various information output signals related to control in the pachinko gaming machine 1, and when power supply to the pachinko gaming machine 1 is started, a predetermined initialization process is not executed. In addition, based on the fact that data indicating the probability variation state is stored in a predetermined area of the RAM 55 (for example, a backup area for storing the probability variation flag), it is output as a state output signal.

  Note that the logic (for example, 0 is on) opposite to the “logic” (for example, 1 is on) shown in FIG. 24 may be used. In particular, for the connection signal, the main board 31 and the payout control board. The “logic” is determined so that the payout control microcomputer 370 always detects the off state when the signal line to the terminal 37 is disconnected or when the cable is disconnected (including no cable connection). . Specifically, generally, when disconnection or cable disconnection occurs, a high level is detected on the signal receiving side, so the high level on the signal line between the main board 31 and the payout control board 37 is the game control means. The “logic” is determined to be in the off state at the output port at. Therefore, if necessary, an output buffer circuit for logically inverting the signal is provided outside the output port on the main board 31.

  Then, various information output signals, that is, information related to control (for example, start port signal, symbol determination number of times 1) from the output port 0 or the output port 1 to the external device (for example, hall computer) via the terminal board 160. Output data of signal, gaming machine specific information, jackpot 1 signal, jackpot 2 signal, jackpot 3 signal, time-short signal, security signal, throwing state signal). In this embodiment, a prize ball signal 1 (a signal that is output every time one prize ball payout is detected) or a gaming machine error status signal (a gaming machine is in an error status (in this example, a ball is out of ball). An error state or a full error state), a door open signal (a signal indicating that an open state of the glass door frame 2 or the mechanism plate of the game frame 11 or an open state of the game frame 11 itself is detected) Are also output to an external device via the terminal board 160.

  In this case, on the payout control board 37 side, a prize ball payout or an error state of the gaming machine is detected, and a prize ball signal 1 or a gaming machine error state signal is input to the main board 31. The prize ball signal 1 and the gaming machine error status signal input to the main board 31 are output via the terminal board 160 via the main board 31 as they are without passing through the game control microcomputer 560. Is done. The prize ball signal 1 and the gaming machine error state signal input to the main board 31 may be output to the outside via the terminal board 160 after temporarily passing through the gaming control microcomputer 560. Further, in a predetermined board (for example, the power board 910, the main board 31 or the payout control board 37) provided with the backup power supply circuit 508, a door open state is detected, and the door open signal is sent to the game control micro on the main board 31. Input to the input port of the computer 560. When the backup power supply circuit 508 is provided outside the main board 31, the door opening signal is output to the outside via the terminal board 160 after temporarily passing through the game control microcomputer 560 on the main board 31. You may make it do. Alternatively, the door opening signal is branched before passing through the main board 31, or the door opening signal is branched on the main board 31 before being input to the input port of the game control microcomputer 560. Instead of going through the board 31 or the game control microcomputer 560, it may be outputted to the outside via the terminal board 160.

  Note that signals output to the outside via the terminal board 160 are not limited to those shown in this embodiment. For example, prize ball information that is output every time ten prize balls are detected may be output to an external device via the terminal board 160. In this case, the payout of the prize ball is also detected on the payout control board 37 side, and the prize ball information is input to the main board 31. The prize ball information input to the main board 31 is output to the outside via the terminal board 160 via the main board 31 as it is without passing through the game control microcomputer 560. However, it is assumed that the prize ball information is branched on the main board 31 and input to the game control microcomputer 560. Also in this case, the prize ball information input to the main board 31 may be output to the outside via the terminal board 160 after temporarily passing through the game control microcomputer 560.

  In addition, for example, the gaming machine has two start winning ports, a first start winning port and a second starting winning port, and is configured to be capable of variably displaying two special symbols, a first special symbol and a second special symbol. In this case, the symbol determination frequency signal 2 may be externally output via the terminal board 160 in addition to the symbol determination frequency signal 1 as a symbol determination frequency signal for notifying the number of times of variation of the special symbol. . In this case, for example, in order to notify the number of fluctuations of both the first special symbol and the second special symbol by externally outputting the symbol determination number 2 signal as a signal for notifying only the number of fluctuations of the first special symbol. The signal may be configured to be externally output as a signal of the number of symbol determinations. With such a configuration, on the external device side such as a hall computer, in addition to the number of fluctuations of only the first special symbol, the number of fluctuations of the first special symbol and the second special symbol, or the fluctuation of only the second special symbol The number of times can also be grasped.

  In this embodiment, only a single bit 2 in the output port 1 of the gaming control microcomputer 560 is assigned to the serial signal indicating the gaming machine specific information. Therefore, the manufacturer code, chip individual number, and model name code included in the gaming machine specific information are all output from bit 2 of the output port 1. In contrast, a plurality of bits at the output port of the gaming control microcomputer 560 may be separately assigned to the manufacturer code, chip individual number, and model name code included in the gaming machine specific information. . In this case, the manufacturer code, the chip individual number, and the model name code included in the gaming machine specific information are respectively output as serial signals from separate bits at the output port of the gaming control microcomputer 560, and the terminal board 160 And so on. Also, a plurality of bits for outputting the gaming machine specific information may be assigned and the gaming machine specific information may be output as parallel data in units of a predetermined number of bytes (for example, 1 byte). The manufacturer code, chip individual number, and model name code included in the gaming machine specific information may all be output from a common bit in the output port, or may be output from separate bits. May be.

  In this embodiment, a dedicated bit 3 at the output port 0 of the game control microcomputer 100 is assigned to the serial signal indicating the on-time state signal. On the other hand, a bit at the output port common to other signals may be assigned to the on-state signal. As an example, the on-state signal may be output from bit 7 in the output port 1 from which the security signal is output. In this case, the external state device recognizes which of the input state signal and the security signal is externally output based on the output timing, for example, by time-division multiplexing the input state signal and the security signal. You can do it. Alternatively, different signal output patterns (for example, patterns indicating the length of the on-time in which each signal is turned on) are prepared for the on-state signal and the security signal, depending on which signal output pattern is used. The external device may recognize which one of the on-time state signal and the security signal is output externally.

  FIG. 25 is an explanatory diagram showing an example of bit assignment of input ports in the game control means. As shown in FIG. 25, the bits 0 to 7 of the input port 0 include the count switch 23, the gate switch 32a, the winning port switches 29a and 30a, the magnet sensor signal 1, the magnet sensor signal 2, the door opening signal, and the award, respectively. Sphere information is input. In this embodiment, two magnet sensors (not shown) for detecting fraud using magnets are provided, and detection signals from the respective magnet sensors are also input to the input port 0. Is done. Further, the detection signal of the start port switch 14a is input to bit 0 of the input port 1. Further, the detection signal of the winning confirmation switch 14b is input to bit 1 of the input port 1. Further, the power-off signal from the power supply board 910 and the detection signal of the clear switch 914 are input to the bits 3 and 4 of the input port 1, respectively.

  FIG. 26 is an explanatory diagram showing the internal configuration of the terminal board 160. FIG. 26A is a circuit diagram showing connections of connectors and the like provided on the terminal board 160. The terminal board 160 shown in FIG. 26A has a connector CN-h serving as an input side connector for connecting a cable for transmitting signals from the main board 31, the payout control board 37, or the door opening switches 155a and 155b. (H = 1, 2, 3) and a connector CNj (j = 1, 2,..., 12) serving as an output side connector for connecting a signal transmission cable to an external device such as a hall computer. It is provided. The signal from the payout control board 37 is transmitted via the main board 11. The terminal board 160 is mounted with a semiconductor relay (PhotoMOS relay) PCj as a driver circuit.

  FIG. 26B is an explanatory diagram showing an example of assignment of connectors provided on the terminal board 160. In the terminal board 160, various signals are input to the terminal board 160 from the main board 31 (game control microcomputer 560) by connecting the cable from the main board 31 to the connector CN-1. Specifically, a start port signal is input to the terminal “2” of the connector CN-1, a symbol determination number 1 signal is input to the terminal “3” of the connector CN-1, and a terminal “4” of the connector CN-1 is input. Is input to the terminal “5” of the connector CN-1, one signal is input to the terminal “6” of the connector CN-1, two signals are input to the terminal “6” of the connector CN-1, and the terminal “ 7 ”is input to the jackpot 3 signal, the time signal is input to the terminal“ 8 ”of the connector CN-1, the security signal is input to the terminal“ 9 ”of the connector CN-1, and the terminal“ The input state signal is input to “10”.

  In addition, when the cable from the payout control board 37 is connected to the connector CN-2 via the main board 31, various signals from the payout control board 37 (the payout control microcomputer 370) are input to the terminal board 160. Is done. Specifically, the prize ball signal 1 is input to the terminal “2” of the connector CN-2, and the gaming machine error state signal is input to the terminal “3” of the connector CN-2. By connecting the cable from the backup power supply circuit 508 via the door opening switches 155a and 155b to the connector CN-3, a door opening signal from the backup power supply circuit 508 is input to the terminal board 160. Specifically, a door open signal is input to the terminal “2” of the connector CN-3.

  The door opening signal output from the backup power supply circuit 508 may be transmitted so as to be directly input to the terminal board 160, or may be input to the terminal board 160 via the payout control board 37. It may be input to the terminal board 160 via the payout control board 37 or the main board 31. When the backup power supply circuit 508 is provided on the payout control board 37, a door opening signal may be transmitted so as to be directly input from the payout control board 37 to the terminal board 160, or the main board 31 may be It may be input to the terminal board 160 via. Alternatively, when the backup power supply circuit 508 is provided on the main board 31, the door opening signal may be transmitted so as to be directly input from the main board 31 to the terminal board 160, or via the payout control board 37. Then, it may be input to the terminal board 160. If the door opening signal is input to the terminal board 160 from the main board 31 or the payout control board 37, wiring for transmitting the door opening signal from the backup power supply circuit 508 to the terminal board 160 is provided. In addition, the wiring between the dispensing control board 37 and the terminal board 160 can be collected, wiring can be easily handled, and wiring work and attachment / detachment work can be easily performed.

  All wiring for transmitting signals input to the terminal board 160 may be routed through the main board 31. That is, signals from the payout control board 37 and the backup power supply circuit 508 are input to the main board 31 and output from the main board 31 to the terminal board 160. According to such a configuration, since the main board 31 and the payout control board 37 and the backup power supply circuit 508 are connected in advance, when the operator performs wiring to the terminal board 160, the terminal board 160 and the main board 31 And the wiring processing operation for the terminal board 160 can be easily performed.

  As shown in FIG. 26A, in the terminal board 160, the signal line of the reference potential is connected to the terminal “1” of the connector CN-h. The signal line is branched and connected to the input terminal “1” of each semiconductor relay PCj (j = 1, 2,..., 12). Further, terminal “i (i = 2,..., 10)” of connector CN-h (terminals “2” to “10” of connector CN-1 and terminals “2”, “3” of connector CN-2 and The signal lines connected to the terminal “2” of the connector CN-3 are respectively connected to the input terminal “2” of the semiconductor relay PCj via a 1 KΩ resistor Rj. The signal line connected to the output terminal “4” of the semiconductor relay PCj is connected to the terminal “1” of the connector CNj. The signal line connected to the output terminal “3” of the semiconductor relay PCj is connected to the terminal “2” of the connector CNj.

  In the semiconductor relay PCj, when a signal current flows through the input terminal, the light emitting element (LED) on the input side emits light. The emitted light is applied to the photoelectric element (solar cell) provided opposite to the LED through the transparent silicon. The photoelectric element that has received the light is exchanged for voltage according to the amount of light, and this voltage passes through the control circuit to charge the MOSFET gate of the output section. When the MOSFET gate voltage supplied from the photoelectric element reaches the set voltage value, the MOSFET becomes conductive and turns on the load. When the signal current at the input terminal is cut off, the light emitting element (LED) stops emitting light. When the light emission of the LED stops, the voltage of the photoelectric element decreases, and when the voltage supplied from the photoelectric element decreases, the gate load of the MOSFET is rapidly discharged by the control circuit. With this control circuit, the MOSFET is turned off and the load is turned off.

  By the operation of the semiconductor relay PCj as described above, a signal input from the input-side connector CN-h is transmitted to the output-side connector CNj and output to an external device such as a hall computer. Specifically, a start port signal is output from the connector CN1, a symbol determination number 1 signal is output from the connector CN2, a game machine specific information is output from the connector CN3, a jackpot 1 signal is output from the connector CN4, and the connector CN5 2 signals are output from the connector CN6, 3 signals are output from the connector CN6, a time reduction signal is output from the connector CN7, a security signal is output from the connector CN8, a closing state signal is output from the connector CN9, and the connector CN10 is output. A prize ball signal 1 is output from the connector CN11, a gaming machine error state signal is output from the connector CN11, and a door opening signal is output from the connector CN12. The assignment of connectors to each external output signal on terminal board 160 is not limited to that shown in this embodiment. For example, the security signal may be output from the end connector (for example, connector CN12) provided on the terminal board 160.

  The security signal output from the connector CN8 is a signal indicating the security state of the gaming machine. Specifically, as will be described later, when it is determined that an abnormal winning to the start winning opening 14 has occurred based on the detection result of the start opening switch 14a and the detection result of the winning confirmation switch 14b, the security signal Is output to an external device such as a hall computer for a predetermined period (for example, 4 minutes). With such a configuration, it is confirmed that an illegal act that causes the start winning opening 14 to be recognized so as to be larger than the actual winning number by using radio waves or the like is performed by an external computer such as a hall computer. It can be made recognizable on the device side.

  In this embodiment, even when the gaming machine is turned on and the initialization process is executed, the security signal is output to an external device such as a hall computer for a predetermined period (for example, 30 seconds). . By configuring as such, it is recognized that the initialization process has been executed at an unnatural timing (for example, even after all the gaming machine power reset operations have been completed when the amusement store is opened). By making it possible, the external device such as a hall computer can recognize the possibility that an unauthorized act of illegally resetting the power of the gaming machine and aiming for a big hit at the power reset timing is performed. it can.

  In this embodiment, as described above, the RAM 55 is based on the case where the abnormal winning is detected and the initialization process (for example, the operation by the clear switch 914 is performed when the game machine is powered on). Common security signals are output from the common connector CN8 of the terminal board 160 to the outside. In this regard, the initialization process is usually performed only when the game machine power is reset when the amusement store is opened. Therefore, the terminal is used for a signal that is output only once a day. Providing a dedicated connector or semiconductor relay on the substrate 160 is not efficient and wasteful. Therefore, in this embodiment, an external output signal is configured by outputting a security signal from the common connector CN8 when an abnormal winning is detected and when an initialization process is executed. The waste of lines and circuit elements is reduced. That is, it is possible to prevent an increase in the number of parts of a mechanism for outputting information to an external device such as a hall computer and complication of wiring work.

  The signal output from the common connector as a security signal is not limited to that shown in this embodiment. For example, not only abnormal winning at the start winning opening 14, but abnormal winning at the large winning opening or the normal winning openings 29, 30 can be detected and externally output as a security signal from the common connector CN8 of the terminal board 160. You may comprise. In this case, for example, in the case of the big winning opening and the normal winning openings 29 and 30, similarly to the start winning opening 14, two types of switches (proximity switch and photo switch) having different detection methods are used as switches for detecting the winning of the game ball. A sensor) is provided, and the presence / absence of an abnormal prize may be determined according to the same determination method as that for the start winning opening 14.

  Further, for example, when abnormal magnetism is detected by a magnet sensor provided in a gaming machine or when abnormal radio waves are detected by a radio wave sensor provided in a gaming machine, a security signal is output from the common connector CN8 of the terminal board 160. You may comprise so that external output is possible. In addition, for example, when an abnormality of various switches provided in the gaming machine is detected (for example, when occurrence of a short circuit is detected by determining that the input value has exceeded the threshold value), a common terminal board 160 is used. The connector CN8 may be configured so that it can be externally output as a security signal.

  As described above, even if a single winning line, abnormal magnetic error, or abnormal radio wave error can be output as a security signal from the common connector CN8 of the terminal board 160, even one signal line can be obtained. If connected, an error detection can be performed by an external device such as a hall computer, and the work load related to error detection can be reduced.

  In the case of detecting an abnormal winning at the big winning opening, when determining based on the number of detections by the count switch 23 and the number of detections by the winning confirmation switch being a predetermined value (for example, 10) or more. In addition, the count switch 23 when the value of the special symbol process flag is not a value indicating that the game is a big hit game (for example, when the value of the special symbol process flag is not 4 or more, see FIG. 52). Even when a game ball is detected by the above, it may be determined that an abnormal winning to the big winning opening has occurred. In addition, in this way, when it is determined that an abnormal winning to the big winning opening has occurred based on the detection result of the count switch 23 and the winning confirmation switch, or an abnormal to the big winning opening based on the value of the special symbol process flag. Even when it is determined that a winning has occurred, the security signal is externally output by setting a predetermined time (for example, 4 minutes) in the security signal information timer, similarly to step S127 in the switch normal / abnormal check process. You can do it.

  Further, for example, even when a communication error between the game control microcomputer 560 and the payout control microcomputer 370 is detected, it can be externally output as a security signal from the common connector CN8 of the terminal board 160. May be. In this case, for example, the game control microcomputer 560 determines that a communication error has occurred based on failure to receive a connection OK command or a prize ball number reception command (to be described later) from the payout control microcomputer 370, and the terminal The security signal may be externally output from the common connector CN8 of the board 160. Further, for example, the game control microcomputer 560 determines that a communication error has occurred based on the value of any of the error bits of bits 0 to 4 of the status register A of the serial communication circuit 505 being set. The security signal may be externally output from the common connector CN8 of the terminal board 160.

  In addition to the signal line and connector CN8 for security signals, a signal line and connector dedicated to communication errors between the game control microcomputer 560 and the payout control microcomputer 370 may be provided on the terminal board 160. When a communication error between the game control microcomputer 560 and the payout control microcomputer 370 is detected, an external device such as a hall computer is transmitted via the terminal board 160 as a signal different from the security signal. May be output.

  In addition to the signal line for security signal output, detection of initialization processing, detection of abnormal winning at the start winning opening 14, detection of abnormal winning at the big winning opening, detection of abnormal magnetic error, abnormal radio wave Separate signal lines are provided for error detection and communication error detection, and an external output signal corresponding to each error is output from the terminal board 160 to an external device such as a hall computer together with a security signal. It may be. With such a configuration, it is possible to recognize that an error has occurred by checking the security signal, and further, by checking the signal output for each type of error, the type of error can be determined on the amusement store side. Can be confirmed. Therefore, when an amusement store requires a confirmation of the type of error, an external output signal for each error type is provided separately from the security signal, so that an external output that better meets the needs of the amusement store can be provided. Can be done. On the other hand, in the case of a game shop that only requests confirmation that some kind of error has occurred, only the security signal out of the externally output signals is connected to an external device such as a hall computer. Check it.

  When a security signal is output from the connector CN8 or the like when it is determined that an abnormal winning at the start winning port 14 has occurred, or when an initialization process is executed by turning on the power to the gaming machine, What is necessary is just to output once the security signal which will be in a predetermined state (on state) continuously over a predetermined period (for example, 4 minutes or 30 seconds etc.). Note that the signal output is not limited to one that is output continuously for a predetermined period of time. For example, in a predetermined period (for example, 4 minutes or 30 seconds), a predetermined signal output period (for example, 1 second) ), After outputting a security signal in a predetermined state (ON state), after a predetermined output stop period (for example, 1 second), the security signal output is stopped, and then the signal output period is set again. The signal output period and the output stop period may be alternately provided so that the signal output is resumed, and the security signal may be repeatedly output a plurality of times.

  In this embodiment, a dedicated connector CN10 is provided corresponding to the on-time state signal. On the other hand, the on-state signal may be output from a connector common to other signals. As an example, the on-state signal may be output from the connector CN8 common to the security signal. In this case, it is only necessary to make it possible for the external device to recognize which signal is output to the outside by performing time division multiplexing or changing the signal output pattern.

  The gaming machine specific information output from the connector CN3 is information given individually in advance for each chip of the gaming control microcomputer 560 or for each gaming machine in the gaming machine. The manufacturer as shown in FIG. Includes code, chip individual number, and model name code. In this embodiment, the glass door provided in the game frame 11 when the power is turned on when power supply to the pachinko gaming machine 1 is started, when the gaming state in the pachinko gaming machine 1 is controlled to the big hit gaming state, and When the door is opened, in which the frame 2, the mechanism board, or the game frame 11 itself is opened, the game machine specific information is output to an external device such as a hall computer. As a result, the game machine specific information is output based on the establishment of any one of a plurality of predetermined different information output conditions, and the external machine side such as a hall computer outputs the game machine specific information. Make legitimacy possible.

  Signals externally output from the common connector as gaming machine specific information are not limited to those shown in this embodiment. For example, information indicating a comprehensive management number (identification number) of the pachinko gaming machine 1 in the game hall, or information indicating the comprehensive pachinko gaming machine 1 in the gaming hall, not limited to information including the manufacturer code, the chip individual number, and the model name code. Information indicating the installation position (for example, part or all of the island number or machine number), information indicating the date of manufacture of the pachinko gaming machine 1, information indicating the date of sale of the pachinko gaming machine 1, and pachinko gaming machine 1 Information indicating the installation date of the pachinko machine, information indicating the date and time of the first activation of the pachinko gaming machine 1, information indicating the date of validity of the pachinko gaming machine 1, information indicating the gaming history of the pachinko gaming machine 1 , Information indicating an error history of the pachinko gaming machine 1, information indicating a repair history of the pachinko gaming machine 1, information indicating a program update history of the pachinko gaming machine 1, and an initialization history of the pachinko gaming machine 1 Some or all of the broadcast may also be included in the gaming machine specific information to be externally output.

  For example, the gaming control microcomputer 560 may include an RTCM (Real Time Clock Module) in order to include information indicating various dates and times in the gaming machine specific information and output the information to the outside. Alternatively, based on information indicating the date and time acquired from the RTCM externally attached to the gaming control microcomputer 560, time information to be externally output included in the gaming machine specific information may be created. The information indicating the game history of the pachinko machine 1 includes the variable display count, the big hit count, the small hit count, the probability variation control count, the time-short control count, the demonstration screen display count, and the big hit after the pachinko machine 1 is turned on. Information indicating a part or all of the number of variable display times from, the number of variable display times after the end of the small hit, the number of reach occurrences, etc. may be used.

  Information output conditions for externally outputting gaming machine specific information are not limited when the power is turned on, when a big hit, or when the door is opened. For example, when it is determined that an abnormal winning to the start winning opening 14 has occurred, the information output condition is satisfied and the gaming machine specific information is output to the outside in accordance with the external output of the security signal. May be. Alternatively, when the gaming machine is turned on and the initialization process is executed, the information output condition is satisfied and the gaming machine specific information is output to the outside in accordance with the external output of the security signal. You may do it. When it is determined that an abnormal winning at the big winning opening or the normal start opening 29, 30 has occurred, the information output condition is in accordance with the external output of the security signal or even when the security signal is not externally output. May be established and gaming machine specific information may be output externally. When abnormal magnetism is detected by the magnet sensor provided in the gaming machine, or when abnormal radio waves are detected by the radio wave sensor provided in the gaming machine, the security signal is output in accordance with the external output. Even if the information is not output to the outside, the information output condition may be satisfied and the gaming machine specific information may be output to the outside. When an abnormality is detected in various switches provided in the gaming machine, the information output condition is met and the game machine specific information is established in accordance with the security signal being externally output or even if the security signal is not externally output. May be output externally.

  When a communication error between the game control microcomputer 560 and the payout control microcomputer 370 (for example, any of overrun, noise error, framing error, parity error, etc.) is detected, a security signal is output to the outside. In accordance with this, or even if the security signal is not output to the outside, the information output condition may be satisfied and the gaming machine specific information may be output to the outside. As described above, some or all of the conditions that are the same as the conditions under which the security signal is externally output or the conditions under which the security signal is externally output may be predetermined as the information output conditions. Good.

  Further, the information output condition for the game machine specific information to be output to the outside is that the clear signal input to the game control microcomputer 560 is turned on, the reset input to the game control microcomputer 560 That the signal has been turned on, a predetermined error relating to payout (for example, any of a prize ball error, a full tank error, a ball shortage error, a payout number error error, etc.) has been notified from the payout control microcomputer 370; That the current date and time acquired from the RTCM built in or externally attached to the gaming control microcomputer 560 is a predetermined time, that the number of variable displays since the power-on of the pachinko gaming machine 1 has reached a predetermined number, That the number of big hits since the power-on of the machine 1 has reached a predetermined number, pachinko machines The number of small hits since turning on the power of the pachinko gaming machine 1 has reached a predetermined number of times, the number of probability variation control times since the turning on of the pachinko gaming machine 1 has reached a predetermined number, and the time-saving control from the time of turning on the pachinko gaming machine 1 The number of times has reached a predetermined number, the number of variable displays after the end of the big hit has reached the predetermined number, the number of variable displays after the end of the small hit has reached the predetermined number, the number of variable displays after the end of the short time Has reached a predetermined number of times, a demo screen has been displayed, a prepaid card has been inserted into the card unit 50, a membership card has been inserted into the card unit 50, and a coin has been inserted into the card unit 50 , An instruction to return a card or coin, an instruction to rent a game ball, an operation of a call button of a call lamp unit, a plurality of items from the payout control board 37 Among such that one of the error signal of the kind has been transmitted, including some or all may be of any predetermined.

  In this embodiment, the maker code, chip individual number, and model name code included in the gaming machine specific information are all provided as common signals provided on the terminal board 160 as a serial signal transmitted through one signal line. Is output from the connector CN3. As a result, the number of parts and the number of wirings of a mechanism for outputting information to an external device such as a hall computer can be reduced, and complication of wiring work can be prevented. That is, the waste of signal lines and circuit elements for external output can be reduced.

  The configuration for outputting the gaming machine specific information to the outside is not limited to the configuration for outputting in a serial signal system using one signal line using the common connector CN3. For example, signal lines are separately provided for the manufacturer code, chip individual number, and model name code included in the gaming machine specific information, and the gaming machine specific information is transferred from the terminal board 160 to an external device such as a hall computer. The included manufacturer code, chip individual number, and model name code may be output in parallel in the serial signal system, and output in the parallel signal system as a whole of the gaming machine specific information. Alternatively, regardless of the manufacturer code, chip individual number, and model name code included in the gaming machine specific information, a plurality of signal lines corresponding to a predetermined number of bytes (for example, 1 byte) are provided as a whole. The whole gaming machine specific information may be sequentially output to an external device such as a computer by a parallel signal system in units of a predetermined number of bytes (for example, 1 byte). Alternatively, the manufacturer code, the chip individual number, and the model name code included in the gaming machine specific information may be output in parallel using the parallel signal system.

  Some of the manufacturer code, chip individual number, and model name code included in the gaming machine specific information are externally output in the serial signal system, while other information included in the gaming machine specific information is a parallel signal. It may be configured to output externally using a method. As an example, for the manufacturer code and chip individual number included in the gaming machine specific information, since the data length (number of bytes) is relatively short as 3 bytes or 4 bytes, from a common connector provided on the terminal board 160, Alternatively, it is externally output by a serial signal system from separate connectors corresponding to the manufacturer code and the individual chip number. On the other hand, the model name code included in the gaming machine specific information has a relatively long data length (number of bytes) of 32 bytes. To do.

  In any of the above configurations, the gaming machine specific information is externally output from the connector CN3 or the like provided separately from the connector CN8 that outputs a security signal on the terminal board 160. On the other hand, the connector CN8 from which the security signal is output may be a common connector from which the gaming machine specific information is output by the serial signal system. For example, all of the manufacturer code, chip individual number, and model name code included in the gaming machine specific information are serial signals transmitted through one signal line common to the security signal, and are provided on the terminal board 160. The signal may be output from the common connector CN8. Alternatively, the manufacturer code, chip individual number, and part of the model name code (for example, manufacturer code and chip individual number) included in the gaming machine specific information are transmitted through a single signal line common to the security signal. A serial signal that is externally output from the common connector CN8, while other information (eg, model name code) included in the gaming machine specific information is a connector that is separate from the connector CN8 from which the security signal is externally output. (For example, the connector CN3 or the like) may be externally output by a serial signal method or a parallel signal method.

  In addition, one information out of the manufacturer code, chip individual number, and model name code included in the gaming machine specific information is externally output by a serial signal system from the connector CN8 from which the security signal is externally output. The two pieces of information may be externally output by a serial signal system or a parallel signal system from a connector provided separately corresponding to each information.

  The maker code, chip individual number, and model name code included in the gaming machine specific information are all externally output from a common connector CN3 provided on the terminal board 160 as a serial signal transmitted through one signal line. In this case, the manufacturer code, the chip individual number, and the model name code may be externally output in an arbitrary predetermined order. As a specific example, when the game machine specific information is output to the outside, the manufacturer code may be output first, the chip individual number may be output, and finally the model name code may be output. As another example, first, the chip individual number may be output, then the model name code may be output, and finally the manufacturer code may be output. Or, output after performing one or both of encryption processing (including scramble processing) and data compression processing on all of the manufacturer code, chip individual number, and model name code included in the gaming machine specific information By doing so, the respective information may be output outside in an indefinite order.

  In the above embodiment, a jackpot 1 signal or a jackpot 2 signal, which is a status signal indicating a big hit gaming state, is output from a connector separate from the connector CN3 from which gaming machine specific information is output to the outside, and the door is opened. A door opening signal serving as a state signal indicating that the door is open is output to the outside. On the other hand, a state signal that can specify a predetermined state in the gaming machine may be configured to be externally output from a connector CN3 that is shared with the gaming machine specific information. For example, state information that can specify a predetermined state such as a big hit or door opening is used as header information or footer information of gaming machine specific information before or after the gaming machine specific information is externally output from the common connector CN3. It may be output externally. Alternatively, status information and gaming machine specific information can be output together after performing one or both of encryption processing (including scramble processing) and data compression processing, so that the information is out of order and output externally. May be.

  As described above, by providing the semiconductor relay PCj on the terminal board 160, signal input from the outside to the inside of the gaming machine can be prevented, and as a result, illegal acts can be reliably prevented. In the above example, the semiconductor relay PCj is provided on the terminal board 160, but other relay elements such as a mechanical relay may be used instead of the semiconductor relay PCj.

  The on-time state signal output from the connector CN9 is a signal indicating whether or not the gaming state is in a special gaming state such as a probability change state at the start of power supply (when the power is turned on) in the pachinko gaming machine 1. Specifically, as will be described later, when the power supply is started in the pachinko gaming machine 1, the special gaming state is set in a predetermined area of the RAM 55 based on the fact that the clear switch 914 is not operated and is turned off. When the data indicating the game state is stored and the data indicating the special gaming state is stored, the on-time state signal is output from an external device such as a hall computer until a predetermined output stop condition is satisfied. Output to the device. By having such a configuration, when there is an effect mode that is a common effect mode regardless of whether it is in the probability variation state or other than the probability variation state, such as the effect mode of mode A or mode B, for example, The fact that the pachinko gaming machine 1 is in a probabilistic state can be easily recognized by an external device such as a hall computer.

  The output stop condition for stopping the external output of the on-time state signal may be satisfied when, for example, the first big hit gaming state is controlled after the power is turned on, and the external output of the on-state signal may be stopped. Note that the condition for stopping the output of the on-state signal is not limited to this. For example, when the game ball that first passes through the start winning opening 14 after the power is turned on is detected by the start opening switch 14a, the output stop condition may be satisfied and the external output of the on state signal may be stopped. Alternatively, when the first probability variation state is controlled after the power is turned on, the output stop condition may be satisfied and the external output of the on-time state signal may be stopped. Alternatively, when the number of variable displays executed after turning on the power reaches a predetermined number, the output stop condition may be satisfied and the external output of the on-time state signal may be stopped. Alternatively, when the elapsed time from the power-on reaches a predetermined time, the output stop condition may be satisfied and the external output of the power-on state signal may be stopped. Alternatively, when the number of game balls launched into the game area 7 after power-on reaches a predetermined number, the output stop condition may be satisfied and the external output of the on-time state signal may be stopped. Alternatively, the external output of the on-state signal may be continued without satisfying the output stop condition until the operation of the clear switch 914 is detected after the power is turned on.

  Next, the operation of the gaming machine will be described. FIG. 27 shows a game control main process executed by the CPU 56 of the game control microcomputer 560 in response to the start of power supply to the game machine and the reset signal to the game control microcomputer 560 becoming high level. It is a flowchart to show. When the input level of the reset terminal to which the reset signal is input becomes a high level, the CPU 56 of the game control microcomputer 560 executes a security check process that is a process for confirming whether the contents of the program are valid. The game control main process after step S1 is started. In the game control main process, the CPU 56 first performs necessary initial settings.

  In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1). Next, an interrupt mode for maskable interrupts is set (step S2), and a stack pointer designation address is set for the stack pointer (step S3). In step S2, the address synthesized from the value (1 byte) of the specific register (I register) of the game control microcomputer 560 and the interrupt vector (1 byte: least significant bit 0) output from the built-in device is Set to the mode indicating the interrupt address. When a maskable interrupt occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter in the stack.

  Next, the CPU 56 starts outputting a connection signal to the payout control microcomputer 370 (step S4). When the CPU 56 starts outputting the connection signal in step S4, the CPU 56 sends a connection signal to the payout control microcomputer 370 unless the power supply of the gaming machine is stopped or output is impossible due to some communication error. Output continuously.

  Next, the built-in device register is set (initialized) (step S5). By the processing in step S5, the CTC (counter / timer) and PIO (parallel input / output port) which are built-in devices (built-in peripheral circuits) are set (initialized).

  The game control microcomputer 560 used in this embodiment also incorporates an I / O port (PIO) and a timer / counter circuit (CTC) 504.

  Next, the CPU 56 sets the RAM 55 in an accessible state (step S6), and proceeds to a clear signal check process.

  Note that a software delay process for delaying the start timing of the game device control process (game control process) for controlling the progress of the game by software may be executed. By such software delay processing, the start timing of the game control processing can be delayed as compared with the case where the software delay processing is not executed. When the delay process is executed, a situation occurs in which the microcomputer of the other control board cannot receive the command transmitted from the game control board (main board 31) to the other control board (for example, the payout control board 37). Can be prevented.

  Next, the CPU 56 checks whether or not the clear signal in the on state is transmitted from the clear switch 914, that is, whether or not the clear switch 914 is turned on (step S7). Note that the CPU 56 may confirm the state of the clear signal (on / off) only once via the input port 0, but may confirm the state of the clear signal multiple times. For example, if it is confirmed that the state of the clear signal is an off state, after a delay time of a predetermined time (for example, 0.1 seconds), the state of the clear signal is reconfirmed. If it is confirmed that the clear signal is in the on state at that time, it is determined that the clear signal is in the on state. Further, at this time, if it is confirmed that the state of the clear signal is the off state, after a delay time of a predetermined time, the state of the clear signal may be confirmed again. Here, the number of reconfirmations is not limited to once or twice, but may be three or more times. It is also possible to check twice and check again when the check results do not match.

  If the clear switch 914 is not on in step S7, whether or not data protection processing for the backup RAM area (for example, power supply stop processing such as addition of parity data) has been performed when power supply to the gaming machine is stopped. (Step S8). In this embodiment, when power supply is stopped, a process for protecting data in the backup RAM area is performed. When it is confirmed that such power supply stop processing has been performed, the CPU 56 determines that the power supply stop processing has been performed, that is, the control state at the time of power supply stop is stored. . When it is confirmed that the power supply stop process is not performed, the CPU 56 executes an initialization process.

  Whether or not the power supply stop process has been performed is determined by the value of the backup monitoring timer stored in the backup RAM area in the power supply stop process corresponding to the execution of the power supply stop process (for example, 2). ) Is confirmed by whether or not. Note that such a confirmation method is an example. For example, a flag indicating that the power supply stop process has been executed is set in the backup flag area in the power supply stop process, and the flag is set in step S8. If it is confirmed that the power supply is stopped, it may be determined that the power supply stop process has been performed.

  If it is determined that the control state at the time of stopping power supply is stored, the CPU 56 performs data check (parity check in this example) in the backup RAM area (step S9). In this embodiment, clear data (00) is set in the checksum data area, and the checksum calculation start address is set in the pointer. Also, the number of checksum calculations corresponding to the number of data to be checksum is set. Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated. The calculation result is stored in the checksum data area, the pointer value is incremented by 1, and the checksum calculation count value is decremented by 1. The above processing is repeated until the value of the checksum calculation count becomes zero. When the value of the checksum calculation count becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area and uses the inverted data as the checksum.

  In the power supply stop process, a checksum is calculated by the same process as described above, and the checksum is stored in the backup RAM area. In step S9, the calculated checksum is compared with the stored checksum. When the power supply is stopped after an unexpected power failure or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area may be different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state when the power supply is stopped, the initialization process (the processes of steps S10 and S11) executed at the time of power-on that is not when the power supply is stopped is stopped. Run.

  If the check result is normal, the CPU 56 sets the setting at the time of power interruption recovery in order to return the internal state of the game control means and the control state of the electric parts control means such as the effect control means to the state when the power supply is stopped. This is performed (step S91). Specifically, the start address of the backup setting table stored in the ROM 54 is set as a pointer, and the contents of the backup setting table are sequentially set in the work area (area in the RAM 55). The work area is backed up by a backup power source. In the backup setting table, initialization data for an area that may be initialized in the work area is set. As a result, the saved contents of the work area that should not be initialized remain. The parts that should not be initialized include, for example, data indicating the gaming state before the power supply is stopped (special symbol process flag, etc.), the area where the output state of the output port is saved (output port buffer), unpaid prize balls This is the part where data indicating the number is set.

  In addition, the CPU 56 sets transmission of a command corresponding to the restoration of power interruption by setting the start address of the backup command transmission table stored in the ROM 54 as a pointer. After this transmission setting is made, a backup command is transmitted after serial communication circuit setting processing in step S15a described later is performed.

  After the setting at the time of restoration of power interruption is thus performed in step S91, whether or not data indicating that the gaming state when the power supply of the pachinko gaming machine 1 is stopped (at the time of power interruption) is a probable change state is stored. Is determined (step S92). That is, when the power supply to the pachinko gaming machine 1 is started, the clear switch 914 is off and the initialization process is not executed. It is determined whether or not data indicating that the gaming state in 1 is a probability variation state as a special gaming state is stored.

  As an example, stored data indicating the state (on / off) of the probability change flag is checked in the backup area of the RAM 55. At this time, it may be determined whether or not data indicating the special gaming state is stored in correspondence with whether or not the probability variation flag is ON. In this embodiment, since all of the RAM 55 is backed up, the contents of the probability change flag are stored for a predetermined period after the power supply is stopped, regardless of the area of the RAM 55. Will be.

  It should be noted that the present invention is not limited to determining whether or not data indicating the special gaming state is stored in correspondence with whether or not the probability variation flag is ON. For example, the stored data may be read from a predetermined storage area separately from the probability change flag. More specifically, based on the fact that the power-off signal is output when the power-off processing (see step 20 in FIG. 28) is executed, data indicating the state of the probability change flag is stored in a predetermined area ( This data is stored for a predetermined period even if the power supply is stopped. In this case, by the process of step S91, the probability variation flag corresponding to the stored data in the predetermined area of the RAM 55 may be set to restore the gaming state when the power supply is stopped (at the time of power interruption). . Further, as the special game state, it may be determined whether or not data indicating not only the probability variation state but also the short time state is stored. For example, the state of the time reduction flag stored in the backup area of the RAM 55 is checked, and it is determined whether or not data indicating the special gaming state is stored depending on whether or not the time reduction flag is on. May be.

  When there is a probability change memory at the time of power interruption (or memory of a special gaming state including a time reduction state), the output of the on-time state signal is designated (step S93). For example, the CPU 56 may designate the output of the on-time state signal by holding the state of the probability variation flag stored in a predetermined area of the RAM 55 as it is. After the output state signal is designated, processing in steps S1099A to S1099F, S1100, and S1101 (see FIG. 68) described later is executed, so that the input state signal is transmitted from the pachinko gaming machine 1 to the external device. Will be output externally. It should be noted that the output of the on-state signal is started after the information output process (see step S31 in FIG. 28) based on the generation of the timer interrupt after the output on the on-state signal is designated in step S93. I can't. For example, as the processing in step S93, after setting the information buffer input state signal output bit position (bit 3 of output port 0 in the example shown in FIG. 24), the information buffer is set to the output value and the output value is set. May be output to the output port 0 to start external output of the on-state signal.

  In this embodiment, the output state signal is designated by holding the state of the probability variation flag as it is when the gaming machine is turned on. That is, the state (ON / OFF) of the probability change flag indicates whether or not the game state in the pachinko gaming machine 1 is a probability change state, and outputs an instruction to output an on-time state signal when the power is turned on. Will show. In this way, by sharing the data indicating the state of the probability change flag corresponding to whether or not the gaming state is the probability change state with the data for issuing an output instruction as to whether to output the state signal at the time of input or not, It is not necessary to prepare dedicated data for externally outputting the input state signal, and an increase in the data capacity stored in the RAM 55 can be prevented.

  It should be noted that an on-state signal output instruction may be issued by setting an on-state signal output designation flag provided separately from the probability variation flag to an on state. The on-state signal output designation flag is set to the on-state based on the fact that the initialization process is not executed when the gaming machine is turned on and is in a special game state such as a probability change state. Any signal indicating a signal output instruction may be used.

  In the initialization process, the CPU 56 first performs a RAM clear process (step S10). Note that the predetermined data may be left as it is without initializing the entire area of the RAM 55. Subsequently, initial setting of the work area is performed (step S11). For example, the CPU 56 sets the start address of the initialization time setting table stored in the ROM 54 as a pointer, and sequentially sets the contents of the initialization time setting table in the work area.

  By the processing in step S11, for example, a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol buffer, a special symbol process flag, a winning ball flag, a ball-out flag, and the like are selectively processed according to the control state. An initial value is set in the flag for this.

  Further, the CPU 56 performs initialization command transmission setting (step S12). For example, the start address of the initialization command transmission table stored in the ROM 54 is set as a pointer, and an initialization command for initializing the sub board according to the contents is transmitted to the sub board. As an initialization command, a command indicating an initial symbol displayed on the effect display device 9, an initialization command to the payout control board 37, or the like can be used. After setting in step S13, an initialization command is transmitted after serial communication circuit setting processing in step S15a described later is performed.

  Further, the CPU 56 sets a predetermined security signal output time (30 seconds in this example) corresponding to the initialization process (step S13). For example, a timer initial value corresponding to the security signal output time is set in a security signal information timer provided in a predetermined area of the RAM 55. The security signal information timer is a timer for measuring the ON time of the security signal output from the terminal board 160. In this embodiment, when a predetermined time is set in the security signal information timer in step S13, an information output process (see S31 in FIG. 28) described later is executed, so that the gaming machine is turned on. When the initialization process is executed, a security signal is externally output for a predetermined time (in this example, 30 seconds).

  In response to the start of power supply (power-on) in the pachinko gaming machine 1, the CPU 56 performs setting for outputting the gaming machine specific information to the outside (step S14). As settings for externally outputting gaming machine specific information, for example, a specific information output request flag for requesting external output of gaming machine specific information is set, and a reading start address of gaming machine specific information is set in a specific information read pointer To do.

  Further, the CPU 56 executes a random number circuit setting process for initially setting the random number circuits 503a and 503b (step S15). In this case, the CPU 56 performs settings according to the random number circuit setting program 551 so that the random number circuits 503a and 503b update the random number values.

  Further, the CPU 56 executes a serial communication circuit setting process for initial setting of the serial communication circuit 505 (step S15a). In this case, the CPU 56 sets the data stored in the predetermined area of the ROM 54 in the serial communication circuit 505 in accordance with the serial communication circuit setting program, so that the serial communication circuit 505 performs serial communication with the payout control microcomputer. I do.

  When the serial communication circuit 505 is initialized, the CPU 56 initializes the priority of interrupt processing executed in response to the interrupt request from the serial communication circuit 505 (step S15b). In this case, the CPU 56 initializes the priority of the interrupt process by executing the process according to the interrupt priority setting program 557.

  For example, the CPU 56 initializes the priority of each interrupt process according to a predetermined interrupt process priority table including the default priority of each interrupt process. In this embodiment, the CPU 56 performs an initial setting so as to preferentially execute an interrupt process that causes the occurrence of a communication error in the serial communication circuit 505 according to the interrupt process priority order table. In this case, for example, the CPU 56 sets an interrupt priority execution flag at the time of communication error indicating that priority is given to an interrupt process whose cause is an interrupt.

  In this embodiment, when a timer interrupt and an interrupt request from the serial communication circuit 505 are generated at the same time, the CPU 56 preferentially performs an interrupt process by the timer interrupt.

  In addition, the default priority of each interrupt process can be changed by the user. For example, the game control microcomputer 560 stores specification information for specifying an interrupt process set by a user (for example, a game machine manufacturer) in a predetermined storage area of the ROM 54 in advance. Then, the CPU 56 sets the priority of interrupt processing according to the designation information stored in a predetermined storage area of the ROM 54.

  In addition to steps S15 to S15b, a part of the setting process of the random number circuit 503 and the serial communication circuit 505 is also executed in the process of step S5. For example, in step S5, an initial value is set in the baud rate register, communication setting register, interrupt control register, and status register of the serial communication circuit 505 as the built-in device register.

  For example, in setting the internal device register, the CPU 56 sets the baud rate of the serial communication circuit 505. In this case, the CPU 56 writes a setting value corresponding to the baud rate to be set in the baud rate register 702 of the serial communication circuit 505. For example, the game control microcomputer 560 stores specification information for specifying a set value set by a user (for example, a game machine manufacturer) in a predetermined storage area of the ROM 54 in advance. Then, the CPU 56 writes the setting value in the baud rate register 702 according to the designation information stored in a predetermined storage area of the ROM 54. For example, when the baud rate set value “156” is set by the CPU 56, the baud rate “1201.92 bps” is generated by the baud rate generation circuit 703 using the equation (1) and the clock frequency “3 MHz”.

  For example, the CPU 56 sets the data format of data transmitted and received by the serial communication circuit 505. In this case, the CPU 56 sets the data length (8 bits or 9 bits) of the transmission / reception data and the presence / absence of the parity function by setting the value of each bit of the control register A707. For example, the game control microcomputer 560 stores specification information for specifying the value of each bit of the control register A707 set by the user (for example, the manufacturer of the game machine) in a predetermined storage area of the ROM 54 in advance. Yes. Then, the CPU 56 sets the value of each bit of the control register A707 according to the designation information stored in a predetermined storage area of the ROM 54.

  Further, for example, the CPU 56 sets whether to permit each interrupt request generated by the serial communication circuit 505. In this case, the CPU 56 sets the value of bits 5, 6, and 7 of the control register B708 to thereby send an interrupt request at the time of transmission (a transmission interrupt request that is an interrupt request when transmitting data, or a transmission completion interrupt that is performed when transmission is completed). Request) and whether or not to accept interrupt request at reception. The CPU 56 can also be set to allow both a transmission interrupt request and a reception interrupt request, and allows only one of a transmission interrupt request and a reception interrupt request. It is also possible to set. Further, the CPU 56 sets whether or not to permit an interrupt request at the time of each communication error by setting the values of the bits 0 to 3 of the control register C709. For example, the game control microcomputer 560 stores in advance a designation information for designating values of each bit of the control register B 708 and the control register C 709 set by a user (for example, a manufacturer of the gaming machine) in a predetermined storage area of the ROM 54. I remember it. Then, the CPU 56 sets the value of each bit of the control register B 708 and the control register C 709 according to the designation information stored in a predetermined storage area of the ROM 54.

  In addition, in the initialization process of the game control main process, a process of setting “250” as an initial value to a prize ball number counter used for detecting a prize ball shortage error or a prize ball excess error, which will be described later, is also executed. . The process for setting the initial value in the prize ball number counter may be executed, for example, in the process for sequentially setting each initial value in the work area in steps S91 and S11 until the process proceeds to steps S15 to S17. It only has to be executed during

  Then, the CPU 56 executes a timer interrupt setting process for setting a CTC register built in the game control microcomputer 560 so that a timer interrupt is periodically taken every predetermined time (for example, 4 ms) ( Step S16). That is, a value corresponding to, for example, 4 ms is set in a predetermined register (time constant register) as an initial value. In this embodiment, it is assumed that a timer interrupt is periodically taken every 4 ms.

  When the timer interrupt setting is completed, the CPU 56 first disables the interrupt (step S17), executes the initial value random number update process (step S18a) and the display random number update process (step S18b), The interrupt is permitted again (step S19). That is, the CPU 56 sets the interrupt disabled state when the initial value random number update process and the display random number update process are executed, and interrupts enable state when the initial value random number update process and the display random number update process are finished. To.

  The initial value random number update process is a process for updating the count value of the counter for generating the initial value random number. The initial value random number is a random number for determining the type of jackpot (for example, a jackpot symbol determining random number for determining a special symbol for generating a jackpot or whether to shift the gaming state to a probable state) Initial value of the count value such as a counter (determination random number generation counter) for generating a probability variation determining random number for generating, a normal random number for determining whether or not to generate a hit based on a normal symbol It is a random number for determining the value. Game control processing described later (game control microcomputer 560 controls itself for game devices such as effect display device 9, variable winning ball device 15 and ball payout device 97 provided in the gaming machine, Alternatively, when the count value of the determination random number generation counter makes one round in a process of sending a command signal to cause another microcomputer to control, or a gaming apparatus control process), an initial value is set in the counter.

  The display random number is a random number for determining the display of the special symbol display 8. In this embodiment, as a display random number, a random number for determining a variation pattern for determining a variation pattern of a special symbol, or a random number for determining a reach for determining whether or not to reach when a big hit is not generated, is used. Used. The display random number update process is a process for updating the count value of the counter for generating the display random number.

  In addition, when the display random number update process is executed, the interrupt disabled state is executed by the display random number update process and the initial value random number update process also in the timer interrupt process described later (that is, the timer This is because the same process is executed in steps S26 and S27 of the interrupt process), so as to avoid conflict with the process in the timer interrupt process. That is, if a timer interrupt is generated during the processing of steps S18a and S18b and the count value of the counter for generating the initial value random number and the display random number is updated during the timer interrupt processing, The continuity of values may be impaired. However, such an inconvenience does not occur if the interrupt is prohibited during the processing of steps S18a and S18b.

  When the interrupt-permitted state is set in step S19, the timer interrupt or interrupt request from the serial communication circuit 505 is permitted until the next processing in step S17 is executed and the interrupt-prohibited state is set. . When a timer interrupt occurs while the interrupt permission state is set, the CPU 56 of the game control microcomputer 560 executes a timer interrupt process to be described later. When an interrupt request is generated from the serial communication circuit 505 while the interrupt permission state is set, the CPU 56 of the game control microcomputer 560 causes each interrupt process (communication error interrupt process or reception Execute time interruption processing and transmission completion interruption processing). In this embodiment, priority is given to the interrupt process before the timer interrupt or the interrupt request is set to be permitted by executing step S15b before the loop process from step S17 to step S19. Processing for setting or changing the order is performed.

  In this embodiment, the game control executed by the CPU 56 based on the user program stored in the program data area of the ROM 54 provided in the game control microcomputer 560 when the power supply to the pachinko gaming machine 1 is started is turned on. In the main process, the output setting of the gaming machine specific information is performed in the process of step S14. That is, the external output of the gaming machine specific information when the power is turned on is performed based on the user program. The external output of the gaming machine specific information at power-on is not limited to that performed based on the user program. For example, when the power is turned on, various information constituting the machine-specific information such as manufacturer code, chip individual number, and model name code is read from the ROM 54 and the chip individual number register 506 and serial signal system sequentially from the bit 2 of the output port 1 and the like. The readout circuit for outputting to the terminal board 160 may be provided as an internal circuit or an external circuit of the game control microcomputer 560. That is, the external output of the gaming machine specific information when the power is turned on may be performed by hardware. Alternatively, before executing the user program read from the ROM 54 when the power is turned on, a security check program for inspecting whether the stored contents of the control data used for controlling the operation of the gaming machine in the ROM 54 or the like has been illegally executed is executed. If so, in the processing executed by the CPU 56 based on this security check program, output settings of gaming machine specific information, information buffer settings, and the like may be performed. That is, the external output of the gaming machine specific information when the power is turned on may be performed based on a system program different from the user program.

  Also, when the pachinko gaming machine 1 is turned on, the initialization process is not executed in the game control main process executed by the CPU 56 based on the user program stored in the program data area of the ROM 54 provided in the game control microcomputer 560. In addition, based on the fact that data indicating that the gaming state is the special gaming state is stored, an output of the on-time state signal is designated in step S93. That is, the external output of the input state signal is performed based on the user program. Note that the external output of the on-state signal is not limited to that performed based on the user program. For example, the external output of the power-on state signal when the power is turned on may be performed by hardware. Alternatively, if the security check program is executed before the user program read from the ROM 54 is executed when the power is turned on, output setting of the on-state signal is performed in the processing executed by the CPU 56 based on the security check program. And information buffer setting may be performed. That is, the external output of the input state signal may be performed based on a system program different from the user program. In this case, the determination as to whether or not data indicating the special gaming state is stored may be performed prior to the determination as to whether or not the clear switch 914 is on. Even with such a configuration, it is possible to recognize that the pachinko gaming machine 1 to which the on-time state signal is output externally stores data indicating that it is in a special gaming state when the power is turned on. By operating the clear switch 914 or the like by the site manager, the stored contents of the pachinko gaming machine 1 can be surely initialized (cleared) by executing the initialization process.

  In this embodiment, when a predetermined operation (for example, a pressing operation) of the clear switch 914 is performed when power supply to the pachinko gaming machine 1 is started (Y in step S7), steps S10, The initialization process of S11 is executed. In this case, the security signal output time is set in step S13, so that the security signal in the on state is output to the outside for a predetermined time (for example, 30 seconds). On the other hand, when power supply to the pachinko gaming machine 1 is started, based on the fact that a predetermined operation of the clear switch 914 is not performed (N in Step S7), initialization of Steps S10 and S11 is performed. If the process is not executed, the power failure recovery setting is performed (step S91), and it is determined whether data indicating a special game state such as a probability change state is stored (step S92). . When such data is stored (Y in step S92), the on-state signal at the time of on-state is externally output based on the output instruction in step S93.

  Next, the timer interrupt process will be described. FIG. 28 is a flowchart showing a 4 ms timer interrupt process executed based on a timer interrupt that occurs every predetermined time (for example, 4 ms) in the game control microcomputer 560. When a timer interrupt occurs during the execution of the game control main process, specifically, during a period in which the interrupt is permitted during the execution of the loop process of steps S17 to S19, the CPU 56 of the game control microcomputer 560 Executes a 4 ms timer interrupt process activated in response to the occurrence of a timer interrupt. In the 4 ms timer interrupt process, the CPU 56 first executes a power-off process (power-off detection process) for detecting whether or not a power-off signal is output (whether or not it is turned on) (step S20). Then, the CPU 56 inputs detection signals of switches such as the gate switch 32a, the start port switch 14a, the winning confirmation switch 14b, the count switch 23, and the winning port switches 29a and 30a via the switch circuit 58, and the input of each switch. Is detected (switching process: step S21). Specifically, if the state of the input port for inputting the detection signal of each switch is ON, the value of the switch timer provided corresponding to each switch is incremented by one.

  Next, the CPU 56 executes a display control process for performing display control of the special symbol display 8, the normal symbol display 10, the special symbol hold storage display 18, and the normal symbol hold storage display 41 (step S22). For the special symbol display 8 and the normal symbol display 10, control for outputting a drive signal to each display is executed according to the contents of the output buffer set in steps S36 and S37.

  Next, the CPU 56 executes magnet sensor error notification processing for performing magnet sensor error notification based on the detection signal input from the magnet sensor (step S24).

  Next, the CPU 56 performs a process of updating the count value of each counter for generating a random number for determination such as a random number for determination per ordinary symbol used for game control (determination random number update process: step S25). Further, the CPU 56 performs a process of updating the count value of the counter for generating the initial value random number (initial value random number update process: step S26). Further, the CPU 56 performs a process of updating the count value of the counter for generating the display random number (display random number update process: step S27).

  Next, the CPU 56 performs special symbol process processing (step S28). In the special symbol process, the corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state. Further, normal symbol process processing is performed (step S29). In the normal symbol process, the corresponding process is selected and executed according to the normal symbol process flag for controlling the display state of the normal symbol display 10 in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state.

  Next, the CPU 56 performs a process of sending an effect control command by setting an effect control command related to the effect symbol synchronized with the variation of the special symbol in the transmission data register of the serial communication circuit 505 (effect symbol command control process: step S30). . It should be noted that the fact that the variation of the effect symbol is synchronized with the variation of the special symbol means that the variation time (variable display period) is the same.

  Next, the CPU 56 performs information output processing for outputting data such as a start port signal supplied to the hall management computer, a symbol determination number of times 1 signal, a jackpot 1 to 3 signal, a time reduction signal, a security signal, and the like (step S31). ).

  Next, the CPU 56 executes processing for transmitting / receiving (input / output) signals to / from the payout control microcomputer 370 via the serial communication circuit 505, and when a winning occurs, detection of the winning opening switches 29a, 30a, etc. Prize ball processing is performed for setting the number of prize balls based on the signal (step S32). In this embodiment, data indicating the number of winning balls is obtained by changing the lower 4 bits of the winning ball number command in response to detection of winning based on the winning opening switch 29a, 30a being turned on. The set prize ball number command is output to the payout control microcomputer 370 via the serial communication circuit 505. The payout control microcomputer 370 mounted on the payout control board 37 drives the ball payout device 97 in response to receiving a prize ball number command in which data indicating the number of prize balls is set.

  In addition, a test terminal process, which is a process for outputting a test signal for enabling the control state of the gaming machine to be confirmed outside the gaming machine, is executed (step S33). In this embodiment, a RAM area (output port buffer) corresponding to the output state of the output port is provided. However, the CPU 56 relates to the connection signal and the contents related to the solenoid in the RAM area of the output port 0. Is output to the output port (step S34: output processing). And CPU56 performs the memory | storage process which checks the increase / decrease in a pending | holding memory | storage number (step S35).

  Further, the CPU 56 performs special symbol display control processing for setting special symbol display control data for effect display of the special symbol in the output buffer for setting the special symbol display control data according to the value of the special symbol process flag ( Step S36). Further, the CPU 56 performs a normal symbol display control process for setting normal symbol display control data for effect display of the normal symbol in the output buffer for setting the normal symbol display control data according to the value of the normal symbol process flag ( Step S37).

  Next, the CPU 56 performs a status display lamp display process for setting status display control data for displaying each status display lamp in an output buffer for setting the status display control data (step S38). In this case, when the gaming state is the short time state, the state display control data for displaying the state indicator lamp indicating the short time state is set in the output buffer. When the gaming state is also controlled to a high probability state (for example, a probability variation state), state display control data for displaying a state indicator lamp indicating the high probability state is set in the output buffer. You may do it.

  Next, the CPU 56 performs frame state output processing for transmitting a frame state display command in which information indicating the error state of the gaming machine is set to display the error state of the gaming machine to the production control microcomputer 100. Execute (step S39).

  Thereafter, the interrupt permission state is set (step S40), and the process ends.

  Next, the prize ball process (step S32) in the 4 ms timer interrupt process will be described. First, payout control signals (connection signals, prize ball information) and payout control commands transmitted and received between the main board 31 and the payout control board 37 will be described.

  FIG. 29 is an explanatory diagram showing an example of the content of a control signal output from the game control means to the payout control means. In this embodiment, a connection signal and prize ball information are transmitted and received as control signals between the main board 31 and the payout control board 37 in order to perform various controls relating to payout control and the like. As shown in FIG. 29, the connection signal is output when the main board 31 rises (when the game control means starts the game control process), and notifies the payout control board 37 that the main board 31 has risen. This is a signal (connection signal for the main board 31). The connection signal indicates that the prize ball can be paid out. The connection signal is output via the I / O port 57 and the output circuit 67A of the game control microcomputer 560, and is used for payout control via the input circuit 373A and the I / O port 372e of the payout control microcomputer 370. It is input to the microcomputer 370. The connection signal is 1-bit data and is transmitted through one signal line. Note that the connection signal is ready to be output by setting an initial value to the bit corresponding to the connection signal of the output port 0 by the process of step S4 executed when the power is turned on (specifically, in step S34). Although it is output by processing, it may be output at the timing of step S4). The prize ball information is information for notifying the main board 31 that ten prize balls have been detected each time one prize ball has been detected on the payout control board 37 side. . The prize ball information is output via the I / O port 372a and the output circuit 373B of the payout control microcomputer 370, and the game control is performed via the input circuit 67B and the I / O port 57 of the game control microcomputer 560. To the microcomputer 560. The prize ball information is 1-bit data and is transmitted through one signal line.

  Similarly to the game control microcomputer 560, the payout control microcomputer 370 includes a serial communication circuit 380. Various payout control commands are transmitted and received between the serial communication circuit 505 built in the game control microcomputer 560 and the serial communication circuit 380 built in the payout control microcomputer 370. The configuration and function of the serial communication circuit 380 built in the payout control microcomputer 370 are the same as the configuration and function of the serial communication circuit 505 built in the game control microcomputer 560.

  FIG. 30 is an explanatory diagram showing an example of the contents of control commands transmitted and received between the game control means and the payout control means. In this embodiment, various payout control commands are transmitted and received between the microcomputers of the main board 31 and the payout control board 37 in order to perform various controls related to payout control and the like.

  As described above, the payout control command is composed of 8-bit data (binary 8-digit data), and is output as a control command indicating predetermined contents depending on the contents of the set 8-bit data.

  The connection confirmation command is sent from the game control microcomputer 560 at regular intervals (1 s) in order to confirm whether or not the connection state between the game control microcomputer 560 and the payout control microcomputer 370 is normal. Control command to be sent. The data content of the connection confirmation command is “A0 (H)”, that is, “10100000”.

  The connection OK command is a control command for notifying that the connection state between the game control microcomputer 560 and the payout control microcomputer 370 is normal, and the payout control microcomputer 370 issues a connection confirmation command. Is a control command that is transmitted as a response signal in response to the reception of. The data content of the connection OK command is “8x (H)”, that is, “1000xxxx”. Here, with respect to “xxxx” in the second byte of the connection OK command, as shown in FIG. 31, a prize ball error (a prize ball payout operation based on winning or a ball lending operation based on a ball rental request cannot be performed normally). 96: When the main control unconnected error shown in FIG. 96, payout switch abnormality detection error 1, payout switch abnormality detection error 2, payout case error, main control communication error) occur. In this case, “1” is set to “x” of the first bit (bit 0). When a full tank error occurs, “1” is set to “x” of the second bit (bit 1). When a ball break error occurs, “1” is set to “x” of the third bit (bit 2). In addition, when a payout number abnormality error occurs when the cumulative value of the number of payouts of prize balls and rental balls, which will be described later, reaches a predetermined value (for example, 2000), the fourth bit (bit 3) “1” is set to “x” of In this way, during the confirmation of the connection between the game control microcomputer 560 and the payout control microcomputer 370, the occurrence of a predetermined error in the payout control microcomputer 370 is detected. 560 can be notified. In the example shown in FIG. 31, the connection OK command is set to a value indicating a payout error (award ball error, full tank error, out of ball error, payout number error error) as a control state. A control state other than an error may be set in the connection OK command. For example, the payout control microcomputer 370 sets a value indicating that a prize ball payout operation or a lending ball payout operation is in a control state to the connection OK command, and transmits it to the game control microcomputer 560. You may make it do.

  The award ball number command is a control command for notifying the number (0 to 15) of game balls for which a payout request is made, and is a control command transmitted by the game control microcomputer 560 based on the occurrence of a win. . The content of the prize ball number command data is “5x (H)”, that is, “0101xxx”. In this embodiment, three game balls are paid out when a game ball is detected by the start port switch 14a, and 10 game balls are paid out when a game ball is detected by any of the game port switches 29a and 30a. When a game ball is detected by the count switch 23, 15 prize balls are paid out. Therefore, when a game ball is detected by the start port switch 14a, a prize ball number command “01010011” for notifying the number of prize balls of 3 is transmitted, and the game ball is detected by one of the winning port switches 29a and 30a. If a prize ball number command “01011010” for notifying 10 prize balls is transmitted and a game ball is detected by the count switch 23, the number of prize balls for notifying 15 prize balls is sent. The command “0101111” is transmitted.

  The prize ball number acceptance command is a control command for notifying that the prize ball number specified by the prize ball quantity command has been accepted, and the payout control microcomputer 370 responds upon receipt of the prize ball quantity command. It is a control command transmitted as a signal. The content of the prize ball number reception command data is “70 (H)”, that is, “01110000”.

  The award ball end command is a control command indicating that the award ball operation (award ball payout operation) has ended, and is a control command that the payout control microcomputer 370 transmits based on the end of the award ball operation. The data content of the winning ball end command is “50 (H)”, that is, “01010000”.

  The command for preparing a prize ball is a control command for notifying that a prize ball movement has not been completed due to a long time for a prize ball movement, a rental ball movement or a predetermined error. is there. The contents of the data of the winning ball preparation command are “4x (H)”, that is, “0100xxxx”. Here, with regard to “xxxx” in the second byte of the command for preparing a prize ball, as shown in FIG. 31, when a prize ball error occurs, “1” is set to “1” in the first bit (bit 0). Is set. When a full tank error occurs, “1” is set to “x” of the second bit (bit 1). When a ball break error occurs, “1” is set to “x” of the third bit (bit 2). In addition, when a payout number abnormality error occurs when the cumulative value of the number of payouts of prize balls and rental balls, which will be described later, reaches a predetermined value (for example, 2000), the fourth bit (bit 3) “1” is set to “x” of In this way, the payout control microcomputer 370 receives a prize ball when the prize ball operation takes a long time, or during a lending ball operation or when a predetermined error occurs during the execution of the prize ball operation. The game control microcomputer 560 can be notified that the operation has not ended, and the contents of the error can also be notified to the game control microcomputer 560. As in the case of the connection OK command, the award ball preparation command notifies that a predetermined error has occurred by changing the contents of the lower 4 bits in accordance with the error state (by changing the predetermined bits). Note that the command for preparing a prize ball is not only in a state where an error occurs and the prize ball operation cannot be executed, but also in a state where the prize ball payout operation cannot be started immediately because the ball rental operation is in progress, This command (signal) is output even in the running state (the state in which the payout operation for the number of prize balls specified by the prize ball number command has not been completed). The example shown in FIG. 31 shows a case where a value indicating a payout error (a prize ball error, a full tank error, a ball run out error, a payout number error error) is set as a control state in the command for preparing a prize ball. However, a control state other than an error may be set in the connection OK command. For example, the payout control microcomputer 370 sets a value indicating that the prize ball payout operation or the lending ball payout operation is in the control state in the award ball preparation command, and the game control microcomputer 560. You may make it transmit to.

  In this embodiment, the connection confirmation signal is realized by a connection confirmation command of the payout control command, the response signal is realized by a connection OK command, the payout number signal is realized by a prize ball number command, and the acceptance signal is It is realized by a prize ball number acceptance command, a payout end signal is realized by a prize ball end command, and a payout signal is realized by a prize ball preparation command.

  32 is a block diagram showing signal lines and the like used for transmission / reception of the control signal shown in FIG. 29 and the control command shown in FIG. As shown in FIG. 32, the connection signal is output by the game control microcomputer 560 via the output circuit 67A and input to the payout control microcomputer 370 via the input circuit 373A. The prize ball information is output by the payout control microcomputer 370 via the output circuit 373B, and input to the game control microcomputer 560 via the input circuit 67B. A prize ball signal 1 and a gaming machine error state signal, which will be described later, are also output by the payout control microcomputer 370 via the output circuit 373B and input to the game control microcomputer 560 via the input circuit 67B. May be. The door opening signal may also be output by the payout control microcomputer 370 via the output circuit 373B and input to the game control microcomputer 560 via the input circuit 67B.

  Of the control commands, the connection confirmation command and the winning ball number command are output from the serial circuit 505 built in the game control microcomputer 560 and input to the serial circuit 380 built in the payout control microcomputer 370. Of the control commands, the connection OK command, the prize ball number reception command, the prize ball end command, and the prize ball preparation command are output from the serial circuit 380 built in the payout control microcomputer 370, and the game control microcomputer 560 It is input to the built-in serial circuit 505. In FIG. 32, two signal lines (signal lines for sending commands from the game control microcomputer 560 to the payout control microcomputer 370 side and payout control microcomputers) are used as signal lines for serial communication. 370 shows a signal line for transmitting a command from 370 to the game control microcomputer 560 side, but actually, the payout control command is transmitted and received through one signal line. A signal line for transmitting a command from the game control microcomputer 560 to the payout control microcomputer 370 side, and a signal line for transmitting a command from the payout control microcomputer 370 to the game control microcomputer 560 side. May be configured as separate signal lines.

  Next, transmission / reception of a payout control command between the game control microcomputer 560 and the payout control microcomputer 370 during normal operation will be described. In this embodiment, a connection confirmation command and a prize ball number command are transmitted from the game control microcomputer 560 to the payout control microcomputer 370, and the payout control microcomputer 370 is connected to the game control microcomputer 560. An OK command, a prize ball number reception command, a prize ball end command, and a prize ball preparation command are transmitted.

  FIG. 33 is a sequence diagram showing signal transmission / reception between the game control microcomputer 560 and the payout control microcomputer 370 during normal operation. As shown in FIG. 33, the game control microcomputer 560 is connected to the payout control microcomputer 370 via the serial communication circuit 505 to confirm whether or not the signal line is disconnected. A confirmation command is transmitted to the payout control microcomputer 370. When the payout control microcomputer 370 receives the connection confirmation command via the serial communication circuit 380, the payout control microcomputer 370 transmits a connection OK command to the game control microcomputer 560. When the game control microcomputer 560 receives the connection OK command, the game control microcomputer 560 transmits a connection confirmation command after 1 s (1 second) has elapsed since the reception. As long as the connection state is normal, the game control microcomputer 560 and the payout control microcomputer 370 repeatedly execute the connection confirmation communication process as described above.

  FIGS. 34 and 35 are sequence diagrams showing signal transmission / reception between the game control microcomputer 560 and the payout control microcomputer 370 during the prize ball movement. As shown in FIGS. 34 and 35, when a winning occurs and a winning ball payout operation is executed, the game control microcomputer 560 is set with data indicating the number of winning balls via the serial communication circuit 505. The prize ball number command is transmitted to the payout control microcomputer 370. In this case, the game control microcomputer 560 does not set a value indicating an error in the lower 4 bits of the received connection OK command with respect to the connection confirmation command transmitted last time (see FIG. 31), and A winning ball number command is transmitted to the payout control microcomputer 370 on the condition that the winning prize is received after the connection OK signal is received until 1 second elapses.

  Next, when the payout control microcomputer 370 receives the award ball number command, if the award ball operation can be executed immediately (that is, if the lending ball is not being dispensed and no error has occurred), the award A prize ball number reception command indicating that the number of balls has been received is transmitted to the game control microcomputer 560 via the serial communication circuit 380. If the prize ball payout is not completed within 1 s (1 second) from the time when the prize ball number acceptance command is transmitted, the prize ball is being prepared after 1 s (1 second) has elapsed since the prize ball number acceptance command is transmitted. Send a command. Thereafter, until the completion of the payout of the winning ball, the winning ball preparation command is repeatedly transmitted every 1 s (1 second) from the time when the winning ball preparation command is transmitted. Also, a payout operation for the number of prize balls specified by the prize ball number command is executed, and when the prize ball payout operation is completed, a prize ball end command indicating the end of the prize ball payout operation is played via the serial communication circuit 380. It transmits to the control microcomputer 560.

  Next, when the game control microcomputer 560 receives the prize ball end command, as shown in FIG. 34, if the number of prize balls to be paid out is not yet stored, the game ball control command 560 issues a prize ball end command. Transmission of a new connection confirmation command is resumed after 1 s (1 second) has elapsed from the time of reception. On the other hand, as shown in FIG. 35, when the number of prize balls to be paid out has already been stored, a prize ball number command for immediately specifying the next prize ball number is issued without waiting for 1 s (1 second). This is sent to the payout control microcomputer 370. In this case as well, the gaming control microcomputer 560 does not set a value indicating an error in the lower 4 bits of the previously received connection OK command or winning ball preparation command (see FIG. 31), and The award ball number command is transmitted to the payout control microcomputer 370 on the condition that the winning prize is received from the reception of the ball end command until 1 second elapses. Thereafter, transmission and reception of control commands are repeated according to the same sequence.

  FIG. 36 is a sequence diagram showing signal transmission / reception between the game control microcomputer 560 and the payout control microcomputer 370 when the winning ball operation cannot be executed immediately. Even if the payout control microcomputer 370 receives the award ball number command, if the lending ball is being paid out or is in an error state, the award ball number specified by the received award ball number command. Unable to start the prize ball payout operation. In such a case, as shown in FIG. 36, even when the payout control microcomputer 370 receives the prize ball number command, it does not immediately send the prize ball number acceptance command, and the prize ball payout operation is completed. A command for preparing a prize ball for notifying that the game has not been sent is transmitted to the game control microcomputer 560. In this case, the payout control microcomputer 370 is in a state of preparing a prize ball at regular intervals (every 1 s) unless the payout operation of the lending ball is completed and the award ball action can be started or the error is not canceled. The command is transmitted to the game control microcomputer 560.

  Next, the payout control microcomputer 370 finishes the lending ball payout operation and becomes ready to start the next prize ball operation, or when the error is canceled, the prize indicating that the number of prize balls has been received is received. The ball number acceptance command is transmitted to the game control microcomputer 560 via the serial communication circuit 380. If the prize ball payout is not completed within 1 s (1 second) from the time when the prize ball number acceptance command is transmitted, the prize ball is being prepared after 1 s (1 second) has elapsed since the prize ball number acceptance command is transmitted. Send a command. Thereafter, until the completion of the payout of the winning ball, the winning ball preparation command is repeatedly transmitted every 1 s (1 second) from the time when the winning ball preparation command is transmitted. Also, a payout operation for the number of prize balls specified by the prize ball number command is executed, and when the prize ball payout operation is completed, a prize ball end command indicating the end of the prize ball payout operation is played via the serial communication circuit 380. It transmits to the control microcomputer 560.

  FIG. 37 is a timing chart showing signal transmission / reception between the game control microcomputer 560 and the payout control microcomputer 370 during normal operation. As shown in FIG. 37, when the game control microcomputer 560 transmits the connection confirmation command to the payout control microcomputer 370, the game control microcomputer 560 receives the connection OK command transmitted from the payout control microcomputer 370. When the game control microcomputer 560 receives the connection OK command, the game control microcomputer 560 transmits the connection confirmation command again after 1 s (1 second) has elapsed since the reception. As long as the connection state is normal, the game control microcomputer 560 and the payout control microcomputer 370 repeatedly execute the connection confirmation communication process as described above.

  If there is a prize when the connection confirmation communication process is not executed (between receiving the connection OK command and transmitting the next connection confirmation command), the game control microcomputer 560 The control for repeatedly transmitting the confirmation command is interrupted, data indicating the number of winning balls is set in the lower 4 bits of the winning ball number command, and the set winning ball number command is transmitted to the payout control microcomputer 370. Upon receiving the prize ball number command, the payout control microcomputer 370 transmits a prize ball number reception command to the game control microcomputer 560. In this case, the game control microcomputer 560 performs a process of subtracting the prize ball number storage based on the reception of the prize ball number reception command (specifically, 1 is subtracted from a prize ball command output counter described later). (See step S52404). Then, the payout control microcomputer 370 pays out the number of prize balls specified by the prize ball number command, and when the prize ball payout (prize ball payout operation) is completed, the prize ball end command is sent to the game control microcomputer. Send to computer 560. As described above, when the winning ball payout operation takes a long time, the payout control microcomputer 370 waits for 1 s (1 second) until the winning ball payout operation is completed. Is sent repeatedly. When the game control microcomputer 560 receives the prize ball end command, if the number of prize balls to be paid out is not yet stored, the game control microcomputer 560 transmits a connection confirmation command after 1 s (1 second) has elapsed since the reception. To do.

  If there is a prize during the execution of the connection confirmation communication process (between sending the connection confirmation command and receiving the connection OK command), the game control microcomputer 560 and the payout control microcomputer 370 Since the connection state is not confirmed, the award ball number command is not immediately transmitted, but the process waits until the connection OK command can be confirmed. When the connection OK command is received from the payout control microcomputer 370, the game control microcomputer 560 sets data indicating the number of winning balls in the lower 4 bits of the winning ball number command, and sets the set number of winning balls. The command is transmitted to the payout control microcomputer 370. Upon receiving the prize ball number command, the payout control microcomputer 370 transmits a prize ball number reception command to the game control microcomputer 560. Then, the payout control microcomputer 370 performs the same processing, pays out the number of prize balls designated by the prize ball number command, and when the prize ball is paid out (prize ball payout operation), The ball end command is transmitted to the game control microcomputer 560.

  After receiving the winning ball end command, the gaming control microcomputer 560 does not set a value indicating an error in the lower 4 bits of the previously received connection OK command or winning ball preparation command (see FIG. 31). In addition, even when the start winning prize is received from the reception of the winning ball end command until 1 second elapses, the winning ball number command is transmitted to the payout control microcomputer 370. In other words, in this embodiment, the game control microcomputer 560 receives a prize ball end command from when a connection OK signal in which a value indicating an error is not set until one second elapses. The award ball number command can be transmitted until 1 second has elapsed.

  FIG. 38 is a timing chart showing signal transmission / reception between the game control microcomputer 560 and the payout control microcomputer 370 when an error occurs in the winning ball. As shown in FIG. 38, when the game control microcomputer 560 transmits the connection confirmation command to the payout control microcomputer 370, the game control microcomputer 560 receives the connection OK command transmitted from the payout control microcomputer 370. If there is a win when the communication process for confirming the connection is not executed, the game control microcomputer 560 sets the data indicating the number of winning balls in the lower 4 bits of the winning ball number command, and the set winning prize is set. The ball number command is transmitted to the payout control microcomputer 370. Upon receiving the prize ball number command, the payout control microcomputer 370 transmits a prize ball number reception command to the game control microcomputer 560. Then, the payout control microcomputer 370 pays out the number of prize balls specified by the prize ball number command. When executing the payout operation for the number of prize balls specified by the prize ball number command, a predetermined error (for example, an abnormal payout number error, a ball lending, a full tank, or an out of ball error) occurs. When the ball payout operation cannot be performed (abnormal state, error state), the payout control microcomputer 370 issues a prize ball preparing command for notifying that an error has occurred and the prize ball payout operation has not ended. It transmits to the game control microcomputer 560. In this case, the payout control microcomputer 370 transmits a prize ball preparing command to the game control microcomputer 560 at regular intervals (every 1 s) unless the generated error is canceled. When the predetermined error state is canceled (resolved) and the winning ball payout operation ends, the payout control microcomputer 370 transmits a winning ball end command to the game control microcomputer 560. The award ball preparation command is transmitted from the payout control microcomputer 370 to the game control microcomputer 560 every 1 s after the award ball number acceptance command is transmitted. Further, while the game control microcomputer 560 is receiving a command for preparing a prize ball, the game control microcomputer 560 is controlled not to transmit a connection confirmation command. Specifically, the payout control microcomputer 370 outputs a prize ball end command based on the completion of the prize ball payout operation, and the game control microcomputer 560 receives the prize ball end command. Based on this, control is performed so as to return to a state in which a connection confirmation command is output every predetermined period (1S).

  FIG. 39 is a timing chart showing signal transmission / reception between the game control microcomputer 560 and the payout control microcomputer 370 when a communication error occurs during connection confirmation. As shown in FIG. 39, the game control microcomputer 560 has transmitted the connection confirmation command to the payout control microcomputer 370, but has not received the connection OK command from the payout control microcomputer 370, that is, When a connection state abnormality (communication error) occurs, the connection confirmation command is transmitted again after 10 s (10 seconds) have elapsed since the connection confirmation command was transmitted. In other words, if the process of transmitting the connection confirmation command every 1 s (1 second) when the connection OK command cannot be received is continued, the number of connection confirmation command transmissions is increased even though the communication state is unstable. Since it increases in vain, the transmission interval of the connection confirmation command is extended to 10 s (10 seconds), and the control is switched to transmitting the connection confirmation command with the minimum necessary number of transmissions until the communication state is recovered. If a winning occurs when a communication error has occurred, the game control microcomputer 560 will receive a connection OK command from the payout controlling microcomputer 370, even if a new winning occurs. Without transmitting the award ball number command, the connection confirmation command is continuously transmitted at regular intervals (10 s). When the communication error is canceled (resolved) and a connection OK command is transmitted from the payout control microcomputer 370, the game control microcomputer 560 transmits a prize ball number command.

  FIG. 40 is a timing chart showing signal transmission / reception between the game control microcomputer 560 and the payout control microcomputer 370 when a communication error occurs during the award ball number notification. As shown in FIG. 40, the game control microcomputer 560 has transmitted a prize ball number command based on the occurrence of a win, but has not received a prize ball number acceptance command from the payout control microcomputer 370. In this case, that is, when a connection state abnormality (communication error) occurs, a connection confirmation command is transmitted to the payout control microcomputer 370 after 10 seconds (10 seconds) have elapsed since the prize ball number command was transmitted. Then, the connection confirmation command is repeatedly transmitted every 10 s (10 seconds) until the communication state is recovered. Thereafter, when the communication error is canceled (resolved) and the connection OK command is received from the payout control microcomputer 370, the award game control microcomputer 560 returns to the normal (normal) operation, and the number of winning balls The command is retransmitted (retryed) to the payout control microcomputer 370. Specifically, the game control microcomputer 560 does not subtract the prize ball number storage if it does not receive the prize ball number acceptance command even after sending the prize ball number command (described later). If N in step S52403, the value of the prize ball command output counter in step S52404 is not subtracted by 1), and the value of the prize ball command output counter is maintained as it is when the prize ball number command is transmitted next time. The prize ball number command is retransmitted based on that (see steps S52301 to S52035 described later).

  FIG. 41 is a flowchart showing an example of the prize ball processing in step S32. In the prize ball process, the game control microcomputer 560 (specifically, the CPU 56), the prize ball command output counter addition process (step S501), the prize ball control process (step S502), and the prize ball counter subtraction process (step S503). ).

  In the prize ball command output counter addition process, a prize ball number table shown in FIG. 42 is used. The prize ball number table is set in the ROM 54. The number of processes (in this example, “4”) is set to the start address of the prize ball number table, and then the lower address of the switch-on buffer, the prize ball command output counter, and the prize ball designation for designating the number of prize balls Data is set sequentially. The prize ball command output counter is a counter that counts the number of prizes received in the prize opening, and is set in the ROM 54, for example. The game control microcomputer 560 includes a corresponding prize ball command output counter for each number of prize balls (0 to 15). In this embodiment, the game control microcomputer 560 includes a prize ball command output counter 1 corresponding to the prize ball number “15” and prize ball command output counters 2, 3 (2) corresponding to the prize ball number “10”. Corresponding to the normal winning ports 29 and 30) and a prize ball command output counter 4 corresponding to the number of prize balls “3”. Each prize ball command output counter is counted up by prize ball command output counter addition processing, as will be described later. If the prize ball command output counter 1 set in the prize ball number table is not 0, the CPU 56 indicates the number of prize balls (15) based on the prize ball designation data for designating the number of prize balls (15). The data is set in the lower 4 bits of the prize ball number command, and the set prize ball number command is transmitted to the payout control microcomputer 370. The CPU 56 determines the number of prize balls (10) if the value of the prize ball command output counter 1 set in the prize ball number table is 0 and the value of the prize ball command output counters 2 and 3 is not 0. Is set in the lower 4 bits of the winning ball number command, and the set winning ball number command is transmitted to the payout control microcomputer 370. To do. Further, the CPU 56 determines that the values of the prize ball command output counter 1 and the prize ball command output counters 2 and 3 set in the prize ball number table are 0 and the value of the prize ball command output counter 4 is not 0. Based on the prize ball designation data for designating the number of prize balls (3), data indicating the number of prize balls (3) is set in the lower 4 bits of the prize ball number command, and the set prize ball number command is issued. It transmits to the control microcomputer 370. In FIG. 42, the switch-on buffer 1 corresponds to the input port 0, and the switch-on buffer 2 corresponds to the input port 2.

  FIG. 43 is a flowchart showing the prize ball command output counter addition processing in step S501. In the prize ball command output counter addition process, the game control microcomputer 560 (specifically, the CPU 56) sets the start address of the prize ball number table as a pointer (step S5101). Then, the data at the address pointed to by the pointer (in this case, the number of processes) is loaded (step S5102).

  Next, the CPU 56 increments the pointer value by 1 (step S5103), loads the lower address of the switch-on buffer pointed to by the pointer into the lower byte of the pointer buffer (step S5104), and loads the switch-on buffer pointed by the pointer buffer into the register. (Step S5105). Next, the CPU 56 increments the value of the pointer by 1 (step S5106), and loads the lower address of the prize ball command output counter pointed to by the pointer into the lower byte of the pointer buffer (step S5107). Next, the CPU 56 increments the value of the pointer by 1 (step S5108), and calculates the logical product of the contents of the switch-on buffer loaded in the register and the prize ball designation data pointed to by the pointer (step S5109).

  If the calculation result in step S5109 is 0 (Y in step S5110), that is, if the detection signal of the switch to be inspected is not on, the number of processes is reduced by 1 (step S5114), and if the number of processes is 0 The process ends, and if the number of processes is not 0, the process returns to step S5103 (step S5115).

  If the calculation result in step S5109 is not 0 (N in step S5110), that is, if the detection signal of the switch to be inspected is on, the CPU 56 adds 1 to the value of the prize ball command output counter pointed to by the pointer. (Step S111). However, when a carry occurs in the value of the prize ball command output counter as a result of the addition, the CPU 56 subtracts 1 from the value of the prize ball command output counter and restores the original value (steps S5112, S5113). Then, the process proceeds to step S5113.

  FIG. 44 is a flowchart showing the prize ball control process in step S502. In the prize ball control process, the game control microcomputer 560 (specifically, the CPU 56) executes any one of steps S521 to S525 in accordance with the value of the prize ball process code.

  FIG. 45 is a flowchart showing the prize ball transmission process 1 (step S521) executed when the value of the prize ball process code is zero. In the prize ball transmission process 1, the CPU 56 performs control to transmit a connection confirmation command to the payout control microcomputer (step S5211). Specifically, the CPU 56 performs processing for outputting a connection confirmation command to the transmission data register of the serial communication circuit 505. Then, the CPU 56 sets a value “1” indicating a prize ball connection confirmation process in the prize ball process code (step S5212), and sets a connection confirmation time 2 (for example, 10 seconds) in the prize ball process timer (step S5213). . If a connection OK command is not received even after 10 seconds have elapsed after transmitting the connection confirmation command based on the connection confirmation time 2 set in step S5213, the connection confirmation command is transmitted thereafter. It is controlled so as to extend the interval to 10 seconds. Specifically, the prize ball process timer set in step S5213 is measured in the processing of steps S5227 and S5229, which will be described later, 10 seconds elapses without receiving a connection OK command, and Y in step S5227. When the determination is made, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S5228 and S5211).

  The prize ball process timer is set to a value (for example, an integer multiple of the interrupt period) in consideration of the interrupt period in the timer interrupt process executed by the game control microcomputer 560. This is because other timers used in the game control microcomputer 560, the payout control microcomputer 370, and the effect control microcomputer 100 (for example, a main control communication control timer, a payout control timer, a re-payout waiting timer, The same applies to the prize ball information output timer and prize ball signal 1 output timer.

  FIG. 46 is a flowchart showing a prize ball connection confirmation process (step S522) executed when the value of the prize ball process code is 1. In the winning ball connection confirmation process, the CPU 56 first confirms whether there is data in the reception data register of the serial communication circuit 505 (step S5221). Specifically, the CPU 56 may confirm the value of bit 5 of the status register A of the serial communication circuit 505 (see FIG. 20). If there is no data in the reception data register (that is, if no command is received), the process proceeds to step S5227.

  If there is data in the reception data register (that is, if a command is received), the CPU 56 checks whether an error has occurred in the serial communication circuit 505 (step S5222). Specifically, the CPU 56 may confirm whether or not any error bit value of bits 0 to 4 of the status register A of the serial communication circuit 505 is set (see FIG. 20). If an error has occurred, the process proceeds to step S5227.

  If no error has occurred in the serial communication circuit 505, the CPU 56 reads the command from the reception data register of the serial communication circuit 505, and checks whether the received command is a connection OK command (step S5223). If it is not a connection OK command, the process proceeds to step S5227.

  If the connection OK command has been received, the CPU 56 stores the error information (see FIG. 31) set in the lower 4 bits of the connection OK command in the frame state display buffer (step S5224).

  Next, the CPU 56 sets a value “2” indicating the prize ball transmission process 2 in the prize ball process code (step S5225), and sets a connection confirmation time 1 (for example, 1 second) in the prize ball process timer (step S5226). . Note that, based on the connection confirmation time 1 set in step S5226, control is performed to repeatedly transmit the next connection confirmation command every time one second elapses after reception of the connection OK command. Specifically, the prize ball process timer set in step S5226 is measured in the processing of steps S52313 and S52315, which will be described later, and one second elapses without sending a prize ball number command, and Y in step S52313. If it is determined, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S52314 and S5211).

  In step S5227, the CPU 56 checks whether or not the prize ball process timer has timed out. If the winning ball process timer has timed out (that is, if the connection OK command has not been received even after 10 seconds have passed after sending the connection confirmation command), the CPU 56 sends a winning ball to the winning ball process code. A value “0” indicating the process 1 is set (step S5228), and the process ends. If the winning ball process timer has not timed out, the CPU 56 subtracts 1 from the value of the winning ball process timer (step S5229).

  FIG. 47 is a flowchart showing the prize ball transmission process 2 (step S523) executed when the value of the prize ball process code is 2. In the prize ball transmission process 2, the CPU 56 checks whether or not any prize ball command output counters 1 to 4 have a count value other than 0 (step S52301). If there is no count value other than 0, the process proceeds to step S52313.

  If any of the prize ball command output counters 1 to 4 has a count value other than 0 (that is, if the count value is 1 or more), the CPU 56 loads the contents of the frame state display buffer. Then, it is confirmed whether or not the content of the frame state display buffer is 0 (step S5232). If the content of the frame state display buffer is not 0, the processing is terminated as it is. By performing such control, when the connection OK command in which the error information is set is received and the payout control microcomputer 370 is controlled to be in the payout stop state, the process does not proceed to step S52303 and subsequent steps. Then, control is made so that transmission of the prize ball number command is suspended.

  If the contents of the frame state display buffer are 0 (that is, if no error relating to payout has occurred), the payout control CPU 371 determines the number of prize balls corresponding to the prize ball command output counter whose count value is not 0. It is set in the buffer (step S52303). Specifically, in step S52301, the CPU 56 first checks whether or not the count value of the prize ball command output counter 1 is zero. If the count value of the prize ball command output counter 1 is 1 or more, in step S52303, the CPU 56 sets 15 prize balls in the number buffer. In step S52301, if the count value of the prize ball command output counter 1 is 0, the CPU 56 checks whether the count values of the prize ball command output counters 2 and 3 are 0 or not. If the count value of the prize ball command output counters 2 and 3 is 1 or more, the CPU 56 sets the number of prize balls in the number buffer in step S52303. In step S52301, if the count value of the prize ball command output counters 2 and 3 is also 0, the CPU 56 checks whether the count value of the prize ball command output counter 4 is 0 or not. If the count value of the prize ball command output counter 4 is 1 or more, in step S52303, the CPU 56 sets the number of prize balls to 3 in the number buffer.

  In addition, the CPU 56 sets the number of prize balls corresponding to the prize ball command output counter whose count value is not 0 in the prize ball number command (step S52304), and uses the prize ball number command in which the number of prize balls is set for payout control. Control to transmit to the microcomputer 370 is performed (step S52305). Specifically, the CPU 56 performs a process of outputting a prize ball number command in which the prize ball number is set to the transmission data register of the serial communication circuit 505.

  By executing the processing of steps S52301 and S52305, in this embodiment, if there is a prize ball command output counter whose count value is not 0 regardless of the connection confirmation command transmission timing (ie, If there is a prize ball number storage and a predetermined payout condition is established), a prize ball number command is transmitted to the payout control microcomputer 370.

  Then, the CPU 56 sets a value “3” indicating the prize ball reception confirmation process in the prize ball process code (step S52306), and sets a connection confirmation time 2 (for example, 10 seconds) in the prize ball process timer (step S52307). . It should be noted that, based on the connection confirmation time 2 set in step S52307, after transmitting the prize ball number command, it is confirmed whether a prize ball number acceptance command or a prize ball preparation command is received within 10 seconds. . Specifically, the prize ball process timer set in step S52307 is measured in steps S52409 and S52411 described later, and 10 seconds have elapsed without receiving a prize ball number acceptance command or a prize ball preparation command. If it is timed out and it is determined as Y in step S52409, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S52410 and S5211).

  If the prize ball number command is transmitted in step S52305 by executing the process of step S52306, the process proceeds to the prize ball reception confirmation process without returning to the prize ball transmission process 1 including the connection confirmation command transmission process. Is done. Therefore, in this embodiment, the process of repeatedly transmitting the connection confirmation command is executed every predetermined time (for example, 1 second) until the prize ball number command is transmitted, but the prize ball number command is transmitted. In particular, the control for transmitting the connection confirmation command is stopped (more specifically, after the prize ball number command is transmitted, the process proceeds to the prize ball end confirmation process by receiving the prize ball number acceptance command described later. (See steps S52403 to S52405) or by receiving the winning ball preparation command and repeating the winning ball receipt confirmation process (see steps S52406 to S52408), without returning to the winning ball transmission process 1 In this case, the control for sending the confirmation command is stopped. Unless an abnormal state occurs in which no payout control command is returned, after the prize ball number command is transmitted, the game control microcomputer 560 is connected until the prize ball payout operation is finished and the prize ball end command is received. A confirmation command is never sent.

  Next, the CPU 56 adds the value of the number buffer set in step S52303 to the prize ball number counter (step S52308), and whether or not the added count value is equal to or greater than a predetermined prize ball shortage determination value (eg, 501). Is confirmed (step S52309). In this embodiment, the prize ball number counter is a counter used for grasping the number of prize balls that have not been paid out on the game control microcomputer 560 side, and when the prize ball number command is transmitted, The number of prize balls designated in (1) is added, and every time ten prize balls are paid out, 10 is subtracted based on the prize ball information output from the payout control microcomputer 370. Further, as described above, the prize ball number counter is set to “250” as an initial value in the initial setting process of the main process. When the count value of the prize ball counter reaches a predetermined prize ball shortage determination value (for example, 501) or more, the number of prize balls that have not been paid out is excessively large. Can be determined. Further, when the count value of the prize ball number counter is less than a predetermined prize ball excess determination value (for example, 0), an abnormally large number of game balls are paid out in excess of the number to be paid out originally. Therefore, it can be determined that an excessive number of prize balls has occurred.

  In this embodiment, the prize ball number counter is added (see step S52308) immediately after the prize ball number command is transmitted (see step S52305). However, the prize ball number command is transmitted. For example, a prize ball number command may be transmitted immediately after the addition process of the prize ball number counter is executed.

  When it is determined that there is a shortage of prize balls, the signal line for outputting the prize ball information is disconnected in addition to the case where some trouble occurs on the payout control microcomputer 370 side and the payout operation cannot be performed normally. A case is also conceivable. On the other hand, when it is determined that the number of prize balls is excessive, a prize ball number command is transmitted in addition to the case where some kind of trouble occurs on the payout control microcomputer 370 side and the payout operation is performed more than necessary. It is also conceivable that some injustice is applied to the command line and the award ball number command is illegally input to the payout control microcomputer 370.

  When the count value of the prize ball number counter is equal to or greater than a predetermined prize ball shortage determination value (for example, 501), the CPU 56 displays a prize ball error flag indicating that a prize ball shortage or a prize ball excess has occurred. It is confirmed whether it has already been set (step S52310). If the prize ball error flag has already been set, the process is terminated. If the prize ball error flag is not set, the CPU 56 sets a prize ball error flag (step S52311) and controls to send a prize ball shortage error command to the effect control microcomputer 100 (step S52312). Specifically, the CPU 56 performs a process of setting the address of the winning ball shortage error command transmission table as a pointer. Then, based on the fact that the address of the winning ball shortage error command transmission table is set in the pointer in step S52312, in the effect symbol command control processing in step S30, the serial communication circuit of the transmission / reception channel with the effect control board 80 is performed. A prize ball shortage error command is output to the transmission data register 505, and the prize ball shortage error command is transmitted to the production control microcomputer 100. Note that once the prize ball error flag is set, it is maintained without being cleared until the power supply to the gaming machine is turned on again after the power supply to the gaming machine is stopped. In this embodiment, regarding the communication between the game control microcomputer 560 and the effect control microcomputer 100, a command is transmitted from the game control microcomputer 560 to the effect control microcomputer 100. Only, not the other way around. Therefore, the game control microcomputer 560 may be equipped with a transmission-only serial communication circuit for communication with the effect control microcomputer 100.

  In this embodiment, based on the reception of a prize ball shortage error command or a prize ball excess error command described later, the effect control microcomputer 100 performs an error notification of prize ball shortage or prize ball excess. However, the error notification of insufficient prize balls or excessive prize balls may be recovered when a predetermined period has elapsed from the start of notification. Further, for example, when the value of the prize ball number counter returns to a range of a predetermined prize ball shortage determination value (for example, 501) or a predetermined prize ball excess determination value (for example, 0), the prize ball shortage or the prize ball is excessive. It is also possible to recover from the error notification.

  In this embodiment, the case where the prize ball number is added to the prize ball number counter at the timing at which the prize ball number command is transmitted in step S52308 is shown. For example, the number of prize balls may be subtracted instead of the one shown in the embodiment. In this case, for example, in the process of step S5311 to be described later, on the contrary, 10 may be added to the value of the winning ball counter based on the input of winning ball information. In the process of step S52309, if the value of the prize ball number counter is less than 0, it is determined that there is a prize ball shortage error. In the process of step S5312 described later, if the value of the prize ball number counter is 501 or more, a prize ball What is necessary is just to determine with an excess error.

  In step S52313, the CPU 56 checks whether or not the prize ball process timer has timed out. If the winning ball process timer has timed out (that is, if no winning ball has been stored and no new winning has occurred by the time one second has elapsed after receiving the connection OK command), the CPU 56 Then, the value “0” indicating the prize ball transmission process 1 is set in the prize ball process code (step S52314), and the process ends. If the winning ball process timer has not timed out, the CPU 56 subtracts 1 from the value of the winning ball process timer (step S52315).

  FIG. 48 is a flowchart showing the winning ball reception confirmation process (step S524) executed when the value of the winning ball process code is 3. In the winning ball receipt confirmation process, the CPU 56 first checks whether or not there is data in the reception data register of the serial communication circuit 505 (step S52401). Specifically, the CPU 56 may confirm the value of bit 5 of the status register A of the serial communication circuit 505 (see FIG. 20). If there is no data in the reception data register (that is, if no command is received), the process proceeds to step S52409.

  If there is data in the reception data register (that is, if a command is received), the CPU 56 checks whether or not an error has occurred in the serial communication circuit 505 (step S52402). Specifically, the CPU 56 may confirm whether or not any error bit value of bits 0 to 4 of the status register A of the serial communication circuit 505 is set (see FIG. 20). If an error has occurred, the process proceeds to step S52409.

  If no error has occurred in the serial communication circuit 505, the CPU 56 reads the command from the reception data register of the serial communication circuit 505, and checks whether or not the received command is a prize ball number acceptance command (step S52403). . If the winning ball number reception command has been received, the CPU 56 subtracts 1 from the value of the winning ball command output counter corresponding to the winning ball number set by the transmitted winning ball number command (step S52404). In addition, the CPU 56 sets a value “4” indicating a prize ball end confirmation process in the prize ball process code (step S52405), and proceeds to step S52408.

  If the received command is not a prize ball number acceptance command, the CPU 56 checks whether or not the received command is a prize ball preparation command (step S52406). If it is not a prize ball preparation command, the process advances to step S52409.

  If the winning ball preparation command has been received, the CPU 56 stores the error information (see FIG. 31) set in the lower 4 bits of the winning ball preparation command in the frame state display buffer (step S52407). Then, the CPU 56 sets the connection confirmation time 2 (for example, 10 seconds) in the prize ball process timer (step S52408). In addition, after receiving the prize ball preparation command based on the connection confirmation time 2 set in step S52408, neither the prize ball number acceptance command nor the next prize ball preparation command can be received after 10 seconds. If it is, the process returns to the control for transmitting the connection confirmation command. Specifically, the prize ball process timer set in step S52408 is measured in the processing of steps S52409 and S52411 described later, and 10 seconds are received without receiving a prize ball number acceptance command or a next prize ball preparation command. If time elapses and it is determined as Y in step S52409, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S52410 and S5211).

  In step S52409, the CPU 56 checks whether or not the prize ball process timer has timed out. If the prize ball process timer has timed out (that is, if no prize ball number acceptance command or prize ball preparation command is received after 10 seconds have passed since the prize ball number command was transmitted), the CPU 56 Then, the value “0” indicating the prize ball transmission process 1 is set in the prize ball process code (step S52410), and the process ends. If the winning ball process timer has not timed out, the CPU 56 subtracts 1 from the value of the winning ball process timer (step S52411).

  FIG. 49 is a flowchart showing the winning ball end confirmation process (step S525) executed when the value of the winning ball process code is 4. In the winning ball end confirmation process, the CPU 56 first confirms whether or not there is data in the reception data register of the serial communication circuit 505 (step S52501). Specifically, the CPU 56 may confirm the value of bit 5 of the status register A of the serial communication circuit 505 (see FIG. 20). If there is no data in the reception data register (that is, if no command is received), the process proceeds to step S52509.

  If there is data in the reception data register (that is, if a command is received), the CPU 56 checks whether an error has occurred in the serial communication circuit 505 (step S52502). Specifically, the CPU 56 may confirm whether or not any error bit value of bits 0 to 4 of the status register A of the serial communication circuit 505 is set (see FIG. 20). If an error has occurred, the process proceeds to step S52509.

  If no error has occurred in the serial communication circuit 505, the CPU 56 reads the command from the reception data register of the serial communication circuit 505, and checks whether the received command is a prize ball end command (step S52503). If the winning ball end command has been received, the CPU 56 sets a value “2” indicating the winning ball transmission process 2 in the winning ball process code (step S52504), and the connection check time 1 (for example, 1) is set in the winning ball process timer. Second) is set (step S52505). It should be noted that, based on the connection confirmation time 1 set in step S52505, the control for transmitting the connection confirmation command when the start winning prize does not occur even after one second has elapsed after receiving the prize ball end command. Return to. Specifically, the prize ball process timer set in step S52505 is measured by the processing in steps S52313 and S52315, and one second has elapsed without sending a prize ball number command without generating a new start prize. If time-out occurs and it is determined as Y in step S52313, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S52314 and S5211).

  Since the process of step S52504 is executed, when a prize ball end command is received, the process first proceeds to prize ball transmission process 2. Therefore, when the number of prize balls is stored, the next is immediately performed. Control is performed so that a winning ball number command is transmitted. On the other hand, after the transition to the prize ball transmission process 2, there is no memorized number of prize balls, and a new prize is also generated until the connection confirmation time 1 (for example, 1 second) set in step S52505 has elapsed. If not, the process further proceeds to a prize ball transmission process 1, and the process of repeatedly transmitting the connection confirmation command is resumed.

  If the received command is not a prize ball end command, the CPU 56 checks whether or not the received command is a prize ball preparation command (step S52506). If it is not a prize ball preparation command, the process advances to step S52509.

  If the winning ball preparation command has been received, the CPU 56 stores the error information (see FIG. 31) set in the lower 4 bits of the winning ball preparation command in the frame state display buffer (step S52507). Then, the CPU 56 sets the connection confirmation time 2 (for example, 10 seconds) in the prize ball process timer (step S52508). In addition, after receiving the winning ball preparation command based on the connection confirmation time 2 set in step S52508, neither the winning ball end command nor the next winning ball preparation command could be received after 10 seconds. In this case, the process returns to the control for transmitting the connection confirmation command. Specifically, the prize ball process timer set in step S52508 is measured in the processing of steps S52509 and S52511 described later, and 10 seconds have elapsed without receiving a prize ball end command or a next prize ball preparation command. If time is out and it is determined as Y in step S52509, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S52510 and S5211).

  In step S52509, the CPU 56 checks whether or not the prize ball process timer has timed out. If the prize ball process timer has timed out (that is, the prize ball end command or the prize ball preparation command cannot be received even after 10 seconds have passed since the prize ball number acceptance command or prize ball preparation command is received) In this case, the CPU 56 sets a value “0” indicating the prize ball transmission process 1 in the prize ball process code (step S52510), and ends the process. If the winning ball process timer has not timed out, the CPU 56 subtracts 1 from the value of the winning ball process timer (step S52511).

  FIG. 50 is a flowchart showing the prize ball counter subtraction process in step S503. In the prize ball counter subtraction process, the CPU 56 first checks whether or not the prize ball information input invalid timer has timed out (step S5301). The prize ball information input invalid timer is a timer that is measured in order to provide an interval period after confirming the input of prize ball information until confirming the input of the next prize ball information. If not timed out, the CPU 56 subtracts 1 from the value of the prize ball information input invalid timer (step S5302) and ends the process.

  If the prize ball information input invalid timer has timed out, the CPU 56 inputs the contents of the input port 0 (step S5303), and checks whether or not the bit of the prize ball information is on (step S5304). If the bit of the prize ball information is on, the process proceeds to step S5305.

  In step S5305, the CPU 56 sets a predetermined prize ball information confirmation count (for example, 8) as the number of processes (step S5305). Then, the CPU 56 confirms whether or not the prize ball information is input, and if the input of the prize ball information can be confirmed, the CPU 56 adds the value of the prize ball information on counter to 1 and the number of processes (8 in this example). The process is repeated until the process is completed (steps S5306 to S5308).

  Next, the CPU 56 checks whether or not the value of the prize ball information on counter is 6 or more (step S5309). If the value of the winning ball information on counter is 6 or more, the CPU 56 sets a predetermined time (for example, 0.8 seconds) in the winning ball information input invalid timer (step S5310) and sets the value of the winning ball number counter to 10 Subtraction is performed (step S5311).

  By executing the above processing, in this embodiment, it is determined that the prize ball information has been inputted on the condition that the prize ball information has been inputted 6 times or more out of the 8 confirmation processes, and 10 pieces of prize ball information are entered. The value of the prize ball number counter is decremented by 10 assuming that the prize ball has been paid out. By such processing, in this embodiment, the situation where it is determined that the prize ball information is erroneously input is reduced, and the game control microcomputer 560 side cannot properly grasp the number of prize balls that have not been paid out. It is preventing.

  Next, the CPU 56 checks whether or not the count value after subtraction is less than a predetermined prize ball excess determination value (for example, 0) (step S5312). When the count value of the prize ball number counter is less than a predetermined prize ball excess determination value (for example, 0), the CPU 56 checks whether or not the prize ball error flag is already set (step S5313). If the prize ball error flag has already been set, the process is terminated. If the prize ball error flag is not set, the CPU 56 sets the prize ball error flag (step S5314) and controls to send a prize ball excess error command to the effect control microcomputer 100 (step S5315). Specifically, the CPU 56 performs a process of setting the address of the winning ball excessive error command transmission table as a pointer. Then, based on the fact that the address of the winning ball excess error command transmission table is set in the pointer in step S5315, in the effect symbol command control process in step S30, the serial communication circuit of the transmission / reception channel with the effect control board 80 is performed. The award ball excessive error command is output to the transmission data register 505, and the award ball excessive error command is transmitted to the production control microcomputer 100.

  Next, the frame state output process (step S39) will be described. FIG. 51 is a flowchart showing an example of the frame state output process in step S39. In the frame state output process, the CPU 56 first loads the contents of the frame state display buffer (step S391). Next, the CPU 56 inputs the content of the input port 0 (step S392) and logically ANDs the input port 0 content with a predetermined door opening signal confirmation mask value (specifically 01000000). (Step S393). Further, the CPU 56 calculates the logical product of the operation result obtained by the logical product and the contents of the frame state display buffer loaded in step S391 (step S394). By executing the above processing, a calculation result is obtained in which the door opening signal input state is further added to the contents of the frame state display buffer.

  Next, the CPU 56 compares the calculation result with the contents of the previous frame state display buffer (step S395). The previous frame state display buffer stores the calculation result of step S394 calculated when the frame state output processing is executed by the previous timer interrupt. When the calculation result is different from the content of the previous frame state display buffer (Y in step S396), the CPU 56 stores the calculation result calculated in step S394 in the previous frame state display buffer and updates the previous frame state display buffer. Along with (Step S397), the calculation result calculated in Step S394 is set as it is to the frame state display command, and control is performed to transmit the frame state display command to the effect control microcomputer 100 (Step S398). Specifically, the CPU 56 performs processing for setting the address of the frame state display command transmission table in the pointer. Then, based on the fact that the address of the frame state display command transmission table is set in the pointer in step S398, in the effect symbol command control processing in step S30, the serial communication circuit 505 for the channel for transmission / reception with the effect control board 80 is performed. The frame state display command is output to the transmission data register, and the frame state display command is transmitted to the production control microcomputer 100.

  By executing the above processing, the error information set by the connection OK command or the winning ball preparation command from the payout control microcomputer 560 (payout number error error, out of ball error, full tank error, winning ball error) And the input state of the door opening signal are set in the frame state display command and transmitted to the production control microcomputer 100.

  In addition, the CPU 56 determines whether or not the door opening signal is in the ON state when the door opening signal is ON based on the state of the door opening signal specified by the processing in steps S391 to S393 (step S398a). Here, the door opening signal transmitted from the door opening switch 155a or the door opening switch 155b and inputted to the input port of the game control microcomputer 560 is that either one or both of the glass door frame 2 and the mechanism plate are opened. Either when the door opening switch 155a detects that the game frame 11 is open, or when the door opening switch 155b detects that the game frame 11 is open to the outer frame 2A. When one or both, it is in the on state.

  When the door is being opened (Y in step S398a), it is determined whether or not the setting for outputting the gaming machine specific information has been executed (step S398b). For example, when the unique information output request flag is on, or when a valid address is set in the unique information read pointer, it may be determined that the output setting of the gaming machine unique information has been completed. When the output setting of the gaming machine specific information has not been completed (N in step S398b), the setting for outputting the gaming machine specific information to the outside is performed (step S398c). For example, the CPU 56 may perform setting for externally outputting the gaming machine unique information by setting the unique information output request flag or setting the reading start address of the gaming machine unique information in the unique information read pointer. .

  By setting the output of the gaming machine specific information in the process of step S398c, the opening of the glass door frame 2, the mechanism plate or the gaming frame 11 is detected based on the door opening signal from the door opening switch 155a or the door opening switch 155b. When this is done, the game machine specific information can be output to the external device, assuming that the information output condition is satisfied. Door opening signals from the door opening switch 155a and the door opening switch 155b are output to an external device via the backup power supply circuit 508, the terminal board 160, and the like. Therefore, when the gaming machine specific information is output to the external device based on the setting in step S398c, the door open signal that is in the ON state is sent to the external device as a state signal indicating that the door or the like is open. Is output.

  Even when the door is open, if it is determined that the output setting of the gaming machine specific information has been completed (Y in step S398b), a restriction is set not to perform the setting for newly outputting the gaming machine specific information to the outside. (Restrict. As a result, when external output of gaming machine specific information is performed based on the establishment of other information output conditions, the output setting of gaming machine specific information based on the establishment of information output conditions when the door is opened is duplicated. Therefore, it is possible to prevent the gaming machine specific information that has been output by the serial signal method so far from being interrupted before the external output is completed. That is, after external output of gaming machine specific information is once started based on output settings, the output of new gaming machine specific information is restricted (restricted) until the output is completed, and the current output state is maintained. . Thus, by avoiding conflicting output settings and maintaining the current output state so as not to interrupt the gaming machine specific information, the gaming machine specific information can be reliably output to an external device such as a hall computer. Unauthorized acts such as changing the chip of the control microcomputer 560 or replacing the main board 31 can be properly detected.

  Next, the special symbol process (step S28) in the 4ms timer interrupt process will be described. FIG. 52 is a flowchart showing an example of a special symbol process processing program executed by the CPU 56 of the game control microcomputer 560. The CPU 56 of the game control microcomputer 560 has the start opening switch 14a for detecting that the game ball has won the start winning opening 14 provided in the game board 6 being turned on, that is, the game ball is starting start winning. If a winning is received at the opening 14 and the winning detection signal SS is input from the start opening switch 14a (step S311), after the start opening switch passing process (step S312) is performed, the processing of steps S300 to S306 is performed according to the internal state. Do one of these processes.

  Special symbol normal processing (step S300): A state in which variable symbol special display can be started (for example, the symbol variation has not been made in the special symbol display 8, and the previous symbol variation in the special symbol display 8 has been completed. Waits for a predetermined period of time to elapse, and not a big hit game). When the special symbol variable display can be started, the start winning memory number for the special symbol is confirmed. If the start winning memorization number is not 0, it is determined based on the random number value generated by the random number circuit 503 stored in the special figure holding memory whether or not the result of variable symbol special display is a big hit. Further, when it is determined to be a big hit, control for transmitting a display result designation command capable of specifying the determined display result to the microcomputer 100 for effect control is further determined, such as whether or not to make a probable big hit. I do. Then, the internal state (special symbol process flag) is updated so as to shift to step S301.

  Variation pattern setting process (step S301): A variation pattern is determined, and a variation time in the variation pattern (variable display time: time from the start of variable display until the display result is derived and displayed (stop display)) is a special symbol. It is determined to be a variable display variable time. In addition, control is performed to transmit a variation pattern command specifying the determined variation pattern to the effect control microcomputer 100, and a variation time timer for measuring the variation time of the determined special symbol is started. Then, the internal state (special symbol process flag) is updated so as to shift to step S302.

  Special symbol variation processing (step S302): When a predetermined time (the time indicated by the variation time timer in step S301) elapses, the internal state (special symbol process flag) is updated to shift to step S303.

  Special symbol stop process (step S303): An effect symbol stop command for instructing stop of the effect symbol is transmitted to the effect control board 80. Moreover, the special symbol in the special symbol display 8 is stopped. If the stop symbol of the special symbol is a jackpot symbol, the internal state (special symbol process flag) is updated to shift to step S304. If not, the internal state is updated to shift to step S300. In addition, it is good also as a structure which does not transmit an effect design stop command. In this case, the effect control board 80 sets the change time to the change time timer based on the change pattern command received from the main board 31 and updates the change time timer to uniquely change the change time of the effect symbol. Monitoring, and when it is determined that the fluctuation time has elapsed, a process of stopping the effect design may be performed.

  Pre-hit opening process (step S304): Control for opening the big winning opening in the big hit gaming state is started. Specifically, a counter (for example, a counter that counts the number of game balls that have entered the grand prize opening) and a flag (a flag used when detecting winning in the prize opening) are initialized, and the solenoid 21 is driven. Open the big prize opening. Also, the execution time of the big hit release processing is set by the process timer, and the big hit flag is set. Then, the internal state (special symbol process flag) is updated so as to shift to step S305.

  Process during opening of big hit (step S305): control for sending the effect control command of the grand prize opening round display to the effect control board 80 and closing conditions of the big prize opening (for example, a predetermined number (for example, 10) in the big prize opening) A process for confirming that the game ball has won) is performed. When the closing condition for the big prize opening is satisfied, if there are still rounds, the internal state is updated to shift to step S304. When all the rounds have been completed, the internal state is updated to shift to step S306.

  Big hit end processing (step S306): Control for causing the effect control means to perform display control for notifying the player that the big hit gaming state has ended. Then, the internal state is updated so as to shift to step S300.

  Small-hit processing (step S307): Control is performed in which the big winning opening is opened and closed in the small-hit gaming state. Specifically, the execution time of the small hit processing is set by the process timer, and the small hit processing is repeatedly executed until the process timer times out. If the closing condition for the big prize opening is established, the small winning time process is repeatedly executed when the big winning opening is opened again. Further, when the number of times the special winning opening is opened reaches a predetermined number (for example, “2”, etc.), the internal state is updated to shift to step S300.

  FIG. 53 is a flowchart showing the start port switch passage processing (step S312). In the start-port switch passing process, the CPU 56 of the game control microcomputer 560 sets the start-winning memory number indicated by the start-winning memory counter (or the start-winning memory number stored in the special figure holding memory) to 4 which is the maximum value. It is confirmed whether it has reached (step S321). If the start winning memory number has not reached 4, the CPU 56 reads the numerical data stored as the random number value from the random value memory circuit of the random number circuit 503 (step S322). Further, the CPU 56 stores the read numerical data as it is, or after performing a predetermined processing, as a storage area (special number corresponding to the value of the start winning memory number as a random value MR1 for determining the special figure display result) It is stored in the symbol determination buffer (special symbol holding memory) (step S323). In this embodiment, the random number circuit 503 inputs an input signal from the start port switch 14a as a latch signal. In this case, the random number circuit 503 latches the counter value of the counter built in the random number circuit 503 in the random value storage circuit (latch circuit) at the timing when the input signal is input from the start port switch 14a. In step S322, the CPU 56 reads the value latched in the random value storage circuit of the random number circuit 503.

  When the random number circuit 503 is configured so that a new count value cannot be latched in the latch circuit even if a latch signal is output unless the count value latched in the random number value storage circuit (latch circuit) is read. As long as it is determined in step S321 that the starting prize storage number has reached the maximum value 4, the count value is not read from the latch circuit, and the new count value is not latched by the latch circuit. Therefore, even if the start winning memorized number is less than 4 and step S322 is executed and the count value is read out from the latch circuit, the old count value latched at a timing other than the original latch timing is read out. Thus, there is a risk that processing such as jackpot determination will be performed using a random number value based on the old count value. Therefore, when the random number circuit 503 is configured so that a new count value cannot be latched unless the count value latched by the latch circuit is read, even if it is determined as N in step S321 (start winning memory) Even if the number is less than 4, the process of step S322 may be executed to read the count value latched in the latch circuit (however, steps S323 to S325 are not executed). By doing so, it is possible to prevent a situation in which processing such as jackpot determination is performed using a random number value based on an old count value latched at a timing other than the original latch timing.

  Next, the CPU 56 sets the random value stored in the predetermined buffer area at the head of the empty entry in the special figure reservation memory (step S324). At this time, the random number value read from the predetermined buffer area is used as it is as the random number value MR1 for determining the special figure display result, or the special figure display generated by executing the predetermined processing using the read random number value. A random number MR1 for determining the result may be set in the special figure holding memory. The random value set in the special figure holding memory may include, for example, the random value MR2 for determining the jackpot type in addition to the random value MR1 for determining the special figure display result. Thereafter, the start winning memory number is increased by 1 by adding 1 to the count of the start winning counter (step S325).

  Note that if the start winning memorization is stored in step S321 but the maximum value of 4 is reached, the start port switch passing process is terminated as it is.

  Next, the special symbol normal process (step S300) in the special symbol process will be described. In this embodiment, when the start condition that allows the variable symbol display to start is satisfied, it is determined whether or not the special symbol display result, which is the variable symbol display result of the special symbol, is “big hit”. It is determined whether or not the figure display result is “small hit”. When it is determined that the special figure display result is “big hit”, the big hit type is determined as one of a plurality of types such as “15R uncertain change”, “15R probability change”, and “2R sudden change”. FIG. 54A shows a special symbol display result determination table 200 used in the special symbol normal processing, and FIG. 54B shows a jackpot type determination table 201 used in the special symbol normal processing. The special figure display result determination table 200 and the jackpot type determination table 201 may be stored in a predetermined area of the ROM 54 in advance.

  The special figure display result determination table 200 determines whether the special figure display result is “big hit”, “small hit”, or “lost” based on numerical data indicating the random value MR1 for determining the special figure display result. This is a table that is referred to in order to determine (predetermined) a fixed special symbol that is a variable display result in a special figure game before it is derived and displayed. The random number value MR1 for determining the special figure display result is generated, for example, by using the random number generated by the random number circuit 503b as it is or by applying a predetermined processing to the random number generated by the random number circuit 503b. What should I do? In this embodiment, it is assumed that the random number value MR1 for determining the special figure display result takes a value in the range of “0” to “65535”.

  In the special figure display result determination table 200, a numerical value to be compared with the random number value MR1 for determining the special figure display result depending on whether the gaming state in the pachinko gaming machine 1 is a normal state, a short time state, or a probable variation state. (Determined value) is assigned to the special figure display results of “big hit”, “small hit”, and “losing”. The CPU 56 compares the numerical data indicating the random number value MR1 for determining the special figure display result with the determined value, and specifies the special figure display result to which the determined value matching the random value MR1 is assigned. It is only necessary to determine whether the result is “big hit”, “small hit”, or “losing”.

  The big hit type determination table 201 indicates whether the big hit type is “15R uncertain change”, “15R positive change”, or “2R sudden change” when the special figure display result is determined (predetermined). FIG. 10 is a table that is referred to for determination based on numerical data indicating a random value MR2 for determining the jackpot type. The random number value MR2 for determining the big hit type is generated, for example, by using the random number generated by the random number circuit 503a as it is or by applying a predetermined processing to the random number generated by the random number circuit 503a. do it. Note that the method of generating the random number MR2 for determining the big hit type is not limited to this. For example, the random number value MR2 may be generated by executing a predetermined processing using the random number value MR1 for determining the special figure display result. Alternatively, the random value MR2 may be generated using a random counter or the like provided in a predetermined area of the RAM 55. In this embodiment, it is assumed that the random value MR2 for determining the jackpot type takes a value in the range of “1” to “100”.

  In the jackpot type determination table 201, for example, a numerical value (decision value) to be compared with the random value MR2 for determining the jackpot type is assigned to the jackpot types of “15R uncertain change”, “15R probability change”, and “2R sudden probability”. . Also, the big hit type determination table 201 indicates the stored value (big hit type buffer value) of the big hit type buffer provided in a predetermined area of the RAM 55 as any of “0” to “2” corresponding to the determination result of the big hit type. It includes table data (setting data) for setting the crab.

  FIG. 55 is a flowchart showing the special symbol normal process in step S300 in the special symbol process. In the special symbol normal process, the CPU 56 of the game control microcomputer 560 is in a state where the variation of the special symbol can be started (for example, the value of the special symbol process flag is a value indicating step S300, and the special symbol holding memory (When the number of stored data (stored data) stored in is other than “0”) (Y in step S401), the special figure display result stored from the special figure holding memory corresponding to the holding number “1” Various numerical data including the random number value MR1 for determination are read (step S402). In this case, the CPU 56 subtracts 1 from the count number of the start winning counter, thereby reducing the number of reserved memories by 1 and assigns to the second to fourth entries (holding numbers “2” to “4”) of the special figure reservation memory. Various stored data including the stored random number value MR1 for determining the special figure display result are shifted up by one entry (step S402).

  Further, the CPU 56 uses a special figure as a table used for determining (predetermining) a special figure display result, which is a display result of the special symbol display 8, as one of “big hit”, “small hit”, and “losing”. The display result determination table 201 is selected and set (step S404). The CPU 56 determines a special figure display result as a display result of the special symbol display 8 based on the random number value MR1 read in step S401 (step S405). In this case, the CPU 56 determines whether or not to make a big hit using the special figure display result determination table 200 selected in step S404 (step S406).

  If it is determined that the special symbol display result, which is the display result of the special symbol display 8, is “big hit” (Y in step S406), the CPU 56 sets a big hit flag indicating that the special symbol display result is determined to be “big hit”. The device is turned on (step S407). At this time, the big hit type determination table 201 is selected and set as a table used for determining the big hit type as one of “15R uncertain change”, “15R positive change”, and “2R sudden change” (step S408). Then, the CPU 56 determines the jackpot type as one of a plurality of types based on the random value MR2 (step S409). Note that the random value MR2 for determining the big hit type may be generated based on the numerical data read from the random number circuit 503 when the process of step S409 is executed, or step S322 of FIG. After being stored in the special figure holding memory based on the numerical data read in step, it may be read in step S402. The CPU 56 sets a jackpot type buffer value based on the determination result of the jackpot type (step S410). As an example, if the jackpot type is “15R uncertain change”, the jackpot type buffer value is “0”, “15R probability change” is “1”, and “2R suddenness” is “2”. .

  If the special figure display result is determined not to be “big hit” (N in step S406) but “small hit” (Y in step S411), the CPU 56 confirms that the special figure display result is determined to be “small hit”. The small hit flag shown is turned on (step S412). When it is determined that the special figure display result is not “small hit” (N in step S411) but “lost”, the big hit flag and the small hit flag are held in the OFF state.

  Thereafter, the CPU 56 determines a confirmed special symbol corresponding to the special symbol display result that is the display result of the special symbol display 8 (step S413). At this time, the special symbol indicating the symbol “-” that becomes the lost symbol is determined as the confirmed special symbol in response to the pre-determined result that the special symbol display result is “lost”. On the other hand, the special symbol indicating the number “2” as the small hit symbol is determined as the confirmed special symbol corresponding to the pre-determined result indicating that the special symbol display result is “small hit”. In addition, when a pre-determined result indicating that the special figure display result is “big hit” is obtained, “3”, “5”, “7”, which are big hit symbols, are determined according to the big hit type determination result. One of the special symbols indicating the numbers is determined as the confirmed special symbol. That is, when the big hit type is determined to be “15R non-probable change”, the special symbol indicating the number “3” that is the 15R non-probable change symbol is determined as the confirmed special symbol. When the big hit type is determined to be “15R probability variation”, the special symbol indicating the number “7” that is the 15R probability variation symbol is determined as the confirmed special symbol. When the big hit type is determined as “2R accuracy”, the special symbol indicating the number “5” that is the 2R probability variable symbol is determined as the confirmed special symbol.

  Then, the CPU 56 updates the value of the special symbol process flag to a value corresponding to the variation pattern setting process (step S414). In step S401, for example, when the number of reserved memory is “0”, when the special symbol cannot be changed (N in step S401), a predetermined demonstration display setting is performed ( Step S415). As an example, a customer waiting demonstration designation command for designating a demonstration display (demonstration screen display) by displaying a predetermined effect image on the effect display device 9 has been transmitted from the main board 31 to the effect control board 80. It is determined whether or not. At this time, if the transmission has been completed, the demonstration display setting is ended as it is. On the other hand, if it has not been transmitted, the transmission setting of the customer waiting demonstration designation command may be performed by setting the head address of the customer waiting demonstration designation command transmission table in the ROM 54 as a pointer, for example.

  Next, the special symbol stop process (step S303) in the special symbol process will be described. FIG. 56 is a flowchart showing the special symbol stop process. In the special symbol stop process, the CPU 56 of the game control microcomputer 560 determines whether or not a special figure confirmation display flag provided in a predetermined area of the RAM 55 is on (step S421). Here, the special figure confirmation display flag is turned on in step S425, which will be described later, in response to the special figure display result (definite special symbol) that is the display result on the special symbol display 8 being derived and displayed. Is set.

  When the special symbol confirmation display flag is OFF (N in step S421), the CPU 56 stops the special symbol variation in the special symbol display 8 and derives and displays the stop symbol (definite special symbol) (step S421). S422). Also, a setting is made to transmit the effect symbol stop command to the effect control board 80 (step S423). Then, a predetermined time (for example, 1 second) set in advance as the special figure confirmation display time is set (step S424). At this time, the special figure confirmation display flag is set to the on state (step S425).

  If the special figure confirmation display flag is set (Y in step S421), the CPU 56 of the game control microcomputer 560 determines whether or not the special figure confirmation display time has elapsed (step S426). If the special figure confirmation display time has not elapsed (N in step S426), the special symbol stop process is terminated and the process waits. When the special figure confirmation display time has elapsed (Y in step S426), the special figure confirmation display flag is cleared and turned off (step S427). Then, it is determined whether or not the big hit flag is on (step S428).

  If the big hit flag is in the on state (Y in step S428), a predetermined time is set as a big hit start production waiting time (step S429). Then, a setting for transmitting the hit start designation command to the effect control board 80 is performed (step S430). Further, the big hit flag is cleared and turned off (step S431). Further, a setting for ending the probability variation state and the time reduction state is performed (step S432). As an example, it is only necessary to clear the probability variation flag and the time reduction flag stored in a predetermined area of the RAM 55 to be in the off state, and to clear the time reduction counter for counting the remaining number of times of the special game in which the time reduction control is executed.

  At this time, it is determined whether or not the setting for outputting the gaming machine specific information has been executed (step S433). For example, when the unique information output request flag is on, or when a valid address is set in the unique information read pointer, it may be determined that the output setting of the gaming machine unique information has been completed. When the output setting of the gaming machine specific information has not been completed (N in step S433), the setting for outputting the gaming machine specific information to the outside is performed (step S434). For example, the CPU 56 may perform setting for externally outputting the gaming machine unique information by setting the unique information output request flag or setting the reading start address of the gaming machine unique information in the unique information read pointer. .

  By setting the output of the gaming machine specific information in the process of step S434, when the gaming state in the pachinko gaming machine 1 becomes the big hit gaming state, it is determined that the information output condition is satisfied, and the gaming machine unique information is transferred to the external device. Enable output. One jackpot signal or two jackpot signals from the output port of the game control microcomputer 560 are turned on when the jackpot game is in progress, and are output to an external device via the terminal board 160. Therefore, when the gaming machine specific information is output to the external device based on the setting in step S434, the big hit 1 signal or the big hit 2 signal in the on state is sent to the external device as a status signal indicating that the big hit game is being played. Is output.

  Even in the big hit gaming state, when it is determined that the output setting of the gaming machine specific information has been completed (Y in step S433), the restriction is set not to newly set the gaming machine specific information to be externally output. (Restrict. As a result, when the game machine specific information is externally output based on the establishment of other information output conditions, the output setting of the game machine specific information based on the establishment of the information output condition at the time of big hit is duplicated. Therefore, it is possible to prevent the gaming machine specific information that has already been output in the serial signal system from being interrupted before the completion of the external output. That is, after external output of gaming machine specific information is once started based on output settings, the output of new gaming machine specific information is restricted (restricted) until the output is completed, and the current output state is maintained. To do. Thus, by avoiding conflicting output settings and maintaining the current output state so as not to interrupt the gaming machine specific information, the gaming machine specific information can be reliably output to an external device such as a hall computer. Unauthorized acts such as changing the chip of the control microcomputer 560 or replacing the main board 31 can be properly detected.

  Thereafter, the CPU 56 of the game control microcomputer 560 updates the value of the special symbol process flag to a value corresponding to the big hit release pre-processing (step S304) (step S435).

  If the big hit flag is not set in step S428 (N in step S428), it is confirmed whether the small hit flag is set (step S436). When the small hit flag is set (Y in step S436), a predetermined time set in advance as the small hit start production waiting time is set (step S437). Then, a setting for transmitting a hit start designation command to the effect control board 80 is performed (step S438). Further, the small hit flag is cleared and turned off (step S439). Thereafter, the value of the special symbol process flag is updated to a value corresponding to the small hitting process (step S307) (step S440).

  When the small hit flag is not set in step S436 (N in step S436), the CPU 56 of the game control microcomputer 560 sets the value of the special symbol process flag to a value corresponding to the special symbol normal process (step S300). (Step S441).

  Thereafter, it is determined whether or not the time reduction control in the probability changing state or the time reduction state is terminated (step S442). As an example, when the time reduction flag is ON, the time reduction count value which is the stored value of the time reduction counter is updated by subtracting 1 for example. Then, it is determined whether or not the updated short time count value matches a predetermined short time end determination value (for example, “0” or the like). At this time, if it coincides with the time reduction end determination value, the time reduction control in the probability changing state or the time reduction state may be ended by clearing the time reduction flag and turning it off. On the other hand, if it does not coincide with the time reduction end determination value, the state of the time reduction flag may be maintained and the time reduction control may be continued. When the gaming state is in a probabilistic state, the time-shortening control may be continued until the special figure display result becomes “big hit” or until a predetermined number of special figure games are executed. Alternatively, when the gaming state is a probability variation state, the time-shortening control may be terminated in step S442. On the other hand, for the probability variation control, until the special figure display result becomes “big hit”, or a predetermined number of times. It may be continued until the special figure game is executed. Further, when the gaming state is the probability variation state, the time-shortening control may be terminated in step S442, and the probability variation control may be terminated.

  Note that the timing for setting the output of the gaming machine specific information at the time of the big hit is not limited to the timing at which the process of step S434 is executed. For example, in either the big hit release pre-processing in step S304, the big hit open process in step S305, or the big hit end process in step S306, the processing in steps S433 and S434 is executed, so that the big hit gaming state is started or controlled. A setting for outputting the gaming machine specific information to the external device may be performed corresponding to either the middle or the end time.

  Next, the big hit end process (step S306) in the special symbol process will be described. FIG. 57 is a flowchart showing the big hit end processing. In the big hit end process, the CPU 56 of the game control microcomputer 560 determines whether or not the big hit end presentation waiting time has elapsed (step S451). The big hit end presentation waiting time may be set when the value of the special symbol process flag is updated to a value corresponding to the big hit end presentation waiting process in the big hit middle opening process (step S305). When the big hit end presentation waiting time has not elapsed (N in step S451), the big hit end processing is ended and the system waits.

  When the big hit end presentation waiting time has elapsed (Y in step S451), the big hit type buffer value stored in a predetermined area of the RAM 55 is read (step S452). Then, it is specified whether the big hit type is “15R uncertain variation”, “15R certain variation”, or “2R sudden variation”. At this time, it is determined whether or not the identified jackpot type is “15R uncertain change” (step S453).

  If the identified jackpot type is “15R non-probable change” (Y in step S453), settings are made to start control that sets the gaming state of the pachinko gaming machine 1 to the short-time state after the jackpot gaming state ends. (Step S454). For example, the CPU 56 sets the time reduction flag to the on state and sets a predetermined count initial value (for example, “100”) corresponding to the upper limit value of the special figure game that can be executed in the time reduction state to the time reduction counter. Set to.

  When the identified big hit type is “15R probability change” or “2R probability change” (N in step S453), after the big hit game state is finished, to start the control to change the game state of the pachinko gaming machine 1 to the probability change state Is set (step S455). For example, the CPU 56 sets the probability variation flag to the on state. At this time, the CPU 56 may determine whether or not to set the time reduction flag to the ON state based on the specified jackpot type or the like. For example, when the specified big hit type is “15R probability variation”, the time-shortening flag is set to the on state to control to the probability variation state (high-accuracy high-base state) in which the time-shortening control is always performed. On the other hand, if the specified jackpot type is “2R accuracy”, whether or not to set the hourly flag to the ON state according to the gaming state before the jackpot gaming state is determined. Good. In other words, if the gaming state before the big hit gaming state is a certain change state or a short-time state, the short-time flag is set to the on state to control to a certain variation state (high-accuracy high-base state) in which the short-time control is performed. To do. On the other hand, if the gaming state before the big hit gaming state was the normal state, the time-shortening flag is kept off and the time-varying control is not performed (high probability low base state). You may control.

  Thereafter, the value of the special symbol process flag is updated to a value corresponding to the special symbol normal process (step S300) (step S456).

  Next, the switch process (step S21) in the 4 ms timer interrupt process will be described. In this embodiment, when the ON state of the detection signal of each switch related to winning detection or gate passage continues for a predetermined time, it is determined that the switch is surely turned on, and processing corresponding to the switch on is started. FIG. 58 is an explanatory diagram showing each 2-byte buffer formed in the RAM 55 used in the switching process. The previous port buffer is a buffer in which the previous switch-on / off determination result (for example, 4 ms before) is stored. The port buffer is a buffer for storing the contents of the ports 0 and 1 input this time. The switch-on buffer is a buffer in which the corresponding bit is set to 1 when switch on is detected and the corresponding bit is set to 0 when switch off is detected. The previous port buffer, port buffer, and switch-on buffer shown in FIG. 58 are prepared for each of the input ports 0 and 1. For example, in this embodiment, two switch-on buffers 1 and 2 are prepared, the switch state of the input port 0 is set to the switch-on buffer 1, and the switch state of the input port 1 is the switch-on buffer 2. Set to

  FIG. 59 is a flowchart showing a processing example of the switch process in step S21 in the 4 ms timer interrupt process. In the switch process, the game control microcomputer 560 first inputs data input to the input ports 0 and 1 (see FIG. 25) (step S101), and sets the input data in the port buffer (step S102). ).

  Next, the initial value of the weight counter formed in the RAM 55 is set (step S103), and the value of the weight counter is decremented by 1 until the value of the weight counter becomes 0 (steps S104 and S105).

  When the value of the wait counter reaches 0, the data of the input ports 0 and 1 are input again (step S106), and a logical product is obtained for each bit between the input data and the data set in the port buffer. (Step S107). Then, the logical product operation result is set in the port buffer (step S108). Of the two input data input from the input port 0 with a time interval of approximately [initial value of weight counter × (processing time of steps S104, S105)] by the processing of steps S103 to S108, both “ Only the bits that are “1” will be “1” in the port buffer. In other words, if the ON state of the switch detection signal continues for a predetermined period [initial value of wait counter × (processing time of steps S104 and S105)], the corresponding bit in the port buffer becomes “1”.

  Further, the game control microcomputer 560 performs exclusive OR for each bit between the data previously set in the port buffer and the data set in the port buffer (step S109). In the result of the exclusive OR operation, the bit corresponding to the switch for which the previous switch-on / off determination result (for example, 4 ms before) differs from the switch-on / off determination result determined to be on this time is “ 1 ”. The game control microcomputer 560 further performs a logical product for each bit between the exclusive OR operation result and the data set in the port buffer (step S110). As a result, of the bits corresponding to the switches for which the previous switch on / off determination result and the switch on / off determination result determined to be on this time are different (according to the exclusive OR operation result), the current on Only the bit corresponding to the switch determined to be (by AND operation) remains as “1”.

  Then, the game control microcomputer 560 sets the logical product calculation result in step S110 in the switch-on buffer (step S111), and sets the contents of the port buffer in which the calculation result in step S108 is set in the previous port buffer. (Step S112).

  By the above processing, among the switches that have been on for a predetermined period of time, the switch on / off determination result of the previous time (for example, 4 ms ago) was off, that is, the switch changed from the off state to the on state. The bit corresponding to the switch is “1” in the switch-on buffer.

  Further, the game control microcomputer 560 (specifically, the CPU 56) performs a switch normal / abnormal check process (step S113).

  FIG. 60 is a flowchart showing a switch normal / abnormal check process. In the switch normality / abnormality check process shown in FIG. 60, the CPU 56 reads the contents of the switch-on buffer corresponding to the input port 1 (step S121). Then, it is confirmed whether or not the value of bit 0 corresponding to the start port switch 14a in the switch-on buffer corresponding to the input port 1 is 0 (step S122). That is, it is confirmed whether or not the start port switch 14a (proximity switch) provided in the upper portion of the start winning port 14 is turned on (a game ball is detected).

  When the value of bit 0 corresponding to the start port switch 14a in the switch on buffer corresponding to the input port 1 is 0 (that is, when the start port switch 14a is in the ON state), the switch formed in the RAM 55 The stored value (switch count value) of the counter is increased by 1 (step S123).

  Further, the CPU 56 checks whether or not the value of bit 1 corresponding to the winning confirmation switch 14b in the switch-on buffer corresponding to the input port 1 is 0 (step S124). That is, it is confirmed whether or not a winning confirmation switch 14b (photo sensor) provided at a lower portion in the start winning opening 14 is turned on (a game ball is detected).

  When the value of bit 1 corresponding to the winning confirmation switch 14b in the switch-on buffer corresponding to the input port 1 is 0 (that is, when the winning confirmation switch 14b is in the ON state), the switch stored in the RAM 55 The count value for use is decreased by 1 (step S125).

  Then, the CPU 56 checks whether or not the switch count value is outside the predetermined normal range (step S126). The normal range of the switch count value indicates an allowable range in the difference between the number of game balls detected by the start port switch 14a and the number of game balls detected by the winning confirmation switch 14b. The value should just be predetermined. The normal range of the switch count value may include not only an upper limit value such as “10” but also a lower limit value such as “−10”. Alternatively, “10” may be set as the default value (initial value) of the switch count value, the upper limit value of the normal range may be “20”, and the lower limit value may be “0”.

  When the switch count value is out of the normal range (Y in step S126), the CPU 56 determines that an abnormal winning to the start winning opening 14 has occurred, and corresponds beforehand to the abnormal start winning in advance. A predetermined security signal output time (in this example, 4 minutes) is set (step S127). In this embodiment, the CPU 56 sets a predetermined time (4 minutes in this example) to the security signal information timer based on the fact that the switch count value is “10” or more. In this embodiment, an abnormal winning of the start winning opening 14 is detected by executing the information output process (see S31) based on the fact that the predetermined time is set in the security signal information timer in step S127. Sometimes, a security signal is externally output for a predetermined time (in this example, 4 minutes).

  In this embodiment, even if a value is already set in the security signal information timer and the security signal is being output to the outside, if a new abnormal winning is detected, the process of step S127 is executed again. The security signal information timer is overwritten with a predetermined time (in this example, 4 minutes). Therefore, when a new abnormal winning is detected during the external output of the security signal, the external output period of the security signal is substantially extended, and a predetermined time (in this example) from the time when the new abnormal winning is detected. 4 minutes) The output of the security signal is continued.

  In response to the occurrence of an abnormal winning at the start winning opening 14 in this way, a setting is made to invalidate the detection of the gaming ball that has become an abnormal winning. That is, in the switch-on buffer, the bit number (for example, bit 0 or bit 1) corresponding to the start winning port 14 where the abnormal winning is detected is cleared, and the bit value is initialized to 0 (step S128). As a result, the detection of the game ball that has become an abnormal winning is invalidated, and a predetermined number (for example, three) of game balls are paid out as a prize ball, or a special game based on the start condition being satisfied, Output of a start port signal to an external device such as a hall computer is limited so as not to be performed. It should be noted that at least one or a combination of two or more of a predetermined number of award balls paid out, a special game based on the establishment of a start condition, and an output of a start port signal to an external device is performed. There may be.

  Thereafter, for example, an abnormal winning notification flag formed in a predetermined area of the RAM 55 is set to an on state (step S129). Thus, based on the fact that the abnormal winning notification flag is turned on, the effect symbol command control processing is executed in step S30 of FIG. A command is sent. On the side of the effect control board 80, for example, the effect control CPU 101a of the effect control microcomputer 100 executes a predetermined notification process based on the reception of the abnormal winning notification command, and displays it in the display area of the effect display device 9. It is only necessary to perform control for recognizing that the abnormal winning has occurred at the start winning opening 14 by displaying a predetermined abnormal winning notification image or the like.

  In this embodiment, the case where the abnormal winning to the start winning opening 14 is detected using only one switch counter is shown. However, the number of detections of the start opening switch 14a and the number of detections of the winning confirmation switch 14b are as follows. Different switch counters may be used. In this case, for example, the value of the first switch counter is incremented by 1 each time the start-up switch 14a is detected, and the second switch counter is detected every time the winning confirmation switch 14b is detected. It is sufficient to add 1 to the value of. In step S126, based on the determination that the difference between the value of the first switch counter and the value of the second switch counter is greater than or equal to a predetermined value (for example, 10), an abnormality to the start winning port 14 is detected. It may be determined that a winning has occurred and the process of step S127 is executed to output the security signal to the outside.

  Further, for example, in addition to abnormal winning at the start winning opening 14, a security signal is also output when an abnormal winning at the big winning opening, an abnormal magnetic error, an abnormal radio wave error, or a communication error is detected. In this case, different error notification commands may be transmitted to the effect control microcomputer 100 for each type of error. Then, on the effect control microcomputer 100 side, error notification may be performed by causing the effect display device 9 to display different error screens for each type of error.

  In the above configuration, when power supply is resumed after the power supply to the gaming machine is stopped, an error notification is being issued before the power supply is stopped. The error notification command may be transmitted again to the effect control microcomputer 100. In other words, since the storage content such as RAM is not backed up by the backup power source on the production control microcomputer 100 side, if a power failure occurs, it is not possible to execute the production such as error notification that has been executed until then. However, the error notification can be resumed when the power failure is recovered by configuring the predetermined error notification command to be transmitted again when the power failure is recovered. The game control microcomputer 560 also backs up the value of the security signal information timer in the backup RAM. If the security signal is being output before the power supply is stopped, it is backed up when the power failure is restored. The output of the security signal may be resumed based on the value of the security signal information timer. By providing these configurations, it is possible to prevent an illegal act such as turning off the error notification or stopping the output of the security signal by intentionally turning off the power to the gaming machine.

  61 and 62 are explanatory diagrams for explaining switch normal / abnormal check processing. Among these, FIG. 61 shows an example of the switch normality / abnormality check process in a normal state, and FIG. 62 shows an example of the switch normality / abnormality check process when an illegal act leading to an abnormal winning is performed. Show.

  As shown in FIGS. 61 and 62, bit 0 of the switch-on buffer corresponding to input port 1 is set to “0” when a game ball is detected by start port switch 14a (proximity switch) corresponding to bit 0. Become. The bit 1 of the switch-on buffer corresponding to the input port 1 becomes “0” when a game ball is detected by the winning confirmation switch 14 b (photo sensor) corresponding to the bit 1. If the switch is operating normally and has not received any fraudulent activity (an act of improperly turning on the detection signal from the switch or improperly turning off the detection signal in the on state) Since the switch 14a is arranged on the upstream side of the winning confirmation switch 14b, first, the start port switch 14a (proximity switch) should be turned on, and then the winning confirmation switch 14b (photo sensor) should be turned on. Accordingly, the value of the switch counter is first incremented by 1 based on the start port switch 14a being turned on (see step S123), and then the value of the switch counter is incremented based on the winning confirmation switch 14b being turned on. 1 is subtracted and the value returns to 0 (see step S125). Therefore, when the game ball passes through the switch, both the bit 0 and the bit 1 of the switch-on buffer corresponding to the input port 1 become “0”, and if it is in a normal operation state, the timing is shifted to the count-up timing ( As shown in FIG. 61, the value of the switch counter should be kept at zero.

  However, when a fraudulent act by radio waves is performed, as shown in FIG. 62, the off state is illegally interrupted by radio waves during the period when the start port switch 14a is turned on once, and the start port switch 14a There is a risk that fraudulent acts that cause the user to recognize as if turned on twice. Accordingly, even though the start port switch 14a is turned on only once, it is misrecognized that the start port switch 14a has been turned on twice, and the value of the switch counter is added by 2 in total. (Step S123 is executed twice). On the other hand, the winning confirmation switch 14b arranged on the downstream side is different in detection method from the electromagnetic starter switch 14a, and uses an optical photosensor. I do not receive it. Therefore, as shown in FIG. 62, when one game ball is detected by the start opening switch 14a, when the game ball is detected on the winning confirmation switch 14b side with a slight delay, the winning confirmation switch 14b is normally turned on. Detection is performed only once, and the value of the switch counter is decremented by 1 to 1 (see step S125). Therefore, when a fraudulent act by radio waves is performed, there is a difference in the number of detections between the start port switch 14a and the winning confirmation switch 14b with different detection methods, so as shown in FIG. Based on the fact that the counter value is not maintained at 0 and the switch counter value is equal to or greater than a predetermined value (10 in this example), the accumulated detection error between the start port switch 14a and the winning confirmation switch 14b is accumulated. Based on the fact that the value is equal to or greater than a predetermined value (10 in this example), it is possible to detect that an abnormal winning to the start winning opening 14 has occurred.

  In addition, it is also conceivable that a similar illegal act is performed by an act of illegally irradiating light. In this case, there is a possibility that a fraudulent act may be performed in which the off-state is illegally interrupted by light during the period when the winning confirmation switch 14b is turned on once and the recognition is performed as if the winning confirmation switch 14b is turned on twice. is there. However, in this case, on the contrary, on the electromagnetic start port switch 14a side, the game ball can be normally detected without being affected by the illegal act of light, and similarly, the value of the switch counter is not kept at 0, Based on the fact that the value of the switch counter is equal to or greater than a predetermined value (10 in this example) (the accumulated value of detection errors between the start port switch 14a and the winning confirmation switch 14b is a predetermined value (10 in this example)). Based on the above, it is possible to detect that an abnormal winning to the start winning opening 14 has occurred.

  In this embodiment, the output of the start port switch 14a and the winning confirmation switch 14b is negative logic, but the output of the start port switch 14a and the winning confirmation switch 14b is positive logic. May be. In this case, for example, the output levels of the start port switch 14a and the winning confirmation switch 14b may be logically inverted by the input driver circuit and then input to the game control microcomputer 560.

  Further, in this embodiment, it is immediately determined as an abnormal winning based on the fact that the value of the switch counter is not kept at 0 (a detection error has occurred between the start switch 14a and the winning confirmation switch 14b). Instead, it is determined that an abnormal winning has occurred based on the value of the switch counter being equal to or greater than a predetermined value (10 in this example). Such a configuration prevents, for example, a case where a game ball has become clogged in the start winning opening 14 from being determined as an abnormal winning due to fraud.

  FIG. 63 is an explanatory diagram showing a case where a game ball is in a clogged state in the start winning opening 14. As shown in FIG. 63, in the start winning opening 14, the start opening switch 14a and the winning confirmation switch 14b are arranged at a certain distance in the vertical direction. Therefore, the game ball won at the start winning opening 14 is first detected by the start opening switch 14a, and then detected by the downstream winning confirmation switch 14b after a short time. As shown in FIG. 63, when a game ball is clogged in the start winning opening 14, there is a difference in the number of detections due to the physical distance difference between the starting opening switch 14a and the winning confirmation switch 14b. It occurs. In this embodiment, as shown in FIG. 63, it is assumed that a maximum of three detection errors occur between the start port switch 14a and the winning confirmation switch 14b. Therefore, in this embodiment, the value of the switch counter is a predetermined value (10 in this example) with a sufficient margin for the three detection errors of the start port switch 14a and the winning confirmation switch 14b in the ball jammed state. By determining that an abnormal winning has occurred based on the above, it is possible to prevent a case where a game ball has become clogged in the start winning port 14 from being determined as an abnormal winning due to fraud. Yes.

  In this embodiment, it is based on the fact that the predetermined value (10 in this example) is sufficient with a sufficient margin for the three detection errors of the start opening switch 14a and the winning confirmation switch 14b in the ball jammed state. Although the case where it is determined that an abnormal winning has occurred is shown, the predetermined value used for determining the abnormal winning is not limited to that shown in this embodiment. For example, if the number of detection errors between the start port switch 14a and the winning confirmation switch 14b in the ball jammed state is more than three, it is possible to prevent erroneous determination of abnormal winning. It may be determined that an abnormal winning has occurred based on the fact that the value of becomes 4 or more.

  In addition, when it is configured to be able to detect abnormal winnings at a plurality of winning mouths, an abnormal winning determination is made using a number greater than the total number of detection errors in the ball jammed state at all of the winning mouths as a predetermined value. You may make it perform. For example, in the case of a gaming machine equipped with two start winning ports, when it is configured to detect an abnormal winning of a large winning port in addition to two starting winning ports, detection in a ball clogged state at each winning port Assuming that there are 3 errors each, a maximum of 3 x 3 = 9 detection errors may occur due to clogging of the ball at the prize opening even if it is not based on fraudulent acts using radio waves. . Therefore, in such a case, if it is determined that an abnormal winning has occurred based on the value of the switch counter being at least 10 or more, it is possible to prevent erroneous determination of an abnormal winning.

  FIG. 64 is a block diagram showing various signals output to the terminal board 160. As shown in FIG. 64, in this embodiment, from the gaming control microcomputer 560 mounted on the main board 31 to the terminal board 160, a start port signal, a symbol determination number 1 signal, gaming machine specific information, One jackpot signal, two jackpot signals, three jackpot signals, a short time signal, a security signal, and an on-time state signal are output by the information output process (see step S31) on the game control microcomputer 560 side. In this embodiment, a prize ball signal 1 and a gaming machine error status signal are sent from the payout control microcomputer 370 mounted on the payout control board 37 to the terminal board 160 via the main board 31. Is output by the information output process (see step S759) on the payout control microcomputer 370 side. Furthermore, in this embodiment, after passing through the backup power supply circuit 508 from the door opening switch 155a or the door opening switch 155b, directly or via one or both of the main board 31 and the dispensing control board 37. A door opening signal is output to the terminal board 160.

  The start port signal is a signal for notifying the number of winnings to the start winning port 14. The symbol determination number 1 signal is a signal for notifying the number of changes in the special symbol. The game machine specific information is information including a chip individual number assigned in advance for each product of the pachinko gaming machine 1 or for each chip of the game control microcomputer 560. The jackpot 1 signal is a signal for notifying that the jackpot game (during the operation of the special variable winning ball apparatus) is in progress. The jackpot 2 signal is a signal for notifying that the jackpot game (during the operation of the special variable winning ball apparatus) or that the special symbol variation time reduction function is being operated (during the short-time state). The jackpot 3 signal is a signal for notifying that a 15-round jackpot game is in progress. The time reduction signal is a signal for notifying that the special symbol variation time reduction function is operating (in the time reduction state).

  The security signal is a signal indicating the security state of the gaming machine. Specifically, when it is determined that an abnormal winning to the starting winning opening 14 has occurred based on the detection result of the starting opening switch 14a and the detection result of the winning confirmation switch 14b, the security signal is displayed for a predetermined period (for example, (4 minutes) is output to an external device such as a hall computer. Also, when the gaming machine is turned on and the initialization process is executed, a security signal is output to an external device such as a hall computer for a predetermined period (for example, 30 seconds).

  It should be noted that the signal output externally as the security signal is not limited to that shown in this embodiment. For example, not only the abnormal winning at the start winning opening 14 but also the abnormal winning at the large winning opening or the normal winning openings 29 and 30 may be detected and output as a security signal to the outside. In addition, for example, when abnormal magnetism is detected by a magnet sensor provided in a gaming machine or when abnormal radio waves are detected by a radio wave sensor provided in a gaming machine, it is configured so that it can be output externally as a security signal. Also good. In addition, for example, when an abnormality of various switches provided in a gaming machine is detected (for example, when an occurrence of a short circuit is detected by determining that an input value exceeds a threshold value), it can be externally output as a security signal. You may comprise as follows. In this way, even if an abnormal winning at the big prize opening, abnormal magnetic error, or abnormal radio wave error is configured to be output as a security signal from the common connector CN8 of the terminal board 160, even one signal line can be connected. In this case, error detection can be performed by an external device such as a hall computer, and the work load related to error detection can be reduced.

  Further, for example, even when a communication error between the game control microcomputer 560 and the payout control microcomputer 370 is detected, it can be externally output as a security signal from the common connector CN8 of the terminal board 160. May be. In this case, for example, the game control microcomputer 560 determines that a communication error has occurred based on failure to receive a connection OK command or a prize ball number reception command (to be described later) from the payout control microcomputer 370, and the terminal The security signal may be externally output from the common connector CN8 of the board 160. Further, for example, the game control microcomputer 560 determines that a communication error has occurred based on the value of any of the error bits of bits 0 to 4 of the status register A of the serial communication circuit 505 being set. The security signal may be externally output from the common connector CN8 of the terminal board 160.

  In addition to the signal line and connector CN8 for security signals, a signal line and connector dedicated to communication errors between the game control microcomputer 560 and the payout control microcomputer 370 may be provided on the terminal board 160. When a communication error between the game control microcomputer 560 and the payout control microcomputer 370 is detected, an external device such as a hall computer is transmitted via the terminal board 160 as a signal different from the security signal. May be output.

  The on-time state signal is a signal indicating whether or not the gaming state when the power is turned on is a special gaming state. Specifically, when the gaming machine is turned on and the initialization process is not executed, the game machine is turned on based on the fact that data indicating the special gaming state is stored in a predetermined area of the RAM 55 or the like. The hour state signal is output to an external device such as a hall computer until a predetermined output stop condition is satisfied.

  The prize ball signal 1 is a signal that is output every time one prize ball payout is detected. Further, the gaming machine error state signal is a signal indicating that the gaming machine is in an error state (in this example, a ball-out error state or a full tank error state). Instead of outputting the prize ball signal 1 to the outside every time one prize ball is detected, a certain prize ball signal is outputted every time a predetermined number (for example, 10) of prize balls is detected. Also good.

  The door opening signal is a state in which the mechanism plate of the glass door frame 2 or the game frame 11 is opened with respect to the game frame 11, or the game frame 11 itself is opened with respect to the outer frame 2A. This is a signal indicating this. In addition to these signals, for example, an arbitrary signal such as a power-on signal may be output to an external device such as a hall computer via the terminal board 160. The power-on signal is a signal indicating that power supply to the pachinko gaming machine 1 is started when the pachinko gaming machine 1 is powered on. When the game machine specific information is output on the assumption that the information output condition is satisfied when the power is turned on, the power on signal is output together with the game machine specific information as a state signal indicating a state in which power supply to the pachinko gaming machine 1 is started. What is necessary is just to output to an apparatus.

  65 to 68 are flowcharts showing the information output process (step S31) in the 4 ms timer interrupt process. Of the processes shown in FIGS. 65 to 68, steps S1002 to S1030 are processes for outputting the start port signal, and steps S1031 to S1036 are processes for outputting the symbol determination number 1 signal. S1050 to S1068 are processes for outputting one jackpot signal, two jackpot signals, three jackpot signals and a short time signal. Further, steps S1069 to S1074 are processes for outputting a security signal, steps S1081 to S1096 are processes for outputting gaming machine specific information, and steps S1099A to S1099F are for outputting an on-time state signal. It is processing.

  In the information output process, the CPU 56 sets an initial value (00 (H)) in the information buffer formed in the RAM 55 (step S1001). Then, the address of the start port information setting table is set in the pointer (step S1002), and the number of processes pointed to by the pointer is loaded (step S1003). The number of processes (= 1) and the start port switch input bit (start port switch input bit determination value (01 (H)) are set in the start port information setting table. In step S1003, the pointer is set to the start port information setting. Since the address of the number of processes in the table is indicated, the data of the number of processes (= 1) in the start port information setting table is loaded.If the gaming machine has two start winning ports, In the start port information setting table, 2 may be set as the number of processes, and start port switch input bits for the two start winning ports may be set respectively.

  Next, the CPU 56 loads the contents of the switch-on buffer into the register (step S1004), and sets the switch-on buffer as switch input data (step S1005). The pointer is incremented by 1 (step S1006), the start port switch input bit pointed to by the pointer is loaded into the register (step S1007), and the logical product of the start port switch input bit and the switch input data is obtained (step S1008). When the content of the switch-on buffer is 01 (H), that is, when the start port switch 14a is on, the logical product operation result is 01 (H). When the start port switch 14a is not turned on, the logical product operation result is 00 (H).

  If the logical operation result is 0 (Y in step S1009), the process proceeds to step S1015. If the result of the logical product is not 0 (N in step S1009), it is determined that a winning has been made for the starting winning port 14, and the starting port information storage counter is loaded into the register (step S1010). The start port information storage counter is a counter that counts the number of remaining outputs of the start port signal (that is, the remaining number of start winnings that have not been output from the start port signal). Next, the CPU 56 adds 1 to the start port information storage counter (step S1011). Then, it is confirmed whether the calculation result (added result) is not 0 (step S1012). When the calculation result is 0 (N in step S1012), 1 is subtracted from the calculation result (step S1013). Then, the calculation result is stored in the start port information storage counter (step S1014).

  Next, the CPU 56 subtracts 1 from the number of processes (step S1015), and determines whether the number of processes is not 0 (step S1016). When the number of processes is not 0 (Y in step S1016), the process proceeds to step S1004. In this embodiment, since the gaming machine has only one start winning opening 14, 1 is set as the initial value of the processing number, and it is always determined that the processing number is 0 in step S1016. It will be.

  If it is determined in step S1016 that the number of processes is 0 (N in step S1016), the CPU 56 loads the start port information storage timer (step S1017), and reflects the state of the start port information storage timer in the flag register. (Step S1018), it is determined whether or not the start port signal is being output (step S1019). The start port information storage timer is a timer for measuring an on time and an off time (for example, an on time of 200 ms and an off time of 200 ms) of the start port signal. If the value of the start port information storage timer is not 0, it is determined that the start port signal is being output. If the value of the start port information storage timer is 0, it is determined that the start port signal is not being output.

  If the start port signal is being output (Y in step S1019), the process proceeds to step S1026. If the start port signal is not being output (N in step S1019), the CPU 56 loads the start port information storage counter (step S1020), and reflects the state of the start port information storage counter in the flag register (step S1021). Then, it is determined whether there is a remaining number of output times of the start port signal (step S1022). When the start port switch 14a is turned on (N in step S1009), the start port information storage counter is incremented by 1, so that it is determined that there is a remaining number of output times of the start port signal.

  If there is no remaining number of output times of the start port signal (Y in step S1022), the process proceeds to step S1031. If there is a remaining number of output times of the start port signal (N in step S1023), the CPU 56 subtracts 1 from the start port information storage counter (step S1023), and the calculation result (result obtained by subtracting 1) is the start port information storage counter. (Step S1024). Then, the winning information operating time (100) is set in the register (step S1025). The winning information operating time (100) is a time for which a 4 ms timer interruption is executed 100 times, that is, a time of 0.400 seconds (400 ms).

  Next, if the winning information operating time is not set in step S1025, the CPU 56 subtracts 1 from the start port information storage timer, and if the winning information operating time is set in step S1025, the CPU 56 subtracts 1 from the winning information operating time. (Step S1026). Then, the calculation result (result obtained by subtracting 1) is stored in the start port information storage timer (step S1027).

  The CPU 56 compares the calculation result with the winning information on time (50) (step S1029), and determines whether the calculation result is shorter than the winning information on time (step S1030). The winning information on time (50) is a time for which a 4 ms timer interrupt is executed 50 times, that is, a time of 0.200 seconds (200 ms).

  If the calculation result is not shorter than the winning information on time, that is, if the calculation result (remaining time of the start port 1 information storage timer) is longer than the winning information on time (200 ms) (N in step S1029) The CPU 56 sets the start port output bit position of the information buffer (bit 0 of the output port 1 in the example shown in FIG. 24) (step S1030). When the start port output bit position of the information buffer is set, the information buffer is set to the output value in the subsequent step S1100, and the output value is output to the output port 1 in step S1101, whereby the start port signal is output to the output port 1. Will be output.

  When a winning is made to the start winning opening 14 (the start opening switch 14a is turned on) by the processing of steps S1001 to S1030 described above, a start opening signal is output. That is, after the start port signal is turned on for 200 ms, it is turned off for 200 ms. By inputting this starting port signal to the hall computer, the number of winnings to the starting winning port 14 can be recognized.

  Since the start port signal is turned on for 200 ms and then turned off for 200 ms, the next start port is turned off after the 200 ms off state even when a start winning is continuously generated in a short time. A signal is output. That is, the start port signals are output at intervals of at least 200 ms.

  Thus, since the start port signals are output at intervals of at least 200 ms, the hall computer can reliably grasp the total number of start winnings.

  Next, the CPU 56 loads the symbol determination number 1 information timer into the register (step S1031), reflects the state of the symbol determination number 1 information timer in the flag register (step S1032), and the symbol determination number 1 information timer times out. It is determined whether or not (step S1033). In this embodiment, in the special symbol variation process (see step S302), when the variation time times out, when the variation of the special symbol is stopped, the symbol determination number 1 information timer outputs the symbol determination number output time (in this example, 0). .500 seconds) is set, and when the symbol determination count output time has not elapsed, it is determined that the symbol determination count 1 information timer has not timed out, and when the symbol determination count output time has elapsed (symbol determination count) When the value of the 1 information timer is 0), it is determined that the symbol determination number 1 information timer has timed out.

  If the symbol determination count 1 information timer has not timed out (N in step S1033), the symbol determination count 1 information timer is decremented by 1 (step S1034), and the calculation result is stored in the symbol determination count 1 information timer (step S1035). . Then, the design buffer count 1 output bit position of the information buffer (bit 1 of output port 1 in the example shown in FIG. 24) is set (step S1036). When the symbol decision number 1 output bit position of the information buffer is set, the information buffer is set to the output value in the subsequent step S1100, and the output value is output to the output port 1 in step S1101, thereby the symbol decision number 1 signal. Is output from the output port 1 (becomes ON state). If the symbol determination number 1 information timer times out (Y in step S1033), the process of step S1036 is not executed, and as a result, the symbol determination number 1 signal is turned off.

  By the processing of steps S1031 to S1036 described above, every time the change of the special symbol is stopped (stopped symbol is fixed), the symbol determination number 1 signal is turned on in the symbol determination number output time (for example, 500 ms).

  Next, the CPU 56 loads the special symbol process flag (step S1050), compares the value of the special symbol process flag with the special winning opening opening pre-processing designation value (“4”) (step S1051), and then displays the special symbol process flag. It is determined whether the value of is less than 4 (step S1052). When the value of the special symbol process flag is less than 4 (Y in step S1052), the process proceeds to step S1058. When the value of the special symbol process flag is 4 or more (N in step S1052), the output bit position of the big hit of the information buffer is set (step S1053). Further, the big output 2 output bit position of the information buffer is set (step S1054). When the big output 1 bit position and the big hit 2 output bit position of the information buffer are set, the information buffer is set to the output value in the subsequent step S1100, and the output value is output to the output port 1 in the step S1101. One signal and two jackpot signals are output from the output port 1 (become turned on).

  Further, the CPU 56 executes a time reduction check process for confirming whether or not it is in the time reduction state (step S1058), and determines whether or not it is in the time reduction state (step S1059). Specifically, the CPU 56 determines whether or not it is in the time reduction state by checking whether or not the time reduction flag that is set when shifting to the time reduction state is set. If the time-short state is set (Y in step S1059), the time-short output bit position of the information buffer is set (step S1060). When the time-short output bit position is set, a time-short signal is output from the output port 1 by setting the information buffer to the output value in the subsequent step S1100 and outputting the output value to the output port 1 in step S1101. (Turns on) Also, the big output 2 output bit position of the information buffer is set (step S1061). When the jackpot 2 output bit position is set, the information buffer is set to the output value in the subsequent step S1100, and the output value is output to the output port 1 in step S1101, so that the jackpot 2 signal is output from the output port 1. (Turns on).

  In addition, the CPU 56 loads the special symbol process flag (step S1062), compares the value of the special symbol process flag with the special winning opening opening pre-processing designation value (“4”) (step S1063), and sets the special symbol process flag. It is determined whether or not the value is less than 4 (step S1064). When the value of the special symbol process flag is less than 4 (Y in step S1064), the process proceeds to step S1069. When the value of the special symbol process flag is 4 or more (N in step S1064), the contents of the big hit symbol determination buffer are loaded and it is confirmed whether or not it is a big hit of 15 rounds (step S1067). Whether or not it is a big hit of 15 rounds can be determined, for example, by confirming the contents of the big hit symbol determination buffer set in the special symbol normal process. For example, the jackpot symbol determination buffer stores the contents of the jackpot type determined by the special symbol normal processing and the contents indicating the jackpot determination result. For example, “1” is a normal jackpot, “2” is a probable bonus jackpot, “3” is suddenly a big hit. If the contents of the big hit symbol determination buffer are “1” or “2”, it is determined that the number of rounds at the big hit is 15 rounds. In this case, the big output 3 output bit position of the information buffer is set (step S1068). When the jackpot 3 output bit position is set, the information buffer is set to the output value in the subsequent step S1100, and the output value is output to the output port 1 in step S1101, whereby the jackpot 3 signal is output from the output port 1. (Turns on).

  By the processing of steps S1050 to S1068 described above, one big hit signal, two big hit signals, three big hit signals, and a short time signal are output (turned on) according to the type of big hit and the gaming state.

  Next, the CPU 56 loads the security signal information timer (step S1069), reflects the state of the security signal information timer in the flag register (step S1070), and determines whether the security signal information timer has timed out (step S1070). S1071). In this embodiment, it is determined that the detection difference between the start opening switch 14a and the winning confirmation switch 14b is outside the normal range (for example, “10” or more or less than “−10”), and an abnormal winning at the start winning opening is determined. When it is determined that the alarm has occurred, a predetermined time (4 minutes in this example) is set in the security signal information timer, and the security signal output time at the time of abnormal start winning is set (step S126 in the switch normal / abnormality check process). , S127), when the predetermined time has not elapsed, it is determined that the security signal information timer has not timed out, and when the predetermined time has elapsed (when the value of the security signal information timer is 0), It is determined that the security signal information timer has timed out.

  Further, in this embodiment, when the power supply to the gaming machine is started and the initialization process is executed, a predetermined time (30 seconds in this example) is set in the security signal information timer and the initialization process is performed. Security signal output time is set (see step S13 in the game control main process), and when the predetermined time has not elapsed, it is determined that the security signal information timer has not timed out, and the predetermined time has elapsed (When the value of the security signal information timer is 0), it is determined that the security signal information timer has timed out.

  If the security signal information timer has not timed out (N in step S1071), the security signal information timer is decremented by 1 (step S1072), and the calculation result is stored in the security signal information timer (step S1073). Then, the security signal output bit position (bit 7 of output port 1 in the example shown in FIG. 24) of the information buffer is set (step S1074). When the security signal output bit position of the information buffer is set, the security signal is output from the output port 1 by setting the information buffer to the output value in the subsequent step S1100 and outputting the output value to the output port 1 in step S1101. Is output (turns on). If the security signal information timer times out (Y in step S1071), the security signal is turned off as a result of not executing the process in step S1074.

  The process of steps S1069 to S1074 described above is executed until 4 minutes have elapsed after the abnormal winning at the start winning opening 14 is detected, or 30 minutes after the initialization process is executed at the start of power supply to the gaming machine. Until the second elapses, a security signal is output using the common connector CN8 of the terminal board 160. If a new abnormal prize is detected during the output of the security signal, the output of the security signal is continued until 4 minutes have elapsed since the last abnormal prize was detected.

  Next, the CPU 56 determines whether or not the gaming machine specific information is being output (step S1081). When the gaming machine specific information is being output (Y in step S1081), the process proceeds to step S1087. When the gaming machine unique information is not being output (N in step S1081), for example, by checking whether or not the unique information output request flag is set, whether or not the gaming machine unique information is output is set. Determination is made (step S1082). If there is no output setting of the gaming machine specific information (N in Step S1082), the process proceeds to Step S1100. When there is an output setting for gaming machine specific information (Y in step S1082), the first external device that is the output destination of gaming machine specific information is designated (step S1083). For example, the CPU 56 reads the output destination designation data stored at the start address of the unique information output destination table, and outputs the output destination of the gaming machine unique information indicated by the output destination designation data as header information of the gaming machine unique information. For example, the first external device as the output destination may be specified. Alternatively, at the output port of the gaming control microcomputer 560, game machine specific information is assigned to a plurality of bits corresponding to a plurality of external devices that are the output destinations of the game machine specific information, and the output ports correspond to the external devices that are the output destinations. The game machine specific information may be output from different bits. Alternatively, at the output port of the gaming control microcomputer 560, external device designation information for designating an external device that is the output destination of the gaming machine specific information is assigned to a bit different from the bit assigned to the gaming machine specific information, and output. External device designation information for designating a previous external device may be output separately from the gaming machine specific information.

  Thereafter, the CPU 56 reads the first 1 bit of the gaming machine specific information (step S1084). For example, the CPU 56 selectively reads the first 1 bit of the gaming machine unique information from the reading start address of the gaming machine unique information set in the unique information read pointer. At this time, the CPU 56 is not limited to directly reading only the first 1 bit of the gaming machine specific information, but based on the gaming machine specific information read in units of a predetermined number of bytes (for example, 1 byte). A value (“0” or “1”) may be specified. As an example, after reading 1 byte of data from the head of the gaming machine specific information, the CPU 56 sets a predetermined value for mask (specifically, 10000000) prepared for specifying the value of the head 1 bit. Logical AND. The calculation result is reflected in the flag register, and if the zero flag is on, the value of the first 1 bit is “0”, and if the zero flag is off, the value of the first 1 bit is specified as “1”. That's fine.

  Further, the CPU 56 sets a value corresponding to 1-bit output time in the 1-bit unique information timer (step S1085). Then, a bit value corresponding to the read result in step S1084 or the like is set in the gaming machine specific information output bit position of the information buffer (bit 2 of output port 1 in the example shown in FIG. 24) (step S1086). When the gaming machine specific information output bit position of the information buffer is set, the information buffer is set to the output value in the subsequent step S1100, and the output value is output to the output port 1 in step S1101, thereby the gaming machine specific information The included 1-bit data value is output from the output port 1.

  When the gaming machine unique information is being output in step S1081 (Y in step S1081), the CPU 56 loads the 1-bit unique information timer (step S1087) and reflects the state of the 1-bit unique information timer in the flag register. In step S1088, it is determined whether the 1-bit unique information timer has timed out (step S1089). In this embodiment, when the gaming machine specific information is output bit by bit in the serial signal system, a predetermined time is set in the 1-bit specific information timer in accordance with the 1-bit output time (see step S1085). When the time has not elapsed, it is determined that the 1-bit unique information timer has not timed out, and when the predetermined time has elapsed (when the value of the 1-bit unique information timer is 0), the 1-bit unique information timer Is determined to have timed out.

  If the 1-bit unique information timer has not timed out (N in step S1089), the 1-bit unique information timer is decremented by 1 (step S1090), and the calculation result is stored in the 1-bit unique information timer (step S1091). At this time, the bit value of the gaming machine specific information similar to that read last time in the processing of step S1084, S1092 or step S1094 is read (step S1092). Note that the CPU 56 holds the previously read bit value in a built-in register or the like, not only the one that reads the bit value of the gaming machine specific information similar to the one read last time, and stores this in the current register. It may be used again as a bit value. Thereafter, the process proceeds to step S1086, and a bit value corresponding to the read result is set in the information buffer.

  Further, when the 1-bit unique information timer times out in step S1089 (Y in step S1089), the CPU 56 determines whether or not the output of all bits included in the gaming machine unique information is completed (step S1093). . For example, if the address set in the unique information read pointer matches a predetermined end address and the output of the last bit read from the address has been completed, all bits included in the gaming machine unique information Is determined to be complete. If the output of all bits has not been completed (N in step S1093), the next 1 bit included in the gaming machine specific information is read (step S1094). As a method of reading the bit value in step S1094, any method may be used as long as the method of reading the first one bit in step S1084 is applied to other bits. If all the bits of the gaming machine specific information read from the address set in the unique information read pointer have been output, the value of the unique information read pointer is incremented by 1, and the gaming machine specific information is started from the next address. One bit of information may be read out. Thereafter, the process proceeds to step S1085, and the 1-bit unique information timer is set.

  In addition, if all bits have been output in step S1093 (Y in step S1093), the CPU 56 determines whether or not there is a next output destination for the gaming machine specific information (step S1095). For example, the CPU 56 determines whether there is an external device that has not yet output the gaming machine specific information among the external devices that are the output destination of the gaming machine specific information indicated by the output destination designation data read from the specific information output destination table. Determine whether. If there is no next output destination (N in step S1095), the process proceeds to step S1100. If there is a next output destination (Y in step S1095), the next external device as the output destination of the gaming machine specific information is designated (step S1096). For example, the CPU 56 reads the output destination designation data stored at the next address in the unique information output table, and outputs the output destination of the gaming machine unique information indicated by the output destination designation data as the header information of the gaming machine unique information. For example, the next external device as the output destination may be specified. Thereafter, the process proceeds to step S1084, and the first 1 bit of the gaming machine specific information is read.

  Through the processing of steps S1081 to S1096 described above, the gaming machine specific information is sequentially read out bit by bit, and the gaming machine specific information is output by the serial signal method using the connector CN3 of the terminal board 160. The CPU 56 is not limited to outputting the game machine specific information by software using a serial signal system, and the game machine specific information may be output using a serial signal system as hardware. For example, the CPU 56 sequentially reads out the gaming machine specific information in units of a predetermined number of bytes (for example, 1 byte) and supplies it to a serial output circuit built in or externally attached to the gaming control microcomputer 560. Thereby, the gaming machine specific information may be output by a serial signal system in units of a predetermined number of bytes (for example, 1 byte).

  Further, the external device that is the output destination of the gaming machine specific information is designated by the processing of steps S1083 and S1096 described above. The CPU 56 is not limited to the one in which the external device that is the output destination of the gaming machine specific information is specified by software, but the gaming machine specific information is transmitted to the plurality of external devices using a signal line branched into a plurality by the hardware configuration. May be output. For example, a hardware configuration using any one of a wiring pattern on the substrate of the main substrate 31 or the terminal substrate 160, a wiring connection outside the substrate, or a wiring or bus configuration in a predetermined IC chip, The signal line for transmitting the gaming machine specific information may be branched into a plurality. With such a hardware configuration, the game machine specific information output from the game control microcomputer 560 may be transmitted to a plurality of external devices, even if the processing of steps S1083 and S1096 is not executed.

  Use of a serial output circuit built in or externally attached to the game control microcomputer 560, output of game machine specific information as a serial signal system in units of a predetermined number of bytes (for example, 1 byte), and signal lines depending on the hardware configuration The game machine specific information may be output to the external device by a configuration including a part or all of the branching.

  The gaming machine specific information may be configured to be externally output from a common connector CN8 that outputs a security signal on the terminal board 160. In this case, even at the output port of the game control microcomputer 560, as shown in FIG. 69 (A), for example, from the common bit position (for example, bit number 7 of the output port 1) where the security signal is output, The unique information may be output by a serial signal system. In the information output process, when the game machine specific information is output from the output port or connector common to the security signal, a process for avoiding the conflict between the two may be executed. For example, as shown in FIG. 69B, when it is determined in step S1082 that there is an output setting for gaming machine specific information (Y in step S1082), it is determined whether or not the security signal information timer has timed out. (Step S1082a). If the security signal information timer has not timed out (N in step S1082a), since the security signal is being output, the output setting of the gaming machine specific information is retained (step S1082b), and the process of step S1100 is performed. Transition. Further, before executing the process of step S1069 shown in FIG. 67, it is determined whether or not the gaming machine specific information is being output. For example, the CPU 56 determines whether or not the 1-bit unique information timer has timed out, and determines that the gaming machine unique information is being output if it has not timed out. If the gaming machine specific information is being output, the process of steps S1069 to S1074 may not be executed, and the process may proceed to step S1081.

  In addition, a bit for outputting game machine specific information is assigned to an output port of the game control microcomputer 560 separately from a bit for outputting a security signal. A circuit configuration for outputting machine specific information may be provided. For example, the terminal board 160 is provided with a buffer circuit capable of temporarily storing each of the security signal and the gaming machine specific information, and a reading circuit for reading the stored contents in these buffer circuits and supplying them to the common connector CN8. When only one of the security signal and the gaming machine specific information is transmitted from the main board 31 to the terminal board 160, the transmitted signal or information is supplied to the common connector CN8 to the external device. Output. Further, when both the security signal and the gaming machine specific information are transmitted from the main board 31 to the terminal board 160, either the security signal or the gaming machine specific information is first buffered based on a predetermined priority setting. Is read out from the buffer circuit and supplied to the common connector CN8. After the output is completed, the other is read out from the buffer circuit and supplied to the common connector CN8. As a priority when outputting the security signal and the gaming machine specific information, for example, the security signal may always be given priority over the gaming machine specific information, or the gaming machine specific information may always be given priority over the security signal. May be output. Alternatively, either one of the security signal and the gaming machine specific information transmitted from the main board 31 to the terminal board 160 is output first, and after the output is completed, the other transmitted is continued. You may make it output.

  Next, the CPU 56 checks whether or not the on-state signal output flag is on (step S1099A). In response to the start of external output of the on-time state signal, the on-time state signal output flag is set to the on state in step S1099C described later. If the on-state signal output flag is off (N in step S1099A), it is determined whether there is an instruction to output the on-state signal (step S1099B). In this embodiment, in addition to the fact that the initialization process is not executed when the gaming machine is turned on, in addition, when data indicating the special gaming state is stored in a predetermined area of the RAM 55, A signal output instruction is set (see step S93 in the game control main process).

  When an instruction to output the on-state signal is set (Y in step S1099B), the on-state signal outputting flag is set to the on state (step S1099C). If the on-state signal output flag is on in step S1099A (Y in step S1099A), it is determined whether the on-state signal output stop condition is satisfied (step S1099D).

  The condition for stopping the output of the on-time state signal may be satisfied, for example, when the first big hit gaming state is controlled after the gaming machine is turned on. Alternatively, when a gaming ball that first passes through the start winning opening 14 after the power is turned on by the gaming machine is detected by the start opening switch 14a, or when it is controlled to the first probability change state after the gaming machine is turned on, When the number of variable displays executed after turning on the power reaches a predetermined number, or when the elapsed time from the turning on of the gaming machine reaches a predetermined time, the game balls launched into the gaming area 7 after turning on the power Even if the condition for stopping the output of the on-time state signal is satisfied at any predetermined timing, such as when the number reaches the predetermined number or when the operation of the clear switch 914 is detected after the power is turned on Good.

  When the input state signal output flag is set to ON in step S1099C, or when it is determined in step S1099D that the output stop condition for the input state signal is not satisfied (N in step S1099D), the information buffer The state signal output bit position at the time of input (bit 3 of output port 0 in the example shown in FIG. 24) is set (step S1099E). When the input state signal output bit position of the information buffer is set, the information buffer is set to the output value in the subsequent step S1100, and the output value is output to the output port 0 in step S1101, so that the input state signal is Output from output port 0 (becomes ON state).

  If it is determined in step S1099D that the condition signal output stop condition has been satisfied (Y in step S1099D), the input condition signal output flag is cleared and turned off (step S1099F). If there is no instruction for outputting the on-state signal in step S1099B (N in step S1099B), or if the output stop condition on the on-state signal is satisfied in step S1099D (Y in step S1099D), step S1099E As a result of the processing not being executed, the on-state signal is turned off.

  The output instruction for the on-time state signal may only be set when the gaming machine is turned on (see step S93 of the game control main process), and no output instruction is set thereafter. Therefore, after the game progress is started after the game machine is turned on, even when data indicating the special game state is stored, the on-time state signal is not output externally. Limited. In addition, after starting the external output of the power-on state signal based on the output instruction at the time of power-on, and after stopping the external output of the power-on state signal due to the establishment of the output stop condition, data indicating the special gaming state Even when stored, the state signal at the time of closing is limited so that it is not output externally.

  Next, the security signal output timing will be described. FIG. 70 is an explanatory diagram showing the output timing of the security signal. In this embodiment, when initialization processing is executed at the start of power supply to the gaming machine (see steps S10 and S11 in FIG. 27), a predetermined time (30 seconds in this example) is set in the security signal information timer. Based on this (see step S13), the information output process (see step S31 in FIG. 28) performs steps S1069 to S1074, S1100, and S1101, and as shown in FIG. A security signal is output from the connector CN8 of the board 160 to an external device such as a hall computer. Further, after the power supply to the gaming machine is started, the detection error between the detection number of the start port switch 14a and the detection number of the winning confirmation switch 14b becomes a predetermined value (10 in this example) or more. Even when it is determined that an abnormal winning at the start winning opening 14 has occurred (see steps S121 to S126), the predetermined time (4 minutes in this example) is set in the security signal information timer. (See step S127), the information output process (see step S31) performs steps S1069 to S1074, S1100, and S1101, and, as shown in FIG. A security signal is output to an external device such as a computer. As described above, in this embodiment, the common connector of the terminal board 160 is used when the initialization process is executed when power supply to the gaming machine is started and when an abnormal winning to the start winning opening 14 is detected. A security signal is externally output from CN8.

  In this embodiment, when the security signal is being output to the outside and a new abnormal winning is detected at the start winning opening 14, the security signal output period is substantially extended. The output of the security signal is continued until a predetermined time (4 minutes in this example) elapses from the time when the abnormal winning to the start winning opening 14 is detected. For example, in the case where the output of the security signal is started based on the fact that the initialization process is executed when the power supply to the gaming machine is started, as shown in FIG. Security signal output should continue. However, as shown in FIG. 70B, even before 30 seconds have elapsed, the detection error between the number of detections of the start port switch 14a and the number of detections of the winning confirmation switch 14b is a predetermined value (in this example, 10) As described above, there is a possibility that it is determined that an abnormal winning to the start winning opening 14 has occurred. In this case, a predetermined time (in this example, 4 minutes) is overwritten and written in the security signal information timer based on the detection of the occurrence of the abnormal winning (see step S127), and the information output process (step S31). Step S1069 to S1074, S1100, and S1101 are executed, and the output of the security signal is continued as shown in FIG. 70B. However, since the value of the security signal information timer has been overwritten to 4 minutes, in this case, as shown in FIG. 70 (B), 4 minutes have elapsed since the abnormal winning to the start winning opening 14 was detected. Until then, the output of the security signal is continued, and the output of the security signal is substantially extended.

  Further, for example, when the output of the security signal is started based on the detection of the abnormal winning at the start winning opening 14, as shown in FIG. 70 (A), in principle, the security signal is output until 4 minutes elapse. Output should continue. However, as shown in FIG. 70C, even before the lapse of 4 minutes, the detection error between the number of detections of the start port switch 14a and the number of detections of the winning confirmation switch 14b is a predetermined value (in this example, 10) As described above, there is a possibility that it is determined that an abnormal winning to the start winning opening 14 has newly occurred. In this case, a predetermined time (4 minutes in this example) is overwritten and written in the security signal information timer based on the newly detected occurrence of an abnormal winning (see step S127), and information output processing ( In step S31), the processing of steps S1069 to S1074, S1100, and S1101 is executed, and as shown in FIG. 70C, the output of the security signal is continued. However, since the value of the security signal information timer is overwritten to 4 minutes, in this case, as shown in FIG. 70 (C), 4 minutes from the time when the abnormal winning to the start winning opening 14 is newly detected. The output of the security signal is continued until elapses, and the output of the security signal is substantially extended.

  When an abnormal winning to the start winning port 14 is detected while the security signal is already being output, the output of the security signal being output is terminated and the output of the next security signal is started again. In this embodiment, as shown in FIGS. 70 (B) and 70 (C), the output time of the security signal being output is extended as it is, so that the security signal is output. In addition to reducing the processing burden on processing, the program capacity for security signal output processing is reduced. In other words, when it is configured to start the output of the next security signal after the output of the security signal being output is completed, the output of the next security signal is started after the output of the security signal is completed. For example, a process for measuring the interval time until completion is required, which increases the processing load and the program capacity. On the other hand, in this embodiment, since the value of the security signal information timer is overwritten as it is, if only the process of setting the value of the security signal information timer is performed (see steps S13 and S127), the security signal is output. It is possible to prevent the increase in processing load and program capacity.

  In this embodiment, when an initialization process is executed at the start of power supply to the gaming machine, a security signal is output for 30 seconds, and an abnormal winning at the start winning opening 14 is detected. Shows the case where the security signal is output over 4 minutes, but the output time of the security signal is not limited to that shown in this embodiment. In other words, it is possible to recognize whether the initialization process has been executed or whether an abnormal winning at the start winning opening 14 has been detected. What is necessary is just to output a security signal over output time different from the case where is detected.

  In this embodiment, the output period of the security signal when an abnormal winning to the start winning opening 14 is detected is set to 4 minutes in the case of an abnormal winning to the starting winning opening 14 as long as possible. This is a substantially maximum time that can be set in order to output a security signal over time. That is, in this embodiment, since the game control microcomputer 560 can set a 2-byte value as the value of the security signal information timer, the maximum value is set to “FFFF (H) = 65535 in the security signal information timer. "Can be set. Therefore, in this embodiment, “60000”, which is almost the maximum value, is set in the security signal information timer, and the timer interruption period is 4 ms. Therefore, security is performed for 4 ms × 60000 = 4 minutes. A signal is output.

  Next, the output timing of game machine specific information will be described. FIG. 71 is an explanatory diagram showing the output timing of the gaming machine specific information. In this embodiment, at the start of power supply to the gaming machine, after the power supply voltage reaches a predetermined voltage and the gaming control microcomputer 560 is activated as shown in FIG. Based on the setting (see step S13), the information output process (see step S31) performs the processes of steps S1081 to S1096, S1100, and S1101, and as shown in FIG. The gaming machine specific information is output from the connector CN3 of the board 160 to an external device such as a hall computer. As described above, in this embodiment, when the power to the gaming machine is turned on, it is assumed that the information output condition is satisfied, and the gaming machine specific information is externally output by the serial signal method from the connector CN3 of the terminal board 160 or the like.

  In this embodiment, at the time of big hit when the gaming state becomes the big hit gaming state, as shown in FIG. 71 (B1), one big hit signal or two big hit signals are turned on, and output setting of the gaming machine specific information is performed. Based on the above (see step S138), the information output process (see step S31) performs the processes of steps S1081 to S1096, S1100, and S1101, and as shown in FIG. 71 (B2), the connector of the terminal board 160 The gaming machine specific information is output from CN3 or the like to an external device such as a hall computer. As described above, in this embodiment, the game machine specific information is output by the serial signal method from the connector CN3 of the terminal board 160 and the like, assuming that the information output condition is satisfied at the time of big hit. With the output of the gaming machine specific information at the time of the big hit, one big hit signal or two big hit signals are output to an external device such as a hall computer as a status signal indicating that the big hit gaming state.

  Further, in this embodiment, when power is being supplied to the gaming machine, as shown in FIG. 71 (C1) when the door is opened by the door opening switch 155a or the door opening switch 155b. Based on the fact that the door opening signal is turned on and the output setting of the gaming machine specific information is performed (see step S398c), the processing of steps S1081 to S1096, S1100, and S1101 is executed in the information output process (see step S31). Then, as shown in FIG. 71 (C2), the gaming machine specific information is output from the connector CN3 of the terminal board 160 to an external device such as a hall computer. As described above, in this embodiment, when the door is opened, it is assumed that the information output condition is satisfied, and the game machine specific information is output from the connector CN3 of the terminal board 160 by the serial signal method. Along with the output of the gaming machine specific information when the door is opened, a door opening signal is output to an external device such as a hall computer as a state signal indicating a state where the door or the like is opened.

  When the power supply to the gaming machine is stopped and being backed up, the door opening switch 155a or the door opening switch 155b can detect the opening of the door or the like by the voltage applied from the backup power source 507, and the door When the door is opened, as shown in FIG. 71D, an on-door door opening signal is output to an external device such as a hall computer. At this time, since the game control microcomputer 560 is in an operation stop state, the game machine specific information is not output to an external device such as a hall computer. Thus, after the power supply to the gaming machine is started, the door opening signal indicating that the opening of the door or the like has been detected and the gaming machine specific information are output to an external device such as a hall computer, while being supplied to the gaming machine. When the power supply is stopped, only the door opening signal is output to the external device. Since the gaming machine specific information is output to the external device, the external device can determine the legitimacy of the gaming machine unique information, and the illegal act by replacing the chip of the gaming control microcomputer 560 in the gaming machine In addition, it is possible to quickly find an illegal act by exchanging the main board 31. Rapid discovery of fraud can also improve deterrence against fraud and prevent fraud.

  Next, the output timing of the on-state signal will be described. FIG. 72 is an explanatory diagram showing the output timing of the on-state signal. In this form of execution, at the start of power supply to the gaming machine, initialization processing is executed after the power supply voltage reaches a predetermined voltage and the gaming control microcomputer 560 is activated as shown in FIG. If the power failure recovery setting is made (see step S91 in FIG. 27), the data indicating the special gaming state is stored, for example, because the probability change flag formed in a predetermined area of the RAM 55 is on. Based on this, an instruction to output the on-time state signal is issued (see step S93 in FIG. 27). In the information output process, the processes of steps S1099A to S1099F, S1100, and S1101 are executed, and, as shown in FIG. A status signal is output. Thus, in this embodiment, when the power to the gaming machine is turned on, the clear signal from the clear switch 914 is not input (N in step S7 in FIG. 27), and the initialization process is not executed. In addition, based on the fact that the data indicating the special gaming state is stored in a predetermined area of the RAM 55, a closing state signal is externally output from the connector CN9 of the terminal board 160 or the like.

  Thus, after the external output of the on-state signal is started, the external output of the on-state signal is continuously performed until a predetermined output stop condition is satisfied. For example, the number of variable displays executed after turning on the gaming machine until it is controlled to the first jackpot gaming state after turning on the gaming machine, or until it is controlled to the first certain change state after turning on the gaming machine Cleared after turning on the power until the number of game balls fired to the game area 7 after turning on the power reaches the predetermined number until the elapsed time from turning on the gaming machine reaches the predetermined time until the number reaches the predetermined number The on-state signal can be continuously output to the outside until a predetermined output stop condition such as until the operation of the switch 914 is detected.

  FIG. 73 is an explanatory diagram showing a configuration example of a game information processing system including an external device that can receive various signals output from the pachinko gaming machine 1 and gaming machine specific information and execute various processes. In the configuration example shown in FIG. 73, as an external device to which various signals from the pachinko gaming machine 1, gaming machine specific information, and the like are input, a gaming hall where the pachinko gaming machine 1 is installed (the gaming hall A in the example shown in FIG. 73). The card unit 50, the stand terminal device 770, and the hall computer 771 are provided.

  The card unit 50 is a game-related device provided along with the pachinko gaming machine 1, and a plurality of the pachinko gaming machine 1 and the card unit 50 are provided as a set. ) Or the like as long as it can be identified.

  The terminal device 770 is provided on a plurality of game islands arranged in the game hall, and stores various information (game related information) related to games in the gaming machine based on various data transmitted from the plurality of pachinko gaming machines 1. Any relay terminal device may be used as long as it is aggregated and the aggregated value of the aggregated game-related information is transmitted to the hall computer 771 or the like. The stand terminal device 770 may be a computer system configured to include a communication circuit, a control circuit (including a microcomputer), a storage device (ROM, RAM, hard disk, or flash memory), for example.

  The hall computer 771 is provided at a predetermined location (for example, a management office) in the game arcade and is connected to be able to communicate with a plurality of terminal devices 770, and collects game-related information output from each of the terminal devices 770. It is only necessary to manage the operation status of each gaming machine in a centralized manner. The hall computer 771 includes, for example, a communication circuit, a control circuit (including a microcomputer), a storage device (ROM or RAM, a hard disk or flash memory), an input device (keyboard or mouse), an output device (display, speaker, printer) and the like. Any computer system that is provided and configured may be used. The hall computer 771 may be one that centrally manages game-related information using one computer system, or one that distributes and manages game-related information using a plurality of computer systems or recording devices (databases, etc.). There may be.

  The stand terminal device 770 and the hall computer 771 only need to constitute a game management device. The calling lamp provided above the pachinko gaming machine 1 is also configured to be included in one set with the pachinko gaming machine 1 and the card unit 50, and various signals output from the pachinko gaming machine 1 and information specific to the gaming machine, etc. May also be transmitted to this ringing lamp. The calling lamp may be any game information display device that displays game information (for example, game state, number of starts, number of jackpots, etc.) in a gaming machine such as the pachinko gaming machine 1 to the player. Various signals output from the pachinko gaming machine 1, gaming machine specific information, and the like may be transmitted from the calling lamp to the hall computer 771 after being transmitted to the calling lamp. Alternatively, various signals and gaming machine specific information output from the pachinko gaming machine 1 are branched outside the pachinko gaming machine 1 (for example, an internal circuit of the base terminal device 770), and the calling lamp and the hall computer 771 It may be transmitted toward. Alternatively, various signals output from the pachinko gaming machine 1, gaming machine specific information, and the like may be transmitted from the hall computer 771 toward the calling lamp after being once transmitted to the hall computer 771.

  In addition, a relay computer that relays various information externally output from the base terminal device 770 and transmits the information to the hall computer 771 may be provided between the base terminal device 770 and the hall computer 771. In addition to the hall computer 771, a member management computer for managing member information related to a player registered as a member at each game hall is provided, and the game machine specific information output from the pachinko gaming machine 1 It may be transmitted to a management computer or the like. The pachinko gaming machine 1 includes a terminal device 770 and a hall computer 771 via a communication cable or network communication device (for example, a repeater represented by a repeater hub, a bridge or router represented by a switching hub, or a gateway terminal). Even if each device is given a network address (IP address, MAC address, etc.) and can output game machine specific information etc. to the outside by accessing the local area network (LAN) Good.

  The card unit 50 is connected to a card terminal device or a card management computer via a communication cable or a network communication device, and can externally output card related information related to a membership card, a prepaid card, etc. Also good. The card unit 50 may be configured to further externally output various signals externally output from the pachinko gaming machine 1 and gaming machine specific information together with the card related information. In this way, various signals output from the pachinko gaming machine 1 and gaming machine specific information may be transmitted to a card terminal device, a card management computer, or the like. Various signals output from the pachinko gaming machine 1 and gaming machine specific information may be transmitted from the card unit 50 to the hall computer 771 after being transmitted to the card unit 50. Alternatively, various signals and gaming machine specific information output from the pachinko gaming machine 1 are branched outside the pachinko gaming machine 1 (for example, an internal circuit of the base terminal device 770), and the card unit 50 and the hall computer 771 are branched. And may be transmitted toward. Alternatively, various signals output from the pachinko gaming machine 1, gaming machine specific information, and the like may be transmitted from the hall computer 771 toward the card unit 50 after being once transmitted to the hall computer 771.

  Outside the game hall where the pachinko gaming machine 1 is installed, for example, a general management device 773 serving as an external device capable of receiving the gaming machine specific information output from the pachinko gaming machine 1 to a management organization different from the gaming hall. May be provided. The management organization may be, for example, a management office of an entity that manages each game hall (game hall A, game hall B,...), And the gaming machine installed in each game hall is appropriate. It may be a third-party organization (a business cooperative, a general incorporated association, a public interest incorporated association, an administrative organization, etc.) for managing The overall management device 773 may have a function of processing management information such as the operating status and sales of the gaming machines installed in each game hall, and conformity with the standards of the gaming machines installed in each gaming hall. It is not necessary to have a function of processing management information only by processing only information related to the above.

  The gaming machine specific information output from the pachinko gaming machine 1 is once aggregated by the hall computer 771 or the like, and then via a telecommunication network that becomes a wide area network (WAN) such as the Internet or a dedicated line. , It may be transmitted to the overall management device 773 installed in the management organization. Alternatively, the gaming machine unique information output from the pachinko gaming machine 1 by either the base terminal device 770 or the relay computer may be aggregated and then transmitted to the overall management device 773. Alternatively, the pachinko gaming machine 1 may be capable of externally outputting gaming machine specific information and the like by accessing a wide area network via a communication cable or a network communication device. In this case, the gaming machine specific information output from the pachinko gaming machine 1 may not be collected by the hall computer 771 or the like but may be individually transmitted to a management organization outside the gaming hall. When the game machine unique information is aggregated by the hall computer 771 or the like and transmitted to the overall management device 773 of the management organization, the information output condition for outputting the game machine unique information from the pachinko machine 1 is established. At this point, the game machine specific information or the like may be immediately transmitted to the overall management device 773, or it is collected when a predetermined date and time arrives or when a predetermined output instruction operation is performed. The game machine specific information or the like may be transmitted to the overall management device 773.

  Transmission destinations (output targets) such as various signals output from the pachinko gaming machine 1 and gaming machine specific information are made different depending on which information output condition is satisfied among a plurality of types of information output conditions. It may be. As a specific example, when the power is turned on, the card unit 50 and the hall computer 771 are transmission destinations. When the jackpot is hit, the hall computer 771 and the calling lamp are transmission destinations. When the door is opened, only the hall computer 771 is the transmission destination. It may be. For example, various signals output from the pachinko gaming machine 1 or game machine specific information may be constantly transmitted to the hall computer 771 regardless of which of the multiple types of information output conditions is satisfied. Good. Like the hall computer 771, transmission destinations such as various signals and game machine specific information may always include transmission destinations regardless of which of the multiple types of information output conditions is satisfied. Good. Alternatively, depending on which of the multiple types of information output conditions is met, only those that may or may not be the transmission destination of various signals and game machine specific information may be external devices. Good.

  Alternatively, each output destination (output target) may be made different in accordance with various types of signals output from the pachinko gaming machine 1 or the type of gaming machine specific information. As a specific example, the security signal may be transmitted to the card unit 50, the hall computer 771, and the calling lamp, and the gaming machine specific information and the on-time state signal may be transmitted only to the hall computer 771. . The game management device is not limited to the base terminal device 770 or the hall computer 771, but based on various signals output from the pachinko gaming machine 1 and game machine specific information, a game generated in connection with a game on the game machine Any information processing apparatus that manages related information may be used. More specifically, a card unit 50 installed adjacent to the pachinko gaming machine 1, a calling lamp serving as a game information display device, or the like may have a function as a game management device.

  In the game control microcomputer 560, for example, in the unique information output destination table stored in advance in the ROM 54, the information output condition and the external device to be the transmission destination (output target) are set so as to be associated with each other. Just do it. When the CPU 56 designates the external device that is the output destination of the gaming machine specific information in steps S1083 and S1096 (see FIG. 68), the external device associated with the established information output condition is output as the specific information. What is necessary is just to be able to specify by a destination table etc. Note that the output destination of the game machine specific information is not limited to the one on which the game machine specific information is output by the CPU 56 of the game control microcomputer 560 on the main board 31 side, for example, the output destination of the game machine specific information is determined on the terminal board 160 side. A circuit configuration or the like may be provided. More specifically, a look-up table (LUT) corresponding to the specific information output destination table is provided on the terminal board 160, and status signals (one big hit signal, two big hit signals, and a door opening signal) input to the input side connector. Based on the above, the output destination of the gaming machine specific information may be designated according to the established information output condition. For various signals different from the gaming machine specific information, the output destination may be specified in the same manner as the gaming machine specific information.

  Alternatively, various signals and gaming machine-specific information can be obtained by wiring patterns on the main board 31 or terminal board 160, by wiring connection outside the board, or by wiring or bus configuration within a predetermined IC chip. It may be output to a plurality of external devices after being branched into a plurality.

  As described above, the external device that is the transmission destination (output target) of various signals and gaming machine specific information output from the pachinko gaming machine 1 is not limited to each configuration shown in FIG. 73, but is shown in FIG. Various devices that are not included may be included, and each configuration illustrated in FIG. 73 may not be included in the transmission destination (output target). That is, the transmission destination (output target) of the gaming machine specific information can be arbitrarily set.

  Next, notification signal processing based on various signals output from the pachinko gaming machine 1 and gaming machine specific information will be described. FIG. 74 is a flowchart showing notification signal processing executed by the game management device such as the stand terminal device 770 and the hall computer 771. In the game management device, the notification signal processing may be repeatedly executed after the microcomputer is started by turning on the power.

  In the notification signal processing shown in FIG. 74, first, it is determined whether or not a security signal has been received (step S601). Here, the security signal is a first state specification for specifying that the initialization process is executed at the time of power-on in the gaming machine or that a predetermined error such as occurrence of an abnormal start winning in the gaming machine has occurred. Signal. That is, in the process of step S601, at least a first state specifying signal for specifying that a predetermined initialization process has been executed in the gaming machine or that a predetermined error has occurred in the gaming machine has been received. It is determined whether or not.

  When a security signal is received (Y in step S601), a predetermined initialization process is executed when power supply is started in the gaming machine, and a predetermined error occurs. It is recognized that the state 1 has occurred, and operation control is performed when a security signal is received (step S602). As an example, in the process of step S602, the gaming machine that externally outputs the security signal is identified based on the machine number or the like of the gaming machine that externally outputs the security signal, and the gaming machine is informed that the security signal has been received. It is only necessary to perform a notification operation to notify the user in an identifiable manner. In the game management device, for example, displaying a notification image on a display, outputting a notification sound from a speaker, turning on a notification lamp, transmitting a notification signal by wireless communication or wired communication, or The notification operation at the time of receiving the security signal may be performed by combining some or all of these. In addition, information (data) indicating that the gaming machine that externally outputs the security signal can be specified may be stored in a predetermined storage device together with information indicating the reception date and time.

  Subsequently, it is determined whether or not a closing state signal has been received (step S603). Here, the state signal at the time of insertion is used to specify that data indicating a special gaming state is stored in addition to the fact that the initialization process is not executed when power supply is started in the gaming machine. It becomes a 2nd state specific signal. That is, in the process of step S603, in order to specify that data indicating a specific gaming state is stored in addition to the fact that the predetermined initialization process is not executed when power supply is started in the gaming machine. It is determined whether the second state specifying signal is received.

  When the power-on state signal is received (Y in step S603), in addition to the fact that the predetermined initialization process is not executed when power supply is started in the gaming machine, data indicating a specific gaming state is present. Recognizing that the stored second state has occurred, operation control is performed when the on-state signal is received (step S604). As an example, in the process of step S604, based on the machine number of the gaming machine that externally outputs the on-time state signal, the gaming machine that externally output the on-time state signal is identified and the on-time state signal is received. The notification operation | movement which alert | reports the game machine so that identification is possible should just be performed with alerting | reporting. In the game management device, for example, displaying a notification image on a display, outputting a notification sound from a speaker, turning on a notification lamp, transmitting a notification signal by wireless communication or wired communication, or The notification operation at the time of receiving the on-time state signal may be performed by combining some or all of them.

  Subsequently, it is determined whether or not the gaming machine specific information has been received (step S605). When the gaming machine unique information is received (Y in step S605), it is determined whether or not the received gaming machine unique information has been registered (step S606). If the gaming machine unique information has not been registered (N in step S606), settings for registering the gaming machine unique information are performed (step S607). In the gaming management apparatus, a data table for registering gaming machine specific information for each gaming machine may be created and stored in a predetermined storage device.

  If the gaming machine unique information has been registered (Y in step S606), the received gaming machine unique information is collated with the already registered gaming machine unique information (step S608). Based on the comparison result, it is determined whether or not the gaming machine specific information matches (step S609). If the game machine specific information does not match (N in step S609), operation control is performed when an abnormality is determined that an abnormality has occurred in the game machine specific information (step S610). As an example, in the process of step S610, the gaming machine that externally outputs the gaming machine specific information is identified based on the machine number of the gaming machine that externally outputs the gaming machine specific information, and the mismatch of the gaming machine specific information is detected. A notification operation for notifying that the gaming machine can be specified is performed together with the notification to that effect. In the game management device, for example, displaying a notification image on a display, outputting a notification sound from a speaker, turning on a notification lamp, transmitting a notification signal by wireless communication or wired communication, or By combining some or all of these, a notification operation at the time of abnormality determination of gaming machine specific information may be performed. In addition, information (data) indicating that a gaming machine having externally output gaming machine specific information can be specified may be stored in a predetermined storage device together with information indicating a reception date and time.

  Next, the operation | movement using the game machine specific information etc. which were externally output from the pachinko game machine 1 is demonstrated. FIG. 75 is an explanatory diagram showing a case where the gaming machine specific information output from the pachinko gaming machine 1 is transmitted to the hall computer 771. As shown in FIG. 75 (A), the gaming machine specific information transmitted from the main board 31 to the terminal board 160 inside the pachinko gaming machine 1 is sent through various devices or other devices. Directly to the hall computer 771. The hall computer 771 only needs to execute processing for determining the legitimacy of the gaming machine specific information output from the pachinko gaming machine 1.

  As an example, the hall computer 771 determines whether or not there is an abnormality in the pachinko gaming machine 1 by using the gaming machine specific information output when the power of the pachinko gaming machine 1 is turned on. More specifically, as shown in FIG. 75 (B), when power is turned on on the first day when the pachinko gaming machine 1 is installed in the game hall, the game machine specific information output from the pachinko gaming machine 1 is registered. Processing is executed. At this time, in the hall computer 771, for example, for each pachinko gaming machine 1 connected to the terminal device 770, a data table is created for registering gaming machine specific information in association with the number of each machine, etc. What is necessary is just to memorize | store in an apparatus. The game machine specific information registered in the data table is displayed on a display device (display) provided in the hall computer 771 according to a predetermined display instruction operation, for example, so that the manager of the game hall can check it. It may be.

  After the gaming machine unique information corresponding to each pachinko gaming machine 1 is registered in the hall computer 771 in this way, for example, the gaming machine unique information output from the pachinko gaming machine 1 when the power is turned on in each business day is displayed on the side of the hall computer 771. Get in. Then, based on the comparison result between the registered gaming machine specific information (registered information) and the acquired gaming machine specific information (acquired information), a match is confirmed or a mismatch is detected. For example, as shown in FIG. 75B, when a coincidence with the registered information is detected when the power is turned on on the second day, it is determined that there is no abnormality, and a normal management process or the like is executed. Thereafter, if a mismatch with the registered information is detected when the power is turned on on the α-th day, it may be determined that an abnormality has occurred and an alarm process for generating an alarm may be executed. In the alarm processing, for example, an alarm screen is displayed on a display device (display) included in the hall computer 771, an alarm sound is output from a speaker included in the hall computer 771 or a speaker connected to the hall computer 771, and the hall computer 771 is output. Control to execute an alarm operation including a part or all of the lighting of the connected alarm lamp may be performed. Further, by executing alarm processing in the hall computer 771, an alarm screen may be displayed on a display device provided at a predetermined position of the game hall, or an alarm is issued from a speaker provided at the predetermined position of the game hall. A sound may be output, or an alarm lamp provided at a predetermined position in the game hall may be turned on. Or alarm information may be transmitted to the communication terminal which the staff of a game hall carries, and you may make it alert | report the generation | occurrence | production of abnormality.

  By determining that an abnormality has occurred when the power is turned on on the α-th day, the chip of the game control microcomputer 560 is replaced or the main board 31 is replaced at least after the power-on of the previous day. It can be presumed that fraud has occurred. Therefore, it is possible to limit the time when the fraudulent act is performed, and it is possible to increase the possibility that the fraudulent act is prevented.

  As another example, the hall computer 771 determines whether there is an abnormality in the pachinko gaming machine 1 using the gaming machine unique information output at the time of the big hit of the pachinko gaming machine 1. More specifically, as shown in FIG. 75 (C), when the power is first turned on in the pachinko gaming machine 1, a process for registering the gaming machine specific information output from the pachinko gaming machine 1 is executed. Here, when the power is turned on for the first time, similarly to the example of FIG. 75 (B), the power may be turned on on the first day when the pachinko gaming machine 1 is installed in the amusement hall, or in FIG. 75 (B). Unlike the example, it may be when the power of the pachinko gaming machine 1 is first turned on in each business day. The process for registering the gaming machine specific information may be the same process as in the example of FIG.

  After the game machine specific information corresponding to each pachinko gaming machine 1 is registered in the hall computer 771 in this way, for example, during the game with the pachinko gaming machine 1, the pachinko gaming machine 1 at the time of the big hit when the variable display result becomes “big hit” Is obtained on the side of the hall computer 771. And based on the comparison result of registration information and acquisition information, a match is confirmed or a mismatch is detected. For example, as shown in FIG. 75C, when a match with the registered information is detected at the first big hit, it is determined that there is no abnormality, and a normal management process or the like is executed. Thereafter, if a mismatch with the registered information is detected at the α-th big hit, it is determined that an abnormality has occurred, and an alarm process for generating an alarm may be executed. The alarm process may be the same process as in the example of FIG.

  In this way, it is determined that an abnormality has occurred at the α-th big hit, so that at least after the previous big hit, an illegal operation such as changing the chip of the game control microcomputer 560 or replacing the main board 31 It can be presumed that the action was performed. Therefore, it is possible to limit the time when the fraudulent act is performed, and it is possible to increase the possibility that the fraudulent act is prevented.

  As yet another example, the hall computer 771 determines whether there is an abnormality in the pachinko gaming machine 1 using the gaming machine specific information output when the door of the pachinko gaming machine 1 is opened. More specifically, as shown in FIG. 75D, when the power is first turned on in the pachinko gaming machine 1, a process for registering the gaming machine specific information output from the pachinko gaming machine 1 is executed. Thereafter, for example, the hall computer 771 obtains the game machine specific information output from the pachinko machine 1 when the door is opened before the power supply in the pachinko machine 1 is stopped. To do. And based on the comparison result of registration information and acquisition information, a match is confirmed or a mismatch is detected. For example, as shown in FIG. 75 (D), when coincidence with the registered information is detected when the door is opened for the first time, it is determined that there is no abnormality, and normal management processing or the like is executed. Thereafter, if a mismatch with the registered information is detected at the α-th door opening, it is determined that an abnormality has occurred and an alarm process for generating an alarm may be executed.

  In this way, when it is determined that an abnormality has occurred when the α-th door is opened, fraud is caused by changing the chip of the game control microcomputer 560 or replacing the main board 31 at least after the previous door opening. It can be presumed that the action was performed. Therefore, it is possible to limit the time when the fraudulent act is performed, and it is possible to increase the possibility that the fraudulent act is prevented.

  When game machine specific information or the like is output from the pachinko gaming machine 1 to the hall computer 771, for example, information indicating the management number (identification number) of the pachinko gaming machine 1 in the game hall or the pachinko gaming machine 1 in the gaming hall The information indicating the installation position (for example, part or all of the island number or the unit number) is also output to the outside so that on the hall computer 771 side, the gaming machine specific information transmitted from which gaming machine It may be possible to specify. Alternatively, the base terminal device 770 is provided with a plurality of connection ports individually assigned port numbers to the plurality of pachinko gaming machines 1 connected to the respective terminal devices. It is sufficient that the signal line is connected to each connection port. In this case, even if the management number and the information indicating the installation position are not output from the pachinko gaming machine 1, for example, the management number of the terminal device 770 or the gaming machine is transmitted from the terminal device 770 to the hall computer 771. By transmitting the port number assigned to the connection port of the pachinko gaming machine 1 to which the unique information is output, the hall computer 771 identifies which gaming machine is the unique information transmitted from the gaming machine can do.

  FIG. 76 is an explanatory diagram showing a case where the gaming machine specific information output from the pachinko gaming machine 1 is transmitted to the card unit 50. As shown in FIG. 76A, the gaming machine specific information transmitted from the main board 31 to the terminal board 160 inside the pachinko gaming machine 1 is transmitted to the card unit 50. The card unit 50 only needs to execute processing for determining the legitimacy of the gaming machine specific information output from the pachinko gaming machine 1.

  As an example, the card unit 50 determines whether or not there is an abnormality in the pachinko gaming machine 1 using the gaming machine unique information output when the power of the pachinko gaming machine 1 is turned on. More specifically, as shown in FIG. 76 (B), when power is turned on on the first day when the pachinko gaming machine 1 is installed in the game hall, the game machine specific information output from the pachinko gaming machine 1 is registered. Processing is executed. Here, since the card unit 50 is installed adjacent to the pachinko gaming machine 1, it is not necessary to create a data table as in the case of the hall computer 771, and the gaming machine output from the pachinko gaming machine 1 is not necessary. The unique information may be stored in a predetermined storage device.

  After the gaming machine unique information output from the adjacent pachinko gaming machine 1 is registered in the card unit 50 in this way, for example, the gaming machine unique information output from the pachinko gaming machine 1 when the power is turned on in each business day is stored in the card unit 50. Get on the side. And based on the comparison result of registration information and acquisition information, a match is confirmed or a mismatch is detected. For example, as shown in FIG. 76 (B), when coincidence with the registration information is detected when the power is turned on on the second day, it is determined that there is no abnormality and normal card processing or the like is executed. Thereafter, if a mismatch with the registered information is detected when the power is turned on on the α-th day, it may be determined that an abnormality has occurred and an alarm process for generating an alarm may be executed. In the alarm processing, for example, an alarm is displayed on a display device (liquid crystal screen, segment LED, etc.) provided in the card unit 50 or a display device connected to the card unit 50, and an alarm sound is output from a speaker connected to the card unit 50. It is only necessary to perform control for executing an alarm operation including a part or all of the alarm lamp, the alarm lamp included in the card unit 50, and the alarm lamp connected to the card unit 50. Further, by executing an alarm process in the card unit 50, an alarm screen may be displayed on a display device provided at a predetermined position of the game hall, or an alarm is issued from a speaker provided at a predetermined position of the game hall. A sound may be output, or an alarm lamp provided at a predetermined position in the game hall may be turned on. Or alarm information may be transmitted to the communication terminal which the staff of a game hall carries, and you may make it alert | report the generation | occurrence | production of abnormality.

  As another example, the card unit 50 determines whether there is an abnormality in the pachinko gaming machine 1 using the gaming machine specific information output at the time of the big hit of the pachinko gaming machine 1. More specifically, as shown in FIG. 76 (C), when the power is first turned on in the pachinko gaming machine 1, processing for registering the gaming machine specific information output from the pachinko gaming machine 1 is executed. Here, when the power is turned on for the first time, similarly to the example of FIG. 76 (B), the power may be turned on on the first day when the pachinko gaming machine 1 is installed in the amusement hall, or in FIG. 76 (B). Unlike the example, it may be when the power of the pachinko gaming machine 1 is first turned on in each business day. The process for registering the gaming machine specific information may be the same process as in the example of FIG.

  After the game machine specific information of the adjacent pachinko gaming machine 1 is registered in the card unit 50 in this way, for example, when the game is played on the pachinko gaming machine 1, the variable display result is “big hit”. The output gaming machine specific information is acquired on the card unit 50 side. And based on the comparison result of registration information and acquisition information, a match is confirmed or a mismatch is detected. For example, as shown in FIG. 76C, when a match with the registered information is detected at the first big hit, it is determined that there is no abnormality, and normal card processing or the like is executed. Thereafter, if a mismatch with the registered information is detected at the α-th big hit, it is determined that an abnormality has occurred, and an alarm process for generating an alarm may be executed.

  As yet another example, the card unit 50 determines whether there is an abnormality in the pachinko gaming machine 1 using the gaming machine specific information output when the door of the pachinko gaming machine 1 is opened. More specifically, as shown in FIG. 76 (D), when power is first turned on in the pachinko gaming machine 1, a process for registering the gaming machine specific information output from the pachinko gaming machine 1 is executed. Thereafter, for example, on the card unit 50 side, the gaming machine specific information output from the pachinko gaming machine 1 when the door is opened before the power supply in the pachinko gaming machine 1 is stopped is opened. To do. And based on the comparison result of registration information and acquisition information, a match is confirmed or a mismatch is detected. For example, as shown in FIG. 76 (D), when coincidence with the registered information is detected when the door is opened for the first time, it is determined that there is no abnormality and normal card processing or the like is executed. Thereafter, if a mismatch with the registered information is detected at the α-th door opening, it is determined that an abnormality has occurred and an alarm process for generating an alarm may be executed.

  When gaming machine specific information is output from the pachinko gaming machine 1 to the card unit 50, the card unit 50 is installed adjacent to the pachinko gaming machine 1, so that the management number and installation of the pachinko gaming machine 1 are set. There is no need to externally output information indicating the position.

  Next, the operation of the payout control means (the payout control microcomputer 370) will be described. FIG. 77 is an explanatory diagram showing an example of output port assignment in the payout control means. As shown in FIG. 77, each phase signal supplied to the payout motor 289 by the stepping motor is output from the output port 0. In addition, a PRDY signal or an EXS signal is output from the output port 0 to the card unit 50, and a game indicating that the gaming machine is in an error state (in this example, a ball-out error state or a full tank error state). A machine error state signal and a prize ball signal 1 indicating that a prize ball payout has been detected are also output. Further, from the output port 1, each segment output signal of the error display LED 374 by 7 segment LED is output. The output port 1 also outputs prize ball information indicating that ten prize ball payouts have been detected.

  FIG. 78 is an explanatory diagram showing an example of bit assignment of input ports in the payout control means. As shown in FIG. 78, the VL signal, the BRDY signal, and the BRQ signal from the card unit 50 are input to bits 0 to 2 of the input port 0, respectively. A connection signal from the main board 31 is input to bit 4 of the input port 0. In addition, the detection signal of the full switch 48, the detection signal of the ball break switch 187, and the detection signal of the payout motor position sensor 295 are input to the bits 5 to 7 of the input port 0, respectively. In addition, the operation signal from the error release switch 375 and the detection signal of the payout number count switch 301 are input to the bits 0 and 1 of the input port 1, respectively.

  Next, the operation of the payout control means will be described. FIG. 79 is a flowchart showing a main process executed by the payout control means. In the main process, the payout control CPU 371 of the payout control microcomputer 370 first performs necessary initial settings. That is, the payout control CPU 371 first sets the interruption prohibition (step S701). Next, the interrupt mode is set to interrupt mode 2 (step S702), and a stack pointer designation address is set to the stack pointer (step S703).

  Next, the payout control CPU 371 sets a built-in device register (step S704). In the process of setting the internal device register in step S704, the payout control CPU 371 sets the CTC. In this embodiment, one channel of the built-in CTC is used in the timer mode. Therefore, the payout control CPU 371 performs register setting for setting the channel to be used to timer mode, register setting for permitting interrupt generation, and register setting for setting an interrupt vector. The interrupt by the channel is used as a timer interrupt. For example, when it is desired to generate a timer interrupt every 1 ms, a value corresponding to 1 ms is set as an initial value in a predetermined register (time constant register).

  In step S704, the payout control CPU 371 initializes the priority of interrupt processing to be executed in response to the interrupt request from the serial communication circuit 380. In this case, the payout control CPU 371 initializes the priority order of the interrupt process according to the same process as the priority order initial setting process (see step S15b) performed by the CPU 56 of the game control microcomputer 560.

  In step S <b> 704, the payout control CPU 371 sets the serial communication circuit 380. In this case, the payout control CPU 371 sets the baud rate of the receiving circuit, sets the receiving mode (either 8-bit or 9-bit data format), and sets the parity (the presence or absence of parity, even parity or odd parity). Set). In addition, the control registers of the receiving circuit are initialized and the status registers are initialized. Also, the payout control CPU 371 sets the baud rate of the transmission circuit, sets the transmission mode (either 8-bit or 9-bit data format), and sets the parity (the presence / absence of parity, even parity or odd parity) )I do. Also, each control register of the transmission circuit is initialized.

  The interrupt vector set for the channel set to the timer mode (channel 3 in this embodiment) corresponds to the start address of the timer interrupt process. Specifically, the start address of the timer interrupt process is specified by the value set in the I register and the interrupt vector. In the timer interruption process, a payout control process for controlling the payout means (including at least a process of driving the ball payout device 97 in response to a command signal related to award ball payout from the main board, and a ball payout device 97 in response to a ball lending request. A process for driving the program may be included.

  In this embodiment, the interruption mode 2 is also set in the payout control microcomputer 370. Therefore, an interrupt process based on counting up the built-in CTC can be used. Also, an interrupt processing start address can be set according to the interrupt vector sent by the CTC. The interrupt based on CTC channel 3 (CH3) count-up is an interrupt that occurs when the CPU internal clock (system clock) counts down and the register value becomes “0”, and is used as a timer interrupt. .

  Next, the payout control CPU 371 sets the RAM in an accessible state (step S705), and performs a RAM clear process (step S706). In addition, initial values are set in the flags and counters of the RAM area (step S707). Note that the processing in step S707 includes processing for setting the unpaid-off number counter initial value in the unpaid-out number counter. In the process of step S707, the payout control CPU 371 also performs a process of clearing an error flag indicating a detection state of a payout number abnormality error, a full tank error, and a ball breakage error. In this embodiment, when it is determined that there is a payout number error and the payout number error error specification bit is set in the error flag, the payout number error error specification bit is not cleared until the power is reset. Although it does not recover from the number abnormality error, specifically, when the process of step S707 is executed when the power is turned on, the payout number abnormality error designation bit in the error flag is cleared and the payout number abnormality error is recovered.

  The payout control CPU 371 executes serial communication circuit setting processing for initial setting of the serial communication circuit 380 (step S708). In this case, the payout control CPU 371 causes the serial communication circuit 380 to serially communicate with the game control microcomputer 560 according to the same process as the serial communication circuit setting process (see step S15a) performed by the CPU 56 of the game control microcomputer 560. Make settings for Further, as described above, a part of the initial setting of the serial communication circuit 380 is executed in the built-in device register setting process in step S704. Note that all the setting processing of the serial communication circuit 380 may be performed by the serial communication circuit setting processing in step S708.

  Since interruption is prohibited in step S701 of the initial setting process, interruption is permitted before the initialization process is completed (step S709). Thereafter, a loop process for monitoring the occurrence of a timer interrupt is entered.

  As described above, in this embodiment, the built-in CTC of the payout control microcomputer 370 is set so as to repeatedly generate a timer interrupt. When a timer interrupt occurs, the payout control CPU 371 of the payout control microcomputer 370 executes a timer interrupt process.

  FIG. 80 is a flowchart showing an example of timer interrupt processing executed by the payout control means. In the timer interrupt process, the payout control CPU 371 of the payout control microcomputer 370 executes the following process. First, the payout control CPU 371 performs a switch check process (step S751). In the switch check process, the payout control CPU 371 performs a process of confirming the on / off state of the payout number count switch 301 and the error release switch 375 based on the input of the input port 1. Next, the payout control CPU 371 performs an input determination process (step S752). The input determination process is a process for detecting the state of bits 0 to 7 (see FIG. 78) of the input port 0 and reflecting the detection result in a predetermined 1 byte of the RAM (referred to as a sensor input state flag). The payout control CPU 371 checks the state of the sensor input state flag instead of directly checking the state of the input port when performing control based on the state of bits 0 to 7 of the input port 0.

  Next, the payout control CPU 371 executes a prepaid card unit control process for communicating with the card unit 50 (step S753). Next, the payout control CPU 371 executes main control communication processing for communicating with the game control means of the main board 31 (step S754). Next, the payout control CPU 371 performs control for paying out the lent balls in response to a ball lending request from the card unit 50, and performs control for paying out the number of prize balls indicated by the prize ball number command from the main board 31. A payout control process to be executed is executed (step S755).

  Next, the payout control CPU 371 executes a payout motor control process (step S756). In the payout motor control process, when the payout motor 289 is to be driven, a process for outputting the patterns of the payout motors φ1 to φ4 to the output port 0 is performed.

  Next, the payout control CPU 371 executes error processing for detecting various errors (step S757). Next, the payout control CPU 371 executes a prepaid card unit error control process for performing error control of the card unit 50 (step S758). Next, the payout control CPU 371 executes information output processing for outputting prize ball information to the main board 31 and outputting the prize ball signal 1 and the gaming machine error state signal to the outside (step S759). Further, display control processing for performing a predetermined display on the error display LED 374 according to the result of the error processing is executed (step S760).

  In the present embodiment, when various errors (for example, a payout number error error, a full tank error, a ball shortage error, a prepaid card unit unconnected error) are detected in error processing to be described later, an error corresponding to the detected error is detected. Bit is set. Then, in the display control process of step S760, the payout control CPU 371 performs a predetermined display on the error display LED 374 based on the error bit being set.

  In this embodiment, a RAM area (output port 0 buffer, output port 1 buffer) corresponding to the output state of the output port is provided. However, the payout control CPU 371 includes an output port 0 buffer and an output port. The contents of the port 1 buffer are output to the output port (step S761: output processing). The output port 0 buffer and the output port 1 buffer include a payout motor control process (step S756), a prepaid card control process (step S753), a main control communication process (step S754), an information output process (step S759), and a display control process ( It is updated in step S760).

  FIG. 81 is a flowchart showing the main control communication process in step S754. In the main control communication process, the payout control microcomputer 370 (specifically, the payout control CPU 371) executes a main control command reception process (step S740). Then, the payout control CPU 371 executes one of steps S741 to S744 according to the value of the main control communication control code.

  FIG. 82 is a flowchart showing the main control command reception process of step S740 in the main control communication process. In the main control command reception process, the payout control CPU 371 first checks whether or not a connection signal is input (step S7401). If no connection signal is input, the payout control CPU 101 initializes the transmission circuit and the reception circuit of the serial communication circuit 380 (step S7402). As described above, when the connection signal cannot be received, the transmission circuit and the reception circuit of the serial communication circuit 380 are initialized, so that the command is transmitted even though the connection state with the main board 31 is abnormal. It is possible to prevent a situation in which data is stored in the register or the reception data register. Next, the payout control CPU 371 loads the value of the main control communication control code (step S7403), and checks whether or not the value of the main control communication control code is a value “0” indicating the main control connection confirmation process. (Step S7404).

  In this embodiment, in the main control communication process, input of a connection signal from the game control microcomputer 560 is started after power supply to the gaming machine is started, and reception of the first connection confirmation command can be confirmed. The main control connection confirmation process in step S741 is executed. Then, when the reception of the connection confirmation command can be confirmed, the process proceeds to step S742 and subsequent steps, and transmission / reception processing of various payout control commands is executed. Thereafter, if the communication state with the game control microcomputer 560 is maintained normally, one of the processes of steps S742 to S744 is executed, and the main control connection confirmation process of step S741 is basically a game. It will be executed only when the machine is powered on. In step S7404, the fact that the value of the main control communication control code indicates a value other than the main control connection confirmation processing means that after shifting to the processing after step S742, some communication error occurs and the connection signal cannot be input. This is the case. Therefore, when the value of the main control communication control code indicates a value other than the main control connection confirmation process in step S7404, the payout control CPU 371 determines the main control communication error designation bit (game control microcomputer) of the error flag. A bit indicating that an abnormality has occurred in the communication state with 560) is set (step S7405). The error flag is a flag in which various prize ball errors are set, and is formed in a RAM provided in the payout control microcomputer 370. Then, the payout control CPU 371 sets a value “0” indicating main control connection confirmation processing in the main control communication control code (step S7406). If the value of the main control communication control code is “0” indicating the main control connection confirmation process in step S7404, the process proceeds to step S7406.

  Note that the main control confirmation process in step S741 may be executed exceptionally even after the power is turned on to the gaming machine. Specifically, as described above, after determining that a connection signal is not input in step S7401, if the main control connection confirmation process is not being executed in step S7404, the connection signal is not displayed after power is turned on to the gaming machine. It is determined that there is a possibility of being disconnected, and the process returns to the main control connection confirmation process (see step S7406), and again confirms the connection state with the game control microcomputer 560 (specifically, a connection confirmation command is issued). Confirm that it can be received (see step S7412). Further, in the main control communication normal processing described later, even if a predetermined period (1050 ms in this example) has elapsed since the connection OK command was transmitted, the connection confirmation command and the prize ball number command are received from the game control microcomputer 560. If not, it is determined that some communication abnormality has occurred, and the process returns to the main control connection confirmation process (see steps S74202 and S74203), and the connection state with the game control microcomputer 560 is confirmed again (specifically, Confirm that the connection confirmation command can be received (see step S7412).

  If the connection signal is input, the payout control CPU 371 checks whether or not the reception error flag is set in the status register of the serial communication circuit 380 (step S7407). For example, the payout control CPU 371 receives the serial communication circuit 380 if a flag indicating a parity error, framing error, noise error, overrun error, or idle line error is set in the status register of the serial communication circuit 380. It is determined that there is an error state.

  If the reception error flag is set, the payout control CPU 371 initializes the reception circuit of the serial communication circuit 380 (step S7408). In this way, by initializing the receiving circuit of the serial communication circuit 380 in the case of a reception error state, it is possible to prevent a situation in which a reception command is stored in the reception data register even though some reception abnormality has occurred. can do. Then, the payout control CPU 371 sets the main control communication error designation bit of the error flag (step S7409).

  If the reception error flag is not set, the payout control CPU 371 loads the contents of the reception buffer (step S7410) and checks whether or not a connection confirmation command is received (step S7411). Specifically, the payout control CPU 371 checks whether or not the content of the loaded reception buffer is “A0 (H)” (see FIG. 30). If the connection confirmation command has been received, the payout control CPU 371 proceeds to step S7414.

  If a connection confirmation command has not been received, the payout control CPU 371 checks whether or not a prize ball number command has been received. In this embodiment, as shown in FIG. 30, the contents of the connection number command should be at least “51 (H)” and less than “60 (H)”. Accordingly, the payout control CPU 371 first checks whether or not the content of the loaded reception buffer is greater than or equal to the prize ball number command minimum value “51 (H)” (step S7412). Next, if the prize ball number command minimum judgment value is “51 (H)” or more, the payout control CPU 371 determines whether the content of the loaded reception buffer is less than the prize ball number command maximum judgment value “60 (H)”. It is confirmed whether or not (step S7413). If it is less than the winning ball number command maximum determination value “60 (H)”, the payout control CPU 371 determines that a winning ball number command has been received, and proceeds to step S7414.

  In step S7414, the payout control CPU 371 stores the contents of the reception buffer (connection confirmation command, prize ball number command) in the main control communication reception buffer. The main control communication reception buffer is composed of 1 byte and can store only one reception command at a time. Even with this configuration, in this embodiment, the timer interrupt period (1 ms in this example) in the payout control microcomputer 370 is equal to the timer interrupt period (in this example, the game control microcomputer 560). 4 ms), a situation in which a plurality of payout control commands are received within one timer interrupt does not occur, and there is no inconvenience. In addition, even if the award ball number command is received before receiving the first connection confirmation command due to erroneous processing after turning on the power to the gaming machine, the connection confirmation command is subsequently issued. If it is received, it is overwritten and stored in the main control communication reception buffer. Therefore, there is a situation in which the connection confirmation command cannot be confirmed at all in the main control connection confirmation process (step S741) described later, and it becomes impossible to shift to the main control communication normal process. Can be prevented.

  FIG. 83 is a flowchart showing main control connection confirmation processing (step S741) executed when the value of the main control communication control code is zero. In the main control connection confirmation process, the payout control CPU 371 loads the contents of the main control communication reception buffer (step S7411), and confirms whether or not a connection confirmation command is received (step S7412). If a connection confirmation command has been received, the payout control CPU 371 sets a connection OK command (step S7413) and executes main control transmission command conversion processing (step S7414). In the main control transmission command conversion process in step S7414, a process of setting a control state (an error state such as a payout number error error, a ball runout error, a full tank error, a prize ball error, etc.) in the lower 4 bits of the connection OK command is performed. Done. Then, the payout control CPU 371 performs control to transmit the converted connection OK command to the game control microcomputer 560 (step S7415). Specifically, the payout control CPU 371 performs processing for outputting a connection OK command to the transmission register of the serial communication circuit 380.

  The payout control CPU 371 clears the main control communication reception buffer when transmitting the connection OK command in step S7415. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “1” indicating the main control communication normal process in the main control communication control code (step S7416). Then, the payout control CPU 371 sets a predetermined value (1050 ms in this example) to the main control communication control timer (step S7417).

  84 and 85 are flowcharts showing main control communication normal processing (step S742) executed when the value of the main control communication control code is 1. In the main control communication normal process, the payout control CPU 371 subtracts 1 from the value of the main control communication control timer (step S74201), and checks whether the main control communication control timer has timed out (step S74202).

  In this embodiment, as described above, every time one second elapses after the connection OK command is received from the payout control microcomputer 370, the next connection confirmation command is transmitted from the game control microcomputer 560. Therefore, the fact that the main control communication control timer has timed out in step S7402 means that the next connection confirmation command is issued even if 1050 ms (see steps S7417 and S7409) elapses well after 1 second from the transmission of the connection OK command. This is a case where reception was not possible. For this reason, the payout control CPU 371 sets a value “0” indicating the main control connection confirmation process in the main control communication control code (step S7403), and returns to the main control connection confirmation process to wait for the recovery of the communication state. To do.

  If the main control communication control timer has timed out in step S74202, the payout control CPU 371 clears the main control communication reception buffer. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  If the main control communication control timer has not timed out, the payout control CPU 371 checks whether or not a reception command is stored in the main control communication reception buffer (step S74204). If a reception command is stored in the main control communication reception buffer, the payout control CPU 371 checks whether or not the received command is a connection confirmation command (step S74205). If a connection confirmation command has been received, the payout control CPU 371 sets a connection OK command (step S74206) and executes main control transmission command conversion processing (step S74207). In the main control transmission command conversion process in step S74207, a process for setting a control state (an error state such as a payout number error error, a ball out error, a full tank error, a prize ball error) in the lower 4 bits of the connection OK command is performed. Done. Then, the payout control CPU 371 performs control to transmit the converted connection OK command to the game control microcomputer 560 (step S74208). Specifically, the payout control CPU 371 performs processing for outputting a connection OK command to the transmission register of the serial communication circuit 380.

  The payout control CPU 371 clears the main control communication reception buffer when the connection OK command is transmitted in step S74208. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Then, the payout control CPU 371 sets a predetermined value (1050 ms in this example) in the main control communication control timer (step S74209).

  If the command received in step S74205 is not a connection confirmation command, it means that a prize ball number command has been received. In this case, the payout control CPU 371 checks whether or not the value of the error flag is 0 (step S74210). If the value of the error flag is not 0 (that is, if it is an error state and any error bit is set), the process proceeds to step S74219. If the value of the error flag is 0 (that is, if no error state is set and no error bit is set), the payout control CPU 371 checks whether a BRDY signal is input. (Step S74211). If the BRDY signal is input, the process proceeds to step S74219.

  If no BRDY signal is input, the payout control CPU 371 loads a payout control state flag indicating the payout control state (step S74212), and confirms whether the winning ball payout operation or the ball lending payout operation is in progress. (Step S74213). Specifically, the payout control CPU 371 specifies a prize ball payout operation designation bit (bit indicating that a prize ball payout operation is in progress) or a ball lending payout operation designation bit (in a ball lending payout operation) in the payout control state flag. It is confirmed whether or not a bit indicating that is set. If the winning ball payout operation or the ball lending payout operation is being performed, the process proceeds to step S74219. In this embodiment, since the next prize ball number command is transmitted after the prize ball payout operation is finished and the prize ball end command is received, the step is performed unless an abnormality such as a communication error occurs. In S74213, it is not determined that the prize ball payout operation is in progress.

  If neither the winning ball payout operation nor the ball lending payout operation is in progress, the winning ball payout operation based on the received winning ball number command can be started immediately. In this case, the payout control CPU 371 sets the lower 4 bits of the main control communication reception buffer (that is, the number of winning balls set in the winning ball number command) in the unpaid-out number counter (step S74214). The unpaid-out number counter is a counter for counting the number of unpaid out prize balls and rental balls.

  Next, the payout control CPU 371 performs control to transmit a prize ball number acceptance command to the game control microcomputer 560 (step S74215). Specifically, the payout control CPU 371 performs processing for outputting a prize ball number acceptance command to the transmission register of the serial communication circuit 380.

  The payout control CPU 371 clears the main control communication reception buffer when it transmits a prize ball number acceptance command in step S74215. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “3” indicating the main control communication end process in the main control communication control code (step S74216). Then, the payout control CPU 371 sets a predetermined value (1 second in this example) in the main control communication control timer (step S74218). It should be noted that if a prize ball payout operation is not completed after a lapse of one second after the prize ball number acceptance command is transmitted based on the value set in step S74218, a prize ball preparation command is transmitted.

  In step S74219, the payout control CPU 371 stores the lower 4 bits of the main control communication reception buffer (that is, the number of prize balls set with the prize ball number command) in the main control communication prize ball number buffer. That is, in this case, an error state has occurred, or during the winning ball payout operation, the ball lending payout operation, or during the ball lending preparation, the winning ball payout operation based on the received winning ball number command is immediately performed. Can't start. Therefore, the payout control CPU 371 suspends the reply of the prize ball number acceptance command and temporarily saves the prize ball number set in the prize ball number command in the main control communication prize ball number buffer.

  Next, the payout control CPU 371 sets a command for preparing a prize ball (step S74220), and executes main control transmission command conversion processing (step S74221). In the main control transmission command conversion process in step S74221, a control state (error state such as a payout number error error, a ball runout error, a full tank error, a prize ball error, etc.) is set in the lower 4 bits of the command for preparing a prize ball. Processing is performed. Then, the payout control CPU 371 performs control to transmit the converted prize ball preparing command to the game control microcomputer 560 (step S74222). Specifically, the payout control CPU 371 performs processing for outputting a prize ball preparing command to the transmission register of the serial communication circuit 380.

  Note that the payout control CPU 371 clears the main control communication reception buffer when the award ball preparing command is transmitted in step S74222. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “2” indicating the main control communication process to the main control communication control code (step S74223). Then, the payout control CPU 371 sets a predetermined value (1 second in this example) to the main control communication control timer (step S74224). It should be noted that, after the command for preparing a prize ball is transmitted based on the value set in step S74224, the command for preparing the next prize ball is transmitted if it is not ready to start the prize ball payout operation after one second has elapsed. Will be.

  86 and 87 are flowcharts showing main control communication in-process (step S743) executed when the value of the main control communication control code is 2. In the main control communication process, the payout control CPU 371 first checks whether or not a reception command is stored in the main control communication reception buffer (step S74301). If a reception command is stored in the main control communication reception buffer, the payout control CPU 371 checks whether or not the received command is a connection confirmation command (step S 74302). If it is not a connection confirmation command, the process proceeds to step S74306. If a connection confirmation command has been received, the payout control CPU 371 sets a connection OK command (step S74303) and executes main control transmission command conversion processing (step S74304). In the main control transmission command conversion process in step S74304, a process of setting a control state (an error state such as a payout number error error, a ball out error, a full tank error, a prize ball error) in the lower 4 bits of the connection OK command is performed. Done. Then, the payout control CPU 371 performs control to transmit the converted connection OK command to the game control microcomputer 560 (step S74305). Specifically, the payout control CPU 371 performs processing for outputting a connection OK command to the transmission register of the serial communication circuit 380. Then, the process proceeds to step S74306.

  In step S74306, the payout control CPU 371 sets a main control communication error designation bit in the error flag. That is, the main control communication process is a process that is executed after receiving the prize ball number command until the prize ball payout operation can be started based on the received prize ball number command. Since the response of the command is suspended, the game control microcomputer 560 is in a waiting state for receiving the award ball number reception command. During this time, a new payout control command is received from the game control microcomputer 560. There is no trap. Nevertheless, since receiving a new command can determine that some abnormality has occurred in the communication state, the payout control CPU 371 performs processing for setting a main control communication error designation bit.

  The payout control CPU 371 clears the main control communication reception buffer when the main control communication error designation bit is set in step S74306. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “1” indicating the main control communication normal process in the main control communication control code (step S74307). Then, the payout control CPU 371 sets a predetermined value (1050 ms in this example) in the main control communication control timer (step S74308).

  If there is no reception command in the main control communication reception buffer, the payout control CPU 371 subtracts 1 from the value of the main control communication control timer (step S74309), and checks whether the main control communication control timer has timed out (step S74309). S74310).

  If the main control communication control timer has timed out (Y in step S74310), it means that one second or more has elapsed since the previous prize ball preparation command was transmitted. In this case, the payout control CPU 371 sets a winning ball preparing command in order to transmit the next winning ball preparing command (step S74311), and executes main control transmission command conversion processing (step S74312). In the main control transmission command conversion process of step S74312, the control state (error status such as a payout number error error, a ball outage error, a full tank error, a prize ball error, etc.) is set in the lower 4 bits of the command for preparing a prize ball. Processing is performed. Then, the payout control CPU 371 performs control to transmit the converted prize ball preparing command to the game control microcomputer 560 (step S74313). Specifically, the payout control CPU 371 performs processing for outputting a prize ball preparing command to the transmission register of the serial communication circuit 380.

  Then, the payout control CPU 371 sets a predetermined value (1 second in this example) in the main control communication control timer (step S74314). It should be noted that, after the command for preparing a prize ball is transmitted based on the value set in step S74314, the command for preparing the next prize ball is not yet ready if the prize ball payout operation cannot be started after one second has passed. Will be sent.

  If the main control communication control timer has not timed out, the payout control CPU 371 checks whether or not the value of the error flag is 0 (step S74315). If the value of the error flag is not 0 (that is, if it is in an error state and one of the error bits is set), the winning ball payout operation cannot be started yet, so the processing is ended as it is. If the value of the error flag is 0 (that is, if no error state is set and no error bit is set), the payout control CPU 371 checks whether a BRDY signal is input. (Step S74316). If the BRDY signal has been input, the winning ball payout operation cannot be started yet, and the process is terminated as it is.

  If the BRDY signal is not input, the payout control CPU 371 loads a payout control state flag indicating the payout control state (step S74317), and confirms whether the winning ball payout operation or the ball lending payout operation is in progress. (Step S74318). Specifically, the payout control CPU 371 specifies a prize ball payout operation designation bit (bit indicating that a prize ball payout operation is in progress) or a ball lending payout operation designation bit (in a ball lending payout operation) in the payout control state flag. It is confirmed whether or not a bit indicating that is set. If the winning ball payout operation or the ball lending payout operation is in progress, the winning ball payout operation cannot be started yet, so the processing is ended as it is. In this embodiment, since the next prize ball number command is transmitted after the prize ball payout operation is finished and the prize ball end command is received, the step is performed unless an abnormality such as a communication error occurs. In S74318, it is not determined that a prize ball payout operation is in progress.

  If neither the winning ball payout operation nor the ball lending payout operation is in progress, it means that the winning ball payout operation based on the received winning ball number command can be started. In this case, the payout control CPU 371 sets the lower 4 bits of the main control communication prize ball number buffer (that is, the temporarily saved prize ball number) in the unpaid number counter (step S74319).

  In this embodiment, as described above, when the winning ball payout operation cannot be started immediately when the winning ball number command is received, the winning ball number specified by the winning ball number command is immediately set to the unpaid number. Instead of being set in the counter, it is temporarily saved in the main control communication award ball number buffer, but this control is performed, for example, by adding the award ball number to the unpaid number counter during the lending ball payout operation. This is to prevent inconvenience in processing related to payout control, such as preventing a situation where the number of winning balls cannot be accurately managed.

  Next, the payout control CPU 371 performs control to transmit a prize ball number reception command to the game control microcomputer 560 (step S74320). Specifically, the payout control CPU 371 performs processing for outputting a prize ball number acceptance command to the transmission register of the serial communication circuit 380.

  Next, the payout control CPU 371 sets a value “3” indicating the main control communication end process in the main control communication control code (step S74321). Then, the payout control CPU 371 sets a predetermined value (1 second in this example) in the main control communication control timer (step S74322). It should be noted that if a prize ball payout operation is not completed after a lapse of one second after the prize ball number acceptance command is transmitted based on the value set in step S74322, a prize ball preparing command is transmitted.

  FIG. 88 is a flowchart showing main control communication end processing (step S744) executed when the value of the main control communication control code is 3. In the main control communication end process, the payout control CPU 371 first checks whether or not a reception command is stored in the main control communication reception buffer (step S74401). If a reception command is stored in the main control communication reception buffer, the payout control CPU 371 checks whether or not the received command is a connection confirmation command (step S74402). If it is not a connection confirmation command, the process proceeds to step S74406. If a connection confirmation command has been received, the payout control CPU 371 sets a connection OK command (step S74403) and executes main control transmission command conversion processing (step S74404). In the main control transmission command conversion process of step S74404, a process of setting a control state (an error state such as a payout number error error, a ball out error, a full tank error, a prize ball error, etc.) in the lower 4 bits of the connection OK command. Done. Then, the payout control CPU 371 performs control to transmit the converted connection OK command to the game control microcomputer 560 (step S74405). Specifically, the payout control CPU 371 performs processing for outputting a connection OK command to the transmission register of the serial communication circuit 380. Then, control goes to a step S74406.

  In step S74406, the payout control CPU 371 sets a main control communication error designation bit in the error flag. That is, the main control communication end process is a process that is executed after receiving a prize ball number command and starting a prize ball payout operation until the prize ball payout operation based on the received prize ball number command is ended. Since the microcomputer for use 560 is in a waiting state for receiving the winning ball end command, it is unlikely that a new payout control command will be received from the game control microcomputer 560 during this period. Nevertheless, since receiving a new command can determine that some abnormality has occurred in the communication state, the payout control CPU 371 performs processing for setting a main control communication error designation bit.

  The payout control CPU 371 clears the main control communication reception buffer when the main control communication error designation bit is set in step S74406. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “1” indicating the main control communication normal process in the main control communication control code (step S74407). Then, the payout control CPU 371 sets a predetermined value (1050 ms in this example) in the main control communication control timer (step S74408).

  If there is no reception command in the main control communication reception buffer, the payout control CPU 371 subtracts 1 from the value of the main control communication control timer (step S74409), and checks whether the main control communication control timer has timed out (step S74409). S74410).

  If the main control communication control timer has timed out (Y in step S74410), it means that one second or more has elapsed since the last time a prize ball acceptance command or a prize ball preparation command was transmitted. In this case, the payout control CPU 371 sets a prize ball preparing command in order to transmit the next prize ball preparing command (step S74411), and executes main control transmission command conversion processing (step S74412). In the main control transmission command conversion process in step S74412, a control state (error state such as a payout number error error, a ball runout error, a full tank error, a prize ball error, etc.) is set in the lower 4 bits of the command for preparing a prize ball. Processing is performed. Then, the payout control CPU 371 performs control to transmit the converted prize ball preparing command to the game control microcomputer 560 (step S74413). Specifically, the payout control CPU 371 performs processing for outputting a prize ball preparing command to the transmission register of the serial communication circuit 380.

  Then, the payout control CPU 371 sets a predetermined value (1 second in this example) in the main control communication control timer (step S74414). It should be noted that, after the command for preparing a prize ball is transmitted based on the value set in step S74414, the command for preparing the next prize ball is transmitted if the prize ball payout operation is not yet completed after one second has passed. It will be.

  If the main control communication control timer has not timed out, the payout control CPU 371 loads a payout control state flag (step S74415), and checks whether or not a prize ball payout operation is in progress (step S74416). Specifically, the payout control CPU 371 checks whether or not a prize ball payout operation specifying bit is set in the payout control state flag. If the winning ball payout operation is in progress, it means that the winning ball payout operation based on the received winning ball number command has not been finished yet, and the payout control CPU 371 ends the process as it is. If no winning ball payout operation is in progress, it means that the winning ball payout operation based on the received winning ball number command has ended. Therefore, the payout control CPU 371 performs control to transmit a prize ball end command to the game control microcomputer 560 (step S74417). Specifically, the payout control CPU 371 performs a process of outputting a prize ball end command to the transmission register of the serial communication circuit 380.

  The payout control CPU 371 clears the main control communication reception buffer when it transmits the winning ball end command in step S74417. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “1” indicating the main control communication normal process in the main control communication control code (step S74418). Then, the payout control CPU 371 sets a predetermined value (1050 ms in this example) in the main control communication control timer (step S74419).

  FIG. 89 is a flowchart showing main control transmission command conversion processing executed in steps S7414, S74207, S74221, S74304, S74312, S74404, and S74412. In the main control transmission command conversion process, the payout control CPU 371 first loads an error flag and checks whether or not the payout number abnormality error designation bit is set (step S731). If the payout number abnormality error designation bit is set, the payout control CPU 371 sets a main control communication payout number error error output bit (specifically, bit 3) in the conversion buffer (step S732).

  Next, the payout control CPU 371 checks whether or not the ball break error designation bit is set (step S733). If the ball-out error designation bit is set, the payout control CPU 371 sets the main control communication ball-out output bit (specifically bit 2) in the conversion buffer (step S734).

  Next, the payout control CPU 371 checks whether or not the full error designation bit is set (step S735). If the full error specification bit is set, the payout control CPU 371 sets the full output bit for main control communication (specifically bit 1) of the conversion buffer (step S736).

  Next, the payout control CPU 371 checks whether or not other prize ball error designation bits are set (step S737). Specifically, the payout control CPU 371 includes a main control communication error designation bit, a main control unconnected error designation bit, a withdrawal switch abnormality detection error 1 designation bit, a withdrawal switch abnormality detection error 2 designation bit, a withdrawal in the error flag. Check if the case error specification bit is set. If any other prize ball error designation bit is set, the payout control CPU 371 sets a main control communication ball out output bit (specifically bit 0) in the conversion buffer (step S738).

  Then, the payout control CPU 371 sets the contents of the conversion buffer in the payout control command (connection OK command or prize ball preparing command) set for transmission (step S739).

  FIG. 90 is a flowchart showing the payout control process in step S755. In the payout control process, the payout control CPU 371 confirms that the detection signal of the payout number count switch 301 is turned on (step S7501), and checks whether the value of the unpaid number counter is 0. (Step S7502). If the value of the unpaid number counter is 0, the payout control CPU 371 adds 1 to the value of the payout number abnormality counter for counting the cumulative number of abnormal payouts (step S7503). In other words, Y in step S7502 means that the unpaid number to be paid out is not set in the unpaid-out number counter, so that the payout operation is performed even though the game ball should not be paid out. And the payout count switch 301 detects the payout of the game ball. For this reason, there is a possibility that the payout operation has been performed by some kind of fraud, so the payout control CPU 101 cumulatively adds 1 to the value of the payout number abnormality counter.

  The payout number abnormality counter indicates the number of payouts exceeding the number of unpaid game balls to be paid out and the number of payout shortages that did not meet the number of unpaid game balls to be paid out. This is a counter for cumulatively counting. As will be described later, in this embodiment, when the value of the payout number abnormality counter becomes equal to or greater than a predetermined payout number error error determination value (2000 in this example), it is determined that a payout number error has occurred and the payout is stopped. Processing to control the state is performed. Note that the process of step S7503 corresponds to a process of cumulatively counting the excess payout in the payout number abnormality counter.

  In this embodiment, without distinguishing whether the ball is a winning ball or a lending ball, the payout excess number and the payout shortage number are cumulatively counted in the payout number abnormality counter. For only one of the rented balls, the excessive payout and the shortage payout may be cumulatively counted in the payout number abnormality counter. Further, for example, with respect to prize balls and lending balls, it is possible to cumulatively count the excess payout and the shortage payout using separate counters. In this case, it may be determined that a payout number error occurs when the value of one of the counters reaches a predetermined threshold value, or a payout number error error when the total value of both counters reaches a predetermined threshold value. May be determined.

  Further, in this embodiment, the case where the value of the payout number abnormality counter is incremented by 1 when an excessive payout is detected in step S7503 has been shown, but the method of counting up the value of the payout number abnormality counter is described in this embodiment. It is not limited to what is shown in the form. For example, conversely, the excessive payout number may be subtracted from the value of the payout number abnormality counter, and the insufficient payout number may be added to the value of the payout number abnormality counter. In this case, for example, the payout control CPU 371 sets “2000” as the initial value in the payout number abnormality counter in the initial setting process when the power is turned on, and subtracts 1 from the value of the payout number abnormality counter in step S7503. In steps S75320, S75325, and S75335, which will be described later, a value corresponding to the insufficient payout number may be added to the value of the payout number abnormality counter. For example, in the processing of steps S7504, S75321, and S7725 described later, it may be determined that a payout number error has occurred based on the value of the payout number error counter being 2000 or less.

  Next, the payout control CPU 371 checks whether or not the value of the added payout number abnormality counter is equal to or greater than a predetermined payout number error error determination value (for example, 2000) (step S7504). If it is equal to or greater than a predetermined payout number error error determination value (for example, 2000), the payout control CPU 371 determines that a payout number error error has occurred, and indicates a payout number error error indicating that a payout number error error has occurred. A flag is set (step S7505). That is, in this embodiment, the number of abnormal payouts detected is cumulatively managed on the payout control microcomputer 370 side, and if the accumulated value is equal to or greater than a predetermined payout number abnormal error determination value (for example, 2000), It is determined that there is an extremely high possibility that a payout operation is being performed due to some sort of fraud, and it is determined that a payout number abnormality error (an error indicating that the number of game balls paid out is abnormal) has occurred. In addition, there are not a few cases where game balls are paid out excessively or insufficient due to malfunctions, etc., so when an abnormality in the number of payouts is detected, it is immediately determined as a payout number error. The frequency determined to be a payout number abnormality error becomes higher than necessary, and the game is hindered. Therefore, in this embodiment, the number of abnormal payouts detected is cumulatively managed, and the payout number abnormality error is determined on the condition that the accumulated value is equal to or greater than a predetermined payout number abnormality error determination value (for example, 2000). By determining, it is prevented that it is determined that the payout number abnormality error is more than necessary.

  In this embodiment, if it is determined that there is a payout number error and the payout number error error flag is set once, the payout number error error flag is not cleared until the power is reset, and the payout number error error is not recovered. When the payout number abnormality error flag is set, the processes in steps S7504 and S7505 and the processes in S75321, S75322, S7725, and S7726 described later may not be executed. By doing so, it is possible to prevent useless processing after it is once determined that the payout number abnormality error has occurred, and to reduce the processing burden.

  Further, in this embodiment, “2000”, which corresponds to the number of game balls that can be stored in a game ball storage box (so-called dollar box) generally used in a game store, is generally set as a predetermined payout number abnormality error determination value. Although the case where it uses is shown, other values (for example, 1000 or 3000) may be used as the predetermined payout number abnormality error determination value.

  In this embodiment, the payout control process shown in FIG. 90 is a process that is commonly executed when the prize ball payout operation is executed and when the lending ball payout operation is executed. This counter is used in common when counting the number of game balls that have not been paid out with prize balls and when counting the number of game balls that have not been paid out with lending balls. When an abnormality in the number of payouts is detected, the value of the payout number abnormality counter is incremented without distinguishing between payout with a prize ball and payout with a lending ball, and whether or not a payout number abnormality error has occurred. A determination is made.

  If the value of the unpaid-out number counter is not 0, the payout control CPU 371 subtracts 1 from the value of the unpaid-out number counter (step S7506), and the payout ball detection designation bit (game ball payout) is added to the flag of the payout control state. A bit indicating detection) is set (step S7507). The payout ball detection designation bit is a bit that is set when the payout number count switch 301 is turned on, and indicates that the payout number count switch 301 has detected at least one game ball during the payout operation. is there.

  Thereafter, the payout control CPU 371 executes any one of steps S7511 to S7513 according to the value of the payout control code.

  FIG. 91 is a flowchart showing a payout start waiting process (step S7511) executed when the payout control code is 0. In the payout start waiting process, the payout control CPU 371 first checks whether or not the value of the error flag is 0 (step S75101). If an error bit (one or more of all error bits in the error flag) is set, the payout control CPU 371 controls not to execute the subsequent processing. In this embodiment, by executing the processing of step S75101, it is determined that there is a payout number abnormal error, and the payout number abnormal error designation bit of the error bit is set, so that the steps after step S75102 are set. Control is performed so as not to shift to processing, and the payout is stopped.

  If the value of the error flag is 0, the payout control CPU 371 checks whether or not the BRDY signal is input (step S75102). If the BRDY signal is input, the payout control CPU 371 loads a payout control state flag (step S75103), and checks whether or not a ball lending request is being made (step S75104). Specifically, the payout control CPU 371 checks whether or not a ball lending request specifying bit (a bit indicating that a ball lending request is being made) is set in the payout control state flag. The payout control CPU 371 may determine whether or not a ball lending request is being made by confirming whether or not a BRQ signal is input. If a ball lending request is being made (that is, when a ball lending payout operation is started), the payout control CPU 371 resets the ball lending request specifying bit in the payout control state flag (step S75105) and at the same time a payout control state flag. The designated bit during the ball lending / dispensing operation is set (step S75016). Next, the payout control CPU 371 sets a predetermined ball lending number (25 in this example) in the unpaid number counter (step S75107) and a predetermined ball lending number (25 in this example) in the payout motor rotation number buffer. Is set (step S75108). Then, control goes to a step S75113.

  The payout motor rotation frequency buffer is referred to in the payout motor control process (step S756). That is, in the payout motor control process, control is performed to rotate the payout motor 289 by the number of rotations corresponding to the value set in the payout motor rotation frequency buffer.

  If the BRDY signal is not input, the payout control CPU 371 checks whether or not the value of the unpaid-out number counter is 0 (step S75109). If the value of the unpaid number counter is not 0 (that is, when the prize ball payout operation is started), the payout control CPU 371 sets the value of the unpaid number counter in the payout motor rotation number buffer (step S75110). That is, in this case, since the number of prize balls designated by the received prize ball number command should be set in the unpaid quantity counter (see steps S74214 and S74319), the prize ball dispensing operation is started. Then, a process of setting the number of prize balls in the payout motor rotation frequency buffer is performed. Next, the payout control CPU 371 loads a payout control state flag (step S75111), and sets a prize ball paying-out operation designation bit in the payout control state flag (step S75112). Then, control goes to a step S75113.

  In step S75113, the payout control CPU 371 sets a value in the payout motor control code for selecting a process to be executed in the payout motor control process according to the payout motor activation process. Thereby, in the payout motor control process in step S756, a payout motor starting process for starting the payout motor 289 is executed, and a lending ball payout operation or a prize ball payout operation is started. Then, the payout control CPU 371 sets a value “1” indicating the payout motor stop waiting process in the payout control code (step S75114), and ends the process.

  FIG. 92 is a flowchart showing the payout motor stop waiting process (step S7512) executed when the payout control code is 1. In the payout motor stop waiting process, the payout control CPU 371 first loads a payout control state flag (step S7521), and checks whether or not the payout operation is completed (step S7522). Specifically, the payout control CPU 371 checks whether or not a payout operation end designation bit (a bit indicating that the payout operation has ended) is set in the payout control state flag. The payout operation end designation bit is set in the payout motor brake process and the payout motor ball biting release process in the payout motor control process in step S756 shown in FIG.

  In the payout motor control processing, the payout control CPU 371 performs payout motor normal processing (processing such as setting the pointer at the head address of the table stored in the ROM), payout, according to the value of the payout motor control code. Motor start-up processing (processing such as setting the initial value of the excitation pattern in bits 4 to 7 of the port 0 buffer corresponding to the output state of the output port 0), payout motor slow-up processing (starting the rotation of the payout motor 289 smoothly) Therefore, the output state of the output port 0 is read out by reading the contents of the payout motor excitation pattern table at intervals longer than those in the case of constant speed processing and gradually approaching the time intervals in the case of constant speed processing. , Processing of setting bits 4 to 7 in the port 0 buffer corresponding to), payout motor constant speed processing (periodic payout motor excitation pattern) The process of reading the contents of the table and setting the bits 4 to 7 of the port 0 buffer corresponding to the output state of the output port 0), the dispensing motor brake process (the constant speed process to smoothly stop the dispensing motor 289) Port 0 buffer corresponding to the output state of the output port 0 by reading out the contents of the payout motor excitation pattern table at intervals longer than those in the case of, and gradually away from the time interval in the case of constant speed processing Processing of setting the bits 4 to 7), the payout motor ball biting process (when the ball biting state is detected, in order to release the ball biting, the contents of the payout motor excitation pattern table are read and the output port 0 is set. Processing to set bits 4 to 7 in the port 0 buffer corresponding to the output state), and the payout motor ball biting release processing (ball biting state is released) Either processing shifts to the payout motor normal processing process returns to the normal motor control state) execution.

  If the payout operation has been completed, the payout control CPU 371 resets the payout operation end designation bit of the payout control state flag (step S7523) and stops the payout motor used to set a payout passage monitoring time to be described later. The waiting process setting table 2 is set (step S7524).

  Next, the payout control CPU 371 checks whether or not the payout ball number inspected designation bit is set in the payout control state flag (step S7525). The designated number of paid-out balls inspected is a bit indicating that the detection of the number-of-payout count switch 301 has been determined at the end of the payout operation by the payout motor 289 (at the end of normal operation). If the payout ball number inspected designation bit is set, the process proceeds to step S7527. If the payout ball number inspected designation bit is not set, the payout control CPU 371 sets a payout motor stop waiting process setting table (step S7526). That is, the payout control CPU 371 replaces the table set in step S7524 with a payout motor stop waiting process setting table. Then, control goes to a step S7527.

  In step S7527, the payout control CPU 371 sets a value “2” indicating payout passing waiting processing in the payout control code. The payout control CPU 371 sets the payout passing monitoring time in the payout control timer based on the table set in steps S7524 and S7526 (step S7527). The payout passing monitoring time is a time that has a margin in the time from when the last payout ball is paid out by the payout motor 289 until it passes through the payout number count switch 301. In this embodiment, when the payout ball number inspected bit is set in step S7525, 1 second is set as the payout passing monitoring time based on the payout motor stop waiting process setting table 2 set in step S7524. To do. If the paid ball number inspected bit is not set in step S7525, 0.6 seconds is set as the payout passing monitoring time based on the payout motor stop waiting process setting table replaced in step S7526.

  93 to 95 are flowcharts showing a payout passing waiting process (step S7513) executed when the value of the payout control code is 2. In the payout passing waiting process, the payout control CPU 371 first checks the value of the payout control timer (step S75301). If the value is 0, the process proceeds to step S75304. If the value of the payout control timer is not 0, the value of the payout control timer is decremented by 1 (step S75302). If the value of the payout control timer is not 0 (step S75303), that is, if the payout control timer has not timed out, the process is terminated.

  If the payout control timer has timed out, the payout control CPU 371 loads the error flag, and sets the payout number abnormality error designation bit, the dispensing switch abnormality detection error 1 designation bit, or the dispensing switch abnormality detection error 2 designation bit. It is confirmed whether or not (step S75304). If any one of the payout number abnormality error designation bit, the dispensing switch abnormality detection error 1 designation bit, or the dispensing switch abnormality detection error 2 designation bit is set, it is determined that the dispensing operation cannot be continued any more, and step S75306 is executed. Transition. If none of the payout number error error specification bit, the payout switch error detection error 1 specification bit, and the payout switch error detection error 2 specification bit is set, the payout control CPU 371 sets the value of the unpaid number counter to 0. It is confirmed whether or not (step S75305). If the value of the unpaid-out counter is 0, the payout control CPU 371 assumes that the payout operation has ended normally, loads a payout control state flag (step S75306), and is requesting a ballot for the payout control state flag. Bits other than the designated bit and the payout operation end designation bit are reset (step S75307). Then, the payout control CPU 371 sets a value “0” indicating the payout start waiting process in the payout control code (step S75308), and ends the process.

  If the value of the unpaid-out number counter is not 0, the payout control CPU 371 loads an error flag and confirms whether or not the ball breakage error designation bit or the full tank error designation bit is set (step S75309). . If the ball breakage error designation bit or the full tank error designation bit is set, the processing is terminated as it is. If neither the ball breakage error designation bit nor the full tank error designation bit is set, the payout control CPU 371 checks whether or not the payout case error designation bit is set in the error flag (step S75310). If the payout case error designation bit is set, the payout control CPU 371 loads the payout control status flag (step S75311), and sets the payout ball number checked designation bit in the payout control status flag (step S75312). . The payout control CPU 371 also includes a 1 designation bit during re-payout operation (bit indicating execution of the first re-payout operation) and a 2 designation bit during re-payout operation (execution of the second re-payout operation). Is reset (step S75313), and the process is terminated.

  Note that the designated number of paid-out balls has been inspected is a bit indicating that the detection of the number-of-payout count switch 301 has been determined at the end of the payout operation by the payout motor 289 (at the end of normal operation). Note that, when the value of the unpaid-out number counter remains two or more despite the end of the payout operation, the remaining number is added to the payout number abnormality counter. Further, the detection determination by the payout number count switch 301 at the end of the payout operation is executed only once every time the payout operation is executed, and the payout motor ball biting process or the payout motor ball bite releasing process is executed. It is not executed when the biting operation is finished (specifically, since the payout case error designation bit is set in the ball biting state, the ball biting operation is performed by setting the payout ball number checked designation bit in advance in step S75312. Even if the operation is finished, the detection by the payout number count switch 301 is not determined). It should be noted that the payout ball number inspected designation bit is also set when the payout motor constant speed process in the payout motor control process becomes full.

  If the payout case error designation bit is not set in step S75310, the payout control CPU 371 loads a payout control state flag (step S75314) and performs processing for executing re-payout processing after step S75315.

  In order to execute the re-payout process, the pay-out control CPU 371 first checks whether or not the 2 designation bit during re-payout operation of the payout control state flag is set (step S75315). If it is not set, the payout control CPU 371 checks whether or not the 1 designation bit during re-payout operation of the payout control state flag is set (step S75316). If the 1 designation bit during re-payout operation is not set, the payout control CPU 371 sets the 1 designation bit during re-payout operation in the payout control state flag in order to execute the first re-payout operation (step S75317). .

  Next, the payout control CPU 371 checks whether or not the payout ball number inspected designation bit is set in the payout control state flag (step S75318). If the specified number of paid-out balls is inspected, the process proceeds to step S75326. If the specified number of paid-out balls has been inspected, the payout control CPU 371 checks whether or not the value of the unpaid-out number counter is 2 or more (step S75319). If the value of the unpaid-out number counter is not 2 or more, the process proceeds to step S75326. If the value of the unpaid number counter is 2 or more, the payout control CPU 371 adds the value of the unpaid number counter to the payout number abnormality counter (step S75320). Note that the process of step S75320 corresponds to a process of cumulatively counting the number of shortage payouts in the payout number abnormality counter. Next, the payout control CPU 371 checks whether or not the value of the added payout number abnormality counter is equal to or greater than a predetermined payout number error error determination value (for example, 2000) (step S75321). If it is equal to or greater than a predetermined payout number error error determination value (for example, 2000), the payout control CPU 371 determines that a payout number error error has occurred, and indicates a payout number error error indicating that a payout number error error has occurred. A flag is set (step S75322).

  In this embodiment, the payout is performed on condition that the value of the unpaid-out number counter remains at a predetermined reference number (2 in this example) even though the payout operation is finished by the process of step S75319. The value of the unpaid number counter is added to the number abnormality counter. That is, since the payout operation is terminated due to a malfunction or the like, the value of the unpaid-out number counter remains in a small number (1 in this example). If even one unsettled number counter value remains, the accumulated number is immediately counted as a cumulative number in the payout number abnormality counter, and the frequency determined as a payout number abnormality error is increased more than necessary, causing problems to the game. End up. Therefore, in this embodiment, on the condition that the value of the unpaid-out number counter remains 2 or more with a little allowance, the accumulated number is counted in the payout number abnormality counter, and it is determined that there is an unnecessarily large number of payout errors. Is prevented. The process of step S75319 shows a case where the payout number abnormality counter is cumulatively counted up on condition that the payout shortage number is equal to or greater than a predetermined reference number (2 in this example). Alternatively, the payout number abnormality counter may be counted up cumulatively on condition that the number is a predetermined reference number (2 in this example) or more. In this case, for example, on the condition that the number of times determined to be Y in step S7502 shown in FIG. 90 has accumulated and has reached two or more, a count value corresponding to an excessive number of payouts is cumulatively set in step S7503. Count up. In the processing of steps S75319 and S75320, the value of the unpaid number counter is always used as it is in the payout number abnormality counter regardless of whether or not the value of the unpaid number counter remains at a predetermined reference number (2 in this example). You may make it add.

  If the 1 designation bit during re-payout operation is set in step S75316, the payout control CPU 371 checks whether or not the dispensed ball detection designation bit is set in the payout control state flag (step S75323). If the payout ball detection designation bit is set, the payout control CPU 371 proceeds to step S75326. If the payout ball detection designation bit is not set, the payout control CPU 371 sets the 2 designation bit during re-payout operation in the payout control state flag to execute the second re-payout operation (step S75324). Then, 1 is added to the value of the payout number abnormality counter (step S75325). Note that the process of step S75325 corresponds to a process of cumulatively counting the number of shortage payouts in the payout number abnormality counter. Then, control goes to a step S75326. Note that by executing the processing of step S75325, the value of the payout number abnormality counter is incremented by 1 when the re-payout operation is not performed normally despite the execution of the first re-payout operation. The Even when the payout is completed normally, the value of the unpaid-out number counter may not be 0 due to an erroneous count or the like. Therefore, if the payout ball detection designation bit is set by executing the process of step S75323, that is, if the payout number count switch 301 detects the payout of at least one game ball during the payout operation. Since there is a possibility that the payout has been completed normally, the process proceeds to step S75326 without performing the cumulative count of the payout number abnormality counter.

  In step S75326, the payout control CPU 371 sets 1 as the number of repaid operations in order to execute the first repaid operation. Next, the payout control CPU 371 sets the number of re-payout operations (1 in this example) in the payout motor rotation frequency buffer (step S75327). Next, the payout control CPU 371 loads the payout control state flag (step S75328), and resets the payout ball detection designation bit of the payout control state flag (step 75329).

  Next, the payout control CPU 371 sets a value in the payout motor control code for selecting the process executed in the payout motor control process in accordance with the payout motor activation process (step S75330). Thereby, in the payout motor control process of step S756, the payout motor starting process for starting the payout motor 289 is executed, and the re-payout operation is started. Then, the payout control CPU 371 sets a value “1” indicating the payout motor stop waiting process in the payout control code (step S75331), and ends the process.

  If the 2 designation bit during re-payout operation is set in step S75315, the payout control CPU 371 resets the 2 designation bit during re-payout operation of the payout control state flag (step S75332). Next, the payout control CPU 371 checks whether or not the payout ball detection designation bit of the payout control state flag is set (step S75333). If the payout ball detection designation bit is set, the process proceeds to step S75326. If the payout ball detection designation bit is not set, the payout control CPU 371 resets the 2 designation bit during re-payout operation of the payout control state flag (step S75334) and adds 1 to the value of the payout number abnormality counter (step S75334). Step S75335). Note that the process of step S75335 corresponds to a process of cumulatively counting the number of shortage payouts in the payout number abnormality counter. Also, by executing the process of step S75335, even if the second re-payout operation is executed, if the re-payout operation is not performed normally, the value of the payout number abnormality counter is incremented by one. Even when the payout is completed normally, the value of the unpaid-out number counter may not be 0 due to an erroneous count or the like. Therefore, if the payout ball detection designation bit is set by executing the process of step S75333, that is, if the payout number count switch 301 detects the payout of at least one game ball during the payout operation. Since there is a possibility that the payout has been completed normally, the process proceeds to step S75326 without performing the cumulative count of the payout number abnormality counter.

  Next, the payout control CPU 371 loads an error flag, and sets a payout case error designation bit in the error flag (step S75336). Then, the payout control CPU 371 sets a predetermined time (for example, 2 minutes) in the re-payout waiting timer (step S75337) and ends the process. The re-payout waiting timer set in step S57337 is measured by error processing described later (see step S7710), and the payout case error designation bit in the error flag is reset based on the time-out of the re-payout timer. (See steps S7711 and S7712). By executing such processing, in this embodiment, after the payout case error is detected, the error state is automatically recovered based on the fact that two minutes have passed.

  Next, error processing will be described. FIG. 96 is an explanatory diagram showing the relationship between the type of error and the display of the LED 374 for error display. As shown in FIG. 96, when no error has occurred, “−” is displayed on the error display LED 374. When the cumulative count value of the payout number abnormality counter is 2000 or more and a payout number error is detected, the payout control CPU 371 of the payout control microcomputer 370 detects an error display LED 374 as a payout number error. Control to display “A” on the screen. If a payout number abnormality error occurs, the error state is continued until the power supply of the gaming machine is reset.

  When the connection signal from the main board 31 is turned off, the payout control CPU 371 of the payout control microcomputer 370 performs control to display “1” on the error display LED 374 as a main board non-connection error. Do.

  When the disconnection of the payout count switch 301 or a ball clogging occurs at the payout count switch 301, the error display LED 374 is controlled to display “2” as the payout switch abnormality detection error 1. The disconnection of the payout number count switch 301 or the occurrence of ball clogging in the payout number count switch 301 is determined by the detection signal of the payout number count switch 301 not being turned off.

  When the detection signal of the payout number count switch 301 is turned on even though the game ball is not paying out, a control for displaying “3” on the error display LED 374 as a payout switch abnormality detection error 2 is performed. Do. If the detection signal of the payout count switch 301 does not turn on despite the rotation abnormality of the payout motor 289 or the game ball being paid out, “4” is displayed on the error display LED 374 as a payout case error. Control. The specific method for detecting that the detection signal of the payout number count switch 301 is not turned on is as described above.

  When a serial communication error between the game control microcomputer 560 and the payout control microcomputer 370 is detected, control is performed to display “5” on the error display LED 374 as a main control communication error. .

  In addition, when the lower pan is full, that is, when the full switch 48 is turned on, control is performed to display “6” on the error display LED 374 as a full error. When the supply ball is insufficient, that is, when the ball break switch 187 is turned on, control is performed to display “7” on the error display LED 374 as a ball break error.

  Further, when the VL signal from the card unit 50 is turned off, control is performed to display “8” on the error display LED 374 as a prepaid card unit non-connection error. When communication with the card unit 50 is performed at an improper timing, control is performed to display “9” on the error display LED 374 as a prepaid card unit communication error. The prepaid card unit communication error is detected in the prepaid card unit control process (step S758).

  Among the above errors, after a payout switch abnormality detection error 2, a payout case error, or a main control communication error occurs, the error release switch 375 is operated and an operation signal is output from the error release switch 375 (becomes ON state). The payout control means returns to the state before the error occurred.

  As already described, the payout control CPU 371 specifically displays an error on the error display LED 374 according to the relationship shown in FIG. 96 in the display control process of the timer interrupt process (see step S760). For example, the payout control CPU 371 generates a prepaid card unit unconnected error in the display control process based on the setting of the prepaid card unit unconnected state designation bit in the error process described later (see step S7729). An error display “8” indicating that is displayed on the error display LED 374 is controlled. Further, for example, based on the fact that the full error specification bit is set in the error processing (see step S7714), an error display “6” indicating that a full error has occurred in the display control processing is displayed on the error display LED 374. Control the display.

  97 and 98 are flowcharts showing the error processing in step S757. In the error processing, the payout control CPU 371 first loads an error flag, and the error flag payout switch abnormality detection error 2 designation bit, a payout case error designation bit, a main control communication error designation bit, and a payout number abnormality error designation bit. The other error bits are reset (step S7701). Next, the payout control CPU 371 checks whether or not the value of the error flag is 0 (step S7702). If the value of the error flag is 0, the process proceeds to step S7710. If the value of the error flag is not 0 (that is, if the payout switch abnormality detection error 2 designation bit, the withdrawal case error designation bit, the main control communication error designation bit, or the withdrawal number abnormality error designation bit is set) The control CPU 371 checks whether or not the operation signal is turned on from the error release switch 375 (step S7703). When the operation signal is turned on, the error recovery time is set in the pre-error recovery timer (step S7709). The error recovery time is the time from when the error release switch 375 is operated until the actual return from the error state to the normal state.

  If the operation signal from the error release switch 375 is not on, the value of the timer before error recovery is confirmed (step S7704). If the value of the timer before error recovery is 0, that is, if the timer before error recovery is not set, the process proceeds to step S7710. If the pre-error recovery timer is set, the value of the pre-error recovery timer is decremented by -1 (step S7705). If the pre-error recovery timer value becomes 0 (step S7706), the payout switch of the error flags is set. The abnormality detection error 2 designation bit, the payout case error designation bit, and the main control communication error designation bit are reset (step S7707), and if set, the re-payout waiting timer is reset (step S7708). Then, control goes to a step S7710. If the pre-error recovery timer has not timed out, the process proceeds to step S7713.

  When the processing of step S7707 is executed, there may be an error bit that is not in the set state among the payout switch abnormality detection error 2 designation bit, the payout case error designation bit, and the main control communication error designation bit. There is no problem even if the error bit that is not set is reset. As described above, in this embodiment, when an error (see FIG. 96) that causes the setting of the payout switch abnormality detection error 2, the payout case error, and the main control communication error bit occurs, an error occurs. The error is released when the release switch 375 is pressed.

  In step S7710, if set, the payout control CPU 371 subtracts 1 from the value of the re-payout waiting timer, and checks whether the re-payout wait timer after the subtraction has timed out (step S7711). If the re-payout waiting timer has timed out, the payout control CPU 371 resets the payout case error designation bit in the error flag (step S7712). Then, control goes to a step S7713.

  As described above, in this embodiment, when the payout case error is detected and the payout detection error designation bit is set by executing the processes of steps S7707 and S7712, the error release switch 375 is pressed. On the condition that the error has been canceled (more precisely, the time before error recovery has passed) and on the condition that a predetermined time (2 minutes in this example) has passed after detection of the payout case error The error may be automatically canceled. In this embodiment, regarding the payout number abnormality error, once detected, it is not canceled unless the power supply to the gaming machine is reset.

  When the processing of steps S7707 and S7712 is executed and the payout case error designation bit is reset, the payout control code is “2” (corresponding to the execution of the payout passing waiting process shown in FIGS. 93 to 95). Then, the game ball payout retry operation is started. That is, when the payout control process in step S755 is executed next, if the payout passing waiting process in step S7513 is executed, the repayout process is performed again. For example, if a prize ball payout process has been performed and the value of the unpaid-out number counter is not 0, the process proceeds from step S75305 to steps S75309 and S75310, and the payout case error designation bit is in the reset state in step S75310. Therefore, the process for starting the re-payout process after step S75314 is executed again, and the re-payout process is executed.

  As described above, the payout control means is used to pay out a game ball when the payout number count switch 301 detects no game ball even though the ball payout device 97 pays out a game ball. After performing the correct payout control for causing the ball payout device 97 to execute the retry operation for a predetermined number of times (for example, twice) as a limit, the payout number count switch 301 has detected no game balls. When it is detected (see step S75314 and subsequent steps in FIGS. 93 to 95), the control state related to payout is shifted to an error state, and an error release signal is output from the error release switch 375 in the error state, or a payout case Corrected payout that makes correction payout control again on condition that a predetermined time (2 minutes in this example) has passed since the error was detected To run the control restart processing.

  Further, even during re-payout processing in an error state (specifically, during re-payout processing before setting a payout case error and during re-payout processing after the error release switch 375 is pressed), step S7501 shown in FIG. S7502 and S7506 are executed. That is, even when an error related to payout occurs, if the game ball passes the payout number count switch 301, the value of the unpaid-out number counter is subtracted. Accordingly, the value of the unpaid-out number counter when returning from the error state is a value reflecting the number of game balls actually paid out. That is, even if an error related to payout occurs, the number of game balls actually paid out can be accurately managed.

  Also, in the payout passing waiting process shown in FIGS. 93 to 95, even when it is confirmed that the game ball has been paid out as a result of the re-payout process, the payout case error bit is not reset. The bit of the payout case error is reset only when the error release switch 375 is operated (specifically, when an error return time after operation has elapsed) or when a payout case error is detected for a predetermined time. (2 minutes in this example) has elapsed (steps S7707, S7712). That is, until a predetermined time (in this example, 2 minutes) has passed since the detection of the payout case error, the payout case error (insufficient payout) is automatically determined based on the fact that the game ball has passed through the payout number count switch 301. The error) state is not canceled, and the payout case error is not canceled without an artificial operation. Therefore, the game store clerk and the like can surely recognize that a shortage of payout has occurred. However, in this embodiment, at least a long time (2 minutes in this example) after the occurrence of the payout case error is configured to automatically cancel the payout case error so that the payout case error is generated. Prevents longer duration than necessary.

  In some cases, a gaming machine may be configured such that a hardware reset (reset for the payout control CPU 371) is performed by operating the error release switch 375. When the error release switch 375 is operated, for example, the value of the unpaid number counter is also cleared. However, in this embodiment, since the payout control means is configured to perform the re-payout operation again by operating the error release switch 375, the payout process is executed reliably, which is disadvantageous to the player. Can not be given.

  In step S7713, the payout control CPU 371 checks the detection signal of the full tank switch 48. If the detection signal of the full tank switch 48 is output (if it is in the ON state), the full tank error designation bit in the error flag is set (step S7714).

  Further, the payout control CPU 371 checks the detection signal of the ball break switch 187 (step S7715). If the detection signal of the ball break switch 187 is output (if it is on), the ball break error designation bit in the error flag is set (step S7716).

  Furthermore, the payout control CPU 371 checks the state of the connection signal from the main board 31 (step S7717), and if the connection signal is not output (if it is in the off state), sets the main board unconnected error designation bit. (Step S7718).

  Further, the payout control CPU 371 checks the value of the switch timer corresponding to the payout number count switch 301 among the switch timers in which the state of the detection signal of each switch is set, and the value is the switch on maximum time (for example, “ 250 ") (step S7719), the bit of the payout switch abnormality detection error 1 is set in the error flag (step S7720). It should be noted that the value of each switch timer is incremented by 1 when the state of the input port to which the detection signal of each switch is input is switched on in the input determination process of step S752, and cleared by 0 when it is off. Accordingly, the fact that the value of the switch timer corresponding to the payout number count switch 301 exceeds the switch on maximum time means that the payout number count switch 301 is in the on state exceeding the switch on maximum time. Then, it is determined that the game ball is clogged at the disconnection of the payout number count switch 301 or at the portion of the payout number count switch 301.

  Further, the payout control CPU 371 loads the payout control state flag when the value of the switch timer corresponding to the payout number count switch 301 becomes a switch-on determination value (for example, “4”) (step S7721). In step S7722), it is confirmed whether the winning ball payout operation or the ball lending payout operation is in progress (step S7723). Specifically, the payout control CPU 371 checks whether or not a prize ball payout operation specifying bit or a ball lending payout operation specifying bit is set in the payout control state flag. If the designated bit during the winning ball payout operation and the designated bit during the ball lending payout operation are both in the reset state, the payout control CPU 371 determines that the game ball has passed through the payout number count switch 301 even though the payout operation is not in progress, an error flag. Among these, the bit of the payout switch abnormality detection error 2 is set (step S7724).

  Further, the payout control CPU 371 checks whether or not the value of the payout number abnormality counter is equal to or greater than a predetermined payout number error error determination value (for example, 2000) (step S7725). If it is equal to or greater than a predetermined payout number error error determination value (for example, 2000), the payout control CPU 371 determines that a payout number error has occurred and sets a payout number error error flag (step S7726).

  Next, the payout control CPU 371 resets the prepaid card unit error flag for setting the error state of the prepaid card unit 50 (step S7727). Further, the payout control CPU 371 checks the input state of the VL signal from the card unit 50 (step S7728). If the VL signal is not input (if it is in the off state), the prepaid card unit error flag The prepaid card unit unconnected error designation bit is set (step S7729).

  In the display control process of step S760, the error display LED 374 performs notification by display (numerical display) according to the error flag and the error bit in the prepaid card unit error flag. Therefore, a communication error can be notified by the error display LED 374. Further, since the communication error is detected on the payout control means side, the communication error can be detected without increasing the burden on the game control means.

  In this embodiment, the main board unconnected error is automatically canceled when the connection signal is turned on (see steps S7701, S7717, and S7718), but the condition that the error cancel switch 375 is further operated is set. In addition, the error state may be eliminated.

  In this embodiment, a communication error is reported so as to be distinguishable from a communication error with the card unit 50 (prepaid card unit non-connection error and prepaid card unit communication error) and other errors (see FIG. 96). ). Therefore, a communication error between the game control microcomputer 560 and the payout control microcomputer 370 is easily identified.

  In this embodiment, in error processing, first of the error flags, other than the payout switch abnormality detection error 2 designation bit, the payout case error designation bit, the main control communication error designation bit, and the withdrawal number abnormality error designation bit. After the bit is reset once (see step S7701), it is checked every time error processing is executed whether a full error, a ball break error, or a main control unconnected error has occurred. The payout switch abnormality detection error 2 designation bit, the payout case error designation bit, and the main control communication error designation bit are reset on the condition that the error release switch 375 has been operated. However, the payout number abnormality error is not canceled once it is set. Therefore, in this embodiment, when a payout number error occurs, the payout number error is canceled as a condition that the power supply is reset.

  99 and 100 are flowcharts showing the information output processing in step S759. In the information output process, the payout control CPU 371 first loads a payout control state flag (step S7901), and checks whether or not a ball lending payout operation is in progress (step S7902). Specifically, the payout control CPU 371 checks whether or not the designated bit during the ball lending payout operation of the payout control state flag is set. If the ball lending / dispensing operation is in progress, the process proceeds to step S7909. If the ball lending payout operation is not in progress, the payout control CPU 371 checks whether or not the payout number count switch 301 is in the on state (step S7903). If the payout number count switch 301 is in the ON state (in this case, the payout by the winning ball is detected), the payout control CPU 371 adds 1 to the value of the winning ball signal 1 output number counter (step S7904). At the same time, the value of the prize ball payout number counter is incremented by 1 (step S7905). The prize ball signal 1 output number counter is a counter for counting the number of times the condition for outputting the prize ball signal 1 is satisfied. The prize ball payout number counter is a counter for counting the number of game balls paid out by the prize ball payout.

  Next, the payout control CPU 371 checks whether or not the value of the added prize ball payout counter is equal to or greater than a predetermined prize ball information output determination value (10 in this example) (step S7906). If it is equal to or greater than a predetermined prize ball information output determination value (10 in this example), the payout control CPU 371 resets the prize ball payout number counter (step S7907) and sets the value of the prize ball information output number counter. 1 is added (step S7908). The prize ball information output count counter is a counter for counting the number of times that the condition for outputting prize ball information is satisfied.

  Next, if it is set, the payout control CPU 371 decrements the prize ball information output timer by 1 (step S7909), and checks whether the prize ball information output timer after the subtraction has timed out (step S7910). The prize ball information output timer is a timer for measuring the output duration time of prize ball information. If not timed out, the process proceeds to step S7914. If time-out has occurred, the payout control CPU 371 checks whether or not the value of the prize ball information output number counter is 0 (step S7911). If the value of the prize ball information output number counter is 0, the process proceeds to step S7915. If the value of the winning ball information output number counter is not 0 (that is, if the number of winning ball information output conditions is still satisfied), the payout control CPU 371 subtracts 1 from the value of the winning ball information output number counter. (Step S7912). Next, the payout control CPU 371 sets a prize ball information output timer in order to start outputting the next prize ball information (step S7913). Then, the payout control CPU 371 performs control to output the prize ball information to the game control microcomputer 560 (step S7914). Specifically, the payout control CPU 371 performs a process of setting output data in a prize ball information output bit (bit 7, see FIG. 77) of the output port 1.

  Next, if the payout control CPU 371 is set, the prize ball signal 1 output timer is decremented by 1 (step S7915), and it is confirmed whether or not the prize ball signal 1 output timer after the subtraction has timed out (step S7916). ). The prize ball signal 1 output timer is a timer for measuring the output duration time of the prize ball signal 1. If not timed out, the process proceeds to step S7920. If time-out has occurred, the payout control CPU 371 checks whether or not the value of the prize ball signal 1 output number counter is 0 (step S7917). If the value of the winning ball signal 1 output number counter is 0, the process proceeds to step S7921. If the value of the prize ball signal 1 output number counter is not 0 (that is, if the number of established conditions for the prize ball signal 1 still remains), the payout control CPU 371 determines the value of the prize ball signal 1 output number counter. 1 is subtracted (step S7918). Next, the payout control CPU 371 sets a prize ball signal 1 output timer to start outputting the next prize ball signal 1 (step S7919). Then, the payout control CPU 371 performs control to output the prize ball signal 1 to the outside (step S7920). Specifically, the payout control CPU 371 performs processing for setting output data in a prize ball signal 1 output bit (bit 0; see FIG. 77) of the output port 0. In this embodiment, the winning ball signal 1 is not directly input to the terminal board 160 from the payout control board 31 and output to the outside, but is input to the terminal board 160 once through the main board 31. Is output externally.

  Next, the payout control CPU 371 performs processing for setting output data in the gaming machine error state signal output bit (bit 1, see FIG. 77) of the output port 0 (step S7921), and loads an error flag (step S7922). ). If either the ball breakage error designation bit or the full tank error designation bit is set in the error flag (Y in steps S7923 and S7924), the gaming machine error status signal output bit of the output port 0 remains set. The process ends. In this case, the gaming machine error status signal is output to the outside based on the fact that the gaming machine error status signal output bit of the output port 0 is set in step S7921. In this embodiment, the gaming machine error state signal is not directly input from the payout control board 31 to the terminal board 160 but externally output, but is input to the terminal board 160 once via the main board 31. And output externally. On the other hand, if neither the ball breakage error designation bit nor the full tank error designation bit is set in the error flag, the payout control CPU 371 clears the gaming machine error state signal output bit of the output port 0 (step S7925), and processing Exit.

  By executing the above processing, in this embodiment, the prize ball signal 1 is output to the outside every time one prize ball payout is detected on the payout control means side. Further, prize ball information is output to the game control means side every time ten payout balls are detected on the payout control means side. Further, when a ball break error or a full tank error is detected on the payout control means side, a gaming machine error state signal is output to the outside.

  Next, the operation of the effect control means will be described. FIG. 101 is a flowchart showing an effect control main process executed by effect control microcomputer 100 (specifically, effect control CPU 101a) as effect control means mounted on effect control board 80. The effect control CPU 101a starts executing the effect control main process when the power is turned on. In the production control main process, first, initialization processing is performed for clearing the RAM area, setting various initial values, and initializing a timer for determining the activation control activation interval (for example, 4 ms) (step S1). S781). Thereafter, the effect control CPU 101a proceeds to a loop process for monitoring the timer interrupt flag (step S782). When a timer interrupt occurs, the effect control CPU 101a sets a timer interrupt flag in the timer interrupt process. If the timer interrupt flag is set in the effect control main process, the effect control CPU 101a clears the flag (step S783) and executes the following effect control process.

  In the effect control process, the effect control CPU 101a first analyzes the received effect control command and performs a process of setting a flag according to the received effect control command (command analysis process: step S784).

  Next, the effect control CPU 101a performs effect control process processing (step S785). In the effect control process, the process corresponding to the current control state (effect control process flag) is selected from the processes corresponding to the control state, and display control of the effect display device 9 is executed.

  Next, a random number update process for updating a count value of a counter for generating a random number such as a jackpot symbol determining random number is executed (step S786). Thereafter, the process proceeds to step S782.

  FIG. 102 is a flowchart illustrating a specific example of command analysis processing (step S784). The effect control command received from the main board 31 is stored in the reception command buffer, but in the command analysis process, the effect control CPU 101a checks the content of the command stored in the command reception buffer.

  Note that FIG. 102 shows the processing in the case of receiving a command indicating an error relating to payout control among the effect control commands transmitted from the game control microcomputer 560. Various effect control commands such as a variation pattern command indicating a variation pattern and a display result specifying command indicating a display result indicating whether or not to win are transmitted from the game control microcomputer 560.

  In the command analysis process, the effect control CPU 101a first checks whether or not a reception command is stored in the command reception buffer (step S611). Whether it is stored or not is determined by comparing the value of the command reception number counter with the read pointer. The case where both match is the case where the received command is not stored. When the reception command is stored in the command reception buffer, the effect control CPU 101a reads the reception command from the command reception buffer (step S612). When read, the value of the read pointer is incremented by +2 (step S613). The reason for +2 is that 2 bytes (1 command) are read at a time.

  If the received effect control command is a frame state display command (step S614), the effect control CPU 101a sets a prize ball error bit (bit 0, see FIG. 31) among the lower 4 bits of the frame state display command. It is confirmed whether it has been done (step S615). If set, the effect control CPU 101a performs control to superimpose and display predetermined prize ball error notification information on the display screen of the effect display device 9 (step S616). For example, the effect control CPU 101 a performs control to display a character string such as “A prize ball error has occurred” on the display screen of the effect display device 9.

  Further, the effect control CPU 101a checks whether or not the full error bit (bit 1, see FIG. 31) of the lower 4 bits of the frame state display command is set (step S617). If set, the effect control CPU 101a performs control to superimpose and display predetermined full tank error notification information on the display screen of the effect display device 9 (step S618). For example, the effect control CPU 101 a performs control to display a character string such as “a full tank error has occurred” on the display screen of the effect display device 9.

  In addition, the effect control CPU 101a checks whether or not the ball break error bit (bit 2, see FIG. 31) in the lower 4 bits of the frame state display command is set (step S619). If set, the effect control CPU 101a performs control to superimpose and display predetermined ball-out error notification information on the display screen of the effect display device 9 (step S620). For example, the effect control CPU 101 a performs control to display a character string such as “A ball break error has occurred” on the display screen of the effect display device 9.

  Further, the effect control CPU 101a checks whether or not the payout number error error bit (bit 3; see FIG. 31) in the lower 4 bits of the frame state display command is set (step S621). If set, the effect control CPU 101a performs control to superimpose and display predetermined payout number abnormality error notification information on the display screen of the effect display device 9 (step S622). For example, the effect control CPU 101 a performs control to display a character string such as “A payout number error has occurred” on the display screen of the effect display device 9.

  If the received effect control command is a prize ball shortage error command (step S623), the effect control CPU 101a performs control to superimpose and display predetermined prize ball shortage error notification information on the display screen of the effect display device 9 (step S623). S624). For example, the effect control CPU 101 a performs control to display a character string such as “There was a shortage of prize balls error” on the display screen of the effect display device 9.

  If the received effect control command is a prize ball excess error command (step S625), the effect control CPU 101a performs control to superimpose and display predetermined prize ball excess error notification information on the display screen of the effect display device 9 (step S625). S626). For example, the effect control CPU 101a performs control to display a character string such as “An excessive prize ball error has occurred” on the display screen of the effect display device 9.

  In addition, each error display may not be simply displayed in a superimposed manner, but may be prioritized and notified of an error having a high priority by ranking from the viewpoint of fraud importance. For example, a payout number abnormality error may be preferentially notified with the highest priority, or a newly generated error may be preferentially notified when the error state changes.

  If the received effect control command is another command, the effect control CPU 101a sets a flag corresponding to the received effect control command (step S627). Then, control goes to a step S611. For example, when a variation pattern command or a display result designation command is received, the effect control CPU 101a also performs processing for storing the received variation pattern command or display result designation command in a predetermined storage area formed in the RAM. Do.

  Next, a transition example of the effect mode in the pachinko gaming machine 1 will be described. The pachinko gaming machine 1 in this embodiment includes a plurality of effect modes with different effect modes in the effect display device 9, the speaker 27, and the like. FIG. 103 is a diagram for explaining a transition example of the effect mode. In this embodiment, as shown in FIG. 103, four effect modes of mode A, mode B, mode C, and mode N are provided. These effect modes are switched according to the current effect mode, the jackpot type, or the like when the big hit gaming state is ended, when the variable display of the effect symbols is started, or when the time reduction state is ended. In addition, in order to enhance a production effect, production modes other than these may be provided.

  Mode N is also referred to as a normal mode. When no transition is made to any production mode, that is, the production mode such as after power-on is this mode N. As shown in FIG. 103, in this mode N, when the variable display result is “big hit” and the big hit type is “15R probability change”, and it is notified that the transition to the probability change state is made after the big hit gaming state ends. (With probability change notification), after the big hit gaming state, the mode C effect mode is entered. Here, when there is a probability change notification for notifying that the transition to the probability change state is made, for example, in the variable display of the effect symbol, the effect symbol of the probability variation big hit combination is directly derived and displayed, or the predetermined re-lottery effect The player is surely changed after the jackpot gaming state is finished, for example, by the fact that the winning symbol combination pattern is derived and displayed (in the case of direct hit) or the jackpot promotion promotion effect is executed by the jackpot promotion promotion effect. What is necessary is just to be able to discriminate | determine that it will be in a state.

  Further, in mode N, when the variable display result is “big hit” and the big hit type is “15R probability change”, and it is not notified that the transition to the probability change state is not made (no probability change notification), the big hit gaming state ends. Later, the mode A transitions to the effect mode. Here, when there is no probability change notification that does not notify the transition to the probability change state, for example, in the variable display of the effect symbol, the effect symbol of the normal jackpot combination is directly derived and displayed, or the predetermined re-lottery effect Whether or not the player enters the probable change state after the end of the big hit gaming state due to the fact that the normal jackpot combination production symbol is derived and displayed, or the big hit middle promotion promotion effect is executed by the big hit middle promotion effect, etc. What is necessary is to make it difficult or impossible to distinguish. In mode N, when the variable display result is “big hit” and the big hit type is “2R sudden probability”, the mode shifts to the mode C effect mode after the big hit gaming state.

  In mode A, when the variable display result is “big hit”, the big hit type is “15R probability change”, and there is a probability change notification, the mode shifts to the mode C effect mode after the big hit gaming state ends. In mode A, the variable display result is “big hit” and the big hit type is “15R probability change”, and there is no probability change notification, or the variable display result is “big hit” and the big hit type is “15R non-probable”. In this case, after the big hit gaming state, the mode B is shifted to the effect mode. In mode A, when the variable display result is “big hit” and the big hit type is “2R sudden probability”, the mode A effect mode continues even after the big hit gaming state ends. In the mode A, when the time reduction control in the time reduction state is finished, the mode shifts to the mode N effect mode.

  In the mode B, when the variable display result is “big hit” and the big hit type is “15R probability change” and there is a probability change notification, the mode shifts to the mode C effect mode after the big hit gaming state ends. In mode B, when the variable display result is “big hit” and the big hit type is “15R probability change” and there is no probability change notification, or when the variable display result is “big hit” and the big hit type is “15R uncertain change”, Alternatively, when the variable display result is “big hit” and the big hit type is “2R sudden probability”, the mode B effect mode continues even after the big hit gaming state ends. Further, in the mode B, when the time reduction control in the time reduction state is completed, the mode shifts to the mode N effect mode.

  In mode C, when the variable display result is “big hit” and the big hit type is “15R probability change” and there is a probability change notification, or when the variable display result is “big hit” and the big hit type is “2R accuracy” The effect mode of mode C continues even after the end of the big hit gaming state. In mode C, when the variable display result is “big hit” and the big hit type is “15R probability change” and there is no probability change notification, or when the variable display result is “big hit” and the big hit type is “15R uncertain change”. Shifts to the mode B effect mode after the end of the big hit gaming state.

  The gaming state when the mode N is the production mode is the normal state. In the mode C, the variable display result is “big hit” and the big hit type is “15R probability change” and there is a probability change notification, or the variable display result is “big hit” and the big hit type is “2R accuracy”. In some cases, a transition is made from another production mode. Therefore, it is possible to specify that the gaming state when the mode C is the production mode is the probability variation state. For example, in the effect mode of mode C, “probably changing” or the like may be displayed in the display area of the effect display device 9 so as to clearly indicate the probability changing state.

  On the other hand, in the mode A and mode B, the variable display result is “big hit” and the big hit type is “15R probability change” and there is no positive change notification, or the variable display result is “big hit” and the big hit type is In the case of “15R uncertain change”, the transition is made from another effect mode. The gaming state at this time is controlled to a probability change state when the big hit type is “15R probability change”, and is controlled to a short time state when the big hit type is “15R non-change probability”. Therefore, in the mode A or the mode B production mode, the gaming state can be either the short-time state or the probability variation state. In such a mode A or mode B production mode, for example, when controlled to a predetermined special gaming state in which probability variation control is performed, such as probability variation state, and when not controlled to such a special gaming state It is difficult or impossible to specify whether or not a common effect is executed, and whether or not the special game state is controlled. In addition, the plurality of effect modes may include an effect mode in which the gaming state in the pachinko gaming machine 1 can be recognized, such as the mode N or the mode C effect mode. As in the effect mode, only the effect mode in which the game state is difficult to specify or cannot be specified may be included. An effect mode in which the game state is difficult to specify or cannot be specified, such as the effect mode of mode A or mode B, is also referred to as a common effect mode.

  As described above, the mode B effect mode is not directly shifted from the mode N effect mode. Thereby, the range of production is widened and the interest of the game is improved.

  In the effect mode of mode C, for example, the same background or character image effect may be continuously executed over a plurality of variable displays. As an example, the effect mode of mode C may be an effect mode called a battle mode. More specifically, when the variable display result is “big hit”, the teammate character performs battle battle with the enemy character, and when the big hit type is “15R probability variation”, the production pattern of the probability variation jackpot combination is When it is derived and displayed, the teammate character performs an effect of winning the enemy character and continues the battle mode. When the jackpot type is “15R probability change” and there is no probability change notification, or when “15R non-probability change” is displayed, when the effect symbol of the normal jackpot combination is derived and displayed, the teammate character loses the enemy character. You may make it complete | finish a battle mode and make it transfer to the production mode of mode A or mode B. Thus, in mode C, it can be notified that a certain change state is caused by a battle effect. In such a battle mode, the effect symbol may be in a reach state only when the variable display result is “big hit” or “small hit”. Furthermore, when the effect symbol is in the reach state, the ratio that the big hit type is “15R probability variation” may be different depending on which combination of the effect symbols that are stopped and displayed. In the effect modes of mode A, mode B, and mode C, for example, different effect modes are set by changing the background displayed on the effect display device 9. Moreover, it is good also as different production modes by making the character in the above-mentioned battle mode different, or making it produce a different aspect. In addition, when the game state is in the probable state in the common effect mode in the common effect mode, such as the mode A and the mode B effect mode, the end of the time-short state is ended. When the variable display of 100 times as a condition is executed, it may be notified that the state is a probable change state. (If the gaming state is a short-time state, the short-time state ends and the gaming state can be specified) ) Further, during the jackpot gaming state when the effect mode is shifted to after the jackpot gaming state ends, the rendering corresponding to the transitioned rendering mode may be executed. For example, during the jackpot gaming state, an effect of displaying a character image or background corresponding to each effect mode (mode A, mode B, and mode C) may be executed.

  The production control ROM incorporated in or external to the production control microcomputer 100 of the production control board 80 corresponds to a plurality of production modes such as mode A, mode B, mode C, and mode N as shown in FIG. Table data constituting the effect control pattern tables 250A to 250D as shown in FIG. The effect control ROM stores table data constituting a mode transition effect control pattern table 251 as shown in FIG. 104 (B). The mode transition effect control pattern table 251 only needs to store a plurality of types of data indicating the contents of various effect controls in the mode transition effect executed in accordance with the mode transition as the mode transition effect control pattern. In addition, various effects are stored in the effect control ROM in which a plurality of types of data indicating the contents of various effect controls are stored as various effect control patterns during the period when the game is controlled to the big hit game state or the small hit game state. A control pattern table or the like may be formed.

  In the effect control pattern tables 250A to 250D shown in FIG. 104 (A), depending on whether the effect mode in the pachinko gaming machine 1 is a plurality of modes A, mode B, mode C, or mode N, the effect modes mutually. It is only necessary to store a plurality of types of data indicating the contents of control of various effects operations with different effects as effect control patterns. For example, each of the effect control pattern tables 250A to 250D only needs to include a symbol variation control pattern table and a notice effect control pattern table.

  In the symbol variation control pattern table, for a plurality of variation patterns, etc., during the period from the start of variable display of the rendering symbol to the stop display (derivation display) of the finalized symbol that becomes the final stop symbol Control contents of various effect operations such as a variable display operation of the effect symbol in the display area of the display device 9, an effect display operation in the reach effect, and an effect symbol display operation in the variable display effect such as “pseudo-ream” and “slip”. It is only necessary that a plurality of types of data to be shown are stored as symbol variation control patterns. In the notice effect control pattern table, a plurality of types of data indicating the control content of the effect operation in the notice effect need only be stored as the notice effect control pattern in correspondence with a plurality of notice patterns prepared in advance. The effect control pattern tables 250A to 250D may be address management tables that manage the storage addresses of pattern data constituting a plurality of types of effect control patterns. In this case, in the effect control ROM, table data constituting each effect control pattern table 250A to 250D is stored in a predetermined storage area, and a pattern configuring each effect control pattern in a different area from this storage area. Data only needs to be stored.

  Regardless of whether the effect mode in the pachinko gaming machine 1 is a plurality of modes A, mode B, mode C, or mode N, the symbol variation control pattern or the notice effect control pattern includes the control details of the common effect operation. Data to indicate may be included. In this case, for the data indicating the control content of the rendering operation common to each rendering mode, the common rendering control pattern table provided separately from the rendering control pattern tables 250A to 250D corresponding to each rendering mode, etc. It may be stored as a pattern. As an example, the control contents of the rendering operation associated with the variable display of the rendering symbol in the period before the variable display state of the rendering symbol becomes the reach state are individually associated with each rendering mode, and each rendering control pattern table It is specified by the symbol variation control pattern stored in 250A to 250D. On the other hand, the control contents of the rendering operation including the reach rendering after the variable display state of the rendering symbol has reached the reach state is common to each rendering mode, and the symbol variation stored in the common rendering control pattern table is stored. It may be specified by a control pattern.

  FIG. 105 (A) shows a configuration example of the effect control pattern. Various effect control patterns such as a design variation control pattern, a notice effect control pattern, a mode transition effect control pattern stored in the mode transition effect control pattern table 251 or various effect control patterns are, for example, an effect control process timer determination value, a display Consists of control data for controlling various performance operations such as control data, sound control data, lamp control data, operation detection control data, and end code. It is only necessary to set the switching timing or the like. In addition, the effect control pattern may include, for example, movable member control data for designating the content of operation control in a movable member provided inside or outside the game area 7. The effect control process timer determination value is a value (determination value) to be compared with the value of the effect control process timer (effect control process timer value) provided in a predetermined area of the effect control RAM incorporated in the effect control microcomputer 100. ) And a determination value corresponding to the execution time (effect time) of each effect operation is set in advance. In place of the effect control process timer determination value, for example, a predetermined effect control command is received from the main board 31, or a predetermined process is executed as a process for controlling the effect operation in the effect control microcomputer 100. Data indicating the switching timing of effect control or the like may be set corresponding to predetermined control content or processing content.

  The display control data includes data indicating the display mode of the effect image in the display area of the effect display device 9 such as data indicating the change mode of each effect symbol during variable display of the effect symbols. That is, the display control data is data that designates the display operation of the effect image in the display area of the effect display device 9. The audio control data includes data indicating an audio output mode from the speaker 27, such as data indicating an output mode of a sound effect or the like interlocked with the variable display operation of the effect symbol during the variable display of the effect symbol. That is, the audio control data is data that specifies an audio output operation from the speaker 27. The lamp control data includes data indicating the lighting operation mode of the light emitter, such as the decorative lamp 25, the top frame lamp 28a, the left frame lamp 28b, and the right frame lamp 28c. That is, the lamp control data is data for designating the lighting operation of the light emitter. The operation detection control data includes data indicating a period during which an operation on the operation unit such as a predetermined operation button is effectively detected, control contents of the rendering operation when the operation is effectively detected, and the like. That is, the operation detection control data is data that designates an effect operation corresponding to an operation on the operation unit. Note that these control data do not have to be included in all the effect control patterns, but an effect control pattern including a part of the control data according to the contents of the effect operation by each effect control pattern. There may be.

  FIG. 105 (B) is a diagram for describing various rendering operations executed according to the content of the rendering control pattern. In the production control microcomputer 100, the production control CPU 101a determines the control content of the production operation according to various control data included in the production control pattern. For example, when the effect control process timer value matches one of the effect control process timer determination values, the effect design process is displayed in a manner specified by the display control data associated with the effect control process timer determination value, and the character Control is performed to display effect images such as images and background images in the display area of the effect display device 9. In addition, control is performed to output sound from the speaker 27 in a mode specified by the audio control data, and control is performed to blink the light emitter in a mode specified by the lamp control data, and a period specified by the operation detection control data. Control for changing the rendering operation is performed based on the operation on the operation unit detected in step. Note that dummy data (data not specifying control) may be set as data corresponding to a production component that does not become a control target even though it corresponds to the production control process timer determination value.

  The effect control CPU 101a in the effect control microcomputer 100 sets the effect control pattern based on the variation pattern indicated in the variation pattern designation command, for example, when starting variable display of the effect symbol. Here, when setting the effect control pattern, the pattern data constituting the corresponding effect control pattern may be read from the effect control ROM and temporarily stored in a predetermined area of the effect control RAM. The storage address of the effect control ROM of the pattern data constituting the effect control pattern may be temporarily stored in a predetermined area of the effect control RAM, and the reading position of the stored data in the effect control ROM may be specified. After that, every time the production control process timer value is updated, it is determined whether or not it matches any of the production control process timer judgment values. If they match, the production operation according to the corresponding various control data Control. In this way, the effect control CPU 101a performs effects devices (effect display device 9, speaker 27, decoration lamp 25, etc.) according to the contents of process data # 1 to process data #n (n is an arbitrary integer) included in the effect control pattern. The control of the light emitter etc. is advanced. In each process data # 1 to process data #n, display control data # 1 to display control data #n and voice control data # 1 to voice control associated with production control process timer determination values # 1 to #n are provided. Data #n, lamp control data # 1 to lamp control data #n, and operation detection control data # 1 to operation detection control data #n indicate the control content of the rendering operation in the rendering device and specify the execution of the rendering control. Control execution data # 1 to production control execution data #n are configured.

  A command according to the effect control pattern set in this way is output from the effect control microcomputer 100 to the VDP 109, the audio output board 70, and the like. In the VDP 109 that has received a command from the effect control microcomputer 100, the image data indicated by the command is read from the CGROM and temporarily stored in the VRAM. In the audio output board 70 that has received a command from the production control microcomputer 100, for example, the voice synthesis IC 753 reads the voice data indicated by the command from the voice data ROM 754 and temporarily stores it in the voice RAM or the like. Expand.

  FIG. 106 is a flowchart showing the effect control process (step S785) in the effect control main process shown in FIG. In the effect control process, the effect control CPU 101a performs one of steps S800 to S807 in accordance with the value of the effect control process flag. In each process, the following process is executed. In the effect control process, the display state of the effect display device 9 is controlled to realize variable display of effect symbols.

  For example, the gaming machine has two start winning ports, a first start winning port and a second starting winning port, and is configured to be able to display two special symbols, a first special symbol and a second special symbol, in a variable manner. If there is, the control related to the variable display of the effect symbol synchronized with the variation of the first special symbol and the control related to the variable display of the effect symbol synchronized with the variation of the second special symbol are executed in one effect control process. What should I do? On the other hand, the variable display of the effect symbol synchronized with the variation of the first special symbol and the variable display of the effect symbol synchronized with the variation of the second special symbol are executed by separate effect control process processing. May be. Further, in this case, it may be determined which special symbol variation display is being executed depending on which representation control process processing is performing the variation display of the representation symbol.

  Variable display start waiting process (step S800): It is confirmed whether or not a variation pattern command has been received from the game control microcomputer 560. Specifically, it is confirmed whether or not the variation pattern command reception flag set in the command analysis process is set. If the variation pattern command has been received, the value of the effect control process flag is changed to a value corresponding to the variable display effect setting process (step S801).

  Variable display effect setting processing (step S801): Settings for executing various effect operations during variable display of effect symbols are performed. Thereafter, control is performed so that the variation of the effect symbol is started. Then, the value of the effect control process flag is updated to a value corresponding to the variable display effect process (step S802).

  Effect processing during variable display (step S802): Controls the switching timing of each fluctuation state (fluctuation speed) constituting the fluctuation pattern and monitors the end of the fluctuation time. In addition, control for executing various rendering operations is performed in accordance with the progress of variable display of the rendering symbols. When the variation time ends, the effect symbol is stopped and displayed, and then the value of the effect control process flag is updated to a value corresponding to the special symbol waiting process (step S803).

  Special figure waiting process (step S803): It is checked whether or not a hit start designation command is received from the game control microcomputer 560. Specifically, it is confirmed whether or not a hit start designation command reception flag is set in the command analysis process. If the hit start designation command is received, it is confirmed whether the game is controlled to the big hit gaming state or the small hit gaming state based on the EXT data. When the small hit game state is controlled, the value of the effect control process flag is updated to a value corresponding to the small hit medium effect process (step S804). In the case of being controlled to the big hit gaming state, the value of the production control process flag is updated to a value corresponding to the big hit medium production process (step S806). When a predetermined time has elapsed without receiving the hit start designation command, the value of the effect control process flag is updated to a value corresponding to the variable display start waiting process (step S800).

  Small hit effect processing (step S804): Control during the small hit game is performed. For example, the display control of the effect image in the effect Hijisokochi 9 is performed using the patterns for small hits included in the various effect control patterns. Then, the value of the effect control process flag is updated to a value corresponding to the small hit end effect process (step S805).

  Small hit end effect processing (step S805): In the effect display device 9, display control is performed to notify the player that the small hit game state has ended. Then, the value of the effect control process flag is updated to a value corresponding to the variable display start waiting process (step S800).

  Big hit effect processing (step S806): Control during a big hit game is performed. For example, when a special winning opening opening designation command or a special winning opening open designation command is received, display control of the number of rounds in the effect display device 9 is performed. Then, the value of the effect control process flag is updated to a value corresponding to the ending effect process (step S807).

  Ending effect processing (step S807): In the effect display device 9, display control is performed to notify the player that the big hit gaming state has ended. Then, the value of the effect control process flag is updated to a value corresponding to the variable display start waiting process (step S800).

  Next, the waiting process per special figure (step S803) in the effect control process will be described. FIG. 107 is a flowchart illustrating an example of a special figure waiting process. In the special symbol waiting process, the effect control microcomputer 100 (specifically, the effect control CPU 101a) first determines whether or not a predetermined hit start designation command reception waiting time has elapsed (step S811). . The hit start designation command reception waiting time may be set, for example, when the effect symbol is stopped and displayed (derived display) with the end of the variation time in the variable display effect process.

  If the hit start designation command reception waiting time has not elapsed (N in step S811), it is determined whether or not a hit start designation command has been received (step S812). When a winning start designation command is received (Y in step S812), to notify the start of the big hit gaming state or the small hit gaming state among the various effect control patterns stored in the various effect control pattern tables. The effect control pattern for hit notification prepared in the above is selected and set as a usage pattern (step S813). At this time, for example, based on the special figure display result ("big hit" or "small hit", big hit type, etc.) specified from the EXT data of the hit start designation command, any of a plurality of various effect control patterns is used as the usage pattern. It is only necessary to decide whether or not to do so.

  Thereafter, setting for starting control of the hit notification operation is performed based on the presentation control execution data read from the presentation control pattern set as the usage pattern (step S814). For example, a predetermined time is set as the hit notification time that is the execution time for performing the hit notification operation. Then, the display control command designated by the display control data is transmitted to the VDP 109, the command corresponding to the voice data designated by the voice control data is sent to the voice output board 70, and the lamp control data is designated. Of the signal output to the lamp driver board 35, a part or all of the signal output may be performed sequentially or in parallel (if only one operation is performed). As a result, the variable display result is “big hit” or the like by the display of the effect image in the display area of the effect display device 9, the output operation of the sound or sound effect from the speaker 27, the lighting operation of the light emitter such as the decoration lamp 25, or the like. “Small hit” can be notified that the gaming state is controlled to the big hit gaming state or the small hit gaming state.

  Subsequently, for example, it is confirmed whether or not the special figure display result specified from the EXT data of the hit start designation command is “big hit” (step S815). When the special figure display result is not “big hit” (N in step S815), it is determined that the game is controlled to the small hit gaming state, and the value of the production control process flag corresponds to the small hit effect production process (step S804). Update to the specified value. When the special figure display result is “big hit” (Y in step S815), it is determined that the game is controlled to the big hit gaming state, and the value of the production control process flag is a value corresponding to the big hit medium production process (step S806). Update to

  If the hit start designation command reception waiting time has elapsed in step S811 (Y in step S811), for example, by checking a mode flag formed in a predetermined area of the effect control RAM, the current effect mode is changed. Specify (step S818). Then, it is determined whether or not the specified production mode is mode N (step S819). If the current effect mode is not mode N (N in step S819), it is determined whether or not it is the end timing of the short-time state (step S820). If it is the end timing of the short-time state (Y in step S820), a setting for shifting the effect mode to the mode N is performed (step S821). For example, the mode flag value is set to a value corresponding to the mode N, and the mode transition effect control pattern MCN stored in the mode transition effect control pattern table 251 is selected and set as a use pattern at the time of mode transition effect.

  Thereafter, the value of the effect control process flag is updated to a value corresponding to the variable display start waiting process (step S800) (step S822).

  Next, the big hit effect processing (step S806) in the effect control process will be described. FIG. 108A is a flowchart showing an example of the big hit effect processing. In the big hit effect processing, the effect control CPU 101a first determines whether or not the hit notification time has elapsed (step S831). When the hit notification time has not elapsed (N in step S831), the hit notification operation is controlled (step S832).

  When the hit notification time has elapsed (Y in step S831), it is determined whether or not it is a jackpot promotion promotion period in which a probability variation promotion effect that becomes a jackpot promotion effect is executed (step S833). The jackpot promotion effect period is a predetermined effect period when the probability change promotion effect is executed based on the determination result of whether or not to execute the probability change promotion effect at a predetermined probability change promotion effect timing. May be set as. When it is the big hit promotion promotion period (Y in step S833), operation control in the big hit middle promotion effect is performed (step S834).

  If it is not the big hit promotion promotion period (N in step S833), it is determined whether or not it is the end timing of the big hit effect (step S835). For example, when a hit end designation command transmitted from the main board 31 is received, it may be determined that it is the end timing of the big hit effect. If it is not the end timing of the big hit effect (N in step S835), operation control in the big hit effect is performed according to the number of rounds that is the number of rounds executed in the big hit gaming state (step S836).

  If it is the end timing of the big hit effect (Y in step S835), the current effect mode is specified by checking the mode flag, for example (step S837). In addition, the presence / absence of the probability change notification is specified from the final stop symbol (the stop symbol at the end of the variation time) in the current variation and the production content in the probability variation promotion effect (step S838). Then, based on the current effect mode, the presence / absence of probability change notification, and the like, the effect mode to be transferred according to the mode change setting shown in FIG. 108 (B) is set (step S839). The mode transition setting shown in FIG. 108 (B) corresponds to the mode transition example shown in FIG. At this time, the value of the mode flag is set to a value corresponding to the effect mode after the transition, and one of the mode transition effect control patterns stored in the mode transition effect control pattern table 251 is selected, and at the time of the mode transition effect Set as usage pattern. Thereafter, the value of the effect control process flag is updated to a value corresponding to the ending effect process (step S807) (step S840). Thus, when the big hit gaming state ends, the transition effect mode is set based on the fact that the mode control condition for transitioning the effect mode is established. At this time, for example, it is possible to control to a common effect mode that can execute a common effect, such as the mode A or the mode B effect mode, regardless of whether the state is the probability variation state or the short time state. In addition, even when the game is controlled to the normal state instead of the short-time state after the big hit gaming state is ended, it is common regardless of whether the state is the probability change state or the normal state by shifting to the mode A or the mode B. What is necessary is just to enable it to control to the common production | presentation mode which can perform this production.

  In addition, when the probability change promotion effect is executed as the ending effect, the process of steps S837 to S839 may be executed after the probability change promotion effect is executed. Alternatively, the production content of the probable change promotion effect in the ending effect may be specified in advance, and an effect mode may be set that shifts according to the presence / absence of the probable change notification from the identification result.

  FIG. 109 shows an example of the background in each effect mode. FIG. 109A shows the background in mode N. FIG. In mode N (normal mode), no image is displayed on the background as shown in FIG. FIG. 109B shows the background in mode A. In mode A, an image of the sea is displayed as shown in FIG. FIG. 109C shows the background in mode B. In mode B, a mountain image is displayed as shown in FIG. FIG. 109D shows the background in mode C. In mode C, a space image is displayed as shown in FIG. Thus, each effect mode is distinguished by the background image. In addition to this, each effect mode may be distinguished by displaying one or both of the effect symbols and character images corresponding to each effect mode. Moreover, according to each production | presentation mode, you may distinguish each production | generation mode by varying the sound effect output from the speaker 27 during the variable display of production | presentation symbol.

  If the notification of entering the probable change state is not made before the jackpot gaming state based on the fact that the jackpot symbol is derived and displayed as the display result of the special symbol on the special symbol display 8, the jackpot gaming state is ended. Later, control is made to the probability variation state or the time reduction state, and the mode is shifted to the mode A or the mode B effect mode in which it is not possible to specify the probability variation state or the time reduction state. In other words, the mode A and mode B production modes are common production modes in which a common production can be executed regardless of whether or not the gaming state is a certain change state.

  As described above, according to this embodiment, the game control microcomputer 560 stores, for example, data indicating a special game state in addition to the fact that initialization processing is not executed when power is supplied to the gaming machine. Based on what has been done, an on-state signal is output to the outside of the gaming machine until a predetermined output stop condition is satisfied. Thereby, the gaming state when the power supply of the gaming machine is started can be managed by an external device such as a hall computer, and can be easily grasped by the manager of the game hall. For example, if the gaming state is a probable change state at the previous stoppage of power supply in the gaming machine (at the time of power failure), the setting at the time of power failure recovery when the power supply of the gaming machine is started (step of FIG. 27) (Refer to S91), and there is a possibility that the recovery is performed with the probability variation state. In particular, when there is a common performance mode in which a common performance can be executed regardless of whether or not the gaming state is a certain change state, such as the mode A or the mode B, the appearance of the gaming machine From the top, it may be impossible or extremely difficult to determine whether or not the state has been changed. If the game is restored after the recovery, and the game is played after the recovery, the special figure display result easily becomes a “hit” and the game is controlled to the big win game state. There is a risk of profit. Therefore, in this embodiment, it is possible to easily recognize the gaming state when the power supply of the gaming machine is started, and to prevent such disadvantages from occurring. In this case, it is not necessary for an administrator of the game hall to monitor individual gaming machines at power-on to check whether they are in a special gaming state such as a probable change state. It is possible to easily check whether there is a gaming machine in a gaming state.

  In addition, according to this embodiment, the game control microcomputer 560 indicates that the initialization process has been executed when the game machine is powered on, and that a predetermined error (in this example, an abnormality to the start winning port 14). A security signal is output to the outside of the gaming machine based on the establishment of a predetermined signal output condition including that it has been determined that (winning) has occurred. In this case, the game control microcomputer 560 has a common output terminal (a terminal board of the terminal board) provided in the gaming machine when the initialization process is executed and when it is determined that a predetermined error has occurred. A security signal is output from the common connector CN8). The game machine specific information can also be output from a common output terminal from which such a security signal is output. As a result, while the number of wires between the gaming machine and the external device is reduced, it is possible to prevent fraud including when the power supply to the gaming machine is started.

  Further, when a predetermined signal output condition is newly established when a security signal is output (in this example, when an abnormal winning to the start winning opening 14 is newly detected), an output time for outputting the security signal Is extended. Therefore, by outputting a security signal based on the execution of the initialization process, it is possible to prevent an illegal act performed when the gaming machine is powered on. In addition, since the security signal is output to the common output terminal when the initialization process is executed and when it is determined that a predetermined error has occurred, the waste of the signal line for external output is reduced. Can do. Therefore, it is possible to reduce the waste of the signal line for external output while preventing an illegal act performed when the power to the gaming machine is turned on.

  Also, according to this embodiment, the game control microcomputer 560 is based on the detection signal input from the start port switch 14a (proximity switch) and the detection signal input from the winning confirmation switch 14b (photo sensor). When it is determined that the difference between the number of game balls detected by the start port switch 14a and the number of game balls detected by the winning confirmation switch 14b exceeds a predetermined threshold (in this example, 10 or more). As a predetermined error, it is determined that an abnormal winning to the start winning opening 14 has occurred. In this embodiment, the start port switch 14a and the winning confirmation switch 14b are constituted by sensors of different detection methods (in this example, a proximity switch and a photo sensor). For this reason, it is possible to more reliably detect fraudulent acts with respect to the switch that detects the game ball, and to take certain measures against fraud.

  Further, according to this embodiment, the game control microcomputer 560 executes the special symbol variation display and the prize ball payout process based on only the detection signal input from the start port switch 14a. . The detection signal input from the winning confirmation switch 14b is used only for determining whether or not an abnormal winning to the start winning opening 14 has occurred. Therefore, since the special symbol variation display and the prize ball payout process are performed based on the detection result of one of the switches, it is possible to prevent an increase in the processing burden accompanying the strengthening of countermeasures against fraud.

  In addition, according to this embodiment, the game control microcomputer 560 determines that the difference between the number of game balls detected by the start port switch 14a and the number of game balls detected by the winning confirmation switch 14b is a predetermined value. More than the difference (for example, 3) between the number of detected game balls in the start opening switch 14a and the number of detected game balls in the winning confirmation switch 14b when the inside of the start winning opening 14 is in a blocked state. It is determined whether or not the value (10 in this example) has been exceeded. Therefore, when a game ball stays in the start winning opening 14 and becomes in a clogged state, it is possible to prevent erroneous determination that an abnormal winning to the starting winning opening 14 has occurred. Accordingly, it is possible to prevent erroneous determinations associated with strengthening countermeasures against fraud.

  In addition, according to this embodiment, the game control microcomputer 560 has a predetermined error (in this example, an abnormal winning to the start winning opening 14) when the initialization process is executed when the gaming machine is turned on. ) To output a security signal over different times. Specifically, in this embodiment, when the initialization process is executed when the power to the gaming machine is turned on, a security signal is output to the outside for 30 seconds, and an abnormal winning at the start winning opening 14 is detected. When the security signal is issued, a security signal is externally output for 4 minutes. Therefore, by determining the output time of the security signal, it is possible to determine whether the initialization process has been performed or a predetermined error has occurred in an external device such as a hall computer. It becomes.

  For example, in a game management device that manages game-related information that occurs in association with a game in a gaming machine such as a hall computer or a terminal device, at least based on receiving a security signal that is a first state identification signal, A first state including that a predetermined initialization process (see steps S10 and S11 in FIG. 27) has been executed in the gaming machine and that a predetermined error such as the occurrence of an abnormal winning at the start winning opening 14 has occurred. Recognize that occurred. Further, in this gaming management device, the initialization process is not executed when power supply is started in the gaming machine based on the receipt of the on-time state signal as the second state specifying signal. In addition, it is recognized that a second state in which data indicating a specific gaming state such as a probability variation state is stored has occurred. Corresponding to the first state and the second state thus recognized, a predetermined process such as a notification operation control process corresponding to each state is executed. As a result, it is possible to easily grasp the gaming state when the power supply of the gaming machine is started, and it is possible to easily detect an illegal act performed when the power supply of the gaming machine is started and Can take appropriate anti-fraud measures.

  In addition, the gaming control microcomputer 560 may be configured based on the fact that a predetermined information output condition including a part or all of the gaming machine, for example, when the gaming machine is turned on, when a big hit, or when the door is opened, is established. The game machine specific information is output to the outside. The game machine unique information is unique information given individually in advance for each product of the pachinko gaming machine 1 or for each product (each chip) of the game control microcomputer 560. Also, after the power supply to the gaming machine is started, the door opening signal is output together with the gaming machine specific information when the door is opened, while only the door opening signal is output when the power supply to the gaming machine is stopped. . As a result, it is possible to quickly find an illegal act by changing the chip of the game control microcomputer 560 or exchanging the main board 31 and to prevent the illegal act.

  Further, according to this embodiment, when the gaming machine specific information is output based on the establishment of any one of the information output conditions, the new gaming machine specific information is updated even if other information output conditions are satisfied. The current output state is maintained by regulating the output. Thereby, it is possible to avoid output setting conflicts so as not to interrupt the gaming machine specific information, and to reliably output the gaming machine specific information to an external device such as a hall computer. It is possible to appropriately find fraudulent acts due to replacement or replacement of the main board 31.

  Further, according to this embodiment, along with the output of the gaming machine specific information, a state signal that can specify a predetermined state in the gaming machine, such as one jackpot signal, two jackpot signals, or a door opening signal is output. . As a result, it is possible to limit the time when fraudulent acts such as changing the chip of the game control microcomputer 560 or replacing the main board 31 are performed, and the possibility that fraud is prevented is increased. .

  In addition, according to this embodiment, for example, gaming machine specific information is output to a plurality of external devices including part or all of a hall computer or a card unit. Validity can be determined. This further increases the possibility that fraud is prevented.

  Further, according to this embodiment, the gaming machine specific information can be output by the serial signal system. Thereby, fraudulent acts can be prevented while reducing the number of wires between the gaming machine and the external device.

  Further, according to this embodiment, the game control microcomputer 560 and the payout control microcomputer 370 transmit and receive control commands by serial communication. Further, the game control microcomputer 560 sends a connection confirmation command for confirming the communication connection state with the payout control microcomputer 370 every time a predetermined period (1 second in this example) elapses. To 370. The payout control microcomputer 370 transmits a connection OK command to the game control microcomputer 560 based on the reception of the connection confirmation command. In this case, the payout control microcomputer 370 is connected in such a manner that the game control microcomputer 560 can recognize the control state (in this example, a prize ball error, a full tank error, a ball shortage error, and a payout number error error). The command is transmitted to the game control microcomputer 560. With such a configuration, by using a serial communication method, it is possible to facilitate wiring between the game control microcomputer 560 and the payout control microcomputer 370. In addition, the control state signal (response signal to which the control state is added) is transmitted by placing the control state on the connection OK command that the payout control microcomputer 370 periodically outputs based on the reception of the connection confirmation command. Can do. Therefore, it is possible to prevent the control state signal from being missed without considering the output timing of the control state signal, and the communication between the game control microcomputer 560 and the payout control microcomputer 370 is reliably performed. be able to. In this embodiment, the cycle (interval) for transmitting the connection confirmation command is 1 second, but it may be 0.5 seconds or the like.

  Further, according to this embodiment, the game control microcomputer 560 resets a predetermined period (1 second in this example) to the prize ball process timer when the execution of the payout control is finished, and the prize ball process. Measurement control by the timer is started (see step S52505). If the number of prize balls is not stored (specifically, if no prize ball command output counter has a count value of 1 or more in step S52301), the game control microcomputer 560 resets the game. A new connection confirmation command is transmitted to the payout control microcomputer 370 based on the time-out of the prize ball process timer. For this reason, an interval period can be provided between the end of execution of payout control and the transmission of a new connection confirmation command, and processing at the end of execution of payout control is concentrated, and a new connection check command is overwritten. Can be prevented.

  Further, according to this embodiment, the game control microcomputer 560 transmits a winning ball number command to the payout control microcomputer 370 based on the detection of a winning regardless of the transmission timing of the connection confirmation command. To do. Further, the payout control microcomputer 370 transmits a prize ball number reception command based on the reception of the prize ball number command, and receives a prize ball preparation command during execution of the payout control. The signal is transmitted to the game control microcomputer 560 every signal output period (1 second in this example). In this case, the payout control microcomputer 370 receives the prize ball in such a manner that the game control microcomputer 560 can recognize the control state (in this example, a prize ball error, a full tank error, an out of ball error, and a payout number error error). The preparing command is transmitted to the game control microcomputer 560. Further, the game control microcomputer 560 stops the transmission of the connection confirmation command based on the reception of the prize ball number reception command. Therefore, it is possible to reduce the control burden of the game control microcomputer 560 by not performing connection control command transmission control unnecessarily during execution of payout control. Even when the payout control is being executed, the control state signal can be output by adding the control state to the award ball preparation command, so that the game control microcomputer 560 can recognize the control state. it can.

  Further, according to this embodiment, the game control microcomputer 560 receives the award ball end command and then stores the number of award balls (specifically, the prize ball command output counter in step S52301). If the count value is 1 or more), a new prize ball number command is immediately transmitted to the payout control microcomputer 370 regardless of the transmission of the connection confirmation command. Therefore, it is possible to speed up the execution process of the payout control.

  In addition, according to this embodiment, the game control microcomputer 560 determines whether a predetermined error (in this example, a prize ball error, a full tank error, a full ball error, based on the control state indicated by the received connection OK command. , And a payout quantity abnormality error). Then, the game control microcomputer 560 transmits a prize ball number command to the payout control microcomputer 370 on the condition that it is determined that a predetermined error has not occurred. Therefore, it is possible to prevent the inconvenience of sending a prize ball number command when the payout control cannot be normally performed due to an error state. In particular, in this embodiment, since the RAM provided in the payout control microcomputer 370 is not backed up by the backup power supply, if a prize ball number command is transmitted when there is an abnormality in the payout control, the power is reset. For example, the memorized number of prize balls may be lost, which may cause a great disadvantage to the player. Therefore, in this embodiment, when there is an abnormality in the payout control, the prize ball number command is transmitted while the memory of the prize ball number is retained on the game control microcomputer 560 side backed up by the backup power source. It is possible to prevent such a disadvantage from occurring by controlling to hold.

  Further, according to this embodiment, the game control microcomputer 560 increases the time interval for transmitting the connection confirmation command when the connection OK command cannot be received after transmitting the connection confirmation command. Whenever a specific period (10 seconds in this example) elapses, the control is switched to the connection confirmation command transmission. Therefore, in a state where the communication state between the game control microcomputer 560 and the payout control microcomputer 370 is unstable, the connection confirmation command transmission process is performed by extending the interval period until the connection confirmation command is transmitted. Can be performed less frequently, and a wasteful processing load can be reduced.

  Further, according to this embodiment, the payout control microcomputer 370 causes the game to occur when a predetermined error (in this example, a prize ball error, a full tank error, a ball shortage error, and a payout number error) occurs. Information that allows the control microcomputer 560 to recognize a predetermined error is set by changing a specific bit of the connection OK command, and the connection OK command in which the setting has been made is transmitted to the game control microcomputer 560. The game control microcomputer 560 transmits a frame state display command in which information capable of recognizing a predetermined error set in the received connection OK command is set as it is to the effect control microcomputer 100. Then, based on the reception of the frame state display command, the production control microcomputer 100 controls the production device (the production display device 9 in this example) to notify that a predetermined error has occurred. Do. Therefore, it is possible to notify that a predetermined error has occurred using the effect device, and to reduce the processing load on the game control microcomputer 560.

  In addition, according to this embodiment, the payout control microcomputer 370 has a payout excess exceeding the number of unpaid game balls to be paid out and the number of unpaid games to be paid out. The number of shortage payouts that did not reach the ball is cumulatively counted using a payout number abnormality counter. When the value of the payout number abnormality counter becomes equal to or greater than a predetermined payout number error error determination value (2000 in this example), the payout control is stopped and the payout stop state is controlled. Therefore, instead of judging each payout control, the payout control is executed by comprehensively judging the payout control executed under an abnormal condition based on the value of the payout number abnormality counter counted up cumulatively. Can be stopped. Therefore, it is possible to more accurately prevent the act of illegally paying out the game ball.

  Further, according to this embodiment, the payout control microcomputer 370 counts up the value of the payout number abnormality counter when a payout shortage number equal to or greater than a predetermined reference number (2 in this example) occurs. Therefore, it is possible to prevent inconvenience that the execution of the payout control is stopped more than necessary. In other words, since there are not a few small numbers (1 in this example) of insufficient payouts in the operating state of the gaming machine, the number of insufficient payouts exceeding the predetermined reference number (2 in this example) has occurred. By counting up on the condition, it is possible to prevent the execution of the payout control from being stopped more than necessary.

  Further, according to this embodiment, the payout control microcomputer 370 executes re-payout control for driving and controlling the ball payout device 97 to pay out only one game ball when a payout shortage occurs. . If the payout of the game ball is not detected even after the re-payout control is executed, the value of the payout number abnormality counter is counted up. Therefore, even if the number of payout shortages is small, it is possible to appropriately stop the execution of payout control by reflecting it in the count value of the payout number abnormality counter, and to take illegal measures to prevent the act of illegally paying out game balls. Can be strengthened.

  Further, according to this embodiment, when the payout number abnormality error is detected and controlled to the payout stop state, the payout stop state is canceled on condition that the power supply of the gaming machine is reset. Therefore, in order to release the payout stop state, the game store clerk must confirm the abnormal state and then perform the release operation. Therefore, the payout stop state is canceled illegally and the game is continued in the abnormal state. This can be prevented.

  Further, according to this embodiment, the RAM 55 provided in the gaming control microcomputer 560 can retain the stored contents for a predetermined period by the backup power supply even when the power supply to the gaming machine is stopped. In addition, when the game control microcomputer 560 is controlled to be in the payout stop state, the game control microcomputer 560 prohibits the transmission of the winning ball number command even if a winning occurs. For this reason, the number of prize balls stored in the RAM 55 (specifically, the value of the prize ball command output counter) is cleared even though the payout is stopped due to an abnormality caused by the gaming machine side that is not caused by fraud. It is possible to prevent such a situation from occurring, and it is possible to prevent the player from being disadvantaged.

  Further, according to this embodiment, the game control microcomputer 560 adds the prize ball number to the prize ball number counter at the timing of sending the prize ball number command, and receives the prize ball information based on the received prize ball information. Subtract 10 from the value of the ball counter. Then, based on the fact that the value of the prize ball number counter is equal to or greater than a predetermined prize ball shortage determination value (501 in this example), it is determined that there is a prize ball shortage error. Based on the fact that it is less than the determination value (0 in this example), it is determined that there is an excessive prize ball error. Therefore, the abnormal state can be detected by both the game control microcomputer 560 and the payout control microcomputer 370. Accordingly, it is possible to further strengthen the fraud countermeasure that prevents the act of illegally paying out the game ball.

  Further, according to this embodiment, the game control microcomputer 560 transmits a connection signal indicating a connection state of communication with the payout control microcomputer 370 to the payout control microcomputer 370 via the output port 57. Since the payout control microcomputer 370 can confirm the communication connection state at any timing, the payout of the prize ball is performed when the communication connection state is abnormal. This can be surely prevented.

  In the above embodiment, the game control microcomputer 560 normally transmits a connection confirmation command 1 second after the connection OK command is received, and when a communication error occurs (for example, connection When the OK command cannot be received), the connection confirmation command is transmitted 10 seconds after the connection confirmation command is transmitted, and the period of 1 second or 10 seconds is measured by a timer (a counter configured by software). However, the connection confirmation command may be transmitted by an internal interrupt that occurs when the counter updated as hardware by the internal clock reaches a predetermined value (1 second or 10 seconds). In that case, the counter may be cleared by reception of the connection OK command, or the counter may be cleared if an internal interrupt is generated with a predetermined value.

  The present invention is not limited to the above embodiment, and various modifications and applications are possible. For example, in the above embodiment, a configuration for controlling to a common effect mode such as the effect mode of mode A or mode B based on the fact that a predetermined mode control condition such as the end of the big hit game state is established, When the power supply of the machine is started, the initialization process is executed in response to the operation on the clear switch 914 and the occurrence of a predetermined error such as the occurrence of an abnormal winning at the start winning opening 14 A configuration that outputs a security signal externally based on the establishment of a predetermined signal output condition, special processing such as a probability change state in addition to the fact that initialization processing is not executed when power supply to the gaming machine is started A configuration that outputs a state signal at the time of external input until a predetermined output stop condition is satisfied based on storing data indicating a gaming state, predetermined information Based on the force condition is satisfied, the configuration for externally outputting the gaming machine specific information, and configuration for realizing a variety of functions has been described as being provided all in a single pachinko game machine 1.

  However, the present invention is not limited to this, and a part of the configuration may be provided as long as it is necessary for solving a predetermined problem. As an example, on the premise of having a configuration for controlling to the common production mode, if it has a configuration for externally outputting the state signal at the time of input, a configuration for externally outputting the security signal, Of the configuration for externally outputting gaming machine specific information, the configuration for realizing various other functions, etc., some or all of them may not be provided. The configuration for realizing the present invention only needs to be able to solve at least one problem existing in the prior art, and is not required to solve all the problems and derivative problems.

  Next, a modified example of the physical configuration of the terminal board 160 mounted on the gaming machine will be described. 110 and 111 are explanatory views showing modifications of the physical configuration of the terminal board 160. FIG. The gaming machine is provided with a cover member 800 for covering and protecting each board such as the main board 31, the effect control board 80, and the payout control board 37, for example, as shown in FIGS. 110 and 111. As described above, the terminal board 160 may be embedded in the cover member 800. Also, a terminal board cover 801 for covering and protecting the terminal board 160 is attached to a portion of the cover member 800 where the terminal board 160 is attached. Here, FIG. 110 shows a state where the terminal board cover 801 is attached to the cover member 800, and FIG. 111 shows a state where the terminal board cover 801 is removed from the cover member 800. As shown in FIG. 111, two terminal claws 801a are provided on the upper portion of the terminal board cover 801, and the terminal board is secured by inserting the claws 801a and fastening them with screws 801b. A cover 801 can be attached.

  110 and 111, a plurality of terminals 96a, 96b, 98a, 98b,... For connecting cables with external devices such as hall computers are provided on the terminal board 160. A terminal board 900 is provided. Further, the terminal board 900 has a two-stage configuration including a terminal row including terminals 96a, 96b,... And a terminal row including terminals 98a, 98b,. One set (set of signal line and ground line). For example, in the example shown in FIGS. 110 and 111, one set of terminals 96a and 96b arranged in the horizontal direction among the terminals in the upper row of terminals is one set, and the horizontal direction of the terminals in the lower row of terminals. One set of the terminal 98a and the terminal 98b arranged in a row. Further, the terminals 96a, 96b, 98a, 98b,... Provided on the terminal board 900 are respectively provided with knobs 95a, 95b, 99a, 99b, and the knobs 95a, 95b,. The terminals 96a, 96b, 98a, 98b... Are opened by performing operations such as pressing 99a, 99b. For example, when the upper knob 95a is pressed, the cable can be connected to the terminal 96a, and when the lower knob 99a is pressed, the cable can be connected to the terminal 98a. For example, when the upper knob 95b is pressed, the cable can be connected to the terminal 96b, and when the lower knob 99b is pressed, the cable can be connected to the terminal 98b.

  110 and 111, the knobs 95a, 95b, 99a, 99b,... Provided for each of the terminals 96a, 96b, 98a, 98b,. Has been. With such a configuration, it is possible to prevent inconveniences such as accidentally operating the knob for the adjacent terminal, and improve workability when performing the work of connecting the cable to the terminal board 900. be able to.

  FIG. 112 is an explanatory diagram showing a cross-sectional structure of a portion of the cover member 800 where the terminal board 160 is attached. As shown in FIG. 112, the terminal board 160 is sufficiently placed so that the terminal board 900 provided on the terminal board 160 is located inside the surface of the cover member 800 (the X plane shown in FIG. 112). The cover member 800 is attached to the back side. As such, since the terminal board 900 provided on the terminal board 160 is configured to be inside the surface of the cover member 800 (the X surface shown in FIG. 112), the game ball is mistakenly played during the game. It is possible to prevent the occurrence of inconvenience such as contact with the terminal board 900.

  As shown in FIG. 112, the terminal board cover 801 is inclined so that the side wall portion 801c is gradually narrowed. Since the side wall 801c is inclined as described above, even when the terminal board cover 801 is attached, it is easy for a finger or the like to enter, and when connecting the cable to the terminal board 900, Workability can be improved.

  In the above embodiment, the case where the pachinko machine is applied as the gaming machine according to the present invention has been described. However, the parrot machine can also be applied as the gaming machine according to the present invention. In this case, any configuration and operation (processing) shown in the above embodiment may be applied. For example, based on the establishment of a predetermined information output condition, game machine specific information given in advance is output to an external device for each product of a parrot machine or for each product (each chip) of a control microcomputer. You may be made to do. In addition, the number of game balls taken in or returned from the parrot machine is cumulatively counted up in a counter, and when the counter value exceeds a predetermined abnormality determination value (for example, 2000), the number of game balls taken in or returned It may be determined that an abnormality has occurred in the number and the capture operation and the return operation are controlled to be stopped. It is also possible to apply a slot machine as a gaming machine according to the present invention. In this case, any configuration and operation (processing) shown in the above embodiment may be applied. For example, based on the establishment of a predetermined information output condition, game machine specific information assigned in advance is output to the external device for each product of the slot machine or for each product (each chip) of the control microcomputer. You may be made to do. In addition, the number of medals paid out from the hopper tank in the slot machine is cumulatively counted up to a counter, and if the counter value becomes a predetermined abnormality determination value (for example, 2000) or more, an abnormality has occurred in the number of medals paid out. The determination may be made so that the medal payout operation from the hopper tank is controlled to be stopped.

  For example, when applied to a slot machine or parrot machine, when a medal or game ball return operation is performed, an excessive return number or an unpaid number of returns may be counted up cumulatively. Further, for example, when applied to a hopper tank of a slot machine, the excessive number of medals and the number of unpaid medals may be counted up cumulatively. Furthermore, for example, when applied to a parrot machine, the number of excessive game balls taken or the number of insufficient game balls taken in is counted up for the purpose of detecting abnormal operation of the gaming machine, not as fraud. You may make it do.

  Hereinafter, embodiments of the slot machine will be described with reference to the drawings (FIGS. 113 and 114). As shown in FIG. 113, the slot machine 601 of the present embodiment (modified example) includes a housing (not shown) having an open front surface, a front door pivotally supported on a side end of the housing, It is composed of

  Inside the casing of the slot machine 601 of the present embodiment, reels 602L, 602C, and 602R (hereinafter also referred to as a left reel, a middle reel, and a right reel) in which a plurality of types of symbols are arranged on the outer periphery are arranged in parallel in the horizontal direction. As shown in FIG. 113, three consecutive symbols out of the symbols arranged on the reels 602L, 602C, and 602R are arranged so as to be seen from the see-through window 603 provided on the front door.

  For example, “red 7 (outline 7 in the figure)”, “BAR”, “replay”, “watermelon”, “cherry”, “bell” can be distinguished from each other on the outer periphery of the reels 602L, 602C, 602R. A plurality of types of symbols are drawn 21 in a predetermined order. The symbols drawn on the outer peripheries of the reels 602L, 602C, and 602R are displayed on the perspective window 603 in upper, middle, and lower three stages, respectively.

  The reels 602L, 602C, and 602R are provided in correspondence with each other and rotated by reel motors 632L, 632C, and 632R (see FIG. 114), so that the symbols of the reels 602L, 602C, and 602R are continuously provided in the see-through window 603. In addition to being displayed while changing, by stopping the rotation of the reels 602L, 602C, and 602R, three continuous symbols are derived and displayed on the fluoroscopic window 603 as display results.

  Further, on the front door, a medal insertion unit 604 capable of inserting medals, a medal payout exit 609 from which medals are paid out, and credits (the number of medals stored as a player's own game value) are used for one medal. A single bet switch 605 that is operated when setting the bet number of the bet, and using a credit, a specified number of bet numbers determined according to the game state within the range (in this embodiment, in the normal game state, “ 3 ”, MAXBET switch 606 operated when setting“ 1 ”for the regular bonus), medals stored as credits and the medals used for setting the bet amount are settled (for setting the credit and bet number) A check switch 610 operated when the medal used is returned), a start switch 607 operated when starting the game, Le 602L, 602C, stop switch 608L is operated to stop each rotation of the 602R, 608C, 608R are provided.

  Also, on the front door, a credit indicator 611 that displays the number of medals stored as credits, a game that displays the number of medals acquired in a big bonus, which will be described later, and an error code indicating the contents when an error occurs, etc. An auxiliary indicator 612 and a payout indicator 613 for displaying the number of medals paid out due to the occurrence of a winning are provided.

  Also, on the front door, 1 BETLED 614 that notifies that the bet number is set by 1 is lit, 2 BETLED 615 that notifies that the bet number is set is 2 and lit that 3 bets are set 3BETLED 616 to be notified by, lighting request LED 617 to notify that the medal can be inserted by lighting, start valid LED 618 to notify that the game start operation by operating the start switch 607 is effective, weight (previous game) (Waiting to start reel rotation since a certain period of time has not elapsed since the start) LED 619 during waiting to notify that it is on, LED during replay 620 to notify that it is in a replay game to be described later Is provided.

  Further, inside the MAXBET switch 606, a BET switch valid LED 621 (see FIG. 114) for notifying by lighting that the betting number setting operation by the operation of the single BET switch 605 and the MAXBET switch 606 is effective is provided. In the stop switches 608L, 608C, 608R, the left, middle, and right stop valid LEDs 622L, 622C, 622R that notify that the reel stop operation by the corresponding stop switches 608L, 608C, 608R is valid are turned on. (See FIG. 114).

  A liquid crystal display 651 capable of displaying an effect image or the like related to a game is provided at the upper center position inside the front door, and a display image displayed on the display screen through a liquid crystal display window 670 disposed in front of the liquid crystal display 651. Can be visually recognized. Further, on the left and right sides of the liquid crystal display 651, two movable accessories 675L and 675R that perform effects related to the game are respectively disposed, and are disposed in front of the left and right movable combinations 675L and 675R. As described above, the internal movable accessory 675L and 675R can be seen through from the production perspective windows 671L and 671R made of a transparent panel provided on the front door.

  Further, between the left and right movable combination objects 675L and 675R and the production perspective windows 671L and 671R, there is a concealment state in which the left and right movable combinations 675L and 675R are hidden from the production perspective windows 671L and 671R so that they cannot be seen through. , Endless shutter sheets constituting two shutter devices (not shown) that can be changed to a non-hidden state in which the left and right movable accessories 675L and 675R can be seen through the production perspective windows 671L and 671R are arranged. It is installed.

  Further, inside the front door, a reset switch 623 for detecting a reset operation for canceling an error state and a stop state excluding a RAM abnormality error by a predetermined key operation, changing a set value or checking a set value Set value display 624 for displaying the set value at that time, and the flow path of medals inserted from the medal insertion unit 604, the hopper tank (not shown) side provided inside the housing or the medal payout outlet 609 side A flow path switching solenoid 630 for selectively switching to any one of the above, a insertion medal sensor 631 for detecting a medal that has been inserted from the medal insertion unit 604 and flowed down to the hopper tank side is provided.

  Inside the casing, a reel unit (not shown) including reel sensors 633 capable of detecting the reel reference positions of the reels 602L, 602C, 602R, reel motors 632L, 632C, 632R, and reels 602L, 602C, 602R, respectively. , A hopper tank (not shown) for storing medals inserted from the medal insertion unit 604, a hopper motor 634 for paying out medals stored in the hopper tank from the medal payout outlet 609, and the hopper motor 634 being paid out. A payout sensor 635 for detecting a medal, a power supply box (not shown), and a door switch 625 for detecting the opening of the front door are provided.

  On the front face of the power supply box, a stop switch 636 for selecting enable / disable of a stop function for controlling the stop state at the end of the big bonus (a state in which the progress of the game is restricted until a reset operation is performed), An automatic checkout switch 629 for selecting whether the automatic checkout function is valid / invalid for controlling automatic checkout processing (processing for adjusting (returning) medals stored as credits regardless of the player's operation) at the end of the big bonus, Setting key switch 637 for switching to the setting change mode at startup, functioning as a reset switch for canceling an error state or a stop state except for a RAM abnormality error in normal times, and winning probability of internal lottery in the setting change mode A reset / setting switch 638 that functions as a setting switch for changing the setting value of (delay rate) Power switch 639 is operated to ON / OFF the power is provided.

  When a game is played in the slot machine 601 of this embodiment, first, medals are inserted from the medal insertion unit 604, or credits are used to set the number of bets. In order to use the credit, the single BET switch 605 or the MAX BET switch 606 may be operated. When a predetermined number of bets determined according to the gaming state are set, the pay lines L1 to L5 (see FIG. 113) become valid and the operation of the start switch 607 is valid, that is, the game can be started. It becomes a state. In the present embodiment, as the specified number of bets, three are determined in the normal gaming state, and one is determined in the regular bonus. If medals are inserted beyond the prescribed number corresponding to the gaming state, the amount is added to the credit.

  When the start switch (also referred to as a lever) 607 is operated while the game can be started, the reels 602L, 602C, and 602R rotate, and the symbols of the reels 602L, 602C, and 602R continuously change. When any one of the stop switches 608L, 608C, and 608R is operated in this state, the rotation of the corresponding reels 602L, 602C, and 602R is stopped, and the display result is derived and displayed on the fluoroscopic window 603.

  Then, when all the reels 602L, 602C and 602R are stopped, one game is completed, and a predetermined symbol combination (hereinafter also referred to as a role) is set on any of the activated pay lines L1 to L5. When the reels 602L, 602C, and 602R are stopped as a display result, a winning occurs, and a predetermined number of medals are awarded to the player and added to the credit. Further, when the credit reaches the upper limit (50 in this embodiment), medals are paid out directly from the medal payout exit 609 (see FIG. 113). If a combination of symbols with payout of medals is arranged on a plurality of activated pay lines, the total number of payouts determined for each combination of symbols aligned on the activated pay line is totaled. The total number of medals is awarded to the player. However, an upper limit (15 in this embodiment) is set for the number of medals to be awarded in one game. When the total number of medals exceeds the upper limit, the upper limit number of medals is awarded. The Rukoto. In addition, when a combination of symbols accompanying the transition of the gaming state is stopped as a display result of each reel 602L, 602C, 602R on any of the activated pay lines L1 to L5, a game corresponding to the combination of symbols Transition to the state.

  FIG. 114 is a block diagram showing a configuration of the slot machine 601. As shown in FIG. 114, the slot machine 601 includes a game control board 640 (corresponding to the game control board (main board) 31 of FIG. 8), an effect control board 690 (corresponding to the effect control board 80 of FIG. 8), a power supply The board 600 is provided, the gaming state is controlled by the game control board 640, the presentation according to the gaming state is controlled by the presentation control board 690, and the power supply board 600 is used to drive electric power for the electrical components constituting the slot machine 601. Generated and supplied to each unit.

  The game control board 640 is connected to the one-sheet BET switch 605, the MAXBET switch 606, the start switch 607, the stop switches 608L, 608C, and 608R, the settlement switch 610, the reset switch 623, the insertion medal sensor 631, and the reel sensor 633. In addition, the above-described payout sensor 635, stop switch 636, automatic settlement switch 629, setting key switch 637, and reset / setting switch 638 are connected via the power supply board 600, and detection of these connected switches is detected. A signal is input.

  The game control board 640 includes the credit display 611, the game auxiliary display 612, the payout display 613, 1 to 3 BET LEDs 614 to 616, the insertion request LED 617, the start valid LED 618, the waiting LED 619, the replaying LED 620, and the BET. A switch valid LED 621, left, middle, and right stop valid LEDs 622L, 622C, and 622R, a set value display 624, a flow path switching solenoid 630, and reel motors 632L, 632C, and 632R are connected to each other, and are described above via the power supply board 600. The hopper motor 634 is connected, and these electric components are driven based on the control of a main control unit 641 (corresponding to the game control microcomputer 560 in FIG. 8) described later mounted on the game control board 640. Like That.

  The game control board 640 includes a CPU 641a, a ROM 641b, a microcomputer having a RAM 641c as an RWM (Read / Write Memory), and an I / O port 641d, a main control unit 641 for controlling the game, a predetermined range (this embodiment) In the example, a random number generation circuit 642 for generating random numbers of 0 to 16383), a sampling circuit 643 for acquiring random numbers from the random number generation circuit, a switch such as a sensor or a switch connected to the game control board 640 directly or via the power supply board 600 Switch detection circuit 644 that detects a detection signal input from a motor, motor drive circuit 645 that controls the drive of reel motors 632L, 632C, and 632R, solenoid drive circuit 646 that controls the drive of flow path switching solenoid 630, and game control board Various indicators and LEDs connected to 640 LED drive circuit 647 that performs drive control, power supply voltage supplied to the slot machine 601 is monitored, and when a voltage drop is detected, a power drop detection that outputs a voltage drop signal to that effect to the main controller 641 A circuit 648, a reset circuit 649 that gives a reset signal to the CPU 641a when the power is turned on or when an initialization command from the CPU 641a is not input, and other various devices and circuits are mounted.

  The CPU 641a transmits various commands to the effect control board 690 via the I / O port 641d. A command transmitted from the game control board 640 to the effect control board 690 is sent in only one direction, and no command is sent from the effect control board 690 to the game control board 640. A transmission line for commands transmitted from the game control board 640 to the effect control board 690 includes a strobe (INT) signal line, a data transmission line, and a ground line, and is connected via the effect relay board 680. The game control board 640 and the effect control board 690 are not directly connected.

  On the effect control board 690, a liquid crystal display 651 (see FIG. 113) disposed on the front door of the slot machine 601, an effect LED 652, speakers 653 and 654, a reel LED 655, a shutter motor 810, a shutter sensor 811, and a movable object Electrical components such as the LED 881, the movable object motor 805, and the movable object sensor 829 are connected, and these electrical components are driven based on control by a later-described sub-control unit 691 mounted on the effect control board 690. It is like that.

  The effect control board 690 is composed of a microcomputer having a CPU 691a, a ROM 691b, a RAM 691c, and an I / O port 691d in the same manner as the main control part 641, and includes a sub-control part 691 for effect control and an effect control board 690. A liquid crystal drive circuit 692 that controls the drive of the connected liquid crystal display 651, an effect effect LED 652, a reel LED 655, an LED drive circuit 693 that controls the drive of the movable object LED 881, and a sound that controls audio output from the speakers 653 and 654. Output circuit 694, detection signal input from switches such as a reset circuit 695 that provides a reset signal to the CPU 691a when the power is turned on or when an initialization command is not input from the CPU 691a, a shutter sensor 811, a movable object sensor 829, and switches Detect the switch The CPU 691a receives a command transmitted from the game control board 640, and is mounted with a motor driving circuit 697 for controlling the driving of the H detection circuit 696, the shutter motor 810, and the movable object motor 805. In addition to performing various controls for performing effects, each part of the control circuit mounted on the effect control board 690 is controlled directly or indirectly.

  Next, the internal lottery process executed by the main control unit 641 will be described. At the timing when the start switch 607 is turned on, the sampling circuit 643 acquires (extracts) a numerical value (random number) counted by the random number generation circuit 642. The sampling circuit 643 outputs the numerical value acquired as a random number to the CPU 641a in the main control unit 641.

  The CPU 641a in the main control unit 641 uses the numerical value acquired from the sampling circuit 643 and the determination value set for each combination (small combination, replay combination, special combination, etc.) in the internal lottery table stored in the ROM 641b. By comparing, it is determined whether or not a small role / replaying role / special role is won. Further, as a table for internal lottery, a plurality of tables are provided so that the medal payout rate changes according to the set value / game state (normal game state, regular bonus). For example, in the internal lottery table, a plurality of judgment values are set for each of a small combination (cherry, bell), a re-playing combination (replay), a special combination (regular bonus, big bonus), and a loss. Further, for example, when “1” to “6” are provided as setting values that can be set by the reset / setting switch 638, the determination value is assigned so that the medal payout rate changes as the setting value number increases. Table is used. In addition, when the gaming state is a normal gaming state, a table in which a judgment value is assigned to each of the roles and outliers so that any of the small roles, replaying roles, and special roles can be won is used. In the case of a regular bonus, a table in which judgment values are assigned to the small role and the offside so that only the small role can be won (a table in which no judgment value is assigned to the replaying role / special role) is used. . The setting of the determination value in the above table is an example, and the determination value is not limited to such setting. In this embodiment, the number of bets can be set by the player only “3” in the normal gaming state and “1” in the regular bonus, but either of the normal gaming state or the regular bonus can be set. Even in the gaming state, any one of “1” to “3” can be set by the player as the bet number. A plurality of internal lottery tables having different winning probabilities for replaying and special roles may be prepared, and internal lottery may be performed using tables corresponding to the number of bets.

  As described above, in the slot machine 601 of this embodiment, the medal payout rate changes according to the set value, and the winning probability of the internal lottery is determined according to the set value. In order to change the setting value, it is necessary to turn on the power of the slot machine 601 after the setting key switch 637 is turned on. When the setting key switch 637 is turned on and the power is turned on, “1” is displayed on the setting value display 624 as the initial value of the setting value, and the setting change that allows the setting value to be changed by operating the reset / setting switch 638 is possible. Enter mode. When the reset / setting switch 638 is operated in the setting change mode, the setting value displayed on the setting value display 624 is updated by one (when the operation is further performed from the setting “6”, “1” is updated). Back to). When the start switch 607 is operated, the set value is confirmed, and the confirmed set value is stored in the RAM 641c of the main control unit 641. Then, when the setting key switch 637 is turned off, the state shifts to a state in which the game can proceed.

  When confirming the set value, the bet number can be set during execution of the process for making the bet number settable (BET process) (including a state where a medal can be inserted). When the setting key switch 637 is turned on, the setting value is displayed on the setting value display 624, and the mode shifts to a setting value confirmation mode in which the setting value set at that time can be confirmed. Then, when the setting key switch 637 is turned off, the state shifts to a state in which the game can proceed.

  In the slot machine 601 of the present embodiment, the prescribed number of bets that can be set is determined according to the gaming state as described above, and the prescribed number of bets determined according to the gaming state is set. It becomes possible to start the game on the condition. In this embodiment, there are a regular bonus and a normal gaming state as the gaming state. Among these, 1 is defined as the prescribed number of bets corresponding to the regular bonus, and the prescribed number of bets corresponding to the normal gaming state is as follows. 3 is defined. For this reason, when the gaming state is a regular bonus, the game can be started when the betting number is set to 1, and when the gaming state is the normal gaming state, the game is started when the betting number is set to 3. Can be started. In this embodiment, when a specified number of bets corresponding to the gaming state is set, all winning lines L1 to L5 are activated, and the specified number corresponding to the gaming state is If it is 1, all winning lines L1 to L5 are activated when 1 is set as the bet number, and if the specified number is 3 according to the gaming state, 3 is set as the bet number. All winning lines L1 to L5 are activated.

  In the slot machine 601 of this embodiment, when all the reels 602L, 602C, and 602R are stopped, the winning line that is activated (in the case of this embodiment, all the winning lines are always activated. The activated winning line is simply referred to as a winning line), and a winning combination is obtained when a combination of symbols called “comb” is arranged. The type of winning combination is determined according to the game state, but it can be roughly divided into a small role with payout of medals and a replay that can start the next game without the need to set the number of bets. There are a game combination and a special combination with a transition of the game state. Below, a small role and a re-playing role are collectively called a general role. In order for winning of each combination determined according to the game state to occur, it is necessary to win an internal lottery and the winning flag of the combination must be set in the RAM 641c.

  Of the winning flags for each of these combinations, the winning flag for the small role and the re-playing role is valid only in the game in which the flag is set, and is invalid in the next game. It is valid until the combination of combinations permitted by the flag is complete, and is invalid in a game having the combination of combinations permitted. In other words, once the special combination winning flag is won, even if the combination of the combination permitted by the flag cannot be made, the winning flag is not invalidated and is carried over to the next game. It becomes. As described above, in the slot machine 601 according to the present invention, when it is determined by the prize predetermining means that the generation of the specific prize is permitted and the specific prize display result is not derived to the prize variable display section, There is a carry-over means for carrying over the decision to allow the generation of a prize from the next game. In such a configuration, even when the specific winning display result is not derived to the winning variable display section, the decision to allow the occurrence of the specific winning is carried over from the next game onward, A loss to the player can be prevented.

  As a combination in the slot machine 601, a big bonus and a regular bonus are defined as a special combination, cherry and bell are defined as a small combination, and replay is defined as a re-playing combination. In addition, as a combination of combinations in the slot machine 601, big bonus + cherry and regular bonus + cherry are determined. That is, the total of the combination of the combination and combination is 7.

  In the slot machine 601 of the present embodiment, the combination of combinations and combinations of combinations that are subject to lottery differ depending on whether the gaming state is a normal gaming state or a regular bonus. Furthermore, when the gaming state is the normal gaming state, it depends on whether any special role is being carried over (whether any special role has already been set in the winning flag of the special role). The combination of combinations and combinations that are subject to lottery are also different. In this embodiment, a state number corresponding to the gaming state is assigned, and when performing an internal lottery, a state number corresponding to the current gaming state is set, and a role to be a lottery object is determined according to this state number. It becomes possible to specify. Specifically, when no special combination is carried over in the normal gaming state, “0” is set as the state number, and when any special combination is carried over in the normal gaming state, “1” is set as the state number, and “2” is set as the state number in the case of a regular bonus.

  When the gaming state is a normal gaming state and no special role is carried over, that is, when the state number is set to “0”, a big bonus, a regular bonus, a big bonus + cherry, a regular bonus + Cherry, replay, cherry, bell, that is, all combinations and combinations of combinations are subject to internal lottery. In addition, when the game state is the normal game state and any special combination is carried over, that is, when the state number is set to “1”, a combination of replay, cherry, bell combination and combination Is subject to internal lottery. Further, when the game state is a regular bonus, that is, “2” is set as the state number, the combination of cherry and bell and combinations of combinations are targeted for internal lottery.

  Cherry is awarded when the “Cherry” symbol is derived on one of the winning lines for the left reel in any gaming state, and two medals are paid out in the normal gaming state. 15 medals are paid out. If the “Cherry” symbol stops at the upper or lower level of the left reel, the combination of cherries will be aligned on the two winning lines L2 and L4 or the winning lines L3 and L5. Since you won the cherry on the winning line, 4 medals will be paid out in the normal gaming state, but in the regular bonus, even if you win the cherry on the 2 winning lines, one game Since the upper limit of the number of medals to be paid out at 15 is set to 15, only 15 medals are paid out. A bell is awarded when a combination of “Bell-Bell-Bell” is placed on any of the winning lines in any gaming state, and in the normal gaming state, 8 medals are paid out. 15 medals are paid out.

  Replay is awarded when a combination of “replay-replay-replay” is arranged on any of the winning lines in the normal gaming state. When a replay is won, the medals will not be paid out, but the next game can be started without setting the number of bets again, so the number of bets no longer required to be set in the next game (the regular bonus will not be replayed and will always be 3) This is substantially the same as when three corresponding medals are paid out.

  The regular bonus is awarded when a combination of “red 7-red 7-BAR” is arranged on any of the winning lines in the normal gaming state. When the regular bonus is won, the gaming state shifts from the normal gaming state to the regular bonus. The regular bonus ends when 12 games are consumed, or when 8 games are won (any kind of combination is possible), whichever comes first. While the game state is the regular bonus, the regular bonus medium flag is set in the RAM 641c.

  The big bonus is awarded when a combination of “red 7-red 7-red 7” is aligned on any of the winning lines in the normal gaming state. When the big bonus is won, the gaming state shifts to the big bonus. When transitioning to the big bonus, the transition to the regular bonus is performed at the same time as the transition to the big bonus, and when the regular bonus ends, if the big bonus has not ended, the transition is made to the regular bonus again and repeated until the big bonus ends Controlled by regular bonus. That is, during the big bonus, the regular bonus is always controlled. The big bonus ends when the total number of medals paid out to the player in the big bonus exceeds 465. At this time, the regular bonus is ended regardless of whether the regular bonus end condition is satisfied. While the gaming state is the big bonus, the big bonus medium flag is set in the RAM 641c.

  The regular bonus and the big bonus described above may be collectively referred to simply as “bonus”.

  It should be noted that in the reels 601L, 601C, and 601R in FIG. 113, only the white 7 symbol is drawn, but the illustration is omitted, and the reels 601L, 601C, and 601R are actually also surrounded by dotted lines. The design is drawn.

  In the slot machine 601 of the present embodiment, there is a possibility that a small role, a re-playing role or a special role (bonus) is won in the internal lottery (a small role, a re-playing role or a special role is won by winning the internal lottery). Suggestive effects suggesting that there is a possibility that the winning flag is set in the RAM 641c) on the stage members (liquid display 651, movable right and left movable parts 675L, 675R, etc. of the liquid crystal display 651). To be executed. In particular, based on the fact that it is determined that the special combination is allowed to be generated by the internal lottery process (a state in which the internal lottery is won and the special combination winning flag is set in the RAM 641c), the CPU 691a displays the liquid crystal display. The suggestion effect is executed so that a specific display result (for example, “7, 7 and 7” are aligned) is obtained as a combination of the left, middle, and right symbols Z1 to Z3 displayed on the display screen of the device 651. .

  Note that the gaming state advantageous to the player is not limited to the above-mentioned big bonus and regular bonus, but for example, a notification target winning that occurs on condition that reel derivation conditions (for example, stop order and stop timing) are satisfied. When a stop switch 606L, 606C, or 606R is operated by limiting a game state (so-called assist time (AT)) in which an operation procedure that satisfies a derivation condition is notified or at least one of the reels is retracted. Control the displayed symbols to be easy to stop, and the challenge time (CT) that allows the player to derive a combination of winning symbols by pushing forward, specific winnings (for example, replay winnings and singles) Gaming state (so-called replay time (RT) Middle state), and further, a game state (for example, ART that combines assist time and replay time) may be mounted, and the suggestion producing means establishes a transition condition for shifting to these game states. The suggestion effect may be performed so that a specific display result is obtained based on what is being performed.

  Further, the type of specific display result may be different depending on the type of gaming state where the transition condition is satisfied. For example, “7 ・ 7 ・ 7” or “3 ・ 3 ・ 3” is based on the big bonus won as a special role in the internal lottery, and the regular bonus is won as a special role in the internal lottery. “3 · 3 · 3” is aligned, and “1 · 1 · 1” is aligned based on the fact that the transition condition for shifting to the replay time (RT) is satisfied.

  In the example of the slot machine shown in FIGS. 113 and 114, the control microcomputer is realized by the main control unit 641 mounted on the game control board 640. The payout means is realized by a hopper driven by a hopper motor 634. Further, the game control medium payout control means is realized by executing processing for controlling the hopper motor 634 by the main control unit 641. The cumulative update means is realized by the main control unit 641 executing a process of cumulatively adding a payout excess or payout deficiency to a counter. Also, the payout stopping means is realized by being controlled by the main control unit 641 so as not to operate the hopper motor 634. As shown in the example of the gaming machine shown in FIGS. 113 and 114, in a slot machine or the like, a game control process for controlling the progress of the game is executed by the main control unit 641 mounted on the game control board 640. At the same time, the hopper motor 634 is controlled to perform payout control. Therefore, in the example of the gaming machine shown in FIGS. 113 and 114, the game control microcomputer is realized by the main control unit 641, and the payout control microcomputer is also realized by the main control unit 641.

  In the case of the slot machine shown in FIGS. 113 and 114, the ROM 641b included in the main control unit 641, the chip individual number register provided separately from the ROM 641b, or the like for each product of the slot machine or the control micro For each product (each chip) of the computer, it is only necessary to store game machine specific information given individually in advance. When a predetermined information output condition is satisfied, the gaming machine specific information is output to the external device.

  Information output conditions for externally outputting the gaming machine specific information include, for example, a setting in which the setting value is confirmed when the power is turned on when the power supply to the slot machine is started, when the setting value is changed. At the time of confirmation, when the start switch 607 is detected, at the start operation, at the time of bonus for transitioning to a regular bonus or big bonus, assist time (AT), replay time (RT), concentration state, etc. advantageous game state for the player There are one or more conditions including a part or all of a predetermined one or a plurality of types of gaming states at the start of the game, an error when a predetermined error is detected, etc. , It may be determined in advance.

  When an error that can be an information output condition occurs, for example, an abnormality in the game medal auxiliary warehouse, an abnormality in no payout game medal, an abnormal clogging in the medal payout device, an abnormal payout in the medal payout device, an abnormality in the medal selector, Detection of occurrence of abnormalities including part or all of abnormal rotation speeds, abnormal stoppages corresponding to small roles, replays or special roles without winning in internal lottery, abnormal RWM contents, etc. When it is done. The abnormality of the game medal auxiliary storage occurs when the game medal auxiliary storage (overflow tank) enters a state where it is about to exceed the medal storage limit. The absence of payout game medals occurs when, for example, the hopper motor 634 is idle for more than 2.8 seconds due to a lack of payout medals, or when no medals are sent out due to a failure of the hopper motor 634. The game medal clogging abnormality in the medal payout device occurs when the medal is not sent out because the medal payout outlet 609 is jammed, and the medal to be paid out remains at the position of the payout sensor 635 for 101 milliseconds or more. The payout abnormality of the medal payout device is detected when a detection signal of 11 milliseconds or more is output from only one of the two sensors included in the payout sensor 635 during the payout of the medal, or when the medal payout time is not two. Occurs when a detection signal is output from only one of the sensors. Abnormality in the medal selector is detected by a sensor provided in the medal selector that detects the medal inserted from the medal insertion unit 604 and selects the medal type or authenticity, or from 10 milliseconds. Occurs when passage or backflow is detected outside the 100 millisecond range. An abnormality in the rotational speed of the rotation occurs when the reels 602L, 602C, and 602R do not rotate at a normal speed and the retry is performed four times and still does not rotate normally. The abnormality of the RWM content occurs when the number of insertions or the set value is not correct at the time of internal lottery, or when the storage content of the RAM 641c serving as the RWM that has been backed up at the time of power-on is abnormal.

  Further, for example, a voltage from a backup power source (for example, a battery or a capacitor) included in a predetermined backup power supply circuit is applied to the door switch 625, and even when power supply to the slot machine 601 is stopped. It is only necessary to detect a state where the front door is opened and to output a door opening signal. Thereby, when it is detected that the front door is opened by the door switch 625, after the power supply to the slot machine 601 is started, the game machine specific information is output to the external device together with the door opening signal, When power supply to the slot machine 601 is stopped, it is only necessary to output only the door opening signal to the external device.

  In addition, when the gaming machine specific information is output from the slot machine 601 to the external device based on the establishment of one of the information output conditions, a new output of the gaming machine specific information is performed even if another information output condition is satisfied. May be regulated to maintain the current output state. A state signal that can specify a predetermined state in the slot machine 601 may be externally output in accordance with the output of gaming machine specific information based on the establishment of any one of the information output conditions among a plurality of different information output conditions. .

  In addition, by outputting the gaming machine specific information from the slot machine 601 to a plurality of external devices, the validity of the gaming machine specific information may be determined in each external device. The gaming machine specific information only needs to be output from the slot machine 601 to an external device by a serial signal system.

  Also, in the case of the slot machine shown in FIGS. 113 and 114, when various errors are detected, a security signal may be externally output via a terminal board or the like. In this case, for example, when a RAM initialization process or setting change is performed at the time of starting the slot machine, a security signal is output to the outside, and when a hopper error is detected (the number of payouts from the hopper tank is A security signal may also be output externally even when an abnormality in the number of medals paid out is detected based on a predetermined abnormality determination value (for example, 2000) or more. Also, for example, in addition to or instead of these cases, for example, when there is no medals in the hopper tank and the payout cannot be performed (medals run out), or when medals are clogged, the inserted medals are distributed. Even when various errors are detected such as when an error of a selector to be detected is detected, the security signal may be output to the outside. In these cases, the game machine specific information may also be output from a common connector that outputs the security signal to the outside.

  Also, in the case of the slot machines shown in FIGS. 113 and 114, data indicating a specific gaming state is stored in addition to the predetermined initialization process not being executed when power supply is started. Based on the above, the on-state signal may be output externally until a predetermined output stop condition is satisfied. In this case, the data indicating the special gaming state is stored in a backup area in the RAM 641c of the main control unit 641, for example, and an advantageous gaming state such as an assist time (AT), a replay time (RT), or a concentrated state. It is sufficient if the data indicates whether or not. For example, when the first special combination occurs after the power is turned on, or when the operation of the start switch 607 is detected for the first time after the power is turned on, the first assist time after the power is turned on. (AT), replay time (RT), or special gaming state such as concentration state, when the number of variable displays executed after power-on reaches a predetermined number of times, the elapsed time from power-on is predetermined Established at any predetermined timing, such as when the time reaches, the number of medals paid out after power-on reaches a predetermined number, or when the clear switch operation is detected after power-on do it.

  In the configuration of the game information processing system shown in FIG. 73, the pachinko gaming machine 1 may be replaced with the slot machine shown in FIGS. 113 and 114. Even in this case, for example, the game management device configured by using the terminal device 770, the hall computer 771, and the like performs predetermined processing based on the security signal and the on-time state signal received from the slot machine. The gaming state when the power supply to the slot machine is started can be easily grasped.

  In addition to these, various device operations including the device configuration of the gaming machine such as the pachinko gaming machine 1 and the slot machine, the data configuration, the processing shown in the flowchart, the display operation of the effect image in the display area of the effect display device 9, Changes and modifications can be arbitrarily made without departing from the spirit of the present invention. Furthermore, the program and data for realizing the present invention are attached to and detached from a gaming machine such as a pachinko gaming machine 1 or a slot machine, or a computer device included in a gaming management device such as a stand terminal device 770 or a hall computer 771. The present invention is not limited to a form distributed and provided by a free recording medium, but may be a form distributed by preinstalling in a storage device such as a computer device in advance. Furthermore, the program and data for realizing the present invention are distributed by downloading from other devices on a network connected via a communication line or the like by providing a communication processing unit. It doesn't matter.

  And the execution form of various processes is not only executed by attaching a removable recording medium, but can also be executed by temporarily storing the downloaded program and data via a communication line etc. in an internal memory etc. Or a form directly executed using hardware resources on the other device side on a network connected via a communication line or the like. Further, various processes can be executed by exchanging data with other computer devices or the like via a network.

DESCRIPTION OF SYMBOLS 1 ... Pachinko machine 9 ... Production display device 14 ... Start winning opening 14a ... Start opening switch 14b ... Winning confirmation switch 15 ... Variable winning ball apparatus 31 ... Game control board (main board)
37 ... Dispensing control board 50 ... Card unit 54 ... ROM
56 ... CPU
80 ... Production control board 100 ... Production control microcomputer 101a ... Production control CPU
101b ... Serial communication circuit (production control side)
155a, 155b ... Door opening switch 160 ... Terminal board 370 ... Discharge control microcomputer 371 ... Discharge control CPU
380 ... Serial communication circuit (dispensing control side)
505 ... Serial communication circuit (game control side)
506 ... Chip individual number register 507 ... Backup power supply 508 ... Backup power supply circuit 560 ... Microcomputer 771 for game control ... Hall computer

Claims (1)

A gaming machine capable of performing a predetermined game,
Fluctuation data storage means for storing fluctuation data generated when performing control;
Storage content holding means capable of holding the storage content of the variation data storage means for a predetermined period even when power supply to the gaming machine is stopped;
Initialization operation means for outputting an operation signal in response to an operation;
Initialization processing execution means for executing initialization processing for initializing the storage contents of the variation data storage means when power supply is started and the operation signal is input from the initialization operation means;
Error determination means for determining whether or not a predetermined error has occurred;
To connect a signal line for outputting a signal to the outside of the gaming machine, located on the side where the control board is provided with respect to the surface of the cover member for covering and protecting the control board provided in the gaming machine A terminal board provided with a plurality of terminals;
A terminal board cover that is detachably attached to the cover member and covers and protects the terminal board on which the terminal board is provided;
A predetermined signal output condition is satisfied, including at least that the initialization process has been executed by the initialization process execution means and that the error determination means has determined that the predetermined error has occurred. An external output means for outputting a predetermined external output signal to the outside of the gaming machine via the terminal,
The external output means includes
The predetermined external output signal is output from a common terminal when the initialization process is executed by the initialization process execution unit and when the predetermined error is determined by the error determination unit. Output,
If the predetermined signal output condition is newly satisfied when the predetermined external output signal is being output, the output time for outputting the predetermined external output signal is extended,
The common terminal includes a reference potential input unit and an external output signal input unit, and the two terminals are configured as one set, and a knob for opening the signal line is provided for each terminal. And
The knobs are arranged to alternate with each other,
The application terminals board cover has an opening for operating the knob,
In the state where the terminal board cover is attached to the cover member, the terminal board cover covers the terminal board, and the knob is located at the opening.
A gaming machine characterized by that.