JP2007244438A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a game machine capable of executing securer put-out control while achieving quick put-out of game media to hardly receive fraudulence. <P>SOLUTION: A put-out controlling CPU loads upper-graded bytes of a prize ball total expected put-out number counter PA in a register (a step S690A). If any upper 6 bits are not zero (a step S690B), the upper 6 bits are cleared to zero, and stored in the prize ball total expected put-out number counter PA (a step S690C). If the value in a put-out operation counter is not zero, it is confirmed whether the content of the prize ball total expected put-out number counter PA is equivalent to the content of a previous prize ball total expected put-out number counter PB (a step S694). If the contents are not equivalent to each other, the value equivalent to the difference between the content of the prize ball total expected put-out number counter PA and the content of the a previous prize ball total expected put-out number counter PB is added to the put-out operation counter to update the put-out operation counter (a step S695). <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a gaming machine such as a pachinko gaming machine in which a player can play a game using game media and a predetermined number of game media are paid out as prizes according to the game.

  As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a prize area such as a prize opening provided in the game area, a predetermined number of prize balls are paid out to the player. There is something to be done. The game media is paid out by a payout device. The payout device is generally controlled by a payout control means including a payout control microcomputer mounted on the payout control board. Since the progress of the game is controlled by game control means including a game control microcomputer mounted on the main board, information that can specify the number of winning balls based on the winning of the game medium in the winning area is obtained from the game control means. It is transmitted to the payout control means.

  The number of winning balls corresponding to the winning is determined, for example, as 10 or 15 according to each of the plurality of winning areas provided. There are some gaming machines that pay out a ball for each win when a win occurs, but in order to shorten the total payout time, if consecutive wins occur, a winning ball based on multiple wins is awarded. There are also gaming machines that pay out in a lump without dividing. For example, when winnings corresponding to 10 winning balls are generated three times in succession, 30 winning balls are continuously paid out in a lump.

  Further, when the payout control means is performing the prize ball payout control, if the information regarding the new prize ball payout is received from the game control means, the payout control means newly sets the number of unpaid prize balls at that time. There is a gaming machine that controls such that the number of prize balls is added and paid out in a lump including award balls based on newly generated winnings (see, for example, Patent Document 1).

JP-A-2005-270310

  In the case where control is made so as to pay out in a lump including prize balls based on newly generated winnings, it is necessary to have a storage means for storing the expected number of prize balls to be continuously paid out. When paying out in a lump, a large number of prize ball payouts are executed from the start to the end of payout. Then, when a change that increases the planned number of prize balls stored in the storage means due to electrical noise or the like, an unexpectedly large number of prize balls may be paid out. Further, when the number of prize balls scheduled to be stored in the storage means is increased by an illegal act, a large number of prize balls are paid out illegally.

  Therefore, an object of the present invention is to provide a gaming machine that can perform more reliable payout control while realizing quick payout of game media and is less susceptible to fraud.

  In the gaming machine according to the present invention, a player can play a game using a game medium (for example, a game ball), and the game ball has won a predetermined payout condition (for example, a winning area such as a prize opening). ) Is a gaming machine that pays out a predetermined number of game media as prizes, and controls the progress of the game (for example, executes the processing of steps S21 to S30 (excluding step S29)) A game control microcomputer (for example, a game control microcomputer 560) that transmits a payout control command (for example, a prize ball number signal) for instructing the number of game media to be paid out based on the establishment of a predetermined payout condition; , A payout means (for example, a ball payout device 97) for paying out the game medium, and a payout drive means (for example, a payout motor 28) for driving the payout means to pay out the game medium. ) And a payout control microcomputer (for example, a payout control microcomputer 370) that controls the payout driving means in accordance with the payout control command received from the game control microcomputer. Drive amount data storage means (for example, a payout operation counter) that stores data that can specify the drive amount until the end of payout of game media by the drive means, and drive when the payout drive means drives the payout means Drive amount update means for subtracting the data stored in the amount data storage means by an amount corresponding to the drive amount of the payout drive means (for example, the part that executes the process of step S644 in the payout control microcomputer 370), payout Storage means for storing data indicating the number of payouts of game media according to a control command, A prize game medium number data storage means (for example, a prize ball payout total number counter) having a fixed number of bits, and a payout control instruction when receiving a payout control instruction, a prize game medium number data The prize game medium number data addition means (for example, the portion that executes the processing of step S696 in the payout control microcomputer 370) and the payout drive means drive the payout means to be added to the data stored in the storage means. Sometimes, the drive amount for executing the addition processing for adding the data indicating the drive amount corresponding to the increased number of data stored in the prize game medium number data storage means to the data stored in the drive amount data storage means Data adding means (for example, steps S690A to S690C, S693, S694, S695 in the payout control microcomputer 370) And the previous prize game medium number data storage means for storing the data stored in the prize game medium number data storage means when the drive amount data addition means adds the data (for example, the previous prize game medium data storage means) And the driving amount data adding means matches the data stored in the prize game medium number data storage means with the data stored in the previous prize game medium number data storage means. A determination process executing means for executing a determination process for determining whether or not there is a prize (for example, the portion of the payout control microcomputer 370 that executes the process of step S694) and the determination process executing means before the determination process is executed. Number of bits corresponding to the number exceeding the predetermined storage upper limit value among the predetermined number of bits (for example, 16 bits) in the game medium number data storage means. It is checked whether or not the effective value (for example, 1) corresponding to having the stored value (for example, the upper 6 bits) indicates the effective value. When the effective value is indicated, the bit has the stored value. And an invalid value changing means (for example, a portion for executing the processing of steps S690A to S690C in the payout control microcomputer 370) that changes to an invalid value (for example, 0) corresponding to the absence, and by the determination processing executing means An addition process is executed when it is determined that the data do not match (for example, the processes of steps S694 and S695 are executed).

  In another aspect of the gaming machine according to the present invention, a player can play a game using a game medium (for example, a game ball), and a game ball is placed in a predetermined payout condition (for example, a winning area such as a prize opening). Is a game machine that pays out a predetermined number of game media as prizes according to the establishment of a prize, and controls the progress of the game (for example, processing of steps S21 to S30 (excluding step S29) )), A game control microcomputer (for example, a game control microcomputer) that transmits a payout control command (for example, a prize ball number signal) that indicates the number of game media to be paid out based on a predetermined payout condition being satisfied. A computer 560), a payout means (for example, a ball payout device 97) for paying out game media, and a payout drive means (for example, payout) for driving the payout means to pay out game media 289) and a payout control microcomputer (for example, payout control microcomputer 370) for controlling the payout driving means in accordance with the payout control command received from the game control microcomputer. Is a drive amount data storage means (for example, a payout operation counter) for storing data that can specify the drive amount until the end of payout of the game medium by the payout drive means, and when the payout drive means drives the payout means In addition, drive amount update means for subtracting the data stored in the drive amount data storage means by an amount corresponding to the drive amount of the payout drive means (for example, the portion of the payout control microcomputer 370 that executes the process of step S644). And storage means for storing data indicating the number of payouts of game media according to the payout control command The prize game medium number data storage means (for example, a prize ball payout total number counter) having a predetermined number of bits and the payout control command when the payout control command is received, A prize game medium number data adding means for adding to the data stored in the medium number data storage means (for example, the portion for executing the processing of step S696 in the payout control microcomputer 370), and the payout driving means drives the payout means. In this case, an addition process is performed in which data indicating the driving amount corresponding to the increase in the number of data stored in the premium game medium number data storage means is added to the data stored in the driving amount data storage means. Drive amount data adding means (for example, steps S690A, S690C, S693, S694 in the payout control microcomputer 370) , S695 for executing the process) and the previous prize game medium number data storage means for storing the data stored in the prize game medium number data storage means when the drive amount data addition means adds the data (for example, And the driving amount data adding means is configured such that the data stored in the prize game medium number data storage means is equal to the data stored in the previous prize game medium number data storage means. A determination process executing means for executing a determination process for determining whether or not it has been performed (for example, the portion of the payout control microcomputer 370 that executes the process of step S694) and the determination process executing means before the determination process is executed. The number of the predetermined number of bits (for example, 16 bits) in the prize game medium number data storage means exceeds the predetermined storage upper limit value. Invalid value changing means (for example, steps S690A and S690C in the payout control microcomputer 370) that changes the bits to be performed (for example, the upper 6 bits) to invalid values (for example, 0) corresponding to having no stored value. And the addition process is performed when the determination process execution unit determines that the data does not match (for example, the process of steps S694 and S695 is executed). And

  The payout control microcomputer is configured to determine whether or not the data stored in the prize game medium number data storage means has increased when the payout driving means drives the payout means (for example, the payout control means) A part for executing the processing of step S694 in the control microcomputer 370) and an increase number specifying means (for example, a payout control microcomputer) for specifying the increase number when the increase determination means determines that the data is increasing. 370 when the process of step S695 is executed) and when the driving amount data adding means executes the adding process, the data stored in the prize game medium number data storage means is stored in the previous prize game medium number data storage means. The previous prize game medium number data setting means to be set (for example, in the payout control microcomputer 370) It may be configured so as to include a portion) that performs the process of step S697.

  The payout control microcomputer initializes the data set in the previous prize game medium number data storage means when the payout of the game media is completed (for example, step S672 in the payout control microcomputer 370). The part which performs the process of (2) may be included.

  The predetermined payout condition is established by winning a game medium in each of a plurality of winning areas (for example, winning openings 29, 30, 33, 39, starting winning opening 14, and large winning opening) provided in the gaming area. , Game medium detecting means for detecting a game medium won in accordance with each of a plurality of winning areas and outputting a winning detection signal to a game control microcomputer (for example, a prize opening switch 29a, 30a, 33a, 39a, a count switch) 23 and the start port switch 14a), and the game control microcomputer is configured to immediately transmit a payout control command (allowing a delay of several ms in control) in response to the input of the winning detection signal. May be.

  The game control microcomputer includes a game control CPU (for example, CPU 56) for executing game control processing and a serial communication circuit (for example, serial communication circuit 505) for serial communication with the payout control microcomputer. The serial communication circuit satisfies predetermined interrupt request conditions (for example, a communication error has occurred in the serial communication circuit 505, transmission of transmission data has been completed, and reception data has been received from the dispensing control board 37). Interrupt request means (for example, interrupt control circuit 714) that generates an interrupt request to the game control CPU when the interrupt request is generated, a communication error occurs in the serial communication circuit. Including an error interrupt request (for example, a communication error interrupt request) that is generated when The microcomputer executes a game control process on the basis of the occurrence of a timer interrupt that occurs periodically (for example, every 2 ms), and timer interrupt setting means that performs settings for generating a timer interrupt ( For example, when the power supply to the gaming machine is started, the timer interrupt setting means sets the timer interrupt before the timer interrupt is set. Serial communication circuit initial setting means for performing initial setting of the serial communication circuit (for example, a part for executing the processing of step S15a in the game control microcomputer 560), and for interrupt control based on an error time interrupt request Communication prohibition means for prohibiting communication with a microcomputer (for example, a game control microcomputer 560) , When the communication error flag is set in steps S1241, S1251, S1261, S1271, and S1291 based on the fact that the communication error flag is set in step S41, the processing is terminated. It may be configured.

  The game control microcomputer includes a game control CPU (for example, CPU 56) that executes game control processing and a random number circuit (for example, random number circuit 503) that generates random numbers. Numerical value updating means (for example, a counter 521) for updating numerical data in a predetermined order from a predetermined initial value to a predetermined final value within a predetermined range in which numerical data can be updated based on an input, and numerical value updating Including a random number storage means (for example, a random value storage circuit 531) for storing numerical data updated by the means as a random value, and the game control microcomputer includes a timer allocation periodically (for example, every 2 ms). Timer interrupt setting means for executing a game control process based on the occurrence of an interrupt and setting for generating a timer interrupt (example: For example, when the power supply to the gaming machine is started, the timer interruption setting unit sets the timer interruption when the power supply to the gaming machine is started. Random number circuit initial setting means (for example, a part for executing the processing of step S15 in the game control microcomputer 560) that performs initial setting of the random number circuit. The predetermined initial value of the numerical data to be updated is based on microcomputer identification information (for example, an ID number unique to the game control microcomputer 560) for identifying the game control microcomputer assigned to each game control microcomputer. Configured (for example, execute the process of step S154b). It may be.

  A variable display means (for example, a special symbol display 8 or a variable display device 9) capable of variably displaying a plurality of types of identification information that can identify each of them is provided, and predetermined variable display execution conditions (for example, a start prize) After the winning of the game ball to the mouth 14 is established, the variable display of the identification information is started based on the establishment of the variable display start condition (for example, the final stop of the special symbol and the end of the jackpot game), A gaming machine that shifts to a specific gaming state (for example, jackpot gaming state) advantageous to a player when a display result of variable display becomes a specific display result (for example, jackpot symbol), and a game control microcomputer Is a random number reading means (for example, the game control microcomputer 560 for reading random number values (for example, random R) stored in the random number storage means). 204) and a display result determining means (for example, a game) for determining whether or not the display result of the variable display of the identification information is set as the specific display result when the variable display start condition is satisfied. The control microcomputer 560 includes steps for executing the processes of steps S62, S63, S82, and S83, and the display result determining means uses the random number read by the random number reading means as a predetermined judgment value (for example, a big hit It may be configured to determine whether or not the display result of the variable display of the identification information is set as a specific display result by determining whether or not it matches with the (determination value).

  A variable display means (for example, a special symbol display 8 or a variable display device 9) capable of variably displaying a plurality of types of identification information that can identify each of them is provided, and a predetermined variable display execution condition (for example, a start prize) After the winning of the game ball to the mouth 14 is established, the variable display of the identification information is started based on the establishment of the variable display start condition (for example, the final stop of the special symbol and the end of the jackpot game). A gaming machine that shifts to a specific gaming state (for example, a jackpot gaming state) that is advantageous to the player when the display result of the variable display becomes a specific display result (for example, a jackpot symbol). A first electric component control microcomputer (for example, sound) that controls one electric component (for example, at least one of the variable display device 9, the speaker 27, and the lamp). The first electric component control board (for example, the sound / lamp control board 80b or the symbol control board 80a) on which the lamp control microcomputer 100b or the symbol control microcomputer 100a) is mounted, and the second electric component used for the game effect. A second electric component control microcomputer (for example, a symbol control microcomputer 100a or a sound / lamp control microcomputer 100b) that controls (for example, at least one of the variable display device 9, the speaker 27, and a lamp). ) Mounted on the second electrical component control board (for example, the symbol control board 80a or the sound / lamp control board 80b), and the game control microcomputer detects the identification information when the variable display start condition is satisfied. Whether the display result of variable display of a specific display result Display result determining means (for example, a portion of the game control microcomputer 560 for executing the processes of steps S62, S63, S82, and S83) and variable display of identification information based on the determination result of the display result determining means The game control-side command transmission means (for example, the process of step S104 in the game control microcomputer 560) transmits the variation pattern command that can identify the selected variation pattern to the first electrical component control microcomputer. The first electric component control microcomputer includes an effect content determination means (for example, sound / lamp control) for determining the content of the game effect based on the variation pattern command received from the game control microcomputer. For microcomputer 100b A portion for executing the processing of steps S1853 to S1855) and a command (for example, an effect content command) that can specify the content of the game effect determined by the effect content determination means, is transmitted to the second electric component control microcomputer. Electric component control side command transmission means (for example, a part of the sound / lamp control microcomputer 100b that executes the processing of steps S1856 and S1857), and the second electric component control microcomputer receives the first electric component control side command. Based on the content of the game effect indicated by the command transmitted by the transmitting means, the game effect using the second electrical component is controlled (for example, the symbol controlling microcomputer 100a performs the operation of step S775 based on the effect content command). Execute the production control process) It may have been made.

  The first electrical component control microcomputer is configured to generate command content command (for example, a sound / lamp control microcomputer) that can specify the content of the game effect determined by the effect content determination means based on the variation pattern command. 100b includes a portion that executes a process of generating an effect content command in the process of step S1856, and the first electric component control side command transmitting means transmits the effect content command generated by the command generating means (for example, sound / The lamp control microcomputer 100b transmits an effect content command in the process of step S1856), and the second electric component control microcomputer transmits the game effect indicated by the effect content command transmitted by the first electric component control side command transmission means. Using the second electrical component based on the contents of Controlling the game effects (e.g., executes the process of step S775 based on the symbol control microcomputer 100a Produce contents command) may be configured so.

  The first electric component control microcomputer adds the contents of the game effect determined by the effect content determination means to the variation pattern command (for example, the sound / lamp control microcomputer 100b adds the content of the effect to the variation pattern command. The first electric component control side command transmitting means includes a variation pattern command to which the content of the game effect is added by the effect content adding means. (For example, the sound / lamp control microcomputer 100b executes the same processing as in step S1856), and the second electrical component control microcomputer transmits the variation pattern command transmitted by the first electrical component control side command transmission means. Based on the contents of the game production shown in Controlling the game effects that had (for example, executes the processing of step S775 based on the symbol control microcomputer 100a Produce contents command) may be configured so.

  In the first aspect of the invention, the driving amount data adding means determines whether the data stored in the prize game medium number data storage means matches the data stored in the previous prize game medium number data storage means. The determination processing is executed, and before the determination processing is executed, the bit corresponding to the number exceeding the predetermined storage upper limit value among the predetermined number of bits in the prize game medium number data storage means has the stored value If the valid value is indicated, the bit is changed to an invalid value corresponding to the fact that the stored value is not included, and the data does not match in the determination process. Therefore, it is possible to prevent the number of prize balls from being paid out exceeding the storage upper limit value in the prize game medium number data storage means. Therefore, even if control is performed so as to pay out in a lump including prize balls based on newly generated winnings, it is possible to perform more reliable payout control and make it difficult to receive fraud.

  In the invention described in claim 2, the driving amount data adding means determines whether the data stored in the prize game medium number data storage means matches the data stored in the previous prize game medium number data storage means. Before the determination process is executed, the bit corresponding to the number exceeding the predetermined storage upper limit value among the predetermined number of bits in the prize game medium number data storage means has a stored value. Since it is configured to execute an addition process when it is determined that the data does not match in the determination process, the number exceeding the storage upper limit value in the prize game medium data storage means Can be prevented from being paid out. Therefore, even if control is performed so as to pay out in a lump including prize balls based on newly generated winnings, it is possible to perform more reliable payout control and make it difficult to receive fraud.

  In the invention according to claim 3, the payout control microcomputer determines whether or not the data stored in the prize game medium number data storage means has increased when the payout driving means drives the payout means. An increase determination means, an increase number specifying means for specifying an increase number when the increase determination means determines that the data is increasing, and a prize game medium when the drive amount data addition means executes the addition process Since the previous prize game medium number data setting means for setting the data stored in the number data storage means in the previous prize game medium number data storage means is included, it is accurate based on the stored contents of the previous prize game medium number data setting means. You can pay out premium game media.

  In the invention according to claim 4, since the payout control microcomputer includes initialization means for initializing the data set in the previous prize game medium number data storage means when the payout of the game medium is completed. There is no mistake in specifying the number of increases in determining whether the next data increase.

  In the invention described in claim 5, there is provided game medium detection means for detecting a game medium won according to each of a plurality of winning areas and outputting a winning detection signal to the game control means, and the game control microcomputer comprises: Since the payout control command is immediately transmitted in response to the input of the winning detection signal, the payout control command can be quickly transmitted to the payout control microcomputer.

  In the invention according to claim 6, when the game control microcomputer starts the supply of power to the gaming machine, before the timer interrupt setting means sets the timer interrupt, the serial communication circuit is initialized. Since serial communication circuit initial setting means for setting and communication prohibition means for prohibiting communication with the payout control microcomputer in the interrupt processing based on the error time interrupt request, an error related to communication has occurred. Communication will not continue in a state where

  According to the seventh aspect of the present invention, the random number circuit initial setting means includes a game control microcomputer provided with a predetermined initial value of the numerical data updated by the numerical value update means for each game control microcomputer in the initial setting. Since it sets based on the microcomputer identification information for identification, the randomness of a random value can be improved.

  In the invention according to claim 8, the display result determining means determines whether or not the random value read by the random number reading means matches the predetermined determination value, thereby displaying the display result of the variable display of the identification information. Since it determines whether it is set as a specific display result, the randomness that the display result of variable display is determined to be a specific display result can be improved.

  In the ninth aspect of the invention, the first electrical component control microcomputer includes an effect content determination means for determining the content of the game effect based on the variation pattern command received from the game control microcomputer, and an effect content determination means. A first electric component control side command transmission means for transmitting a command capable of specifying the content of the determined game effect to the second electric component control microcomputer, wherein the second electric component control microcomputer performs the first electric component control. Since the game effect using the second electrical component is controlled based on the content of the game effect indicated by the command transmitted by the side command transmission means, the game control microcomputer does not have to determine the effect content. The processing burden on the game control microcomputer can be reduced.

  In a tenth aspect of the present invention, the first electric component control microcomputer includes command generation means for generating an effect content command capable of specifying the content of the game effect determined by the effect content determination means based on the variation pattern command. The first electrical component control side command transmission means transmits the effect content command generated by the command generation means, and the second electrical component control microcomputer transmits the effect content command transmitted by the first electrical component control side command transmission means. Since the game effect using the second electrical component is controlled based on the contents of the game effect shown in FIG. 2, the control burden on the game control microcomputer can be reduced.

  In the eleventh aspect of the invention, the first electric component control microcomputer includes an effect content adding means for adding the content of the game effect determined by the effect content determining means to the variation pattern command, and the first electric component control side command The transmission means transmits the variation pattern command to which the content of the game effect is added by the effect content addition means, and the second electric component control microcomputer transmits the variation pattern command transmitted by the first electric component control side command transmission means. Since the game effect using the second electric component is controlled based on the content of the game effect shown, the control burden of the game control microcomputer can be reduced and the first electric component control microcomputer transmits Can reduce the number of commands to be executed.

Embodiment 1 FIG.
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, the overall configuration of a pachinko gaming machine that is an example of a gaming machine will be described. FIG. 1 is a front view of a pachinko gaming machine as viewed from the front. In the following embodiments, a pachinko gaming machine will be described as an example. However, the gaming machine according to the present invention is not limited to a pachinko gaming machine, and a predetermined number of gaming media are paid out as prizes according to the game. It can also be applied to other gaming machines such as slot machines.

  The pachinko gaming machine 1 includes an outer frame (not shown) formed in a vertically long rectangular shape and a game frame attached to the inside of the outer frame so as to be openable and closable. Further, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape that is provided in the game frame so as to be opened and closed. The game frame includes a front frame (not shown) installed to be openable and closable with respect to the outer frame, a mechanism plate to which mechanism parts and the like are attached, and various parts attached to them (excluding a game board described later). Is a structure including

  As shown in FIG. 1, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2 is a hitting ball supply tray (upper plate) 3. Under the hitting ball supply tray 3, an extra ball receiving tray 4 for storing game balls that cannot be accommodated in the hit ball supply tray 3 and a hitting operation handle (operation knob) 5 for launching the game balls are provided. A game board 6 is detachably attached to the back surface of the glass door frame 2. The game board 6 is a structure including a plate-like body constituting the game board 6 and various components attached to the plate-like body. A game area 7 is formed on the front surface of the game board 6.

  Near the center of the game area 7, there is provided a variable display device (decorative symbol display device) 9 including a plurality of variable display portions each variably displaying an effect decorative symbol. The variable display device 9 has, for example, three variable display portions (symbol display areas) of “left”, “middle”, and “right”. The variable display device 9 performs variable display of a decorative symbol as a symbol for decoration (production) during the variable symbol display period of the special symbol by the special symbol indicator 8. The variable display device 9 that performs variable display of decorative symbols is controlled by an effect control microcomputer mounted on the symbol control board. At the bottom of the variable display device 9, four special symbol hold memory indicators 18 are provided for displaying the number of effective winning balls that have entered the start winning opening 14, that is, the number of hold memories (also referred to as start memory or start prize memory). ing. The special symbol hold memory display 18 displays up to four hold memory numbers in the order of winning. The special symbol hold storage display 18 increases the number of LEDs in the lit state by 1 each time there is a start winning in the start winning opening 14. Then, each time the special symbol display 8 starts variable display, the special symbol hold storage indicator 18 reduces the number of LEDs in the lit state by 1 (that is, turns off one LED). Specifically, the special symbol hold storage display 18 shifts the lighting state every time variable display is started on the special symbol display 8. In this example, the upper limit number (up to 4) is provided for the starting memory number by winning to the start winning opening 14, but the upper limit number may be four or more.

  A special symbol display (special symbol display device) 8 that variably displays a special symbol as identification information is provided on the variable display device 9. In this embodiment, the special symbol display 8 is realized by a simple and small display (for example, 7 segment LED) capable of variably displaying numbers 0 to 9, for example. The special symbol display 8 may be configured to variably display a larger number of numbers such as 0 to 99 in order to make it difficult for the player to grasp a specific stop symbol. In addition, the variable display device 9 performs variable display of a decorative symbol as a symbol for decoration (production) during the variable symbol display period of the special symbol by the special symbol indicator 8.

  Below the variable display device 9, a variable winning ball device 15 is provided as a start winning port 14. The winning ball that has entered the start winning opening 14 is guided to the back of the game board 6 and detected by the start opening switch 14a. A variable winning ball device 15 that opens and closes is provided below the start winning opening 14. The variable winning ball device 15 is opened by a solenoid 16.

  An open / close plate 20 that is opened by a solenoid 21 in a specific gaming state (big hit state) is provided below the variable winning ball device 15. The opening / closing plate 20 is a means for opening and closing a large winning opening (variable winning ball apparatus). The winning ball guided from the opening / closing plate 20 to the back of the game board 6 is detected by the count switch 23.

  When a game ball wins the gate 32 and is detected by the gate switch 32a, the variable display of the normal symbol display 10 is started. In this embodiment, variable display is performed by alternately lighting the left and right lamps (a symbol can be visually recognized when the lamp is lit). For example, if the right lamp is lit when the variable display ends, it is a win. When the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined number of times. In the vicinity of the normal symbol display 10, a normal symbol start memory display 41 having a display unit with four LEDs for displaying the number of winning balls entered into the gate 32 is provided. Each time there is a prize at the gate 32, the normal symbol start memory display 41 increases the number of LEDs to be turned on by one. Then, every time variable display on the normal symbol display 10 is started, the number of LEDs to be lit is reduced by one.

  The game board 6 is provided with a plurality of winning ports (ordinary winning ports) 29, 30, 33, and 39. The winning holes 29, 30, 33, and 39 for the game balls are awarded to the winning port switches 29a and 30a, respectively. , 33a, 39a. Each winning opening 29, 30, 33, 39 constitutes a winning area provided in the game board 6 as an area for accepting game media and allowing winning. The start winning opening 14 and the big winning opening also constitute a winning area that accepts game media and allows winning. Decorative lamps 25 blinking and displayed during the game are provided around the left and right sides of the game area 7, and an outlet 26 for absorbing a game ball that has not won a prize is provided at the bottom. Two speakers 27 that emit sound effects are provided on the left and right upper portions outside the game area 7. On the outer periphery of the game area 7, a top frame lamp 28a, a left frame lamp 28b, and a right frame lamp 28c are provided. Further, a decoration LED is installed around each structure (such as a big prize opening) in the game area 7. The top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, and the decorative LED are examples of a decorative light emitter provided in the gaming machine.

  In this example, a prize ball LED 51 that is lit while paying out a prize ball is provided in the vicinity of the left frame lamp 28b, and a ball break LED 52 that is lit when the refill ball is cut is provided in the vicinity of the top frame lamp 28a. It has been. As described above, the pachinko gaming machine 1 of this embodiment is provided with lamps and LEDs as light emitters in various places. Further, a prepaid card unit (hereinafter, also simply referred to as “card unit”) that enables lending a ball by inserting a prepaid card is installed adjacent to the pachinko gaming machine 1 (not shown).

  The card unit includes, for example, a use indicator lamp that indicates whether or not the card unit is in a usable state, a connection table direction indicator that indicates which side of the pachinko gaming machine 1 corresponds to the card unit, When checking the card insertion indicator lamp that indicates that a card has been inserted, the card insertion slot into which a card as a recording medium is inserted, and the card reader / writer mechanism provided on the back of the card insertion slot A card unit lock is provided to release the unit.

  The game balls launched from the hit ball launching device enter the game area 7 through the hit ball rail, and then descend the game area 7. If the game ball enters the start winning opening 14 and is detected by the start opening switch 14a, the decorative display on the variable display device 9 starts variable display (variation) if the variable display of the pattern can be started. If it is not in a state where the variable display of symbols can be started, the start winning memory number is increased by one.

  The variable display of the decorative symbols on the variable display device 9 stops when a certain time has elapsed. If the combination of decorative symbols at the time of stoppage is a jackpot symbol (specific display result), the game shifts to a jackpot gaming state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or a predetermined number (for example, 10) of game balls wins.

  When the combination of decorative symbols on the variable display device 9 at the time of stoppage is a combination of jackpot symbols (probability variation symbols) with a probability variation, the probability of the next jackpot increases. That is, it becomes a more advantageous state for the player in the probability variation state.

  When the game ball wins the gate 32, the normal symbol display unit 10 is in a state where the normal symbol is variably displayed. Further, when the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the probability variation state, the probability that the stop symbol in the normal symbol display 10 becomes a winning symbol is increased, and the opening time and the number of times of opening of the variable winning ball device 15 are increased.

  FIG. 2 is a block diagram illustrating an example of a circuit configuration in the main board 31. 2 also shows the payout control board 37, the symbol control board 80a, the interface board 66, the relay board 77, and the sound / lamp control board 80b mounted on the gaming machine. The main board 31 includes a control circuit 53 including a game control microcomputer 560 for controlling the pachinko gaming machine 1 according to a program and an I / O port unit 57, a gate switch 32a, a start port switch 14a, a count switch 23, and a prize. An input driver circuit 58 for supplying signals from the mouth switches 29a, 30a, 33a, 39a to the game control microcomputer 560, a solenoid 16 for opening / closing the variable winning ball apparatus 15, and a solenoid 21 for opening / closing the special variable winning ball apparatus 20 And a solenoid circuit 59 for driving the computer in accordance with a command from the game control microcomputer 560.

  Note that the switches such as the gate switch 32a, the start port switch 14a, the count switch 23, and the winning port switches 29a, 30a, 33a, and 39a may be referred to as sensors. That is, the name of the game medium detection means (game ball detection means in this example) that can detect a game ball is not limited. Each of the start port switch 14a, the count switch 23, and the winning port switches 29a, 30a, 33a, and 39a that perform winning detection is also a winning detection means that detects the winning of a game ball in the winning area. Note that even if a passing gate such as the gate 32 is used, if a prize ball is paid out, a game ball entering the passing gate becomes a winning and a switch provided on the passing gate (for example, The gate switch 32a) becomes a winning detection means. In this embodiment, a continuation right (right to proceed to the next round) is always generated in rounds other than the final round. However, a V winning area is provided in the big winning opening, and a game ball is won in the V winning area. You may make it generate the continuation right on condition.

  The game control microcomputer 560 is in accordance with a ROM 54 for storing a game control (game progress control) program and the like, a RAM 55 as a storage means (variation data storage means for storing fluctuation data) used as a work memory, and a program. A CPU 56 that performs a control operation is included. The CPU 56 means a central processing unit (a part excluding storage means such as the ROM 54 and the RAM 55) that operates according to a program in the game control microcomputer 560. In addition to the CPU 56, the game control microcomputer 560 means a part including storage means such as the ROM 54 and RAM 55, a random number circuit 503, a serial communication circuit 505, and the like. In this embodiment, the ROM 54 and the RAM 55 are built in the game control microcomputer 560. That is, the game control microcomputer 560 is a one-chip microcomputer. The one-chip microcomputer only needs to include at least the RAM 55, and the ROM 54 may be external or internal. Further, the I / O port unit 56 may be built in the game control microcomputer 560.

  In the game control microcomputer 560, the CPU 56 executes control in accordance with the program stored in the ROM 54. Therefore, the game control microcomputer 560 executes (or performs processing) or the CPU 56 executes. Specifically, the CPU 56 executes control according to a program. The same applies to microcomputers mounted on substrates other than the main substrate 31. The game control means is realized by a game control microcomputer 560.

  The RAM 55 is a backup RAM as a non-volatile storage means that is partially or entirely backed up by a backup power source created on the power supply substrate 910. That is, even if the power supply to the gaming machine is stopped, a part or all of the contents of the RAM 55 is stored for a predetermined period (until the capacitor as the backup power supply is discharged and the backup power supply cannot be supplied). In particular, at least data (a special symbol process flag or the like) corresponding to the game state, that is, the control state of the game control means, and data indicating the number of unpaid prize balls are stored in the backup RAM. The data corresponding to the control state of the game control means is data necessary for restoring the control state before the occurrence of a power failure or the like based on the data when the power is restored after a power failure or the like occurs. In addition, data corresponding to the control state and data indicating the number of unpaid winning balls are defined as data indicating the progress state of the game. In this embodiment, it is assumed that the entire RAM 55 is backed up.

  A reset signal from the power supply board 910 is input to the reset terminal of the game control microcomputer 560. The reset signal from the power supply board 910 is also input to the reset terminal of the payout control microcomputer. That is, the power supply board 910 is equipped with a reset circuit that generates a reset signal supplied to the game control microcomputer 560, the payout control microcomputer, or the like. When the reset signal goes high, the game control microcomputer 560, the payout control microcomputer, etc. become operable, and when the reset signal goes low, the game control microcomputer 560, the payout control microcomputer, etc. The operation stops. Therefore, during the period when the reset signal is at a high level, an allowable signal that allows the operation of the game control microcomputer 560, the payout control microcomputer, etc. is output, and the period during which the reset signal is at a low level. Thus, an operation stop signal for stopping the operation of the game control microcomputer 560, the payout control microcomputer, or the like is output. The reset circuit may be mounted on each electrical component control board (a board on which a microcomputer for controlling electrical parts is mounted), or may be mounted on one or a plurality of electrical component control boards. A reset circuit may be mounted and a reset signal may be supplied from the reset circuit to another electrical component control board.

  Furthermore, a power-off signal indicating that the power supply voltage from the power supply board 910 has dropped below a predetermined value is input to the input port of the game control microcomputer 560. That is, the power supply board 910 monitors the voltage value of a predetermined voltage (for example, DC 30 V or DC 5 V) used in the gaming machine, and when the voltage value decreases to a predetermined value (decrease in the power supply voltage). Is detected), a power supply monitoring circuit for outputting a power-off signal indicating that is mounted. In addition, a clear signal indicating that the clear switch for instructing to clear the contents of the RAM is operated is input to the input port of the game control microcomputer 560.

  In this embodiment, the sound / lamp control means (configured by a sound / lamp control microcomputer) mounted on the sound / lamp control board 80 b is connected to the game control microcomputer 560 via the relay board 77. An effect control command is received, and sound output control of the speaker (sound output device) 27, display control of each of the lamps 25, 28a, 28b, 28c, and the like are performed. The sound / lamp control means transfers the received effect control command to the symbol control means (configured by a symbol control microcomputer) mounted on the symbol control board 80a. Further, a command (production content command) is generated based on the received production control command, and the generated command is transmitted to the symbol control means. The symbol control means receives a command from the sound / lamp control means and performs display control of the variable display device 9 for variably displaying the decorative symbol. As described above, in this embodiment, sound output control of the speaker 27, display control of the lamps 25, 28a, 28b, and 28c, and display control of the variable display device 9 are performed, whereby various game effects are executed. Is done.

  In this embodiment, the payout control means (configured by the payout control microcomputer 370) mounted on the payout control board 37 receives a prize ball command from the game control microcomputer 560, and By outputting a drive signal to the ball payout device 97 and causing the ball payout device 97 to rotate the payout motor, the payout processing of the winning ball is executed.

  FIG. 3 is a block diagram showing a circuit configuration example of the relay board, the sound / lamp control board, and the symbol control board. As shown in FIG. 3, the sound / lamp control board 80b is mounted with a sound / lamp control microcomputer 100b including a sound / lamp control CPU 101b and a RAM. The RAM may be externally attached. In the sound / lamp control board 80b, the sound / lamp control microcomputer 100b operates according to a program stored in a built-in or external ROM (not shown), and is input via the relay board 77. In response to the strobe signal (effect control INT signal) from the input driver 102, the effect control command is received via the input driver 102 and the input port 103.

  The effect control command and the effect control INT signal are first input to the input driver 102 on the sound / lamp control board 80b. The input driver 102 passes the signal input from the relay board 77 only in the direction toward the sound / lamp control board 80b (passes the signal in the direction from the sound / lamp control board 80b to the relay board 77). It is also a unidirectional circuit as signal direction regulating means.

  A signal that allows the signal input from the main board 31 to pass through the relay board 77 only in the direction toward the sound / lamp control board 80b (does not pass the signal in the direction from the sound / lamp control board 80b to the relay board 77). A unidirectional circuit is mounted as a direction regulating means. For example, a diode or a transistor is used as the unidirectional circuit. FIG. 3 illustrates a diode. A unidirectional circuit is provided for each signal.

  The sound / lamp control microcomputer 100 b outputs a signal for driving the lamp to the lamp driver 352. The lamp driver 352 amplifies a signal for driving the lamp and supplies the amplified signal to each lamp provided on the frame side such as the top frame lamp 28a, the left frame lamp 28b, and the right frame lamp 28c. Further, it is supplied to a decorative lamp 25 provided on the frame side.

  The sound / lamp control microcomputer 100b outputs the sound number data to the speech synthesis IC 173. The voice synthesizing IC 173 generates a voice or a sound effect corresponding to the sound number data and outputs it to the amplifier circuit 175. The amplifier circuit 175 outputs an audio signal obtained by amplifying the output level of the speech synthesis IC 173 to a level corresponding to the volume set by the volume 176 to the speaker 27. The voice data ROM 174 stores control data corresponding to the sound number data. The control data corresponding to the sound number data is a collection of data indicating the sound effect or sound output mode in a time series in a predetermined period (for example, a decorative symbol variation period).

  The sound / lamp control microcomputer 100b transfers the received effect control command to the symbol control board 80a via the input / output port 104, generates a command based on the received effect control command, and inputs the generated command. The data is transmitted to the symbol control board 80a via the output port 104.

  As shown in FIG. 3, the symbol control board 80a has a symbol control microcomputer 100a including a symbol control CPU 101a and a RAM. The RAM may be externally attached. In the symbol control board 80a, the symbol control microcomputer 100a operates in accordance with a program stored in a built-in or external ROM (not shown), and receives a command from the sound / lamp control board 80b via the input / output port 702. Receive. Then, the symbol control microcomputer 100a causes the VDP (video display processor) 109 to perform display control of the variable display device 9 using the LCD based on the received command.

  That is, the symbol control microcomputer 100a issues an image drawing instruction (development instruction) to the VDP 109 in accordance with the received command. The VDP 109 reads necessary data from a character ROM (not shown) based on an instruction from the symbol control microcomputer 100a, and expands the read data into a VRAM (not shown).

  The VRAM is a buffer memory for expanding image data generated by the VDP 109. Then, the VDP 109 outputs the image data in the VRAM to the variable display device 9. As a result, the image is displayed on the display screen of the variable display device 9.

  FIG. 4 is a block diagram showing components related to payout, such as the payout control board 37 and the ball payout device 97. As shown in FIG. 4, a payout control microcomputer 37 (an example of an electrical component control microcomputer) 370 including a payout control CPU 371 is mounted on the payout control board 37. In this embodiment, the payout control microcomputer 370 is a one-chip microcomputer and incorporates at least a RAM. The payout control CPU 371, the RAM (not shown), the ROM (not shown) storing the payout control program, the I / O port, and the like constitute the payout control means. That is, the payout control means is realized by a payout control CPU 371, a payout control microcomputer 370 having a RAM and a ROM, and an I / O port. The I / O port may be built in the payout control microcomputer 370. At least a part of the RAM in the payout control microcomputer 370 is backed up by a backup power source mounted on the power supply board 910. However, in this embodiment, it is assumed that all RAM areas are backed up. Therefore, even when power is not supplied to the gaming machine, the storage contents of the RAM are preserved for a predetermined period (until the backup power supply cannot be supplied because the capacitor as the backup power supply is discharged).

  Detection signals from the ball break switch 187, the full switch 48, and the payout count switch 301 are input to the I / O port 372 i of the payout control board 37 via the relay board 72. The detection signal from the payout motor position sensor 295 is input to the I / O port 372h of the payout control board 37 via the relay board 72. The payout motor position sensor 295 is a sensor composed of a light emitting element (LED) and a light receiving element for detecting the rotational position of the payout motor 289, and is used for detecting that the game ball is clogged, that is, so-called ball biting. . In the payout control microcomputer 370 mounted on the payout control board 37, the detection signal from the ball break switch 187 indicates a full ball state, or the detection signal from the full tank switch 48 indicates a full tank state. Then, the ball payout process is stopped.

  When there is a winning game ball at the winning opening, a prize ball number signal (payout number data) indicating the number of prize balls to be paid out is output (transmitted) from the serial communication circuit 505 via the output circuit 67. At the start of power supply, an initialization command or a recovery command is output (transmitted) via the I / O port unit 57 and the output circuit 67.

  The award ball number signal is input to the payout control microcomputer 370 via the input circuit 373A. When the payout control microcomputer 370 receives the prize ball number signal via the I / O port 372e, the payout control microcomputer 370 controls to drive the ball payout device 97 to pay out the number of game balls indicated by the prize ball number signal. The award ball number signal corresponds to a payout command signal for designating the payout number. The initialization command and the recovery command are input to the I / O port 372e via the input circuit 373A. The payout control microcomputer 370 performs a predetermined control when an initialization command or a recovery command is input via the I / O port 372e.

  In addition, a power-off signal indicating that the power supply voltage has dropped below a predetermined value is input from the power supply board 910 to the input port 372g. A clear signal indicating that the clear switch has been operated is not input to the payout control microcomputer 370.

  The payout control microcomputer 370 receives, via the output port 372b, a prize ball information signal indicating the number of prize balls to be paid and a ball lending number signal indicating the number of balls lent. Output to 160). A driver circuit is provided outside the output port 372b, but is not shown in FIG.

  Also, the payout control microcomputer 370 outputs an error signal to the error display LED 374 using a 7-segment LED via the output port 372c. A detection signal from an error release switch 375 for releasing the error state is input to the input port 372f of the payout control board 37. The error cancel switch 375 is used to cancel the error state by software reset.

  Further, a drive signal from the payout control microcomputer 370 to the payout motor 289 is transmitted to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the output port 372a and the relay board 72. A driver circuit (motor drive circuit) is installed outside the output port 372a, but is not shown in FIG.

  A card unit control microcomputer is mounted on the card unit 50 installed adjacent to the gaming machine. In addition, the card unit 50 is provided with a usable display lamp, a connecting table direction indicator, a card insertion display lamp, and a card insertion slot. A frequency display LED 60, a ball lending LED 61, a ball lending switch 62, and a return switch 63 provided in the vicinity of the hitting ball supply tray 3 are connected to the interface board (relay board) 66.

  A card lending switch signal indicating that the ball lending switch 62 has been operated and a return switch signal indicating that the return switch 63 has been operated are given to the card unit 50 from the interface board 66 in accordance with the player's operation. . Further, a card balance display signal indicating a prepaid card balance and a ball lending display signal are given from the card unit 50 to the interface board 66. Between the card unit 50 and the payout control board 37, a connection signal (VL signal), a unit operation signal (BRDY signal), a ball lending request signal (BRQ signal), a ball lending completion signal (EXS signal) and a pachinko machine operation signal ( PRDY signal) is transmitted / received via the input port 372j and the output port 372d. An interface board 66 is interposed between the card unit 50 and the payout control board 37. Therefore, a signal such as a connection signal (VL signal) is transmitted and received between the card unit 50 and the payout control board 37 via the interface board 66 as shown in FIG.

  In this embodiment, the case where the card unit 50 is installed adjacent to the gaming machine as a separate body from the gaming machine is taken as an example, but the card unit 50 may be integrated with the gaming machine. Further, the present invention can be applied even when a game ball corresponding to the amount of money is lent out in accordance with coin insertion.

  Next, the configuration of the power supply substrate 910 will be described with reference to the block diagram of FIG. The power supply board 910 is provided with a power switch 914 for executing or shutting off power supply to each electrical component control board and mechanism component in the gaming machine. Note that the power switch 914 may be provided outside the power supply board 910 in the gaming machine. When the power switch 914 is in a closed state (on state), an AC power supply (AC 24 V) is applied to the input side (primary side) of the transformer 911. The transformer 911 is for electrically insulating the AC power supply (AC24V) and the inside of the power supply board 910, and its output voltage is also AC24V. A varistor 918 as an overvoltage protection circuit is installed on the input side of the transformer 911.

  The power supply board 910 is installed independently of the electric component control board (the main board 31, the payout control board 37, the sound / lamp control board 80b, etc.), and generates a voltage used by each board and mechanism component in the gaming machine. In this example, AC24V, VSL (DC + 30V), VLP (DC + 24V), VDD (DC + 12V) and VCC (DC + 5V) are generated. Further, a capacitor 916 serving as a storage holding means for holding the stored contents in the backup power supply (VBB), that is, the backup RAM, is charged from DC + 5V (VCC), that is, a power supply line for driving an IC or the like on each substrate. Further, a backflow preventing diode 917 is inserted between the +5 V line and the backup +5 V (VBB) line. Note that VSL is generated by rectifying and boosting AC 24 V with a rectifying element in the rectifying and smoothing circuit 915. VSL becomes a solenoid driving power source. VLP is a lamp lighting voltage, and is generated by rectifying AC24V with a rectifier in the rectifier circuit 912.

  The DC-DC converter 913 serving as a power supply voltage generation unit has one or a plurality of switching regulators (two regulator ICs 924A and 924B are shown in FIG. 5), and generates VDD and VCC based on VSL. Relatively large capacitors 923A and 923B are connected to the input sides of the regulator ICs (switching regulators) 924A and 924B. Accordingly, when the power supply to the gaming machine from the outside is stopped, the DC voltages such as VSL, VDD, VCC, etc., decrease relatively slowly.

  As shown in FIG. 5, AC24V output from the transformer 911 is supplied to the connector 922B as it is. The VLP is supplied to the connector 922C. VCC, VDD and VSL are supplied to connectors 922A, 922B and 922C.

  The cable connected to the connector 922A is connected to the main board 31. The cable connected to the connector 922B is connected to the payout control board 37. Therefore, VBB is also supplied to the connectors 922A and 922B. For example, a cable connected to the connector 922C is connected to the sound / lamp control board 80b. Each voltage is supplied to the symbol control board 80a via the sound / lamp control board 80b.

  In addition, a clear switch 921 having a push button structure is mounted on the power supply board 910. Since the power supply board 910 is mounted, the power supply system extending from the power supply board 910 to the main board 31 can be integrated into one system, and the clear signal wiring from the clear switch 921 can be easily separated from the power supply system. it can. When the clear switch 921 is pressed, a low level (ON state) clear signal is output and is output to the main board 31 via the connector 922B. If the clear switch 921 is not pressed, a high level (off state) signal is output. The clear switch 921 may have a configuration other than the push button structure. Further, the clear switch 921 may be provided other than the power supply board 910 in the gaming machine.

  Further, the power supply board 910 generates a reset signal for the microcomputer mounted on the electric component control board, amplifies the reset signal from the power supply monitor circuit 920 that outputs a power-off signal, and the power supply monitor circuit 920. And an output driver circuit 925 that amplifies the power-off signal and outputs the amplified signal to the connector 922B. The reset signal for the symbol control microcomputer is transmitted to the symbol control board 80a via the sound / lamp control board 80b. Further, when the reset circuit is mounted on each electric component control board, the voltage value that makes the reset signal high may be made different (for example, the case of the main board 31 is made highest). The timing at which the reset signal for the game control microcomputer 560 goes high is the latest.)

  The power supply monitoring circuit 920 is a circuit that realizes power supply monitoring means for outputting a power-off signal and reset signal generation means for generating a reset signal. As the power supply monitoring circuit 920, a commercially available power failure monitoring reset module IC should be used. Can do.

  When the power supply to the gaming machine is stopped, the power supply monitoring circuit 920 sets the reset signal to a low level on condition that a predetermined period has elapsed since the power-off signal was output (set to a low level). The predetermined period is a time sufficient for the game control microcomputer 560 mounted on the main board 31 and the payout control microcomputer 370 mounted on the payout control board 37 to execute a power-off process described later. is there. That is, the power monitoring circuit 920 outputs a power-off signal as a voltage drop detection signal, and after the game control microcomputer 560 and the payout control microcomputer 370 have completed the power-off process, the operation stop signal ( Reset signal low level). In addition, when power supply to the gaming machine is started and VCC exceeds +4.5 V, for example, the reset signal is set to high level.

  The power-off signal from the power supply monitoring circuit 920, that is, the detection signal from the power supply monitoring means, is input to the payout control microcomputer 370 via the input port 372g on the payout control board 37. That is, the payout control microcomputer 370 can confirm the occurrence of the stop of the power supply to the gaming machine by monitoring the input signal of the input port 372g. The power-off signal from the power supply monitoring circuit 920 is input to the game control microcomputer 560 via the input port mounted on the main board 31. That is, the gaming control microcomputer 560 can confirm the occurrence of the stop of the power supply to the gaming machine by monitoring the input signal of the input port.

  In this embodiment, the power supply monitoring means (power supply monitoring circuit 920) monitors the output of the power supply of a predetermined potential, and the external condition of the gaming machine is used as a detection condition for stopping the supply of power supplied to the gaming machine from the outside. However, the detection condition is not limited to this, and the fact that the power from the outside has been interrupted is used. Other conditions may be used as long as they can be detected. For example, the presence / absence of a full-wave rectified waveform during the conversion of AC voltage (AC24V) to DC voltage may be monitored, and a power-off signal may be output when the waveform cannot be detected for a predetermined period or longer. Alternatively, the AC voltage may be directly monitored, and a power-off signal may be output when the AC voltage waveform cannot be detected for a predetermined period or longer. That is, the monitoring target of the power supply monitoring circuit is not limited to the voltage, and may be a full-wave rectified waveform or a half-wave rectified waveform, as long as it can detect that the supply voltage to the gaming machine has decreased. Further, a signal obtained by digitizing an AC wave may be monitored, and the detection condition may be that the AC wave has been interrupted when the digital signal has become flat. Further, for example, a + 12V power supply voltage or a + 5V power supply voltage may be monitored, and it may be detected that the voltage has dropped to a predetermined value and a power-off signal is output. However, in order to prevent a malfunction of a switch operating at + 12V, it is preferable to monitor a voltage of + 12V or higher.

  In this embodiment, the power monitoring means is mounted on the power supply board 910, but the power monitoring means may be mounted on the payout control board 37. When mounted on the payout control board 37, the power-off signal path from the power supply monitoring means to the game control microcomputer 560 and the payout control microcomputer 370 is shortened, and noise may be applied to the power-off signal. Can be reduced.

  FIG. 6 is a block diagram showing a circuit configuration of the main board 31 and signal lines of an effect control command transmitted from the main board 31 to the sound / lamp control board 80. As shown in FIG. 6, in this embodiment, the game control microcomputer 560 mounted on the main board 31 uses the eight signal lines CD0 to CD7 for transmitting the effect control signal to produce the effect control command. Is transmitted to the sound / lamp control board 80b. Further, between the main board 31 and the sound / lamp control board 80b, an effect control INT signal signal line for transmitting and receiving a strobe signal is also wired. Note that the game control microcomputer 560 transmits an effect control command via the I / O port unit 57 (not shown in FIG. 6).

  As shown in FIG. 6, the main board 31 is connected to wiring from the start port switch 14a and the like (only the start port switch 14a is shown in FIG. 6). The main board 31 is also provided with wiring from the special variable winning ball apparatus 20 which is a large winning opening, and various switches 29a, 30a, 33a, 39a for detecting the winning of game balls to other winning holes. It is connected. Further, the main board 31 is connected to a solenoid 16 that opens and closes the variable winning ball device 15 and wirings to the solenoid 21 that opens and closes the special variable winning ball device 20.

  The game control microcomputer 560 operates in accordance with a clock circuit 501, a reset controller 502 that functions as a system reset means, a random number circuit 503a, 503b, a ROM 54 that stores a game control program, a RAM 55 that is used as a work memory, and a program. CPU 56, CTC 504 that sends an interrupt request signal to CPU 56, and serial communication circuit 505 that performs asynchronous serial communication with payout control board 37 and the like are incorporated.

The clock circuit 501 outputs a reference clock signal CLK having a predetermined period generated by dividing the system clock signal by 2 ⁷ (= 128) to the random number circuits 503a and 503b. When a low level signal is input for a predetermined period, the reset controller 502 outputs a predetermined initialization signal to the CPU 56 and the random number circuits 503a and 503b to reset the game control microcomputer 560.

  Further, in this embodiment, as shown in FIG. 6, the game control microcomputer 560 is equipped with two random number circuits 503a and 503b having different ranges of random number values that can be generated. The random number circuit 503a is a random number circuit (hereinafter also referred to as a 12-bit random number circuit) that generates a 12-bit pseudo-random number. The 12-bit random number circuit 503a has a function of generating a random number having a value in a range that can be generated by 12 bits (that is, a range from 0 to 4095). The random number circuit 503b is a random number circuit (hereinafter also referred to as a 16-bit random number circuit) that generates a 16-bit pseudo-random number. The 16-bit random number circuit 503b has a function of generating a random number having a value in a range that can be generated in 16 bits (that is, a range from 0 to 65535). In this embodiment, the case where the game control microcomputer 560 includes two random number circuits is described. However, the game control microcomputer 560 may include three or more random number circuits. In this embodiment, when the 12-bit random number circuit 503a and the 16-bit random number circuit 503b are comprehensively expressed, or when indicating either the 12-bit random number circuit 503a or the 16-bit random number circuit 503b, This is called a random number circuit 503.

  Next, the configuration of the random number circuit 503 will be described. FIG. 7 is a block diagram illustrating a configuration example of the random number circuit 503. In this embodiment, the basic configurations of the 12-bit random number circuit 503a and the 16-bit random number circuit 503b are the same. As shown in FIG. 7, the random number circuit 503 includes a counter 521, a comparator 522, a count value permutation changing circuit 523, a clock signal output circuit 524, a count value update signal output circuit 525, a random value read signal output circuit 526, and a random number update. A system selection signal output circuit 527, a selector 528, a random number circuit activation signal output circuit 530, a random value storage circuit 531, an inversion circuit 532, a latch signal generation circuit 533, and a timer circuit 534 are included.

  In this embodiment, the random number circuit 503 determines whether the display result of variable display of a plurality of types of identification information is a specific display result (for example, whether the stop symbol of the special symbol display 8 is a jackpot symbol) A random number for jackpot determination is generated to determine whether or not. When the CPU 56 determines that the specific display result is based on the random number generated by the random number circuit 503, the CPU 56 shifts the gaming state to a specific gaming state (for example, a big hit gaming state) advantageous to the player. Note that the random number generated by the random number circuit 503 may be used as a determination random number other than the jackpot symbol, such as a variation pattern determination random number for determining a variation pattern of a special symbol.

  The counter 521 receives the predetermined signal selected by the selector 528 and outputs a count value C in response to the signal input from the selector 528. In this case, the counter 521 inputs a predetermined initial value, cyclically updates the count value C from the initial value to a predetermined final value according to a certain rule, and outputs it. Further, when the count value C is updated to the final value, the counter 521 outputs a notification signal indicating that the count value C has been updated to the final value to the CPU 56. In this embodiment, when a notification signal is output from the counter 521, the CPU 56 updates the initial value.

  In this embodiment, every time a signal is input from the selector 528 (every time a rising edge in the signal from the selector 528 is input), the counter 521 increments the count value C from “0” to “4095” by one. Count up. Further, when the counter 521 counts up the count value C to “4095”, the counter 521 outputs a notification signal indicating that the count value C has been updated to the final value to the CPU 56. Then, the CPU 56 inputs a notification signal from the counter 521 and updates the initial value. Then, the counter 521 counts up the count value C again from the initial value updated by the CPU 56 to “4095”. Further, when counting up to “4095”, the counter 521 starts counting from “0” again. Then, the counter 521 outputs a notification signal to the CPU 56 when it counts up to a value (final value) immediately before the updated initial value. In this embodiment, the comparator 522 outputs a notification signal to the counter 521 when all count values are input, as will be described later. In this case, when the notification signal is input from the comparator 522, the counter 521 resets the count value to “0”.

  The comparator 522 determines whether the input count value is larger than the random number maximum value set in the random number maximum value setting register 535, and the count value is larger than the random number maximum value (exceeded the random number maximum value). ), A notification signal may be output to the counter 521. In this case, for example, when the comparator 522 determines that the count value exceeds the random number maximum value, the notification signal is output to the counter 521 before the clock signal output circuit 524 next outputs the random number generation clock signal SI1. . For example, consider a case where the random number maximum value “256” is set in the random number maximum value setting register 535. In this case, when the counter 521 counts up from “0” to “256” and further outputs the count value “257”, the comparator 522 determines that the input count value “257” exceeds the random number maximum value “256”. Determine and output a notification signal to the counter 521. When the notification signal is input from the comparator 522, the counter 521 updates the count value to “258” and outputs it without waiting for the input of the random number generation clock signal SI1 from the clock signal output circuit 524. By repeatedly executing the above processing, the comparator 522 determines that the count value exceeds the random number maximum value while inputting the count value “257” to “4095”, and stores the count value in the repeat counter 521. Output a notification signal. The counter 521 repeatedly updates and outputs the count value without waiting for the input of the random number generation clock signal SI1 from the clock signal output circuit 524 while the notification signal is input from the comparator 522. By doing so, until the clock signal output circuit 524 next outputs the random number generation clock signal SI1, the count value is controlled to be counted up from “257” to “4095” at a high speed, Control is performed so that random numbers from “257” to “4095” are skipped (not stored in the random value storage circuit 531).

  The count value permutation change circuit 523 includes a count value permutation change register (RSC) 536, an update rule selection register (RRC) 542, and an update rule memory 543. The count value permutation change register 536 stores count value permutation change data “01h” for changing the permutation (order of arrangement from the initial value to the final value), which is the update order of the count value C counted up by the counter 521. . When the numerical value permutation change data “01h” is stored in the count value permutation change register 536, the count value permutation change circuit 523 displays the count value C permutation that the counter 521 counts up and updates. The permutation is changed to a different permutation from when “01h” is not stored. “H” indicates a hexadecimal number. In this case, when the numerical value permutation change data “01h” is stored, the count value permutation changing circuit 523 switches the update rule used for changing the permutation of the count values. In addition, when the counter 521 starts updating the count value after switching the update rule used for changing the count value permutation, the count value permutation change data of the count value permutation change register 536 is initialized from “01h” by the CPU 56. The value is returned to “0 (= 00h)” (cleared).

  Instead of clearing the count value permutation data by the CPU 56, the count value permutation data may be cleared on the random number circuit 503 side. For example, when the register value is set in the update rule selection register (RRC) 542 based on the count value permutation change data “01h” being written in the count value permutation change register 536, the count value permutation change circuit 523 The register value of the count value permutation change register 536 may be cleared.

  FIG. 8 is an explanatory diagram showing an example of the update rule selection register (RRC) 542. The update rule selection register 542 is a register that sets an update rule used for rearranging the order of count values output from the counter 521 (changing the permutation). In this embodiment, an update rule used for changing the permutation of count values output from the counter 521 is set by setting a register value in the update rule selection register 542. As shown in FIG. 8, the update rule selection register 542 is an 8-bit register, and the initial value is set to “0 (= 00h)”. The update rule selection register 542 is configured in a state where bits 0 to 3 can be written and read. In addition, the update rule selection register 542 is configured in a state where bits 4 to 7 cannot be written or read. Therefore, even if control is performed to write values to bits 4 to 7 of the update rule selection register 542, it is invalid, and all the values read from bits 4 to 7 are “0 (= 0000b)”. “B” indicates a binary number.

  The value (register value) of the update rule selection register 542 is changed from “0 (= 00h)” to “15” in response to the count value permutation change data “01h” being written in the count value permutation change register 536. (= 0Fh) ”is updated cyclically. That is, each time the count value permutation data “01h” is written to the count value permutation change register 536, the register value of the update rule selection register 542 is incremented from “0” by “1” to become “15”. Return to "0".

  FIG. 9 is an explanatory diagram showing an example of the update rule memory 543. As shown in FIG. 9, the update rule memory 543 stores the value (register value) of the update rule selection register 542 and the count value update rule in association with each other. In the example illustrated in FIG. 9, for example, when the register value 1 is set in the update rule selection register 542, it can be seen that the permutation of the count values output by the counter 521 is changed using the update rule B. In FIG. 9, the update rule A is the same update rule as that by which the counter 521 updates the count value C, and is stored in the update rule memory 543 in association with the register value “0”. Also, in the update rule memory 543, update rules B to P different from the update rule in which the counter 521 updates the count value C are stored in association with the register values “1” to “15”.

  When the count value permutation change data “01h” is written in the count value permutation change register 536, the count value permutation change circuit 523 first counts from the counter 521 until the final count value “4095” is first input. The count value is output as it is according to the currently set update rule. The count value permutation changing circuit 523 changes the count value update rule when the final value “4095” of the count value is input from the counter 521. When the initial value is changed by the CPU 56, the count value permutation changing circuit 523 inputs the final value after the change (the value immediately before the initial value) from the counter 521, and updates the count value. Will be changed.

  The count value permutation change circuit 523 selects an update rule corresponding to the register value of the update rule selection register 542 from the update rule memory 543, and sets it as an update rule used for changing the count value permutation. The count value permutation change circuit 523 changes the permutation from the initial value of the count value to the final value according to the set update rule when the counter 521 starts updating the count value again in order from the initial value “0”. To do. When the initial value is changed by the CPU 56, the count value permutation changing circuit 523 starts counting in accordance with the set update rule when the counter 521 starts updating the count value in order from the changed initial value. The permutation from the initial value to the final value will be changed. Then, the count value permutation change circuit 523 outputs a count value according to the changed permutation.

  In this embodiment, when the maximum random number to be generated is limited by setting the maximum random number in a random number maximum value setting register 535 described later, the count value permutation changing circuit 523 counts The value C is limited to the maximum random number or less, and the permutation is changed and output. For example, it is assumed that the random number maximum value “256” is set in the random number maximum value setting register 535, and the count value permutation changing circuit 523 changes the update rule A to the update rule B to change the count value permutation. Shall. In this case, the count value permutation changing circuit 523 changes the count value permutation to “256 → 255” according to the update rule B based on the random number maximum value “256” set in the random number maximum value setting register 535 of the comparator 522. → → → 0 "and output.

  As described above, when the count value permutation change data “01h” is written in the count value permutation change register 536, the count value permutation change circuit 523 changes the update rule to use the permutation of the count value C. Change and output. Therefore, the randomness of the random number generated by the random number circuit 503 can be improved.

  FIG. 10 is an explanatory diagram illustrating an example in which the count value permutation changing circuit 523 changes the permutation of the count values output from the counter 521. As shown in FIG. 10, the CPU 56 writes the count value permutation change data “01h” into the count value permutation change register 536 at a predetermined timing. Then, 1 is added to the register value of the update rule selection register 542. For example, the register value of the update rule selection register 542 is updated from “0” to “1”. When the register value is updated, the count value permutation changing circuit 523 updates the “update rule A” corresponding to the register value “0” before the update until the final value “4095” of the count value is input from the counter 521 for the first time. The count value is updated according to "." At this time, the count value permutation changing circuit 523 outputs the count values in a permutation of “0 → 1 →... → 4095” according to the update rule A.

  When the final value “4095” of the count value is input from the counter 521, the count value permutation changing circuit 523 selects “update rule B” corresponding to the updated register value “1” from the update rule memory 543. To set. When the count value permutation changing circuit 523 starts to input the count values after the initial value “0” from the counter 521 again, the count value permutation changing circuit 523 changes the permutation of the count values according to the selected “update rule B” and outputs it. In this embodiment, the count value permutation changing circuit 523 changes the permutation from “0 → 1 →... → 4095” to “4095 → 4094 →... → 0” and outputs the count value.

  Thereafter, the count value permutation change register 536 is reset in response to the count value permutation change circuit 523 starting the count value updating operation in accordance with the updated update rule, as will be described later. Then, until the next count value permutation change data “01h” is written to the count value permutation change register 536, the count value permutation change circuit 523 counts the permutation as “4095 → 4094 →. Continue to output values.

  When the count value permutation change data “01h” is written again to the count value permutation change register 536 by the CPU 56, the register value of the count value permutation change register 536 is updated from “1” to “2”. When the final value “4095” of the count value is input from the counter 521, the count value permutation changing circuit 523 selects and sets “update rule C” corresponding to the register value “2” from the update rule memory 543. . When the count value permutation changing circuit 523 starts to input the count value after the initial value “0” again from the counter 521, the count value permutation changing circuit 523 updates and outputs the count value permutation in accordance with the “update rule C” selected and set. In this embodiment, the count value permutation changing circuit 523 changes the permutation from “4095 → 4094 →... → 0” to “1 → 3 →... → 4095 → 0 →. Output the count value.

  As described above, the count value permutation register 536 is reset, and then the count value permutation data “01h” is written again into the count value permutation change register 536, whereby the permutation of the count values can be further changed.

  FIG. 11 is an explanatory diagram illustrating an example of the count value permutation change register (RSC) 536. The count value permutation change register 536 is a register that sets count value permutation change data “01h” for changing the permutation of count values counted up by the counter 521. As shown in FIG. 11, the count value permutation change register 536 is a readable 8-bit register, and the initial value is set to “0 (= 00h)”. Further, count value permutation change register 536 is configured such that only bit 0 can be written and read. That is, count value permutation change register 536 is configured such that bits 1 to 7 cannot be written or read. Accordingly, even if control is performed to write a value to bits 1 to 7 of the count value permutation change register 536, the value read from bits 1 to 7 is all “0 (= 0000000b)”.

  Note that the value of the count value permutation change register 536 is reset by the CPU 56 in response to the count value permutation change circuit 523 starting a count value update operation in accordance with the updated update rule. In this case, the CPU 56 returns the value written in the count value permutation change register 536 from the count value permutation change data “01h” to the initial value “0 (= 00h)”.

  The comparator 522 includes a random number maximum value setting register (RMX) 535 that stores random number maximum value setting data for designating the maximum value of random R (random number maximum value). The comparator 522 limits the update range of the count value updated by the counter 521 according to the random number maximum value indicated in the random number maximum value setting data stored in the random number maximum value setting register 535. In this embodiment, the comparator 522 has a random number maximum value (for example, “0100h”) indicated by the count value input from the counter 521 and the random number maximum value setting data (for example, “0100h”) stored in the random number maximum value setting register 535. 256 "). When the comparator 522 determines that the input count value is equal to or less than the random number maximum value, the comparator 522 outputs the input count value to the random value storage circuit 531.

  In this embodiment, the comparator 522 specifically performs the following control. The comparator 522 obtains the initial value of the count value from the CPU 56 when updating the initial value of the count value, and obtains the number of count values from the initial value to the maximum random number. For example, when the initial value of the count value is “157” and the maximum random number value is “256”, the comparator 522 calculates the number of count values from the initial value to the maximum random number value as “100”. Further, the comparator 522 counts up how many count values are input from the initial value as the count values are input from the count value permutation changing circuit 523. When the number of input count values from the initial value reaches “100”, the comparator 522 determines that all count values from the initial value “157” to the maximum value “256” have been input. Then, the comparator 522 outputs a notification signal indicating that all count values have been input to the counter 521. By determining based on the number of count values, even when the count value permutation circuit 523 has changed the count value permutation, the comparator 522 limits the update range of the count value to the maximum random number or less. When all count values are input, a notification signal can be output to the counter 521.

  An operation in which the comparator 522 limits the update range of the count value will be described. In this embodiment, the case where the count value permutation changing circuit 523 selects the update rule A and the random number maximum value “256” is set in the random number maximum value setting register 535 will be described.

  While the counter 521 is updating the count value from “0” to “256”, the count value permutation changing circuit 523 updates based on the random number maximum value “256” set in the random number maximum value setting register 535. In accordance with rule A, the count values from “0” to “256” are output to the comparator 522 as they are. In this case, the count value permutation changing circuit 523 receives the value of the random number maximum value “256” from the comparator 522, determines whether the count value input from the counter 521 is larger than the random number maximum value, and the update rule is changed. Even when it is set (for example, update rule B), the count values from “257” to “4095” are compared based on the random number maximum value “256” set in the random number maximum value setting register 535. The data is not output to the device 522. For example, when the initial value is set to “0” and the count value is updated to the final value “256”, the counter 521 outputs a notification signal to the CPU 56. When the notification signal is output, the CPU 56 changes the initial value of the count value of the counter 521. In this embodiment, the CPU 56 changes the initial value to “50”.

  Note that the comparator 522 may determine whether the count value is greater than the maximum random number “256”, instead of the count value permutation changing circuit 523. In this case, for example, the comparator 522 determines whether or not the count value is greater than the random number maximum value set in the random number maximum value setting register 535, and determines that the count value is greater than the random number maximum value. Is output to the counter 521. When the comparator 522 determines that the count value exceeds the random number maximum value, the comparator 522 outputs a notification signal to the counter 521 before the clock signal output circuit 524 next outputs the random number generation clock signal SI1. By doing so, the comparator 522 counts up the count value from “257” to “4095” at high speed until the clock signal output circuit 524 next outputs the random number generation clock signal SI1. Thus, the counter 521 is controlled. By doing so, the count value is output to the random value storage circuit 531 only when the value from the count value permutation changing circuit 523 is less than “257”, and the value from the count value permutation changing circuit 523 is “257”. When the value is greater than or equal to “,” the count value can be updated at high speed.

  Based on the update rule A, while the count value is input from “0” to “255” from the count value permutation changing circuit 523, the comparator 522 inputs the count value below the maximum random number “256”. Therefore, the input count value is output to the random value storage circuit 531 as it is. Next, when the count value input from the count value permutation changing circuit 523 reaches “256”, the comparator 522 outputs the input count value to the random value storage circuit 531 and all the values from the initial value to the maximum value. A notification signal indicating that the count value is input is output to the counter 521. Specifically, the comparator 522 inputs the initial value of the count value (“0” in this embodiment) from the CPU 56 when changing the initial value of the count value, and the random number maximum from the initial value “0”. The number of count values (in this embodiment, “257”) up to the value (in this embodiment, “256”) is obtained. When the number of count values input from count value permutation changing circuit 523 reaches 257, a notification signal indicating that all count values have been input is output to counter 521. In this embodiment, since the initial value is changed to “50” by the CPU 56, the counter 521 does not reset the count value even when a notification signal is input from the comparator 522, but the changed initial value. The count value is updated from “50”.

  While the counter 521 updates the count value from the changed initial value “50” to “256”, the count value permutation changing circuit 523 sets the random number maximum value “256” set in the random number maximum value setting register 535. Based on the update rule A, the count values from “50” to “256” are output to the comparator 522 as they are. Further, the count value permutation changing circuit 523 does not output the count values from “257” to “4095” to the comparator 522 based on the random number maximum value “256” set in the random number maximum value setting register 535. When the count value to be updated by the counter 521 makes one round (when updated 257 times), when the count value permutation change data is written in the count value permutation change register 536, the count value permutation change circuit 523 Change the permutation of count values and output. For example, when the update rule is changed to the update rule B, the count value permutation changing circuit 523 changes the count value permutation from “256 → 255 →... 50” and outputs the result.

  While the count values from “256” to “50” are input from the count value permutation changing circuit 523, the comparator 522 outputs the input count value as it is to the random value storage circuit 531. Next, when the count value input from the count value permutation change circuit 523 reaches “50”, the comparator 522 outputs the input count value to the random value storage circuit 531 and all the values from the initial value to the maximum value. A notification signal indicating that the count value is input is output to the counter 521. Specifically, the comparator 522 receives the initial value of the count value (“50” in this embodiment) from the CPU 56 when changing the initial value of the count value, and the random number maximum value from the initial value “50”. The number of count values up to (“256” in this embodiment) (“207” in this embodiment) is obtained. When the number of count values input from count value permutation changing circuit 523 reaches 207, a notification signal indicating that all count values have been input is output to counter 521.

  Even when the count value permutation changing circuit 523 changes the count value permutation, the comparator 522 outputs a notification signal to the counter 521 when the number of count values reaches 207. By doing so, even if the permutation of the count values is changed, the notification signal is counted based on the input of all the count values from the initial value “50” to the maximum value “256”. 521 can be output.

  When the notification signal is input from the comparator 522, the counter 521 resets the initial value of the count value and returns it to “0”. Then, the counter 521 updates the count value from “0”. When the value of the counter 521 is updated again from “0”, the count value permutation changing circuit 523 outputs the count values from “49” to “0” to the comparator 522 based on the count value from the counter 521. The comparator 522 outputs the count value to the random value storage circuit 531 based on the count value input from the count value permutation changing circuit 523. Then, when the counter 521 updates the count value to the final value (“49” in this embodiment), the counter 521 outputs a notification signal to the CPU 56. When the notification signal is output, the initial value of the count value of the counter 521 is changed again by the CPU 56.

  By repeating the operation as described above, the comparator 522 causes the counter 521 to continuously count up the count value from “0” to the random number maximum value “256”, and the value from “0” to “256”. Is stored in the random value storage circuit 531 as a random R (random number value). In other words, the comparator 522 limits the update range of the count value to the random number maximum value “256” or less, and causes the counter 521 to update the count value.

  FIG. 12 is an explanatory diagram showing an example of the random number maximum value setting register (RMX) 535. FIG. 12A shows an example of the random number maximum value setting register 535 installed in the 12-bit random number circuit 503a. FIG. 12B shows an example of the random number maximum value setting register 535 installed in the 16-bit random number circuit 503b. First, the random number maximum value setting register 535 mounted in the 12-bit random number circuit 503a will be described. As shown in FIG. 12A, in the 12-bit random number circuit 503a, the random number maximum value setting register 535 is a 16-bit register, and the initial value is set to “4095 (= 0FFFh)”. The random number maximum value setting register 535 is configured so that bits 0 to 11 can be written and read. The random number maximum value setting register 535 is configured such that bits 12 to 15 cannot be written or read. Therefore, in the 12-bit random number circuit 503a, even if control is performed to write values to bits 12 to 15 of the random number maximum value setting register 535, the values read from bits 12 to 15 are all “0 (= 0000b)”. It is.

  The random number maximum value set in the random number maximum value setting register 535 has a predetermined lower limit value. In this embodiment, when random number maximum value setting data “0000h” to “00FFh” designating a value smaller than the lower limit value “256” is written in the random number maximum value setting register 535, the CPU 56 stores the random number maximum value setting register. The random number maximum value setting data “0FFFh” for specifying the initial value “4095” is set again in 535. That is, the random number maximum value that can be set in the random number maximum value setting register 535 is from “256” to “4095”, and when the CPU 56 determines that a value smaller than the lower limit value “256” is set, the random number maximum value Is reset to a predetermined value “4095”. The CPU 56 cannot write the random number maximum value setting register 535 in which the random number maximum value setting data is written until the game control microcomputer 560 (specifically, the CPU 56) is reset by the reset controller 502. Control. In addition, the random number maximum value setting register 535 may be formed so as not to be writable until a reset signal is input after data is written, instead of being controlled so as not to be writable by the CPU 56.

  Next, the random number maximum value setting register 535 mounted in the 16-bit random number circuit 503b will be described. As shown in FIG. 12B, in the 16-bit random number circuit 503b, the random number maximum value setting register 535 is a 16-bit register, and the initial value is set to “65535 (= FFFFh)”. Further, in the 16-bit random number circuit 503b, the random number maximum value setting register 535 is configured in a state in which all of the bits 0 to 15 can be written and read.

  When random number maximum value setting data “0000h” to “00FFh” for designating a value smaller than the lower limit value “256” is written in the random number maximum value setting register 535, the CPU 56 sets the initial value in the random number maximum value setting register 535 to the initial value. The random number maximum value setting data “FFFFh” specifying the value “65535” is reset. That is, the random number maximum value that can be set in the random number maximum value setting register 535 is from “256” to “65535”, and when the CPU 56 determines that a value smaller than the lower limit value “256” is set, the random number maximum value Is reset to a predetermined value “65535”. The CPU 56 cannot write the random number maximum value setting register 535 in which the random number maximum value setting data is written until the game control microcomputer 560 (specifically, the CPU 56) is reset by the reset controller 502. Control. In addition, the random number maximum value setting register 535 may be formed so as not to be writable until a reset signal is input after data is written, instead of being controlled so as not to be writable by the CPU 56.

  The clock signal output circuit 524 includes a cycle setting register (RPS) 537 for storing cycle setting data for designating the cycle of the clock signal output to the selector 528 and the inverting circuit 532 (that is, the count value update cycle). The clock signal output circuit 524 divides the reference clock signal CLK input from the clock circuit 501 mounted on the game control microcomputer 560 based on the cycle setting data stored in the cycle setting register 537, and generates a random number circuit. A clock signal (random number generating clock signal SI1) used to generate a random number value is generated inside 503. By doing so, the clock signal output circuit 524 operates to output the random number generation clock signal SI1 for updating the count value C to the counter 521 on condition that the clock signal has been input a predetermined number of times. . The period setting data is data for setting how many times the reference clock signal CLK input from the clock circuit 501 is to be divided. The clock output circuit 524 outputs the generated random number generating clock signal SI1 to the selector 528 and the inverting circuit 532. For example, when the cycle setting data “0Fh (= 15)” is written in the cycle setting register 537, the clock signal output circuit 524 divides the reference clock signal CLK input from the clock circuit 501 by 16, and generates random numbers. A clock signal SI1 is generated. In this case, the cycle of the random number generating clock signal SI1 generated by the clock signal output circuit 524 is “cycle of system clock signal × 128 × 16”. Note that the clock signal output circuit 524 divides the reference clock signal CLK by (the value set in the period setting register 537 + 1).

  FIG. 13 is an explanatory diagram showing an example of the cycle setting register (RPS) 537. As shown in FIG. 13, the period setting register 537 is an 8-bit register, and the initial value is set to “FFh corresponding to 256 division”. The cycle setting register 537 is configured in a state where both writing and reading are possible.

  In addition, a predetermined lower limit value is determined for the value of the cycle setting data set in the cycle setting register 537. In this embodiment, when the cycle setting data “00h to 06h” designating a value smaller than the lower limit value “system clock signal cycle × 128 × 7” is written in the cycle setting register 537, the CPU 56 In 537, the cycle setting data “07h” for specifying the lower limit value “system clock signal cycle × 128 × 7” is reset. That is, the period that can be set in the period setting register 537 is “system clock signal period × 128 × 7” to “system clock signal period × 128 × 256”, and the CPU 56 is set to a value smaller than the lower limit value. If it is determined that it is, the cycle setting data is reset. The CPU 56 controls the period setting register 537 in which the period setting data is written to be unwritable until the game controller microcomputer 560 (specifically, the CPU 56) is system reset by the reset controller 502. Instead of controlling the CPU 56 to disable writing, the period setting register 537 may be formed so that writing is not possible until a reset signal is input after data is written.

  Note that, without setting the cycle setting data as the lower limit value in the cycle setting register 537, the clock signal output circuit 524, for example, directly supplies the reference clock signal CLK to the counter 521 and the inverting circuit 532 based on the set cycle setting data. You may make it output. In this case, the CPU 56 does not need to perform processing for setting the value of the cycle setting data set in the cycle setting register 537 by comparing it with the lower limit value. Further, the counter 521 updates the count value C every time the reference clock signal CLK is input from the clock signal output circuit 524.

  The count value update signal output circuit 525 includes a count value update register (RGN) 538 that stores count value update data “01h”. The count value update data is data for requesting update of the count value. The count value update signal output circuit 525 outputs the count value update signal SI3 to the selector 528 in response to the count value update data “01h” being written in the count value update register 538.

  FIG. 14 is an explanatory diagram illustrating an example of the count value update register 538. As shown in FIG. 14, the count value update register 538 is an unreadable 8-bit register and is configured so that only bit 0 can be written. Accordingly, even if control is performed to write a value to bits 1 to 7 of the count value update register 538, it is invalidated.

  The random value read signal output circuit 526 includes a random value take-in register (RLT) 539 for storing random value take-in data “01h”. The random value acquisition data is data for requesting acquisition of the count value to the random value storage circuit 531. The random value read signal output circuit 526 generates a latch value read signal for requesting reading of the random value in response to the random value take-in data “01h” being written in the random value take-in register 539. Output to the circuit 533.

  FIG. 15 is an explanatory diagram showing an example of the random value fetch register 539. As shown in FIG. 15, the random value fetch register 539 is an unreadable 8-bit register. The random value fetch register 539 is configured so that only bit 0 can be written. That is, even if control is performed to write a value to bits 1 to 7 of the random value fetch register 539, it is invalidated.

  The random number update method selection signal output circuit 527 includes a random number update method selection register (RTS) 540 that stores random number update method selection data. The random number update method selection data is data for designating one of the random number update methods, which is a method for updating the value of the random R. The random number update method selection signal output circuit 527 responds to the random number update method selection data written in the random number update method selection register 540, and corresponds to the random number update method specified by the written random number update method selection data. The update method selection signal is output to the selector 528 and the latch signal generation circuit 533.

  FIG. 16A is an explanatory diagram illustrating an example of the random number update method selection register 540. As shown in FIG. 16A, the random number update method selection register 540 is an 8-bit register, and the initial value is set to “00h”. The random number update method selection register 540 is configured in a state where bits 0 to 1 can be written and read. The random number update method selection register 540 is configured in a state where bits 2 to 7 cannot be written or read. Therefore, even if control is performed to write a value to bits 2 to 7 of the random number update method selection register 540, it is invalid, and all the values read from bits 2 to 7 are “0 (= 000000b)”.

  FIG. 16B is an explanatory diagram of an example of random number update method selection data written to the random number update method selection register 540. As shown in FIG. 16B, the random number update method selection data is composed of 2-bit data. The random number update method selection data “01b” is used to specify the first random number update method. The random number update method selection data “10b” is used to specify the second random number update method. In this embodiment, the first random number update method is a method of updating the count value triggered by the output of the count value update signal SI3 from the count value update signal output circuit 525. The second random number update method is a method of updating the count value triggered by the output of the random number generation clock signal SI1 from the clock signal output circuit 524. Further, when the random number update method selection data “01b” or “10b” is written in the random number update method selection register 540, the random number circuit 503 is ready to be activated. On the other hand, when the random number update method selection data “00b” or “11b” is written to the random number update method selection register 540, the random number circuit 503 cannot be activated.

  The selector 528 selects either the count value update signal SI 3 output from the count value update signal output circuit 525 or the random number generation clock signal SI 1 output from the clock signal output circuit 524 and outputs the selected signal to the counter 521. When a random number update method selection signal (also referred to as a first random number update method selection signal) corresponding to the first random number update method is input from the random number update method selection signal output circuit 527, the selector 528 outputs a count value update signal. The count value update signal SI3 output from the circuit 525 is selected and output to the counter 521. On the other hand, when a random number update method selection signal (also referred to as a second random number update method selection signal) corresponding to the second random number update method is input from the random number update method selection signal output circuit 527, the selector 528 outputs a clock signal. The random number generation clock signal SI 1 output from the circuit 524 is selected and output to the counter 521. When the first update method selection signal is input from the random number update method selection signal output circuit 527, the selector 528 receives a clock signal according to the count value update signal SI3 output from the count value update signal output circuit 525. A numerical value update instruction signal for instructing update of numerical data synchronized with the random number generation clock signal SI 1 output from the output circuit 524 may be output to the counter 521.

  The random number circuit activation signal output circuit 530 includes a random number circuit activation register (RST) 541 that stores random number circuit activation data “80h”. The random circuit activation data is data for requesting activation of the random number circuit 503. When random number circuit activation data “80h” is written to the random number circuit activation register 541, the random number circuit activation signal output circuit 530 outputs a predetermined random number circuit activation signal to the counter 521 and the clock signal output circuit 537, and the counter 521 and the clock The signal output circuit 524 is turned on. The random number circuit 503 is activated by starting the count value updating operation by the counter 521 and the internal clock signal output operation by the clock signal output circuit 524.

  FIG. 17 is an explanatory diagram showing an example of the random number circuit activation register 541. As shown in FIG. 17, the random number circuit activation register 541 is an 8-bit register, and the initial value is set to “00h”. The random number circuit activation register 541 is configured such that only bit 7 can be written and read. In addition, the random number circuit activation register 541 is configured such that bits 0 to 6 cannot be written or read. That is, even if control is performed to write a value to bits 0 to 6 of the random number circuit activation register 541, the value is invalid, and all values read from bits 0 to 6 are “0 (= 000000b)”.

  The random value storage circuit 531 is a 16-bit register, for example, and stores a random R value that is a random number used in the jackpot determination in the game control process. The random value storage circuit 531 stores the count value C output from the counter 521 via the comparator 522 as a random R value in response to the input of the latch signal SL from the latch signal generation circuit 533. Each time the latch signal SL is input from the latch signal generation circuit 533, the random value storage circuit 531 reads the count value C updated by the counter 521 and stores the random R value.

  FIG. 18 is a circuit diagram showing a configuration example of the random value storage circuit 531. As shown in FIG. 18, the random value storage circuit 531 includes two AND circuits 201 and 203, two NOT circuits 202 and 204, 16 flip-flop circuits 2101 to 2116, and 16 OR circuits. 2201-2216.

  As shown in FIG. 18, the input terminal of the AND circuit 201 is connected to the output terminal of the latch signal generation circuit 533 and the output terminal of the NOT circuit 204, and the output terminal is connected to the input terminal of the NOT circuit 202 and the flip-flop circuit 2101. Are connected to clock terminals Clk1 to Clk16. The input terminal of the NOT circuit 202 is connected to the output terminal of the AND circuit 201, and the output terminal is connected to one input terminal of the AND circuit 203.

  The input terminal of the AND circuit 203 is connected to the output terminal of the NOT circuit 202 and the CPU 56 mounted on the game control microcomputer 560, and the output terminal is connected to the input terminal of the NOT circuit 204. The input terminal of the NOT circuit 204 is connected to the output terminal of the AND circuit 203, and the output terminal is connected to one input terminal of the AND circuit 201 and one input terminal of the OR circuits 2201 to 2216.

  The input terminals D1 to D16 of the flip-flop circuits 2101 to 2116 are connected to the output terminal of the comparator 522. The clock terminals Clk1 to Clk16 of the flip-flop circuits 2101 to 2116 are connected to the output terminal of the AND circuit 201, and the output terminals Q1 to Q16 are connected to the other input terminals of the OR circuits 2201 to 2216.

  The input terminals of the OR circuits 2201 to 2216 are connected to the output terminal of the NOT circuit 204 and the output terminals of the flip-flop circuits 2101 to 2116, and the output terminals are connected to the CPU 56 mounted on the game control microcomputer 560. .

  The operation of the random value storage circuit 531 is described. FIG. 19 is a timing chart showing the timing at which each signal is input to the random value storage circuit 531 and the timing at which the random value storage circuit 531 outputs each signal. As shown in FIG. 19, when the output control signal SC (high level signal in this embodiment) is not input from the CPU 56 mounted on the game control microcomputer 560 (that is, one input terminal of the AND circuit 203). When the latch signal SL is input from the latch signal generation circuit 533 (in the example shown in FIG. 19, at timings T1, T2, and T7), the two input terminals of the AND circuit 201 Both inputs to go high. Therefore, the signal SR output from the output terminal of the AND circuit 201 is at a high level. The signal SR output from the AND circuit 201 is input to the clock terminals Clk1 to Clk16 of the flip-flop circuits 2101 to 2116.

  The flip-flop circuits 2101 to 2116 are responsive to the rising edges of the signal SR input from the clock terminals Clk1 to Clk16, and the bit data C1 to C1 of the count value C input from the comparator 522 via the input terminals D1 to D16. C16 is latched and stored as bit data R1 to R16 of the random value. The flip-flop circuits 2101 to 2116 output random R bit data R1 to R16 to be stored from the output terminals Q1 to Q16.

  When the output control signal SC is not input (in the example shown in FIG. 19, the period up to the timing T3 and the period after the timing T6), the input to one input terminal of the AND circuit 203 is at the low level. The signal SG output from the output terminal of the circuit 203 is at a low level. The signal SG output from the AND circuit 203 is inverted by the NOT circuit 204 to be a high level signal. A high level signal is input from the NOT circuit 204 to one input terminal of each of the OR circuits 2201 to 2216.

  As described above, since the input to one of the input terminals of the OR circuits 2201 to 2216 is at a high level, the OR is input regardless of whether the signal input to the other input terminal is at a high level or a low level. The circuits 2201 to 2216 output high level signals. That is, the signals SO1 to SO16 output from the OR circuits 2201 to 2216 are all at a high level regardless of whether the values of the input random R bit data R1 to R16 are “0” or “1”. (“1”). By doing so, the value output from the random value storage circuit 531 is always “65535 (= 1111111111111111b)”, and the random R cannot be read from the random value storage circuit 531. That is, even if an attempt is made to read a random number from the random value storage circuit 531, only the same value “65535” can always be read from the random value storage circuit 531, and when the output control signal SC is not input, the random value storage circuit 531 is in an unreadable (disabled) state. When the 16-bit random number circuit 503b is used, the value “65535” as the random number value may be used. In this case, even if the CPU 56 reads the value “65535”, the CPU 56 cannot determine whether the value is a random number or an unreadable state. Therefore, in the determination table for each jackpot determination shown in FIG. 38, when the random R is “65535”, it may be set to be determined as “out of”.

  When the output control signal SC is input from the CPU 56 when the latch signal SL is not input from the latch signal generation circuit 533 (in the example shown in FIG. 19, the period from the timing T4 to the timing T6), Since the inputs to the two input terminals are both at the high level, the signal SG output from the output terminal of the AND circuit 203 is at the high level. The signal SG output from the AND circuit 203 is inverted in the NOT circuit 204 to be a low level signal. A low level signal is input from the NOT circuit 204 to one input terminal of the OR circuits 2201 to 2216.

  As described above, since the input to one input terminal of the OR circuits 2201 to 2216 is at a low level, when the signal input to the other input terminal is at a high level, the output from the output terminals of the OR circuits 2201 to 2216 is high. A level signal is output. In addition, when a signal input to the other input terminal of the OR circuits 2201 to 2216 is at a low level, a low level signal is output from the OR circuits 2201 to 2216. That is, the values of the random R bit data R1 to R16 input to the other input terminals of the OR circuits 2201 to 2216 are unchanged from the output terminals of the OR circuits 2201 to 2216 (that is, the values of the bit data R1 to R16 are “ “1” is output when it is “1” and “0” when it is “0”). By doing so, random R can be read from the random value storage circuit 531. That is, when the output control signal SC is input, the random value storage circuit 531 enters a readable (enable) state.

  However, if the latch signal SL is input from the latch signal generation circuit 533 before the output control signal SC is input from the CPU 56, the input to one input terminal of the AND circuit 203 is at a low level. Even if the output control signal SC is input while the latch signal SL is being input (in the example shown in FIG. 19, it is output from the output terminal of the AND circuit 203). The signal SG remains at a low level. The signal SG output from the AND circuit 203 is inverted by the NOT circuit 204 to be a high level signal. A high level signal is input from the NOT circuit 204 to one input terminal of each of the OR circuits 2201 to 2216.

  As described above, since the input to one of the input terminals of the OR circuits 2201 to 2216 is at a high level, the OR is input regardless of whether the signal input to the other input terminal is at a high level or a low level. The signals SO1 to SO16 output from the circuits 2201 to 2216 are all at a high level. Even though the output control signal SC is input, the random R cannot be read from the random value storage circuit 531. That is, when the latch signal SL is input, the random value storage circuit 531 cannot receive the output control signal SC. When the 16-bit random number circuit 503b is used, the value “65535” as the random number value may be used. In this case, even if the CPU 56 reads the value “65535”, the CPU 56 cannot determine whether the value is a random number or an unreadable state. Therefore, in the determination table for each jackpot determination shown in FIG. 38, when the random R is “65535”, it may be set to be determined as “out of”.

  Further, when the output control signal SC is input from the CPU 56 before the latch signal SL is input from the latch signal generation circuit 533, the input to one input terminal of the AND circuit 201 is at a low level. Even if the latch signal SL is input while the control signal SC is being input (in the example shown in FIG. 19, timing T5), the signal SR output from the output terminal of the AND circuit 201 remains at the low level. It becomes. Therefore, the signal SR input to the clock terminals Clk1 to Clk16 of the flip-flop circuits 2101 to 2116 does not rise from the low level to the high level, and the random R bit data R1 to R16 stored in the flip-flop circuits 2101 to 2116. Is not updated despite the latch signal SL being input. That is, when the output control signal SC is input, the random value storage circuit 531 cannot receive the latch signal SL.

  The inversion circuit 532 generates the inverted clock signal SI2 in which the polarity of the clock signal is inverted by inverting the signal level in the random number generation clock signal SI1 input from the clock signal output circuit 524. Further, the inverting circuit 532 outputs the generated inverted clock signal SI2 to the latch signal generating circuit 533.

  The latch signal generation circuit 533 is configured using a selector, a flip-flop circuit, and the like. The latch signal generation circuit 533 receives the random number read signal from the random number read signal output circuit 526 and the inverted clock signal SI2 from the inversion circuit 532, and stores the random value in the random value storage circuit 531. Output SL. The latch signal generation circuit 533 outputs the latch signal SL in accordance with the random value update method designated by the random number update method selection signal from the random number update method selection signal output circuit 527. In this case, when the first random number update method selection signal output circuit 527 receives the first random number update method selection signal output circuit 527, the latch signal generation circuit 533 selects the inverted clock signal SI2 output from the inversion circuit 532, and the latch signal It outputs to the random value storage circuit 531 as SL. On the other hand, when the second random number update method selection signal is input from the random number update method selection signal output circuit 527, the latch signal generation circuit 533 inverts the random value read signal output from the random value read signal output circuit 526. In synchronization with the rising edge of the inverted clock signal SI2 output from the circuit 532, the latch signal SL is output to the random value storage circuit 531.

  The timer circuit 534 inputs a winning detection signal SS indicating that a winning of a game ball to the starting port 14 has been detected from the starting port switch 14a. The timer circuit 534 measures the time during which the winning detection signal SS is continuously input from the start port switch 14a. Then, when the measurement time reaches a predetermined period (for example, 3 ms), the timer circuit 534 writes the random number value capture data “01h” in the random value capture register 539 of the random value read signal output circuit 526. For example, the timer circuit 534 is configured by an up counter or a down counter that is activated in response to the input of a high level signal. The timer circuit 534 receives the reference clock signal CLK sequentially input from the clock circuit 501 while the input from the start port switch 14a is at a high level (that is, while the winning detection signal SS is continuously input). Count up or down. Then, when the count value to be counted up or down reaches a value corresponding to 3 ms, the timer circuit 534 determines that the winning detection signal SS is input from the start port switch 14a, and stores the random number value capture data “01h”. Write to the random value fetch register 539.

  Next, the configuration of the serial communication circuit 505 will be described. The serial communication circuit 505 performs serial communication with each electrical component control microcomputer (for example, the payout control microcomputer 370) in a data format using a full duplex method, an asynchronous method, and standard NRZ (non-return zero) encoding. Do. The serial communication circuit 505 includes a transmission unit that transmits various data (for example, a prize ball number signal) to each control board, and a reception unit that receives various data (for example, a prize ball ACK command) from each control board. .

  FIG. 20 is a block diagram illustrating a configuration example of the transmission unit of the serial communication circuit 505. FIG. 21 is a block diagram illustrating a configuration example of the receiving unit of the serial communication circuit 505. The serial communication circuit 505 includes a baud rate register 702, a baud rate generation circuit 703, two status registers 705 and 706, three control registers 707, 708, and 709, a transmission data register 710, a reception data register 711, a transmission shift register 712, and a reception Shift register 713, interrupt control circuit 714, transmission format / parity generation circuit 715, and reception format / parity check circuit 716. As shown in FIG. 20, the transmission unit of the serial communication circuit 505 includes a baud rate register 702, a baud rate generation circuit 703, a status register A 705, control registers 707, 708, and 709, and a transmission data register 710. , A transmission shift register 712, an interrupt control circuit 714, and a transmission format / parity generation circuit 715. As shown in FIG. 21, the receiving unit of the serial communication circuit 505 includes a baud rate register 702, a baud rate generation circuit 703, status registers 705 and 706, control registers 707, 708, and 709, received data, among these components. The register 711, the reception shift register 713, the interrupt control circuit 714, and the reception format / parity check circuit 716 are configured.

  In the serial communication circuit 505, the transmission unit and the reception unit are actually configured using a common circuit. As described above, the serial communication circuit 505 functions as a transmission circuit or a reception circuit by properly using each component of the serial communication circuit 505.

  First, the data format of data transmitted and received by the serial communication circuit 505 with each control board will be described. FIG. 22 is an explanatory diagram illustrating an example of a data format of data transmitted / received by the serial communication 505 to / from each control board. As shown in FIG. 22, the data transmitted and received by the serial communication circuit 505 is configured as one frame including a start bit, data, and a stop bit. Further, the data length of data transmitted and received by the serial communication circuit 505 can be set to either 8 bits or 9 bits by performing initial setting in a serial communication circuit setting process described later. FIG. 22A shows an example of the data format when the data length is set to 8 bits. FIG. 22B shows an example of the data format when the data length is set to 9 bits.

  As shown in FIG. 22, the data transmitted and received by the serial communication circuit 505 is a start bit (logic “0”) indicating the start of one frame that is output after high-level (logic “1”) idle data. )including. Further, following the start bit, 8-bit or 9-bit transmission / reception data is included. Then, following the transmission / reception data, a stop bit (logic “1”) indicating the end of one frame is included.

  The serial communication circuit 505 transmits / receives data from the least significant bit (bit 0) of transmission / reception data according to the data format shown in FIG. Further, if initial setting is performed in a serial communication circuit setting process described later, it is possible to set so that a parity bit is added to transmission / reception data. When the setting is such that a parity bit is added, the most significant bit of the transmission / reception data is used as a parity bit (odd parity or even parity). For example, when the data length is set to 8 bits, bit 7 of transmission / reception data is used as a parity bit. For example, when the data length is set to 9 bits, bit 8 of transmission / reception data is used as a parity bit.

  The baud rate generation circuit 703 generates a baud rate used by the serial communication circuit 505 based on a clock signal output from the clock circuit 501 and a setting value (also referred to as a baud rate setting value) set in the baud rate register 702. In this case, the baud rate generation circuit 703 obtains the baud rate using a predetermined calculation formula based on the clock signal and the baud rate setting value. For example, the baud rate generation circuit 703 obtains the baud rate used by the serial communication circuit 505 using equation (1).

Baud rate = clock frequency / (baud rate set value x 16) Equation (1)

  FIG. 23 is an explanatory diagram showing a baud rate register (SIBR) 702. The baud rate register 702 is a register that sets a predetermined setting value for designating a baud rate value generated by the baud rate generation circuit 703. For example, it is assumed that the baud rate register 702 obtains a baud rate using the equation (1) and the clock frequency is 3 MHz. In this case, if the desired target baud rate is 1200 bps, the setting value “156” is set in the baud rate register 702. Then, the baud rate generation circuit 703 generates the baud rate “1201.92 bps” using the equation (1) based on the clock frequency “3 MHz” and the baud rate set value “156”. The baud rate register 702 is a 16-bit register, and an initial value is set to “0 (= 00h)”. Bit 0 to bit 12 of the baud rate register 702 can be written and read. Bit 13 to bit 15 of baud rate register 702 cannot be written or read. Therefore, even if control is performed to write values to bits 13 to 15 of the baud rate register 702, the values are invalid and all the values read from bits 13 to 15 are “0 (= 000b)”.

  FIG. 24A is an explanatory diagram illustrating an example of the control register A (SICL1) 707. The control register A 707 is a register for setting the communication format of the serial communication circuit 505. In this embodiment, the communication format of the serial communication circuit 505 is set by setting the value of each bit of the control register A707. In the control register A707, communication format setting data for setting a communication format such as a data format of transmission / reception data and various communication methods is set. As shown in FIG. 24A, the control register A707 is an 8-bit register, and the initial value is set to “0 (= 00h)”. In addition, bits 0 to 4 of the control register A707 can be written and read. Further, bits 5 to 7 of control register A707 cannot be written or read. Therefore, even if control is performed to write a value to bits 5 to 7 of the control register A707, it is invalid, and all the values read from bits 5 to 7 are “0 (= 000b)”.

  FIG. 24B is an explanatory diagram of an example of communication format setting data set in the control register A707. As shown in FIG. 24B, setting data for setting the data length of data to be transmitted and received is set in bit 4 (bit name “M”) of the control register A707. As shown in FIG. 24B, by setting bit 4 to “0”, the data length of the transmission / reception data is set to 8 bits. Further, by setting bit 4 to “1”, the data length of the transmission / reception data is set to 9 bits.

  In bit 3 (bit name “WAKE”) of the control register A707, setting data for setting a wake-up method for waking up the receiver circuit (the receiving unit of the serial communication circuit 505) in the standby state. Is set. As shown in FIG. 24 (B), by setting bit 3 to “0”, an idle line wakeup method for wakeup when an idle line is recognized is set. In addition, by setting bit 3 to “1”, an address mark wakeup method for wakeup by recognizing a predetermined address mark is set.

  In bit 2 (bit name “ILT”) of the control register A707, setting data for selecting a detection method of idle data of received data is set. As shown in FIG. 24B, by setting bit 2 to “0”, a detection method for detecting idle data after the start bit included in the received data is set. Further, by setting bit 2 to “1”, a detection method for detecting idle data after a stop bit included in received data is set.

  Setting data for setting whether or not to use the parity function is set in bit 1 (bit name “PE”) of the control register A707. As shown in FIG. 24B, the parity function is not used by setting bit 1 to “0”. Further, by setting bit 1 to “1”, the parity function is set to be used.

  Setting data for setting the type of parity when the parity function is used is set in bit 0 (bit name “PT”) of the control register A707. As shown in FIG. 24B, by setting bit 0 to “0”, even parity is set as the parity type. Also, by setting bit 0 to “1”, odd parity is set as the parity type.

  FIG. 25A is an explanatory diagram illustrating an example of the control register B (SICL2) 708. The control register B 708 is a register in which whether or not to permit an interrupt request from the serial communication circuit 505 is set. In this embodiment, whether or not an interrupt request from the serial communication circuit 505 is permitted is set by setting the value of each bit of the control register B708. In the control register B708, interrupt request setting data indicating whether or not various interrupt requests are permitted is mainly set. In addition to the interrupt request setting data, setting data for performing various settings of the serial communication circuit 505 is also set in the control register B708. As shown in FIG. 25A, the control register B708 is an 8-bit register, and the initial value is set to “0 (= 00h)”. Further, bits 0 to 7 of the control register B708 can be written and read.

  FIG. 25B is an explanatory diagram showing an example of interrupt request setting data set in the control register B708. As shown in FIG. 25B, setting data indicating whether or not a transmission interrupt request, which is an interrupt request to be performed at the time of data transmission, is permitted is set in bit 7 (bit name “TIE”) of the control register B708. Is done. As shown in FIG. 25B, by setting bit 7 to “0”, the transmission interrupt request is set to be prohibited. Also, by setting bit 7 to “1”, the transmission interrupt request is set to be permitted.

  Bit 6 (bit name “TCIE”) of the control register B708 is set with setting data indicating whether or not to permit a transmission completion interrupt request, which is an interrupt request to be made when data transmission is completed. As shown in FIG. 25B, by setting bit 6 to “0”, the transmission completion interrupt request is set to be prohibited. Further, by setting bit 6 to “1”, the transmission completion interrupt request is set to be permitted.

  Bit 5 (bit name “RIE”) of the control register B 708 is set with setting data indicating whether or not a reception interrupt request, which is an interrupt request to be performed when data is received, is permitted. As shown in FIG. 25B, by setting bit 5 to “0”, the reception interrupt request is set to be prohibited. Further, by setting bit 5 to “1”, the reception interrupt request is set to be permitted.

  Bit 4 (bit name “ILIE”) of the control register B708 is set with setting data indicating whether or not an idle line interrupt request, which is an interrupt request to be performed when an idle line of received data is detected, is permitted. As shown in FIG. 25B, by setting bit 4 to “0”, the idle line interrupt request is set to be prohibited. Further, by setting bit 4 to “1”, it is set to permit an idle line interrupt request.

  In bit 3 (bit name “TE”) of the control register B708, setting data indicating whether to use the transmission circuit (the transmission unit of the serial communication circuit 505) is set. As shown in FIG. 25B, by setting bit 3 to “0”, the transmission circuit is set not to be used. Further, by setting bit 3 to “1”, the transmission circuit is set to be used.

  In bit 2 (bit name “RE”) of the control register B708, setting data indicating whether or not to use the receiving circuit is set. As shown in FIG. 25B, by setting bit 2 to “0”, the receiving circuit is set not to be used. Further, by setting bit 2 to “1”, the receiving circuit is set to be used.

  Setting data indicating whether or not to use the wakeup function of the receiving circuit is set in bit 1 (bit name “RWU”) of the control register B708. As shown in FIG. 25B, by setting bit 1 to “0”, the wakeup function is set not to be used. Further, by setting bit 1 to “1”, the wakeup function is set to be used.

  Setting data indicating whether or not to use a predetermined break code transmission function is set in bit 0 (bit name “SBK”) of the control register B708. As shown in FIG. 25B, by setting bit 1 to “0”, the break code transmission function is set not to be used. Also, by setting bit 1 to “1”, the break code transmission function is set to be used. When bit 1 is set to “1”, the serial communication circuit 505 transmits a break code (for example, a signal continuously including “0”) to the control board (payout control board 37).

  FIG. 26A is an explanatory diagram illustrating an example of the status register A (SIST1) 705. The status register A 705 is a register for confirming various statuses of the serial communication circuit 505. In this embodiment, the CPU 56 can confirm various statuses of the serial communication circuit 505 by confirming the value of each bit of the status register A 705. As shown in FIG. 26A, the status register A705 is an 8-bit register, and the initial value is set to “0 (= 00h)”. In addition, bits 0 to 7 of the status register A705 can only be read. Therefore, even if control is performed to write a value to bits 0 to 7 of the status register A705, it is invalidated.

  FIG. 26B is a diagram showing an example of status confirmation data stored in the status register A705. As shown in FIG. 26 (B), transmission data indicating that transmission data is not stored in transmission data register 710 (transmission data empty) in bit 7 (bit name “TDRE”) of status register A 705. An empty flag is stored. As shown in FIG. 26B, when “0” is stored in bit 7, transmission data is not yet transferred from transmission data register 710 to transmission shift register 712, and transmission data is stored in transmission data register 710. Indicates that it is in the stored state. When “1” is stored in bit 7, the transmission data is transferred from the transmission data register 710 to the transmission shift register 712, and no transmission data is stored in the transmission data register 710 (transmission data empty). Indicates that there is.

  Bit 6 (bit name “TC”) of the status register A 705 stores a transmission completion flag indicating that transmission of transmission data from the serial communication circuit 505 has been completed. As shown in FIG. 26B, when “0” is stored in bit 6, the transmission data stored in the transmission shift register 712 is being transmitted, and the transmission data from the serial communication circuit 505 is not transmitted. Indicates that transmission has not been completed. Further, when “1” is stored in bit 6, the transmission data stored in the transmission shift register 712 has been transferred, and transmission of transmission data from the serial communication circuit 505 has been completed. It shows that.

  The transmission of the transmission data is completed, and the CPU 56 waits for a reception confirmation signal from the transmission destination control board. In this embodiment, when a transmission interrupt is set as will be described later, the serial communication circuit 505 sets the bit 6 of the status register A 705 to “1” and confirms reception when detecting the completion of transmission of transmission data. An interrupt request (referred to as an interrupt request at the time of transmission) is made to the CPU 56 assuming that the signal wait state has been entered. That is, in response to the interrupt acceptance input (IRQ input) of the CPU 56, a low level signal that is an interrupt request level is output. The low level signal is given to the IRQ input of the CPU 56 via an interrupt controller built in the game control microcomputer 560.

  Bit 5 (bit name “RDRF”) of status register A 705 stores a reception data full flag indicating that reception data is stored in reception data register 711 (reception data full). As shown in FIG. 26B, when “0” is stored in bit 5, it indicates that the reception data register 711 contains no reception data. When “1” is stored in bit 5, the value of the reception shift register 713 is transferred to the reception data register 711, and reception data is stored in the reception data register 711 (reception data Full).

  When the reception data is stored in the reception data register 711, the CPU 56 is ready to perform reception processing by reading the reception data from the reception data register 711. In this embodiment, when the serial communication circuit 505 detects that the reception data is full, the bit 5 of the status register A 705 is set to “1” and an interrupt request (interrupt request at reception) is made to the CPU 56 that reception processing is possible. Do).

  Bit 4 (bit name “IDLE”) of the status register A705 stores an idle line detection flag indicating that the reception circuit has detected an idle line. As shown in FIG. 26B, when “0” is stored in bit 4, it indicates that the receiving unit of the serial communication circuit 505 has not detected an idle line. When “1” is stored in bit 4, it indicates that the receiving unit of the serial communication circuit 505 has detected an idle line.

  Bit 3 (bit name “OR”) of the status register A 705 indicates that the reception shift register 713 has received the next data before the CPU 56 reads the reception data stored in the reception data register 711 (overload). An overrun flag indicating (run) is stored. As shown in FIG. 26B, when “0” is stored in bit 3, it indicates that the receiving circuit has not detected an overrun. When “1” is stored in bit 3, it indicates that the receiving circuit has detected an overrun.

  If an overrun occurs, the next received data is stored in the receiving shift register 713 before the received data in the received data register 711 is read, so that the received data is overwritten and the CPU 56 receives the received data. Cannot read correctly. Therefore, communication with each control board cannot be performed correctly, causing the game control microcomputer 560 to malfunction. In this embodiment, when detecting an overrun, the serial communication circuit 505 sets bit 3 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 assuming that an error has occurred during communication.

  Bit 2 (bit name “NF”) of status register A 705 stores a noise error flag indicating that noise has been detected in the received data. As shown in FIG. 26B, when “0” is stored in bit 2, it indicates that the receiving circuit is not detecting noise in the received data. Further, when “1” is stored in bit 2, it indicates that the receiving circuit has detected noise in the received data.

  For example, when detecting each bit of the received data, the serial communication circuit 505 detects “1” or “0” having a predetermined bit length by using the baud rate generated by the baud rate generation circuit 703. In this case, when the detected length of “1” or “0” is less than the predetermined bit length, the serial communication circuit 505 detects a noise error because noise has occurred in the received data. When a noise error occurs, there is a high possibility that correct received data cannot be received due to the noise, which causes the gaming control microcomputer 560 to malfunction. In this embodiment, when detecting a noise error, the serial communication circuit 505 sets bit 2 of the status register A 705 to “1” and makes an interrupt request to the CPU 56 that an error has occurred during communication.

  Bit 1 (bit name “FE”) of the status register A 705 indicates that it is detected that the position of the stop bit of the received data is “0” (originally, the stop bit is “1”) (framing error). A framing error flag is stored. As shown in FIG. 26B, when “0” is stored in bit 1, it indicates that the receiving circuit has not detected a framing error in the received data. When “1” is stored in bit 1, it indicates that the receiving circuit has detected a framing error.

  When a framing error occurs, it is in a state where the stop bit of the received data has not been correctly received, and therefore there is a high possibility that correct received data cannot be received, causing the gaming control microcomputer 560 to malfunction. In this embodiment, when the serial communication circuit 505 detects a framing error, it sets bit 1 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 that an error has occurred during communication.

  Bit 0 (bit name “PF”) of status register A 705 has a parity error flag indicating that the parity value obtained from the received data does not match the parity value included in the received data (parity error). Is stored. As shown in FIG. 26B, when “0” is stored in bit 0, it indicates that the receiving circuit has not detected a parity error in the received data. Further, when “1” is stored in bit 0, it indicates that the receiving circuit has detected a parity error.

  When a parity error occurs, each data bit or parity bit of the received data has not been correctly received, and therefore there is a high possibility that correct received data cannot be received, causing the gaming control microcomputer 560 to malfunction. . In this embodiment, when the serial communication circuit 505 detects a parity error, the serial communication circuit 505 sets bit 0 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 that an error has occurred during communication.

  FIG. 27A is an explanatory diagram showing an example of the status register B (SIST2) 706. The status register B 706 is a register for confirming the reception state (reception status) of the serial communication circuit 505. In this embodiment, the CPU 56 can confirm the reception status of the serial communication circuit 505 by confirming the value of the bit of the status register B 706. As shown in FIG. 27A, the status register B 706 is an 8-bit register, and the initial value is set to “0 (= 00h)”. In addition, bit 0 of status register B706 can only be read. Therefore, even if control is performed to write a value to bit 0 of the status register A705, it is invalidated. Further, bits 1 to 7 of the status register B706 cannot be written or read. Therefore, even if control is performed to write a value to bits 1 to 7 of the status register A 705, it is invalid, and all values read from bits 1 to 7 are “0 (= 0000000b)”.

  FIG. 27B is a diagram showing an example of status confirmation data stored in the status register B706. As shown in FIG. 27B, a reception active flag indicating that the reception circuit is receiving reception data (reception active) is stored in bit 0 (bit name “RAF”) of the status register B706. . As shown in FIG. 27B, when “0” is stored in bit 0, it indicates that the reception circuit is not receiving reception data. Further, when “1” is stored in bit 0, it indicates that the reception circuit is receiving reception data. When the serial communication circuit 505 detects the start bit, it sets the bit 0 of the status register B 706 to “1” on the assumption that reception of received data has started.

  FIG. 28A is an explanatory diagram illustrating an example of the control register C (SICL3) 709. The control register C709 is a register for setting whether to permit an interrupt request when a communication error occurs in the serial communication circuit 505. In this embodiment, by setting the value of each bit of the control register C709, it is set whether to permit or prohibit an interrupt request during communication from the serial communication circuit 505. In the control register C709, error interrupt request setting data indicating whether or not various interrupt requests at the time of a communication error are permitted is mainly set. In addition to the error interrupt request setting data, the control register C709 stores 9th bit data when the data length is set to 9 bits. Setting data for performing various settings of the serial communication circuit 505 is also set. As shown in FIG. 28A, the control register C709 is an 8-bit register, and the initial value is set to “0 (= 00h)”. Further, bits 0 to 3 and bits 6 and 7 of the control register C709 can be written and read. Further, bits 4 and 5 of control register C709 cannot be written or read. Therefore, even if a control for writing a value to bits 4 and 5 of the control register C709 is performed, it is invalid, and all the values read from bits 4 and 5 are “0 (= 00b)”.

  FIG. 28B is an explanatory diagram showing an example of error interrupt request setting data set in the control register C709. As shown in FIG. 28 (B), the bit 7 (bit name “R8”) of the control register C709 stores the 9th bit data of the received data when the data length is set to 9 bits. Further, bit 6 (bit name “T8”) of the control register C709 stores the ninth bit of transmission data when the data length is set to nine bits.

  In bit 3 (bit name “ORIE”) of the control register C709, setting data indicating whether or not to permit an overrun flag interrupt request, which is an interrupt request to be performed when an overrun is detected, is set. As shown in FIG. 28B, by setting bit 3 to “0”, the overrun flag interrupt request is set to be prohibited. Further, by setting bit 3 to “1”, the overrun flag interrupt request is set to be permitted.

  Bit 2 (bit name “NEIE”) of the control register C709 is set with setting data indicating whether or not to permit a noise error flag interrupt request, which is an interrupt request to be performed when a noise error is detected. As shown in FIG. 28B, by setting bit 2 to “0”, the noise error flag interrupt request is set to be prohibited. Also, by setting bit 2 to “1”, the noise error flag interrupt request is set to be permitted.

  Bit 1 (bit name “FEIE”) of the control register C709 is set with setting data indicating whether or not to permit a framing error flag interrupt request, which is an interrupt request to be performed when a framing error is detected. As shown in FIG. 28B, by setting bit 1 to “0”, the framing error flag interrupt request is set to be prohibited. Further, by setting bit 1 to “1”, the framing error flag interrupt request is set to be permitted.

  Bit 0 (bit name “PEIE”) of the control register C709 is set with setting data indicating whether or not to permit a parity error flag interrupt request which is an interrupt request to be performed when a parity error is detected. As shown in FIG. 28B, by setting bit 0 to “0”, the parity error flag interrupt request is set to be prohibited. Further, by setting bit 0 to “1”, the parity error flag interrupt request is set to be permitted.

  FIG. 29 is an explanatory diagram showing a data register (SIDA) included in the serial communication circuit 505. The data register 701 is a register that stores data transmitted and received by the serial communication circuit 505. As shown in FIG. 29, the data register is an 8-bit register, and the initial value is set to “0 (= 00h)”. Data register 701 is configured such that bits 0 to 7 can be written and read.

  In this embodiment, when the serial communication circuit 505 transmits transmission data, the data register is used as the transmission data register 710. When the data length is set to 9 bits, bit 6 of the data register and control register C709 is used as the transmission data register 710. In this case, bits 0 to 7 of the data register are used as bits 0 to 7 of the transmission data register 710, and bit 6 of the control register C709 is used as bit 8 of the transmission data register 710.

  Further, when the serial communication circuit 505 receives received data, the data register is used as the received data register 711. When the data length is set to 9 bits, bit 7 of the data register and control register C709 is used as the reception data register 711. In this case, bit 0 to bit 7 of the data register are used as bit 0 to bit 7 of the reception data register 711, and bit 7 of the control register C 709 is used as bit 8 of the reception data register 711.

  The interrupt control circuit 714 makes various interrupt requests to the CPU 56. In this embodiment, when the bit 6 (TCIE) of the control register B 708 is set to “1”, the interrupt control circuit 714 notifies the CPU 56 when transmission of transmission data to the transmission data register 710 is completed. In addition to outputting an interrupt signal, an interrupt request is made by setting bit 6 (TC) of status register A705 to “1”. Even when the interrupt prohibition is set (for example, when bit 6 (TCIE) of the control register B708 is set to “0”), the interrupt control circuit 714 completes transmission of transmission data. Then, bit 1 (TC) of status register A 705 is set to “1”, that is, the bit of control register B 708 is set regardless of whether the interrupt is enabled / disabled. It is assumed that setting the bit of the status register A 705) and outputting an interrupt signal to the CPU 56 makes an interrupt request to the CPU 56.

  In addition, when bit 5 (RIE) of the control register B 708 is set to “1”, the interrupt control circuit 714 enters a state where reception data is stored in the reception data register 711 (when reception data full is detected). ), An interrupt signal is output to the CPU 56, and an interrupt request is made by setting bit 5 (RDRF) of the status register A705 to “1”.

  The interrupt control circuit 714 outputs an interrupt signal to the CPU 56 when various communication errors occur when any one of the bits 0 to 3 of the control register C709 is set to “1”. Further, the interrupt control circuit 714 sets “1” to bits 0 to 3 of the status register A 705 according to the type of communication error. For example, when bit 3 (ORIE) of control register C709 is set to “1”, when an overrun is detected, an interrupt signal is output and bit 3 (OR) of status register A705 is set to “1”. To make an interrupt request. For example, when bit 2 (NEIE) of the control register C709 is set to “1”, when a noise error is detected, an interrupt signal is output and bit 2 (NF) of the status register A705 is set to “1”. An interrupt request is made by setting. Also, for example, when bit 1 (FEIE) of the control register C709 is set to “1”, if a framing error is detected and an interrupt request is made, “1” is set to bit 1 (FE) of the status register A705. Set. For example, when bit 0 (PEIE) of the control register C709 is set to “1”, when a parity error is detected, an interrupt signal is output and bit 0 (PF) of the status register A705 is set to “1”. An interrupt request is made by setting. When a plurality of communication errors are detected, the interrupt control circuit 714 outputs an interrupt signal based on the plurality of communication errors and sets the corresponding bits of the status register A 705 to “1”.

  The CPU 56 can specify the cause of the interrupt according to the state of each bit of a register (status register A 705 or the like) in which the status is set. Then, a program set from an address determined in advance according to the interrupt cause is executed.

  The transmission format / parity generation circuit 715 generates a data format of transmission data. In this embodiment, the transmission format / parity generation circuit 715 generates a data format by adding a start bit and a stop bit to the transmission data stored in the transmission data register 710 and transfers the data format to the transmission shift register 712. If bit 1 (PE) of control register A707 is set to “1” and the parity function is set to be used, the transmission format / parity generation circuit 715 adds a parity bit to the transmission data. Generate a data format.

  The reception format / parity check circuit 716 detects the data format of the reception data. In this embodiment, the reception format / parity check circuit 716 detects the start bit and the stop bit from the reception data stored in the reception shift register 713, detects the data portion included in the reception data, and receives the reception data register. Forward to 711. When bit 1 (PE) of the control register A707 is set to “1” and the parity function is set to be used, the reception format / parity check circuit 716 obtains the parity of the reception data and receives the reception data. It is detected whether or not it matches the parity included in.

  FIG. 30 is an explanatory diagram showing an example of an address map of a storage area in the game control microcomputer 560. As shown in FIG. 30, the area from address 0000h to 1FFFh in the storage area of the game control microcomputer 560 is allocated to the ROM 54. An area from addresses 7E00h to 7FFFh is allocated to the RAM 55. Further, the area from address FD00h to address FDFFh is allocated to a built-in register such as the random number maximum value setting register 535.

  As shown in FIG. 30, the area from address 0000h to 1FFFh allocated to the ROM 54 includes a user program area and a user program management area. A program (user program) 550 created in advance by a user (for example, a game machine designer) is stored in the user program area in the area of addresses 0000h to 1F7Fh. Further, data (user program execution data) necessary for the CPU 56 to execute the user program 550 is stored in the user program management area in the area of addresses 1F80h to 1FFFh. Of the areas 7E00h to 7FFFh allocated to the RAM 55, the areas 7E00h to 7EFFh are unused areas, and the areas 7F00h to 7FFFh are used as work areas.

  FIG. 31 is an explanatory diagram showing an example of an address map in the user program management area. As shown in FIG. 31, in the area of address 1F97h, an initial value changing method selected by the user among the initial value changing methods which are methods for changing the initial value input to the counter 521 is designated. The initial value change method setting data is stored. Further, in the areas 1F98h and 1F99h, RAM address data for specifying an address in the RAM 55 (designated RAM address) designated in advance by the user among addresses 7F00h to 7FFFh allocated to the RAM 55 is stored. The In this case, of the values indicating the designated RAM address, the lower value of the designated RAM address is stored in the 1F98h address, and the higher value of the designated RAM address is stored in the 1F99h address.

  FIG. 32 is an explanatory diagram of an example of initial value change method setting data. As shown in FIG. 32, the initial value change data is composed of 8-bit data. The initial value change data “00h” is data specifying that the initial value is not changed as the initial value change method. In this embodiment, when the initial value change data “00h” is set, the counter 521 of the random number circuit 503 updates the count value from a predetermined initial value “0” to a predetermined final value. Become. Further, the initial value change data “01h” is data specifying that the initial value input to the counter 521 is changed to a value based on an ID number for identifying the game control microcomputer 560 as an initial value change method. It is. In this embodiment, when the initial value change data “01h” is set, the initial value of the counter value updated by the counter 521 is changed from “0” to a value based on the ID number. The count value is updated from the initial value to a predetermined final value.

  The user program 550 stored in the user program area will be described. FIG. 33 is an explanatory diagram showing a configuration example of the user program 550. As shown in FIG. 33, in this embodiment, the user program 550 includes a random number circuit setting program 551 composed of a plurality of types of program modules, a display result determination program 552, a count value permutation change program 554, and a random program. A numerical value update program 555, a serial communication circuit setting program 556, and an interrupt priority setting program 557 are included.

  The random number circuit setting program 551 is a program for causing the random number circuit 503 to execute a random number circuit setting process for performing an initial setting for updating the random R value. That is, the CPU 56 functions as a random number circuit setting unit by executing processing according to the random number circuit setting program 551.

  FIG. 34 is an explanatory diagram showing a configuration example of the random number circuit setting program 551. As shown in FIG. 34, the random number circuit setting program 551 includes, as a plurality of types of program modules, a random number maximum value setting module 551a, a random number update method selection module 551b, a cycle setting module 551c, a random number circuit activation module 551d, An initial value changing module 551e and a random number circuit selecting module 551f are included.

  The random number maximum value setting module 551a is a program module for causing the random number circuit 503 to set the maximum value of random R preset by a user (for example, a game machine manufacturer). The CPU 56 executes processing according to the random number maximum value setting module 551a, thereby writing random number maximum value setting data for specifying the maximum value of the random R preset by the user in the random number maximum value setting register 535. By doing so, the CPU 56 sets the maximum value of the random R preset by the user in the random number circuit 503. For example, when “255” is set in advance as the maximum value of the random R by the user, the CPU 56 writes the random number maximum value setting data “00FFh” in the random number maximum value setting register 535 and the maximum value of the random R “255”. Is set in the random number circuit 503.

  The random number update method selection module 551b is a program module for causing the random number circuit 503 to set the random number update method (first random number update method or second random number update method) selected by the user. The CPU 56 writes the random number update method selection data “01b” or “10b” designating the random number update method selected by the user in the random number update method selection register 540 by executing the process according to the random number update method selection module 551b. By doing so, the CPU 56 sets the random number update method selected by the user in the random number circuit 503. Therefore, the game control microcomputer 560 has a function of selecting either the first random number update method or the second random number update method as the random number update method used by the random number circuit 503 for the random number update.

  The cycle setting module 551c is a program for causing the random number circuit 503 to set the cycle of the internal clock signal preset by the user (that is, the cycle in which the clock signal output circuit 524 outputs the clock signal to the selector 528 and the inverting circuit 532). It is a module. The CPU 56 writes the period setting data for designating the period of the internal clock signal set in advance by the user in the period setting register 537 by executing the process according to the period setting module 551c. By doing so, the CPU 56 sets the cycle of the internal clock signal preset by the user in the random number circuit 503. For example, when the cycle of the internal clock signal is set in advance as “system clock signal cycle × 128 × 16” by the user, the CPU 56 writes the cycle setting data “0Fh” in the cycle setting register 537 and sets the internal clock signal The period “system clock signal period × 128 × 16” is set in the random number circuit 503.

  The random number circuit activation module 551d is a program module for activating the random number circuit 503. The CPU 56 activates the random number circuit 503 by writing the random number circuit activation data “80h” into the random number circuit activation register 541 by executing processing according to the random number circuit activation module 551d.

  The initial value change module 551e is a program module for changing the initial value of the count value updated by the counter 521. The CPU 56 functions as an initial value changing unit by executing processing according to the initial value changing module 551e. The CPU 56 executes the initial value changing module 551e to change the initial value of the count value updated by the counter 521 by the initial value changing method selected by the user. By doing so, the game control microcomputer 560 has a function of selecting an initial value changing method.

  In this embodiment, when initial value change method setting data “01h” is stored in the area of address 1F97h in the user program management area, the CPU 56 sets the initial value of the count value for each game control microcomputer 560. The value is changed to a value calculated based on the assigned unique ID number.

  For example, the CPU 56 associates, in advance, a predetermined storage area of the ROM 54 (or the RAM 55) with an ID number of the game control microcomputer 560 and a calculated value obtained by performing a predetermined calculation based on the ID number. I remember it. In this case, for example, if the ID number of the game control microcomputer 560 is “100”, the calculated value “150” obtained by adding the predetermined value “50” to the ID number “100” is set in advance as the ID number. Are stored in association with each other. Further, for example, the calculated value “50” obtained by subtracting the predetermined value “50” from the ID number “100” is stored in advance in association with the ID number. Further, for example, only a predetermined value may be stored in advance in association with the ID number. Then, the CPU 56 may use a value “150” obtained by adding an ID number (for example, “100”) to a predetermined value (for example, “50”) stored in advance as an initial value of the count value. Further, the CPU 56 may use a value “50” obtained by subtracting a predetermined value (eg, “50”) stored in advance from the ID number (eg, “100”) as the initial value of the count value.

  When the initial value change method setting data “01h” is stored, the CPU 56 changes the initial value of the count value to the calculated value based on the ID number stored in advance. By doing so, the randomness of the random number generated by the random number circuit 503 can be further improved, and the initial value of the random number can be made difficult to recognize only by looking at the ID number of the game control microcomputer 560. . Therefore, it is possible to more reliably prevent the transition condition to the big hit state from being illegally established by an action such as generating a captured signal using a radio signal to the gaming machine, and improving security. Can be improved.

  For example, when initial value change method setting data “01h” is stored, the CPU 56 calculates the ID number of the game control microcomputer 560 and a predetermined value (for example, adds the predetermined value to the ID number). The initial value of the count value is changed to the calculated value obtained. In this case, for example, the CPU 56 may calculate a value that is randomly changed using a random number as an ID number, thereby randomly updating a value used for the calculation and obtaining an initial value. By doing so, the randomness of the random numbers generated by the random number circuit 503 can be further improved.

  The random number circuit selection module 551f is a program module for setting a random number circuit to be used when executing a timer interrupt process including a game control process from among the random number circuits 503 built in the game control microcomputer 560. The CPU 56 executes a process according to the random number circuit selection module 551f, so that any of the two random number circuits (12-bit random number circuit 503a and 16-bit random number circuit 503b) built in the game control microcomputer 560 is selected. Set whether to use when executing timer interrupt processing. For example, the CPU 56 uses a 12-bit random number circuit 503a or 16-bit as a random number circuit used when executing the timer interrupt process according to a predetermined set value (a value set in advance by the user) stored in a predetermined storage area of the ROM 54. The random number circuit 503b is set.

  Note that both the 12-bit random number circuit 503a and the 16-bit random number circuit 503b may be set as random number circuits used when the timer interrupt process is executed. In this case, for example, the CPU 56 may perform a jackpot determination based on a random number generated by the 12-bit random number circuit 503a and may perform a probability change determination based on the random number generated by the 16-bit random number circuit 503b. In this embodiment, the random value storage circuit 531 is present in each of the 12-bit random number circuit 503a and the 16-bit random number circuit 503b (that is, a random-value storage circuit that stores a random number for 12 bits and a 16-bit random-number storage circuit). A random value storage circuit for storing random numbers exists separately). When both the 12-bit random number circuit 503a and the 16-bit random number circuit 503b are set, the CPU 56 is provided in the RAM 55 with the random number read from the 12-bit random number circuit 503a and the random number read from the 16-bit random number circuit 503b. Stored in separate buffer areas. Therefore, even when the timing for reading a random number from the 12-bit random number circuit 503a and the timing for reading a random number from the 16-bit random number circuit 503b are the same, two different random numbers can be extracted and stored in different buffer areas.

  The random value update program 555 is a program for updating the value of the random R stored in the random value storage circuit 531 when the first random number update method is selected as the random number update method. The CPU 56 functions as a random value updating unit by executing processing according to the random value updating program 555. When the first random number update method is selected, the CPU 56 executes the random value update program 555 and writes the count value update data “01h” in the count value update register 538, whereby the count value is stored in the counter 521. And the value of the random R stored in the random value storage circuit 531 is updated. When the second random number update method is selected as the random number update method, the counter 521 is updated with the random number generation clock signal output from the clock signal output circuit 537, and the random value storage circuit 531 is updated. The value of random R stored in is updated.

  The display result determination program 552 is a program for determining whether or not the display result on the special symbol display 8 is a jackpot symbol. The game control microcomputer 560 (specifically, the CPU 56) functions as display result determination means by executing processing according to the display result determination program 552.

  In this embodiment, the game control microcomputer 560 (specifically, the CPU 56) establishes a condition (execution condition) for the game ball to win the variable winning ball device 15 and execute the variable display of the special symbol. In response to this, the processing is executed in accordance with the display result determination program 552. Then, the CPU 56 reads the updated random R value from the random value storage circuit 531 and determines whether or not the display result on the special symbol display 8 is a jackpot symbol.

  FIG. 35 is an explanatory diagram illustrating an operation in which the CPU 56 updates the random R value or reads the random R value when the first random number update method is selected. As shown in FIG. 35, when the first random number update method is selected, the CPU 56 writes the count value update data “01h” to the count value update register 538, thereby storing the random number value storage circuit 531. The value of R (eg “2”) is updated. Then, the CPU 56 receives the random R value from the random value storage circuit 531 in response to the fact that the game ball has won the variable winning ball device 15 and the condition (execution condition) for executing the variable symbol special display is established. (For example, “2”) is read out.

  When the random R value stored in the random value storage circuit 531 is further updated, an interval equal to or longer than the cycle of the system clock signal output from the clock circuit 501 has elapsed since the random R value was updated during the previous update. Sometimes, the count value update data “01h” must be written to the count value update register 538. This is because it is necessary to secure time for reading the updated random R value from the random value storage circuit 531.

  FIG. 36 is an explanatory diagram showing an operation in which the CPU 56 reads the value of the random R when the second random number update method is selected. As shown in FIG. 36, when the second random number update method is selected, the timer circuit 534 writes the random value fetch command “01h” in the random value fetch register 539, and the counter 521 outputs it. The count value (for example, “2”) is taken into the random value storage circuit 531 and the random R value stored in the random value storage circuit 531 is updated. Then, the CPU 56 reads the updated random R value (for example, “2”) from the random value storage circuit 531.

  Specifically, when the second random number update method is selected, the counter 521 updates the count value C using the input of the random number generation clock signal SI1 as a trigger. Thereafter, when the random value acquisition command “01h” is written in the random value acquisition register 539, the latch signal generation circuit 533 outputs the latch signal SL to the random value storage circuit 531. Then, the random value storage circuit 531 reads and stores the count value output from the counter 521 with the input of the latch signal SL as a trigger. Then, the CPU 56 reads the value of random R stored in the random value storage circuit 531.

  If the timer circuit 534 does not write the random number value acquisition command “01h” to the random number value acquisition register 539, even if the counter 521 updates the count value, the random value storage circuit 531 will not update the counter 521. Do not read numerical values. For example, the timer circuit 534 writes the random value take-in command “01h” into the random value take-in register 539, causes the count value “3” output from the counter 521 to be taken into the random value store circuit 531, and the random value store circuit 531. , The random R value “3” stored therein is updated. In this case, the count value output from the counter 521 is updated from “3” to “4” or “5” unless the timer circuit 534 writes the random number value acquisition command “01h” in the random number acquisition register 539 again. However, the random value stored in the random value storage circuit 531 is not updated, and the random value read from the random value storage circuit 531 remains “3”.

  The count value permutation change program 554 writes count value permutation change data “01h” to the count value permutation change register 536, and executes count value permutation change processing for changing the permutation of count values stored in the random value storage circuit 531. It is a program for. The game control microcomputer 560 (specifically, the CPU 56) functions as numerical data permutation changing means by executing processing according to the count value permutation changing program 554. The CPU 56 executes the count value permutation change program 554 and writes the count value permutation change data “01h” in the count value permutation change register 536, whereby the count value permutation change circuit 523 outputs and inputs to the random value storage circuit 531. The permutation of the count values to be changed.

  The serial communication circuit setting program 556 is a serial communication circuit setting process for performing initial settings for serial communication with a microcomputer (in this embodiment, a payout control microcomputer) mounted on each control board in the serial communication circuit 505. Is a program for executing That is, the game control microcomputer 560 (specifically, the CPU 56) functions as a serial communication circuit setting unit by executing processing according to the serial communication circuit setting program 556.

  The interrupt priority setting program 557 is a program for initially setting the priority of interrupt processing executed in response to an interrupt request from the serial communication circuit 505. That is, the game control microcomputer 560 (specifically, the CPU 56) functions as priority order initial setting means by executing processing according to the interrupt priority order setting program 556.

  Further, as shown in FIG. 37, the game control microcomputer 560 includes a special figure holding memory 570, a big hit determination table memory 571, a flag memory 572, and a start winning port switch timer memory 573. Specifically, these memories are formed in the ROM 54 or the RAM 55.

  In the special figure holding memory 570, the game ball wins the variable winning ball apparatus 15 and the execution condition for the variable symbol display is satisfied, but the variable display start condition is not yet satisfied (for example, the special symbol indicator 8 is a memory for storing pending data including the number of times the execution condition of variable display is satisfied (8 is still executing variable display). The special figure holding memory 570 includes four entries, and each entry includes a holding number and a random R read from the random value storage circuit 531 according to the winning order in the order in which the game balls win the variable winning ball device 15. A value is stored in association with each other. In addition, whenever the special symbol variable display on the special symbol display 8 is finished once or the big hit gaming state is finished, the variable display start condition based on the top information of the special symbol holding memory 570 is set. The variable display based on the top information of the special figure holding memory 570 is executed. In this case, when the condition for starting the variable display of special symbols is satisfied, the information registered in the second or lower place in the special figure holding memory 570 is moved up by one place. In addition, when a game ball newly wins the variable winning ball apparatus 15 during the variable display of the special symbol, the value of the random R read from the random value storage circuit 531 based on the new winning is the special R value. It is registered in the empty entry in the figure holding memory 570.

  The jackpot determination table memory 571 stores a plurality of jackpot determination tables used by the CPU 56 to determine whether or not the display result of the special symbol display 8 is a jackpot symbol. Specifically, the big hit determination table memory 571 stores a normal time big hit determination table used in a gaming state (referred to as a normal state) other than the probability variation state, as shown in FIG. The jackpot determination table memory 571 stores a probability change jackpot determination table used in the probability change state, as shown in FIG. Note that, when the jackpot determination is performed using the determination table shown in FIG. 38, the probability of determining the jackpot greatly varies depending on the random number maximum value set in the random number maximum value setting register 535. In this case, for example, if the set random number maximum value is too small, the difference in the probability of determining a big hit between the case where the normal big hit determination table is used and the case where the probability variation big hit determination table is used becomes small. As a result, the player's interest in the game is diminished. Therefore, a plurality of determination tables (a plurality of normal time big hit determination tables and a plurality of probability variation big hit determination tables) may be stored in the big hit determination table memory 571 in association with the random number circuit 503 and the maximum random number. . Then, the CPU 56 uses the determination table corresponding to the random number circuit 503 to be used and the random number maximum value among the determination tables stored in the jackpot determination table memory 571, according to the display result determination program 552, You may make it determine whether a display result is a jackpot symbol. By doing so, even if the type of random number circuit 503 to be used and the maximum random number value are different, it is possible to control so that the probability of determining a big hit is somewhat the same.

  In this embodiment, a 16-bit random number circuit 503b is used. That is, it is assumed that it is decided to use the 16-bit random number circuit 503b in the process of step S151. Therefore, the random R can take a value in a range that can be generated in 16 bits (range from 0 to 65535).

  In the flag memory 572, various flags used in the game control process for controlling the progress of the game are set. For example, in the flag memory 572, a probability change flag indicating that the gaming state is a probability change state and a big hit flag indicating that the game state is a big hit state are set.

  The start port switch timer memory 573 stores a timer value that is added or cleared in accordance with the winning detection signal SS output from the start port switch 14a.

  Next, the operation of the gaming machine will be described. FIG. 39 and FIG. 40 are flowcharts showing the main processing executed by the CPU 56 in response to the start of power supply to the gaming machine and the reset signal to the gaming control microcomputer 560 becoming high level. When the input level of the reset terminal to which the reset signal is input becomes a high level, the CPU 56 executes a security check process that is a process for confirming whether the contents of the program are valid, and then performs a main process after step S1. To start. In the main process, the CPU 56 first performs necessary initial settings.

  In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1). Next, an interrupt mode for maskable interrupts is set (step S2), and a stack pointer designation address is set for the stack pointer (step S3). In step S2, the address synthesized from the value (1 byte) of the specific register (I register) of the CPU 56 and the interrupt vector (1 byte: least significant bit 0) output from the built-in device indicates the interrupt address. Set to mode. When a maskable interrupt occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter in the stack.

  Next, the built-in device register is set (initialized) (step S4). By the processing in step S4, the CTC (counter / timer) and PIO (parallel input / output port), which are built-in devices (built-in peripheral circuits), are set (initialized).

  The game control microcomputer 560 used in this embodiment also incorporates an I / O port (PIO) and a timer / counter circuit (CTC) 504.

  Next, the RAM 55 is set in an accessible state (step S5), and the process proceeds to a clear signal check process.

  Next, the CPU 56 checks whether or not a clear signal is output from, for example, a clear switch 921 mounted on the power supply board 910 (step S7). If the clear signal is not output, check whether data protection processing of the backup RAM area (for example, power supply stop processing such as addition of parity data) was performed when power supply to the gaming machine was stopped (Step S8). In this embodiment, when power supply is stopped, a process for protecting data in the backup RAM area is performed. When it is confirmed that such power supply stop processing has been performed, the CPU 56 determines that the power supply stop processing has been performed, that is, the control state at the time of power supply stop is stored. . When it is confirmed that the power supply stop process is not performed, the CPU 56 executes an initialization process.

  Whether or not the power supply stop process has been performed is determined by the value of the backup monitoring timer stored in the backup RAM area in the power supply stop process corresponding to the execution of the power supply stop process (for example, 2). ). Note that such a confirmation method is an example. For example, a flag indicating that the power supply stop process has been executed is set in the backup flag area in the power supply stop process, and the flag is set in step S8. If it is confirmed that the power supply is stopped, it may be determined that the power supply stop process has been performed.

  If it is determined that the control state at the time of stopping power supply is stored, the CPU 56 performs data check (parity check in this example) in the backup RAM area (step S9). In this embodiment, clear data (00) is set in the checksum data area, and the checksum calculation start address is set in the pointer. Also, the number of checksum calculations corresponding to the number of data to be checksum is set. Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated. The calculation result is stored in the checksum data area, the pointer value is incremented by 1, and the checksum calculation count value is decremented by 1. The above processing is repeated until the value of the checksum calculation count becomes zero. When the value of the checksum calculation count becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area and uses the inverted data as a checksum.

  In the power supply stop process, a checksum is calculated by the same process as described above, and the checksum is stored in the backup RAM area. In step S9, the calculated checksum is compared with the stored checksum. When the power supply is stopped after an unexpected power failure or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area may be different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state when the power supply is stopped, the initialization process (the process of steps S10 to S14a) executed when the power is turned on, not when the power supply is stopped is stopped. Execute.

  If the check result is normal, the CPU 56 performs a game state restoration process for returning the internal state of the game control means and the control state of the electric component control means such as the sound / lamp control means to the state when the power supply is stopped. Specifically, the start address of the backup setting table stored in the ROM 54 is set as a pointer (step S91), and the contents of the backup setting table are sequentially set in the work area (area in the RAM 55) (step S92). ). The work area is backed up by a backup power source. In the backup setting table, initialization data for an area that may be initialized in the work area is set. As a result of the processing in steps S91 and S92, the saved contents of the work area that should not be initialized remain. The parts that should not be initialized include, for example, data indicating the gaming state before the power supply is stopped (special symbol process flag, etc.), the area where the output state of the output port is saved (output port buffer), unpaid prize balls This is the part where data indicating the number is set.

  Further, the CPU 56 sets the head address of the backup command transmission table stored in the ROM 54 as a pointer (step S93), and the power supply is restored to the sub board (sound / lamp control board 80b) according to the contents. Is executed to transmit a recovery command indicating (step S94). Further, a recovery command is transmitted to the payout control microcomputer 370 mounted on the payout control board 37 (step S95). Then, the process proceeds to step S15. In this embodiment, the recovery command is transmitted after the game state recovery process is executed. However, the game state recovery process may be executed after the recovery command is transmitted.

  Since the RAM clear process is not performed when the processes of steps S91 to S95 are executed, and the stored contents of the backup RAM area should have been saved, the execution state of the game control process is the state before the power supply is stopped. It will be restored to the state of.

  In the initialization process, the CPU 56 first performs a RAM clear process for clearing the contents of the RAM 55 (step S10). Note that the predetermined data may be left as it is without initializing the entire area of the RAM 55. Also, the initial address of the initialization setting table stored in the ROM 54 is set as a pointer (step S11), and the contents of the initialization setting table are sequentially set in the work area (step S12).

  Control states such as a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol buffer, a total prize ball number storage buffer, a special symbol process flag, an award ball flag, an out-of-ball flag, etc. An initial value is set in a flag for selectively performing processing according to the above.

  Further, the CPU 56 sets the start address of the initialization command transmission table stored in the ROM 54 as a pointer (step S13), and initializes the sub board (sound / lamp control board 80b) according to the contents. A process of transmitting the command to the sub-board is executed (step S14). As an initialization command, a command indicating an initial symbol displayed on the variable display device 9 can be used.

  Next, the CPU 56 transmits an initialization command to the payout control microcomputer 370 mounted on the payout control board 37 (step S14a).

  Further, the CPU 56 executes a random number circuit setting process for initially setting the random number circuits 503a and 503b (step S15). In this case, the CPU 56 performs setting according to the random number circuit setting program 551 to make the random number circuits 503a and 503b update the value of the random R.

  Further, the CPU 56 executes serial communication circuit setting processing for initial setting of the serial communication circuit 505 (step S15a). In this case, the CPU 56 performs processing according to the serial communication circuit setting program 556, thereby setting the serial communication circuit 505 to perform serial communication with the payout control microcomputer.

  When the serial communication circuit 505 is initialized, the CPU 56 initializes the priority of interrupt processing executed in response to the interrupt request from the serial communication circuit 505 (step S15b). In this case, the CPU 56 executes the process according to the interrupt priority setting program 557, thereby initializing the priority of the interrupt process.

  For example, the CPU 56 initializes the priority of interrupt processing according to a predetermined interrupt processing priority table including the default priority of each interrupt processing. FIG. 41 is an explanatory diagram of an example of an interrupt processing priority table. In this embodiment, the CPU 56 is initially configured to preferentially execute an interrupt process whose cause is a communication error in the serial communication circuit 505 in accordance with the interrupt process priority table shown in FIG. Set. In this case, for example, the CPU 56 sets an error-time interrupt priority execution flag indicating that interrupt processing whose interrupt cause is the occurrence of a communication error is preferentially executed. Note that the timer interrupt process for executing the game control process is also a target for setting the priority of the interrupt process.

  In addition, the default priority of each interrupt process can be changed by the user. For example, the CPU 56 stores specification information for specifying an interrupt process set by a user (for example, a game machine manufacturer) in a predetermined storage area of the ROM 54 in advance. Then, the CPU 56 sets the priority of interrupt processing according to the designation information stored in a predetermined storage area of the ROM 54.

  Then, the CPU 56 sets a CTC register built in the game control microcomputer 560 (specifically, the CPU 56) so that a timer interrupt is periodically taken every predetermined time (for example, 2 ms). Process is executed (step S16). That is, a value corresponding to, for example, 2 ms is set in a predetermined register (time constant register) as an initial value. In this embodiment, it is assumed that a timer interrupt is periodically taken every 2 ms.

  When the setting of the timer interrupt is completed, the CPU 56 repeatedly executes the display random number update process (step S18). The CPU 56 sets the interrupt disabled state when the display random number update process is executed (step S17), and sets the interrupt enabled state when the display random number update process is completed (step S19). Note that the display random number is a random number for determining the symbol displayed on the special symbol display 8, and the display random number update processing is to update the count value of the counter for generating the display random number. It is processing.

  Further, the CPU 56 may repeatedly update the count value of the counter for generating the display random number, and may repeatedly update the count value of the counter for generating the initial value random number. In that case, a game control process described later (the game control microcomputer controls itself a game device such as the variable display device 9, the variable winning ball device 15 and the ball payout device 97 provided in the game machine. In a process, or a process of transmitting a command signal to cause another microcomputer to control, also referred to as a gaming device control process), a process of incrementing the count value of the counter for generating an initial value random number is executed. The initial value random number is a random number for determining an initial value of a count value such as a big hit symbol determining random number, a probability variation determining random number, a counter for generating a normal symbol determining random number (determination random number generation counter), etc. (Software random number). In the game control process, the CPU 56 updates the initial value determination random number when the count value of the determination random number generation counter or the like is updated to a predetermined update final value (for example, when the count value makes one round). The value is set as an initial update value in the determination random number generation counter. As described above, when the predetermined initial value of the determination random number is set based on the initial value determination random number, the type of the specific gaming state (for example, the special symbol displayed on the special symbol display 8) In addition to symbols, it is possible to improve the randomness of the random number for determination used for determining the number of rounds in the jackpot game, whether or not to shift to the probable change state after the jackpot game is finished, and the like.

  Note that when the display random number update process is executed, the interrupt disabled state is executed because the display random number update process is also executed in the timer interrupt process described later. This is to avoid this. That is, if a timer interrupt is generated during the process of step S18 and the count value of the counter for generating the display random number is updated during the timer interrupt process, the continuity of the count value is impaired. There is a case. However, such an inconvenience does not occur if the interrupt is prohibited during the process of step S18.

  Also, a game clerk or the like can easily perform initialization processing by starting the power supply to the gaming machine (for example, turning on the power switch 914) while the clear switch 921 is turned on and the clear signal is output. Can be executed. That is, RAM clear or the like can be performed.

  Next, the random number circuit setting process (step S15) in the main process will be described. FIG. 42 is a flowchart showing the random number circuit setting process. In the random number circuit setting process, the CPU 56 executes the process according to the random number circuit selection module 551f included in the random number circuit setting program 551, and from among the random number circuits 503a and 503b built in the game control microcomputer 560, the game control process A random number circuit to be used at the time of execution of the timer interrupt process including is set (step S151). The designation information for designating the random number circuit 503 used when executing the timer interrupt process set by the user (for example, the manufacturer of the gaming machine) is stored in a predetermined storage area of the ROM 54 in advance. Then, the CPU 56 selects either the 12-bit random number circuit 503a or the 16-bit random number circuit 503b according to the designation information stored in the predetermined storage area of the ROM 54, and uses the selected random number circuit when executing the timer interrupt process. Set as a random number circuit. In this embodiment, a random number generated by the 16-bit random number circuit 503b is used as a random number used for the jackpot determination, but both the 12-bit random number circuit 503a and the 16-bit random number circuit 503b will be described.

  As described above, in step S151, whether or not each of a plurality of random number circuits (12-bit random number circuit 503a and 16-bit random number circuit 503b) having different predetermined ranges of numerical data that can be updated can be used is set. Therefore, it is possible to prevent unnecessary random numbers from being processed during the execution of the timer interrupt process, and the control burden on the game control microcomputer 560 (specifically, the CPU 56) can be reduced. For example, when the game control microcomputer 560 performs the game control process using only the random number generated by one of the two random number circuits 503a and 503b, the random number is read from the random circuit that is not used for the game control process. Processing or the like can be prevented, and the control burden on the game control microcomputer 560 can be reduced.

  When the CPU 56 sets the random number circuit 503 to be used in step S151, the counter 521 of the random number circuit which is set not to be used is stopped by stopping the operation of the counter 521 or the clock signal output circuit 524, for example. Do not update. Further, for example, the CPU 56 updates the count value C of the counter 521 of the random number circuit that is set not to use, but the CPU 56 does not output the output control signal SC and reads the random number from the random value storage circuit 531. You may control so that it may not come out. Further, for example, the CPU 56 prevents the random value fetch data “01h” from being written into the random value fetch register 539 of the random number circuit that is set not to be used, and the latch signal generation circuit 533 disturbs the latch signal SL. It may be controlled not to output to the numerical value storage circuit 531.

  As described above, by setting the random number circuit 503 to be used, by setting only the random number circuit 503 to be used, it is possible to appropriately set the range of the random number value to be generated. Further, it is possible to prevent unnecessary random numbers from being processed during the execution of the timer interrupt process, and the control burden on the game control microcomputer 560 (specifically, the CPU 56) can be reduced. For example, when a big hit determination is performed using a determination table including a distant value (for example, “1” and “100”) as a big hit determination value, the big hit is determined with a predetermined big hit probability (eg, 1/100). As a result, the number of types of determination values to be processed is smaller when the random number by the 12-bit random number circuit 503a is used than when the random number by the 16-bit random number circuit 503b is used, and the game control microcomputer 560 is used. The control burden is reduced.

  Further, the CPU 56 executes processing in accordance with the random number maximum value setting module 551a included in the random number circuit setting program 551, and generates random number maximum value setting data for designating a random number maximum value set in advance by the user as a random number maximum value setting register 535. (Step S152). By doing so, the random number maximum value of random R preset by the user is set in the random number circuit 503. When the 12-bit random number circuit 503a is set as the random number circuit used when the timer interrupt is executed, the CPU 56 sets the random number maximum value designating the random number maximum value (any value from “0” to “4095”). Data is written into the random number maximum value setting register 535 of the 12-bit random number circuit 503a. Further, when the 16-bit random number circuit 503b is set as the random number circuit used when the timer interrupt is executed, the CPU 56 sets the random number maximum value for designating the maximum random number value (any value from “0” to “65535”). Data is written into the random number maximum value setting register 535 of the 16-bit random number circuit 503b.

  When “0” to “255” are set as the random number maximum value, the random number maximum value is reset to a predetermined value in the random number maximum value resetting process described later. Even when control is performed to write a value greater than “256” as the random number maximum value, values “0” to “255” are set in the random number maximum value setting register 535 due to garbled data or the like. In the case where it is lost, the random number maximum value is reset to a predetermined value in the random number maximum value resetting process described later.

  As described above, since the maximum value of the random number to be generated is set in advance in the random number maximum value setting register 535 in step S152, a random number having a value larger than the range of random numbers used during execution of the timer interrupt process is generated. This can be prevented, and the processing load on the random number circuit 503 and the CPU 56 can be reduced.

  Further, the CPU 56 checks whether the random number maximum value set in the random number maximum value setting register 535 in step S152 is not less than a predetermined lower limit value. If the random number maximum value is not more than the lower limit value, the random number maximum value setting register The random number maximum value resetting process for resetting the random number maximum value set in 535 is executed (step S153).

  Further, the CPU 56 executes a process according to the initial value change module 551e included in the random number circuit setting program 551, and executes an initial value change process for changing the initial value of the count value updated by the counter 521 of the random number circuit 503 (step). S154).

  Further, the CPU 56 executes processing according to the random number update method selection module 551b included in the random number circuit setting program 551, and writes the random number update method selection data in the random number update method selection register 540 (step S155). By doing so, the random number update method of the random number circuit 503 is set. In this embodiment, the CPU 56 writes the random number update method selection data “10h” in the random number update method selection register 540. That is, in this embodiment, the second random number update method is set as the random number update method of the random number circuit 503.

  In addition, the CPU 56 executes processing according to the cycle setting module 551c included in the random number circuit setting program 551, and sets the cycle setting data (the reference clock signal by how many minutes) that specifies the cycle of the random number generation clock signal SI1 set in advance by the user. The data for setting whether to circulate) is written in the period setting register 537 (step S156). By doing so, the cycle of the random number generating clock signal SI1 preset by the user is set in the random number circuit 503.

  Further, the CPU 56 sets whether or not to update the initial value input to the counter 521 when the count value is updated to a predetermined final value by the counter 521 of the random number circuit 503 (step S157). When the count value is updated to a predetermined final value by the counter 521, a setting value indicating whether or not to update the initial value input to the counter 521 is set in advance by the user and stored in a predetermined area of the ROM 54. . Whether or not the CPU 56 updates the initial value input to the counter 521 when the counter 521 updates the count value to a predetermined final value in accordance with a predetermined set value stored in a predetermined storage area of the ROM 54. Set up. In this embodiment, when the CPU 56 determines in step S157 that the initial value input to the counter 521 is to be updated, the count value is updated to a predetermined final value (when a notification signal is input from the counter 521). An initial value update flag indicating that the initial value is updated is set.

  Instead of changing the initial value of the count value by the CPU 56, the initial value of the count value may be changed to a predetermined value on the random number circuit 503 side based on the update of the count value to the final value. For example, the random number circuit 503 includes an initial value update data register that stores initial value update data indicating that the initial value is updated, and an initial value change circuit that changes the initial value. Value update data is set in the initial value update data register. In this case, when the counter 521 updates the count value to the final value, the counter 521 outputs a notification signal to the initial value change circuit. Then, the initial value changing circuit checks whether or not initial value update data is set in the initial value update data register. When the initial value change circuit confirms that the initial value update data is set, the initial value change circuit changes the initial value of the count value to a predetermined value. Note that the initial value changing circuit may change the initial value of the count value whose permutation has been changed in the count value permutation changing process described later.

  Further, the CPU 56 sets whether or not to change the permutation of the count values updated by the counter 521 when the count value is updated to a predetermined final value by the counter 521 of the random number circuit 503 (step S158). When the counter 521 updates the count value to a predetermined final value, a setting value indicating whether or not to change the permutation of the count value output by the counter 521 is set in advance by the user and stored in a predetermined area of the ROM 54. ing. Then, the CPU 56 changes the permutation of the count values output by the counter 521 when the count value is updated by the counter 521 to a predetermined final value according to a predetermined set value stored in a predetermined storage area of the ROM 54. Set whether or not. In this embodiment, if the CPU 56 determines in step S158 that the permutation of count values output by the counter 521 is to be changed, the CPU 56 changes the permutation of count values when the count value is updated to a predetermined final value. The indicated count value permutation change flag is set. In this embodiment, the case where the count value permutation change flag is set in step S158 according to a predetermined set value will be described. The CPU 56 changes the permutation of the count values output by the counter 521 based on the count value permutation change flag being set in the count value permutation changing process described later.

  Instead of changing the permutation of count values under the control of the CPU 56, the permutation of count values may be changed on the random number circuit 503 side based on updating the count values up to the final value. For example, the random number circuit 503 includes a permutation change data register that stores permutation change data indicating that the permutation of count values is to be changed. In step S158, the CPU 56 sets the permutation change data in the permutation change data register. In this case, when the counter 521 updates the count value to the final value, the notification signal is output to the count value permutation change circuit 523, and the count value permutation change circuit 523 that has received the notification signal receives the permutation change data in the permutation change data register. Check whether it is set. When the count value permutation changing circuit 523 confirms that the permutation change data is set, it changes the permutation of the count values.

  Then, the CPU 56 executes processing according to the random number circuit activation module 551d included in the random number circuit setting program 551, and writes the random number circuit activation data “80h” in the random number circuit activation register 541 (step S159). By doing so, the CPU 56 activates the random number circuit 503.

  Next, the random number maximum value resetting process (step S153) in the random number circuit setting process will be described. FIG. 43 is a flowchart showing the random number maximum value resetting process. In the random number maximum value resetting process, the CPU 56 reads the random number maximum value set in the random number maximum value setting register 535 (step S153a). When the 12-bit random number circuit 503a is set as the random number circuit used when executing the timer interrupt process, the CPU 56 reads the random number maximum value set in the random number maximum value setting register 535 of the 12-bit random number circuit 503a. . Also, as in this embodiment, when the 16-bit random number circuit 503b is set as the random number circuit used when executing the timer interrupt process, the CPU 56 sets the random number maximum value setting register 535 of the 16-bit random number circuit 503b. Read the maximum random number.

  The CPU 56 determines whether or not the read random number maximum value is smaller than a predetermined lower limit value (step S153b). When the 12-bit random number circuit 503a is set, the maximum random number that can be set in the 12-bit random number circuit 503a is from “256” to “4095”. It is determined whether or not the maximum random number read from is smaller than the lower limit value “256”. When the 16-bit random number circuit 503b is set, the maximum random number that can be set in the 16-bit random number circuit 503b is from “256” to “65535”. It is determined whether the random number maximum value read from the register 535 is smaller than the lower limit “256”.

  When the read random number maximum value is smaller than the lower limit value, the CPU 56 resets the random number maximum value set in the random number maximum value setting register 535 to a predetermined value (step S153c). When the 12-bit random number circuit 503a is set, if it is determined that the random number maximum value read from the random number maximum value setting register 535 of the 12-bit random number circuit 503a is equal to or lower than the lower limit value “256”, the CPU 56 sets the random number maximum value. The random number maximum value set in the register 535 is reset to a predetermined value “4095”. When the 16-bit random number circuit 503b is set, if it is determined that the random number maximum value read from the random number maximum value setting register 535 of the 16-bit random number circuit 503b is smaller than the lower limit “256”, the CPU 56 sets the random number maximum value. The random number maximum value set in the register 535 is reset to a predetermined value “65535”.

  As described above, when the random number maximum value set in the random number maximum value setting register 535 is smaller than the predetermined lower limit value, the random number maximum value is reset to a predetermined value. Therefore, it is possible to prevent an excessively small value from being set as the maximum value of the random number due to a malfunction of the game control microcomputer 560 or an action such as generating a capture signal using a radio signal for the game machine. be able to. Therefore, it is possible to prevent a situation in which a random number having an excessively small value range from the minimum value to the maximum value is generated.

  In this embodiment, in step S152, random number maximum value setting data designating a random number maximum value preset by the user is written in the random number maximum value setting register 535. Even if the random number maximum value that should have been written for some reason has changed (becomes smaller than the predetermined lower limit value), the random number maximum value is never left smaller than the predetermined lower limit value. Further, the process of step S152 may not be executed. Even in this case, the random number maximum value is not left smaller than the predetermined lower limit value in the process of step S153.

  Next, the initial value changing process (step S154) in the random number circuit setting process will be described. FIG. 44 is a flowchart showing the initial value changing process. In the initial value changing process, the CPU 56 first reads the initial value changing method setting data stored in the area 1F97h in the user program execution data area, and specifies the initial value changing method selected by the user. In this case, the CPU 56 determines whether or not the value of the read initial value changing method setting data is “01h” (step S154a), thereby specifying the initial value changing method selected by the user.

  When the value of the initial value change method setting data is “01h”, the CPU 56 sets the initial value input to the counter 521 of the random number circuit 503 to a value set based on the ID number unique to the game control microcomputer 560. Change (step S154b). For example, the CPU 56 stores the ID number of the game control microcomputer 560 and the calculated value obtained by performing the predetermined calculation based on the ID number in association with each other in a predetermined storage area of the ROM 54 in advance. In step S154b, the CPU 56 changes the initial value of the count value to the calculated value based on the stored ID number. Further, for example, in step S154b, the CPU 56 calculates the ID number of the game control microcomputer 560 and a predetermined value (for example, the ID number (for example, “100”) to a predetermined value (for example, “100”). The initial value of the count value is set to the calculated value (for example, “200”). When the initial value input to the counter 521 is changed, the game control microcomputer 560 sets an initial value change flag indicating that the initial value of the count value has been changed (step S154c).

  When the CPU 56 changes the initial value input to the counter 521 in step S154b, the CPU 56 checks the value of the random number maximum value setting register 535 of the comparator 522 of the random number circuit 503, and the value set based on the ID number is determined. It is determined whether or not it is greater than the maximum random number. If it is determined that the value set based on the ID number is equal to or greater than the maximum random number, the CPU 56 does not change the initial value input to the counter 521 (for example, the initial value remains “0” and does not change). By doing so, it is possible to prevent a situation where the initial value of the count value is set to a value equal to or greater than the maximum random number.

  If the value of the initial value change method setting data is not “01h” in step S154a (that is, the value of the initial value change method setting data stored in the area 1F97h of the user program execution data area is “00h”). In the case), the CPU 56 does not change the initial value of the count value, ends the initial value changing process as it is, and proceeds to step S155.

  By executing the random number circuit setting process, various signals are input to the random number circuit 503 when the timer interrupt process including the game control process is performed, and various signals are generated in the random number circuit 503. FIG. 45 is a timing chart showing the timing at which each signal is input to the random number circuit 503 and the timing at which each signal is generated in the random number circuit 503.

  As shown in FIG. 45, the clock circuit 501 increases the signal level of the output terminal from a low level to a high level at predetermined intervals (timing T11, T21,... Shown in FIG. 45). A reference clock signal CLK (see FIG. 45A) is input to 503.

  The clock signal output circuit 524 divides the reference clock signal CLK supplied from the clock circuit 501 to generate a random number generation clock signal SI1 (see FIG. 45B). For example, the clock signal output circuit 524 raises the signal level of the output terminal from the low level to the high level at timings T11, T12,..., And changes the signal level from the high level to the low level at timings T21, T22,. To output a random number generating clock signal SI1.

  In the example shown in FIG. 45, for the sake of easy understanding, the clock signal output circuit 524 divides the reference clock signal CLK by 2 to generate the random number generating clock signal SI1. However, in the actual random number circuit, the period that can be set in the period setting register 537 is from “system clock signal period × 128 × 7” to “system clock signal period × 128 × 256”. Therefore, in an actual random number circuit, the clock signal output circuit 524 is set in the cycle setting register 537 in a range from “system clock signal cycle × 128 × 7” to “system clock signal cycle × 128 × 256”. The reference clock signal CLK is divided by a division ratio corresponding to the cycle setting data “07h” to “FFh” to generate a random number generating clock signal SI1. The random number generating clock signal SI 1 generated by the clock signal output circuit 524 is output to the selector 528 and the inverting circuit 532.

  In this embodiment, since the second random number update method is set in the random number circuit setting process, the second random number update method selection signal is input from the random number update method selection signal output circuit 527 to the selector 528. When the second random number update method selection signal output circuit 527 receives the second random number update method selection signal output circuit 527, the selector 528 selects the random number generation clock signal SI1 input from the clock signal output circuit 524 and outputs it to the counter 521. . The counter 521 updates the count value C and outputs it to the count value permutation change circuit 523 every time the rising edge of the random number generation clock signal SI1 supplied from the selector 528 is input.

  The inversion circuit 532 generates the inverted clock signal SI2 (see FIG. 45C) by inverting the signal level of the random number generation clock signal SI1 input from the clock signal output circuit 524. For example, the inverting circuit 532 lowers the signal level of the output terminal from the high level to the low level at timings T11, T12,..., And the signal level from the low level to the high level at timings T21, T22,. As a result, the inverted clock signal SI2 is output. Further, the inverted clock signal SI <b> 2 generated by the inverting circuit 532 is output to the latch signal generating circuit 533.

  When a predetermined time (for example, 3 milliseconds) elapses after the winning detection signal SS (see FIG. 45D) is input to the timer circuit 534, the latch signal generation circuit 533 receives a disturbance from the random value read signal output circuit 526. A numerical reading signal is input. For example, when the signal level of the output terminal of the random number read signal output circuit 526 rises from a low level to a high level, the random value read signal is input to the latch signal generation circuit 533. The latch signal generation circuit 533 inverts the random value read signal input from the random value read signal output circuit 526 in response to the input of the second random number update method selection signal from the random number update method selection signal output circuit 527. A latch signal SL (see FIG. 45E) is output in synchronization with the rising edge of the inverted clock signal SI2 supplied from 532.

  As described above, the random number circuit 503 updates the count value C at the timings T11, T12, T13... And outputs the latch signal SL at the timing T22 different from the timings T11, T12, T13. The random number value is stored in 531.

  Next, the serial communication circuit setting process (step S15a) in the main process will be described. FIG. 46 is a flowchart showing the serial communication circuit setting process. In the serial communication circuit setting process, the CPU 56 first executes the process according to the serial communication circuit setting program 556 to set the baud rate of the serial communication circuit 505 (step S1511). In this case, the CPU 56 writes a setting value corresponding to the baud rate to be set in the baud rate register 702 of the serial communication circuit 505. The designation information that designates the setting value set by the user (for example, the manufacturer of the gaming machine) is stored in a predetermined storage area of the ROM 54 in advance. Then, the CPU 56 writes the setting value in the baud rate register 702 according to the designation information stored in a predetermined storage area of the ROM 54. For example, when the baud rate set value “156” is set by the CPU 56, the baud rate “1201.92 bps” is generated by the baud rate generation circuit 703 using the equation (1) and the clock frequency “3 MHz”.

  Further, the CPU 56 sets a data format of data transmitted / received by the serial communication circuit 505 (step S1512). In this case, the CPU 56 sets the data length (8 bits or 9 bits) of the transmission / reception data and the presence / absence of the parity function by setting the value of each bit of the control register A707. For example, the designation information that designates the value of each bit of the control register A 707 set by the user (for example, the manufacturer of the gaming machine) is stored in a predetermined storage area of the ROM 54 in advance. Then, the CPU 56 sets the value of each bit of the control register A707 according to the designation information stored in a predetermined storage area of the ROM 54.

  Further, the CPU 56 sets whether to permit each interrupt request generated by the serial communication circuit 505 (step S1513). In this case, the CPU 56 sets whether or not to permit a transmission interrupt request and a reception interrupt request by setting the values of bits 5 and 6 of the control register B708. Further, the CPU 56 sets whether or not to permit each communication error interrupt request by setting the value of bits 0 to 3 of the control register C709. The designation information that designates the value of each bit of the control register B 708 and the control register C 709 set by the user (for example, the manufacturer of the gaming machine) is stored in a predetermined storage area of the ROM 54 in advance. Then, the CPU 56 sets the value of each bit of the control register B 708 and the control register C 709 according to the designation information stored in a predetermined storage area of the ROM 54.

  Next, the game control process will be described. FIG. 47 is a flowchart showing the timer interrupt process. When a timer interrupt occurs during execution of the main process, specifically, in a period in which the interrupt is permitted during the execution of the loop process of steps S17 to S19, the CPU 56 responds to the occurrence of the timer interrupt. The game control process is executed in the timer interrupt process activated by In the timer interrupt process, the CPU 56 first executes a power-off process for detecting whether or not a power-off signal is output (whether or not it is turned on) (step S20). In the power-off process, if the power-off signal is on, the CPU 56 saves execution state information indicating that data is stored in the RAM that is backed up by power, and also creates parity data to back up the power. Saved in the RAM.

  Next, detection signals of switches such as the gate switch 32a, the start port switch 14a, the count switch 23, and the winning port switches 29a, 30a, 33a, and 39a are input via the input driver circuit 58, and the state of these is determined ( Switch processing: step S21). Specifically, if the state of the input port for inputting the detection signal of each switch is ON, the value of the switch timer provided corresponding to each switch is incremented by one.

  Next, the CPU 56 checks whether or not the initial value is updated when the count value is updated to a predetermined final value in the random number circuit setting process (see step S157), and the random number circuit 503 is checked. The initial value input to the counter 521 is updated (initial value update process: step S22).

Next, a process of updating the count value of each counter for generating each determination random number used for game control is performed (step S23: determination random number update process). The random number for determination is a random number (software random number) for determining a jackpot symbol or the like. In this embodiment, as shown in FIG. 48, as software random numbers,
Random 1: Random symbol for determining a special symbol for generating a special symbol random 2: Random random symbol for determining a special symbol for generating a special symbol for generating a big jackpot 3: Random pattern for determining a special symbol Random pattern random number 4: random number for normal symbol determination for determining whether to generate a hit based on a normal symbol 5: random number for probability variation determination for determining whether to control the probability variation state Is used.

  In this embodiment, random numbers 2, 4, and 5 are determination random numbers, and random numbers 1 and 3 are display random numbers.

  The CPU 56 cyclically updates from a predetermined update initial value (for example, 0 for random 2) to a predetermined update final value (for example, 9 for random 2). Cyclic means that when the counter value exceeds the update final value, the counter is returned to the update initial value. The random R value stored in the random value storage circuit 531 is used as a big hit determination random number for determining whether or not to win.

  Further, in this embodiment, a big hit symbol is determined based on random 2 and whether or not to shift to a probable variation state based on random 5 is determined, but is shifted to a big hit symbol and a probable variation state based on one random number. It may be determined whether or not. For example, when only random 2 is used, if the value of random 2 is “7”, it is determined that the jackpot symbol is set to “7” and the state is shifted to the probability variation state. The design is determined according to a random value of 2 and is determined not to shift to the probability variation state. By performing such control, the data used by the CPU 56 can be reduced, and as a result, the burden on the CPU 56 can be reduced.

  In addition to the software random numbers illustrated in FIG. 48, other software random numbers may be used. For example, a random number for determining the number of rounds for determining the number of rounds in the jackpot game, a random number for determining the number of winning balls for determining the maximum number of winning balls for one round in the jackpot game, and each round in the jackpot game Alternatively, a random number for lottery of lottery for winning big hits for determining the number of winning balls for winning in the big winning opening in may be used. Further, the big hit symbol may be determined by one software random number, and the number of rounds may be determined by lottery. In addition, when it is decided to have a probable big hit, whether to play a normal probable big hit game with a normal number of rounds (for example, 15 rounds), or the number of rounds is small (for example, two rounds) and the round time is extremely short A software random number may be used to determine whether to play a so-called sudden probability change game. In this case, it is possible to determine whether to perform a normal probability variable big hit game or a sudden probability variable big hit game with one software random number, and to determine the big hit symbol.

  Further, the CPU 56 performs a process of updating the count value of the counter for generating the display random number (display random number update process: step S24).

  Next, the CPU 56 performs a count value permutation changing process for causing the count value permutation changing circuit 523 to change the permutation of the count values output by the counter 521 of the random number circuit 503 (step S25). In this embodiment, whether or not to execute the count value permutation change process is determined depending on whether or not the count value permutation change flag is set in step S158 of the random number circuit setting process. Then, the CPU 56 executes the count value permutation change process based on the fact that the count value permutation change flag is set.

  Further, the CPU 56 performs special symbol process processing (step S26). In the special symbol process control, a corresponding process is selected and executed according to a special symbol process flag for controlling the special symbol display 8 and the big prize opening in a predetermined order according to the gaming state. Then, the value of the special symbol process flag is updated during each process according to the gaming state. Further, normal symbol process processing is performed (step S27). In the normal symbol process, the corresponding process is selected and executed according to the normal symbol process flag for controlling the display state of the normal symbol display 10 and the open / close state of the variable winning ball apparatus 15 in a predetermined order. Then, the value of the normal symbol process flag is updated during each process according to the gaming state.

  Next, the CPU 56 performs a process of setting an effect control command related to the decorative symbol synchronized with the change of the special symbol in a predetermined area of the RAM 55 and sending the effect control command (effect control command control process: step S28). Note that the fact that the variation of the decorative symbol is synchronized with the variation of the special symbol means that the variation time (variable display period) is the same.

  Further, the CPU 56 performs information output processing for outputting data such as jackpot information, start information, probability variation information supplied to the hall management computer, for example (step S29).

  Further, the CPU 56 executes a prize ball process for setting the number of prize balls based on the detection signals from the prize opening switches 29a, 30a, 33a, 39a and the like (step S30). Specifically, a payout command command such as a prize ball number signal indicating the number of prize balls is output to the payout control board 37 in response to winning detection based on turning on the prize opening switches 29a, 30a, 33a, 39a, etc. . The payout control microcomputer 370 mounted on the payout control board 37 drives the ball payout device 97 in response to receiving a prize ball number signal indicating the number of prize balls.

  In addition, a test terminal process, which is a process for outputting a test signal for enabling the control state of the gaming machine to be confirmed outside the gaming machine, is executed (step S31). In this embodiment, a RAM area (output port buffer) corresponding to the output state of the output port is provided. However, the CPU 56 uses the contents related to the solenoid in the RAM area of the output port related to the solenoid as the output port. Output (step S32: output processing). Thereafter, the CPU 56 sets the interrupt permitted state (step S33) and ends the process.

  With the above control, in this embodiment, the game control process is started periodically (for example, every 2 ms). In this embodiment, the game control process is executed by the timer interrupt process. However, in the timer interrupt process, for example, only a flag indicating that an interrupt has occurred is set, and the game control process has a flag. It may be executed in the main process based on the setting.

  Further, for example, in the timer interrupt process, only the switch process (step S21), the effect control command control process (step S28), and the later-described interrupt count process (steps S3201a and S3202) are executed in the game control process. In addition, other processes in the game control process may be executed in the main process. In this case, the CPU 56 executes steps S22 to S27 and steps S29 to S33 of the game control process in the loop process from step S17 to step S19 in the main process. In the timer interrupt process, only the switch process (step S21) and the interrupt count process (steps S3201a and S3202) described later are executed in the game control process, and other processes in the game control process are performed. You may make it perform in a main process.

  Further, the processing of steps S21 to S30 (excluding step S29) corresponds to a game control process for controlling the progress of the game.

  Next, the initial value update process (step S22) in the timer interrupt process will be described. FIG. 49 is a flowchart showing the initial value update process. In the initial value update process, the CPU 56 checks the state of the notification signal indicating that the count value C output from the counter 521 of the random number circuit 503 has been updated to the final value (step S220). When it is detected that the notification signal is in the on state, the CPU 56 checks whether or not the initial value update flag is set (step S221). That is, in the random number circuit setting process, the CPU 56 checks whether or not the setting for updating the initial value is made when the count value is updated to a predetermined final value (see step S157).

  When the initial value update flag is set, the CPU 56 determines to update the initial value input to the counter 521 when the counter 521 of the random number circuit 503 updates the count value to a predetermined final value. When the initial value update flag is set, the CPU 56 checks whether or not the initial value change flag is set (step S222). That is, the CPU 56 determines whether or not the initial value of the count value is currently changed (that is, whether or not it is changed to a value based on the ID number of the game control microcomputer 560).

  When the initial value change flag is set (that is, when the initial value is currently changed based on the ID number of the game control microcomputer 560), the CPU 56 uses the initial value input to the counter 521 as the game control. The value based on the ID number of the microcomputer 560 is returned to the original value (for example, “1”) (step S223). Then, the CPU 56 resets the initial value change flag (step S224) and ends the initial value update process.

  If the initial value change flag is not set (that is, the initial value is not currently changed), the CPU 56 changes the initial value input to the counter 521 to a value based on the ID number of the game control microcomputer 560. (Step S225). In this case, for example, if the ID number of the game control microcomputer 560 is “100”, the initial value input to the counter 521 is calculated by adding a predetermined value “100” to the ID number “100”. Change to the value “200”. Further, for example, the initial value input to the counter 521 is changed to the calculated value “50” obtained by subtracting the predetermined value “50” from the ID number “100”. Then, the CPU 56 sets an initial value change flag (step S226) and ends the initial value update process.

  When both the 12-bit random number circuit 503a and the 16-bit random number circuit 503b are set, in step S225, the CPU 56 uses the random number read from one random number circuit (for example, the 12-bit random number circuit 503a) as a predetermined value as an ID number. The initial value input to the counter 521 may be obtained. Then, the CPU 56 may use a random number read from the other one (for example, a 16-bit random number circuit 503b) as a random number for determining the big hit.

  When the CPU 56 updates the initial value input to the counter 521 in step S225, the CPU 56 checks the value of the random number maximum value setting register 535 of the comparator 522 of the random number circuit 503, and the value set based on the ID number is obtained. It is determined whether or not it is greater than the maximum random number. If the CPU 56 determines that the value set based on the ID number is equal to or greater than the maximum random number, the CPU 56 does not update the initial value input to the counter 521 with a predetermined value (for example, updates with the predetermined value “0”). do not do). By doing so, it is possible to prevent a situation where the initial value of the count value is set to a value equal to or greater than the maximum random number.

  If it is determined in step S220 that the notification signal is in the OFF state, or if it is determined in step S221 that the initial value update flag is not set, the CPU 56 does not update the initial value input to the counter 521. Then, the initial value update process is finished as it is, and the routine goes to Step S24.

  Next, the count value permutation change process (step S25) in the timer interrupt process will be described. FIG. 50 is a flowchart showing the count value permutation change process. The CPU 56 performs a count value permutation change process by executing a process according to the count value permutation change program 554. In the count value permutation change process, the CPU 56 checks the state of the notification signal indicating that the count value C output from the counter 521 of the random number circuit 503 has been updated to the final value (step S241). When it is detected that the notification signal is in the on state, the CPU 56 checks whether or not the count value permutation change flag is set (step S242). That is, the CPU 56 determines whether or not the setting for changing the permutation of the count values updated by the counter 521 when the count values are updated to a predetermined final value has been made in the random number circuit setting process (see step S158). Check.

  When the count value permutation change flag is set, the CPU 56 determines that the permutation of the count values updated by the counter 521 is changed when the counter 521 of the random number circuit 503 updates the count value to a predetermined final value. Then, the game control microcomputer 560 writes the count value permutation change data “01h” in the count value permutation change register 536 (step S243). That is, the CPU 56 causes the count value permutation change circuit 523 to change the permutation of the count values C input to the random value storage circuit 531 by writing the count value permutation change data “01h”.

  As described above, in the count value permutation change process, when the random number is updated to a predetermined final value, the permutation of the count value updated by the counter 521 is changed, so that the randomness generated by the random number circuit 503 is more random. Can be improved.

  Next, the special symbol process (step S26) in the main process will be described. FIG. 51 is a flowchart showing an example of a special symbol process processing program executed by the CPU 56. If the start port switch 14a for detecting that a game ball has won the start winning port 14 provided in the game board 6 is turned on, that is, the start winning a prize in which the game ball wins the start winning port 14. Has occurred (step S311), the start-port switch passing process (step S312) is performed, and then any one of steps S300 to S307 is performed according to the internal state.

  Special symbol normal process (step S300): A state in which variable symbol special display can be started (for example, after the symbol variation has not been made in the special symbol indicator 8 and the previous symbol variation in the special symbol indicator 8 has ended) Wait until the predetermined period has passed and the game is not in big hit game. When the special symbol variable display can be started, the start winning memory number for the special symbol is confirmed. If the start winning memorization number is not 0, it is determined whether or not the result of variable symbol special display is a big hit based on the random R generated by the random number circuit 503 and stored in the special symbol holding memory 570. Then, the internal state (special symbol process flag) is updated to a value corresponding to step S301.

  Special symbol stop symbol setting process (step S301): A stop symbol after variable display of the special symbol is determined. Then, the internal state (special symbol process flag) is updated to a value corresponding to step S302.

  Variation pattern setting process (step S302): A variation pattern is determined, and the variation time in the variation pattern (variable display time: the time from the start of variable display until the display result is derived and displayed (stop display)) is a special symbol. It is determined to be a variable display variable time. In addition, a variation time timer that measures the variation time of the determined special symbol is started. Then, the internal state (special symbol process flag) is updated to a value corresponding to step S303.

  Special symbol variation processing (step S303): When a predetermined time (time indicated by the variation time timer in step S302) elapses, the internal state (special symbol process flag) is updated to a value corresponding to step S304.

  Special symbol stop process (step S304): A decorative symbol stop designation command for instructing stop of the decorative symbol is transmitted to the sound / lamp control board 80b. Moreover, the special symbol in the special symbol display 8 is stopped. If the special symbol stop symbol is a jackpot symbol, the internal state (special symbol process flag) is updated to a value corresponding to step S305. Otherwise, the internal state is updated to a value corresponding to step S300. Note that the decorative symbol stop designation command may not be transmitted. In this case, the sound / lamp control CPU 101b on the sound / lamp control board 80b sets the change time in the change time timer based on the change pattern command from the main board 31, and updates the change time timer. , The variation time of the decorative symbol is independently monitored, and when it is determined that the variation time has elapsed, the decorative symbol is stopped.

  Preliminary winning opening opening process (step S305): Control for opening the large winning opening is started. Specifically, a counter (for example, a counter that counts the number of game balls that have entered the big winning opening) and a flag (a flag used when detecting winning in the winning opening) are initialized, and the solenoid 21 is driven. Open the big prize opening. Also, the process timer sets the execution time of the big prize opening opening process and sets the big hit flag. Then, the internal state (special symbol process flag) is updated to a value corresponding to step S306.

  Processing for opening a special prize opening (step S306): control for sending a presentation control command for round display of the special prize opening to the sound / lamp control board 80b and conditions for closing the special prize opening (for example, a predetermined number (for example, a special prize opening) A process of confirming that 10) gaming balls have won) is performed. If the closing condition for the big prize opening is satisfied, the condition for continuation of the big hit gaming state is satisfied, and if there are still remaining rounds, the internal state is updated to a value corresponding to step S305. When all the rounds are finished, the internal state is updated to a value corresponding to step S307.

  Big hit end processing (step S307): Control is performed to cause the symbol control means to perform display control for notifying the player that the big hit gaming state has ended via the sound / lamp control means. Then, the internal state is updated to a value corresponding to step S300.

  FIG. 52 is an explanatory diagram showing an example of the contents of the effect control command sent to the sound / lamp control board 80b. In the example shown in FIG. 52, commands 8001 (H) to 8009 (H) are effect control commands (variation) for designating a variation pattern of decorative symbols variably displayed on the variable display device 9 in response to variable display of special symbols. Pattern command). The effect control command for designating the variation pattern is also a command for designating the variation start.

  The command 9000 (H) is an effect control command (probability variable jackpot designation command) for designating that the display result of the variable display device 9 is a probability variation jackpot symbol. Command 9001 (H) is an effect control command (ordinary jackpot designation command) for designating that the display result of variable display device 9 is an uncertain variable jackpot symbol (normal jackpot symbol). The command 9002 (H) is an effect control command (offset designation command) for designating that the display result of the variable display device 9 is an off symbol. For example, when a re-draw lottery effect is performed during a big hit, even if the probable big hit, the probable big hit symbol does not become a display result. You may send it.

  Since the commands 9000 (H) to 9002 (H) are effect control commands for designating the display result of the variable display device 9, the commands 9000 (H) to 9002 (H) are referred to as display result commands.

  The command A000 (H) is an effect control command (decorative symbol stop designation command) for designating stop of variable display (variation) of decorative symbols on the variable display device 9.

  The command BXXX (H) is an effect control command that is sent from the start of the big hit game to the end of the big hit game. The commands D000 (H) to EXXXX (H) are effect control commands relating to the display state of the variable display device 9 that is not related to the variation of the decorative symbols and the big hit game.

  Command B000 (H) is an effect control command (a jackpot start designation command) that designates that a jackpot game is to be started. The command B1XX (H) is an effect control command (display command when the big winning opening is opened) for designating display during the round during the big hit game. Note that the number of rounds displayed in “XX” is set. The command B2XX (H) is an effect control command (display command after opening the big prize opening) that specifies display after the round (display of the interval between rounds) during the big hit game. Note that the number of rounds displayed in “XX” is set. Command B300 (H) is an effect control command (a jackpot end designation command) for designating the end of the jackpot game.

  Command D000 (H) is an effect control command for designating a customer waiting demonstration. The command E000 (H) is an effect control command (probability change state designation command) that designates that the gaming state has become a probability change state (high probability state). Command E001 (H) is an effect control command (time-short state designation command) for designating that the gaming state has become a time-short state. The command E002 (H) is an effect control command (normal state designation command) that designates that the gaming state is neither the probability change state nor the short time state.

  When the sound / lamp control microcomputer 100b mounted on the sound / lamp control board 80b receives the above-described effect control command from the game control microcomputer 560 mounted on the main board 31, it is shown in FIG. The sound output control of the speaker 27 is executed according to the contents, and the lamp lighting control is executed. The sound / lamp control microcomputer 100b transmits the received effect control command to the symbol control microcomputer 100a, generates a command based on the received effect control command, and generates the generated command. It transmits to the computer 100a. When receiving the command from the sound / lamp control microcomputer 100b, the symbol control microcomputer 100a executes display control of the variable display device 9 in accordance with the received command.

  52. An effect control command other than the effect control command shown in FIG. 52 is also transmitted from the main board 31 to the sound / lamp control board 80b.

  FIG. 53 is a flowchart showing the start port switch passage processing (step S312). In the start port switch passing process, the CPU 56 of the game control microcomputer 560 sets the start winning memory number (or the starting winning memory number stored in the special figure holding memory 570) indicated by the start winning counter to 4 which is the maximum value. It is confirmed whether it has reached (step S3201). If the start winning memory number has not reached 4, the CPU 56 adds 1 to the value of the interrupt execution counter indicating the number of times the timer interrupt process has been executed (step S3201a). That is, the CPU 56 executes a process of counting the number of times that the timer interrupt process has been executed. In this embodiment, by executing step S3201a, the CPU 56 counts up an interrupt execution number counter indicating the number of times the timer interrupt process has been executed each time the timer interrupt process is executed. When the value of the interrupt execution number counter is incremented by 1, the CPU 56 checks whether or not the number of executions of the timer interrupt process indicated by the interrupt execution number counter has reached a predetermined number (for example, 3 times) (step) S3202). When the number of executions of the timer interrupt process reaches a predetermined number, in step S3207, the CPU 56 resets the interrupt execution number counter. Then, after the game ball has won the start winning opening 14, the CPU 56 checks whether or not the interrupt execution number counter has reached a predetermined number.

  The value set in advance as the predetermined number of times in step S3202 is determined as follows. As described above, the timer circuit 534 of the random number circuit 503 measures the time that the winning detection signal SS is continuously input from the start port switch 14a, and detects that the measurement time has reached a predetermined period, Write numerical value capture data “01h”. In this embodiment, a predetermined period (for example, 3 ms) measured by the timer circuit 534 is a period in which a predetermined number of timer interrupt processes are executed (for example, when the timer interrupt process every 2 ms is executed three times). The predetermined number of times (eg, 3 times) used in step S3202 is set so as to be shorter than 6 ms. By setting as such, it is possible to prevent the random number from being read again after the random number is read and before the random number value stored in the random value storage circuit 531 is updated. It is possible to prevent a random number having the same value as the random number read from the circuit 531 from being read again. The timer circuit 534 does not measure the input time of the winning detection signal SS, but the CPU 56 measures the input time of the winning detection signal SS and writes the random value fetch data “01h” to the random value fetch register 539. May be.

  When the number of executions of the timer interrupt processing has reached a predetermined number, the CPU 56 can output the output control signal SC to the random number value storage circuit 531 of the specified random number circuit 503 and read the random number value storage circuit 531 (enable). The state is controlled (step S3203).

  The CPU 56 reads the random R value stored as the random number value from the random value storage circuit 531 of the random number circuit 503 (step S3204). Further, the CPU 56 stores the read random R value in the storage area (special symbol determination buffer (special symbol holding memory 570)) corresponding to the value of the start winning memorized number (step S3205). When the CPU 56 stores the value of the random R in the storage area, the CPU 56 stops outputting the output control signal SC to the random value storage circuit 531 and controls the random value storage circuit 531 to be unreadable (disabled) ( Step S3206). Further, the CPU 56 resets the interrupt execution number counter (step S3207). Then, the CPU 56 sets the random R value stored in the predetermined buffer area at the head of the empty entry in the special figure reservation memory 570 (step S3208), and increments the count of the start prize counter by 1 to store the start prize memory. The number is increased by 1 (step S3209).

  Further, the CPU 56 extracts values of random numbers (software random numbers) such as a determination random number and a display random number, and stores them in a storage area (a special symbol determination buffer) corresponding to the value of the start winning memory number ( Step S3210). Note that extracting a random number means reading a count value from a counter for generating a random number and setting the read count value as a random value. In step S3210, random 1 to random 3 and random 5 are extracted from the random numbers shown in FIG.

  If the start winning memorized number has reached 4 which is the maximum value in step S3201, and if the number of executions of the timer interrupt process has not reached the predetermined number in step S3202, the start port switch passing process is terminated.

  As described above, the timer interrupt process has been executed a predetermined number of times in reading the random R from the random value storage circuit 531 in the starting port switch passing process (that is, continued while the timer interrupt process is executed a predetermined number of times). The random number is read from the random value storage circuit 531 on the condition that the winning detection signal SS is input). Therefore, it is possible to prevent the random number from being read again after the random number is read and before the value of the random number stored in the random value storage circuit 531 is updated. Further, it is possible to prevent a random number having the same value as the random number read from the previous random number value storage circuit 531 from being read again.

  Next, the special symbol normal process (step S300) in the special symbol process will be described. FIG. 54 is a flowchart showing special symbol normal processing. In the special symbol normal process, the CPU 56 of the game control microcomputer 560 can start the variation of the special symbol (for example, when the value of the special symbol process flag is a value indicating step S300), The value of the starting winning memory number (holding memory number) is confirmed (step S51). Specifically, the count value of the start winning storage counter is confirmed. The case where the value of the special symbol process flag is a value indicating step S300 is a case where the symbol is not changed in the variable display device 9 and is not in the big hit game. On the other hand, if the start winning memorized number is 0 in step S51, the CPU 56 ends the special symbol normal process as it is.

  If the starting winning memory number is not 0, each random value (random R, each determining random number, display random number) stored in the storage area (special symbol determining buffer) corresponding to the starting winning memory number = 1 is used. The value is read and stored in the random number buffer area of the RAM 55 (step S52), the value of the number of start winning memories is decreased by 1 (the value of the start winning memory counter is decreased by 1), and the contents of each storage area are shifted (step S53). ). That is, each random number value stored in the storage area corresponding to the start winning memory number = n (n = 2, 3, 4) is stored in the storage area corresponding to the starting winning memory number = n−1. Therefore, the order in which the random number values stored in the respective storage areas corresponding to the respective start winning memory numbers are extracted always matches the order of the starting winning memory numbers = 1, 2, 3, and 4. It has become. That is, in this example, the CPU 56 executes a process of shifting the contents of each storage area every time the variable display start condition is satisfied.

  Then, the value of the special symbol process flag is updated to a value corresponding to the special symbol stop symbol setting process (step S301) (step S54).

  FIG. 55 is a flowchart showing a special symbol stop symbol setting process. In the special symbol stop symbol setting process, the CPU 56 of the game control microcomputer 560 reads the jackpot determination random number (random R) from the random number buffer area (step S61) and executes the jackpot determination module (step S62). The jackpot determination module is a program that compares a jackpot determination value determined in advance with a jackpot determination random number and executes a process of determining a jackpot if they match. If it is determined to be a big hit (step S63), the process proceeds to step S81. Note that deciding whether to win or not is to decide whether or not to shift to the big win gaming state, but whether the special symbol display 8 and the variable display device 9 are to use the stop symbol as a big hit symbol? It also means deciding whether or not.

  In steps S62 and S63, if the probability change flag is not set, the CPU 56 determines that the gaming state is a normal state other than the probability change state, and determines whether or not the display result of the special symbol display 8 is a big hit symbol. As a table used for the determination, a normal jackpot determination table (see FIG. 38A) is used. Further, when the probability change flag is set, the CPU 56 determines that the gaming state is a probability change state, and as a table used to determine whether or not the display result of the special symbol display 8 is a jackpot symbol. A probability change big hit determination table (see FIG. 38B) is used. Then, it is determined whether or not the value of the jackpot determination random number matches the jackpot determination value set in the table (the value described in the left column in FIGS. 38A and 38B).

  If it is decided not to win, the CPU 56 reads out the design random number for detachment from the random number buffer area (step S64), and determines the design based on the random design decision random number (step S65). Then, the process proceeds to step S87. If it is decided to win, the process proceeds to step S81.

  In step S81, the CPU 56 sets a big hit flag. Then, the jackpot symbol determining random number is read from the random number buffer area (step S82), and the jackpot symbol is determined based on the jackpot symbol determining random number (step S83). Further, the probability variation determining random number is read out (step S84), and it is determined based on the probability variation determining random number whether or not the probability variation big hit is made (step S85). When the probability variation big hit is set, the probability variation big hit flag is set (step S86), and the process proceeds to step S87. If it is not a probable big hit, the process proceeds to step S87.

  In step S87, the value of the special symbol process flag is updated to a value corresponding to the variation pattern setting process (step S302).

  FIG. 56 is a flowchart showing the variation pattern setting process in the special symbol process. In the variation pattern setting process, the CPU 56 reads the variation pattern determination random number from the random number buffer area (step S101). Then, a variation pattern is selected from the variation pattern table (step S102). In step S102, data corresponding to a numerical value that matches the random number for determining the variation pattern is extracted from the variation pattern table, and the variation pattern indicated by the data is selected.

  Next, the CPU 56 transmits an effect control command (probability variation jackpot designation command) for specifying a probability variation jackpot if it is determined to be a probability variation jackpot, and if it is determined not to be a probability variation jackpot, a normal jackpot is determined. A designated production control command (usually big hit designation command) is transmitted, and if it is not determined to be a big hit, control is performed so as to send a deviation designated production control command (outage designation command) (step S103).

  Next, the CPU 56 performs control to transmit a variation pattern command corresponding to the variation pattern selected in step S102 to the effect control microcomputer 100 (step S104). Also, the special symbol change is started (step S105). Further, a value corresponding to the variation time of the variation pattern is set in the variation time timer formed in the RAM 55 (step S106). Then, the value of the special symbol process flag is updated to a value corresponding to the special symbol changing process (step S303) (step S107).

  FIG. 57 is a flowchart showing the special symbol changing process in the special symbol process. In the special symbol changing process, the CPU 56 decrements the variable time timer by 1 (step S121), and when the variable time timer times out (step S122), the value of the special symbol process flag corresponds to the special symbol stop process (step S304). The updated value is updated (step S123). If the variable time timer has not timed out, the process ends.

  Next, payout control signals and payout control commands transmitted and received between the main board 31 and the payout control board 37 will be described. In this embodiment, various payout control commands are transmitted and received between the serial communication circuit 505 built in the game control microcomputer 560 and the serial communication circuit 376 (see FIG. 59) built in the payout control microcomputer 370. Is done. Note that the serial communication circuit 376 built in the payout control microcomputer 370 has the same configuration as the serial communication circuit 505 built in the game control microcomputer 560, for example. FIG. 58 is an explanatory diagram showing an example of the contents of control signals (commands) transmitted and received between the game control microcomputer 560 and the payout control microcomputer 370.

  The award ball number signal is a command output for designating the number (0 to 15) of game balls for which a payout request is made. The prize ball ACK command “D2” is a command for notifying the game control means that the payout control means has received the prize ball number signal. The prize ball ACK command corresponds to a reception confirmation signal indicating that a prize ball number signal has been received. The initialization command is a command indicating that the game control microcomputer 560 has executed initialization processing when power supply is started. The recovery command is a command indicating that the game control microcomputer 560 has executed the game state recovery process when power supply is started.

  59 is a block diagram showing signal lines and the like used for transmission / reception of the command shown in FIG. As shown in FIG. 59, the winning ball number signal is output from the serial communication circuit 505 built in the game control microcomputer 560, and is built in the payout control microcomputer 370 via the output circuit 67 and the input circuit 373A. Input to the serial communication circuit 376. The prize ball ACK command is output from the serial communication circuit 376 built in the payout control microcomputer 370, and is sent to the serial communication circuit 505 built in the game control microcomputer 560 via the output circuit 373B and the input circuit 68. Entered.

  The initialization command and the recovery command are input to the payout control microcomputer 370 via the output circuit 67 and the input circuit 373A.

  In this embodiment, the initialization command and the recovery command are parallel data output from the output port of the game control microcomputer 560. When the game control microcomputer 560 outputs the initialization command and the recovery command, for example, the game control microcomputer 560 outputs the payout control INT signal (not shown) corresponding to the take-in signal together with the data of the initialization command and the recovery command (see FIG. 58). Output). The payout control INT signal is input to an interrupt terminal of the payout control microcomputer 370, and the payout control microcomputer 370 receives an initialization command and a recovery command by an interrupt process based on the input of the payout control INT signal.

  In this embodiment, the prize ball number signal and the prize ball ACK command are serial signals. However, the prize ball number signal and the prize ball ACK command may be transmitted and received as parallel data accompanied by a payout control INT signal, as in the case of the initialization command and the recovery command. In this case, the prize ball number signal and the prize ball ACK command are transmitted / received via the I / O port. Then, the payout control microcomputer 370 receives the award ball number signal by an interruption process based on the input of the payout control INT signal. In addition, the initialization command and the recovery command may be transmitted as serial signals.

  Further, in this embodiment, two-way communication using the prize ball number signal and the prize ball ACK command is executed for the payout control. However, the payout control board is not used from the main board 31 without using the prize ball ACK command. One-way communication with respect to 37 may be performed.

  FIG. 60 is a timing chart showing an example of how to output a payout control signal and a payout control command. As shown in FIG. 60, when the winning detection switch detects the winning of a game ball, the game control means (game controlling microcomputer 560) pays out a winning ball number signal corresponding to the number of winning balls paid out in accordance with the winning. This is transmitted to the control means (dispensing control microcomputer 370). Specifically, when the gaming control microcomputer 560 detects that a game ball has won a winning area provided in the gaming machine using a detection signal of a winning detection switch, the gaming control microcomputer 560 calculates a predetermined number of winning balls. It is added to the contents of the total number of winning balls stored in the backup RAM. When the content of the total winning ball number storage buffer becomes a non-zero value, a winning ball number signal corresponding to the number of winning balls paid out in accordance with winning is transmitted to the payout control microcomputer 370.

  In this embodiment, when a game ball is detected by the start port switch 14a, four prize balls are paid out, and when a game ball is detected by any of the prize port switches 33a, 39a, 29a, 30a. Seven prize balls are paid out, and when a game ball is detected by the count switch 23, 15 prize balls are paid out. Specifically, the game control microcomputer 560 determines that the prize ball number signal “04” indicates that when the number of prize balls is four, the number of prize balls is four, according to the number of prize balls to be paid out. When the number of prize balls is 7, a prize ball number signal “07” indicating that the number of prize balls is 7, and the number of prize balls is 15 when the number of prize balls is 15. A prize ball number signal “0F (H)” indicating 15 is transmitted. “H” indicates a hexadecimal number.

  When the transmission of the award ball number signal is completed, the serial communication circuit 505 of the game control microcomputer 560 makes a transmission interrupt request to the CPU 56 of the game control microcomputer 560 as shown in FIG. The game control microcomputer 560 (specifically, the CPU 56) recognizes that the transmission of the award ball number signal has been completed by the interrupt request at the time of transmission, and confirms reception from the payout control microcomputer 370. The signal is waiting.

  Upon confirming the reception of the prize ball number signal, the payout control microcomputer 370 stores the number of prize balls indicated in the received prize ball number signal in the planned prize ball payout total counter of the payout control microcomputer 370 (FIG. 78). Then, the payout control microcomputer 370 transmits the prize ball ACK command “D2” to the game control microcomputer 560. In this embodiment, the payout control microcomputer 370 sets a reception interrupt flag in the interrupt process based on the reception interrupt request from the serial communication circuit 376 built in the payout control microcomputer 370. If the reception interrupt flag is set in the main control communication process shown in FIG. 78, the number of prize balls is stored in the award ball payout scheduled total counter, but in the interruption process based on the reception interrupt request from the serial communication circuit 376. The number of prize balls may be stored in a prize ball payout total counter. In this case, when the serial communication circuit 376 built in the payout control microcomputer 370 receives the prize ball number signal, it makes an interrupt request at the time of reception to the CPU of the payout control microcomputer 370. Then, the CPU of the payout control microcomputer 370 stores an award ball number in the award ball payout scheduled total buffer by executing an interrupt process in response to an interrupt request from the serial communication circuit 376. The payout control microcomputer 370 stores the prize ball number indicated in the received prize ball number signal in the prize ball unpaid number counter in the interrupt process based on the interrupt request upon reception from the serial communication circuit 376. It may be.

  When the prize ball ACK command is received and the prize data ACK command is stored in the reception data register 711, the serial communication circuit 505 of the game control microcomputer 560, as shown in FIG. A reception interrupt request is made to the CPU 56 of 560. The CPU 56 recognizes that the serial communication circuit 505 has received the data by executing the interrupt process by the interrupt request at the time of reception, and receives a prize ball ACK command from the reception data register 711 in the prize ball ACK wait process described later. Read.

  FIG. 61 is a flowchart showing an example of the prize ball processing in step S30. In the prize ball process, the CPU 56 executes a prize ball number addition process (step S1201) and a prize ball control process (step S1202). Then, the contents of the port buffer formed in the RAM 55 are output to the output port (step S1203). The contents of the port buffer are updated in the prize ball control process.

  In the loop processing from step S17 to step S19 in the main processing, if there is an interrupt request from the serial communication circuit 505 while it is in the interrupt enabled state, the CPU 56 responds to the cause of the interrupt that the serial communication circuit 505 has made an interrupt request. Execute interrupt processing. FIG. 62 is a flowchart illustrating an example of interrupt processing that the serial communication circuit 505 performs in response to an interrupt request. FIG. 62A shows a communication error interrupt process executed by the game control microcomputer 560 (specifically, the CPU 56) when the serial communication circuit 505 makes an interrupt request with a communication error as an interrupt cause. FIG. 62 (b) shows a reception interrupt executed by the game control microcomputer 560 (specifically, the CPU 56) when an interrupt request is issued with the serial communication circuit 505 receiving the received data. It is processing. FIG. 62 (c) shows a transmission time executed by the game control microcomputer 560 (specifically, the CPU 56) when an interrupt request is issued with the cause of the interruption that the serial communication circuit 505 has completed transmission of transmission data. Interrupt processing.

  The CPU 56 determines whether or not it is initially set to execute one of the interrupt processes with priority. In this embodiment, the CPU 56 gives priority to an interrupt process that causes the occurrence of a communication error in the serial communication circuit 505 based on the fact that the communication error interrupt priority execution flag is set. And execute.

  When there is an interrupt request from the serial communication circuit 505, the CPU 56 checks each bit of the status register A 705 of the serial communication circuit 505 to identify the cause of the interrupt. In this case, the CPU 56 determines whether any interrupt process is preferentially executed. For example, the CPU 56 determines whether or not it is initially set to execute one of the interrupt processes with priority. In this embodiment, the CPU 56 gives priority to an interrupt process that causes the occurrence of a communication error in the serial communication circuit 505 based on the fact that the communication error interrupt priority execution flag is set. And execute.

  The CPU 56 preferentially checks bit 0 to bit 3 of the status register A705 based on the fact that the communication error interrupt priority execution flag is set, and identifies the cause of the interrupt. That is, the CPU 56 determines whether another interrupt cause (reception of received data has been received) as to whether or not an interrupt request has occurred due to the occurrence of a communication error (overrun, noise error, framing error, or parity error) in the serial communication circuit 505. Or, determination is performed with priority over transmission data transmission completion). If the CPU 56 determines that one or more of the bits 0 to 3 of the status register A 705 is “1”, the CPU 56 specifies that the cause of the interruption is that a communication error has occurred in the serial communication circuit 505. To do.

  If it is determined that the cause of the interruption is that a communication error has occurred in the serial communication circuit 505, the CPU 56 changes the communication error interrupt process shown in FIG. 62A to another interrupt process (FIGS. 62B and 62). It is executed with priority over the interrupt processing shown in (c). In this case, the CPU 56 sets a communication error flag indicating that a communication error has occurred in the serial communication circuit 505 (step S41).

  When a communication error is detected, the CPU 56 notifies the sound / lamp control microcomputer 100b that a communication error has occurred in the serial communication circuit 505. Display command). When the sound / lamp control microcomputer 100b receives the communication error display command, the sound / lamp control microcomputer 100b performs an effect using sound, display, light emitter, etc., and notifies that a communication error has occurred.

  In the communication error interrupt process, the CPU 56 controls to prohibit communication with the payout control board 37 or stops the transmission / reception function of the serial communication circuit 505.

  If the cause of the interruption is not the occurrence of a communication error in the serial communication circuit 505, the CPU 56 confirms bit 5 of the status register A. That is, the CPU 56 determines whether or not the cause of the interrupt is that the serial communication circuit 505 has received the received data. When determining that the bit 5 of the status register A is “1”, the CPU 56 specifies that the cause of the interruption is that the serial communication circuit 505 has received the reception data.

  When it is determined that the cause of the interruption is that the serial communication circuit 505 has received the received data, the CPU 56 executes a reception interrupt process shown in FIG. In this case, the CPU 56 sets a reception interrupt flag indicating that the serial communication circuit 505 is receiving reception data (step S42). The CPU 56 may not only set the reception interrupt flag but also read data from the reception data register 711 of the serial communication circuit 505 and store the read data in a predetermined area of the RAM 55.

  If the cause of the interruption is not a communication error occurring in the serial communication circuit 505, the CPU 56 confirms bit 6 of the status register A. That is, the CPU 56 determines whether or not the cause of the interrupt is that the serial communication circuit 505 has completed transmission of transmission data. When determining that the bit 6 of the status register A is “1”, the CPU 56 specifies that the cause of the interruption is that the serial communication circuit 505 has completed transmission of transmission data.

  If it is determined that the cause of the interruption is that the serial communication circuit 505 has completed transmission of transmission data, the CPU 56 executes a transmission interrupt process shown in FIG. In this case, the CPU 56 sets a transmission interrupt flag indicating that the serial communication circuit 505 has completed transmission of transmission data (step S43).

  FIG. 63 is an explanatory diagram showing an example of bit assignment of input ports in the game control means. As shown in FIG. 63, the detection signals of the count switch 23, the gate switch 32a, the winning port switches 33a, 39a, 29a, and 30a, and the start port switch 14a are input to bits 1 to 7 of the input port 0, respectively. . In addition, the power-off signal from the power supply monitoring board 910 and the detection signal (clear signal) of the clear switch 921 from the power supply board 910 are input to bits 0 and 1 of the input port 1, respectively.

  In the prize ball number adding process, a prize ball number table shown in FIG. 64 is used. The prize ball number table is set in the ROM 54. The number of processes (in this example, “6”) is set in the head address of the winning ball number table, and then the lower address of the switch-on buffer, and each switch of the winning opening that will pay out the winning ball by winning. The switch input bit determination value and the number of winning balls are sequentially set corresponding to each switch of the winning opening. The switch input bit determination value is a value corresponding to a bit to which a detection signal of each switch at the input port is input. The upper address of the switch-on buffer is a fixed value (for example, 7F (H)). In the prize ball number table, the same data is set in each of the lower addresses of the six switch-on buffers. In this embodiment, the addresses of the ROM 54 and the RAM 55 are designated by 16 bits.

  FIG. 65 is a flowchart showing the prize ball number adding process. In the winning ball number adding process, the CPU 56 sets the start address of the winning ball number table in the pointer (step S1211). Then, the data at the address pointed to by the pointer (in this case, the number of processes) is loaded (step S1212). Next, the upper address (8 bits) of the switch-on buffer is set in the upper 1 byte of the 2-byte check pointer (step S1213).

  Then, the value of the pointer is incremented by 1 (step S1214), the prize ball number table data pointed to by the pointer (in this case, the lower address of the switch-on buffer) is set in the lower 1 byte of the check pointer (step S1215), The pointer value is incremented by 1 (step S1216). Next, the address data pointed to by the check pointer, that is, the contents of the switch-on buffer is loaded into the register (step S1217), and the loaded contents and the data of the prize ball number table pointed to by the pointer (in this case, the switch input bit judgment value) ) And the logical product (step S1218). As a result, 7 bits other than the bit corresponding to the detection signal of the switch to be inspected become 0 in the register loaded with the contents of the switch-on buffer. Then, the pointer value is increased by 1 (step S1219).

  If the calculation result in step S1218 is 0, that is, if the detection signal of the switch to be inspected is on, the prize ball number table data pointed to by the pointer (in this case, the prize ball number) is used as the prize ball addition value. (Steps S1220 and S1221), and the prize-ball addition value is added to the contents of the 16-bit total prize-ball number storage buffer formed in the RAM 55 (step S1222). If a carry occurs as a result of the addition, the content of the total number of winning balls storage buffer is set to 65535 (= FFFF (H)) (steps S1223 and 1224).

  In step S1225, the number of processes is reduced by 1. If the number of processes is 0, the process ends. If the number of processes is not 0, the process returns to step S1214 (step S1226). In step S1220, if it is confirmed that the calculation result in step S1218 is 0, that is, the detection signal of the switch to be inspected is in an OFF state, the process proceeds to step S1225.

  FIG. 66 is a flowchart showing the prize ball control processing in step S1202. In the prize ball control process, after executing the prize ball abnormality detection process in step S1230, the CPU 56 executes any one of steps S1231 to S1235 according to the value of the prize ball process code.

  FIG. 67 is a flowchart showing a prize ball transmission waiting process (step S1231) executed when the value of the prize ball process code is zero. In the award ball transmission waiting process, the CPU 56 checks whether or not a communication error flag is set (step S1241). That is, the CPU 56 first checks whether or not a communication error has occurred in the serial communication circuit 505. If the communication error flag is set, the game control microcomputer 560 ends the process. That is, since a communication error has occurred in the serial communication circuit 505, the CPU 56 controls to prohibit communication with the payout control board 37.

  If the communication error flag is not set, the CPU 56 confirms the contents of the total winning ball number storage buffer (step S1242). If the value is 0, the process ends. If not, the value of the prize ball process code is set to 1 (step S1243), and the process ends.

  FIG. 68 is a flowchart showing a prize ball number signal transmission process (step S1232) executed when the value of the prize ball process code is 1. In the winning ball number signal transmission process, the CPU 56 checks whether or not a communication error flag is set (step S1251). That is, the CPU 56 first checks whether or not a communication error has occurred in the serial communication circuit 505. When the communication error flag is set, the CPU 56 ends the process as it is. That is, since a communication error has occurred in the serial communication circuit 505, the CPU 56 controls to prohibit communication with the payout control board 37.

  If the communication error flag is not set, the CPU 56 checks whether or not the content of the total prize ball number storage buffer is smaller than the prize ball command maximum value (“15” in this example) (step S1252). If the content of the total prize ball number storage buffer is equal to or greater than the prize ball command maximum value, the prize ball command maximum value is set in the prize ball number buffer (step S1253). If the content of the total prize ball number storage buffer is smaller than the maximum value of the prize ball command, the content of the total prize ball number storage buffer is set in the prize ball number buffer (step S1254).

  Thereafter, the CPU 56 writes the content of the prize ball number buffer as a prize ball number signal in the transmission data register 710 of the serial communication circuit 505 (step S1255), sets the value of the prize ball process code to 2 (step S1256), and performs processing. Exit. In this embodiment, the maximum value of the prize ball command is “15”. Accordingly, a prize ball number signal designating a payout number of “15” at the maximum is written in the transmission data register 710. Thereafter, the award ball number signal written in the transmission data register 710 is transferred to the transmission shift register 712 and transmitted from the transmission shift register 712 to the payout control microcomputer 370.

  FIG. 69 is a flowchart showing a prize ball transmission completion waiting process (step S1233) executed when the value of the prize ball process code is 2. In the award ball transmission completion waiting process, the CPU 56 checks whether or not a communication error flag is set (step S1261). That is, the CPU 56 first checks whether or not a communication error has occurred in the serial communication circuit 505. When the communication error flag is set, the CPU 56 ends the process as it is. That is, since a communication error has occurred in the serial communication circuit 505, the game control microcomputer 560 (specifically, the CPU 56) controls to prohibit communication with the payout control board 37.

  If the communication error flag is not set, the CPU 56 checks whether or not the transmission interrupt flag is set (step S1262). If the transmission interrupt flag is set, the CPU 56 proceeds to the process of step S1263. If the transmission interrupt flag is not set, the CPU 56 ends the process as it is. That is, the CPU 56 determines whether or not the serial communication circuit 505 has already completed transmission of the prize ball number signal written in the transmission data register 710 in the prize ball number signal transmission process, and has completed transmission of the prize ball number signal. If this is confirmed, the process after step S1263 is performed.

  If the transmission interrupt flag is set, the CPU 56 resets the transmission interrupt flag (step S1263). Then, the CPU 56 subtracts the contents of the prize ball number buffer (the number of prize balls paid out to the payout control means) from the contents of the total prize ball number storage buffer (step S1264).

  Here, the content of the prize ball number buffer is subtracted when the transmission of the prize ball number signal is completed, but when the prize ball ACK command is received from the payout control microcomputer 370, the content of the prize ball number buffer is changed. You may make it subtract. That is, the content of the winning ball number buffer may be subtracted immediately before or after step S1279 shown in FIG. Further, the content of the prize ball number buffer may be subtracted immediately before or after the prize ball number signal (prize ball number command) is transmitted to the payout control microcomputer 370. That is, the content of the winning ball number buffer may be subtracted immediately before or after step S1255 shown in FIG. Further, the present invention is not limited to the case illustrated here, and the content of the prize ball number buffer may be subtracted at another time related to the transmission of the prize ball number signal.

  Further, the CPU 56 sets an ACK reception completion determination time value in the prize ball timer (step S1266). Then, the value of the prize ball process code is set to 3 (step S1267), and the process is terminated. The ACK reception completion determination time value is a time value for monitoring whether or not a prize ball ACK command is received from the payout control means.

  FIG. 70 is a flowchart showing a prize ACK waiting process (step S1234) executed when the value of the prize ball process code is 3. In the award ball ACK waiting process, the CPU 56 checks whether or not a communication error flag is set (step S1271). That is, the CPU 56 first checks whether or not a communication error has occurred in the serial communication circuit 505. When the communication error flag is set, the CPU 56 ends the process as it is. That is, since a communication error has occurred in the serial communication circuit 505, the CPU 56 controls to prohibit communication with the payout control board 37.

  If the communication error flag is not set, the CPU 56 checks whether or not the reception interrupt flag is set (step S1272). That is, the CPU 56 checks whether or not the serial communication circuit 505 receives the received data and the received data register 711 stores the data. If the reception interrupt flag is set, the CPU 56 proceeds to the process of step S1273. On the other hand, if the reception interrupt flag is not set, the CPU 56 proceeds to the process of step S1275.

  If the reception interrupt flag is set, the CPU 56 reads data from the reception data register 711 of the serial communication circuit 505 (step S1273). Further, the CPU 56 determines whether or not the read data is a prize ball ACK command (whether or not it is a command “D2”) (step S1274).

  If the reception interrupt flag is not set in step S1272, or if the data read in step S1274 is not a prize ball ACK command, the CPU 56 still receives a prize ball ACK command from the payout control microcomputer 370. Judge that it is not in the state. In this case, the CPU 56 decrements the value of the prize ball timer by 1 (step S1275), and ends the process if the value is not 0 (step S1276). When the value of the prize ball timer reaches 0, it is determined that the payout control microcomputer 370 has not transmitted the prize ball ACK command, a retransmission flag is set (step S1277), and the value of the prize ball process code is set to 4. (Step S1278), and the process ends. When the value of the prize ball process code becomes 4, the prize ball retransmission process (step S1235) is executed. When the retransmission flag is set, a payout abnormality notification start command is transmitted to the sound / lamp control board 80b in the prize ball abnormality detection process (step S1230).

  In step S1274, when confirming that the data read from the reception data register 711 is a prize ball ACK command, the CPU 56 resets the reception interrupt flag (step S1279), and sets the value of the prize ball process code to 0. (Step S1280). If the retransmission flag is set because the communication is normally completed, the retransmission flag is reset (steps S1281 and S1282).

  Through the above processing, the game control means stores the total number of game balls as prize balls to be paid out based on the establishment of the payout condition in the total prize ball number storage buffer so as to be specified. The game control means also issues a payout command command (award ball number signal) for designating a payout number of a predetermined number of prize balls to the payout control means based on the number of prize balls stored in the total prize ball number storage buffer. Send. Here, the predetermined number is 15 if the number of prize balls stored in the total prize ball number storage buffer is 15 or more, and is stored in the total prize ball number storage buffer if it is less than 15. The number of prize balls. Then, when the prize ball number signal designating the prize ball payout is transmitted, a subtraction process is performed to subtract the payout number designated by the prize ball number signal from the prize ball number stored in the total prize ball number storage buffer. The payout control microcomputer 370 transmits a prize ball ACK command immediately after receiving the prize ball number signal, so that the communication regarding the prize ball number signal can be completed regardless of the prize ball payout from the ball payout device 97. The control microcomputer 560 (specifically, the CPU 56) can continuously transmit the next prize ball number signal before the prize ball payout of the number of payouts designated by the prize ball number signal is completed.

  In this embodiment, as a prize game medium number data storage means for storing the total number of prize game media to be paid out based on the establishment of the payout condition, a total prize ball number storage buffer for storing the total number itself is exemplified. However, the prize game medium number storage means for storing the total number of prize game media so as to be identifiable stores the number of prizes received in each prize area, or the number of prizes for each prize area (for example, the same number of prize balls) (for example, The number of winning holes 14 corresponding to the number of four winning balls, the number of winning holes 33, 39, 29, 30 corresponding to the number of seven winning balls, and the number of winning points corresponding to the number of 15 winning balls. And the number of winnings that have not yet been paid out). In that case, a prize ball number signal in which a number corresponding to the number of prize balls for each winning area is set is transmitted from the game control microcomputer 560 to the payout control microcomputer 370. Further, instead of transmitting a winning ball number signal indicating the number of winning balls, a payout command command indicating that there has been a winning or a winning number is transmitted from the game control microcomputer 560 to the payout control microcomputer 370. It may be.

  FIG. 71 is a flowchart showing a prize ball re-transmission process (step S1235) executed when the value of the prize ball process code is 4. The CPU 56 checks whether or not the communication error flag is set in the winning ball re-transmission process (step S1291). That is, the CPU 56 first checks whether or not a communication error has occurred in the serial communication circuit 505. When the communication error flag is set, the CPU 56 ends the process as it is. That is, since a communication error has occurred in the serial communication circuit 505, the game control microcomputer 560 (specifically, the CPU 56) controls to prohibit communication with the payout control board 37.

  If the communication error flag is not set, the CPU 56 rewrites the contents of the prize ball number buffer in the transmission data register 710 of the serial communication circuit 505 as a prize ball number signal (step S1292). Further, the CPU 56 sets the ACK reception completion determination time value again in the prize ball timer (step S1293). Then, the value of the prize ball process code is set to 3 (step S1294), and the process ends.

  Since the value of the prize ball process code is set to 3, the prize ball ACK waiting process is executed again. In the prize ball ACK waiting process to be executed again, if it is not detected that the prize ball ACK command has been received again, specifically, if the prize ball timer times out in step S1276, the prize ball again A retransmission process is executed. As described above, when the winning ball ACK command as the reception confirmation signal indicating that the payout amount data has been received cannot be received, the CPU 56 repeats the retransmission of the winning ball number signal until the winning ball ACK command can be received.

  FIG. 72 is a flowchart showing the prize ball abnormality detection process in step S230. In the prize ball abnormality detection process, when the CPU 56 detects that the retransmission flag has changed from the reset state to the set state, the CPU 56 uses the payout abnormality notification start command as an effect control command to the sound / lamp control board 80b (specifically, Performs transmission control to the sound / lamp control CPU 100b (steps S1301 and S1302). The CPU 56 does not transmit the payout abnormality notification start command after executing the prize ball retransmit processing, but transmits the payout abnormality notification start command to the sound / lamp control board 80b and then executes the prize ball retransmit processing. You may make it do.

  When transmitting the effect control command to the sound / lamp control microcomputer 100b, the CPU 56 pointers the address of a command transmission table (preliminarily set for each command in the ROM 54) according to the type of the effect control command. Set to. And the address of the command transmission table according to an effect control command is set to a pointer, and an effect control command is transmitted in an effect control command control process (step S28).

  Further, the CPU 56 detects that the re-transmission flag is changed from the set state to the reset state (therefore, it is detected only when the reset state is first set when the set state continues). Then, control is performed to transmit a payout abnormality notification end command to the sound / lamp control board 80b (specifically, to the sound / lamp control microcomputer 100b) (steps S1303 and S1304).

  In this embodiment, when the retransmission flag is reset, the CPU 56 transmits a payout abnormality notification end command in step S1304, but may be configured not to transmit it. In this case, the burden on the game control microcomputer 560 (specifically, the CPU 56) is reduced. In this case, the sound / lamp control microcomputer 100b is configured to terminate the payout abnormality notification independently after a predetermined time, for example.

  Next, the operation of the payout control microcomputer 370 will be described. FIG. 73 is a flowchart showing a main process executed by the payout control CPU 371 in the payout control microcomputer 370. The payout control microcomputer 370 also includes a serial communication circuit 376 (see FIG. 59) similar to the game control microcomputer 560. When power is turned on to the gaming machine and the input level of the reset terminal to which a reset signal is input becomes high, the payout control CPU 371 first performs necessary initial settings. That is, the payout control CPU 371 first sets the interruption prohibition (step S701). Next, the interrupt mode is set to interrupt mode 2 (step S702), and a stack pointer designation address is set to the stack pointer (step S703).

  The payout control CPU 371 initializes the built-in device register (step S704), and initializes CTC and PIO (step S705).

  In this embodiment, one channel of the built-in CTC is used in the timer mode. Accordingly, in the built-in device register setting process in step S704 and the process in step S705, register setting for setting the channel to be used to timer mode, register setting for permitting interrupt generation, and setting an interrupt vector. The register is set.

  The interrupt vector set for the channel set to the timer mode (channel 3 in this embodiment) corresponds to the start address of the timer interrupt process. Specifically, the start address of the timer interrupt process is specified by the value set in the I register and the interrupt vector. In the timer interruption process, a payout control process for controlling the payout means (including at least a process of driving the ball payout device 97 in accordance with a command signal relating to award ball payout from the main board, and a ball payout device 97 in response to a ball lending request. A process for driving the above may be included).

  In this embodiment, the interruption mode 2 is also set in the payout control microcomputer 370. Therefore, an interrupt process based on counting up the built-in CTC can be used. Also, an interrupt processing start address can be set according to the interrupt vector sent by the CTC.

  An interrupt based on CTC channel 3 (CH3) count-up is an interrupt that occurs when the internal clock (system clock) of the payout control CPU 371 is counted down and the register value becomes “0”. Used as Specifically, a clock obtained by dividing the operation clock of the payout control CPU 371 is supplied to the CTC, the register value is subtracted by the input of the clock, and when the register value becomes 0, a timer interrupt occurs.

  Further, the payout control CPU 371 sets the RAM in an accessible state (step S706).

  Next, it is confirmed whether or not data protection processing for the backup RAM area (for example, processing for stopping power supply such as addition of parity data) has been performed when power supply to the gaming machine is stopped (step S707). Whether or not the protection process has been performed depends on whether the value of the backup monitoring timer stored in the backup RAM area in the power supply stop process corresponds to the execution of the data protection process in the backup RAM area (for example, 10) It is confirmed by whether or not. Note that such a confirmation method is merely an example. For example, a flag indicating that data protection processing has been executed is set in the backup flag area in the power supply stop processing, and the flag is set in step S707. If it is confirmed that there is a backup, it may be determined that there is a backup.

  If it is determined that there is a backup, the payout control CPU 371 performs a data check (parity check in this example) in the backup RAM area (step S708). In this embodiment, clear data (00) is set in the checksum data area, and the checksum calculation start address is set in the pointer. Also, the number of checksum calculations corresponding to the number of data to be checksum is set. Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated. The calculation result is stored in the checksum data area, the pointer value is incremented by 1, and the checksum calculation count value is decremented by 1. The above processing is repeated until the value of the checksum calculation count becomes zero. When the value of the checksum calculation count becomes 0, the payout control CPU 371 inverts the value of each bit of the contents of the checksum data area and uses the inverted data as the checksum.

  In the power supply stop process, a checksum is calculated by the same process as described above, and the checksum is stored in the backup RAM area. In step S710, the calculated checksum is compared with the stored checksum. When the power supply is stopped after an unexpected power failure or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area is different from the data when the power supply is stopped. In such a case, the internal state cannot be returned to the state at the time of power supply stop, so the payout control state recovery processing is not executed, and the initialization processing (steps S715 and S716) is executed. The stored contents of the RAM are initialized by the initialization process, and the payout control process is started from the initial state.

  If the check result is normal, the data in the backup RAM area has been saved. Therefore, the payout control CPU 371 performs payout control state recovery processing. Specifically, a value at the time of restoration is set in the work area of the RAM (step S709). Setting the value at the time of restoration is a process of setting an initial value (for example, 0) in a non-backup area included in the RAM, for example. Then, the backup RAM area in the RAM is not cleared. Therefore, the execution state of the payout control process is restored to the state before the power supply is stopped. In this embodiment, since the entire area of the RAM is backed up, the processing in step S709 may be omitted.

  Also, the payout control CPU 371 sets a payout stop flag indicating that the game ball payout process is prohibited (step S711). Further, a predetermined value (a value corresponding to the time until the reset timing of the payout stop flag) is set in the monitoring timer for determining the reset timing of the payout stop flag (step S712). Then, control goes to a step S717.

  In the initialization process, the payout control CPU 371 first performs a RAM clear process for clearing the contents of the RAM (step S715). Also, initial values are set in the RAM area flag, counter (work area), and the like (step S716).

  The payout control CPU 371 includes a CTC register built in the payout control microcomputer 370 (specifically, the payout control CPU 371) so that a timer interrupt is periodically taken every predetermined time (for example, 2 ms). A timer interrupt setting process for setting is performed (step S717). In this embodiment, it is assumed that a timer interrupt is periodically taken every 2 ms.

  Since the interruption is prohibited in step S701 of the initial setting process, the payout control CPU 371 sets the interruption permitted state (step S718). Thereafter, a loop process for monitoring the occurrence of a timer interrupt is entered.

  In the loop process, the payout control CPU 371 executes a power-off process for monitoring whether or not a power-off signal is output (step S719). The power-off process is the same process as the power-off process executed by the CPU 56 of the game control microcomputer 560. That is, if the power-off signal is on, execution state information indicating that data is stored is stored in the power-backed-up RAM, and parity data is created and stored in the power-backed-up RAM. To do. By executing such processing, it is ensured that the value of the award ball unpaid number counter is stored in the power-backed RAM.

  As described above, the built-in CTC of the payout control CPU 371 is set to repeatedly generate a timer interrupt. When a timer interrupt occurs, the payout control CPU 371 executes a timer interrupt process after step S752. The payout control CPU 371 performs a process of initializing the serial communication circuit 376 between the process of step S715 and the process of step S716, for example, but is omitted from FIG. The processing for initial setting of the serial communication circuit 376 is the same as the serial communication circuit setting processing executed by the CPU 56 in step S15a.

  FIG. 74 is a flowchart showing an example of timer interrupt processing executed by the payout control CPU 371. In the timer interrupt process, the payout control CPU 371 executes a payout control process after step S752.

  In the payout control process, the payout control CPU 371 performs an input determination process (step S752). The input determination process is a process of detecting the state of a switch or the like that detects a game ball and reflecting the detection result in a predetermined 1 byte of RAM (referred to as an input state flag).

  Next, the payout control CPU 371 executes a payout motor control process (step S753). In the payout motor control process, when the payout motor 289 is to be driven, a process for outputting the patterns of the payout motors φ1 to φ4 to the output port is performed.

  Further, the payout control CPU 371 executes a prepaid card unit control process for communicating with the card unit 50 (step S754). Next, the payout control CPU 371 executes main control communication processing for communicating with the game control microcomputer 560 of the main board 31 (step S755). Further, a prize ball lending control process for performing a control for paying out a lending ball in response to a ball lending request from the card unit 50 and performing a control for paying out the number of award balls indicated by a prize ball number signal from the main board. Is executed (step S756).

  Then, the payout control CPU 371 executes error processing for detecting various errors (step S757). Further, an information output process for outputting prize ball information and ball lending information output to the outside of the gaming machine is executed (step S758). Further, a predetermined display is performed on the error display LED 374 according to the result of the error processing and the like, and a display control process for lighting the prize ball LED and the ball break LED is executed (step S759).

  In this embodiment, a RAM area (output port buffer) corresponding to the output state of the output port is provided, but the payout control CPU 371 outputs the output port buffer to the output port (step S760). : Output processing). The contents of the output port buffer are the payout motor control process (step S753), the prepaid card control process (step S754), the main control communication process (step S755), the information output process (step S758), and the display control process (step S759). Updated.

  Further, the payout control CPU 371 executes a payout stop flag control process (step S761) for resetting the payout stop flag. Thereafter, the payout control CPU 371 sets the interrupt permitted state (step S762) and ends the process.

  Also, the payout control microcomputer 370 (specifically, the payout control CPU 371), like the game control microcomputer 560 (specifically, the CPU 56), outputs from the serial communication circuit 376 while the interrupt is permitted. When there is an interrupt request, the serial communication circuit 376 executes an interrupt process according to the cause of the interrupt request. In this embodiment, when the CPU 371 for payout control specifies that the interrupt cause is that the serial communication circuit 376 has received the received data, the interrupt processing at the time of reception is performed according to the same processing as shown in FIG. Execute. In this case, the payout control CPU 371 sets a reception interrupt flag indicating that the serial communication circuit 376 is receiving reception data. As in the case of the CPU 56, the payout control CPU 371 not only sets the reception interrupt flag but also reads data from the reception data register of the serial communication circuit 376 and stores the read data in a predetermined area of the RAM. You may make it do.

  FIG. 75 is a flowchart showing a payout control INT signal interrupt process based on the payout control INT signal. In the payout control INT signal interruption process, the payout control CPU 371 inputs received data from an input port assigned to input a command from the game control microcomputer 560 (step S751). If the input received data is initialization command data, an initialization command reception flag indicating that the initialization command has been received is set (steps S752 and S753). If the input received data is a recovery command data, a recovery command reception flag indicating that the recovery command has been received is set (steps S754 and S755). Thereafter, the payout control CPU 371 sets the interrupt permitted state (step S756) and ends the process.

  FIG. 76 is a flowchart showing the payout stop flag control process. In the payout stop flag control process, the payout control CPU 371 decrements the value of the monitoring timer by 1 (step S741). When the value of the monitoring timer becomes 0, that is, when the monitoring timer times out, the payout stop flag is reset (steps S742 and S743). As the payout stop flag is reset, the game ball is allowed to be paid out. Further, the payout control CPU 371 sets an initialization prohibition flag (step S744).

  If the monitoring timer has not timed out, the payout control CPU 371 checks whether an initialization command has been received (step S746) on condition that the initialization prohibition flag is not set (step S745). . When the initialization command is received, a RAM clear process for clearing the contents of the RAM is performed (step S747). Also, initial values are set in the RAM area flag, counter (work area), and the like (step S747). Since the contents of the RAM are cleared, when the payout stop flag is set, the payout stop flag is reset.

  In this embodiment, the payout control process is stopped when the execution state of the payout control process is restored to the state before the power supply stop according to the storage contents of the RAM backup area being saved when the power supply is started. The flag is set, and the game ball is prohibited from being paid out. The game control microcomputer 560 determines whether the execution state of the game control process is in accordance with the stored contents of the backup area of the RAM being stored on the condition that the clear switch 921 is not pressed when power supply is started. When the power supply is restored to the state before the stop of the power supply, the initialization command is not output (the process proceeds to step S15 after executing the processing of steps S91 to S95 in FIG. 40).

  Conversely, when the clear switch 921 is pressed, the game control microcomputer 560 outputs an initialization command (see step S14a in FIG. 40).

  Upon receiving the initialization command, the payout control microcomputer 370 immediately executes initialization processing (steps S747 and S748). Therefore, even if the clear signal from the clear switch 921 is not input to the payout control microcomputer 370, when the game control microcomputer 560 executes the initialization process, the payout control microcomputer 370 immediately starts Can be processed. Also, after resetting the payout stop flag and setting the payout enabled state, the initialization process is not executed.For example, even if an initialization command is erroneously received due to noise or the like, the initialization process is not performed. It will never be executed.

  The payout control microcomputer 370 sets the payout stop flag so as not to execute the payout process when the execution state of the payout control process is restored to the state before the power supply stop. If such control is not performed, the payout control microcomputer 370 resumes payout of game balls based on the value of the award ball non-payout counter stored in the backup RAM area. At that time, if the clear switch 921 is pressed, the payout of game balls should not be resumed, but some game balls are paid out before the game control microcomputer 560 sends an initialization command. There is a possibility that. However, in this embodiment, when the execution state of the payout control process is restored to the state before the stop of power supply, control is first performed so that the payout process is not executed, so that such a possibility disappears. Further, since the payout control microcomputer 370 executes the initialization process immediately after receiving the initialization command, the game control microcomputer 560 and the payout control microcomputer 370 execute an initialization process in which the game control microcomputer 370 is reliably matched. be able to.

  In this embodiment, the payout control microcomputer 370 resets the payout stop flag when the monitoring timer times out without receiving the initialization command, so the game control microcomputer 560 executes the game control process. When the state is restored to the state before the power supply stop, the restoration command may not be output.

  FIG. 77 is a flowchart showing the payout motor control process in step S753. In the payout motor control process, if the payout stop flag is not set (step S520), the payout control microcomputer 370 executes any one of steps S521 to S526 according to the value of the payout motor control code. . If the payout stop flag is set, the processes in steps S521 to S526 are not executed.

  In the payout motor normal process (step S521) executed when the value of the payout motor control code is 0, if a value other than 0 is set in the payout operation counter, the payout control microcomputer 370 stores a pointer in the ROM. Set to the start address of the stored table. The payout motor normal process setting table stores a payout motor excitation pattern table in which data of excitation patterns (payout motors φ1 to φ4) of each step for rotating the payout motor 289 at the time of ball payout is sequentially set. Yes. Then, the value of the dispensing motor control code is set to 1.

  In the payout motor start preparation process (step S522) executed when the value of the payout motor control code is 1, the payout control microcomputer 370 stores the initial value of the excitation pattern in the output port buffer corresponding to the output state of the output port. The processing such as setting is performed. Then, the value of the dispensing motor control code is set to 2.

  In the payout motor slow-up process (step S523) executed when the value of the payout motor control code is 2, the payout control microcomputer 3701 is in the case of constant speed processing in order to smoothly start the payout motor 289. The content of the payout motor excitation pattern table is read and set in the output port buffer corresponding to the output state of the output port at a time interval longer than the time interval and gradually approaching the time interval for constant speed processing. . At the time of reading, the contents of the payout motor excitation pattern table at the address pointed to by the pointer are read and the pointer value is incremented by one. Then, when it is time to shift to the constant speed process, the value of the payout motor control code is set to 3.

  In the payout motor constant speed process (step S524) executed when the value of the payout motor control code is 3, the payout control microcomputer 370 periodically reads the content of the payout motor excitation pattern table and outputs the output port. Set the output port buffer corresponding to the status. When the value of the payout operation counter reaches a predetermined value (for example, 1), the value of the payout motor control code is set to 4.

  In the payout motor brake process (step S525) executed when the value of the payout motor control code is 4, the payout control microcomputer 370 stops the payout motor 289 more smoothly than in the case of the constant speed process. The content of the payout motor excitation pattern table is read at a long interval and gradually away from the time interval in the case of constant speed processing, and set in the output port buffer corresponding to the output state of the output port. Then, when it is time to stop the payout motor 289, the value of the payout motor control code is set to zero.

  In the payout motor brake process, the rotation of the payout motor 289 is finally stopped. However, at the time of stoppage, the payout motor excitation pattern is repeatedly repeated in the output state of the output port in the payout motor normal process. Set to the corresponding output port buffer. The stop-time payout motor excitation pattern is a pattern in which at least one phase of the payout motors φ1 to φ4 is excited. Since the excitation pattern given to the payout motor 289 is one type of stop-time payout motor excitation pattern (it does not change), the payout motor 289 does not rotate. Moreover, since the dispensing motor 289 is excited, it does not rotate easily. Therefore, for example, even if an action that gives vibration to a gaming machine installed in a gaming store is performed, the gaming ball is not paid out. If the excitation is canceled while the rotation of the payout motor 289 is stopped, the payout motor 289 is not restrained, so that the payout motor 289 vibrates in the rotation direction in accordance with the vibration given from the outside, and the game ball is paid out. There is a possibility. Further, when the rotation of the payout motor 289 is stopped, the payout motor brake process is started so that the value of the payout operation counter is 0. The subtraction of the payout operation counter is executed in a payout motor stop waiting process to be described later.

  In the ball biting payout motor brake process (step S526) executed when the value of the payout motor control code is 5, the payout control microcomputer 370 performs the payout motor 289 in the case of rotation for releasing the ball biting. In order to stop the operation smoothly, the content of the payout motor excitation pattern table is read at a time interval gradually moving away from the time interval in the case of constant speed processing, and set in the output port buffer corresponding to the output state of the output port. . The ball biting motor brake process is executed when it is detected that ball biting or the like has occurred.

  FIG. 78 is a flowchart showing the main control communication process in step S755. In the main control communication process, the payout control CPU 371 checks whether or not the reception interrupt flag is set (step S542). That is, the payout control CPU 371 checks whether or not the serial communication circuit 376 receives the received data and the data is stored in the reception data register of the serial communication circuit 376.

  If the reception interrupt flag is set, the payout control CPU 371 reads data from the reception data register of the serial communication circuit 376 (step S543). Further, the payout control CPU 371 determines whether or not the read data is a prize ball number signal (whether it is any of the commands “04”, “07”, or “0F”) (step S544). .

  When confirming that the data read from the reception data register of the serial communication circuit 376 is a prize ball number signal, the payout control CPU 371 resets the reception interrupt flag (step S545), and the prize ball number signal indicates The number of prize balls is stored in a prize ball payout total counter provided in a predetermined area of the RAM (step S546). Then, the payout control CPU 371 writes the prize ball ACK command to the transmission data register 710 of the serial communication circuit 376 (step S547), and ends the process. Thereafter, the winning ball ACK command written in the transmission data register is transferred to the transmission shift register of the serial communication circuit 376 and transmitted from the transmission shift register of the serial communication circuit 376 to the game control microcomputer 560. In addition, the winning ball payout scheduled total counter is formed in the RAM.

  Note that the process of step S546 may be replaced with a process of adding the number of prize balls indicated by the prize ball number signal to the prize ball unpaid number counter. When such a change is made, in the award ball payout addition control (see FIG. 81), which will be described later, in place of the process of step S694, the value of the award ball unpaid number counter and the value of the previous award ball payout scheduled total counter Are compared with each other, and instead of the processing in step S697, processing for setting the value of the award ball unpaid number counter in the previous award ball payout scheduled total counter is executed. In the prize ball lending process shown in FIG. 80, the process of step S604 is not executed, and the value of the award ball unpaid number counter and the value of the previous award ball payout total counter are set when the payout operation ends ( In step S641 in FIG. 83, initialization is performed.

  In this embodiment, when power supply to the gaming machine is started, the initialization command and the recovery command output by the gaming control microcomputer 560 are received by an interrupt process different from the main control communication process. Is done. That is, the signal line of the payout control INT signal is connected to the external interrupt terminal of the payout control microcomputer 370. When a payout control INT signal is input from the game control microcomputer 560, the payout control CPU 371 executes an interrupt process based on the payout control INT signal. In the interruption process, the payout control CPU 371 inputs data from an input port assigned to input data of an initialization command and a recovery command. For example, if the input data is initialization command data, a flag indicating that the initialization command has been received is set. If the input data is recovery command data, the recovery command has been received. Set the flag to indicate.

  When the initialization command and the recovery command are transmitted and received by serial communication, the initialization command and the recovery command may be received in the main control communication process.

  FIG. 79 is an explanatory diagram showing an example of a counter used by the payout control CPU 371 in the payout control process. In this embodiment, a prize-ball-payout-scheduled total counter that stores the total number of prize-balls to be paid out, which is the number obtained by cumulatively adding the numbers specified in the prize-ball number command, and an addition process (addition process) described later are executed. A total number of previous prize ball payout total counters that store the total number of prize ball payouts prior to being played, a payout operation counter in which a value corresponding to the number of revolutions of the payout motor 289 at the time of prize ball payout is set, and a series of prize balls A winning ball unpaid number counter in which the number of winning balls at the time of paying is set and a lending ball unpaid number counter in which the number of lending balls is set are used. These counters are formed in the RAM. Each counter is a 16-bit (2 bytes) counter.

  The payout operation counter is used to determine the rotation speed of the payout motor 289. The values of the award ball unpaid number counter and the lending ball unpaid number counter are decremented by 1 when the payout number count switch 301 is turned on (the game ball passes the switch). Therefore, the award ball unpaid number counter and the lending ball unpaid number counter detect that the game ball finally paid out by the payout motor 289 passes through the payout number count switch 301 (the count value becomes 0). Used to determine that the award ball lending and ball lending have been completed.

  In order to determine the rotation speed of the payout motor 289, a payout operation timer that determines a rotation time according to the payout number may be used instead of the payout operation counter. When the payout operation timer is used, the data held in the drive amount data storage means (in this case, the timer value of the payout operation timer) corresponds to the drive amount of the payout drive means (in this example, the payout motor 289). The driving amount updating means for subtracting the minute amount corresponds to executing a process of reducing the timer value of the payout operation timer as time elapses.

  FIG. 80 is a flowchart showing the winning ball lending control process in step S756. In the winning ball lending control process, the payout control CPU 371 executes the winning ball payout amount addition control if the payout stop flag is not set (step S599). The prize ball payout amount addition control is a process for adding the number of newly received prize ball number commands to the number of prize balls to be paid out. If the payout stop flag is set, the processes after step S600 are not executed.

  Next, when the payout control CPU 371 confirms that the detection signal of the payout number count switch 301 is turned on (step S601), the payout control CPU 371 determines whether or not the ball is being loaned based on the ball lending operation in progress flag ( Step S602). If the ball is being lent, the value of the unpaid ball rental counter is decremented by 1 (step S603). If not, the value of the prize ball unpaid counter is decremented by 1 (step S604). Thereafter, any one of steps S610 to S612 is executed according to the value of the payout control code.

  FIG. 81 is a flowchart showing the control for adding the number of prize balls to be paid out. In the prize ball payout addition control, the payout control CPU 371 loads the upper byte of the prize ball payout total counter (PA) into the register (step S690A). Then, it is confirmed whether or not the upper 6 bits of the upper byte are all 0 (step S690B). If there is even one “1” bit among the upper 6 bits, the upper 6 bits are cleared to 0 and stored in the award ball payout total counter (PA) (step S690C).

  In this embodiment, the upper limit value of the winning ball payout scheduled total counter (PA) is a value (decimal number 1023) represented by the lower 10 bits of 16 bits. In this embodiment, the game control microcomputer 560 performs a predetermined number of predetermined bits (16 bits in this example) in the prize ball payout total counter (PA) before executing the determination process in step S694. Check whether the bit (the upper 6 bits in this example) corresponding to the number exceeding the storage upper limit value (1023 in this example) indicates a valid value (1 in this example) corresponding to having the stored value When the valid value is indicated, the bit is changed to an invalid value (0 in this example) corresponding to not having a stored value, and when it is determined in the determination process that the data does not match The addition process of step S695 is executed. Even if the winning ball payout total counter (PA) is increased due to fraud, the value of the bit corresponding to the number exceeding the predetermined storage upper limit value is invalidated. As a result, it is possible to make it difficult to receive fraud.

  Next, the payout control CPU 371 determines whether there is a bit indicating an error state in an error flag in which various error states are reflected in each bit, and when there is a bit indicating an error state. (However, the bit of the prepaid card unit non-connection error described later (see FIG. 86) is excluded), the processing is terminated without doing anything (step S691). Further, it is determined whether or not the ball lending operation flag is set. If it is set, the processing is terminated without doing anything (step S692). Since the winning ball lending control process is executed every 2 ms, the winning ball payout amount addition control is also executed every 2 ms. However, in the error state due to the process of step S691, the processes after step S693 are not executed. Note that, as a result of the determination in step 692, the processing after step S693 is not executed while the ball lending process is being executed.

  Further, the payout control CPU 371 determines whether or not the value of the payout operation counter is not 0 (step S693). If it is not 0, the processing after step S694 is executed. However, if it is 0, the processing after step S694 is not executed.

  In step S694, the payout control CPU 371 checks whether or not the content of the planned winning ball payout counter (PA) is the same as the content of the previous winning ball payout total counter (PB). If they are not the same, a process for adding the number of prize balls to be paid after step S695 (hereinafter referred to as an addition process or an addition process) is executed. The previous prize ball payout total counter (PB) is set with the content of the prize ball payout total counter (PA) at the start of the prize ball payout process and when the extra process (previous addition process) is executed. Yes. Further, when a prize ball number command is received from the game control means, the number instructed by the prize ball number command is added to a prize ball payout scheduled total counter (PA) (see FIG. 78). Accordingly, the fact that the content of the total number of winning ball payout counter (PA) is different from the content of the previous total number of paying ball counter (PB) means that a new winning ball number command has been received from the game control means. Therefore, if the conditions for prohibiting the addition of steps S691 to S693 are not satisfied, the addition process after step S695 is performed.

  In step S695, the payout control CPU 371 adds, to the payout operation counter, a value corresponding to the difference between the content of the total prize ball payout total counter (PA) and the content of the previous prize ball payout total counter (PB). To update the payout operation counter (step S695). In addition, the difference between the contents of the total number of expected winning ball payout counter (PA) and the content of the total number of previous winning ball payout scheduled counter (PB) is added to the number of unpaid prize ball counter (step S696). Furthermore, the previous winning ball payout scheduled total counter (PB) is updated by setting the content of the expected winning ball payout total counter (PA) in the previous winning ball payout scheduled total counter (PB) (step S697). In this embodiment, when one game ball is paid out from the payout motor 289, the value of the payout operation counter is decremented by 1. Therefore, the addition value for the payout operation counter and the addition for the award ball non-payout number counter are added. The value is the same value. Further, by adding to the payout operation counter, the payout motor 297 rotates extra by an amount corresponding to the added value (added value). As a result, game balls are paid out by an amount corresponding to the added value until the payout motor 297 stops. That is, the time required for payout per game ball is shortened.

  In step S697, instead of setting the content of the planned total payout ball counter (PA) in the previous total payout ball counter (PB), the planned total payout ball counter (PA) and the previous prize ball payout are set. The contents of the scheduled total counter (PB) may be cleared to zero. That is, when the increase determination means determines that the data has increased, the increase number specifying means moves the increase data stored in the prize game medium number data storage means to the payout operation counter (step S695). The stored contents of the prize game medium number data storage means (in this example, the prize ball payout scheduled total counter (PA)) and the previous prize game medium number data storage means (in this example, the previous prize ball payout scheduled total counter (PB)) are stored. It may be initialized. In such a configuration, it is possible to prevent the storage capacities of the prize game medium number data storage means and the prize game medium number data storage means from increasing.

  In this embodiment, since one game payout device 97 performs game ball payout based on the prize ball number command and game ball payout based on the loan request, when the ball lending process is executed, The prize ball payout process cannot be executed. Therefore, even if the extra process is performed while the ball lending process is being performed, the award ball payout is not performed, and therefore a meaningless process is performed. However, by prohibiting the extra process when performing the ball lending process, it is possible to improve the efficiency of the extra process so that the meaningless process is not executed.

  Similarly, in an error state (however, a prepaid card unit non-connection error bit described later (see FIG. 86) is not a target), the winning ball payout process cannot be executed. Therefore, even if the extra process is performed in an error state, the prize ball payout is not executed, and therefore a meaningless process is performed. However, by prohibiting the extra process in the error state, it is possible to improve the efficiency of the extra process so that the meaningless process is not executed. The addition process is executed collectively when the error state is canceled based on the operation signal from the error cancellation switch 375 (additions based on all prize ball number commands received in the error state are added. )

  FIG. 82 is a flowchart showing the payout start waiting process (step S610) executed when the payout control code is 0. In the payout start waiting process, the payout control CPU 371 does not execute the subsequent processes if an error bit (however, a prepaid card unit unconnected error bit (described later) (see FIG. 86) described later) is not set) is set (step S620).

  If the error bit is not set (the prepaid card unit unconnected error bit may be set), the payout control CPU 371 checks whether or not the VL signal is on (step S621). ). If it is off, the process proceeds to step S631. When checking whether the VL signal is on, the bit of the prepaid card unit unconnected error may be checked. In addition, by such control, when the communication with the card unit 50 cannot be normally performed, it is possible to prevent the game ball from being paid out according to the request from the card unit 50, and it is unnecessary. Game ball payout (payment of game balls when game media wins a prize area) can be prevented from being stopped. In other words, the process of confirming whether or not the VL signal is on is executed only in the payout start waiting process and not in the payout motor stop waiting process or the like, so that the game ball is paid out when a game medium wins in the winning area That is, when the prize ball payout is started, the prize ball payout is not interrupted even if the VL signal is turned off. This also applies to ball lending. Also, in the payout motor stop waiting process or the like, it may be confirmed whether or not the VL signal is on, and when the VL signal is turned off, the payout of the game ball may be interrupted immediately.

  When the VL signal is on, if the BRDY signal is not on (step S622), the process for paying out a prize ball after step S631 is executed. If the BRDY signal is on and the BRQ signal, which is a ball lending request signal, is on, a ball lending operation flag is set (steps S623 and S624). Then, “25” is set in the unpaid ball lending number counter (step S625), and “25” is set in the payout operation counter (step S626).

  The payout operation counter is referred to in the payout motor control process (step S753). That is, in the payout motor control process, control is performed to rotate the payout motor 289 by the number of rotations corresponding to the value set in the payout operation counter.

  Thereafter, the payout control CPU 371 sets a value (specifically “1”) corresponding to the payout motor activation preparation process (step S522) to the payout motor control code for selecting the process executed in the payout motor control process. It is set (step S627), the value of the payout control code is set to 1 (step S628), and the process is terminated.

  In step S631, the payout control CPU 371 checks whether or not the content of the winning ball payout scheduled total counter (PA) is 0 (step S631). If 0, the process ends. When a prize ball number command is received from the game control means of the main board 31 in the main control communication process, a value other than 0 (the number indicated by the prize ball number command) is added to the total number of payballs scheduled to be paid out (PA). Has been. If the content of the total number of paying ball counters (PA) is not 0, the content of the total number of scheduled paying ball counters (PA) is set in the payout operation counter (step S632), and the number of winning balls in the award ball is not paid out The contents of the payout scheduled total counter (PA) are set (step S633). In addition, the content of the total number of winning ball payouts counter (PA) is set in the previous number of paying ball payouts total counter (PB) (step S634). Then, a winning ball operating flag is set (step S635), and the process proceeds to step S627.

  FIG. 83 is a flowchart showing a payout motor stop waiting process (step S611) executed when the payout control code is 1. In the payout motor stop waiting process, the payout control CPU 371 checks whether or not the payout operation of the payout motor 289 has ended (step S641). For example, the payout control CPU 371 sets a flag to that effect when the payout motor brake process (step S525) in the payout motor control process ends, and confirms the flag in step S641 to determine the payout motor 289. It can be confirmed whether or not the payout operation is completed. If the payout operation has not ended, the payout control CPU 371 decrements the value of the payout operation counter by 1 when the payout motor position sensor 295 is turned on (step S644). In step S641, it may be determined whether or not the value of the payout operation counter is 0. If the value of the payout operation counter is 0, it may be determined that the payout operation has ended.

  When the payout operation of the payout motor 289 is completed, the payout control CPU 371 sets the payout passing monitoring time in the payout control monitoring timer (step S642). The payout passing monitoring time is a time that has a margin in the time from when the last payout ball is paid out by the payout motor 289 until it passes through the payout number count switch 301. Then, the value of the payout control code is set to 2 (step S643), and the process ends.

  84 and 85 are flowcharts showing a payout passing waiting process (step S612) executed when the value of the payout control code is 2. In the payout passing waiting process, when the prize ball is being paid out, it is determined that the payout has been completed normally if the value of the prize ball unpaid number counter is 0. Note that the value set in the payout operation counter for determining the rotation amount of the payout motor 289 corresponds to the value set in the award ball non-payout number counter at the start of the payout process, and the control here is performed. When executed, the value of the payout operation counter is 0 corresponding to the stop of the payout motor 289 (the payout motor 289 has been paid out). The payout motor 289 should have made a predetermined number of payouts, but the payout number count switch 301 provided at the bottom of the ball payout device 97 could only detect less than a predetermined number of payouts. Become. That is, the payout has not been completed normally.

  When the value of the award ball unpaid-out counter is not 0, if the error ball is not in an error state, a game ball re-payout operation is attempted. In the re-payout operation, when it is detected by the payout number count switch 301 that the game ball is actually paid out, it is determined that the payout has been completed normally.

  Further, when the ball lending is being paid out, it is determined that the payout has been completed normally if the value of the ball lending unpaid-out counter is 0. If the value of the ball lending unpaid number counter is not 0, if it is not an error state, a re-payout operation of the game ball or the remaining number of ball lending (corresponding to the value of the ball lending unpaid number counter) is attempted.

  As a specific process of the above description, in the payout passing waiting process, the payout control CPU 371 decrements the value of the payout control timer by 1 if the value of the payout control timer is not 0 (step S651). If the value of the payout control timer is not 0 (step S652), that is, if the payout control timer has not timed out, the process is terminated.

  If the payout control timer has timed out (step S652), it is determined whether or not a ball lending payout process (ball lending operation) has been executed (step S653). Whether or not the ball lending operation has been executed is confirmed by whether or not the ball lending operation in progress flag in the payout control state flag formed in the RAM is set. When the ball lending operation is not executed, that is, when the prize ball payout processing (prize ball operation) is executed, the payout control CPU 371 checks the value of the award ball unpaid number counter (step S654). ). If the value of the prize ball unpaid number counter is 0, the following process is performed assuming that the prize ball payout process is normally completed.

  That is, the value set in the previous prize ball payout total counter (PB) is subtracted from the contents of the prize ball payout total counter (PA) (step S671). Then, the content of the previous winning ball payout scheduled total counter (PB) is cleared (initialized) to 0 (step S672).

  In addition, the payout ball detection bit, the re-payout operation bit, the winning ball operation flag and the ball lending operation bit in the payout control state flag are reset (step S655), the payout control code is set to 0 (step S656), and the processing is performed. The re-payout operation bit is a control bit used when the re-payout process is executed.

  In step S671, the content of the previous total number of payout balls counter (PB) is subtracted without clearing the content of the total number of payballs scheduled to be paid out (PA). In consideration of the fact that a new prize ball number command is received and the contents of the prize ball payout scheduled total counter (PA) may increase during the execution of.

  Although not explicitly shown in FIG. 84, the addition process is not executed while the payout passing waiting process is being executed (because “Y” is not set in step S693 shown in FIG. 81). If executed, the initialization process of step S672 is executed in spite of the content of the previous winning ball payout scheduled total counter (PB) being updated, whereby the previous winning ball payout scheduled total counter (PB). This is because the number of prize balls paid out may not be accurate. Also, the value of the award ball unpaid out counter is increased (see step S696), and the check process in step S654 cannot be executed normally. However, as long as the value of the payout control timer does not become 0, the extra process may be executed while the payout passing waiting process is being executed. In this case, when the addition process is executed, the payout control code is updated to 1. In this embodiment, when the payout sensor (payout number count switch 301) detects the last game ball, the payout motor 289 is not stopped, but when the payout motor 289 pays out the last game ball. The payout motor 289 is stopped. Therefore, there is no possibility that a new game ball is paid out by driving the payout motor 289. That is, the accuracy of the continuous payout control that is not divided for each prize ball that is executed in order to realize quick prize ball payout is increased.

  The payout control CPU 371 determines that an error flag (specifically, a payout switch error error 1 bit, a payout switch error error 2 bit, and a payout case error bit when the value of the award ball unpaid number counter is not 0. The re-payout operation is executed on the condition that any one or a plurality of bits) is not set (step S659). If the error flag is set, the re-payout operation is not executed.

  In order to execute the re-payout process, the pay-out control CPU 371 first checks whether or not the re-payout operation bit is set (step S661). If not set, the re-payout operation in-progress bit is set (step S662), and a value corresponding to the value of the award ball unpaid number counter or the ball lending unpaid number counter is set in the payout operation counter (step S663). ). Thereafter, the payout control code is set to 1 (step S667), and the process is terminated.

  In step S661, when it is confirmed that the re-payout operation in-progress bit is set, the payout control CPU 371 does not pay out the game ball even when the re-payout process is executed (the payout number count switch 301 is set in the game ball). Is not detected), a payout case error bit in the error flag is set (step S666). At that time, the re-payout operation in-progress bit is reset (step S665). Then, the process ends.

  As described above, if the game ball is not paid out correctly even after performing the re-payout operation in the re-payout process (corrected payout process), the payout count switch non-passing error bit (payout) is assumed as a game ball payout operation failure. Case error bit) is set.

  Upon confirming that the ball lending / dispensing process (ball lending operation) has been executed in step S653, the payout control CPU 371 confirms whether or not the value of the ball lending unpaid out counter is 0 (step S657). . If it is 0, it is determined that the ball lending / dispensing process is normally completed, and the process proceeds to step S655.

  If the value of the ball lending unpaid number counter is not 0, an error flag (specifically, any one bit of the payout switch abnormal error 1 bit, the payout switch abnormal error 2 bit, and the payout case error bit) On the condition that (multiple bits) is not set (step S658), the re-payout process is executed. If the error flag is set, the re-payout process is not executed.

  Next, error processing will be described. FIG. 86 is an explanatory diagram showing the relationship between the type of error and the display of the LED 374 for error display. In the error flag (for example, 1 byte) formed in the RAM, there are bits corresponding to the errors shown in FIG.

  As shown in FIG. 86, when the payout count switch 301 is disconnected or a ball clogging occurs in the payout count switch 301, “2” is displayed on the error display LED 374 as the payout switch abnormality detection error 1. Control. The disconnection of the payout number count switch 301 or the occurrence of ball clogging in the payout number count switch 301 is determined by the detection signal of the payout number count switch 301 not being turned off.

  When the detection signal of the payout number count switch 301 is turned on even though the game ball is not paying out, a control for displaying “3” on the error display LED 374 as a payout switch abnormality detection error 2 is performed. Do. If the detection signal of the payout count switch 301 does not turn on despite the rotation abnormality of the payout motor 289 or the game ball being paid out, “4” is displayed on the error display LED 374 as a payout case error. Control. The specific method for detecting that the detection signal of the payout number count switch 301 is not turned on is as described above.

  In addition, when the lower pan is full, that is, when the full switch 48 is turned on, control is performed to display “6” on the error display LED 374 as a full error. When the supply ball is insufficient, that is, when the ball break switch 187 is turned on, control is performed to display “7” on the error display LED 374 as a ball break error.

  Further, when the VL signal from the card unit 50 is turned off, control is performed to display “8” on the error display LED 374 as a prepaid card unit non-connection error. When communication is made with the card unit 50 at an incorrect timing, control is performed to display “9” on the error display LED 374 as a prepaid card unit communication error. The prepaid card unit communication error is detected in the prepaid card unit control process (step S754).

  Among the above errors, after the occurrence of a payout switch abnormality detection error 2, a payout case error or a prize ball REQ signal error, the error release switch 375 is operated and an operation signal is output from the error release switch 375 (becomes turned on). The payout control means returns to the state before the error occurred.

  FIG. 87 is an explanatory diagram showing an example of changes in the contents of the counter used in the prize ball payout control. The winning ball payout total counter, the previous winning ball payout total counter, the payout operation counter, and the award ball unpaid number counter are initialized (specifically, when the payout control state recovery process such as step S709 is not executed). It is cleared to 0 in the process of step S715. Thereafter, for example, when 15 prize ball number commands are received, the value of the prize ball payout total counter is 15 in the main control communication process. Then, when the prize ball payout process is started, 15 is set in the previous prize ball payout scheduled total counter, the payout operation counter, and the prize ball non-payout number counter (see steps S632 to S634). Thereafter, each time the payout motor position sensor 295 is turned on, the value of the payout operation counter is decremented by 1, and every time the payout number count switch 301 is turned on, the value of the award ball non-payout number counter is decremented by 1. In the meantime, for example, when 10 prize ball number commands are received, 10 is added to the prize ball payout scheduled total counter in the main control communication process to become 25.

  Then, the difference (10 in this example) between the contents of the total number of the expected winning ball payout counter (PA) and the total number of the previous planned winning ball payout counter (PB) is obtained by the addition process (steps S695 and S696) in the additional control for the number of paid-in balls. ) Is added to the payout operation counter and the award ball non-payout number counter. Therefore, the value of the payout operation counter and the award ball non-payout number counter is 18. Further, the contents of the previous prize ball payout scheduled total counter (PB) are the same as the contents of the prize ball payout scheduled total counter (PA) (see steps S695 to S697).

  Thereafter, when the value of the unsuccessful prize ball counter reaches zero and the prize ball payout is completed, the previous prize ball payout total counter (PB) is determined from the content of the prize ball payout total counter (PA) (25 in this example). Is subtracted (the subtraction result is 0 in this example), and the previous award ball payout scheduled total counter (PB) is cleared.

  FIG. 88 is an explanatory diagram showing another example of changes in the contents of the counter used in the prize ball payout control. The contents of the total number of winning ball payout counter (PA) and the value of the previous winning ball payout total counter (PB) are 15, and 10 winning ball number commands are received during the paying out of the winning ball. And Then, in the main control communication process, 10 is added to the prize ball payout scheduled total counter to be 25.

  Then, by the addition process executed when the value of the payout operation counter reaches a predetermined value (for example, 1), the contents of the planned total payout ball counter (PA) and the total previous payball payout total counter (PB) (10 in this example) is added to the payout operation counter and the award ball non-payout number counter. Accordingly, the value of the payout operation counter and the award ball non-payout number counter is 11. Further, the contents of the previous winning ball payout scheduled total counter (PB) are the same as the contents of the winning ball payout scheduled total counter (PA).

  It is assumed that the prohibition condition for the extra process is satisfied when the winning ball payout process is continued (see steps S691 and S692). Therefore, it is assumed that the addition process is not executed, but 15 prize ball number commands and 10 prize ball number commands are received during that time. Then, in the main control communication process, 15 and 10 are added to the prize ball payout scheduled total counter to be 50.

  When the prohibition condition for the extra process is canceled, the difference (25 in this example) between the contents of the total prize ball payout total counter (PA) and the previous prize ball payout total counter (PB) is paid out by the extra process. The value is added to the operation counter and the award ball unpaid number counter, and the value of the payout operation counter and the award ball unpaid number counter becomes 26. Further, the contents of the previous winning ball payout scheduled total counter (PB) are the same as the contents of the winning ball payout scheduled total counter (PA).

  Thereafter, when the value of the award ball unpaid number counter becomes 0 and the award ball payout is completed, the previous award ball payout total counter (PB) is determined from the content of the award ball payout total counter (PA) (50 in this example). Is subtracted (the subtraction result is 0 in this example), and the previous award ball payout scheduled total counter (PB) is cleared.

  In this embodiment, the CPU 56 performs initial setting of the random number circuit 503 (random number circuit setting processing) from the start of power-on to the gaming machine until the timer interrupt setting is performed, and the random number circuit setting processing. Then, a value based on the ID number unique to the game control microcomputer 560 is set as the initial value of the random number. Therefore, the randomness of the random number generated by the random number circuit 503 can be improved. In addition, since the randomness of random numbers can be improved, the timing of random number generation can be made difficult to be recognized by a player or a game store, and by generating a capture signal using a radio signal for a gaming machine It is possible to prevent the condition for shifting to a specific gaming state such as a big hit state from being illegally established.

  Also, in this embodiment, when the serial communication circuit 505 makes an interrupt request, the interrupt process when a communication error is caused as an interrupt cause is preferentially executed to control the communication to a prohibited state. Therefore, it is possible to prevent communication with the payout control board 37 mounted on the gaming machine in a state where a communication error has occurred. Therefore, malfunction due to a communication error can be prevented.

Embodiment 2. FIG.
FIG. 89 is a flowchart showing the award ball payout addition control in the second embodiment. In this embodiment, the payout control CPU 371 determines whether or not the value of the payout operation counter has reached a predetermined value (for example, 1) (step S693B). When the predetermined value is reached, the processing after step S694 is executed. However, if the predetermined value is not reached, the processing after step S694 is not executed.

  Other controls are the same as those in the first embodiment. Note that the processing after step S694 is executed at the timing when the value of the payout operation counter is updated to a predetermined value (for example, when the value is changed from 2 to 1), and is not always executed in a state where the predetermined value is reached. Absent.

  In this embodiment, the addition process is executed only at the timing when the value of the payout operation counter is updated to a predetermined value. Therefore, it is possible to reduce the number of determinations as to whether or not the data has increased (the process of step S694), and to reduce the burden of the determination process.

Embodiment 3 FIG.
FIG. 90 is a flowchart showing control for adding the number of prize balls in the third embodiment. Unlike the first embodiment and the second embodiment, in this embodiment, the payout control CPU 371 loads the upper byte of the prize ball payout scheduled total counter (PA) into the register (step S690A). ) Without checking whether the upper 6 bits of the upper byte are all 0, the upper 6 bits are cleared to 0 and stored in the award ball payout scheduled total counter (PA) (step S690C). Other controls are the same as those in the first embodiment.

Embodiment 4 FIG.
FIG. 91 is a flowchart showing the award ball payout addition control in the fourth embodiment. In this embodiment, the payout control CPU 371 determines whether or not the value of the payout operation counter has reached a predetermined value (for example, 1) (step S693B). When the predetermined value is reached, the processing after step S694 is executed. However, if the predetermined value is not reached, the processing after step S694 is not executed. Other controls are the same as those in the third embodiment.

Embodiment 5 FIG.
FIG. 92 is a flowchart showing a payout stop flag control process in the fifth embodiment. In the fifth embodiment, the payout control CPU 371 checks whether or not a prize ball number signal is received from the game control microcomputer (step S742B). When the prize ball number signal is received, the payout stop flag is reset (step S743). As the payout stop flag is reset, the game ball is allowed to be paid out.

  If the winning ball number signal has not been received, the payout control CPU 371 checks whether or not the initialization command has been received on the condition that the initialization prohibition flag is not set (step S745) (step S745). S746). When the initialization command is received, a RAM clear process for clearing the contents of the RAM is performed (step S747). Also, initial values are set in the RAM area flag, counter (work area), and the like (step S748). Since the contents of the RAM are cleared, when the payout stop flag is set, the payout stop flag is reset. Other controls are the same as those in the first to fourth embodiments.

  The payout control CPU 371, for example, in the main control communication process (see FIG. 78), when a prize ball number signal is received for the first time after the power supply to the gaming machine is started, a flag indicating that fact is given. set. When the payout control CPU 371 detects that the flag has been set, it determines that a prize ball number signal has been received.

  Upon receiving the initialization command, the payout control microcomputer 370 immediately executes initialization processing (steps S747 and S748). Therefore, even if the clear signal from the clear switch 921 is not input to the payout control microcomputer 370, when the game control microcomputer 560 executes the initialization process, the payout control microcomputer 370 immediately starts Can be processed.

  The payout control microcomputer 370 sets the payout stop flag so as not to execute the payout process when the execution state of the payout control process is restored to the state before the power supply stop. Therefore, there is no possibility that the payout control microcomputer 370 pays out some game balls before the game control microcomputer 560 transmits the initialization command even though the clear switch 921 is pressed. . Further, in connection with the recovery process, the payout control microcomputer 370 can immediately start the payout control process at the time when the payout control process should be started.

  In this embodiment, the payout control microcomputer 370 resets the payout stop flag when it receives the award ball number signal without receiving the initialization command, so that the game control microcomputer 560 does the game control process. When the execution state is restored to the state before the power supply stop, the recovery command may not be output. Further, the payout control microcomputer 370 does not have to execute the process (step S712) for setting the monitoring timer in the main process (see FIG. 73).

Embodiment 6 FIG.
FIG. 93 is a flowchart showing the payout stop flag control process in the sixth embodiment. In the sixth embodiment, the payout control CPU 371 checks whether or not a recovery command has been received from the game control microcomputer (step S742C). Specifically, it is confirmed whether or not a recovery command reception flag is set. If the recovery command reception flag is set, the recovery command reception flag is reset (step S742D), and the payout stop flag is reset (step S743). As the payout stop flag is reset, the game ball is allowed to be paid out.

  If the recovery command reception flag is not set, the payout control CPU 371 checks whether the initialization command has been received on the condition that the initialization prohibition flag is not set (step S745) (step S745). S746). When the initialization command is received, a RAM clear process for clearing the contents of the RAM is performed (step S747). Also, initial values are set in the RAM area flag, counter (work area), and the like (step S748). Since the contents of the RAM are cleared, when the payout stop flag is set, the payout stop flag is reset. Other controls are the same as those in the first to fourth embodiments. However, the payout control microcomputer 370 does not have to execute the process of setting the monitoring timer (step S712) in the main process (see FIG. 73).

  Also in this embodiment, the payout control microcomputer 370 sets the payout stop flag so as not to execute the payout process when the execution state of the payout control process is restored to the state before the power supply stop. . Therefore, there is no possibility that the payout control microcomputer 370 pays out some game balls before the game control microcomputer 560 transmits the initialization command even though the clear switch 921 is pressed. . Further, the payout control microcomputer 370 can start the payout control process early in relation to the recovery process.

  In each of the above embodiments, the payout of game balls is permitted on the condition that the initialization command is not received within a predetermined time (see FIG. 76), or the game is executed on the condition that the prize ball number command is received. The ball is permitted to be dispensed (see FIG. 92), or the game ball is permitted to be dispensed on the condition that the recovery command has been received (see FIG. 93). If any one of the two conditions is satisfied, the payout of the game ball may be permitted. Further, in the payout stop flag control process, when any command (or signal) among the initialization command, the recovery command, and the winning ball number signal is first received, the payout of the game ball is permitted. Good. In this case, the initialization prohibition flag is set when any command is received.

  Next, the operation of the sound / lamp control means will be described. FIG. 94 is a flowchart showing a main process executed by the sound / lamp control microcomputer 100b. When power supply to the gaming machine is started and the reset signal becomes high level, the sound / lamp control microcomputer 100b starts main processing. In the main process, the sound / lamp control microcomputer 100b first performs an initialization process for clearing the RAM area, setting various initial values, initializing a timer for determining the activation control activation interval, and the like. This is performed (step S781). Thereafter, the sound / lamp control microcomputer 100b shifts to a loop process for monitoring the timer interrupt flag (step S782). When a timer interrupt occurs, the sound / lamp control microcomputer 100b sets a timer interrupt flag in the timer interrupt process. If the timer interrupt flag is set in the main process, the sound / lamp control microcomputer 100b clears the flag (step S783) and executes the following sound / lamp control process.

  A timer interrupt takes, for example, every 2 ms. That is, the sound / lamp control process is activated every 2 ms, for example. In this embodiment, only the flag is set in the timer interrupt process, and the specific sound / lamp control process is executed in the main process, but the sound / lamp control process is executed in the timer interrupt process. Also good.

  In the sound / lamp control process, the sound / lamp control microcomputer 100b first analyzes the received effect control command (command analysis process: step S784). Next, the sound / lamp control microcomputer 100b performs effect content determination processing (step S785). In the effect content determination process, the sound / lamp control microcomputer 100b uses the variable display device 9 based on the effect control command (variation pattern command or display result designation command) (whether or not to perform the notice effect). Kaya, the type of notice effect). Further, the sound / lamp control microcomputer 100b generates an effect content designation command indicating the determined effect content.

  Next, the sound / lamp control microcomputer 100b performs sound output processing (step S786). In this case, the sound / lamp control microcomputer 100b outputs sound number data (for example, sound number data corresponding to the variation pattern indicated by the variation pattern command) to the speech synthesis IC 173. Then, the voice synthesis IC 173 generates a voice or a sound effect corresponding to the sound number data and outputs it to the amplifier circuit 175.

  Next, the sound / lamp control microcomputer 100b performs lamp display processing (step S787). In this case, the sound / lamp control microcomputer 100b performs lamp control based on the lamp control execution data set in the process data.

  The process data is composed of data obtained by collecting a plurality of combinations of process timer set values and presentation control execution data. The effect control execution data includes lamp control execution data and sound number data. In the lamp control execution data, data indicating the lamp display state during the symbol variation period is set. In addition, as the sound number data, data indicating output timings such as fluctuating sounds and sound effects during the symbol fluctuating period is set. When the timing for switching the display state (for example, the timing at which a new character appears on the variable display device 9 or the timing at which the lamp is switched from the lighting state to the extinguishing state) arrives during the symbol variation period, the effect control means The display state of the lamp and the sound output from the speaker 27 are controlled according to the next effect control execution data in the data. In the process timer set value, a time corresponding to the switching timing is set.

  The process data is stored in the ROM of the sound / lamp control board 80b. The process data is prepared for each of the symbol variation patterns. In this way, the sound / lamp control means controls the rendering device based on the program and process data stored in the ROM, and controls a plurality of rendering devices (speakers 27 and lamps in this embodiment). The related program is stored in the ROM mounted on the sound / lamp control board 80b. And ROM which stores those programs can be comprised as one ROM.

  Further, the sound / lamp control microcomputer 100b executes a process of updating the random number counter (step S788). Further, the sound / lamp control microcomputer 100b performs a process of sending the effect control command received from the main board 31 and the effect content designation command generated in the effect content determination process in step S785 to the symbol control board 80a ( Command control processing: Step S789). Thereafter, the process returns to the process of checking the timer interrupt flag in step S782.

  The signal line of the effect control INT signal from the main board 31 is input to the external interrupt terminal of the sound / lamp control microcomputer 100b. When the production control INT signal is input from the main board 31 to the external interrupt terminal, the sound / lamp control microcomputer 100b is interrupted. Then, the sound / lamp control microcomputer 100b executes an effect control command reception process in the interrupt process. In the effect control command reception process, the sound / lamp control microcomputer 100b stores the received effect control command data in the command reception buffer.

  In this embodiment, process data stored in the ROM of the sound / lamp control board 80b (hereinafter also referred to as sound / lamp control side process data) includes process timer set values, sound number data, and lamp control execution. The data includes a plurality of combinations of presentation control execution data including data. The process data stored in the ROM of the symbol control board 80a (hereinafter also referred to as symbol control side process data) is a collection of a plurality of combinations of process timer setting values and presentation control execution data including only display control execution data. Consists of data.

  FIG. 95 is an explanatory diagram showing random numbers used in the sound / lamp control process. Each random number is used as follows.

(1) Random 1: Decide whether or not to execute the notice effect (for determining the notice effect execution). In this embodiment, when the variable display device 9 performs variable display of the decorative pattern in the reach mode, the sound / lamp control microcomputer 100b, for example, has a random 1 that matches a predetermined determination value. On the other hand, it is determined that a notice effect will be performed. Note that the sound / lamp control microcomputer 100b may determine whether or not to perform the notice effect using random 1 regardless of whether or not the variable display of the reach mode is performed.
(2) Random 2: When performing the notice effect, the type of the notice effect performed using the variable display device 9 is determined (for determining the notice effect type).

  FIG. 96 is a flowchart showing the effect content determination process in step S785. In the effect content determination process, the sound / lamp control microcomputer 100b confirms whether or not the variation pattern reception flag is set (step S1851). The fluctuation pattern reception flag is set when it is determined in the command analysis process (step S784) of the sound / lamp control main process that a fluctuation pattern command has been received.

  If the variation pattern reception flag is set, the sound / lamp control microcomputer 100b resets the variation pattern reception flag and identifies the variation pattern of the decorative design based on the received variation pattern command. Further, the sound / lamp control microcomputer 100b determines whether or not the variable display to be executed using the variable display device 9 is a variation accompanied by reach based on the identified variation pattern (step S1852). For example, in the sound / lamp control microcomputer 100b, when the variation pattern indicated in the received variation pattern command is a pattern with reach (for example, EXT data “02 (H)” to “09 (H)”). In the case of a variation pattern), the sound / lamp control microcomputer 100b determines that the variation involves reach. If the fluctuation pattern reception flag is not set in step S1851, the sound / lamp control microcomputer 100b ends the process as it is.

  If it is determined that the fluctuation is accompanied by reach, the sound / lamp control microcomputer 100b determines whether or not to perform the notice effect based on the notice effect execution determination random number (random 1) (step S1853). For example, the sound / lamp control microcomputer 100b determines to perform a notice effect using the variable display device 9 when the random 1 matches the determination value. Note that if it is not a change accompanied by reach in step S1852, the process proceeds to step S1857.

  When it is determined not to perform the notice effect (step S1854), the sound / lamp control microcomputer 100b receives the variation pattern command and the variation pattern command and the display result designation command when the variation pattern command is received. The display result designation command is transferred to the symbol control microcomputer 100a, and the symbol control microcomputer 100a executes variable display of decorative symbols and game effects using the variable display device 9. In this case, if sound / lamp control microcomputer 100b determines not to perform the notice effect in step S1854, the sound / lamp control microcomputer 100b generates an effect content designation command designating that the notice effect is not performed, and transmits it to the symbol control microcomputer 100a. (Step S1857).

  If it is decided to perform the notice effect (step S1854), the sound / lamp control microcomputer 100b uses the variable display device 9 to perform the kind of the notice effect that is performed based on the random number for determining the notice effect type (random 2). Is determined (step S1855). For example, the sound / lamp control microcomputer 100b can change the speed of the decorative symbol and the rotation direction of the decorative symbol in the notice effect based on the random 2, variable display device. 9 determines which character is to appear.

  In this embodiment, a case will be described in which the effect content is determined by specifying whether or not the reach is based on the variation pattern command. However, the sound / lamp control microcomputer 100b uses the display result designation command as a display result designation command. The content of the production may be determined by specifying that it is a non-probable big hit or a probable big hit.

  Further, the sound / lamp control microcomputer 100b generates an effect content designation command indicating the determined effect content (whether or not to perform the notice effect and the type of the notice effect). Then, the sound / lamp control microcomputer 100b performs a process of transmitting the produced effect content designation command to the symbol control board 80a (step S1856). The sound / lamp control microcomputer 100b transfers (transmits) the display result designation command and the variation pattern command received from the game control microcomputer 560 to the symbol control board 80a together with the effect content designation command. Then, the symbol control microcomputer 100a on the symbol control board 80a performs variable display of decorative symbols and games based on the production content designation command, display result designation command and variation pattern command received from the sound / lamp control microcomputer 100b. Produce. In this case, the symbol control microcomputer 100a reads the display control execution data from the ROM based on the received effect content designation command, and uses the variable display device 9 for the VDP 109 based on the read display control execution data. To do.

  In step S1856, the sound / lamp control microcomputer 100b may add the determined production content to the variation pattern command or the display result designation command instead of generating the production content designation command. For example, the sound / lamp control microcomputer 100b adds the effect content to the variation pattern command or the display result designation command by adding a value indicating the effect content to the header portion of the command. In this case, the sound / lamp control microcomputer 100b may add a value indicating the effect content to the header portion of only the variation pattern command. Then, the sound / lamp control microcomputer 100b may perform a process of transmitting the variation pattern command to which the effect content is added to the symbol control board 80a. Further, the sound / lamp control microcomputer 100b may add a value indicating the content of the effect to the header portion of only the display result command. Then, the sound / lamp control microcomputer 100b may perform a process of transmitting the display result command to which the contents of the effect are added to the symbol control board 80a. When the notice effect is not performed, the sound / lamp control microcomputer 100b directly transfers the variation pattern command or display result command received from the game control microcomputer 560 to the symbol control microcomputer 100a. Become.

  Further, in this embodiment, information indicating whether it is a big hit, whether it is a probable big hit, a fluctuation pattern, and the presence / absence of a notice is added together in a fluctuation pattern command or a display result command, and the added command is a symbol control board. You may perform the process transmitted with respect to 80a. In this case, since only one command is required, the number of commands for the symbol control board 80a can be reduced.

  Also, in this embodiment, the command for specifying the contents of the effect is performed by executing the command control process (see step S789) in the sound / lamp control main process based on the setting of the address of the transmission table in step S1856. Is transmitted to the symbol control board 80a.

  In addition, when the effect content determined in step S1855 is added to the variation pattern command or the display result designation command, the sound / lamp control microcomputer 100b adds the determined effect content (for example, background color or appearing character). A variation pattern command or a display result designation command may be transmitted to the symbol control microcomputer 100a. The symbol control microcomputer 100a reads display control execution data from the ROM based on the received variation pattern command and display result designation command, and produces an effect using the variable display device 9 based on the read display control execution data. You may go.

  Further, process data including both display control execution data and lamp control execution data may be stored in the ROM of the sound / lamp control board 80b. In this case, the sound / lamp control microcomputer 100b may extract display control execution data corresponding to the determined effect content from the ROM, and transmit it to the symbol control microcomputer 100a together with the generated effect content designation command. . Then, the symbol control microcomputer 100a may produce an effect using the variable display device 9 based on the received display control execution data.

  When process data including both display control execution data and lamp control execution data is stored in the ROM of the sound / lamp control board 80b, the sound / lamp control microcomputer 100b responds to the determined contents of the effect. The display control execution data may be extracted from the ROM and transmitted to the symbol control microcomputer 100a. Then, the symbol control microcomputer 100a may produce an effect using the variable display device 9 based on the received display control execution data.

  In this embodiment, the sound / lamp control microcomputer 100b uniquely determines the contents of the presentation (whether or not to perform the notice effect and the type of the notice effect) based on the variation pattern command. Further, the symbol control microcomputer 100a executes the game effect using the variable display device 9 in accordance with the effect contents determined by the sound / lamp control microcomputer 100b. Therefore, it is not necessary for the game control microcomputer 560 to determine the contents of the effects. Therefore, the processing load of the game control microcomputer 560 can be reduced.

  Note that the sound / lamp control microcomputer 100b may generate a decorative symbol variation time designation command indicating the variation time of the decorative symbol and transmit the command to the symbol control board 80a. Further, upon receiving the effect content designation command, the symbol control microcomputer 100a on the symbol control board 80a causes the VDP 109 to execute the variable display of the decorative symbols on the variable display device 9 based on the received effect content designation command. Make a notice effect.

  In this embodiment, an effect control command from the main board 31 is first received by the sound / lamp control board 80b, and then an effect control command and an effect content designation command are sent from the sound / lamp control board 80b to the symbol control board 80a. However, the design control board 80a may first receive an effect control command from the main board 31.

  In the example shown in FIG. 96, when a variation pattern command is received, it is determined whether or not the variation is accompanied by reach. If the variation is accompanied by reach, the presence / absence of execution of the notice effect is determined. , Processing to generate a production content command. However, the present invention is not limited to such a configuration. For example, when a variation pattern command is received, it is determined whether the variation pattern is for big hit. Whether to execute or not may be determined, and processing for generating an effect content command may be performed. Even with such a configuration, the control burden of the game control microcomputer 560 can be reduced.

  Next, the operation of the symbol control means will be described. FIG. 97 is a flowchart showing main processing executed by the symbol controlling microcomputer 100a. When power supply to the gaming machine is started and the reset signal becomes high level, the symbol controlling microcomputer 100a starts main processing. In the main process, the symbol control microcomputer 100a first performs an initialization process for clearing the RAM area, setting various initial values, initializing a timer for determining the start interval of the production control, and the like ( Step S771). Thereafter, the symbol controlling microcomputer 100a shifts to a loop process for checking the timer interrupt flag (step S772). When a timer interrupt occurs, the symbol control microcomputer 100a sets a timer interrupt flag in the timer interrupt process. If the timer interrupt flag is set in the main process, the symbol control microcomputer 100a clears the flag (step S773) and executes the following symbol control process.

  A timer interrupt takes, for example, every 2 ms. That is, the symbol control process is activated every 2 ms, for example. In this embodiment, only the flag is set in the timer interrupt process, and the specific symbol control process is executed in the main process. However, the symbol control process may be executed in the timer interrupt process.

  In the symbol control process, the symbol control microcomputer 100a first analyzes the received effect control command (command analysis process: step S774). Next, the symbol control microcomputer 100a performs symbol control process processing (step S775). In the symbol control process, the process corresponding to the current control state (symbol control process flag) is selected from the processes corresponding to the control state, and the display control of the variable display device 9 is executed. Further, a process for updating the random number counter is executed (step S776). Thereafter, the process returns to the process of checking the timer interrupt flag in step S772.

  The INT signal from the sound / lamp control board 80b is input to the interrupt terminal of the symbol controlling microcomputer 100a. For example, when the INT signal from the sound / lamp control board 80b is turned on, the symbol control microcomputer 100a is interrupted. Then, the symbol controlling microcomputer 100a executes a receiving process of the effect control command and the effect content command in the interrupt process. In the command reception process, the symbol control microcomputer 100a stores the received command data in the command reception buffer.

  FIG. 98 is a flowchart showing a specific example of command analysis processing (step S774). The effect control command and the effect content designation command received from the sound / lamp control board 80b are stored in the reception command buffer. However, in the command analysis process, the symbol control microcomputer 100a receives the command stored in the command reception buffer. Check the contents of.

  In the command analysis process, the symbol control microcomputer 100a first checks whether or not a reception command is stored in the command reception buffer (step S7611). Whether it is stored or not is determined by comparing the value of the command reception number counter with the read pointer. The case where both match is the case where the received command is not stored. If the received command is stored in the command receiving buffer, the symbol controlling microcomputer 100a reads the received command from the command receiving buffer (step S7612). When read, the value of the read pointer is incremented by 1 (step S7613).

  If the received effect control command or the like is an effect control command for designating a variation pattern (step S7614), the symbol controlling microcomputer 100a stores the EXT data of the command in the variation pattern data storage area (step S7615). In this case, the symbol controlling microcomputer 100a sets a variation pattern reception flag indicating that the variation pattern command has been received (step S7616).

  The processing in steps S7614 to S7616 is also executed in command analysis processing executed by the sound / lamp control microcomputer 100b.

  If the effect control command or the like confirmed to be received in step S7611 is an effect control command for designating the display result (step S7619), the symbol controlling microcomputer 100a displays the EXT data of the command as the display result ( It is stored in the display result storage area as a special symbol display result (step S7620). Next, a stop symbol of a decorative symbol (left middle right symbol) corresponding to the display result specified by the display result specifying command is determined and stored in the decorative symbol storage area (step S7621). Note that the stop symbol of the decorative design is determined based on a random number for determining the decorative design. In addition, it is confirmed whether or not the variation pattern specified by the variation pattern command is a variation pattern with reach, and in the case of a variation pattern with reach, reach patterns (for example, left and right ornaments) Designs having the same design but different decorative designs are determined.

  If the received command read in step S7612 is another effect control command, the symbol control microcomputer 100a sets a command reception flag corresponding to the received command, and stores the received command if necessary (step S7622).

  For example, if the received command is a recovery command, data (for example, a flag) indicating a gaming state corresponding to the recovery command is stored. Such processing is also executed in command analysis processing executed by the sound / lamp control microcomputer 100b.

  FIG. 99 is a flowchart showing the symbol control process (step S775) in the main process shown in FIG. In the symbol control process, the symbol control microcomputer 100a executes any one of steps S1800 to S1805 according to the value of the symbol control process flag. In each process, the following process is executed.

  Ornamental symbol normal processing (step S1800): It is confirmed whether or not a variation pattern command is received. If the variation pattern command has been received, the symbol control microcomputer 100a changes the value of the symbol control process flag to a value corresponding to step S1801 (decoration symbol variation start processing).

  Decoration symbol variation start processing (step S1801): Process data predetermined according to the variation pattern is selected, a process timer is started, and display control of the variable display device 9 is started. Thereafter, the value of the symbol control process flag is updated to a value corresponding to step S1802 (decorative symbol changing process).

  Decoration symbol variation processing (step S1802): Controls the switching timing of each variation state (variation speed, etc.) constituting the variation pattern, and monitors the end of the variation time. Thereafter, the value of the symbol control process flag is updated to a value corresponding to step S1803 (decorative symbol stop processing).

  Decoration symbol stop process (step S1803): When the variation time elapses, control is performed to stop the variation of the symbol and display the stop symbol (determined symbol). Thereafter, in the case of a big hit, the value of the symbol control process flag is updated to a value corresponding to step S1804 (big hit display process). Otherwise, the symbol control process flag value is updated to a value according to step S1800.

  Big hit display process (step S1804): After the end of the fluctuation time, the big hit display is controlled. Thereafter, the value of the symbol control process flag is updated to a value according to step S1805 (during big hit game).

  Big hit game processing (step S1805): Control during the big hit game is performed. For example, when an effect control command for display before opening of the big winning opening or display when opening the big winning opening is received, display control during the round or interval is performed. Further, when the big hit game is finished, a predetermined ending display indicating that the big hit game is finished is performed. Thereafter, the value of the symbol control process flag is updated to a value according to step S1800.

  Here, a sound / lamp control board 80b and a symbol control board 80a are provided as control boards on which a microcomputer for controlling the effect device is mounted, and the game control microcomputer 560 of the main board 31 is attached to the sound / lamp control board 80b. An effect control command is transmitted to the sound / lamp control microcomputer 100b mounted, and the sound / lamp control microcomputer 100b responds to the effect control command to the symbol control microcomputer 100a mounted on the symbol control board 80a. A description has been given of the case where the system is configured to transmit the received command. However, the game control microcomputer 560 transmits an effect control command to the symbol control microcomputer 100a, and the symbol control microcomputer 100a transmits a command corresponding to the effect control command to the sound / lamp control microcomputer 100b. It may be configured.

  FIG. 100 is an explanatory diagram showing another example of the contents of the effect control command sent to the sound / lamp control board 80b. In the example shown in FIG. 52, the probability variation jackpot designation command, the normal jackpot designation command, and the miss designation command are used as the display result commands. In the example shown in FIG. 100, effect control commands (91XX (H), 92XX (H), 93XX (H)) for designating stop symbols for the left, middle, and right decorative symbols are used as display result commands.

  When the effect control command shown in FIG. 100 is used, the probability variation big hit symbol of the decorative symbol (the combination of the decorative symbols that are stopped and displayed on the variable display device 9 when it is determined to be the probability variation big hit. For example, “7” “7 ”“ 7 ”) and a non-probable big hit symbol of a decorative symbol (ordinary big hit symbol: a combination of decorative symbols that are stopped and displayed on the variable display device 9 when it is determined to be a normal big hit, for example,“ 7 ”“ 7 "A combination of left, middle and right decorative patterns other than" 7 "). When the special design stop symbol setting process (see FIG. 55) determines the special symbol stop symbol, the game control microcomputer 560 also determines the decorative symbol stop symbol, and determines the determined decorative symbol stop symbol. An effect control command (91XX (H), 92XX (H), 93XX (H)) for designating the left middle right decorative symbol is transmitted to the sound / lamp control microcomputer 80b. The sound / lamp control microcomputer 80b transmits the effect control commands to the symbol control microcomputer 80a. The design control microcomputer 80a derives and displays a stop symbol of the decorative design on the variable display device 9 when the variable display time of the decorative design elapses according to the effect control commands.

  FIG. 101 is a block diagram showing another circuit configuration example of the relay board 77, the sound / lamp control board 80b, and the symbol control board 80a. When the circuit configuration shown in FIG. 101 is used, for example, the symbol control microcomputer 100a mounted on the symbol control board 80a follows the process similar to steps S1851 to S1856, based on the variation pattern command. Whether or not to perform, and the type of notice effect). Then, the symbol controlling microcomputer 100a causes the VDP 109 to perform a notice effect using the variable display device 9 in accordance with the determined effect contents. Further, the symbol control microcomputer 100a may generate an effect content designation command indicating the determined effect content and transmit it to the sound / lamp control board 80b. Then, the sound / lamp control microcomputer 100b mounted on the sound / lamp control board 80b performs display control of the lamps 25, 28a, 28b, 28c in accordance with the contents of the effect indicated in the received effect content designation command. Sound output control of the sound output device 27 may be performed.

  In this embodiment, the case where the sound / lamp control board 80b and the symbol control board 80a are used as the case where each effector is controlled using separate control boards has been described. Each effect device may be controlled using. For example, each rendering device may be controlled using a sound control board that controls the sound output device 27, a lamp control board that controls each lamp, and a symbol control board that controls the variable display device 9. In this case, for example, the effect control command from the main board 31 is first received by the sound control board, and the sound control microcomputer mounted on the sound control board receives the effect contents (notice effect) based on the received variation pattern command. Whether or not, and the type of the notice effect) may be determined (a process having the same contents as the process shown in FIG. 96). Then, the sound control microcomputer may transmit a command indicating the determined production contents to the lamp control board and the symbol control board (configuration to transmit to the symbol control board via the lamp control board or the symbol control board) Including a configuration of transmitting to the lamp control board via Further, each effect device may be controlled using a sound / symbol control board for controlling the sound output device 27 and the variable display device 9 and a lamp control board for controlling each lamp. In this case, for example, an effect control command from the main board 31 is received by the sound / symbol control board, and the sound / symbol control microcomputer mounted on the sound / symbol control board is based on the received variation pattern command. The contents of the effect may be determined (a process having the same contents as the process shown in FIG. 96). Then, the sound / symbol control microcomputer may transmit a command indicating the determined effect to the lamp control board. Note that the present invention is not limited to the combination of the above control boards, but a configuration in which an effect control command is transmitted from the main board 31 to the lamp control board and a command is transmitted from the lamp control board to the sound / symbol control board. May be.

  In addition, the sound control microcomputer identifies the number of decorative symbol shifts based on the display result designation command, and the decorative symbol variation time based on the basic time indicated by the variation pattern command and the decorative symbol shift number. May be specified. Then, the sound control microcomputer may generate a command including the determined content of the effect and the variation time (or add it to the effect control command) and transmit it to the lamp control board or the symbol control board. The production control command from the main board 31 is first received by the lamp control board or the design control board, and the microcomputer mounted on the lamp control board or the design control board determines the production contents or specifies the variation time. Also good.

  Note that the pachinko gaming machine of each of the above embodiments mainly has a predetermined game value when the stop symbol of the special symbol that is variably displayed on the variable display device 9 based on the start winning is a combination of the predetermined symbols. Pachinko machines that can be granted to a player, but if there is a prize in a predetermined area of an electric accessory that is released based on the start prize, a pachinko machine that can be given a predetermined game value or start Even if it is a pachinko machine where a predetermined right is generated or continued when there is a prize for a predetermined electric combination that is released when the symbol of the symbol variably displayed based on the winning combination becomes a combination of the predetermined symbols The invention can be applied. Furthermore, the present invention can be applied to a slot machine as long as it has a configuration including a main board and a payout control board.

  The present invention is applicable to gaming machines such as pachinko gaming machines and slot machines, and in particular, can be suitably applied to gaming machines equipped with a gaming control microcomputer incorporating a random number circuit and a serial communication circuit.

It is the front view which looked at the pachinko game machine from the front. It is a block diagram which shows the structural example of a game control board (main board). It is a block diagram which shows the circuit structure in a sound / lamp control board, and the circuit structure in a symbol control board. It is a block diagram which shows the circuit structure in a payout control board. It is a block diagram which shows the circuit structure in a power supply board. FIG. 10 is a block diagram showing a circuit configuration of a main board and signal lines of an effect control command transmitted from the main board to the sound / lamp control board. It is a block diagram which shows the structural example of a random number circuit. It is explanatory drawing which shows the example of an update rule selection register. It is explanatory drawing which shows the example of an update rule memory. It is explanatory drawing which shows the example in case a count value permutation change circuit changes the permutation of the count value which a counter outputs. It is explanatory drawing which shows the example of a count value permutation change register. It is explanatory drawing which shows the example of a random number maximum value setting register. It is explanatory drawing which shows the example of a period setting register. It is explanatory drawing which shows the example of a count value update register. It is explanatory drawing which shows the example of a random value taking-in register. It is explanatory drawing of an example of the random number update system selection register and the random number update system selection data written in the random number update system selection register. It is explanatory drawing which shows the example of a random number circuit starting register. It is a circuit diagram which shows one structural example of a random value storage circuit. It is a timing chart which shows the timing when each signal is input into a random value storage circuit, and the timing when a random value storage circuit outputs each signal. It is a block diagram which shows the structural example of the transmission part of a serial communication circuit. It is a block diagram which shows the structural example of the receiving part of a serial communication circuit. It is explanatory drawing which shows the example of the data format of the data which serial communication transmits / receives with each control board. It is explanatory drawing which shows the example of a baud rate register. It is explanatory drawing which shows the example of the control register A and communication format setting data. It is explanatory drawing which shows the example of the control register B and interrupt request setting data. It is a figure which shows the example of status register A and status confirmation data. It is a figure which shows the example of status register B and status confirmation data. It is explanatory drawing which shows the example of the control register C and error interrupt request setting data. It is explanatory drawing which shows the example of the data register with which a serial communication circuit is provided. It is explanatory drawing which shows an example of the address map of the storage area in the microcomputer for game control. It is explanatory drawing which shows an example of the address map in a user program management area. It is explanatory drawing which shows an example of initial value change system setting data. It is explanatory drawing which shows the structural example of a user program. It is explanatory drawing which shows the structural example of a random number circuit setting program. It is explanatory drawing which shows the operation | movement which updates the value of random R, or reads the value of random R, when the 1st random number update system is selected. It is explanatory drawing which shows the operation | movement which updates the value of random R, or reads the value of random R, when the 2nd random number update system is selected. It is explanatory drawing which shows each memory with which the microcomputer for game control is provided. It is explanatory drawing which shows the example of the table memory for jackpot determination. It is a flowchart which shows the main process which the microcomputer for game control performs. It is a flowchart which shows the main process which the microcomputer for game control performs. It is explanatory drawing which shows the example of an interruption process priority table. It is a flowchart which shows a random circuit setting process. It is a flowchart which shows a random number maximum value reset process. It is a flowchart which shows an initial value change process. It is a timing chart which shows the timing when each signal is input into a random number circuit, and the timing when each signal is generated in a random number circuit. 5 is a flowchart showing a serial communication circuit setting process. It is a flowchart which shows a timer interruption process. It is explanatory drawing which shows a software random number. It is a flowchart which shows a random circuit initial value update process. It is a flowchart which shows a count value permutation change process. It is a flowchart which shows an example of a special symbol process process. It is explanatory drawing which shows an example of the content of an effect control command. It is a flowchart which shows a starting port switch passage process. It is a flowchart which shows an example of a special symbol normal process. It is a flowchart which shows an example of a special symbol stop symbol setting process. It is a flowchart which shows an example of a fluctuation pattern setting process. It is a flowchart which shows an example of a special symbol change process. It is explanatory drawing which shows an example of the content of the control signal transmitted / received between the microcomputer for game control, and the microcomputer for payout control. It is a block diagram which shows the signal line etc. which are used for transmission / reception of a control signal and a control command. It is a timing chart showing an example of how to output a payout control signal and a payout control command. It is a flowchart which shows an example of a prize ball process. It is a flowchart which shows an example of the interruption process which a serial communication circuit performs with respect to an interruption request. It is explanatory drawing which shows the example of the bit allocation of the input port in a game control means. It is explanatory drawing which shows the example of a prize ball number table. It is a flowchart which shows a prize ball number addition process. It is a flowchart which shows a prize ball control process. It is a flowchart which shows a prize ball transmission waiting process. It is a flowchart which shows a prize ball number command transmission process. It is a flowchart which shows a prize ball transmission completion waiting process. It is a flowchart which shows a prize ball ACK waiting process. It is a flowchart which shows a prize ball re-transmission process. It is a flowchart which shows a prize ball abnormality detection process. It is a flowchart which shows the main process which the microcomputer for payout control performs. It is a flowchart which shows the timer interruption process which the microcomputer for payout control performs. It is a flowchart which shows payout control INT signal interruption processing. It is a flowchart which shows a payout stop flag control process. It is a flowchart which shows a payout motor control process. It is a flowchart which shows a main control communication process. It is explanatory drawing which shows an example of the counter used in payout control processing. It is a flowchart which shows a prize ball lending control process. It is a flowchart which shows prize ball payout number addition control. It is a flowchart which shows the payout start waiting process. It is a flowchart which shows a payout motor stop waiting process. It is a flowchart which shows payout passage waiting processing. It is a flowchart which shows payout passage waiting processing. It is explanatory drawing which shows the relationship between the kind of error, and the display of LED for an error display. It is explanatory drawing which shows an example of the change of the content of the counter used in prize ball payout control. It is explanatory drawing which shows the other example of the change of the content of the counter used in prize ball payout control. It is a flowchart which shows prize ball payout number addition control. It is a flowchart which shows prize ball payout number addition control. It is a flowchart which shows prize ball payout number addition control. It is a flowchart which shows a payout stop flag control process. It is a flowchart which shows a payout stop flag control process. It is a flowchart which shows the main process which the microcomputer for sound / lamp control performs. It is explanatory drawing which shows each random number used by a sound / lamp control process. It is a flowchart which shows the production content determination process which the microcomputer for sound / lamp control performs. It is a flowchart which shows the main process which the microcomputer for symbol control performs. It is a flowchart which shows the specific example of the command analysis process which the microcomputer for symbol control performs. It is a flowchart which shows the symbol control process process which the microcomputer for symbol control performs. It is explanatory drawing which shows the other example of the content of an effect control command. It is a block diagram which shows the circuit structure in a symbol control board, and the circuit structure in a sound / lamp control board.

Explanation of symbols

1 Pachinko machine 31 Game control board (main board)
37 Dispensing control board 56 CPU
80a Symbol control board 80b Sound / lamp control board 100a Symbol control microcomputer 100b Sound / lamp control microcomputer 370 Discharge control microcomputer 503a 12-bit random number circuit 503b 16-bit random number circuit 505 Serial communication circuit 521 Counter 522 Comparator 523 Counter value permutation change circuit 528 Selector 531 Random value storage circuit 560 Microcomputer for game control 714 Interrupt control circuit

Claims (11)

A gaming machine in which a player can play a game using a game medium, and pays out a predetermined number of game media as a prize according to establishment of a predetermined payout condition,
A game control microcomputer for controlling the progress of the game and transmitting a payout control command for instructing the number of payouts of game media based on a predetermined payout condition being satisfied;
A payout means for paying out game media;
Payout driving means for driving the payout means to pay out the game medium;
A payout control microcomputer that controls the payout driving means in accordance with the payout control command received from the game control microcomputer;
The dispensing control microcomputer is:
Drive amount data storage means for storing data capable of specifying the drive amount until the end of payout of the game medium by the payout drive means;
Drive amount updating means for subtracting the data stored in the drive amount data storage means by an amount corresponding to the drive amount of the payout drive means when the payout drive means is driving the payout means;
A storage means for storing data indicating the number of payouts of game media in response to the payout control command, the prize game medium number data storage means having a predetermined number of bits,
A prize game medium number data adding means for adding the number of payouts instructed by the payout control command to the data stored in the prize game medium number data storage means when the payout control command is received;
When the payout driving means is driving the payout means, the drive amount data storage means stores data indicating the drive amount according to the increase in the number of data stored in the prize game medium number data storage means. Drive amount data adding means for performing addition processing for adding to stored data;
A previous prize game medium number data storage means for storing data stored in the prize game medium number data storage means when the drive amount data addition means adds data;
The driving amount data adding means includes
A determination process executing means for executing a determination process for determining whether or not the data stored in the premium game medium number data storage means and the data stored in the previous premium game medium number data storage means match; ,
Before the determination process is executed by the determination process execution means, bits corresponding to the number exceeding the predetermined storage upper limit value among the predetermined number of bits in the premium game medium number data storage means have a stored value. Whether or not the corresponding valid value is indicated, and when the valid value is indicated, the bit includes an invalid value changing means for changing the bit to an invalid value corresponding to having no stored value,
The game machine, wherein the addition process is executed when the determination process execution means determines that the data does not match. A gaming machine in which a player can play a game using a game medium, and pays out a predetermined number of game media as a prize according to establishment of a predetermined payout condition,
A game control microcomputer for controlling the progress of the game and transmitting a payout control command for instructing the number of payouts of game media based on a predetermined payout condition being satisfied;
A payout means for paying out game media;
Payout driving means for driving the payout means to pay out the game medium;
A payout control microcomputer that controls the payout driving means in accordance with the payout control command received from the game control microcomputer;
The dispensing control microcomputer is:
Drive amount data storage means for storing data capable of specifying the drive amount until the end of payout of the game medium by the payout drive means;
Drive amount updating means for subtracting the data stored in the drive amount data storage means by an amount corresponding to the drive amount of the payout drive means when the payout drive means is driving the payout means;
A storage means for storing data indicating the number of payouts of game media in response to the payout control command, the prize game medium number data storage means having a predetermined number of bits,
A prize game medium number data adding means for adding the number of payouts instructed by the payout control command to the data stored in the prize game medium number data storage means when the payout control command is received;
When the payout driving means is driving the payout means, the drive amount data storage means stores data indicating the drive amount according to the increase in the number of data stored in the prize game medium number data storage means. Drive amount data adding means for performing addition processing for adding to stored data;
A previous prize game medium number data storage means for storing data stored in the prize game medium number data storage means when the drive amount data addition means adds data;
The driving amount data adding means includes
A determination process executing means for executing a determination process for determining whether or not the data stored in the premium game medium number data storage means and the data stored in the previous premium game medium number data storage means match; ,
Before the determination process is executed by the determination process execution means, the bit corresponding to the number exceeding the predetermined storage upper limit value of the predetermined bit number in the premium game medium number data storage means has a stored value. And an invalid value changing means for changing to an invalid value corresponding to not being,
The game machine, wherein the addition process is executed when the determination process execution means determines that the data does not match. The dispensing control microcomputer
An increase determination means for determining whether or not the data stored in the prize game medium number data storage means has increased when the payout driving means is driving the payout means;
An increase number specifying means for specifying an increase number when the increase determining means determines that the data is increasing; and
When the driving amount data adding means executes the addition processing, the previous prize game medium number data setting means for setting the data stored in the prize game medium number data storage means in the previous prize game medium number data storage means is included. The gaming machine according to claim 1 or 2. The payout control microcomputer includes initialization means for initializing data set in the previous prize game medium number data storage means when payout of game media is completed. A gaming machine according to any one of the above. The predetermined payout condition is established by winning a game medium in each of a plurality of winning areas provided in the gaming area,
Game medium detecting means for detecting a game medium won according to each of the plurality of winning areas and outputting a winning detection signal to a game control microcomputer;
The gaming machine according to any one of claims 1 to 4, wherein the game control microcomputer immediately transmits a payout control command in response to an input of the winning detection signal. The game control microcomputer includes a game control CPU that executes game control processing, and a serial communication circuit that performs serial communication with the payout control microcomputer.
The serial communication circuit includes an interrupt request means for generating an interrupt request for the game control CPU when a predetermined interrupt request condition is satisfied,
The interrupt request generated by the interrupt request means includes an error time interrupt request generated when a communication error occurs in the serial communication circuit,
The game control microcomputer is:
The game control process is executed based on the occurrence of a periodic timer interrupt,
Timer interrupt setting means for performing settings for generating the timer interrupt;
A serial communication circuit initial setting means for performing an initial setting of the serial communication circuit before the timer interrupt is set by the timer interrupt setting means when power supply to the gaming machine is started;
The gaming machine according to any one of claims 1 to 5, further comprising communication prohibiting means for prohibiting communication with the payout control microcomputer in the interrupt processing based on the error interrupt request. The game control microcomputer includes a game control CPU that executes game control processing and a random number circuit that generates random numbers.
The random number circuit includes:
Numerical value updating means for updating numerical data according to a predetermined order from a predetermined initial value to a predetermined final value in a predetermined range in which the numerical data can be updated based on an input of a predetermined signal;
Random number storage means for storing numerical data updated by the numerical value update means as a random value,
The game control microcomputer
The game control process is executed based on the occurrence of a periodic timer interrupt,
Timer interrupt setting means for performing settings for generating the timer interrupt;
Random number circuit initial setting means for performing initial setting of the random number circuit before the timer interrupt setting is set by the timer interrupt setting means when power supply to the gaming machine is started,
In the initial setting, the random number circuit initial setting means identifies the game control microcomputer in which the predetermined initial value of the numerical data updated by the numerical value update means is assigned to each game control microcomputer. The gaming machine according to any one of claims 1 to 6, wherein the gaming machine is set based on microcomputer identification information. Provided with variable display means capable of variably displaying a plurality of types of identification information that can identify each of them, and after the predetermined variable display execution condition is established, the identification information can be changed based on the establishment of the variable display start condition A gaming machine that starts display and shifts to a specific gaming state advantageous to the player when the display result of the variable display of identification information becomes a specific display result,
The game control microcomputer
Random number reading means for reading a random number value stored in the random number storage means;
Display result determining means for determining whether or not the display result of the variable display of the identification information is the specific display result when a variable display start condition is satisfied,
The display result determination unit determines whether the random value read by the random number reading unit matches a predetermined determination value, thereby setting the display result of the variable display of the identification information as a specific display result. The gaming machine according to claim 7, wherein it is determined whether or not. Provided with variable display means capable of variably displaying a plurality of types of identification information that can identify each of them, and after the predetermined variable display execution condition is established, the identification information can be changed based on the establishment of the variable display start condition A gaming machine that starts display and shifts to a specific gaming state advantageous to the player when the display result of the variable display of identification information becomes a specific display result,
A first electric component control board on which a first electric component control microcomputer for controlling the first electric component used for the game effect is mounted;
A second electric component control board mounted with a second electric component control microcomputer for controlling the second electric component used for the game effect,
The game control microcomputer
Display result determining means for determining whether or not the display result of variable display of identification information is the specific display result when a variable display start condition is satisfied;
Based on the determination result of the display result determining means, a variation pattern for variable display of the identification information is selected, and a variation pattern command capable of specifying the selected variation pattern is transmitted to the first electric component control microcomputer. Command transmission means,
The first electric component control microcomputer is:
Effect content determining means for determining the content of the game effect based on the variation pattern command received from the game control microcomputer;
A first electric component control side command transmitting means for transmitting a command capable of specifying the content of the game effect determined by the effect content determining means to the second electric component control microcomputer;
The second electric component control microcomputer controls the game effect using the second electric component based on the content of the game effect indicated by the command transmitted by the first electric component control side command transmission means. The gaming machine according to any one of claims 1 to 8. The first electric component control microcomputer includes command generation means for generating an effect content command that can specify the content of the game effect determined by the effect content determination means based on the variation pattern command,
The first electrical component control side command transmission means transmits the effect content command generated by the command generation means,
The second electrical component control microcomputer controls the game effect using the second electrical component based on the content of the game effect indicated by the effect content command transmitted by the first electrical component control side command transmission means. The gaming machine according to claim 9. The first electrical component control microcomputer includes an effect content adding means for adding the content of the game effect determined by the effect content determining means to the variation pattern command,
The first electrical component control side command transmission means transmits the variation pattern command to which the content of the game effect is added by the effect content adding means,
The second electrical component control microcomputer performs a game effect using the second electrical component based on the content of the game effect indicated by the variation pattern command transmitted by the first electrical component control side command transmission means. The gaming machine according to claim 9 to be controlled.

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