JP2013135914A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine that transmits and receives data reliably between an SDRAM and a CPU even if the CPU is used which does not include an SDRAM dedicated interface.SOLUTION: The game machine includes: a bus wiring 442 for connecting the CPU 404 to the SDRAM 408 and transmitting game data; a clock output circuit 405 for outputting a clock signal SDCLK for synchronizing the CPU 404 with the SDRAM 408; and a clock line wired shorter than the bas wiring 442 in length and connecting the clock output circuit 405 and the SDRAM 408 to each other, and transmitting the clock signal SDCLK therethrough.

Description

  The present invention relates to a game machine represented by a pachinko machine or the like.

2. Description of the Related Art Conventionally, there is a game machine having an electric circuit in which a ROM, SDRAM, or the like is connected to a dedicated interface provided in a CPU.
Conventionally, there is a game machine having an electric circuit in which a clock signal input to a CPU is also used as a clock signal input to a VDP.

JP 2008-200302 A

However, there is a problem that a CPU having a dedicated interface is expensive. Further, although a CPU having no dedicated interface is inexpensive, when such a CPU is used, a ROM, SDRAM, or the like is connected to the CPU bus. For this reason, in order to reliably transmit and receive data between the CPU and the SDRAM, a synchronization circuit for synchronizing the CPU and the SDRAM is required.
Further, when generating a dot clock signal sufficiently corresponding to the specifications of the display device from the clock signal input to the VDP, a dot clock signal generation circuit is required.
In either case, there may be a problem that the cost of the gaming machine is increased because the cost of the electric circuit used for the gaming machine is increased.

  An object of the present invention is to provide a game machine capable of reducing the cost.

The above purpose is
Image display means for displaying an image;
Image data generating means for generating image data;
Image data transmitting means for transmitting the image data generated by the image data generating means to the image display means;
First clock signal output means;
A game machine equipped with
The first clock signal output means outputs a first clock signal at a first frequency,
The first frequency is set based on the number of pixels provided in the image display means,
The image data generating means generates the image data by using a second clock signal having a second frequency generated from the first clock signal output from the first clock signal output means. Yes,
The second frequency is higher than the first frequency.
This is achieved by a game stand characterized by that.

  According to the present invention, it is possible to reduce the cost of a game machine.

It is the external appearance perspective view which looked at the pachinko machine 100 by one embodiment of this invention from the front side (player side). It is the external view which looked at the pachinko machine 100 by one embodiment of this invention from the back side. 1 is a schematic front view of a game board 200 of a pachinko machine 100 according to an embodiment of the present invention as viewed from the front. It is a circuit block diagram of the control part of the pachinko machine 100 by one embodiment of the present invention. FIG. 5 is a diagram schematically showing a circuit layout of a first sub-board 160 which is a pachinko machine 100 according to an embodiment of the present invention and shows a part of the components of the first sub-control unit 400 shown in FIG. 4. is there. FIG. 6 is a diagram showing a circuit layout of an actual board of the first sub board 160 shown in FIG. 5 in the pachinko machine 100 according to the embodiment of the present invention. It is a figure which shows the timing chart etc. of the operation | movement in the write cycle of SDRAM408 provided in the pachinko machine 100 by one Embodiment of this invention. It is a figure which shows the timing chart etc. of the operation | movement in the read cycle of SDRAM408 with which the pachinko machine 100 by one embodiment of this invention was equipped. It is a figure which shows the timing chart etc. of the operation timing of the clock signal SDCLK input into SDRAM408 provided in the pachinko machine 100 by one Embodiment of this invention, and a predetermined data signal. FIG. 2 is a diagram showing an example of a waveform of a clock signal at an input terminal of a clock signal SDCLK input to the SDRAM 408 and an arrangement position of the CPU 404 and the SDRAM 408 in the pachinko machine 100 according to the embodiment of the present invention. The pachinko machine 100 according to the embodiment of the present invention includes the number of pixels of the decorative symbol display device 208, the dot clock frequency determined based on the number of pixels, the maximum operable frequency of the VDP 434, and the maximum output frequency of the dot clock. FIG. It is a figure explaining each frequency of the system clock signal and dot clock signal which are generated in VDP434 provided in the pachinko machine 100 by one embodiment of the present invention. FIG. 7 is an enlarged view showing a vicinity of a mounting region of a VDP 434 of the first sub-board 160 shown in FIG. FIG. 13 illustrates a pachinko machine 100 according to an embodiment of the present invention, and illustrates a circuit configuration example of the hardware setting circuit 460 illustrated in FIG. The pachinko machine 100 according to the embodiment of the present invention includes the number of pixels of the decorative symbol display device 208, the dot clock frequency determined based on the number of pixels, the maximum operable frequency of the VDP 434, and the maximum output frequency of the dot clock. It is a figure which shows the other example of each of these. FIG. 6 is a diagram showing an example in which a sound source circuit 416 is connected to a bus wiring 442 in place of the VDP 434 and the CGROM 406a in the pachinko machine 100 according to the embodiment of the present invention. It is the schematic front view which looked at the slot machine as a game stand by the modification of one embodiment of this invention from the front. It is a figure which shows the game machine by the modification of one embodiment of this invention, (a) shows the casino machine 2000, (b) is a portable provided with the memory | storage part which memorize | stores the electronic data which implement | achieves this invention. A telephone 3000 is shown, (c) shows a portable game machine 4000 having a storage unit for storing electronic data for realizing the present invention, and (d) has a storage unit for storing electronic data for realizing the present invention. A home video game machine 5000 is shown, and (e) shows a data server 6000 storing electronic data for realizing the present invention.

  Hereinafter, a gaming machine (for example, a ball game machine such as a pachinko machine 100 or a spinning game machine such as a slot machine) according to an embodiment of the present invention will be described in detail with reference to the drawings. First, the overall configuration of the pachinko machine 100 according to the present embodiment will be described with reference to FIG. In addition, the figure is the external appearance perspective view which looked at the pachinko machine 100 from the front side (player side). As an external structure, the pachinko machine 100 includes an outer frame 102, a main body 104, a front frame door 106, a door 108 with a ball storage tray, a launching device 110, and a game board 200 on the front surface.

  The outer frame 102 is a wooden frame member having a vertical rectangular shape for fixing to an installation location (island facilities or the like) provided in a gaming machine installation sales shop. The main body 104 is referred to as an inner frame, and is a member that is provided inside the outer frame 102 and serves as a longitudinal rectangular gaming machine base body that is rotatably attached to the outer frame 102 via a hinge portion 112. The main body 104 is formed in a frame shape and has a space 114 inside. In addition, when the main body 104 is opened, an inner frame opening sensor (not shown) that detects the opening of the main body 104 is provided.

  The front frame door 106 is attached to the front surface of the main body 104 on the front side of the pachinko machine 100 so as to be openable and closable with a lock function, and is configured in a frame shape so that the inside Is a door member having an opening. The front frame door 106 is provided with a transparent plate member 118 made of glass or resin at the opening, and a speaker 120 and a frame lamp 122 are attached to the front side. A game area 124 is defined by the rear surface of the front frame door 106 and the front surface of the game board 200. Further, a front frame door opening sensor (not shown) that detects opening of the front frame door 106 when the front frame door 106 is opened is provided.

  The door 108 with a ball storage tray is a door member attached to the lower side of the main body 104 on the front surface of the pachinko machine 100 so as to have a lock function and be openable and closable. The ball storage tray-equipped door 108 is capable of storing a plurality of game balls (hereinafter simply referred to as “balls”), and an upper plate 126 provided with a passage for guiding the game balls to the launching device 110. A lower plate 128 that stores game balls that cannot be stored in the upper plate 126, a ball removal button 130 that discharges the game balls stored in the upper plate 126 to the lower plate 128 by the player's operation, A ball discharge lever 132 that discharges game balls stored in the lower plate 128 to a game ball collection container (common name, dollar box) by operation, and a game ball guided to the launching device 110 by operation of the player 200 ball launching handles 134 for launching into the game area 124, chance buttons 136 for changing the effects of the various effects devices 206 by the player's operation, and the chance button 136 to emit light. Sub button lamp 138, ball lending operation button 140 for instructing ball lending to a card unit (CR unit) installed in the game store, and return operation button for instructing the card unit to return the player's balance 142, and a ball rental display unit 144 for displaying the balance of the player and the state of the card unit. In addition, a lower plate full tank sensor (not shown) that detects that the lower plate 128 is full is provided.

  The launching device 110 is attached to the lower side of the main body 104, and a launching rod 146 that rotates when the ball launching handle 134 is operated by the player, and a launching rod 148 that strikes the game ball at the tip of the launching rod 146. .

  The game board 200 has a game area 124 on the front surface, and is detachably attached to the main body 104 using a predetermined fixing member so as to face the space 114 of the main body 104. The game area 124 can be observed from the opening after the game board 200 is mounted on the main body 104.

  FIG. 2 is an external view of the pachinko machine 100 of FIG. 1 viewed from the back side. The upper part of the back surface of the pachinko machine 100 has an opening that opens upward, a ball tank 150 for temporarily storing game balls, and a lower part of the ball tank 150 that is formed at the bottom of the ball tank 150. A tank rail 154 is provided for guiding a ball that has passed through the communicating hole and dropped to the dispensing device 152 located on the right side of the back surface.

  The payout device 152 is formed of a cylindrical member, and includes a payout motor, a sprocket, and a payout sensor (not shown) inside. The sprocket is configured to be rotatable by a payout motor. The sprocket that temporarily passes through the tank rail 154 and flows down into the payout device 152 is temporarily retained, and the payout motor is driven to rotate by a predetermined angle. Thus, the temporarily accumulated game balls are sent one by one downward to the payout device 152.

  The payout sensor is a sensor for detecting the passage of the game ball sent out by the sprocket. When the game ball is passing, either a high signal or a low signal is passed. Either the high signal or the low signal is output to the payout controller 600. The game ball that has passed through the payout sensor passes through a ball rail (not shown) and reaches the upper plate 126 disposed on the front side of the pachinko machine 100. The pachinko machine 100 has this configuration. To pay out the ball to the player.

  On the left side of the payout device 152 in the figure, a main board case 158 that houses the main board 156 that constitutes the main control section 300 that performs control processing for the entire game, and control related to effects based on the processing information generated by the main control section 300 The first sub-board case 162 that houses the first sub-board 160 that constitutes the first sub-control unit 400 that performs processing, and the second sub-board that performs control processing related to effects based on the processing information generated by the first sub-control unit 400. An error release switch that constitutes a second sub-board case 166 that houses the second sub-board 164 that constitutes the control unit 500, a payout control unit 600 that performs control processing related to the payout of game balls, and that releases an error by the operation of a game clerk Discharge board case 172 storing the payout board 170 having 168, launch base constituting the launch control unit 630 that performs control processing relating to the launch of the game ball A launch board case 176 that houses 174, a power control unit 660 that supplies power to various electrical gaming machines, and a power switch 178 that turns the power on and off by the operation of a game store clerk and an RWM clear by being operated when the power is turned on A power board case 184 that houses a power board 182 that includes an RWM clear switch 180 that outputs a signal to the main controller 300, and a CR interface 186 that transmits and receives signals between the payout controller 600 and the card unit are provided. ing.

  FIG. 3 is a schematic front view of the game board 200 as viewed from the front. In the game board 200, an outer rail 202 and an inner rail 204 are arranged, and a game area 124 in which a game ball can roll is defined. An effect device 206 is disposed in the approximate center of the game area 124. The effect device 206 is provided with a decorative symbol display device 208 at substantially the center, and around the normal symbol display device 210, the first special symbol display device 212, the second special symbol display device 214, and the normal symbol. A holding lamp 216, a first special symbol holding lamp 218, a second special symbol holding lamp 220, and a high-probability medium lamp 222 are provided. The effect device 206 performs the effect by operating the effect movable body 224, and details thereof will be described later. In addition, hereinafter, the normal symbol may be referred to as “general symbol”, the special symbol as “special symbol”, the first special symbol as “special symbol 1”, and the second special symbol as “special symbol 2”.

  The decorative symbol display device 208 is a display device for performing various displays used for decorative symbols and effects. In the present embodiment, the decorative symbol display device 208 is configured by a liquid crystal display device (Liquid Crystal Display). The decorative symbol display device 208 is divided into four display areas, a left symbol display area 208a, a middle symbol display area 208b, a right symbol display area 208c, and an effect display area 208d, and the left symbol display area 208a, the middle symbol display area 208b, and The right symbol display area 208c displays different decorative symbols, and the effect display area 208d displays an image used for the effect. Furthermore, the position and size of each display area 208a, 208b, 208c, 208d can be freely changed within the display screen of the decorative symbol display device 208. In addition, the decorative symbol display device 208 has a display range in which one small, for example, circular symbol can be displayed, and a fourth symbol display region (not shown in FIG. 3) provided at, for example, the lower left corner of the effect display region 208d. (Shown). In addition, although the liquid crystal display device is employ | adopted as the decoration symbol display apparatus 208, it is not a liquid crystal display device, What is necessary is just the structure which can display various effects and various game information, for example, a dot matrix display device Other display devices including a 7-segment display device, an organic EL (ElectroLuminescence) display device, a reel (drum) display device, a leaf display device, a plasma display, and a projector may be adopted.

  The general map display device 210 is a display device for displaying a general map, and is configured by a 7-segment LED in this embodiment. The special figure 1 display device 212 and the special figure 2 display device 214 are display devices for displaying the special figure, and are configured by 7-segment LEDs in the present embodiment.

  The multi-purpose hold lamp 216 is a lamp for indicating the number of general-purpose variable games (details will be described later) that are on hold. In this embodiment, the general-purpose variable games are reserved up to a predetermined number (for example, two). It is possible to do. The special figure 1 hold lamp 218 and the special figure 2 hold lamp 220 are lamps for indicating the number of special figure variable games that are held (details will be described later). In the present embodiment, a predetermined number of special figure variable games are displayed. It is possible to hold up to (for example, four). The high-probability medium lamp 222 is a lamp for indicating that the gaming state is a high-probability state in which a big hit is likely to occur or a high-probability state. Turns on when switching to the probability state, and turns off when switching from the high probability state to the low probability state.

  In addition, there are predetermined ball entrances such as a general prize opening 226, a general figure start opening 228, a special figure 1 start opening 230, a special figure 2 start opening 232, and a variable prize opening around the rendering device 206. 234 is provided.

  In the present embodiment, a plurality of general winning holes 226 are arranged on the game board 200, and when a predetermined ball detection sensor (not shown) detects a ball entering the general winning holes 226 (wins in the general winning holes 226). In this case, the payout device 152 is driven, and a predetermined number (for example, 10) of balls are discharged to the upper plate 126 as prize balls. The player can freely take out the balls discharged to the upper plate 126. With these configurations, the player can pay out the winning balls to the player based on winning. The ball that has entered the general winning opening 226 is guided to the back side of the pachinko machine 100 and then discharged to the amusement island side. In this embodiment, a ball to be paid out to a player as a consideration for winning may be referred to as a “prize ball”, and a ball lent to a player may be referred to as a “lending ball”. They are called “balls (game balls)”.

  The normal start port 228 is configured by a device called a gate or a through chucker for determining whether or not a ball has passed a predetermined area of the game area 124. In this embodiment, the left side of the game board 200 is used. One is arranged. Unlike the ball that has entered the general winning opening 226, the ball that has passed through the usual starting port 228 is not discharged to the amusement island side. When a predetermined ball detection sensor detects that the ball has passed through the normal map starting port 228, the pachinko machine 100 starts a normal map variable game by the general map display device 210.

  In the present embodiment, only one special figure 1 starting port 230 is provided at the center of the game board 200. When a predetermined ball detection sensor detects a ball entering the special opening 1 starting port 230, a payout device 152, which will be described later, is driven, and a predetermined number (for example, three) of balls are discharged to the upper plate 126 as prize balls. At the same time, the special figure variable game by the special figure 1 display device 212 is started. Note that the ball that has entered the special figure 1 starting port 230 is guided to the back side of the pachinko machine 100 and then discharged to the amusement island side.

  The special figure 2 starting port 232 is called an electric tulip (electrical chew). In the present embodiment, only one special opening 2 232 is disposed directly below the special figure 1 starting port 230. The special figure 2 starting port 232 includes a wing member 232a that can be opened and closed to the left and right. While the wing member 232a is closed, it is impossible to enter a sphere. When the winning symbol is stopped and displayed, the blade member 232a opens and closes at a predetermined time interval and a predetermined number of times. When a predetermined ball detection sensor detects a ball entering the special opening 2 232, the payout device 152 is driven, and a predetermined number (for example, four) of balls is discharged to the upper plate 126 as prize balls. Then, the special figure variable game by the special figure 2 display device 214 is started. The ball that has entered the special figure 2 starting port 232 is guided to the back side of the pachinko machine 100 and then discharged to the amusement island side.

  The variable winning opening 234 is called a big winning opening or an attacker, and in the present embodiment, only one variable winning opening 234 is arranged below the center of the game board 200. The variable winning opening 234 includes a door member 234a that can be freely opened and closed. When the door member 234a is closed, it is impossible to enter a ball, and the special symbol display device stops and displays the big hit symbol when the special symbol variable game is won. In this case, the door member 234a opens and closes at a predetermined time interval (for example, an opening time of 29 seconds and a closing time of 1.5 seconds) at a predetermined number of times (for example, 15 times). When a predetermined ball detection sensor detects a ball entering the variable winning opening 234, the payout device 152 is driven to discharge a predetermined number (for example, 15 balls) of balls to the upper plate 126 as prize balls. The ball that entered the variable winning opening 234 is guided to the back side of the pachinko machine 100 and then discharged to the amusement island side.

  Further, a plurality of disc-shaped hitting direction changing members 236 called a windmill and a plurality of game nails 238 are arranged in the vicinity of these winning openings and start openings, and at the bottom of the inner rail 204, An out port 240 is provided for guiding a ball that has not won a prize or starting port to the back side of the pachinko machine 100 and then discharging it to the game island side.

  The pachinko machine 100 supplies the ball stored in the upper plate 126 by the player to the launch position of the launch rail, drives the launch motor with strength according to the operation amount of the player's operation handle, The outer rod 202 and the inner rail 204 are passed by the launcher 148 and are launched into the game area 124. Then, the ball that has reached the upper part of the game area 124 falls downward while changing the advancing direction by the hitting direction changing member 236, the game nail 238, etc., and a winning opening (general winning opening 226, variable winning opening 234) or start opening (Special Figure 1 Start Port 230, Special Figure 2 Start Port 232) Wins the Out Port 240 without winning any of the winning ports or start ports, or just passing through the normal start port 228 To do.

  Next, the rendering device 206 of the pachinko machine 100 will be described. On the front side of the effect device 206, a warp device 242 and a stage 244 are arranged in an area where the game ball can roll, and an effect movable body 224 is arranged in an area where the game ball cannot roll. In addition, a decorative symbol display device 208 and a shielding device 246 (hereinafter sometimes referred to as a door or a shutter) are disposed on the back side of the effect device 206. That is, in the effect device 206, the decorative symbol display device 208 and the shielding means are located behind the warp device 242, the stage 244, and the effect movable body 224. The warp device 242 discharges the game balls that have entered the warp inlet 242a provided at the upper left of the effect device 206 to the stage 244 below the front surface of the effect device 206 from the warp outlet 242b. The stage 244 can roll a ball discharged from the warp outlet 242b or a ball that has been picked up by a nail of the game board 200, and the passed ball passes to the special opening 1 230 in the center of the stage 244. A special route 244a is provided to facilitate entry.

  In this embodiment, the effect movable body 224 includes an upper arm 224a and a forearm 224b imitating the upper arm and forearm of a human right arm, and an upper arm motor and an elbow (not shown) that rotate the upper arm 224a to the position of the shoulder A forearm motor (not shown) that rotates the forearm 224b at a position is provided. The effect movable body 224 moves in front of the decorative symbol display device 208 by the upper arm motor and the forearm motor.

  The shielding device 246 includes a lattice-like left door 246a and right door 246b, and is disposed between the decorative symbol display device 208 and the front stage 244. Belts wound around two pulleys (not shown) are fixed to the upper portions of the left door 246a and the right door 246b, respectively. That is, the left door 246a and the right door 246b move to the left and right as the belt driven by the motor through the pulley moves. When the left door 246a and the right door 246b are closed, the shielding means shields the inner end portions thereof so that it is difficult for the player to visually recognize the decorative symbol display device 208. In the state where the left door 246a and the right door 246b are opened, each inner end portion slightly overlaps the outer end portion of the display screen of the decorative symbol display device 208, but the player can visually recognize all of the display of the decorative symbol display device 208. It is. In addition, the left door 246a and the right door 246b can be stopped at arbitrary positions, respectively, for example, only a part of the decorative design so that the player can identify which decorative design the displayed decorative design is. Can be shielded. In addition, the left door 246a and the right door 246b may be configured so that a part of the decorative symbol display device 208 behind the lattice hole can be visually recognized, or the shoji part of the lattice hole is closed with a translucent lens body. The display by the decorative symbol display device 208 may be made vaguely visible to the player, or the shoji part of the holes in the lattice is completely blocked (shielded), and the decorative symbol display device 208 behind is made completely invisible. Also good.

  Next, the circuit configuration of the control unit of the pachinko machine 100 will be described in detail with reference to FIG. This figure shows a circuit block diagram of the control unit. The control unit of the pachinko machine 100 can be roughly classified into a main control unit 300 that controls the central part of the game and a command signal (hereinafter simply referred to as “command”) transmitted by the main control unit 300. A first sub-control unit 400 that controls the second sub-control unit 500 that controls various devices based on a command transmitted from the first sub-control unit 400, and a command transmitted by the main control unit 300 The payout control unit 600 that mainly controls the game ball payout, the launch control unit 630 that controls the launch of the game ball, and the power supply control unit 660 that controls the power supplied to the pachinko machine 100 are configured. Yes.

  First, the main control unit 300 of the pachinko machine 100 will be described. The main control unit 300 includes a basic circuit 302 that controls the entire main control unit 300. The basic circuit 302 includes a CPU 304, a ROM 306 for storing control programs and various data, and data temporarily. A RAM 308 for storing, an I / O 310 for controlling input / output of various devices, a counter timer 312 for measuring time and the number of times, and a WDT 314 for monitoring an abnormality in program processing are mounted. Note that another storage device may be used for the ROM 306 and the RAM 308, and this is the same for the first sub-control unit 400 described later. The CPU 304 of the basic circuit 302 operates by inputting a clock signal of a predetermined period output from the crystal oscillator 316b as a system clock.

  In addition, the basic circuit 302 includes a counter circuit 318 used as a hardware random number counter that changes a numerical value in the range of 0 to 65535 each time a clock signal output from the crystal oscillator 316a is received (this circuit includes two circuits). And a predetermined ball detection sensor, for example, a sensor that detects a game ball passing through each start port, winning port, variable winning port, front frame door opening sensor, and inner frame opening sensor. And a sensor circuit 322 for receiving signals output from various sensors 320 including a lower plate full sensor and outputting a comparison result with an amplification result or a reference voltage to the counter circuit 318 and the basic circuit 302, and a predetermined symbol display device For example, a drive circuit 324 for performing display control of the special figure 1 display device 212 and the special figure 2 display device 214, and a predetermined symbol display device, for example, A drive circuit 326 for performing display control of the display device 210 and various status display units 328 (for example, a general map hold lamp 216, a special figure 1 hold lamp 218, a special figure 2 hold lamp 220, a high accuracy medium lamp 222, etc.) Drive circuit 330 for performing display control, and various solenoids 332 for opening and closing a predetermined movable member, for example, a blade member 232a of the special drawing 2 starting port 232, a door member 234a of the variable prize opening 234, and the like. A drive circuit 334 is connected.

  When the ball detection sensor 320 detects that the ball has won the special figure 1 starting port 230, the sensor circuit 322 outputs a signal indicating that the ball has been detected to the counter circuit 318. Upon receiving this signal, the counter circuit 318 latches the value at the timing of the counter corresponding to the special figure 1 starting port 230, and uses the latched value as a built-in counter value storage register corresponding to the special figure 1 starting port 230. To remember. Similarly, when the counter circuit 318 receives a signal indicating that a ball has won the special figure 2 starting port 232, the counter circuit 318 latches the value corresponding to the timing of the counter corresponding to the special figure 2 starting port 232 at that timing. The obtained value is stored in a built-in counter value storage register corresponding to the special figure 2 starting port 232.

  Further, an information output circuit 336 is connected to the basic circuit 302, and the main control unit 300 is connected to an information input circuit 350 provided in an external hall computer (not shown) or the like via the information output circuit 336. 100 game information (for example, game state) is output.

  Further, the main control unit 300 is provided with a voltage monitoring circuit 338 for monitoring the voltage value of the power source supplied from the power source control unit 660 to the main control unit 300. The voltage monitoring circuit 338 has a voltage value of the power source. When the voltage is less than a predetermined value (9 V in this embodiment), a low voltage signal indicating that the voltage has decreased is output to the basic circuit 302.

  Further, the main control unit 300 is provided with a start signal output circuit (reset signal output circuit) 340 that outputs a start signal (reset signal) when the power is turned on, and the CPU 304 starts from the start signal output circuit 340. When a signal is input, game control is started (main control unit main processing described later is started).

  The main control unit 300 includes an output interface for transmitting a command to the first sub-control unit 400 and an output interface for transmitting a command to the payout control unit 600. With this configuration, the first control unit 300 Communication with the sub-control unit 400 and the payout control unit 600 is enabled. Information communication between the main control unit 300 and the first sub-control unit 400 and the payout control unit 600 is one-way communication. The main control unit 300 sends commands and the like to the first sub-control unit 400 and the payout control unit 600. The first sub control unit 400 and the payout control unit 600 are configured such that signals such as commands cannot be transmitted to the main control unit 300.

  Next, the first sub control unit 400 of the pachinko machine 100 will be described. The first sub-control unit 400 includes a basic circuit 402 that controls the entire first sub-control unit 400 mainly based on commands transmitted from the main control unit 300. The basic circuit 402 includes a CPU 404, An SDRAM 408 for temporarily storing data, an I / O 410 for controlling input / output of various devices, and a counter timer 412 for measuring time and frequency are mounted. The CPU 404 of the basic circuit 402 operates by inputting a clock signal of a predetermined period output from the crystal oscillator 414 as a system clock.

  The basic circuit 402 includes a ROM 406 for storing a control program and various effects data, a sound source circuit 416 for controlling the speaker 120 (and amplifier), and various lamps 418 (for example, a chance button lamp 138). A drive circuit 420 for performing control, a drive circuit 432 for performing drive control of the shielding device 246, a shielding device sensor 430 for detecting the current position of the shielding device 246, and a chance to detect pressing of the chance button 136 The button detection sensor 426, the sensor circuit 428 that outputs detection signals from the shielding device sensor 430 and the chance button detection sensor 426 to the basic circuit 402, and the image data stored in the CGROM 406a based on the signal from the CPU 404 are read out. Display using work area of VRAM 436 Are connected to the VDP (Video Display Processor) 434 for displaying an image on the decorative pattern display unit 208 generates an image, a. The VDP 434 operates by inputting a clock signal having a predetermined period output from the crystal oscillator 438. The ROM 406 includes a CGROM 406a that stores various effect data and a ROM 406b that stores a control program (see FIG. 5). However, the control program and the various effect data may be stored in the same ROM.

  Next, the second sub control unit 500 of the pachinko machine 100 will be described. The second sub-control unit 500 includes a basic circuit 502 that receives the control command transmitted from the first sub-control unit 400 via the input interface and controls the entire second sub-control unit 500 based on the control command. The basic circuit 502 includes a CPU 504, a RAM 508 for temporarily storing data, an I / O 510 for controlling input / output of various devices, and a counter timer 512 for measuring time and frequency. It is equipped with. The CPU 504 of the basic circuit 502 operates by inputting a clock signal of a predetermined period output from the crystal oscillator 514 as a system clock, and controls a control program and data for controlling the entire second sub-control unit 500, and an image display A ROM 506 storing data and the like is provided.

  The basic circuit 502 includes a drive circuit 516 for controlling the drive of the effect movable body 224, an effect movable body sensor 424 that detects the current position of the effect movable body 224, and a detection signal from the effect movable body sensor 424. Is output to the basic circuit 502, a game board lamp drive circuit 530 for controlling the game board lamp 532, and a game table frame lamp drive for controlling the game table frame lamp 542 The circuit 540 is connected to a serial communication control circuit 520 that performs lighting control by serial communication between the game board lamp drive circuit 530 and the game stand frame lamp drive circuit 540.

  Next, the payout control unit 600, the launch control unit 630, and the power supply control unit 660 of the pachinko machine 100 will be described. The payout control unit 600 controls the payout motor 602 of the payout device 152 mainly based on a command signal or the like transmitted from the main control unit 300, and a prize ball or a rental ball based on a control signal output from the payout sensor 604 It is detected whether or not the payout has been completed, and communication with a card unit 608 provided separately from the pachinko machine 100 is performed via the interface unit 606.

  The launch control unit 630 outputs a control signal output from the payout control unit 600 to permit or stop the launch, or a launch intensity output circuit provided in the ball launch handle 134 to operate the ball launch handle 134 by the player. Control of the launch motor 632 that drives the launcher 146 and launcher 148, and control of the ball feeder 634 that supplies the launcher 110 with a ball from the upper plate 126 based on a control signal that indicates the launch intensity according to the amount. I do.

  The power control unit 660 converts the AC power supplied from the outside to the pachinko machine 100 into a DC voltage, converts it to a predetermined voltage, and controls each control unit such as the main control unit 300 and the first sub control unit 400, the payout device 152, etc. Supply to each device. Further, the power supply control unit 660 supplies a power storage circuit (for example, a power supply circuit) for supplying power to a predetermined part (for example, the RAM 308 of the main control unit 300) for a predetermined period (for example, 10 days) even after the external power supply is cut off. , Capacitor). In the present embodiment, a predetermined voltage is supplied from the power supply control unit 660 to the payout control unit 600 and the second sub control unit 500, and the main control unit 300, the second sub control unit 500, and the launch control unit are supplied from the payout control unit 600. Although a predetermined voltage is supplied to 630, the predetermined voltage may be supplied to each control unit and each device through another power supply path.

  Next, the configuration of the first sub-control unit 400 provided in the pachinko machine 100 according to the present embodiment will be described with reference to FIGS. FIG. 5 is a diagram schematically showing a circuit layout of the first sub-board 160 extracted from some of the components of the first sub-control unit 400 shown in FIG. FIG. 6 is a circuit layout of the actual substrate of the first sub-board 160 shown in FIG. 5 and shows the arrangement positions of the components shown in FIG.

  As shown in FIGS. 5 and 6, the first sub-board 160 has bus wirings 442 that extend from substantially the center to the vicinity of the corners of the board. For example, the first sub-board 160 has a multilayer (for example, six layers) printed circuit board. The bus wiring 442 is wired in the inner layer of this printed circuit board, for example. The first sub-board 160 includes a crystal oscillator 414, a CPU 404, a crystal oscillator 438, a VDP 434, a CGROM 406a, a ROM 406b, and an SDRAM 408 mounted on the mounting surface of the printed circuit board. The CPU 404, the VDP 434, the ROM 406b, and the SDRAM 408 are mounted on, for example, the wiring area of the bus wiring 442 and are electrically connected to the bus wiring 442 through via holes (not shown) formed in the first sub-board 160 (hereinafter, referred to as “the wiring”). “Electrically connected” is abbreviated as “connected”).

  The CPU 404, the ROM 406b, and the SDRAM 408 are mounted across the bus wiring 442. The bus wiring 442 is formed in the shape of one-stroke writing wiring on one inner layer substrate so that the CPU 404 and the SDRAM 408 are disposed near both ends, for example. The VDP 434 is connected to a wiring formed on another inner layer substrate through a via hole formed in the middle of this one-stroke wiring, for example.

  As shown in FIG. 5, the crystal oscillator 414 is connected to an external clock signal input terminal EXTAL of the CPU 404, for example. For example, the crystal oscillator 414 outputs a clock signal having a frequency of 30.0 MHz to the CPU 404. The CPU 404 includes a clock output circuit 405 that outputs a clock signal SDCLK for synchronizing the SDRAM 408 with the microcomputer having the CPU 404 as a control unit. The clock output circuit 405 generates and outputs a clock signal SDCLK based on the clock signal output from the crystal oscillator 414. The CPU 404 performs game control based on the clock signal output from the crystal oscillator 414 or the clock signal output from the clock output circuit 405 and game data. For example, the game data includes lottery result information, game time measurement counter information (for 4.1 s timer, symbol variation time information), information for specifying an effect during execution, image / sound being reproduced, light emission Information for specifying an aspect, image information, sound information, information on an LED light emission aspect, and the like are included. The CPU 404 and the SDRAM 408 can be synchronized with each other by a clock signal SDCLK. The CPU 404 is connected to the SDRAM 408 via the clock line 440. The clock line 440 is wired on the surface layer of the printed circuit board which is a mounting surface of the CPU 404 and the like. As a result, the clock line 440 does not have a via hole portion for wiring in the inner layer, so that it may be possible to prevent an error due to a resistance component in the via hole portion. The clock signal SDCLK is input from the CPU 404 to the SDRAM 408 via the clock line 440.

  The VDP 434 has, for example, two clock signal input terminals DCLKI and PLLREF, a RAM 435, and an input / output terminal (not shown) connected to the CGROM 406a. A clock signal output terminal (not shown) of the crystal oscillator 438 is connected to the clock signal input terminals DCLKI and PLLREF. For example, the crystal oscillator 438 outputs a clock signal having a frequency of 33.264 MHz to the VDP 434. The relationship between the frequency of the clock signal output from the crystal oscillator 438 and the operating frequency of the VDP 434 will be described later.

  A CGROM 406 a is connected to the VDP 434. The CGROM 406a stores original image data corresponding to an image displayed on the decorative symbol display device 208. The CGROM 406a is a NOR type storage device.

  By the way, Japanese Laid-Open Patent Publication No. 2009-106308 discloses a game machine equipped with an image ROM storing image data. The game table disclosed in the publication uses a NAND-type image ROM capable of high-speed operation. On the other hand, as the image ROM, for example, a NOR-type ROM may be used to execute random access. The NOR type ROM may have a slower reading speed than the NAND type. In this case, even if a VDP capable of high-speed processing is operated at the maximum operable frequency, the entire processing time is delayed due to the delay time in image reading. As a result, the processing speed of the entire image processing is reduced, and there is a problem that power consumption increases due to the VDP operating at the maximum operable frequency. Thus, there are devices that consume a lot of power in circuit boards used in pachinko machines.

  Therefore, in the pachinko machine 100 according to the present embodiment, the VDP 434 operates at a frequency lower than the maximum operable frequency so that the VDP 434 consumes appropriate power. Thereby, the pachinko machine 100 may reduce the amount of heat generated while reducing the power required for image control. Furthermore, by suppressing the power consumption of the VDP 434, it is possible to use a small device of a low power type for the power supply system, and thus it is possible to design a compact circuit board.

  Next, the relationship between the clock line 440 connecting the CPU 404 and the SDRAM 408 and the bus wiring 442 will be described with reference to FIGS. In the pachinko machine 100 according to the present embodiment, for example, the wiring length of the clock line 440 connecting the CPU 404 and the SDRAM 408 is shorter than the wiring length of the bus wiring 442 connecting the CPU 404 and the SDRAM 408, for example. It has the characteristics. Thereby, the pachinko machine 100 according to the present embodiment may be able to reliably transmit and receive data between the CPU 404 and the SDRAM 408. Further, even if a synchronization circuit for synchronizing the CPU 404 and the SDRAM 408 is not provided, a CPU that does not have a dedicated interface for connecting to the SDRAM 408 can be used, so that the cost of the pachinko machine 100 can be reduced. There is a case. Hereinafter, a difference between the wiring length of the clock line 440 and the wiring length of the bus wiring 442 will be specifically described.

  A CPU provided in a conventional game machine has a dedicated interface for connecting to an SDRAM (nonvolatile storage device that operates in synchronization with an external clock), and the CPU and SDRAM directly transmit and receive data to and from each other. (For example, JP 2008-167840 A). However, the CPU having the interface has a problem that it is expensive. On the other hand, the CPU 404 provided in the pachinko machine 100 according to the present embodiment does not have a dedicated interface for connecting to the SDRAM, but can reliably perform the synchronous operation with the SDRAM 408 and is inexpensive. It has the advantage of being.

  FIG. 7 shows an operation timing chart of the SDRAM 408 in the write cycle (data write operation). FIG. 7A to FIG. 7C show the timing chart. FIG. 7A shows an example of the clock signal SDCLK observed at the clock signal input terminal of the SDRAM 408. The clock signal SDCLK1 shown by the wavy line in the figure is the wiring length of the clock line 440 connecting the CPU 404 and the SDRAM 408 ( In the description of FIGS. 7 and 8, hereinafter, the “wire length Ccs of the clock line 440” is referred to as the wiring length of the bus wiring 442 connecting the CPU 404 and the SDRAM 408 (in the description of FIGS. Represents a clock signal SDCLK observed at the clock signal input terminal of the SDRAM 408, and the clock signal SDCLK2 indicated by a solid line in the figure is the wiring of the clock line 440. When the length Ccs is shorter than the wiring length Bcs of the bus wiring 442, the SDCL It shows an example of a clock signal SDCLK observed at the input terminal 408 of the clock signal. FIG. 7B shows an example of the data signal 1 output from the CPU 404 observed at the data signal input terminal of the SDRAM 408 when the wiring length Ccs of the clock line 440 and the wiring length Bcs of the bus wiring 442 are equal. FIG. 7C schematically shows that the data signal 2 output from the CPU 404 is observed at the data signal input terminal of the SDRAM 408 when the wiring length Ccs of the clock line 440 is shorter than the wiring length Bcs of the bus wiring 442. An example of this is schematically shown. In addition, the passage of time is shown from left to right in FIGS. 7 (a) to 7 (c). FIG. 7D is a list for explaining some of the symbols shown in FIGS. 7A to 7C. The data signals 1 and 2 include, for example, game data, control command data for controlling the SDRAM 408, and the like.

  For example, the CPU 404 outputs the data signal after the data output delay time CdT elapses in synchronization with the rising edge of the clock signal SDCLK, and ends the output of the data signal after the data output hold time CTh elapses in synchronization with the next rising edge. The SDRAM 408 latches the data signal at the rising edge of the input clock signal SDCLK, for example, and writes the data in a predetermined storage area. In order for the SDRAM 408 to reliably latch the data signal, the data signal 1 must be held in advance on the data signal output side prior to the input setup time of the SDRAM 408 (rising (or falling) of the clock signal). It is necessary to input to the SDRAM 408 so as to satisfy STs and input hold time (time when the output side of the data signal must hold the data signal after the clock signal is issued) STh.

  For example, assuming that the wiring delay of the clock line 440 is equal to the wiring delay of the bus line 442, when the wiring length Ccs of the clock line 440 and the wiring length Bcs of the bus line 442 are equal, the wiring delay of both the wirings 440 and 442 is obtained. 7 (a) and 7 (b), when the CPU 404 starts the output operation of the data signal 1 at the timing of time te1, the data signal 1 has the data output delay time CdT. (For example, the maximum delay time 13 ns (nanosecond)) is input to the SDRAM 408 at the timing of the time te2 and the data output hold time CTh (for example, the minimum hold time) is synchronized with the rising edge of the clock signal SDCLK1 at the time te3. The output ends at time te4 after elapse of time 1ns). The data signal 1 input to the SDRAM 408 is latched at the rising edge of the clock signal SDCLK1 at the timing of the time te3 and written to a predetermined storage area of the SDRAM 408.

  The margin of the input setup time in the write cycle of the SDRAM 408 is from the period of the clock signal SDCLK1 (16.66 ns in this example) to the output delay time CdT of the CPU 404 and the input setup time STs of the SDRAM 408 (minimum value is, for example, 1.5 ns). Can be obtained by subtracting. When the wiring length Ccs of the clock line 440 and the wiring length Bcs of the bus wiring 442 are equal, the setup time margin wTsm1 in the write cycle is 2.16 ns (= 16.66 ns− (13 ns + 1.5 ns)). Further, the hold time margin in the write cycle of the SDRAM 408 can be obtained by subtracting the input hold time STh (minimum value is, for example, 0.8 ns) of the SDRAM 408 from the output hold time CTh of the CPU 404. When the wiring length Ccs of the clock line 440 and the wiring length Bcs of the bus wiring 442 are equal, the hold time margin wThm1 in the write cycle is 0.2 ns (= 1.0 ns−0.8 ns).

  As described above, when the wiring length Ccs of the clock line 440 and the wiring length Bcs of the bus wiring 442 are equal, the margin wThm1 of the input hold time in the write cycle of the SDRAM 408 is much larger than the margin wTsm1 of the input setup time. Becomes smaller.

  In order to increase the margin wThm1 of the input hold time, it is necessary to delay the input timing of the data signal 1 to the SDRAM 408 from the timing shown in FIG. In order to delay the input timing of the data signal 1 to the SDRAM 408, it is preferable to increase the wiring delay by increasing the wiring length Bcs of the bus wiring 442. However, since the bus wiring 442 has a large number of wirings, a wiring area necessary for lengthening the bus wiring 442 is widened, and the first sub-board 160 is enlarged. Therefore, in the pachinko machine 100 according to the present embodiment, the clock length of the bus line 442 is not changed and the clock length Bcs of the bus line 442 is not changed compared to the conventional pachinko machine in which the wiring length Ccs of the clock line 440 and the wiring length Bcs of the bus line 442 are equal. The wiring length Ccs of the line 440 is shortened. As a result, the pachinko machine 100 according to the present embodiment has a rising timing of the clock signal SDCLK input to the SDRAM 408 earlier than the timing at which the data signal is input to the SDRAM 408, compared to the conventional pachinko machine 100. The same effect as that obtained by delaying the signal input timing can be obtained.

  If the input timing of the data signal 2 to the SDRAM 408 when the wiring length Ccs of the clock line 440 is shorter than the wiring length Bcs of the bus wiring 442 is made coincident with the input timing of the data signal 1, FIGS. As shown in c), the clock signal SDCLK2 of the pachinko machine 100 according to the present embodiment rises earlier by Δt than the clock signal SDCLK1 of the conventional pachinko machine. As a result, the input hold time margin wThm2 in the present embodiment is larger by Δt than the conventional input hold time margin wThm1. As a result, the data signal output from the CPU 404 may be reliably transmitted to the SDRAM 408. The input setup time margin wTsm2 of the present embodiment is smaller than the conventional input setup time margin mThs1 by Δt. However, as described above, the setup time margin wTsm1 is relatively large at 2.16 ns. Therefore, even when the input hold time margin is reduced by Δt, the data signal can be reliably transmitted from the CPU 404 to the SDRAM 408.

  FIG. 8 shows an operation timing chart of the SDRAM 408 in a read cycle (data read operation). FIG. 8A to FIG. 8C show the timing chart. FIG. 8A shows an example of the clock signal SDCLK observed at the output terminal of the clock signal of the CPU 404, and the clock signal SDCLK1 indicated by the wavy line in the figure is changed from the wiring length Ccs of the clock line 440 to the wiring length Bcs of the bus wiring 442. An example of the clock signal SDCLK observed at the clock signal output terminal of the CPU 404 in the case where they are equal, the clock signal SDCLK2 shown by a solid line in the figure is when the wiring length Ccs of the clock line 440 is shorter than the wiring length Bcs of the bus wiring 442. An example of the clock signal SDCLK observed at the clock signal output terminal of the CPU 404 is shown. FIG. 8B shows an example of the data signal 1 read from the SDRAM 408 observed at the data signal input terminal of the CPU 404 when the wiring length Ccs of the clock line 440 and the wiring length Bcs of the bus wiring 442 are equal. FIG. 8C schematically shows data read from the SDRAM 408 that is observed at the data signal input terminal of the CPU 404 when the wiring length Ccs of the clock line 440 is shorter than the wiring length Bcs of the bus wiring 442. An example of the signal 2 is schematically shown. In addition, the passage of time is shown from left to right in FIGS. 8 (a) to 8 (c). FIG. 8D is a list for explaining some of the symbols shown in FIGS. 8A to 8C. The data signals 1 and 2 include game data and the like, for example.

  The SDRAM 408 reads the data signal after elapse of the read data output delay time SdT in synchronization with the rising edge of the clock signal SDCLK, for example, and finishes reading out the read data signal after elapse of the read data output hold time STh in synchronization with the next rising edge. . The CPU 404 latches the data signal read from the SDRAM 408 at the rising edge of the clock signal SDCLK, for example, and writes the data in a predetermined storage area. In order for the CPU 404 to reliably latch the data signal, the data signal needs to be input to the CPU 404 so as to satisfy the input setup time CTs and the input hold time CTh of the CPU 404.

  For example, when the wiring length Ccs of the clock line 440 and the wiring length Bcs of the bus wiring 442 are equal, the SDRAM 408 reads the data signal 1 at the timing of time te1, as shown in FIGS. 8A and 8B. When the operation is started, the data signal 1 is input to the CPU 404 at the time te2 after the elapse of the read data output delay time SdT (for example, the maximum delay time 5.4 ns), and read after the clock signal SDCLK1 rises at the time te3. The output ends at time te4 after the elapse of the data output hold time STh (for example, the minimum hold time 2.7 ns). The data signal 1 input to the CPU 404 is latched at the rising edge of the clock signal SDCLK1 at the timing te3 and stored in a predetermined storage area of the CPU 404.

  The margin of the input setup time in the read cycle of the SDRAM 408 is from the cycle of the clock signal SDCLK1 (16.66 ns in this example) to the read data output delay time SdT of the SDRAM 408 and the input setup time CTs of the CPU 404 (the minimum value is, for example, 8. 0 ns) can be subtracted. When the wiring length Ccs of the clock line 440 and the wiring length Bcs of the bus wiring 442 are equal, the setup time margin rTsm1 in the read cycle is 3.26 ns (= 16.66 ns− (5.4 ns + 8.0 ns)). Become. The margin of the read data hold time in the read cycle of the SDRAM 408 can be obtained by subtracting the input hold time CTh (minimum value is, for example, 2.0 ns) of the CPU 404 from the read data hold time CTh of the SDRAM 408. When the wiring length Ccs of the clock line 440 and the wiring length Bcs of the bus wiring 442 are equal, the read data hold time margin rThm1 in the read cycle is 0.7 ns (= 2.7 ns-2.0 ns).

  As described above, when the wiring length Ccs of the clock line 440 and the wiring length Bcs of the bus wiring 442 are equal, the margin rThm1 of the input hold time in the read cycle of the SDRAM 408 is much larger than the margin rTsm1 of the input setup time. Becomes smaller.

  As described above, in the pachinko machine 100 according to the present embodiment, the conventional pachinko machine in which the wiring length Ccs of the clock line 440 and the wiring length Bcs of the bus wiring 442 are equal to increase the margin of the input hold time in the write cycle. In contrast, the wiring length Ccs of the clock line 440 is shortened without changing the wiring length Bcs of the bus wiring 442. When the wiring length Ccs of the clock line 440 is shortened with respect to the wiring length Bcs of the bus wiring 442, the same effect as that obtained by extending the wiring length Bcs of the bus wiring 442 in the read cycle as well as the write cycle can be obtained. . That is, the input timing of the data signal 1 to the CPU 404 can be delayed from the timing shown in FIG.

  If the input timing of the data signal 2 to the CPU 404 when the wiring length Ccs of the clock line 440 is shorter than the wiring length Bcs of the bus wiring 442 is made coincident with the input timing of the data signal 1, FIG. As shown in c), the pachinko machine 100 according to the present embodiment has a rising timing of the clock signal SDCLK output from the CPU 404 relative to the input timing of the data signal input to the CPU 404, as compared with the conventional pachinko machine. The effect is the same as when the data signal input timing is delayed. For this reason, the read data hold time margin rThm2 in this embodiment is larger than the conventional read data hold time margin rThm1 by Δt. As a result, the data signal read from the SDRAM 408 may be reliably transmitted to the CPU 404 in some cases. In this embodiment, the read data setup time margin rTsm2 is smaller than the conventional read data setup time margin rThs1 by Δt. However, as described above, the read data setup time margin rTsm1 is relatively large at 3.26 ns. Therefore, even when the read data hold time margin is reduced by Δt, the data signal can be reliably transmitted from the SDRAM 408 to the CPU 404.

Next, a difference between the wiring length of the clock line 440 connecting the CPU 404 and the SDRAM 408 and the wiring length of the bus wiring 442 connecting the CPU 404 and the SDRAM 408 will be described. If the speed of electricity is V, the high speed in vacuum is C, the relative permittivity of the insulator covering the data line and the clock line is ε _0, and the relative permeability of the insulator is μ ₀ , the speed of electricity V Is represented by the following equation (1).
V = C / √ (ε ₀ × μ ₀ ) (1)
Further, when the increase time of the data hold time, that is, the time when the timing of the clock signal is accelerated (for example, Δt shown in FIGS. 7 and 8) is A, the difference in length DiffL between the clock line and the data line is Is represented by the following equation (2).
DiffL = A × V
= A × C / √ (ε ₀ × μ ₀ ) (2)

When Δt shown in FIG. 7 is increased by 100 ps (picoseconds), that is, when the increase time A = 100 ps as an example, the length of the clock line (for example, clock line 440) and the data line (for example, bus wiring 442) is increased. The difference value DiffL will be described. If the first sub-board 160 is formed of a glass epoxy board (FR-4) having a six-layer structure, the dielectric constant ε ₀ of the insulator is 4.7 and the relative permeability μ ₀ is 1. . The speed of light in vacuum is about 300,000 kilometers / second. For this reason, the electric speed V of the clock line 440 and the bus wiring 442 is 0.138 mm / ps from the equation (1). When the increase time A = 100 ps, the length difference value DiffL between the clock line 440 and the bus wiring 442 is 13.8 mm according to the equation (2). Therefore, by making the wiring length of the clock line 440 13.8 mm shorter than the wiring length of the bus wiring 442, the margin of the input hold time of the SDRAM 408 can be increased by 100 ps compared to the case where both wiring lengths are equal. There is.

  Next, the maximum value maxDiffL of the difference in length between the clock line 440 and the bus wiring 442 will be described with reference to FIG. FIG. 9 shows a timing chart showing the operation timing of the clock signal SDCLK and the predetermined data signal input to the SDRAM 408. FIG. 9A shows the timing chart. In the figure, the upper part shows the clock signal SDCLK, and the lower part shows predetermined data. FIG. 9B is a list of descriptions of symbols shown in FIG. 9A.

  As shown in FIG. 9A, in the SDRAM 408, for example, predetermined data is latched at the rising edge of the clock signal SDCLK. For example, the predetermined data includes game data, control command data for controlling the SDRAM 408, and the like. As shown in FIGS. 9A and 9B, the clock period of the clock signal SDCLK is represented by “F”, the input setup time of the SDRAM 408 is represented by “Ts”, and the input hold time of the SDRAM 408 is “ The margin (margin) of the input setup time of the SDRAM 408 is represented by “Tsm”, and the margin (margin) of the input hold time of the SDRAM 408 is represented by “Thm”. For example, the minimum value of the input setup time Ts of the SDRAM 408 is 1.5 ns, and the minimum value of the input hold time Tc is 0.8 ns.

By the way, in order to transmit and receive data most stably between the CPU 404 and the SDRAM 408, it is necessary that both the setup time and the hold time sufficiently satisfy the specifications of the CPU 404 and the SDRAM 408. That is, even if only one timing margin of the setup time and the hold time is secured, if the other timing margin is insufficient, the CPU 404 and the SDRAM 408 cannot latch the received data. Therefore, the maximum value maxDiffL of the difference in length between the clock line and the data line is obtained in the case of the increase time A of the data hold time set so that the margin of the input setup time and the margin of the input hold time are equal. It is done. Assuming that the period of the clock signal is F, the setup time is Ts, and the hold time is Th, the maximum value maxDiffL of the difference in length between the clock line and the data line is expressed by the following equation (3).
maxDiffL = 0.5 × (F− (Ts + Th)) × V (3)

  If the clock line 440 is made shorter than the bus wiring 442 and the time Δt at which the timing of the clock signal SDCLK is accelerated becomes too long, the input setup time STs of the SDRAM 408 and the read data input setup time CTs of the CPU 404 cannot be secured. As shown in FIGS. 7D and 8D, since the input setup time STs of the SDRAM 408 is shorter than the input setup time CTs of the CPU 404, there is room for the time when the timing of the clock signal SDCLK is accelerated. Therefore, the maximum value maxDiffL of the difference in length between the clock line 440 and the bus wiring 442 needs to be set so that the read data input setup time CTs of the CPU 404 can be secured.

  For example, the cycle F of the clock signal SDCLK is set to 16.66 ns, Ts in Expression (3) is set to the input setup time CTs of the CPU 404 = 8.0 ns, and Th in Expression (3) is set to the input hold time CTh of the CPU 404 = 2.0 ns. Then, the maximum value maxDiffL of the difference in length between the clock line 440 and the bus wiring 442 is 459 mm from the equation (3). In this case, the time Δt (increase time A) at which the clock signal SDCLK becomes faster is 3326 ps from the equation (2), and the margin of the input hold time of the SDRAM 408 increases by 3.326 ns.

  Thus, the margin of the input data hold time can be increased in the read and write cycles of the SDRAM 408. As a result, the CPU 404 and the SDRAM 408 communicate with each other even if the clock signal or the like deteriorates in quality due to variations in the rise time (or fall time) of the clock signal, reflection, or the like, or an error such as the wiring width or wiring length with respect to the design value occurs. May be able to be stabilized.

  Next, arrangement positions of the CPU 404 and the SDRAM 408 will be described with reference to FIG. FIG. 10 illustrates the voltage waveform of the clock signal at the input position of the clock signal SDCLK of the SDRAM 408 and the arrangement position of the CPU 404 and SDRAM 408. 10A shows Arrangement Example 1, FIG. 10B shows Arrangement Example 2, FIG. 10C shows an example of the clock signal waveform in Arrangement Example 1 in the upper stage, and Arrangement Example 2 in the lower stage. 2 shows an example of a clock signal waveform. In FIG.10 (c), a vertical axis | shaft represents a voltage and represents time passage from the left to the right.

  As shown in FIG. 10A, in the arrangement example 1, for example, the CPU 404 is connected to one end portion of the bus wiring 442 or the vicinity thereof, and the ROM 406b is connected to the other end portion or the vicinity thereof. The SDRAM 408 is connected to the bus wiring 442 between connection points where the CPU 404 and the ROM 406 b are connected to the bus wiring 442. As shown in FIG. 10B, in the arrangement example 2, for example, the CPU 404 is connected near one end of the bus wiring 442 and the SDRAM 408 is connected near the other end. The ROM 406 b is connected to the bus wiring 442 between connection points where the CPU 404 and the SDRAM 408 are connected to the bus wiring 442.

  Arrangement example 2 is less susceptible to reflection of clock signal SDCLK than arrangement example 1, and as shown in FIGS. 10C and 10B, the voltage waveform at the input terminal of clock signal SDCLK of SDRAM 408 is shown. There is little disturbance. Therefore, the arrangement example 2 is faster than the arrangement example 1 by the time Δt when the voltage level of the clock signal SDCLK reaches the high level input voltage VIH of the SDRAM 408. Thereby, for example, the margin of the input hold time of the SDRAM 408 may be increased.

  In this embodiment, for example, the bus wiring 442 includes a first signal line that connects the microcomputer having the CPU 404 as a control unit and the SDRAM 408, and a connection point on the bus wiring 442 that connects the ROM 406b and the bus wiring 442. A second signal line for connecting the ROM 406b (for example, a wiring for connecting the connection point on the bus wiring 442 and the ROM 406b) is included. As shown in FIGS. 5 and 6, the CPU 404 and the SDRAM 408 are arranged in the vicinity of both ends of the bus wiring 442, whereby the wiring from the CPU 404 to the connection point between the bus wiring 442 and the ROM 406 b and the second signal are displayed. The total length of the lines is longer than the length of the first signal line. Thereby, the influence of reflection of a clock signal or the like may be reduced.

  As shown in FIG. 5 and FIG. 6, if the CPU 404 → VDP 434 → ROM 406 b → SDRAM 408 are connected in this order from one end side of the bus wiring 422, the influence of reflection of the clock signal and the like is reduced, and the SDRAM 408 can be stabilized. In some cases, the image processing instruction to the VDP 434 can be stably performed.

  In this embodiment, the bus wiring 422 has a single-stroke wiring shape, so that the SDRAM 408 is less susceptible to reflection of a clock signal or the like than the star wiring shape. Further, by arranging the CPU 404 at one end of the bus wiring 422 having a one-stroke wiring shape and arranging the SDRAM 408 at the other end, the SDRAM 408 is further hardly affected by the reflection.

Next, the relationship between the frequency of the clock signal output from the crystal oscillator 438 and the operating frequency of the VDP 434 will be described with reference to FIGS.
An input clock signal is required for the VDP. Various common use is made for the clock signal input to the electrical components provided in the game machine according to the purpose. For example, Japanese Patent Laid-Open No. 2003-325871 discloses that a reference clock signal is used for a CPU system clock signal and a dot clock signal, and that a clock signal input to a CPU is also used as a clock signal input to a VDP. ing.

  However, in recent years, the specifications of a liquid crystal display device used as a decorative symbol display device provided in a gaming table are rarely changed from the resolution of the maximum specification that can be mounted within the regulations of the gaming table. Compared with the change of the specification of the liquid crystal display device, the VDP specification by 3D (three-dimensional) correspondence or the like is more frequently changed. Furthermore, in the gaming machine described in Japanese Patent Application Laid-Open No. 2003-325871, the dot clock signal is generated with a frequency set by a multiplier / divider circuit. There is a problem that it is difficult to generate a frequency that substantially matches the frequency of the dot clock signal determined based on the number of drawing processes.

  Generally, a system reference clock signal and a display dot clock signal are input to the VDP. The specification of YGV629 (VDP manufactured by Yamaha Corporation) describes that it is possible to supply only a reference clock and generate a dot clock from the reference clock. However, in the configuration in which the reference clock signal is multiplied and divided and used in the VDP, it is extremely difficult to generate the dot clock signal so that the frequency of the dot clock signal conforms to the specifications of the liquid crystal display device.

  Japanese Patent Laid-Open No. 2003-325871 does not describe the VDP system clock signal. In addition, since the frequency of the dot clock signal is determined based on the specifications of the liquid crystal display device, by multiplying the dot clock signal, It is not conceivable to generate a VDP system clock signal.

  Accordingly, the pachinko machine 100 according to the present embodiment reduces the cost of the circuit board by reducing the number of parts mounted on the circuit board while sharing the electrical parts, and the liquid crystal even if the number of parts is small. It has a feature that it can easily make settings sufficiently corresponding to the specifications of the display device and VDP. The pachinko machine 100 according to the present embodiment includes a left symbol display area 208a, a middle symbol display area 208b, a right symbol display area 208c, and an effect display area 208d of the decorative symbol display device 208 that displays information related to the game. A feature is that one clock signal set to a dot clock frequency determined based on the number of pixels in the display area is input to the system clock input terminal and the dot clock input terminal of the VDP 434.

  FIG. 11A shows the number of pixels of the decorative symbol display device 208 and the dot clock frequency determined based on the number of pixels. FIG. 11B shows the maximum operable frequency of the VDP 434 and the dot clock frequency. The maximum output frequency is shown. As shown in FIG. 11A, the decorative symbol display device 208 has, for example, 1056 pixels in the horizontal direction, 525 pixels in the vertical direction, and 554,400 pixels in the entire display area. have. Hereinafter, for example, one pixel is assumed to be composed of a red pixel, a green pixel, and a blue pixel. For example, if the number of frames to be displayed per second on the decorative symbol display device 208 is 60 fps (Frame Per Second), the dot clock frequency is determined to be 33.264 MHz (= 554, 400 × 60). As shown in FIG. 11B, the VDP 434 has, for example, a maximum operable frequency of 200 MHz, and a maximum frequency of a dot clock signal to be output is 110 MHz. The frequency of the dot clock signal is generally lower than the frequency of the system clock signal of VDP434.

  FIG. 12 is a diagram for explaining a system clock signal and a dot clock signal generated in VDP 434. 12A shows a circuit block diagram of a system clock signal and dot clock signal generation circuit in the VDP 434, and FIG. 12B shows initial setting values of the system clock signal and dot clock signal. (C) shows the set value of the frequency of the system clock signal. FIG. 13 is an enlarged view of the vicinity of the VDP 434 mounting region of the first sub-board 160 shown in FIG.

  As shown in FIG. 12A, the crystal oscillator 438 outputs a clock signal having a frequency of 33.264 MHz set based on the number of pixels of the decorative symbol display device 208 to the VDP 434. As shown in FIG. 12 (a), the frequency of the clock signal output from the crystal oscillator 438 is the frequency when image data corresponding to the image to be displayed on the decorative symbol display device 208 is transmitted at a specific number of times and at a specific cycle. Each time specified by both a specific number of times and a specific period is determined based on the number of pixels of the decorative design display device 208 for causing the decorative design display device 208 to display an image corresponding to the image data. Yes.

  For example, the VDP 434 divides the image data generated by the image data generation circuit 452 and the image data generation circuit 452 corresponding to the image to be displayed on the decoration symbol display device 208 into a specific number of times, and displays the decoration symbol display. An image data transmission circuit 454 that transmits to the device 208 at a specific cycle (for example, 30.06 ms = 1 / 33.264 MHz) is accommodated in a one-chip package. The VDP 434 is connected to an image data generation circuit 452 via a PLL (Phase Locked Loop) 456, a clock signal input terminal PLLREF for inputting a system clock signal, and an image data transmission circuit via a frequency divider 458. And a clock signal input terminal DCLKI for inputting a dot clock signal. As shown in FIG. 13, the crystal oscillator 438 is arranged closer to the clock signal input terminal PLLREF than the clock signal input terminal DCLKI. The VDP 434 has a first signal line 461 that connects the clock signal input terminal PLLREF and the crystal oscillator 438, and a length longer than the first signal line 461, and the first signal line 461 that connects the clock signal input terminal DCLKI and the crystal oscillator 438. 2 signal lines 462. Since the frequency of the system clock signal is higher than the frequency of the dot clock signal, it is easily affected by noise. For this reason, the influence of noise on the system clock signal may be reduced by disposing the crystal oscillator 438 in the vicinity of the clock signal input terminal PLLREF.

  Further, as a countermeasure against reflection of the clock signal, the first signal line 461 is provided with a damping resistor R1, and the second signal line 462 is provided with a damping resistor R2. By providing the damping resistors R1 and R2, there are cases where the system is stabilized and the image control process can be operated reliably.

  As shown in FIG. 12A, the VDP 434 has 4-bit setting terminals PLLMD3 to 0, to which a signal for setting the frequency of the system clock signal is input. A hardware setting circuit 460 is connected to the setting terminals PLLMD3 to PLLMD0. A PLL 456 provided in the VDP 434 is connected to the setting terminals PLLMD3 to 0 and the clock signal input terminal PLLREF. The PLL 456 is input by multiplying the frequency of the clock signal input from the clock signal input terminal PLLREF by an integral multiple of 1 to 14 based on the combination of the levels of the signal voltages input to the setting terminals PLLMD3 to PLLMD0. A system clock signal having a frequency higher than that of the clock signal is output to the image data generation circuit 452. The PLL 456 may be provided separately and independently from the VDP 434. The PLL 456 may include a frequency divider circuit 458.

  The VDP 434 includes a frequency divider 458 connected to the clock signal input terminal DCLKI. The frequency divider 458 divides the clock signal input from the clock signal input terminal DCLKI and outputs the divided clock signal to the clock signal output terminal DCLKO and the image data transmission circuit 454 as a dot clock signal. Note that the clock signal input from the clock signal input terminal DCLKI is also used to generate a communication clock signal.

  Next, frequency settings for the system clock signal and the dot clock signal will be described. As shown in FIG. 12B, the register DOV provided in the VDP 434 stores the setting values of the setting terminal PLLMD and the frequency division ratio of the dot clock signal. The initial value of the setting terminal PLLMD is set to “0000b” (“b” indicates a binary number), and the initial value of the frequency division ratio of the dot clock signal is set to “000b”. The set value stored in the register DOV is valid for both the write operation and the read operation as indicated by “R / W” in the item “R / W” in the rightmost column of FIG. It is.

  The setting terminals PLLMD3 to 0 are composed of 4 bits, the setting terminal PLLMD0 is the least significant bit, and the setting terminal PLLMD3 is the most significant bit. As shown in FIG. 12C, when the setting terminals PLLMD3 to 0 are set to “0000b”, the PLL 456 has a system clock signal having the same frequency (1 ×) as the frequency of the clock signal input from the clock signal input terminal PLLREF. Is output. When setting terminals PLLMD3 to 0 are set to “0001b”, PLL 456 outputs a system clock signal having a frequency twice that of the clock signal input from clock signal input terminal PLLREF. Similarly, when the setting terminals PLLMD3 to 0 are respectively set to “0010b” to “1101b”, the PLL 456 has a system clock having a frequency of 3 to 14 times the frequency of the clock signal input from the clock signal input terminal PLLREF. Each signal is output. In addition, setting the setting terminals PLLMD3 to 0 to “1110b” and “1111b” is prohibited.

  FIG. 14 shows a configuration example of the hardware setting circuit 460 shown in FIG. FIG. 14A shows a circuit configuration example of the hardware setting circuit 460, and FIG. 14B shows set values of the setting terminals PLLMD3 to PLLMD0.

  As shown in FIG. 14A, the hardware setting circuit 460 is configured to be able to input a signal having a voltage level of either a high level input voltage or a low level input voltage to the setting terminals PLLMD3 to PLLMD0. For example, the hardware setting circuit 460 can input a power supply voltage of 3.3V to the setting terminals PLLMD3 to 0 as a high level input voltage, and can input 0V (ground level) to the setting terminals PLLMD3 to 0 as a low level input voltage. It is configured. The multiplication rate of the PLL 456 can be set by hardware and does not need to be handled by software.

  In this embodiment, in order to set the frequency of the system clock signal to 6 times the frequency of the clock signal input to the clock signal input terminal PLLREF, the setting terminals PLL0 and PLL2 are connected to the power supply terminal 464 supplied with the power supply voltage. The setting terminals PLL1 and PLL3 are connected to the ground terminal 466, respectively. As a result, as shown in FIG. 14B, the setting values of the setting terminals PLLMD3 to PLLMD3 to “1010b” become “1010b”, and the PLL 456 receives the clock input to the clock signal input terminal PLLREF as shown in FIG. A system clock signal having a frequency six times that of the signal is generated and output to the image data generation circuit 452. Since the frequency of the clock signal input to the clock signal input terminal PLLREF is 33.264 MHz, the frequency of the system clock signal is 199.584 MHz. Thus, the frequency of the system clock signal is lower than the maximum operable frequency of VDP.

  Returning to FIG. 12A, the image data generation circuit 452 can generate image data corresponding to the image displayed on the decorative symbol display device 208 based on the maximum operable frequency of the VDP 434. In this embodiment, the image data generation circuit 452 generates image data using a system clock signal generated from a clock signal output from the crystal oscillator 438 and having a frequency lower than the maximum operable frequency of the VDP 434. The image data generation circuit 452 transfers the image data from the CGROM 406a to the VRAM 436 (see FIG. 4) based on a command from the CPU 404, and forms a display image in a predetermined display area of the VRAM 436. Further, the image data generation circuit 452 outputs image data corresponding to the display image to the image data transmission circuit 454. The image data generation circuit 452 executes these processes using a system clock signal of 199.584 MHz, for example.

  The image data transmission circuit 454 outputs the image data input from the image data generation circuit 452 to the decorative symbol display device 208 in synchronization with, for example, the rising edge of the dot clock signal output from the frequency divider 458. The frequency of the clock signal output from the crystal oscillator 438 is set to match the frequency of the dot clock signal necessary for displaying an image on the decorative symbol display device 208. For this reason, the frequency division ratio of the frequency divider 458 is set to 1/1 times the initial set value. The frequency divider 458 outputs a dot clock signal having a frequency of 33.264 MHz to the image data transmission circuit 454 and the clock signal output terminal DCLKO without dividing the clock signal input from the clock signal input terminal DCLKI.

  In the pachinko machine 100 according to the present embodiment, since the frequency of the clock signal output from the crystal oscillator 438 is set to be the same as the frequency of the dot clock signal, the decorative symbol display is performed even if the frequency divider 458 is not provided. The dot clock signal required to drive the device 208 can be generated. The VDP 434 operates without any problem even if it is not operated with the system clock signal having the maximum operable frequency as long as the frequency is within the range not exceeding the maximum operable frequency. The pachinko machine 100 according to the present embodiment receives the clock signal output from the crystal oscillator 438 and generates the system clock signal of the VDP 434. Therefore, unlike the gaming machine described in JP-A-2003-325871, the multiplication / It becomes easy to set the frequency of each clock signal by frequency division. Furthermore, in the present embodiment, the clock signal output from the crystal oscillator 438 is branched and input to the clock signal input terminals PLLREF and DCLKI provided in the VDP 434, and the damping resistors R1 and R2 are used as a countermeasure against reflection of the clock signal. Is provided.

  The main processing of the first sub control unit 400 in which the CPU 404 is mounted includes V sink interrupt waiting processing and WDT clear processing. In the V sync interrupt waiting process, it is monitored whether or not a V sync signal generated from the system clock signal is transmitted to the CPU 404. The pachinko machine 100 is reset if the V sync signal is not transmitted from the VDP 434 to the CPU 404 for a long time. As a result, it can be seen that an abnormality has occurred in the clock signal for VDP434.

  Next, another setting example of the frequency of each clock signal of the crystal oscillator 438 and the VDP 434 will be described with reference to FIG. In the setting example shown in FIG. 15A, the decorative symbol display device 208 has, for example, 800 pixels in the horizontal direction, 400 pixels in the vertical direction, and 320,000 pixels in the entire display area. Has pixels. For example, if the number of frames displayed per second on the decorative symbol display device 208 is 60 fps, the dot clock frequency (the frequency of the clock signal output from the crystal oscillator 438) is determined to be 19.200 MHz (= 320,000 × 60). The The multiplication rate of VDP 434 is set to 10 times (the setting value of setting terminals PLLMD3 to 0 is “1001b”), and the frequency of the system clock signal is set to 192.00 MHz, which is lower than the maximum operable frequency (200 MHz). The frequency of the clock signal output from the crystal oscillator 438 is set to match the frequency of the dot clock signal necessary for displaying an image on the decorative symbol display device 208. For this reason, the frequency division ratio of the frequency divider 458 is set to 1/1 times the initial set value.

  In the setting example shown in FIG. 15B, the decorative symbol display device 208 has, for example, 1280 pixels in the horizontal direction, 800 pixels in the vertical direction, and 1,04,000 in the entire display area. It has pixels. For example, if the number of frames displayed per second on the decorative symbol display device 208 is 30 fps, the dot clock frequency (the frequency of the clock signal output from the crystal oscillator 438) is 30.720 MHz (= 1,0244,000 × 30). It is determined. The multiplication rate of VDP 434 is set to 6 times (the setting value of setting terminals PLLMD3 to 0 is “0101b”), and the frequency of the system clock signal is set to 184.30 MHz, which is lower than the maximum operable frequency (200 MHz). The frequency of the clock signal output from the crystal oscillator 438 is set to match the frequency of the dot clock signal necessary for displaying an image on the decorative symbol display device 208. For this reason, the frequency division ratio of the frequency divider 458 is set to 1/1 times the initial set value.

  FIG. 16 shows an example in which a sound source circuit 416 is connected to the bus wiring 442 instead of the VDP 434 and the CGROM 406a. The tone generator circuit 416 includes a tone generator IC 416a, a sound ROM 416b, and a RAM 416c. Even when the sound source circuit 416 is connected to the bus wiring 442, the VDP 434 and the CGROM 406 a are connected to the bus wiring 442 by wiring the clock line 440 shorter than the bus wiring 442. The same effect as the case can be obtained.

  Even when the VDP 434, the CGROM 406a, and the sound source circuit 416 are connected to the bus wiring 442, the wiring length of the clock line 440 is shorter than the wiring length of the bus wiring 442, so that the VDP 434 and the CGROM 406a are connected to the bus wiring. The same effect as when connected to 442 can be obtained.

Next, the characteristic configuration of the pachinko machine 100 according to the present embodiment described above will be described with reference to FIGS. 1 to 16 again.
(1) The pachinko machine 100 according to the present embodiment displays predetermined game data (for example, information on a lottery result, information on a game time measurement counter (for 4.1s timer, for symbol variation time), and an effect being executed. A predetermined storage device (for example, SDRAM 408) in which information for specifying, information for reproduction of an image / sound, information for specifying a light emission mode, image information, sound information, and information on an LED light emission mode) are stored; A microcomputer that performs game control based on game data (for example, a circuit having a CPU 404 in a control unit), a data line for transmitting the game data while connecting the microcomputer and the predetermined storage device (for example, , Bus wiring 442) and a first clock signal (for example, for synchronizing the microcomputer and the predetermined storage device) For example, a first clock output circuit (for example, clock output circuit 405) that outputs a clock signal SDCLK) is wired shorter than the data line, and the first clock output circuit and the predetermined storage device are connected to each other. And a clock line (for example, a clock line 440) through which the first clock signal is transmitted.

  As described above, since the length of the clock line to which the first clock signal is transmitted is shorter than the length of the data line, the margin of the input hold time is increased, and data can be reliably transmitted / received. . In addition, there may be a case where the range of conditions of use environment (for example, use temperature) in which the game table can reliably transmit and receive data can be increased. In addition, the failure rate may be reduced due to individual differences such as manufacturing errors of the game machine. Further, even a CPU that does not have a dedicated interface used for connection with an SDRAM or the like does not require a synchronization circuit for synchronizing the CPU and the SDRAM or the like. For this reason, the number of components mounted on the electric circuit can be reduced, and the electric circuit can be downsized. Thereby, the cost of the electric circuit can be reduced and the cost of the game machine can be reduced.

(2) The pachinko machine 100 further includes a second clock output circuit (for example, a crystal oscillator 414) that outputs a second clock signal, and the microcomputer includes the first clock output circuit, A control circuit (e.g., CPU 404) that performs the game control based on the second clock signal output from the second clock output circuit, and the first clock output circuit includes the second clock output. The first clock signal is output based on the second clock signal output from the circuit. Thereby, there are cases where data can be transmitted and received reliably.

(3) In the pachinko machine 100, the electric speed is V, the high speed in vacuum is C, and the relative dielectric of an insulator (for example, a glass epoxy substrate (FR-4)) that covers the data line and the clock line. When the rate is ε ₀ , the relative permeability of the insulator is μ _0, and the increase time of the data hold time is A, the difference in length DiffL between the clock line and the data line is DiffL = A × V = A × C / √ (ε ₀ × μ ₀ ) The relational expression is satisfied. Thereby, there are cases where data can be transmitted and received reliably.

(4) In the pachinko machine 100, when the period of the first clock signal is F, the input setup time is Ts, and the input hold time is Th, the length of the first clock line and the data line The maximum value maxDiffL of the difference satisfies a relational expression of maxDiffL = 0.5 × (F− (Ts + Th)) × V. Thereby, since both the setup time and the hold time can be increased, there are cases where data can be transmitted and received more reliably.

(5) In the pachinko machine 100, the data line connects the microcomputer and the predetermined storage device, and a first signal line to which a predetermined signal is transmitted, and the first signal line A second signal line that connects a predetermined branch point and a predetermined electrical component (for example, ROM 406b, VDP 434, sound source IC 416a) and transmits a predetermined signal, and includes the microcomputer and the predetermined branch The length of the first signal line is longer than the length to the point and the total length of the second signal line. Thereby, the influence of reflection of a clock signal or the like may be reduced.

(6) The pachinko machine 100 according to the present embodiment has an image display device (for example, a decorative symbol display device 208) that displays information related to a game, and an image that generates image data corresponding to an image to be displayed on the image display device. A data generation circuit (for example, image data generation circuit 452) and the image data generated by the image data generation circuit are divided into specific times, and the image display device has a specific period (for example, a period of a dot clock signal). Corresponding to the image data generated by the image data generation circuit for each time specified by both the specific number of times and the specific period. A first clock having a frequency determined based on the number of pixels of the image display device for displaying an image on the image display device. A first clock output circuit (eg, a crystal oscillator 438) that outputs a signal, and the image data generation circuit generates a second clock generated from the first clock signal output from the first clock output circuit. The image data is generated based on a clock signal (for example, a system clock signal).

  As described above, since the dot clock signal and the system clock signal used by the image data generation circuit can be generated from the first clock signal output from the first clock output circuit, it is possible to reduce the size of the board and the number of electrical components. There are cases where it is possible.

(7) In the pachinko machine 100, the image data generation circuit can generate the image data based on a specific frequency (for example, the maximum operable frequency of the VDP 434). The frequency of the clock signal is lower than the specific frequency. As a result, the image data generation circuit may be able to reduce the power required for image control and the amount of heat generated.

(8) The pachinko machine 100 further includes an image control device (for example, a VDP 434) in which the image data generation circuit and the image data transmission circuit are housed in a one-chip package. A first terminal (for example, clock signal input terminal PLLREF) electrically connected to the data generation circuit and a second terminal (for example, clock signal input terminal DCKLI) electrically connected to the image data transmission circuit A first signal line (for example, the first signal line 461) connecting the first terminal and the first clock output circuit, and a length longer than the first signal line, And a second signal line (for example, a second signal line 462) connecting the second terminal and the first clock output circuit. Thereby, there are cases where the image control can be reliably operated.

(9) The pachinko machine 100 is characterized in that damping resistors (for example, resistors R1 and R2) are provided on both the first signal line and the second signal line. Thereby, there are cases where the image control can be reliably operated.

(10) The pachinko machine 100 includes a NOR-type ROM (for example, CGROM 406a) electrically connected to the image control device, and the ROM stores original image data used by the image data generation circuit. It is characterized by. By operating the image controller at a frequency that matches the performance of the peripheral components, in addition to saving power consumption and reducing the amount of heat generated, the data transmission / reception time with the peripheral components is reduced by reducing the data transmission / reception latency with the peripheral components. May be shortened.

  In the above embodiment, the CPU 404 of the first sub control unit 400 has been described as an example, but the present invention is not limited to this. For example, a microcomputer having a CPU as a control unit is provided in the main control unit 300 or the second sub-control unit 500, and any of the microcomputers having the CPU 304 or the CPU 504 in the control unit is the same as the above embodiment. May be obtained.

  In the above embodiment, the clock output circuit 405 is provided in the CPU 404, but the present invention is not limited to this. For example, even if the clock output circuit 405 is provided separately and independently from the CPU 404, the same effect as in the above embodiment may be obtained.

  In the above embodiment, the single data rate SDRAM 408 has been described as an example, but the present invention is not limited to this. For example, even a double data rate SDRAM (DDR SDRAM) and other electric circuits that operate in synchronization with an external clock signal or a predetermined signal may provide the same effects as those of the above embodiment.

  In the above embodiment, the CPU 404 is arranged near one end of the bus wiring 422 and the SDRAM 408 is arranged near the other end, but the present invention is not limited to this. For example, in the case where the pachinko machine 100 has an electrical component that is more susceptible to reflection of a clock signal or the like than the SDRAM 408, even if the electrical component is disposed in the vicinity of the other end of the bus wiring 422, the above-described implementation is performed. An effect similar to that of the form may be obtained.

  In the above embodiment, one SDRAM 408 is connected to the bus wiring 422, but the present invention is not limited to this. For example, even when two or more SDRAMs are connected to the bus wiring 422, or even if the SDRAM 408 is connected to each of the front and back surfaces of the printed circuit board on the terminal side of the bus wiring 422, the same as in the above embodiment May be obtained.

  In the above embodiment, the image data generation circuit 452 and the image data transmission circuit 454 are provided in the VDP 434, but the present invention is not limited to this. For example, even if the image data generation circuit 452 and the image data transmission circuit 454 are provided separately from the VDP 434, the same effects as in the above embodiment may be obtained.

  In the above embodiment, the frequency of the clock signal output from the crystal oscillator 438 matches the frequency of the dot clock signal, but the present invention is not limited to this. For example, even if the frequency of the clock signal output from the crystal oscillator 438 is an integer multiple of the frequency of the dot clock signal, the same effect as in the above embodiment may be obtained.

  In the above embodiment, a pachinko machine is used as an example of a game table, but the present invention is not limited to this. The present invention includes various devices including a predetermined circuit that transmits and receives data between an electric component that operates in synchronization with a clock signal or a predetermined signal and a microcomputer, an image processing unit, and a display unit. It can also be applied to devices.

For example, the present invention can be applied to a slot machine 1000 as shown in FIG.
The game machine according to the present invention corresponds to each reel shown in FIG. 17 as “a plurality of types of symbols 1002 and a plurality of reels 1002 which are rotationally driven, a start lever 1004 for instructing the rotation of the reels”. A stop button 1006 for individually stopping the rotation of the reels, lottery means (lottery prize internal lottery) for determining whether or not internal winning of a plurality of types of winning combinations is successful, and a lottery result of the lottery means The combination of symbols displayed by the reel stop control means (reel stop control processing) that performs stop control for stopping the rotation of the reels and the reels stopped based on the lottery result of the lottery means corresponds to the winning combination. And a determination means (winning determination process) for determining whether or not the symbol combination is predetermined, and when the symbol stop mode is a predetermined winning mode, it corresponds to the predetermined winning mode In addition to payout control means (medal payout process 1008) for performing game medium payout processing for paying out game media to be played, effect means 1010 for executing effects based on the lottery result of the lottery means is provided. A launching device 1014 that launches a ball into the game area 1012, a winning opening 1016 configured to be able to enter a ball launched from the launching device, a detection means 1018 that detects a ball that has entered the winning opening 1016, A payout means 1020 for paying out a ball when the detection means 1018 detects a ball, a variable display device 1022 for variably displaying a predetermined symbol (identification information), and a shutter 1024 movable to a position for shielding the variable display device 1022 And a movable body 1026 that operates in a predetermined operation mode, and the variable display device 1022 displays a symbol when the game ball enters the winning opening and wins. And the stopped displayed After moving, are also suitable for the slot machine 1000 "is a rendering device 1010, such as to produce a game.

  The above-mentioned game machines (for example, the pachinko machine 100 and the slot machine 1000), when a predetermined success / failure determination condition is satisfied (for example, when it is detected that a game ball has entered a predetermined area, (For example, whether or not to open a variable prize opening) A big lottery process for determining whether to release the electric tulip, a lottery process for determining whether to release the electric tulip, a bonus lottery process for determining whether or not to make a bonus state advantageous to the player, If a symbol stop operation is performed, a small symbol lottery process that displays a stop symbol pattern of a predetermined small character (such as a bell)) with a probability of 100% Or a process for determining whether or not the player is determined to be unsuccessful) and the result of the determination of success / failure by the determination unit is a specific success / failure determination result (for example, winning a big win, winning a winner, winning a big bonus role, winning a regular bonus role, small In the case of a winning combination, replay winning, etc., the probability that the player's advantage is the first advantage (eg, disadvantage) is the first control state (eg, normal state, the above-mentioned predetermined lottery process has a low probability) In a second control state (for example, the above-described normal state or the predetermined state), which is a second advantage (for example, more advantageous than the above-mentioned disadvantages) different from the first advantage. The control state transition hand that shifts the control state to a big hit state, a probability change state, an electric support state, a short time state, a big bonus state, a regular bonus state, a bonus state, etc. (E.g., a game controller, the main controller 300) and may be one having a.

  The above-described gaming machines (for example, the pachinko machine 100 and the slot machine 1000) are in a state advantageous to the player (for example, a big hit state, a big bonus state, etc.) when a predetermined symbol form is fixedly displayed on a predetermined symbol display device. Control state transition means (for example, game control means, main control unit 300) for shifting the control state to a regular bonus state, a bonus state, or the like may be provided.

  The gaming machine according to the present invention is shown in FIG. 18 (a). “Insert bills into bill insertion slot 2002, execute lottery based on bet 2004 and start 2006 operation, and display lottery result on lottery result display device 2008. Then, at the time of winning, the number of bonus coins is added to the remaining credit number, and when cashout 2009 is selected, the casino machine 2000 issues a receipt from the receipt issuing machine 2010 with a code corresponding to the remaining credit number. It may be.

  Furthermore, as shown in FIG. 5B, the cellular phone 3000 having a storage unit for storing the electronic data for realizing the present invention, and the electronic data for realizing the present invention as shown in FIG. The present invention may be applied to a portable game machine 4000 having a storage unit for storing the video data and a home video game machine 5000 having a storage unit for storing electronic data for realizing the present invention.

  More specifically, the mobile phone 3000 in FIG. 5B includes an operation unit operated by a player, a data acquisition unit that acquires data related to the game through a mobile phone line, and acquired data about the game (this book And a control unit that controls the game based on the data stored in the storage unit and the operation of the operation unit.

  The portable game machine 4000 in FIG. 6C includes an operation unit operated by a player, a data acquisition unit that acquires data related to the game from a predetermined storage medium (DVD or the like), and acquired data related to the game (the present invention). And a control unit for controlling the game based on the data stored in the storage unit and the operation of the operation unit. The home video game machine 5000 in FIG. 6D includes an operation unit operated by a player, a data acquisition unit that acquires data related to a game from a predetermined storage medium (DVD or the like), and acquired data ( And a control unit that controls the game based on the data stored in the storage unit and the operation of the operation unit.

  Furthermore, as shown in FIG. 5E, the present invention may be applied to a data server 6000 that stores electronic data for realizing the present invention. In some cases, the electronic data for realizing the present invention is downloaded from the data server 6000 to the home video game machine 5000 shown in FIG.

  In addition, a game can be executed by applying the present invention to a game program that simulates the operation of a real machine such as a pachinko machine for a home game machine. In that case, a DVD-ROM, CD-ROM, FD (flexible disk), or any other recording medium can be used as a recording medium for recording the game program.

Furthermore, the present invention has been described by taking a pachinko machine and a slot machine as examples of game machines, but the present invention is not limited thereto, and may be applied to an arrangement ball game machine, a ball ball game machine, a smart ball, and the like.
The present invention can be summarized as follows.
(Appendix 1)
A predetermined storage device in which predetermined game data is stored;
A microcomputer for performing game control based on the game data;
A data line for connecting the microcomputer and the predetermined storage device and transmitting the game data;
A first clock output circuit for outputting a first clock signal for synchronizing the microcomputer and the predetermined storage device;
A clock line that is wired shorter than the data line, connects the first clock output circuit and the predetermined storage device, and transmits the first clock signal. To play.
(Appendix 2)
In the game stand described in Appendix 1,
A second clock output circuit for outputting a second clock signal;
The microcomputer is
The first clock output circuit;
A control circuit for performing the game control based on the second clock signal output from the second clock output circuit;
Including
The game machine according to claim 1, wherein the first clock output circuit outputs the first clock signal based on the second clock signal output from the second clock output circuit.
(Appendix 3)
In the game stand according to appendix 1 or 2,
The electrical speed is V, the high speed in vacuum is C, the relative permittivity of the insulator covering the data line and the clock line is ε ₀ , the relative permeability of the insulator is μ ₀ , and the data hold time If the increase time of A is A, the difference in length DiffL between the clock line and the data line is
DiffL = A × V
= A × C / √ (ε ₀ × μ ₀ )
A game table characterized by satisfying the following relational expression.
(Appendix 4)
In the game stand described in Appendix 3,
Assuming that the period of the first clock signal is F, the input setup time is Ts, and the input hold time is Th, the maximum difference maxDiffL between the lengths of the first clock line and the data line is
maxDiffL = 0.5 × (F− (Ts + Th)) × V
A game table characterized by satisfying the following relational expression.
(Appendix 5)
In the game stand according to any one of appendices 1 to 4,
The data line is
A first signal line for connecting a predetermined signal to the microcomputer and the predetermined storage device;
A second signal line for connecting a predetermined branch point in the first signal line and a predetermined electrical component and transmitting a predetermined signal;
A gaming table, wherein a length of the first signal line is longer than a length obtained by adding the microcomputer to the predetermined branch point and a length of the second signal line.

100 Pachinko machine 136 Chance button 160 First sub-board 208 Decorative symbol display device 208a Left symbol display region 208b Middle symbol display region 208c Right symbol display region 208d Effect display region 226 General prize opening 228 Universal drawing start port 230 Special figure 1 start port 232 Special Figure 2 Start Port 234 Variable Prize Port 300 Main Control Unit 400 First Sub Control Unit 404 CPU
405 clock output circuit 408 SDRAM
414, 438 Crystal oscillator 434 VDP
440 Clock wiring 442 Bus wiring 452 Image data generation circuit 454 Image data transmission circuit 456 PLL
458 frequency divider 460 hardware setting circuit 500 second sub-control unit

Claims (4)

Image display means for displaying an image;
Image data generating means for generating image data;
Image data transmitting means for transmitting the image data generated by the image data generating means to the image display means;
First clock signal output means;
A game machine equipped with
The first clock signal output means outputs a first clock signal at a first frequency,
The first frequency is set based on the number of pixels provided in the image display means,
The image data generating means generates the image data by using a second clock signal having a second frequency generated from the first clock signal output from the first clock signal output means. Yes,
The second frequency is higher than the first frequency.
A game stand characterized by that. The game stand according to claim 1,
The image data generation means includes a multiplication circuit that generates a signal having a predetermined frequency.
The multiplication circuit can set any one of multiple types of multiples,
A setting circuit for setting the multiple,
A game stand characterized by that. The game stand according to claim 1 or 2,
The second frequency is a frequency lower than the operable maximum frequency set in the image data generating means.
A game stand characterized by that. It is a game stand as described in any one of Claims 1-3,
The image data generation means is a video display processor that is provided as a single chip and includes at least the image data transmission means.
A game stand characterized by that.

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