JP4624928B2 - Semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device (hereinafter also referred to as LSI), and more particularly to a technique effective when applied to the configuration of a clock generation portion of the device.

  As a technique studied by the present inventor, for example, the following technique can be considered in the clock generation portion of the semiconductor integrated circuit device.

  Conventionally, a system clock used by an LSI (Large Scale Integrated Circuit) has a clock configuration generated from a common PLL (Phase Locked Loop). For this reason, when the system clock of the LSI chip is changed, the clock frequency to a module (such as SCIF / IREM / USB) that requires a fixed frequency is changed, and various settings (baud rate) of each module are changed from the beginning. It must be made. This is expected to have a large overhead when considering an LSI chip system, and when considering low power consumption, it becomes difficult to change the operating frequency according to the operating state of the system frequency.

  It is also possible to prepare a PLL for each clock that requires a module, but it has a large effect on power consumption and silicon size, and requires a large number of asynchronous bridges. It is not realistic in an LSI having a plurality of ICs.

  For example, the LSI chip system operates according to the following procedure.

  When the power is turned on, it operates according to the following procedure.

  (1) The system clock frequency used for the CPU, external bus interface (I / F), built-in module, etc. is set.

  (2) Based on the frequency of the system clock, a module that operates at a fixed frequency is set.

  (3) Set the operation of the communication partner.

  When changing the frequency, the following procedure is used.

  (1) Change the setting of the frequency of the system clock used for the CPU, external bus interface (I / F), built-in module, and the like.

  (2) Based on the frequency of the system clock determined in (1), the setting of the module operating at a fixed frequency is changed.

  (3) Change the operation setting of the communication partner.

  The system clock means a variable frequency clock such as a CPU clock, a bus clock, an internal module clock.

Further, as such a clock generation technique, for example, a technique described in Patent Document 1 can be cited.
JP 2002-108490 A

  By the way, as a result of examination of the technique of the clock generation part of the semiconductor integrated circuit device as described above, the following has been clarified.

  That is, every time the operating frequency of the system clock is changed, it is necessary to set again a module that operates at a fixed frequency. In particular, since the setting change on the communication partner side in (3) at the time of the frequency change requires a handshake, the overhead of execution time on the LSI system is large, and the dynamic frequency change itself is a chip system. It may be impossible.

  In addition, the fixed frequency value is affected by the change of the system clock frequency.

  Accordingly, an object of the present invention is to provide a clock generation technique capable of reducing overhead in a semiconductor integrated circuit device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, in the semiconductor integrated circuit device according to the present invention, the frequency-variable system clock and the clock system for the fixed frequency communication circuit are separately provided, and a dedicated PLL is provided for each, and the frequency of the system clock is changed. The clock system for the fixed frequency communication circuit is not affected by the change.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  Even when the frequency (frequency multiplication ratio / division ratio) of the system clock with variable frequency is changed, the clock system for the fixed frequency communication circuit is not affected by the frequency change of the system clock, and thus overhead is reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted. In the following description, unless otherwise specified, a symbol representing a terminal name also serves as a wiring name and a signal name, and also serves as a voltage value in the case of a power supply.

  FIG. 1 is a block diagram showing the configuration and operation of a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a block diagram showing the internal bus configuration of the semiconductor integrated circuit device of this embodiment, and FIG. 5 is a timing chart showing an operation at a frequency change in the semiconductor integrated circuit device of the embodiment.

  First, an example of the configuration of the semiconductor integrated circuit device according to the present embodiment will be described with reference to FIG. The semiconductor integrated circuit device of this embodiment is, for example, an LSI 100 such as a microprocessor, a microcontroller, or a one-chip microcomputer, and is formed on one semiconductor chip by a well-known semiconductor manufacturing technique. The LSI 100 includes, for example, a clock generation unit 101 that multiplies and divides the external clock 1 and the external clock 2 to generate a clock for each module, and a clock control unit 102 that performs clock source setting, PLL setting, frequency division setting, and the like. A CPU 103, a bus interface (I / F) 104 for connecting to an external memory 116 connected to the outside of the semiconductor integrated circuit device, a DMAC, 3DIP (3D image processing IP), an image system IP, a timer A built-in module 105 such as a card interface (I / F), a serial interface (I / F) 106 for performing serial communication, an audio interface (AUDIO I / F) 107 for transmitting / receiving audio data, and a USB (Universal Serial Bus) communication It comprises a USB interface (I / F) 108 and the like.

  The clock generation unit 101 includes PLL circuits 109a and 109b that multiply an external clock, frequency dividing circuits 110a and 110b that divide and output the multiplied clock to each module, selection circuits 111a to 111e that select a clock, and the like. It is composed of

  The clock control unit 102 sets a clock source selection, a clock source setting register (REG) 112, a PLL setting register (REG) 113 for setting a multiplication rate of the PLL circuits 109a and 109b, and a frequency division setting. A frequency division setting register (REG) 114 for performing, a bus stop control circuit 115 for controlling the operation of the internal bus, and the like are included. These registers can be read / written by the CPU 103 via the bus. Further, the frequency division setting register (REG) 114 can be set for each module.

  The serial I / F 106 and the AUDIO I / F 107 have frequency dividing circuits 110c and 110d, respectively.

  The external clock of the LSI 100 is supplied from the external clock 1 and the external clock 2 through the clock terminal.

  A frequency variable clock such as a CPU clock, an external bus clock, and an internal module clock is output from the frequency dividing circuit 110a via the selection circuit 111c.

  A frequency-fixed clock such as a serial clock, an audio (AUDIO) clock, or a USB clock is output from the frequency dividing circuit 110b via the selection circuits 111d and 111e.

  The bus I / F 104 is connected to an external memory 116 (flash memory, SDRAM, etc.), the serial I / F 106 is connected to an external LSI 117, the AUDIO I / F 107 is connected to an external LSI 118, and the USB I / F 108 is connected to an external LSI 119.

  Next, an example of the internal bus configuration of the LSI 100 will be described with reference to FIG.

  As shown in FIG. 2, in the LSI 100, the CPU 103a, 3DIP 105a are connected to the internal bus 120a, the CPU 103b, the bus I / F 104, and the DMAC 105c are connected to the internal bus 120b. 105f is connected to the internal bus 120c, and the serial I / F 106a, serial I / F 106b, USB I / F 108, card I / F 105g, and clock generation unit 101 are connected to the internal bus 120e. The internal bus 120a and the internal bus 120b are connected via a bus (BUS) bridge 121a, and the internal bus 120a and the internal buses 120c and 120d are connected via bus (BUS) bridges 121b and 121c. 120b and the internal bus 120e are connected via a bus (BUS) bridge 121d.

  The 3DIP 105a is an IP such as an accelerator for three-dimensional display. The image system IP 105d is an IP (Intellectual Property) such as an image input / output of a camera or the like, or an MPEG operation. The image system IP 105e is an IP such as an LCD driver. The AUDIO I / F 107 is an IP such as voice compression / decompression.

  In FIG. 2, AUDIO I / F 107, serial I / F 106a, serial I / F 106b, and USB I / F 108 are fixed clock modules, and others are variable clock modules.

  Next, an example of the operation of the LSI 100 will be described.

  First, the variable clock system is generated from the external clock 1. The clock input from the external clock 1 is multiplied in the PLL circuit 109a. The multiplied clock is divided by the frequency dividing circuit 110a. The divided clocks (1, 2, 4, 8, 16,...) Generated by the frequency dividing circuit 110a are distributed by the selection circuit 111c, and the CPU 103, the bus are used as the CPU clock, the external bus clock, and the internal module clock. Supplied to the I / F 104 and the built-in module 105. At this time, the setting of the multiplication rate of the PLL circuit 109a is determined by the value of the PLL setting REG113, and the setting of the frequency dividing ratio of the frequency dividing circuit 110a is determined by the value of the frequency division setting REG114.

  Next, the fixed clock system can select a clock source from both the external clock 1 and the external clock 2. The clock selected based on the value of the clock source setting REG112 is multiplied by the PLL circuit 109b. The multiplied clock is divided by the frequency dividing circuit 110b. The divided clocks (divided by 1, 2, 4, 8, 16...) Generated by the frequency dividing circuit 110b are distributed by the selection circuit 111d, and the serial I / F 106, serial clock, AUDIO clock, USB clock, Supplied to AUDIO I / F 107 and USB I / F 108. At this time, the clock source selection setting is determined by the clock source setting REG112, the multiplication rate setting of the PLL circuit 109b is determined by the value of the PLL setting REG113, and the frequency division ratio setting of the frequency dividing circuit 110b is the frequency division setting. It is determined by the value of REG114.

  As for the USB clock, in addition to the clock via the PLL circuit 109b, a direct path from the external clock 1 and the external clock 2 can be selected.

  The variable clock system can be reset after the reset and before the next reset, but the fixed clock system cannot be reset until the next reset after the reset.

  The semiconductor device according to the present embodiment can be changed without affecting the fixed clock system even when the frequency of the variable clock system is changed by separating the variable clock system and the fixed clock system by the configuration and operation as described above. can do.

  For example, as an LSI system, the CPU 103, the external bus operation changes to a light state (sleep or polling) in hardware, and there is no problem even if the frequency of the variable clock system is low, so the frequencies of the CPU clock, external bus clock, and internal module clock If the frequency division setting of the PLL circuit 109a is changed to change the frequency division setting of the frequency divider circuit 110a, the fixed clock system is not affected. In other words, since the serial baud rate setting and the AUDIO clock do not change, there is no need to reset the module that operates with the fixed clock.

  Therefore, even when the frequency of the system clock of the variable clock system is changed, the AUDIO I / F 107, the serial I / F 106, and the USB I / F 108 can continue to operate as they are.

  The USB clock is particularly selected because the clock source is selected so that the external clock 1 and the external clock 2 can be used exclusively. Since the USB clock requires a fixed 48 MHz, other clocks are generated when generated from the PLL circuit 109b. This is because it is desirable to take a form that can be drawn from the source oscillation (clock source) because it is easily restricted by the operating frequency value of the fixed clock system. In addition, when the cycle / phase jitter is added by passing through the PLL circuit 109b and the specification of the USB clock cannot be satisfied, it is assumed that a clock with a clear source oscillation is used.

  Next, an operation example when changing the frequency of the LSI 100 will be described with reference to FIGS.

  The frequency change of the LSI 100 is executed by the following procedure. In FIG. 1 and FIG. 3, the numbers corresponding to the following operations are indicated by numbers with circles.

  First, it is assumed that a reset is first performed from a reset terminal, and for CPU clock control and serial clock control, for example, 1 frequency division is set as an initial value. At this time, the internal state transitions from the internal reset state to the CPU operating state, and the CPU clock and serial clock are each divided by one and output.

  (1) A frequency change REQ (request) is issued from the CPU 103 to the clock control unit 102 via the bus.

  (2) The bus stop control circuit 115 of the clock control unit 102 issues an internal bus stop REQ.

  (3) The bus stop control circuit 115 waits until an internal bus stop ACK (acknowledge) is returned.

  (4) When the internal bus stop ACK is returned, the frequency division setting REG 114 is set to stop, and the selection circuit 111c is switched to stop (CPU clock, external bus clock, internal module clock). At this time, the internal state becomes the internal bus stop state, and the CPU clock stops, but the fixed clock system such as the serial clock is output as it is.

  (5) When the multiplication of the PLL circuit 109a is changed, the PLL setting REG113 is updated and the PLL circuit is redrawn (re-oscillated).

  (6) The frequency division setting REG 114 is updated to the new setting value, and the selection circuit 111c is switched to the new frequency division ratio (CPU clock, external bus clock, internal module clock). In the example of FIG. 3, the CPU clock is updated to divide by two. The serial clock maintains the previous state. If communication is in progress, communication continues.

  (7) The supply of the CPU clock is restarted, and the bus stop control circuit 115 drops the internal bus stop REQ and restarts the operation of the internal bus. At this time, the internal state becomes the CPU operating state.

  As described above, even when the frequency of the variable clock system is being changed, a fixed clock system such as a serial clock is continuously generated independently, so that the communication circuit inside the LSI continues to communicate with the outside. be able to. Communication data can be received until the internal FIFO (buffer) is full. After the resetting of the variable clock system is completed, the communication data is transferred from the internal FIFO to the internal memory or the external memory. If the internal FIFO becomes full while the variable clock system is stopped, the internal bus is in a stopped state, so that communication data cannot be transferred.

  As described above, in the semiconductor integrated circuit device of the present embodiment, the variable clock and the fixed clock system are separated and each clock system has a PLL. As a result, even when the variable clock frequency (multiplication rate / division ratio) is changed, the other fixed clock side clock system is not affected by the frequency change on the variable clock side, so there is no effect. Therefore, the effect of using two clock systems can be obtained.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above embodiment, the serial clock, the audio clock, and the USB clock have been described as the fixed clock system. However, the present invention is not limited to this, and can be applied to a clock system in which other frequencies are fixed. is there.

  The present invention can be used in the manufacturing industry of semiconductor integrated circuit devices and electronic devices.

1 is a block diagram showing a configuration and operation of a semiconductor integrated circuit device according to an embodiment of the present invention. 1 is a block diagram showing an internal bus configuration in a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 4 is a timing chart showing an operation at a frequency change in the semiconductor integrated circuit device according to one embodiment of the present invention.

Explanation of symbols

100 LSI
101 Clock generation unit 102 Clock control unit 103, 103a, 103b CPU
104 Bus interface (I / F)
105 Built-in module 105a 3DIP
105b, 105c DMAC
105d, 105e Image IP
105f Timer 105g Card interface (I / F)
106, 106a, 106b Serial interface (I / F)
107 Audio Interface (AUDIO I / F)
108 USB interface (I / F)
109a, 109b PLL circuits 110a-110d Frequency dividing circuits 111a-111e Selection circuit 112 Clock source setting register (REG)
113 PLL setting register (REG)
114 Divide setting register (REG)
115 Bus stop control circuit 116 External memory 117 to 119 External LSI
120a-120e Internal bus 121a-121d Bus (BUS) bridge

Claims (9)

A first PLL circuit that multiplies an externally input clock; a first frequency divider that divides the clock multiplied by the first PLL circuit to generate a system clock;
A second PLL circuit for multiplying an externally input clock; and a second frequency dividing circuit for generating a communication circuit clock by dividing the clock multiplied by the second PLL circuit;
The first PLL circuit can be reset after the reset and before the next reset,
2. The semiconductor integrated circuit device according to claim 1, wherein the second PLL circuit cannot be reset after the reset until the next reset. The semiconductor integrated circuit device according to claim 1.
The first frequency divider can be reset after the reset and before the next reset,
2. The semiconductor integrated circuit device according to claim 1, wherein the second frequency divider circuit cannot be reset until the next reset after reset. The semiconductor integrated circuit device according to claim 1.
A CPU,
2. The semiconductor integrated circuit device according to claim 1, wherein the resetting of the first PLL circuit is performed by the CPU updating a value of a setting register. The semiconductor integrated circuit device according to claim 2.
A CPU,
2. The semiconductor integrated circuit device according to claim 1, wherein the resetting of the first frequency dividing circuit is performed by the CPU updating a value of a setting register. The semiconductor integrated circuit device according to claim 1.
Having a communication circuit,
During resetting of the first PLL circuit, a communication circuit clock of the communication circuit is independently generated,
The communication circuit is capable of communicating with the outside using the generated communication circuit clock. The semiconductor integrated circuit device according to claim 5.
Data received by communicating with the outside using the communication circuit clock during the resetting of the first PLL circuit is stored in a buffer in the communication circuit,
The semiconductor integrated circuit device is transferred to a built-in memory or an external memory after completion of resetting of the first PLL circuit. The semiconductor integrated circuit device according to claim 5.
During the reset period of the first PLL circuit, the system clock stops outputting,
A semiconductor integrated circuit device, wherein the CPU to which the system clock is input stops operating. The semiconductor integrated circuit device according to claim 7,
The resetting of the first PLL circuit is as follows:
The setting register is updated, the data transfer of the internal bus is stopped, the output of the system clock is stopped, the multiplication factor of the first PLL circuit is changed, the supply of the system clock is restarted, the data of the internal bus A semiconductor integrated circuit device, wherein transfer is resumed. In the semiconductor integrated circuit device according to claim 1,
The semiconductor integrated circuit device, wherein the system clock is a CPU clock.

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