JP4265195B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP4265195B2
JP4265195B2 JP2002295720A JP2002295720A JP4265195B2 JP 4265195 B2 JP4265195 B2 JP 4265195B2 JP 2002295720 A JP2002295720 A JP 2002295720A JP 2002295720 A JP2002295720 A JP 2002295720A JP 4265195 B2 JP4265195 B2 JP 4265195B2
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Prior art keywords
signal
fifo memory
data
processing unit
address
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JP2002295720A
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JP2004133577A (en
Inventor
禎 林
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セイコーエプソン株式会社
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing
    • Y02D10/10Reducing energy consumption at the single machine level, e.g. processors, personal computers, peripherals or power supply
    • Y02D10/13Access, addressing or allocation within memory systems or architectures, e.g. to reduce power consumption or heat production or to increase battery life

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device that performs signal processing on data transferred from an external memory, sequentially stores the data, and sequentially outputs the stored data.
[0002]
[Prior art]
In recent years, a display device such as an LCD panel is used to display an image in a mobile phone device or the like, and an LCD controller that supplies image data to the LCD panel is used. The LCD controller generally has a FIFO memory, outputs a request signal for requesting transfer of image data from the frame memory, performs image processing on the image data transferred from the frame memory in response to the request signal, and performs a FIFO. The image data is sequentially stored in the memory, and the image data stored in the FIFO memory is sequentially output to the LCD panel in response to a read request. Such an LCD controller operates in synchronization with a clock signal supplied from an external circuit or in synchronization with a signal supplied from a built-in PLL circuit.
[0003]
In the conventional LCD controller, when the FIFO memory control unit requests necessary data, the address generator operates in response to the request from the FIFO memory control unit. A clock signal is supplied to the conventional LCD controller from when the FIFO memory control unit requests the necessary data until the data is received. However, in the conventional LCD controller, the supply of the clock signal cannot be stopped until the image data is received after the FIFO memory control unit outputs the request signal. Therefore, in the conventional LCD controller, it takes a long time to supply the clock signal from the external circuit. In addition, the data transfer rate from the frame memory to the LCD controller may be low.
[0004]
[Problems to be solved by the invention]
In view of the above, an object of the present invention is to provide a semiconductor device capable of stopping the supply of a clock signal while the free capacity of the FIFO memory is a predetermined amount.
[0007]
[Means for Solving the Problems]
  In order to solve the above problems, one of the present inventionsThe semiconductor device according to the above aspect outputs an address for reading data in the external memory and a request signal for requesting data transmission in synchronization with the first clock signal supplied from the first external circuit. An address generator unit that receives the data transferred from the external memory in response to the request signal in synchronization with the second clock signal supplied from the second external circuit, and performs a predetermined signal processing A FIFO memory unit that sequentially stores data output from the signal processing unit in synchronization with the second clock signal, and sequentially outputs the stored data in response to a signal that requests reading of the data; and a FIFO memory The first signal for stopping the supply of the first clock signal is output to the first external circuit while the free space of the unit is a predetermined amount, and the FIF A second signal for stopping the supply of the second clock signal until the free capacity of the FIFO memory section becomes larger than the predetermined amount after the predetermined time has elapsed since the free capacity of the memory section has become a predetermined amount. And a FIFO memory control unit for outputting to the second external circuit.
[0008]
Here, the FIFO memory control unit outputs the first signal to the first external circuit while the free capacity of the FIFO memory unit is equal to the amount of data processed in the signal processing unit, and the FIFO memory unit is free. When the signal processing for the data existing in the signal processing unit ends when the capacity becomes equal to the data amount processed in the signal processing unit, the free capacity of the FIFO memory unit is larger than the data amount processed in the signal processing unit. Until then, the second signal may be output to the second external circuit.
[0009]
In addition, the signal processing unit includes N (N is a natural number) signal processing circuits connected in a pipeline, and the FIFO memory control unit stores a write address for storing data in the FIFO memory unit and data in the FIFO memory unit. The read address is read and the first signal is output to the first external circuit while the value obtained by adding (N + 1) to the read address is equal to the write address, and (N + 1) is added to the read address. The second signal is output from the time when the signal processing on the data that can exist in the signal processing unit when the value becomes equal to the write address until the value obtained by adding (N + 1) to the read address is not equal to the write address. It is good also as outputting to a 2nd external circuit.
[0010]
  In addition, the signal processing unit includes N (N is a natural number) signal processing circuits connected in a pipeline, and the FIFO memory control unit stores a write address for storing data in the FIFO memory unit and data in the FIFO memory unit. The read address may be managed, and the first signal may be output to the first external circuit and the second signal may be output to the second external circuit while the read address is equal to the write address. .
  Further, a gating circuit that gates and outputs the first signal by a signal that is enabled from the start of reading of data in the external memory to the end of reading may be further provided.
[0011]
According to the present invention, the power consumption can be reduced by stopping the supply of the clock signal while the FIFO memory has a predetermined free space.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. The same constituent elements are denoted by the same reference numerals, and the description thereof is omitted.
FIG. 1 is a diagram showing an outline of an image display device using a semiconductor device according to the first embodiment of the present invention. As shown in FIG. 1, the image display device 1 includes an LCD module clock generator 2, a timing generation circuit 3, an LCD module 10, and a display control unit 20.
[0013]
The LCD module clock generator 2 supplies the CLKP signal to the display control unit 20. The LCD driver clock signal having the same frequency as the CLKP signal is supplied from the display control unit 20 to the LCD module 10.
The timing generation circuit 3 outputs an image data request signal requesting transmission of image data to the LCD module 10 to the display control unit 20.
[0014]
FIG. 2 is a diagram showing a configuration of the LCD module 10 of FIG. As shown in FIG. 2, the LCD module 10 includes an LCD panel 12 that displays images, characters, and the like, and an LCD driver 11 that drives the LCD panel 12. The LCD driver 11 receives the image data and the LCD driver clock signal from the display control unit 20 and causes the LCD panel 12 to display an image based on the received image data.
[0015]
Referring to FIG. 1 again, the display control unit 20 receives data such as characters and images from an external circuit, performs predetermined processing, and transmits the data to the LCD module 10.
FIG. 3 is a diagram illustrating a configuration of the display control unit 20 of FIG. As shown in FIG. 3, the display control unit 20 includes a system clock generator 4, an I / O controller 21, a ROM 22, a RAM 23, a CPU 24, a DMA (direct memory access) controller 25, a frame memory 26, and the like. The frame memory access control circuit 27, the LCD controller clock generator 28, the clock gating circuit 29, and the LCD controller 30 are included. The I / O controller 21, ROM 22, RAM 23, CPU 24, DMA controller 25, and frame memory access control circuit 27 are connected to each other by a bus B.
[0016]
The system clock generator 4 supplies the CLKM signal to the I / O controller 21, ROM 22, RAM 23, CPU 24, DMA controller 25, frame memory 26, and frame memory access control circuit 27. The I / O controller 21, ROM 22, RAM 23, CPU 24, DMA controller 25, frame memory 26, and frame memory access control circuit 27 operate in synchronization with the CLKM signal. The CLKM signal is also supplied to the LCD controller 30 in order to synchronize data transmission / reception timing.
[0017]
The I / O controller 21 receives data from the external circuit and transmits it to the bus B, and receives data from the bus B and transmits it to the external circuit.
The ROM 22 stores a program executed by the CPU 24.
The CPU 24 performs a predetermined process on the data received from the external circuit by executing the program stored in the ROM 22 while using the RAM 23 as a work area.
[0018]
The DMA controller 25 transfers the image data stored in the RAM 23 to the frame memory access control circuit 27 without involving the CPU 24.
The frame memory access control circuit 27 stores the image data received via the bus B in the frame memory 26. Further, when receiving the image data transfer request from the LCD controller 30, the frame memory access control circuit 27 reads the image data stored in the frame memory 26 and transmits it to the LCD controller 30.
The LCD controller clock generator 28 outputs a CLK signal having the same frequency as the CLKM signal to the clock gating circuit 29.
[0019]
FIG. 4 is a diagram showing an internal configuration of the LCD controller 30 of FIG. 3 as the semiconductor device according to the first embodiment of the present invention. As shown in FIG. 4, the LCD controller 30 receives an image from an address generator 31 that generates an address for reading image data in the frame memory 26 (see FIG. 3) and a frame memory access control circuit 27 (see FIG. 3). The pipeline processing unit 32 that performs predetermined image processing on the data, the image data processed by the pipeline processing unit 32 are sequentially stored, and the LCD driver 11 (see FIG. 2) in the order in which the stored image data is stored. First-in-first-out (FIFO) memory 33 that sequentially outputs to the memory, and a FIFO memory controller 34 that controls the FIFO memory 33.
[0020]
FIG. 5 is a diagram showing an internal configuration of the FIFO memory controller 34 of FIG. As shown in FIG. 5, the FIFO memory controller 34 includes a write address counter 42, a data output enable signal generation unit 43, a read address counter 44, a comparator 46, and an inverting circuit 47.
The write address counter 42 holds a write address that is an address for writing data in the FIFO memory 33 (see FIG. 4). When a valid data enable signal is received from the address generator 31 (see FIG. 4), the write address counter 42 Increment. The write address counter 42 outputs the write address to the FIFO memory 33 (see FIG. 4) and the comparator 46. The write address counter 42 operates in synchronization with the CLKM signal output from the system clock generator 4 (see FIG. 3).
[0021]
When receiving the image data request signal from the timing generation circuit 3 (see FIG. 1), the data output enable signal generation unit 43 generates a data output enable signal and outputs it to the read address counter 44. The data output enable signal generation unit 43 operates in synchronization with the CLKP signal output from the LCD module clock generator 2 (see FIG. 1).
The read address counter 44 holds a read address that is an address for reading data in the FIFO memory 33 (see FIG. 4). When the data output enable signal is received, the read address counter 44 increments the read address. The read address counter 44 outputs the read address to the FIFO memory 33 (see FIG. 4). The read address counter 44 operates in synchronization with the CLKP signal output from the LCD module clock generator 2 (see FIG. 1).
[0022]
The comparator 46 outputs a high-level FIFOFULL signal when the write address and the read address are equal.
The inverting circuit 47 outputs a CEN1 (clock enable 1) signal obtained by inverting the FIFOFULL signal to the clock gating circuit 29 (see FIGS. 3 and 4) and the address generator 31 (see FIG. 4). The CEN1 signal becomes low level when the write address becomes equal to the read address, and becomes high level at other times.
[0023]
Referring back to FIG. 4, the clock gating circuit 29 receives the CEN1 signal from the FIFO memory controller 34. Then, the clock gating circuit 29 transmits the CLK1 signal obtained by gating the CLK signal using the CEN1 signal to the address generator 31, the pipeline processing unit 32, and the FIFO memory 33. The address generator 31 and the pipeline processing unit 32 operate in synchronization with the CLK1 signal. The FIFO memory 33 operates in synchronization with the CLK1 signal when image data is written from the pipeline processing unit 32. The FIFO memory 33 operates in synchronization with the CLKP signal from the LCD module clock generator 2 when reading out the image data in response to a request from the timing generation circuit 3.
[0024]
FIG. 6 is a simplified diagram showing the internal configuration of the address generator 31 of FIG. As shown in FIG. 6, the address generator 31 includes a request generation unit 51, an AND gate circuit 52, an address counter 53, and a valid data enable signal generation unit 54.
The request generation unit 51 outputs a request signal based on the CEN1 signal in synchronization with the CLK1 signal.
[0025]
The AND gate circuit 52 performs an AND operation between the request signal output from the request generation unit 51 and the CEN1 signal. The output signal of the AND gate circuit 52 is output to the frame memory access control circuit 27 as an image data request signal. The address counter 53 operates in synchronization with the CLK1 signal. The address counter 53 holds an address for reading data in the frame memory 26 (see FIG. 3). The address counter 53 receives an acknowledge signal (see the frame memory access control circuit 27 (see FIG. 3)) from the frame memory access control circuit 27 (see FIG. 3). ) Receives the image data request signal from the AND gate circuit 52, the signal is output as a response), and the held address is incremented and output to the frame memory access control circuit 27.
[0026]
When receiving the acknowledge signal, the valid data enable signal generation unit 54 generates a valid data enable signal and outputs it to the write address counter 42 (see FIG. 5) in the FIFO memory controller 34. The valid data enable signal generation unit 54 has the same number of pipeline stages as the pipeline processing unit 32.
[0027]
FIG. 7 is a timing chart showing the operation timing of the LCD controller 30.
As shown in FIG.0When the read address is equal to the write address, the FIFO memory controller 34 outputs a low-level CEN1 signal to the clock gating circuit 29 and the address generator 31. When the address generator 31 receives the low-level CEN1 signal, the time t311The low level image data request signal is output to the frame memory access control circuit 27.
[0028]
When the frame memory access control circuit 27 receives the low-level image data request signal, the frame memory access control circuit 27 stops the transfer of the image data to the pipeline processing unit 32, and at a time t after a predetermined time.ThreeThe low level acknowledge signal is output to the address generator 31.
On the other hand, the clock gating circuit 290After the time t when the CLK signal becomes low level2, The supply of the CLK1 signal to the address generator 31, the pipeline processing unit 32, and the FIFO memory 33 is stopped. As a result, the address generator 31 and the pipeline processing unit 32 stop operating. Further, the FIFO memory 33 stops receiving image data from the pipeline processing unit 32.
[0029]
Thereafter, when the image data in the FIFO memory 33 is read by the timing generation circuit 3 and the read address and the write address are not equal, the time tFour1, the FIFO memory controller 34 outputs a high-level CEN 1 signal to the clock gating circuit 29 and the address generator 31.
The address generator 31FourTime t afterFiveThe high level image data request signal is output to the frame memory access control circuit 27.
[0030]
When receiving the high-level image data request signal, the frame memory access control circuit 27 receives a time t after a predetermined time.6, The high-level acknowledge signal is output to the address generator 31 and the transfer of the image data to the pipeline processing unit 32 is resumed.
On the other hand, the clock gating circuit 29FourAfter the time t when the CLK signal becomes high level7The supply of the CLK1 signal to the address generator 31, the pipeline processing unit 32, and the FIFO memory 33 is resumed. As a result, the address generator 31 and the pipeline processing unit 32 resume operation, and the FIFO memory 33 resumes receiving image data from the pipeline processing unit 32.
[0031]
As described above, according to the LCD controller 30, the CEN1 signal that is at the low level when the read address and the write address are equal is output, and the address generator 31 and the pipeline processing unit 32 while the CEN1 signal is at the low level. Since the supply of the CLK1 signal to the FIFO memory 33 is stopped, the time during which the CLK1 signal is supplied is shortened, and the operation time of the address generator 31, the pipeline processing unit 32, and the FIFO memory 33 is shortened. Power consumption can be reduced.
[0032]
Next, a second embodiment of the present invention will be described. FIG. 8 is a diagram showing an outline of an image display device using a semiconductor device according to the second embodiment of the present invention. As shown in FIG. 8, the image display device 70 includes an LCD module clock generator 2, a timing generation circuit 3, an LCD module 10, and a display control unit 71.
FIG. 9 is a diagram illustrating a configuration of the display control unit 71 of FIG. As shown in FIG. 9, the display control unit 71 includes a system clock generator 4, an I / O controller 21, a ROM 22, a RAM 23, a CPU 24, a DMA controller 25, a frame memory 26, and a frame memory access control. A circuit 27, an LCD controller clock generator 28, clock gating circuits 29 and 72, and an LCD controller 80 are included.
[0033]
FIG. 10 is a diagram showing an internal configuration of the LCD controller 80 of FIG. 9 as a semiconductor device according to the second embodiment of the present invention. As shown in FIG. 10, the LCD controller 80 includes a FIFO memory 33, a FIFO memory controller 81, an address generator 82, and a pipeline processing unit 83.
FIG. 11 is a diagram showing an internal configuration of the FIFO memory controller 81. As shown in FIG. 11, the FIFO memory controller 81 includes a write address counter 42, a data output enable signal generation unit 43, a read address counter 44, an adder 45, a comparator 46, an inverting circuit 47, a delay, A circuit 84 and an OR gate circuit 85 are provided.
[0034]
The adder 45 adds a value obtained by adding “1” to the number of pipeline stages of the pipeline processing unit 83 (see FIG. 10) to the read address. Note that “1” is added in order to transfer the image data existing in the final stage of the pipeline processing unit 83 to the FIFO memory 33. In this embodiment, as will be described later, since the number of pipeline stages of the pipeline processing unit 83 is “3”, the adder 45 adds “4” to the read address. The adder 45 outputs the addition result to the comparator 46.
The delay circuit 84 outputs the CEN1D signal obtained by delaying the CEN1 signal output from the inverting circuit 47 by a predetermined time to one input terminal of the OR gate circuit 85. The delay time of the delay circuit 84 is such that the image data transferred from the frame memory access control circuit 26 to the first stage processing unit in the pipeline processing unit 83 is subjected to predetermined image processing and is stored in the FIFO memory 33. It is necessary time to be written.
The CEN1 signal is input to the other input terminal of the OR gate circuit 85. The OR gate circuit 85 performs a logical OR operation between the CEN1D signal and the CEN1 signal, and outputs a CEN2 (clock enable 2) signal as a calculation result to the clock gating circuit 72.
[0035]
Referring to FIG. 10 again, the clock gating circuit 72 receives the CEN2 signal from the OR gate circuit 85 in the FIFO memory controller 81. Then, the clock gating circuit 72 transmits the CLK2 signal obtained by gating the CLK signal using the CEN2 signal to the pipeline processing unit 83 and the FIFO memory 33. The pipeline processing unit 83 operates in synchronization with the CLK2 signal. The FIFO memory 33 operates in synchronization with the CLK2 signal when image data is written from the pipeline processing unit 83. The FIFO memory 33 operates in synchronization with the CLKP signal from the LCD module clock generator 2 when the image data is read from the timing generation circuit 3.
FIG. 12 is a simplified diagram showing the internal configuration of the address generator 82 of FIG. As shown in FIG. 12, the address generator 82 includes a request generator 51, an AND gate circuit 52, and an address counter 53. Compared with the address generator 31 (see FIG. 6) described above. The valid data enable signal generator 54 is omitted.
[0036]
FIG. 13 is a diagram showing an internal configuration of the pipeline processing unit 83 in FIG. As illustrated in FIG. 13, the pipeline processing unit 83 includes an effective data enable signal generation unit 54 and first to third image data processing units 61 to 63 that respectively perform predetermined image processing. The first to third image data processing units 61 to 63 operate in synchronization with the CLK2 signal. The valid data enable signal generation unit 54 has the same number of pipeline stages as the pipeline processing unit 32 and operates in synchronization with the CLK2 signal.
The first image data processing unit 61 receives image data from the frame memory access control circuit 27, performs first image processing on the received image data, and outputs it to the second image data processing unit 62.
[0037]
The second image data processing unit 62 receives the image data from the first image data processing unit 61, performs the second image processing on the received image data, and outputs it to the third image data processing unit 63.
The third image data processing unit 63 receives the image data from the second image data processing unit 62, performs third image processing on the received image data, and outputs it to the FIFO memory 33. The FIFO memory 33 stores the image data received from the third image data processing unit 63 at a location specified by the write address held by the write address counter 42 (see FIG. 5).
As described above, the first to third image data processing units 61 to 63 constitute a pipeline having “3” stages.
[0038]
FIG. 14 is a timing chart showing the operation timing of the LCD controller 80.
As shown in FIG.TenWhen the value obtained by adding “4” to the read address becomes equal to the write address, the FIFO memory controller 81 outputs a low-level CEN1 signal to the clock gating circuit 29.
[0039]
The clock gating circuit 29TenAfter the time t when the CLK signal becomes low level11Then, the supply of the CLK1 signal to the address generator 82 is stopped. As a result, the address generator 82 stops operating, and the frame memory access control circuit 27 stops the transfer of the image data to the pipeline processing unit 83.
On the other hand, the supply of the CLK2 signal to the pipeline processing unit 83 and the FIFO memory unit 33 is performed at time t.TenTo t after the delay time of the delay circuit 84 has elapsed12Will continue until. As described above, the delay time of the delay circuit 84 is such that the image data transferred from the frame memory access control circuit 27 to the first image data processing unit 61 in the pipeline processing unit 83 performs predetermined image processing. Thus, the time required until the data is written into the FIFO memory 33 is reached. Therefore, time tTenThe image processing for the image data existing in the first to third image data processing units 61 to 63 of the pipeline processing unit 83 at time tTen~ T12Until time t12The image data for which image processing has been completed is written into the FIFO memory 33.
[0040]
Time t12When the CEN1D signal becomes low level, the FIFO memory controller 81 outputs the low level CEN2 signal to the clock gating circuit 72.
When receiving the low-level CEN2 signal, the clock gating circuit 72 receives the time t12After the time t when the CLK signal becomes low level13Then, supply of the CLK2 signal to the pipeline processing unit 83 and the FIFO memory 33 is stopped. As a result, the pipeline processing unit 83 and the FIFO memory 33 stop operating.
[0041]
Thereafter, when the image data in the FIFO memory 33 is read by the timing generation circuit 3 and the value obtained by adding “4” to the read address is not equal to the write address, the time t14The FIFO memory controller 81 outputs a high level CEN1 signal to the clock gating circuit 29 and outputs a high level CEN2 signal to the clock gating circuit 72.
The clock gating circuit 2914After the time t when the CLK signal becomes high level15Then, the supply of the CLK1 signal to the address generator 82 is resumed. Thereby, the address generator 82 resumes the operation.
[0042]
The clock gating circuit 7214After the time t when the CLK signal becomes high level15The supply of the CLK2 signal to the pipeline processing unit 83 and the FIFO memory 33 is resumed. As a result, the pipeline processing unit 83 and the FIFO memory 33 resume operation.
Then time t14To t after a predetermined delay time of the delay circuit 84 has elapsed16, The CEN1D signal goes high.
[0043]
As described above, according to the LCD controller 80, the CEN1 signal that is at the low level is output when the value obtained by adding “4” to the read address is equal to the write address, and the address is output while the CEN1 signal is at the low level. Supply of the CLK1 signal to the generator 82 is stopped, and the address generator 82 stops operating. On the other hand, the supply of the CLK2 signal to the pipeline processing unit 83 and the FIFO memory unit 33 is continued until the processing on the image data existing in the pipeline processing unit 83 is completed, and the pipeline processing unit 83 and the FIFO memory are continued. The unit 33 continues to operate. Therefore, the operation time of the address generator 82 can be shortened to reduce power consumption, and the image processing for the image data existing in the pipeline processing unit 83 can be terminated. In addition, since the pipeline processing unit 83 and the FIFO memory unit 33 stop operating after the image processing on the image data existing in the pipeline processing unit 83 is completed, power consumption can be reduced.
[0044]
Next, a third embodiment of the present invention will be described. FIG. 15 is a diagram showing an outline of an image display device using a semiconductor device according to the third embodiment of the present invention. As shown in FIG. 15, the image display device 90 includes an LCD module clock generator 2, a timing generation circuit 3, an LCD module 10, and a display control unit 91.
FIG. 16 is a diagram showing a configuration of the display control unit 91 of FIG. As shown in FIG. 16, the display control unit 91 includes a system clock generator 4, an I / O controller 21, a ROM 22, a RAM 23, a CPU 24, a DMA controller 25, a frame memory 26, and a frame memory access control. A circuit 27, an LCD controller clock generator 28, clock gating circuits 29 and 72, and an LCD controller 100 are included.
[0045]
FIG. 17 is a diagram showing an internal configuration of the LCD controller 100 of FIG. 16 as a semiconductor device according to the third embodiment of the present invention. As shown in FIG. 17, the LCD controller 100 includes a FIFO memory 33, a FIFO memory controller 81, an address generator 82, a pipeline processing unit 83, and a CEN1 gating circuit 101.
The CEN1 gating circuit 101 is a circuit that outputs a CEN1G signal obtained by gating the CEN1 signal output from the FIFO memory controller 81 with the FREN signal output from the frame memory access control circuit 27. The FREN signal output from the timing generation circuit 3 is a signal that is enabled (here, high level) from the start of frame reading to the end of frame reading.
[0046]
FIG. 18 is a timing chart showing the operation of the CEN1 gating circuit 101. As shown in FIG. 18, the CEN1 gating circuit 101 outputs a low-level CEN1G signal to the clock gating circuit 29 and the address generator 82 when the FREN signal is at a low level. The CEN1 gating circuit 101 outputs the CEN1G signal having a high level to the clock gating circuit 29 and the address generator 82 when the FREN signal is at a high level and the CEN1 signal is at a high level. The CEN1 gating circuit 101 outputs a CEN1G signal at a low level to the clock gating circuit 29 and the address generator 82 when the FREN signal is at a high level and the CEN1 signal is at a low level.
[0047]
As described above, according to the LCD controller 100, the CEN1G signal is disabled (here, low level) when there is no need to read the data stored in the frame memory 26 (see FIG. 16), and the address generator 82 is supplied. The supply of the CLK1 signal can be stopped and power consumption can be further reduced.
[0048]
【The invention's effect】
As described above, according to the present invention, it is possible to reduce power consumption by stopping the supply of the clock signal while the FIFO memory has a predetermined free capacity.
[Brief description of the drawings]
FIG. 1 is a diagram showing an outline of an image display device using a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a diagram illustrating a configuration of the LCD module of FIG. 1;
FIG. 3 is a diagram illustrating a configuration of a display control unit in FIG. 1;
4 is a diagram showing a configuration of an LCD controller of FIG. 3 as a semiconductor device according to the first embodiment of the present invention.
FIG. 5 is a diagram showing a configuration of a FIFO memory controller of FIG. 4;
6 is a diagram showing a configuration of the address generator of FIG. 4;
FIG. 7 is a timing chart showing operation timings of the LCD controller as the semiconductor device according to the first embodiment of the present invention.
FIG. 8 is a diagram showing an outline of an image display device using a semiconductor device according to a second embodiment of the present invention.
9 is a diagram illustrating a configuration of a display control unit in FIG. 8;
10 is a diagram showing a configuration of an LCD controller of FIG. 9 as a semiconductor device according to a second embodiment of the present invention.
11 is a diagram showing a configuration of the FIFO memory controller of FIG. 10;
12 is a diagram showing a configuration of the address generator of FIG. 10;
13 is a diagram illustrating a configuration of a pipeline processing unit in FIG. 10;
FIG. 14 is a timing chart showing the operation timing of the LCD controller as the semiconductor device according to the second embodiment of the present invention.
FIG. 15 is a diagram showing an outline of an image display device using a semiconductor device according to a third embodiment of the present invention.
16 is a diagram showing a configuration of a display control unit in FIG. 15;
17 is a diagram showing a configuration of an LCD controller of FIG. 16 as a semiconductor device according to a third embodiment of the present invention.
18 is a timing chart showing operation timing of the CEN1 gating circuit of FIG.
[Explanation of symbols]
1, 70, 90 Image display device
2 LCD module clock generator
3 Timing generation circuit
4 System clock generator
10 LCD module
11 LCD driver
12 LCD panel
20, 71, 91 Display control unit
21 I / O controller
22 ROM
23 RAM
24 CPU
25 DMA controller
26 frame memory
27 Frame memory access control circuit
28 LCD controller clock generator
29, 72 Clock gating circuit
30, 80, 100 LCD controller
31, 82 Address generator
32, 83 Pipeline processing section
33 FIFO memory
34, 81 FIFO memory controller
42 Write address counter
43 Data output enable signal generator
44 Read address counter
45 Adder
46 Comparator
47 Inversion circuit
51 Request generator
52 AND gate circuit
53 Address counter
54 Valid Data Enable Signal Generation Unit
61 First image data processing unit
62 Second image data processing unit
63 Third image data processing unit
84 Delay circuit
85 OR gate circuit
101 CEN1 gating circuit
B bus

Claims (5)

  1. An address generator for outputting an address for reading data in the external memory in synchronization with a first clock signal supplied from the first external circuit, and for outputting a request signal for requesting data transmission;
    A signal processing unit that receives data transferred from the external memory in response to the request signal and performs predetermined signal processing in synchronization with a second clock signal supplied from a second external circuit;
    A FIFO memory unit that sequentially stores data output from the signal processing unit in synchronization with the second clock signal, and sequentially outputs the stored data in response to a signal that requests reading of the data;
    The first signal for stopping the supply of the first clock signal is output to the first external circuit while the free capacity of the FIFO memory section is a predetermined amount, and the free capacity of the FIFO memory section is output. After the predetermined time has elapsed and a predetermined time has elapsed, the second signal for stopping the supply of the second clock signal until the free capacity of the FIFO memory section becomes larger than the predetermined amount is supplied to the second signal. A FIFO memory control unit for outputting to an external circuit of
    A semiconductor device comprising:
  2. The FIFO memory control unit outputs the first signal to the first external circuit while the free capacity of the FIFO memory unit is equal to the amount of data processed in the signal processing unit, and the FIFO memory When the signal processing for the data existing in the signal processing unit ends when the free capacity of the unit becomes equal to the amount of data processed in the signal processing unit, the free capacity of the FIFO memory unit is determined in the signal processing unit. the semiconductor device according to claim 1, wherein said second signal until greater than the amount of data to be processed and outputs to the second external circuit.
  3. The signal processing unit includes N (N is a natural number) signal processing circuits connected in a pipeline, and the FIFO memory control unit stores a write address for storing data in the FIFO memory unit and the FIFO memory unit. The first address is output to the first external circuit while the value obtained by adding (N + 1) to the read address is equal to the write address, and the read address is read out. When the value obtained by adding (N + 1) to the write address becomes equal to the write address, the value obtained by adding (N + 1) to the read address from the end of signal processing for data that may exist in the signal processing unit. claim 1 also and outputs the second signal until not equal and said second external circuit 2 The semiconductor device according.
  4. The signal processing unit includes N (N is a natural number) signal processing circuits connected in a pipeline, and the FIFO memory control unit stores a write address for storing data in the FIFO memory unit and the FIFO memory unit. The read address for reading the data is managed, and while the read address is equal to the write address, the first signal is output to the first external circuit and the second signal is output to the second external circuit. 3. The semiconductor device according to claim 1 , wherein the semiconductor device outputs the signal to a circuit.
  5. 2. The gating circuit according to claim 1, further comprising a gating circuit that gates and outputs the first signal by a signal that is enabled from the start of reading of data in the external memory to the end of reading. the semiconductor device according to any one of 4.
JP2002295720A 2002-10-09 2002-10-09 Semiconductor device Expired - Fee Related JP4265195B2 (en)

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