JP7489789B2 - Gaming Machines - Google Patents

Description

The present invention relates to a gaming machine that performs a lottery process based on game actions and executes image effects corresponding to the lottery results, and in particular, to a gaming machine that can stably execute powerful image effects.

Pinball gaming machines such as pachinko machines are configured with a pattern start opening on the game board, a pattern display section that displays a series of pattern change patterns based on multiple displayed patterns, and a large prize opening with an opening and closing plate. When a detection switch installed in the pattern start opening detects the passage of a game ball, a winning state is reached, and after the game ball is paid out as a prize ball, the displayed pattern in the pattern display section changes for a predetermined period of time. After that, when the pattern stops in a predetermined pattern such as 7-7-7, a large win state is reached, and the large prize opening is repeatedly opened, creating a game state that is advantageous to the player.

Whether or not such a game state occurs is determined by a jackpot lottery that is executed on the condition that a game ball enters the symbol start hole, and the above-mentioned symbol change action is based on the result of this lottery. For example, if the lottery result is a win state, a presentation action called a reach action is executed for about 20 seconds, and then the special symbols are aligned. On the other hand, a similar reach action may also be executed in a loss state, in which case the player will pay close attention to the progress of the presentation action while strongly hoping for a jackpot state. Then, if the specified symbols are lined up on the stop line at the end of the symbol change action, the player is guaranteed a jackpot state.

This type of pattern change operation is usually performed on a liquid crystal display. A liquid crystal display is generally made up of H dots horizontally by V dots vertically, and each H x V pixel is made up of a basic pixel of the three colors RGB.

The driving of each pixel in an LCD display is executed in synchronization with the device's operating clock CK (=dot clock DCK), and pixel driving of H dots corresponding to one horizontal line is repeated in synchronization with the horizontal synchronization signal HS, and when driving of V lines is completed, it is configured to return to pixel driving of the first line in synchronization with the vertical synchronization signal VS (see Figure 40). Therefore, it is necessary for an external device to supply to the LCD display an image signal corresponding to a resolution of H x V dots, along with the horizontal synchronization signal HS, vertical synchronization signal VS, and dot clock DCK.

Here, in order to smoothly execute the display update operation (frame update) of the liquid crystal display, certain conditions are required for the pulse width of each synchronization signal HS, Vs, and between the timing of each synchronization signal HS, Vs and the transmission timing of the image signal. For example, Figure 40 (g) shows an example of the drive timing conditions required for a 640 x 408 dot VGA (Video Graphics Array).

In the driving conditions shown in the figure, first, the pulse width PWh of the horizontal synchronization signal HS is 96 clocks of the operating clock CK, and the front porch FPh and back port BPh required before and after the horizontal synchronization signal PWh are specified as 16 and 48 clocks of the operating clock CK, respectively.

On the other hand, the pulse width PWv of the vertical synchronization signal VS is two lines, and the front porch FPv and back port BPv required before and after the vertical synchronization signal VS are specified as 19 lines and 33 lines, respectively.

Therefore, in this LCD display, the operating cycle of the drive operation for one line is 16 + 96 + 48 + 640 (= 800) counted by the operating clock CK, and by repeating this vertically for 10 + 2 + 33 + 480 lines (= 525), the display for one frame of the display screen is updated.

The above operation cycle is 800 x 525 cycles counted by the operation clock CK. For example, when the frequency of the operation clock is 25 MHz, the time required to update one frame is 800 x 525/(25 x ¹⁰⁶ ) = 16.8 mS, which is an operation cycle of approximately 1/60 seconds.

Then, the external control device that controls the LCD display repeatedly supplies the LCD display with a horizontal synchronization signal HS that satisfies the above horizontal conditions (PWh, FPh, BPh) and a horizontal synchronization signal HS that satisfies the above vertical conditions (PWvh, FPvh, BPvh), as well as an image signal that corresponds to the number of pixels on the display screen.

JP 2017-093633 A JP 2017-093632 A JP 2016-159030 A JP 2016-159029 A

However, in this type of gaming machine, there is a desire to make the various effects more complex and abundant, and there is a particularly high demand for image effects that use liquid crystal displays. The applicant has made various proposals (References 1 to 4), but there is a need for further sophistication of image effects and further improvements in the control operations of various effects, centered on image effect control. There is also a need for improvements in the drive operation of the liquid crystal display so that the control burden of image effect control can be reduced.

The present invention was made in consideration of the above problems, and aims to provide a gaming machine with further improvements in various presentation control operations, mainly image presentation control.

In order to achieve the above object, the present invention provides a gaming machine having a presentation control means for issuing a display list specifying display contents to be displayed on a screen of a display device and controlling the operation of an image generation means, and the image generation means having a drawing circuit for generating image data realizing the display contents based on instruction commands described in the display list issued by the presentation control means, and realizing an image presentation by the display device of a number of vertical pixels V x number of horizontal pixels H, wherein the image generation means is configured with a data transfer circuit for transferring configuration data of the display list received from the presentation control means in a predetermined acquisition bit unit to a downstream circuit in a predetermined transfer bit unit, and the presentation control means controls the total bit length of the display list to be equal to or larger than the total bit length of the display list, The image generating means is configured to generate an image data so that the transfer rate is an integer N times (N≧1) of a fixed transfer bit unit, and includes a first means for specifying a frequency Fdot of a display clock that specifies the internal operation of a display circuit built into the image generating means, a second means for specifying a line operation time of the display circuit corresponding to one horizontal line of the display device with a horizontal cycle number THc of the display clock, and a third means for specifying a vertical line number TVl that is the number of repetitions of the line operation time, and is configured so that the display circuit does not output image data corresponding to a pixel of the display device during a predetermined number of lines starting from a vertical reference point of a display operation period specified based on the horizontal cycle number THc, the vertical line number TVl, and the value of the frequency Fdot of the display clock.

According to the present invention described above, the vertical blanking period can be optimally set for a given number of lines (WTv), making it possible to realize image control operations that are compatible with the specifications of various display devices.

1 is a perspective view showing a pachinko machine according to an embodiment of the present invention. FIG. 2 is a front view showing the gaming area of the gaming machine of FIG. 1 . 2 is a block diagram showing the overall circuit configuration of the gaming machine of FIG. 1 . 1 is a diagram illustrating the specifications of a display device. FIG. 2 is a block diagram illustrating an internal configuration of the display device. 2 is a block diagram showing in some detail the circuit configuration of a performance control unit of the gaming machine of FIG. 1. 1 is a diagram for explaining a composite chip that constitutes a performance control unit. FIG. 5 is a block diagram showing an internal configuration of the CPU circuit shown in FIG. 4 . This illustrates the memory map of the built-in CPU (performance control CPU) of the CPU circuit. 1A to 1E are diagrams for explaining various transfer operation modes (a) to (b) and transfer operation procedures (c) to (e) of a DMAC. 1 is a diagram for explaining an index space, an index table, a virtual drawing space, and a drawing area. 1 is a block diagram illustrating an internal configuration of a data transfer circuit together with related circuit configurations. 2 is a block diagram showing the internal configuration of a display circuit together with related circuit configurations. FIG. 1 is a diagram illustrating a data valid signal ENAB output from a VDP circuit; 11 is a flowchart illustrating a power reset operation after a CPU reset. 16 is a flowchart illustrating a memory section initialization process which is part of FIG. 15. 16 is a flowchart illustrating a main control process and an interrupt process which are part of FIG. 15. 11 is a flowchart illustrating a CGROM initialization process which is a part of the main control process. 13 is a flowchart for explaining a part of the processing contents regarding another interrupt processing. 13 is a flowchart illustrating the control operation of the performance control CPU 63 when a preloader is not used. 1 is a diagram for explaining the configuration of a display list. 13 is a flowchart showing a DL issuing process for issuing a display list DL. 23 is a flowchart for explaining the operation of FIG. 22 when the DMAC is involved. 24 is a flowchart illustrating an operation subsequent to the processing of FIG. 23. 13 is a flowchart illustrating the control operation of the performance control CPU 63 when a preloader is used. 26 is a flowchart illustrating a part of FIG. 25. 26 is a flowchart illustrating another part of FIG. 25. 11 is a time chart showing the operation of each part of a VDP in an embodiment in which a preloader is not used. 11 is a time chart showing the operation of each part of the VDP in an embodiment using a preloader. FIG. 11 is a block diagram showing an overall circuit configuration according to another embodiment. FIG. 31 is a block diagram showing a portion of FIG. 30 in greater detail. 13 is a flowchart illustrating the operation of another embodiment. 11 is a diagram illustrating yet another embodiment. 11 is a diagram for explaining an embodiment in which a set value is repeatedly set; 1 is a diagram illustrating a circuit configuration of an embodiment using a built-in audio circuit. 4 is a flowchart illustrating an initial setting operation of the audio circuit. 11 is a diagram for explaining another embodiment of a power reset operation after a CPU reset. 4 is a time chart showing an example of a memory READ operation and a memory WRITE operation. 11 is a diagram illustrating another embodiment. 1 is a diagram illustrating a method of driving a general display device.

The present invention will be described in detail below based on the examples. Figure 1 is a perspective view showing a pachinko machine GM of this embodiment. This pachinko machine GM is composed of a rectangular wooden outer frame 1 that is detachably attached to the island structure, and an inner frame 3 that is pivotally attached so as to be able to be opened and closed via hinges 2 fixed to the outer frame 1. A game board 5 is detachably attached to this inner frame 3 from the front side, not from the back side, and a glass door 6 and a front panel 7 are pivotally attached to the front side so as to be able to be opened and closed. In this specification, the glass door 6 and the front panel 7 are collectively referred to as the front door member. The inner frame 3 to which the front door member (glass door 6 and front panel 7) is pivotally attached may be referred to as the game frame.

Illuminated lamps such as LED lamps are arranged in a roughly C-shape around the outer periphery of the glass door 6. Meanwhile, a total of three speakers are arranged on the upper left and right sides and on the lower side of the glass door 6. The two speakers arranged on the upper side are configured to output sound for the left and right channels R and L, respectively, and the speaker on the lower side is configured to output low-pitched sounds.

An upper tray 8 that stores game balls to be launched is attached to the front panel 7, and a lower tray 9 that stores game balls that have spilled over or been removed from the upper tray 8, and a launch handle 10 are provided at the bottom of the inner frame 3. The launch handle 10 is linked to a launch motor, and the game balls are launched by a striking hammer that operates according to the rotation angle of the launch handle 10.

A chance button 11 is provided on the outer periphery of the upper tray 8. This chance button 11 is provided in a position where it can be operated by the player's left hand, and the player can operate the chance button 11 without taking his/her right hand off the launch handle 10. This chance button 11 is not normally functional, but when the game state is in the button chance state, the built-in lamp lights up and the button becomes operable. The button chance state is a game state that is set as needed.

In addition, a rotary switch-type volume switch VLSW is located below the chance button 11, and the player can operate the volume switch VLSW to adjust the speaker volume in eight steps, from silent level (=0) to the maximum level (=7). The speaker volume is initially set by a setting switch (not shown) that can only be operated by an attendant, and the initial setting volume is maintained unless the player operates the volume switch VLSW. In addition, the abnormality notification sound that notifies the player of the occurrence of an abnormal situation is emitted at the maximum volume, regardless of the initial setting volume by the attendant or the volume set by the player.

To the right of the upper tray 8 is an operation panel 12 for operating the ball lending machine, which includes a degree display that displays the remaining balance on the card in three digits, a ball lending switch that commands the lending of a specified amount of game balls, and a return switch that commands the return of the card when the game ends.

As shown in FIG. 2, a guide rail 13 consisting of an outer and inner metallic rail is provided in a ring shape on the surface of the game board 5, and a central opening HO is provided in approximately the center of the guide rail. A movable performance body (not shown) is stored in a concealed state below the central opening HO, and during a movable preview performance, the movable performance body rises and becomes exposed, realizing a preview performance with a predetermined reliability. Here, the preview performance is a performance that notifies the player with uncertainty that a favorable jackpot state will occur, and the reliability of the preview performance means the probability that a jackpot state will occur.

The main display device DS1, which is a large (e.g., 1280 pixels wide by 1024 pixels high) liquid crystal color display (LCD), is placed in the central opening HO, and a movable sub-display device DS2, which is a small (e.g., 480 pixels wide by 800 pixels high) liquid crystal color display, is placed to the right of the main display device DS1. The main display device DS1 is a device that displays specific symbols related to the jackpot state in a variable manner, as well as background images and various characters in an animated manner. This display device DS1 has special symbol display sections Da-Dc in the center and a normal symbol display section 19 in the upper right corner. The special symbol display sections Da-Dc may perform reach effects that raise expectations of the arrival of a jackpot state, and appropriate preview effects are performed in and around the special symbol display sections Da-Dc.

The sub display device DS2 normally displays image information in a stationary state with its display screen tilted at an angle that is easy for the player to see. However, during a specified preview performance, the tilt angle is changed to an angle that is easy for the player to see, and the specified preview image is displayed while moving to the left side of the figure.

In other words, the sub-display device DS2 of the embodiment is not just a display device, but also functions as a movable performance body that executes the preview performance. Here, the preview performance by the sub-display device DS2 is set to have a high reliability, and the player will pay attention to the movement of the sub-display device DS2 with great anticipation.

In the game area where the game balls fall and move, there are a first symbol start hole 15a, a second symbol start hole 15b, a first big prize hole 16a, a second big prize hole 16b, a normal prize hole 17, and a gate 18. Each of these prize holes 15 to 18 has a detection switch inside, so that it can detect the passage of the game ball.

A performance stage 14 is arranged above the first symbol start port 15a, and is configured so that the game ball that enters from the inlet IN can enter the first symbol start port 15 after moving in a seesaw or roulette shape. When the game ball enters the first symbol start port 15, the special symbol display sections Da to Dc are configured to start changing.

The second symbol start opening 15b is configured to be opened and closed by an electric tulip equipped with a pair of opening and closing claws on the left and right, and when the stopped symbol after the normal symbol display section 19 changes displays a winning symbol, the opening and closing claws are opened for a predetermined time or until a predetermined number of game balls are detected.

The normal symbol display unit 19 displays normal symbols. When a gaming ball that has passed through the gate 18 is detected, the normal symbols change for a predetermined period of time and then stop displaying a stop symbol determined by a random number value for lottery that is extracted at the time the gaming ball passes through the gate 18.

The first large prize opening 16a is configured with a slide plate that moves back and forth, and the second large prize opening 16b is configured with an opening and closing plate whose lower end is supported by a shaft and opens forward. The operation of the first large prize opening 16a and the second large prize opening 16b is not particularly limited, but in this embodiment, the first large prize opening 16a is configured to correspond to the first pattern starting opening 15a, and the second large prize opening 16b is configured to correspond to the first pattern starting opening 15b.

In other words, when a game ball enters the first symbol start hole 15a, the special symbol display sections Da-Dc start to move, and then when a predetermined jackpot symbol is aligned on the special symbol display sections Da-Dc, the special game that is the first jackpot starts, and the slide plate of the first jackpot opening 16a opens forward, making it easier for the game ball to enter.

On the other hand, when a predetermined jackpot pattern is aligned in the special pattern display sections Da-Dc as a result of the movement started by the game ball entering the second pattern start hole 15b, a special game that is a second jackpot is started, and the opening and closing plate of the second big prize entry hole 16b is opened to facilitate the entry of the game ball. The game value of the special game (jackpot state) varies depending on the aligned jackpot pattern, but the game value that is awarded is determined in advance based on the result of a lottery that corresponds to the timing of the game ball's entry.

In a typical jackpot state, after the opening and closing plate of the big prize opening 16 is opened, it closes after a predetermined time has elapsed or when a predetermined number of game balls (for example, 10 balls) have entered the prize. This operation continues for a maximum of, for example, 15 times, and is controlled to be in a state advantageous to the player. Note that if the stopped pattern after the change in the special pattern display sections Da to Dc is a specific one of the special patterns, a special bonus is given in which the game after the special play ends will be in a high probability state (probability state).

Figure 3(a) is a block diagram showing the overall circuit configuration of the pachinko machine GM that realizes each of the above-mentioned operations. Also, Figure 3(b) is a circuit diagram showing the circuit configuration of the power supply monitor unit MNI arranged on the payout control board 25, and Figure 3(c) is a drawing explaining the specifications of the main display device DS1 used in this embodiment.

First, the specifications of the main display device DS1 used in the embodiment will be described with reference to FIG. 3(c). As described above, the display device DS1 is a liquid crystal color display with 1280 horizontal and 1024 vertical pixels, and is configured so that odd pixels (ODD) and even pixels (EVEN) adjacent to each other in the left-right direction are received by the receiver RV (RVa+RVb) via separate LVDS (Low Voltage Differential Signaling) transmission paths. Therefore, in this embodiment, in response to this specification, the ODD signal is transmitted via the first transmission path LVDS1, and the EVEN signal is transmitted via the second transmission path LVDS2 (lower right of FIG. 3(a)).

In addition, in this display device DS1, the operating clock CK (see FIG. 7) that defines the internal operation of the display device DS1 is specified to have a frequency in the range of 40 MHz to 70 MHz (typical value = 54 MHz). This operating clock CK corresponds to the LVDS clock CLK described below, but for the sake of convenience in the following explanation, the frequency of the operating clock CK is assumed to be a typical value of 54 MHz. In addition, a configuration is described in which the update time FR (Frame Rate) required to update one frame of image is matched to approximately 1/60 seconds for a 54 MHz operating clock CK.

The display device DS1 is configured to simultaneously process two adjacent pixels in the left and right direction of the display screen with one operating clock CK based on the ODD signal received from the first transmission path LVDS1 and the EVEN signal received from the second transmission path LVDS2. As a result, the pixel data of 1280 pixels in one horizontal line is updated with an operating time of 640/54 MHz = 11.85 μS, and this operation is repeated for 1024 lines, updating one frame of 1280 x 1024 pixel image display. The image is updated line by line in a non-interlaced manner, such as the first line → second line ... → 1024th line.

However, as shown in FIG. 3(c), the specifications of the display device DS1 stipulate that a typical waiting time (blank period) of 204 clocks is provided in the horizontal direction, and a typical waiting time (blank period) of 42 rows is provided in the vertical direction. Therefore, the actual screen update period FR taking these blank periods into account is calculated based on the typical values described above as (204 + 640) x (42 + 1024) / 54 MHz ≈ 16.66 mS, so the frame rate FR is approximately 1/60 Hz.

Note that the horizontal waiting time WTh and the vertical waiting time WTv each have a tolerance range for the typical value, and in practice, values other than the typical values listed above can be selected. However, to set the frame rate FR = 1/60 seconds, it is necessary to accurately set the horizontal/vertical waiting times WTh/WTv so that (WTh + 640) x (WTv + 1024)/54 MHz = 1/60 seconds.

On the other hand, this display device DS1 does not particularly need to receive the horizontal synchronization signal HS and the vertical synchronization signal VS, but when transmitting the ODD signal and the EVEN signal, it is required to transmit the H-level data enable signal ENAB. In other words, when a significant signal (ODD/EVEN signal) is being transmitted to the transmission paths LVDS1 and LVDS2, the data enable signal ENAB must be at an active level (H).

Therefore, in this embodiment, based on the specifications of the main display device DS1 described above, the performance control board 23 and the main display device DS1 are LVDS-connected with a dual link transmission path of an LVDS clock CLK with a frequency of 54 MHz (= 1/2 the dot clock DCK) (Figures 5 and 13 (a)). In addition, in the VDP circuit 52 of this embodiment, a horizontal blank period WTh and a vertical blank period WTv that meet the specifications of the main display device DS1 are provided, and when image data (ODD/EVEN signals) are output, the data enable signal ENAB is set to an active level (H level).

That is, as shown in FIG. 4(b), the data valid signal ENAB is configured to be H level only during the horizontal display period THd of the horizontal synchronization period TH. Therefore, the data valid signal ENAB is always L level during the vertical synchronization period TV other than the vertical display period TVd. Note that the horizontal blank period WTh and the vertical blank period WTv adopt values different from their respective typical values (WTh=204/WTv=42), but the specific design values will be described later with reference to FIG. 14.

In any case, the data valid signal ENAB is repeatedly transmitted as a discrete DE signal via the differential signal lines RA2/RB2 in each operating cycle of the LVDS clock CLK. The data valid signal ENAB shown in FIG. 4(b) and FIG. 4(c) is a demodulated DE signal, which is discrete data transmitted via LVDS, and is a continuous discrete DE signal on the time axis. In addition, the vertical synchronization signal VS and the horizontal synchronization signal HS are also repeatedly transmitted following the DE signal (data valid signal ENAB) on the differential signal lines RA2/RB, but the main display device DS1 used in the embodiment does not utilize these synchronization signals VS and HS.

However, the display device DS1 does not prohibit the transmission of the horizontal synchronization signal HS or the vertical synchronization signal VS. However, the internal operations regulated by these synchronization signals are not executed. In other words, the horizontal line feed timing of the display line is determined to be optimal for the internal circuitry of the display device DS1 based on the falling edge of the data enable signal ENAB and the number of operation clocks CK (corresponding to the LVDS clock CLK) after the rising edge of the data enable signal ENAB (640 = 1280/2 in this embodiment), regardless of the received horizontal synchronization signal HS (downward arrow in Figure 4(b)).

The same is true for the vertical line feed timing after one frame of image display, which is determined to be optimal for the internal circuitry of the display device DS1 based on the number of consecutive data enable signals ENAB of a specified pulse width (1024 in this embodiment) and is not affected by the received vertical synchronization signal VS (downward arrow in FIG. 4(c)). In this way, in this embodiment, there is no need to transmit the horizontal synchronization signal HS or vertical synchronization signal VS to the display device DS1, so there is no need to optimally set the pulse widths PWh/PWv of the synchronization signals HS and VS, the front ports FPh/FPv, and the back ports BPh/BPv, and this significantly reduces the control burden on the performance control unit 23 and the VDP circuit 52.

In addition, the internal operation of the display device DS1 is that horizontal and vertical line feed operations are performed at optimal timing based on its own internal configuration, eliminating the risk of unnatural display operations. Incidentally, in the case of a display device that operates based on a horizontal synchronization signal HS or a vertical synchronization signal VS received from the outside, if the pulse width of the synchronization signals HS and VS, or the front porch period and back porch period before and after the synchronization signals HS and VS, are inappropriate, there is a risk that normal display operations will be impaired.

In FIG. 4(a), the first differential signal LVDS1 using differential signal lines RA0-RA3 and RACCLK transmits odd-numbered pixels (ODD signal on side A), and the second differential signal LVDS2 using differential signal lines RB0-RB3 and RBCLK transmits even-numbered pixels (EVEN signal on side B). In this way, in this embodiment, by transmitting two types of ODD signals and EVEN signals over a dual link transmission path, the frequency of the dot clock DCK can be reduced by half, which improves noise resistance and also increases the transmission distance.

Meanwhile, the main display device DS1 has a built-in conversion receiver RV for the ODD and EVEN signals transmitted over the dual link transmission path, and restores the RGB signal from the two LVDS signals (ODD and EVEN signals) to display one frame's worth of image (1280 x 1024 dots). As explained above, each RGB signal is composed of 8 bits, so the main display device DS1 displays a full-color image with a gradation of ²⁸ x ²⁸ x ²⁸ .

Figure 5 is a block diagram showing the internal configuration of the display device DS1 together with the relevant parts of the VDP circuit 52. As shown in the figure, the ODD signal is transmitted to the LVDS-parallel conversion unit RVa via the first LVDS line (A side), and the EVEN signal is transmitted to the LVDS-parallel conversion unit RVb via the second LVDS line (B side). Of the 8-bit RGB data transmitted over the differential lines SA0/SB0, image data R0-R5 and G0 are extracted, and image data G1-G5 and B0-B1 are extracted from the differential lines SA1/SB1.

In addition, image data B2-B5, DE signal, VS signal, and HS signal are output from differential lines SA2/SB2, and image data G6-G7, R6-R7, and B6-B7 are output from differential lines SA3/SB3. Here, the DE signal is nothing but the data valid signal ENAB. Also, as mentioned above, the output VS signal and HS signal are not used.

The LVDS clock CLK of the differential line RACCLK/RBCLK is then supplied to a PLL circuit to generate an operating clock CK with the same frequency as the LVDS clock CLK, 54 MHz. This operating clock CK regulates the internal operation of the LCD controller LCD_CTL, which processes image data corresponding to two RGB pixels (8 bits x 3 x 2) adjacent to each other in the left-right direction of the LCD panel LCD in synchronization with a single operating clock CK.

Therefore, processing of a pixel with 1280 (=640 x 2) dots in the horizontal direction is completed in 11.85 μS (=640/54 MHz), which is the processing time for 640 operation clocks CK. Note that one pixel is composed of three basic RGB pixels, and the image data of the three basic RGB pixels is one byte long each, with a gradation of ²⁸ x ²⁸ x ²⁸ , so the image data of all pixels (1280 dots) on one line is 3 x 1280 bytes long overall.

As shown in Fig. 5, the liquid crystal controller LCD_CNT appropriately controls the source driver SDV, which drives 1280 source signal lines with drive signals of ²⁸ (=256) gradations, and the gate driver GDV, which controls the ON/OFF of 1024 gate signal lines. Specifically, the liquid crystal controller LCD_CNT realizes an image update operation at a frame rate FR = 1/60 Hz by appropriately operating each part based on the DE signal extracted from the LVDS transmission line and the operation clock CK. As confirmed earlier, the DE signal corresponds to the data valid signal ENAB output by the VDP circuit 52.

In this embodiment, the source driver SDV is configured by arranging 10 driver elements each having 384 output terminals. As explained above, all the pixels (1280 dots) on one line of the liquid crystal panel LCD are composed of 3 x 1280 basic pixels of three colors RGB, so 10 driver elements are required to drive them. These 10 driver elements are supplied with image data DAT in sequence from the liquid crystal controller LCD_CNT, which is transferred appropriately based on the start signal SP and the transfer clock DCLK. Then, in synchronization with the latch signal LT, the analog-converted drive signal is supplied to the 3840 source signal lines. As explained above, it takes 11.85 μS (= 640/54 MHz) to update all the pixels (1280 dots) on one line of the liquid crystal panel LCD.

On the other hand, the LCD controller LCD_CNT updates the gate signal lines to be driven by supplying a gate start signal GS and a gate clock signal GCLK to the gate driver GDV. Here, the gate driver GDV is configured with four driver elements, each with 256 output terminals.

The update timing of the gate signal line is determined based on the falling edge of the DE signal and the operating clock CK, and the horizontal line feed period of the gate signal line is counted by the operating clock CK and is calculated as 640+204 clocks in typical value calculation (see FIG. 3(c)). Based on the number of DE signals (1024), the gate signal line to be driven is reset to the initial state, and the gate start signal GS is output at the optimal timing, and the output of the gate clock signal GCLK is resumed. The vertical line feed period of the gate signal line is counted by the operating clock CK and is calculated as 42+1024 clocks in typical value calculation (see FIG. 3(c)). However, as explained above, in this embodiment, the display device DS1 is operated with a design different from the typical value (see FIG. 14).

The main display device DS1 has been described in detail above, but the sub-display device DS2 operates in a similar manner to that shown in FIG. 40, based on the horizontal synchronizing signal HS and vertical synchronizing signal VS received from the VDP circuit 52. However, it is also preferable for the sub-control device DS2 to be configured to operate based on a data enable signal ENAB, rather than based on the horizontal synchronizing signal HS or vertical synchronizing signal VS. The data enable signal ENAB is transmitted to the sub-display device DS2 as a continuous signal ENAB, not in the form of a discrete DE signal (see the lower right of FIG. 13(a)).

Next, returning to FIG. 3(a), the overall circuit configuration of the pachinko machine GM will be described. As shown in FIG. 3(a), this pachinko machine GM is mainly composed of a power supply board 20 that receives AC 24V and outputs various DC voltages (35V, 12V, 5V) together with AC 24V, a main control board 21 that is responsible for the central and overall game control operation, a performance interface board 22 equipped with a circuit element SND for sound performance, a performance control board 23 that executes lamp performance, sound performance, and image performance in a unified manner based on a control command CMD received from the main control board 21, a liquid crystal interface board 24 located between the performance control board 23 and the display devices DS1 and DS2, a payout control board 25 that controls the payout motor M based on the control command CMD' received from the main control board 21 to pay out game balls, and a launch control board 26 that launches game balls in response to the player's operation.

The performance interface board 22, performance control board 23, and liquid crystal interface board 24 are directly connected to male and female connectors without going through wiring cables. Therefore, even if the circuit configuration of each electronic circuit is made complex and advanced, the storage space of the entire board can be minimized, and noise resistance can be improved by shortening the connection lines.

As shown in the figure, the control command CMD' output by the main control board 21 is transmitted to the payout control board 25. On the other hand, the control command CMD output by the main control board 21 is transmitted to the performance control board 23 via the performance interface board 22. Here, the control commands CMD and CMD' are both 16 bits long, but are sent in parallel in two batches of 8 bits each.

The main control board 21 and the payout control board 25 are equipped with computer circuits including a one-chip microcomputer. The performance control board 23 is equipped with a composite chip 50 that has built-in computer circuits such as a VDP circuit (Video Display Processor) 52 and an internal CPU circuit 51. These control boards 21, 25, 23, the circuits mounted on the performance interface board 22 and the liquid crystal interface board 24, and the operations realized by these circuits are sometimes referred to functionally collectively as the main control unit 21, the performance control unit 23, and the payout control unit 25 in this specification. Note that the performance control unit 23 and the payout control unit 25 are sub-control units relative to the main control unit 21.

This pachinko machine GM is broadly divided into a frame side member GM1 surrounded by a dashed line in Figure 3(a) and a board side member GM2 fixed to the back of the game board 5. The frame side member GM1 includes an inner frame 3 to which a glass door 6 and a front panel 7 are pivotally attached, and an outer wooden frame 1 on the outside of that, and is fixedly installed in the game hall for a long period of time regardless of changes in the model. On the other hand, the board side member GM2 is replaced in response to a change in the model, and a new board side member GM2 is attached to the frame side member GM1 in place of the original board side member. All except the frame side member 1 is the board side member GM2.

As shown in the dashed frame in Figure 3(a), the frame side member GM1 includes a power supply board 20, a backup power supply board 33, a payout control board 25, a launch control board 26, a frame relay board 36, and a motor/lamp drive board 37, and these circuit boards are each fixed in appropriate positions to the inner frame 3. Meanwhile, the main control board 21 and the performance control board 23 are fixed to the back of the game board 5, along with the display devices DS1, DS2 and other circuit boards. The frame side member GM1 and the board side member GM2 are electrically connected by centralized connectors C1 to C3, which are centrally located in one place.

The power supply board 20 generates three types of DC voltages (35V, 12V, 5V) based on the AC voltage AC24V distributed from the gaming hall, and distributes each DC voltage to the performance interface board 22 via the centralized connection connector C2. The three types of DC voltages (35V, 12V, 5V) are also distributed to the payout control board 25 together with the AC voltage AC24V. The DC voltages (35V, 12V, 5V) distributed to the payout control board 25 are then distributed to the main control board 21 together with the backup power supply BAK via the centralized connection connector C1.

The 35V DC is used as the driving power source for the ball feed solenoid and launch solenoid for the ball launch operation, and for the electromagnetic solenoid that opens and closes the electric tulip (variable winning device) and the large winning port 16. The 12V DC is used as the driving power source for the LED lamps and motors controlled by each control board, and as the power supply voltage for the digital amplifier, while the 5V DC is used as the power supply voltage for the one-chip microcomputers of the payout control board 25 and the main control board 21, and for the logic elements mounted on each control board. The 5V DC is stepped down by the DC/DC converter of the performance interface board 22, and the stepped down voltages of various levels are then used as the power supply voltage for various computer circuits (such as the composite chip 50 and the audio processor 27).

The backup power supply BAK is a DC 5V power supply for retaining data in the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 25 after the power is cut off, and is realized, for example, by an electric double-layer capacitor. In this embodiment, a dedicated backup power supply board 33 is provided, and the electric double-layer capacitor placed on the backup power supply board 33 is configured to be charged by the DC voltage of 5V received from the payout control board 25 during game operation.

After the power is cut off, the backup power supply BAK retains the data in the built-in RAM of the one-chip microcomputers of the main control unit 21 and the payout control unit 25, so that the main control unit 21 and the payout control unit 25 can resume the gaming operation before the power was cut off after the power is turned on. The backup power supply board 33 is equipped with an electric double layer capacitor that can retain the memory contents of the built-in RAM of each one-chip microcomputer for at least several days.

In this embodiment, unlike the conventional device configuration, the power supply abnormality signal ABN indicating an abnormal drop in the AC voltage AC24V is generated not by the power supply board 20 but by the power supply monitor unit MNT of the dispensing control board 25. As shown in FIG. 3(b), the power supply monitor unit MNT is configured to have a full-wave rectifier circuit that rectifies the AC24V received from the power supply board 20, a photodiode D that receives the output of the full-wave rectifier circuit and emits light, a phototransistor TR that uses the DC voltage of 5V received from the power supply board 20 as a power source and turns ON based on the light emitted by the photodiode D, and an output unit that outputs an H-level detection signal ABN (power supply abnormality signal) based on the ON operation of the phototransistor TR. The photodiode D and the phototransistor TR constitute a photocoupler PH.

In the above configuration, after the power is turned on, the photocoupler PH quickly turns ON, causing the power supply abnormality signal ABN to go to the normal level (H). However, if the AC power supply subsequently drops abnormally for some reason (normally due to a power cut), the photocoupler PH turns OFF, causing the power supply abnormality signal ABN to go to the abnormal level (L). This power supply abnormality signal ABN is transmitted to the one-chip microcomputer of the payout control board 25, and is also transmitted to the one-chip microcomputer of the main control board 21 via the centralized connection connector C1. Therefore, each one-chip microcomputer that receives the abnormal level of the power supply abnormality signal ABN executes a backup process to store the necessary information in its own built-in RAM. As explained above, the information in the built-in RAM is maintained by the backup power supply BAK, so that the game operation before the power cut can be resumed after the power is turned on.

As shown in FIG. 3(a), the performance interface board 22 is equipped with an audio circuit SND such as an audio processor 27, and the performance control board 23 is equipped with a composite chip 50 that incorporates computer circuits such as a VDP circuit 52 and an internal CPU circuit 51. Hereinafter, the internal CPU circuit may be abbreviated as the CPU circuit.

The performance interface board 22 is equipped with reset circuits RST3 and RST4 that detect an increase in the power supply voltage when the power is turned on and generate various reset signals RT3 and RT4. First, the reset circuit RST3 generates the reset signal RT3 based on the DC voltages of 12V and 5V distributed from the power supply board 20. The reset signal RT3 then resets the power supply to only the audio memory 28 and is transmitted directly to the performance control board 23.

As shown in FIG. 6(a), the reset signal RT3 transmitted to the performance control board 23 is ANDed with the output of the WDT (Watch Dog Timer) circuit 58 in the AND gate G1, and the result is the system reset signal SYS, which resets the power supply to the CPU circuit 51 and the VDP circuit 52 (see FIG. 6(a) and FIG. 6(d)).

After the power is turned on, the reset signal RT3 generated by the reset circuit RST3 remains at L level for a predetermined time as a power reset signal, and then rises to H level. However, if thereafter, either the DC voltage of 12V or the DC voltage of 5V drops (usually when the power is cut off), the system reset signal SYS also drops to L level in response to the drop in the level of the reset signal RT3, and the CPU circuit 51 and VDP circuit 52 of the performance control board 23 are put into a stopped state.

This system reset signal SYS also changes based on the output of the WDT circuit 58 (normally at H level). Therefore, when the reset signal RT3 is in the H state and the output of the WDT circuit 58 drops to L level due to a program runaway or the like, the system reset signal SYS also changes to L level, abnormally resetting the CPU circuit 51 and VDP circuit 52 (see FIG. 6(d)).

On the other hand, the reset circuit RST4 generates a reset signal RT4 based on 3.3V generated by dropping the 5V distributed from the power supply board 20. This reset signal RT4 resets the power supply of the audio processor 27 as a power supply reset signal when the power is turned on.

As shown in the figure, the reset circuit RST4 is also supplied with the system reset signal SYS returned from the performance control board 23, so when the CPU circuit 51 or VDP circuit 52 is abnormally reset, the audio processor 27 is also abnormally reset in synchronization with the abnormal reset of these circuits. As a result, the audio performance returns to its initial state along with the image and lamp performances, and there is no risk of unnatural audio performance continuing.

Next, the payout control board 25, which is the frame side member GM1, and the main control unit 21, which is the board side member GM2, are each equipped with reset circuits RST1 and RST2, and are configured to generate a power reset signal when the power is turned on, and to reset the power of each computer circuit.

In this way, in this embodiment, the reset circuits RST1 to RST4 are arranged in the main control unit 21, the payout control unit 25, and the performance interface board 22, respectively, and the system reset signal SYS is not transmitted between the circuit boards. In other words, since there is no wiring cable to transmit the system reset signal SYS, the risk of the computer circuit being abnormally reset by noise superimposed on the wiring cable is eliminated.

However, the reset circuits RST1 and RST2 provided in the main control unit 21 and the payout control unit 25 each have a built-in watchdog timer, and if they do not receive a regular clear pulse from the CPU of each control unit 21, 25, the CPU is forcibly reset.

The main control unit 21 is also provided with an initialization switch SW that can be operated by an attendant, and is configured to output a RAM clear signal CLR indicating whether the initialization switch SW has been turned ON when the power is turned on. This RAM clear signal CLR is transmitted to the one-chip microcomputers of the main control unit 21 and the dispensing control unit 25, and determines whether or not to initialize the entire area of the built-in RAM of the one-chip microcomputer of each control unit 21, 25.

As explained above, the one-chip microcomputers of the main control unit 21 and the dispensing control unit 25 receive a power abnormality signal ABN from the power monitor MNT located in the dispensing control unit 25, and start the necessary termination processing prior to a power outage or closing of business.

As shown in FIG. 3(a), the main control unit 21 receives from the payout control unit 25 a prize ball count signal indicating the payout operation of game balls, a status signal CON related to abnormalities in the payout operation, and an operation start signal BGN. The status signal CON includes, for example, an out-of-supply signal, a payout shortage error signal, and a lower tray full signal. The operation start signal BGN is a signal that notifies the main control unit 21 that the initial operation of the payout control unit 25 has been completed after power is turned on.

The main control unit 21 also receives switch signals from the detection switches built into each winning slot 16-18 on the game board, while driving solenoids such as electric tulips. The solenoids and detection switches are configured to operate on the power supply voltage VB (12V) distributed from the main control unit 21. Furthermore, each switch signal indicating the winning status of the symbol start slot 15 is converted into a TTL level or CMOS level switch signal by an interface IC that operates on the power supply voltage VB (12V) and power supply voltage Vcc (5V) before being transmitted to the main control unit 21.

As explained above, the performance interface board 22 receives various levels of DC voltage (5V, 12V, 35V) from the power supply board 20 via the centralized connection connector C2 (see Figures 3(a) and 6(a)). The 12V DC voltage is the power supply voltage for the digital amplifier 29 and is also used as the drive voltage for LED lamps and the like. The 35V DC voltage is distributed to appropriate locations in the play frame and is used as the drive voltage for solenoids that move movable objects back and forth.

The DC voltage of 5V is supplied as a power supply voltage to the circuit elements in various parts of the performance interface board 22, and is also supplied to two DC/DC converters DC1 and DC2 to generate 3.3V and 1.0V (see FIG. 6(a)). The generated DC voltages of 3.3V and 1.0V are supplied to the audio processor 27 as power supply voltages for I/O (input/output) and the chip core, respectively. The DC voltage of 3.3V also becomes the base voltage for the power supply reset signal RT4 generated by the reset circuit RST4.

The 5V DC voltage distributed to the performance interface board 22 is distributed to the performance control board 23 together with the 3.3V generated by the DC/DC converter DC1. The 3.3V DC voltage distributed to the performance control board 23 is then supplied as a power supply voltage to the composite chip 50, PROM 53, and CGROM 55.

As shown in FIG. 6(a), two DC/DC converters DC3 and DC4 are arranged on the performance control board 23, and generate 1.5V and 1.05V based on the DC voltage of 5V supplied to each of them. Here, the DC voltage of 1.05V is the power supply voltage for the chip core of the composite chip 50, and the DC voltage of 1.5V is the power supply voltage for I/O (input/output) with the DRAM 54. Therefore, the DC voltage of 1.5V is also supplied to the DRAM 54 as the power supply voltage.

As shown in FIG. 3(a), the performance interface board 22 receives the control command CMD and strobe signal STB from the main control unit 21 and transfers them to the performance control board 23. More specifically, as shown in FIG. 6(a), the control command CMD and strobe signal STB are transferred to the composite chip 50 (CPU circuit 51) of the performance control board 23 via the input buffer 40. Here, the strobe signal STB is the received interrupt signal IRQ_CMD, and the performance control CPU 63 obtains the control command CMD based on the interrupt processing program (interrupt handler) that is started in response to the received interrupt signal IRQ_CMD.

As shown in FIG. 6(a), the input buffer 44 of the performance interface board 22 receives switch signals of the chance button 11 and the volume switch VLSW from the frame relay boards 35 and 36, and transmits each switch signal to the CPU circuit 51 of the performance control board 23. Specifically, it transmits to the CPU circuit 51 a 3-bit encoder output indicating the contact position (0-7) of the volume switch VLSW, and a 1-bit signal indicating the ON/OFF state of the chance button 11.

The performance interface board 22 is also connected to the lamp drive board 30 and the motor lamp drive board 31, and is also connected to the lamp drive board 37 via the frame relay boards 35 and 36. As shown in the figure, an output buffer 42 is arranged corresponding to the lamp drive board 30, and an input buffer 43a and an output buffer 43b are arranged corresponding to the motor lamp drive board 31. For convenience, the input buffer 43a and the output buffer 43b are collectively referred to as the input/output buffer 43 in FIG. 6(a). The input buffer 43a receives the outputs SN0 to SNn of the origin sensor that grasps the current position of the movable performance object (the rotational position of the performance motors M1 to Mn), and transmits them to the CPU circuit 51 of the performance control board 23.

The lamp drive board 30, motor lamp drive board 31, and lamp drive board 37 are equipped with the same type of driver IC, and the performance interface board 22 transfers the serial signal received from the performance control board 23 to each driver IC. Specifically, the serial signal is a lamp (motor) drive signal SDATA and a clock signal CK, and the drive signal SDATA is transmitted to each driver IC in a clock-synchronized manner, and lamp performances using numerous LED lamps and electric lamps, and role-play performances using performance motors M1 to Mn are executed.

In this embodiment, the lamp effects are performed by three lamp groups CH0 to CH2, and the lamp drive board 37 receives the lamp drive signal SDATA0 of CH0 in synchronization with the clock signal CK0 via the frame relay boards 35 and 36. The series of lamp drive signals SDATA0 transmitted as serial signals are output from the driver IC to the lamp group CH0 when the operation control signal ENABLE0 changes to the active level, thereby updating the lighting state of all the lamps at once.

The above also applies to the lamp drive board 30, where the driver IC of the lamp drive board 30 receives the lamp drive signal SDATA1 for the lamp group CH1 in synchronization with the clock signal CK1, and simultaneously updates the lighting state of the lamp group CH1 when the operation control signal ENABLE1 changes to the active level.

Meanwhile, the driver IC mounted on the motor lamp drive board 31 drives the lamp group CH2 in response to a lamp drive signal transmitted in clock synchronous fashion, and drives the performance motor group M1-Mn, which is made up of multiple stepping motors, in response to a motor drive signal transmitted in clock synchronous fashion. The lamp drive signal and motor drive signal are a series of serial signals SDATA2 that are serially transmitted in synchronization with the clock signal CK1, and the driver IC that receives them updates the drive state of the lamp group CH2 and the motor group M1-Mn when the operation control signal ENABLE2 changes to the active level.

Next, the audio circuit SND will be described. As shown in FIG. 6(a), the performance interface board 22 is equipped with an audio processor (audio synthesis circuit) 27 that reproduces audio signals based on instructions received from the CPU circuit 51 (performance control CPU 63) of the performance control board 23, an audio memory 28 that stores compressed audio data, which is the original data of the reproduced audio signal, and a digital amplifier 29 that receives the audio signal output from the audio processor 27.

The audio processor 27 is configured with a built-in WDT circuit that automatically resets the internal circuit settings to default values (initial values) when the internal circuit operates abnormally, and an audio control register SRG. The audio processor 27 accesses the audio memory 28 based on the operating parameters (setting values by audio commands) received by the audio control register SRG from the performance control CPU 63, and reproduces and outputs the required audio signals.

6A, the audio processor 27 and the audio memory 28 are connected by a 26-bit audio address bus and a 16-bit audio data bus. Therefore, the audio memory 28 can store 1 Gbit (= ² × 16) of data.

The sound control registers SRG are divided into register banks 1 to 6, each identified by a register number from 00H to FFH. Therefore, a specified setting operation is realized by the performance control CPU 63 specifying the register bank and then writing a 1-byte operation parameter to the sound control register SRG of the specified register number (1 byte long).

In this embodiment, the register number (00H to FFH) of the sound control register SRG corresponds to the address space CS3 of the performance control CPU 63. For example, when setting the operating parameter YYH in the sound control register SRG with register number XXH, the performance control CPU 63 writes XXH to address zero in the address space CS3, and then writes YYH to address 1. In other words, the performance control CPU 63 writes XXH and YYH in that order to its data bus. Note that in this specification, the suffix H and the prefixes 0X/0x indicate that the numerical values are expressed in hexadecimal.

In addition, in this specification, the address space CS0 to CS7 refers to external memory (excluding built-in memory) for the CPU circuit 51, which can specify the memory type, including whether it is volatile or not, and the data bus width (8/16/32 bits). This address space CS0 to CS7 is selected by different chip select signals CS0 to CS7, and is configured to be configurable so that the READ/WRITE control signal that functions during READ/WRITE access can be optimized according to the memory type. This setting operation is executed for the bus state controller 66.

Figure 6 (e) illustrates the setting operation of the performance control CPU 63 to the sound register SRG, showing the contents of the 2-bit address bus A1-A0 and the 1-byte data bus D7-D0. In this embodiment, the chip select signal CS3 is set at power-on so that it automatically becomes active when the address space CS3 is accessed; this will be described later with reference to Figures 8 and 15.

In any case, in the case of this embodiment, the compressed audio data stored in the audio memory 28 is compressed data of phrases specified by 13-bit phrase numbers NUM (000H to 1FFFH), and a maximum of 8192 types (=2 ¹³ ) of a series of background music (BGM) or a collection of performance sounds (warning sounds) are stored corresponding to the phrase numbers NUM. The phrase numbers NUM are specified by the setting values (operation parameters) of the audio commands transmitted from the performance control CPU 63 to the audio control register SRG of the audio processor 27.

As described above, the audio memory 28 having the above configuration is power-reset by the reset signal RT3, and the audio processor 27 is power-reset by the reset signal RT4. As shown in FIG. 6(c), after power-on, the reset signal RT4 rises to H level after a predetermined assertion period ASRT (L level section). In this embodiment, the internal circuit of the audio processor 27 then automatically functions and executes the initialization sequence process. Note that this initialization sequence process is an internal operation that is executed in a predetermined procedure, and the performance control CPU 63 cannot access the audio register SRG while the initialization sequence process is in operation.

When the internal initialization sequence process is completed, the interrupt signal IRQ_SND to the CPU circuit 51 changes to L level, and the CPU circuit 51 (performance control CPU 63) executes an interrupt processing program based on the interrupt signal IRQ_SND. The interrupt signal IRQ_SND is then returned to H level based on a specified command, the details of which will be described further below with reference to FIG. 17(c).

As shown in FIG. 6(a), the data bus and address bus of the CPU circuit 51 of the performance control unit 23 extend to the clock circuit (real time clock) 38 and performance data memory 39 mounted on the liquid crystal interface board 24. The clock circuit 38 is connected to the lower 4 bits of the address bus and the lower 4 bits of the data bus of the CPU circuit 51, and when the clock circuit 38 is selected by the chip select signal CS4, the CPU circuit 51 is configured to be able to access the internal registers (which have 4-bit address values) at will.

The performance data memory 39 is a high-speed accessible memory element SRAM (Static Random Access Memory), and is connected to 16 bits of the address bus of the CPU circuit 51 and the lower 16 bits of the data bus. When the chip is selected by the chip select signal CS4, the game performance information and other information stored in the SRAM (performance data memory) 39 can be appropriately read/written by the CPU circuit 51. In the address space CS4 selected by the chip select signal CS4, addresses 0 to 15 are assigned to the clock circuit 38, and are therefore not used by the SRAM 39.

The clock circuit 38 and the performance data memory 39 are driven by a secondary battery (not shown), which is charged appropriately by the power supply voltage from the power supply board 20 during game operation. Therefore, even after the power is cut off, the clock circuit 38 continues to keep time, and the game performance information stored in the performance data memory 39 is permanently stored (non-volatile). The clock circuit (RTC) 38 is configured to be able to output an interrupt signal IRQ_RTC to the CPU circuit 51 (RTC interrupt). This RTC interrupt includes an alarm interrupt that can specify the date, day of the week, hour, minute, and second, and a timer interrupt that is activated after a specified time has elapsed. In this embodiment, an alarm interrupt is used to update the daily game performance information at the end of business each day.

As shown on the right side of Figure 6(a), the performance control board 23 is equipped with a composite chip 50 incorporating a CPU circuit 51 and a VDP circuit 52, a control memory (PROM) 53 that stores the control program for the CPU circuit 51, a DRAM (Dynamic Random Access Memory) 54 that can access large amounts of data at high speed, and a CGROM 55 that stores large amounts of CG data required for performance control.

As will be described later with reference to FIG. 9, in this embodiment, the control memory (PROM) 53 is located in the address space CS0 selected by the chip select signal CS0. Also, the DRAM (Dynamic Random Access Memory) 54, which is configured with DDR (Double-Data-Rate 3), is located in the address space CS5 selected by the chip select signal CS5.

Figure 7 (a) is a circuit block diagram illustrating the composite chip 50 that constitutes the performance control unit 23, including related circuit elements. As shown in the figure, the composite chip 50 of the embodiment includes a CPU circuit 51 that issues a display list DL at predetermined time intervals, and a VDP circuit 52 that generates image data based on the issued display list DL to drive the display devices DS1 and DS2. The CPU circuit 51 and the VDP circuit 52 are connected via a CPUIF circuit 56 that relays the data sent and received by each other.

The VDP circuit 52 includes an audio circuit SND that performs the same functions as the audio processor 27, but in the first embodiment described below, the audio circuit SND is not used. However, if the audio circuit SND built into the VDP circuit 52 is used, as in the last embodiment described below, the audio memory 28 and audio processor 27 will not be required.

First, the CPU circuit 51 receives the oscillation output (e.g., 100/3 MHz) of the oscillator OSC1 at the HCLKI terminal and multiplies the frequency (e.g., by 8) to generate a CPU operating clock of about 266.7 MHz (see FIG. 13(b)). Here, the oscillator OSC1 is configured to output a spread spectrum wave, thereby providing EMI (Electromagnetic Interference) measures to prevent radio interference/electromagnetic jamming.

In the present embodiment, the CPU operating clock can be generated based on the output of oscillator OSC2 (described later) instead of oscillator OSC1, making oscillator OSC1 unnecessary. However, in a configuration that uses a single oscillator, the frequency multiplication ratio of the PLL circuit is a fixed value (e.g., 5) the same as that of the system clock described below, so the frequency of the CPU operating clock is 200 MHz (= 40 MHz x 5), the same as the system clock of the VDP circuit 52.

While this configuration has the advantage of sharing the operating cycles of the built-in CPU circuit 51 and the VDP circuit 52, it runs counter to the desire to make the CPU operate as fast as possible. In other words, since the VDP operation cannot be made faster than a certain level, it cannot reliably meet the demand for faster CPU operation. Therefore, in this embodiment, two oscillators are provided to optimize the operating cycles of the VDP circuit 52 and the CPU circuit 51, respectively. Also, by providing a separate oscillator OSC1, it is possible to improve the EMI countermeasures mentioned above.

In light of the above, the VDP circuit 52 will be explained. The VDP circuit 52 receives the oscillation output (40 MHz) of an oscillator OSC2, which is separate from the oscillator OSC1, at the PLLREF terminal, and multiplies the frequency in a PLL (Phase Locked Loop) circuit to produce the system clock for the VDP circuit 52. The frequency multiplication ratio of the PLL circuit is fixedly determined by the setting value of a specific setting terminal. In this embodiment, the setting value of the setting terminal (3-bit PLLMD terminal) is a fixed value of 5, so the system clock for the VDP circuit 52 is 200 MHz (= 40 MHz x 5) (see FIG. 13(b)).

In this embodiment, the dot clocks DCK _A to DCK _C that regulate the operation of the display circuits 74A to 74C and the DDR clock of the external DRAM 54 are also generated based on the oscillation output (40 MHz) of the oscillator OSC2. In other words, the output (40 MHz) of the oscillator OSC2 functions as a reference clock for the entire VDP circuit 52.

13 and 14, the display circuits 74A to 74C usually drive display devices with different specifications, so the dot clocks DCK _A to DCK _C that define the operation of the display circuits 74A to 74C must correspond to the specifications of the display devices to be driven. Based on this requirement, in this embodiment, the display circuits 74A to 74C are configured to receive one of the output clocks (DCLKAI to DCLKCI) of the dedicated oscillation circuits DCLKA to DCLKC and use it as the dot clocks DCK _A to DCK _C.

When this configuration is utilized, it becomes unnecessary to design the multiplication ratio and division ratio described later, or to perform setting processing in the VDP register RGij, and it is possible to easily optimize the frequencies of the dot clocks DCK _A to DCK _C. That is, it is also possible to provide a dedicated oscillator circuit DCLKA with an oscillation frequency F _DOT1 corresponding to the dot clock frequency F _DOT1 of the main display device DS1, and to provide a dedicated oscillator circuit DCLKB with an oscillation frequency F _DOT2 corresponding to the dot clock frequency F _DOT2 of the sub-display device DS2.

However, when such a configuration is adopted, a dedicated oscillator circuit is required corresponding to the number of display devices, and the device configuration becomes complicated. Therefore, in this embodiment, in order to simplify the device configuration, the dot clocks DCK _A /DCK _B of the display circuits 74A / 74B are generated based on the oscillation output (40 MHz) of the oscillator OSC2. Specifically, as shown in Figure 13 (b), for the display circuit 74A that drives the main display device DS1, a dot clock DCK _A with a frequency of 108 MHz is generated by performing a predetermined multiplication process (x108) and a frequency division process (1/40) on the oscillation output (40 MHz) of the oscillator OSC2.

Similarly, for the display circuit 74B that drives the sub-display device DS2, a dot clock DCK B with a frequency F _dot = 27 MHz is generated by performing a predetermined multiplication process (×108) and division process (1/160) on the oscillation output (40 MHz) of the oscillator _OSC2 . Designing these multiplication and division ratios is quite complicated, and it would be easier to provide a dedicated oscillation circuit, but in this embodiment, emphasis is placed on simplifying the device configuration, and a dedicated oscillation circuit is not provided.

In any case, the dot clocks DCK _A to DCK _C are set individually for each of the display circuits 74A to 74C, but in this specification, these dot clocks DCK _A to DCK _C may be collectively referred to as the "display clock DCK." In the following description, the dot clocks DCK _A and DCK _B may be abbreviated to the "dot clock DCK" for convenience.

In this embodiment, since a low-speed LVDS output configuration is not adopted, the LVDS clock CLK of the LVDS signal output via the display circuit 74A is generated through the same process as the dot clock DCK _A and has a frequency of 108 MHz. However, since a dual link transmission path is adopted in this embodiment, the actual frequency of the LVDS clock CLK is 54 MHz as explained in relation to Fig. 4. If a single link transmission path is adopted, the frequency of the LVDS clock CLK is 108 MHz.

As described above, in this embodiment, the oscillation output (40 MHz) of oscillator OSC2 is used as the reference clock for the system clock, dot clock DCK, and DDR clock. Considering the importance of this, oscillator OSC2 is configured to operate at the same power supply voltage of 3.3 V as VDP circuit 52, and to oscillate and output the reference clock on condition that output enable terminal OE is at H level (= 3.3 V). In the unlikely event that the power supply voltage of 3.3 V drops below a predetermined level, normal performance operation cannot be expected, so a non-maskable interrupt (NMI) is generated.

The composite chip 50 is also provided with an HBTSL terminal, and based on the logic level of the HBTSL terminal, it is determined whether the boot program (initial setting program) executed after power-on (CPU reset) is stored in the CGROM 55 (HBTSL = H) or in some other memory (HBTSL = L). As shown in the figure, in this embodiment, HBTSL is set to the L level, and address zero of the address space CS0 of the performance control CPU 63 is assigned to a location other than the CGROM; specifically, the address space CS0 is assigned to the control memory 53.

On the other hand, when the HBTSL terminal is set to the H level (see dashed line), address zero of the address space CS0 of the performance control CPU 63 is assigned to the CGROM 55. In this case, the memory type and bus width (64/32/16 bits) of the CGROM 55 are determined based on the input values to the 2-bit HBTBWD terminal and the 4-bit HBTRMSL terminal, respectively. These points will be discussed further below with reference to Figure 37.

Next, the CPUIF circuit 56 that relays data transmitted and received between the CPU circuit 51 and the VDP circuit 52 will be described. As shown in FIG. 7(a), the CPUIF circuit 56 is connected to a control memory (PROM) 53 that stores control programs and necessary control data in a non-volatile manner, and a work memory (RAM) 57 with a storage capacity of about 2 MB, each of which is configured to be accessible from the CPU circuit 51. As explained above, the control memory (PROM) 53 is located in the address space CS0 selected by the chip select signal CS0, and the work memory (RAM) 57 is located in the address space CS6 selected by the chip select signal CS6.

In this work memory (RAM) 57, a DL buffer BUF is reserved for temporarily storing a display list DL in which a series of instruction commands for specifying each frame of the display devices DS1 and DS2 are written. In this embodiment, the series of instruction commands include texture load commands such as a TXLOAD command for reading image material (texture) from the CGROM 55 and decoding (expanding), texture setting commands such as a SETINDEX command having a function of specifying the VRAM area (index space) to decode (expand) in advance, primitive drawing commands such as a SPRITE command for placing the image material after decoding (expanding) at a predetermined position in the virtual drawing space, environment setting commands such as a SETDAVR command and a SETDAVF command for specifying the drawing area to be actually drawn on the display device from the images drawn in the virtual drawing space by the drawing commands, and an index table control command (WRIDXTBL) related to the index table IDXTBL that manages the index space.

In addition, FIG. 11(c) shows the relationship between the virtual drawing space (horizontal X direction ±8192: vertical Y direction ±8192), the drawing area that can be arbitrarily set in the virtual drawing space, and the actual drawing area in the frame buffers FBa and FBb that temporarily store image data to be output to the display devices DS1 and DS2.

Next, the CPU circuit 51 is a circuit with the same performance as a general-purpose one-chip microcomputer, and is configured with a performance control CPU 63 that controls the image performance in an integrated manner based on the control program in the control memory 53, a watchdog timer (WDT) that forcibly resets the CPU when the program goes out of control, an internal RAM 59 with a storage capacity of about 16 kbytes and used as a working area for the CPU, a DMAC (Direct Memory Access Controller) 60 that realizes data transfer without going through the CPU 63, a serial input/output port (SIO) 61 with multiple input ports Si and output ports So, a parallel input/output port (PIO) 62 with multiple input ports Pi and output ports Po, and an operation control register REG in which a setting value is set to control the operation of each of the above-mentioned parts. However, in this embodiment in which an external WDT circuit 58 is provided, the watchdog timer (WDT) built into the CPU circuit 51 is not used.

For convenience, the term "input/output port" is used in this specification, but in the performance control unit 23, the input/output port includes an input port and an output port that operate independently. This also applies to the input/output circuit 64p and the input/output circuit 64s described below.

The parallel input/output port 62 is connected to an external device (performance interface board 22) through an input/output circuit 64p, and the performance control CPU 63 receives the 3-bit encoder output of the volume switch VLSW, the switch signal of the chance button 11, the control command CMD, and the interrupt signal STB via the input circuit 64p. The 3-bit encoder output and 1-bit switch signal are supplied to the parallel input/output port (PIO) 62 via the input/output circuit 64p.

Similarly, the received control command CMD is supplied to the parallel input/output port (PIO) 62 via the input/output circuit 64p. The strobe signal STB is also supplied to the interrupt terminal of the performance control CPU 63 via the input/output circuit 64p, thereby starting the reception interrupt process. Therefore, the performance control CPU 63, which has grasped the control command CMD based on the reception interrupt process, will unifiedly control the sound performance, lamp performance, motor performance, and image performance corresponding to this control command CMD through a performance lottery, etc.

In this embodiment, the SMC (Serial Management Controller) 78 of the VDP circuit 52 is used for lamp and motor effects, although this is not limited thereto. The SMC 78 is a composite controller incorporating an LED controller and a Motor controller, and is configured to be able to output serial signals in a clock-synchronized manner. The Motor controller is also configured to be able to output latch pulses at any timing based on the set value in a specific control register 70, and is also configured to be able to input serial signals in a clock-synchronized manner.

In this embodiment, the motor drive signal and LED drive signal are output from the SMC unit 78 in synchronization with the clock signal, while a latch pulse is output as an operation control signal ENABLE at an appropriate timing. Also, the origin sensor signals SN0 to SNn from the performance motor groups M1 to Mn are configured to be input serially in a clock synchronization system.

As explained with reference to FIG. 6(a), the clock signals CK0-CK2, drive signals SDATA0-SDATA2, and operation control signals ENABLE0-ENABLE2 are transmitted to the appropriate drive boards 30, 31, and 37 via output buffers 41-43. In addition, the origin sensor signals SN0-SNn are serially input from the motor lamp drive board 31 to the SMC unit 78 via the input/output buffer 43.

However, in this embodiment, it is not necessary to use the SMC unit 78. In other words, the CPU circuit 51 has a built-in general-purpose serial input/output port SIO61, which can be used to execute lamp and motor effects.

Specifically, as shown by the dashed lines in Figure 7(a), in the configuration shown by the dashed lines, clock signals CK0 to CK2 and drive signals SDATA0 to SDATA2 are output via an input/output circuit 64s internally connected to the serial input/output port SIO61, and operation control signals ENABLE0 to ENABLE2 are output via an input/output circuit 64p. Note that, for convenience, these are referred to as input/output ports and input/output circuits, but it is the output ports and output circuits that actually function.

Here, the serial output port SO is configured to incorporate a 16-stage FIFO register. The DMAC circuit 60 is configured to start up upon receiving an operation start instruction (see ST18 in FIG. 20(b)) from the performance control CPU 63, read the necessary drive data in order from the lamp/motor drive table (see FIG. 20(b)), and transfer it by DMA to the FIFO register of the serial output port SO. The drive data stored in the FIFO register is output serially from the serial output port SO in a clock-synchronized manner. Note that the DMAC circuit has multiple DMA channels (e.g., seven), but is configured to DMA transfer lamp drive data using the third DMA channel, which has a lower priority, and DMA transfer motor drive data using the first DMA channel, which has the highest priority.

The operation control register REG built into the CPU circuit 51 is an 8-bit, 16-bit, or 32-bit register with a register number (address value) starting from 0xFF400000, and is configured to be appropriately accessible for WRITE/READ from the performance control CPU 63 (see Figure 9). Therefore, due to the influence of noise, etc., there is a possibility that an irrational value may be set in the operation control register REG.

However, for example, the combined chip 50 can be reset as an abnormality by intentionally executing an infinite loop process and activating the external WDT circuit 58. In this case, the value of the operation control register REG is returned to the same default value (initial value) as after power-on, and the value of the VDP register RGij in the VDP circuit 52 is also returned to the default value (initial value), thereby resolving the abnormal state.

Figure 6(b) shows the circuit configuration related to this reset operation, and is a drawing explaining the reset mechanism characteristic of this embodiment. In this specification, the VDP register denoted as RGij does not mean the operation control register REG built into the CPU circuit 51, but any one of the control register group 70 (see Figure 9) that controls the internal operation of the VDP circuit 52. Also, the system control circuit 520 shown in Figure 6(b) means the internal control circuit of the VDP circuit 52 that functions based on the setting value of the VDP register RGij (any one of the control register group 70 in Figure 9) (see Figure 6(a)). Note that the VDP register RGij is located in the address space CS7 selected by the chip select signal CS7 in the address map of the performance control CPU 63.

To explain the reset mechanism based on the above, as shown in FIG. 6(b), the composite chip 50 is configured so that the internal circuitry can be reset via three OR gates G2 to G4, which receive the logically inverted system reset signal SYS bar. However, in this embodiment, as shown by the dashed line, the built-in WDT is not enabled, so the input terminal and output terminal of OR gate G2 are directly connected.

In any case, a pattern check circuit CHK is provided between the CPU circuit 51 and the VDP circuit 52, and the pattern check circuit CHK is configured to output a reset signal RST on condition that a predetermined keyword sequence (a reset code sequence) is received from the parallel input/output port (PIO) 62.

The internal circuitry of the composite chip 50 is divided into three parts: (1) the CPU circuit 51, (2) the display circuit 74 of the VDP circuit 52, and (3) the non-display circuitry in the VDP circuit 52. Each part is configured to receive reset signals from the first to third reset paths from OR gates G2 to G4.

First, the OR gate G2, whose input/output terminals are directly connected, is associated with the first reset path, and is configured to perform a system reset of the entire CPU circuit 51 based on the system reset signal SYS bar. The OR gate G3 is associated with the second reset path, and is configured to receive the system reset signal SYS bar and the reset signal RST from the pattern check circuit CHK, and to reset the entire VDP circuit 52 based on OR logic.

This second reset path is used not only for the power reset operation when the power is turned on, but also when the performance control CPU 63 detects a specific abnormality and abnormally resets the entire VDP circuit 52 to return it to its initial state. Specifically, if it is determined that a serious abnormality has occurred based on a specific status register RGij that indicates the internal operation of the VDP circuit 52, a reset signal RST is generated from the pattern check circuit CHK to abnormally reset the entire VDP circuit 52. The display circuit 74 is abnormally reset via the second reset path → third reset path via OR gate G4.

On the other hand, the internal circuits built into the VDP circuit 52 are configured so that they can be individually reset when necessary via the fourth reset path. The internal circuits that can be individually reset include the index table IDXTBL, data transfer circuit 72, preloader 73, display circuit 74, drawing circuit 76, SMC circuit 78, and audio circuit SND shown in FIG. 7(a), and the ICM circuit shown in FIG. 12.

The method for realizing the individual reset operation is as shown in the lower part of FIG. 6(b). For example, the display circuit 74 is reset via the fourth reset path 4A → the third reset path by writing the first reset value to a specific VDP register RGij (system command register).

In addition, each internal circuit (72, 73, 74, 76, SND, ...) of the VDP circuit 52 is individually reset by (1) writing a setting value that identifies the target circuit to the first VDP register RGij (reset RQ register), and then (2) writing a second reset value to a specific VDP register RGij (system command register) (fourth reset path 4B). Although not used in this embodiment, the audio circuit SND can be reset not only by the fourth reset path 4B, but also by writing a reset value to a specific VDP register (circuit setting command register) (fourth reset path 4C).

Since this embodiment has the above configuration, not only does the entire VDP circuit 52 automatically return to its initial state when the power is turned on or the program crashes, but each part can also be returned to its initial state as necessary to recover from an abnormal situation. For example, when the drawing circuit 76 freezes after there is no READ/WRITE access to the built-in VRAM 71 for a certain period of time, the drawing circuit 76 is initialized individually via the fourth reset path 4B (see ST16a in FIG. 20(d)). The same is true for the preloader 73 and data transfer circuit 72, and when a certain abnormality occurs, the preloader 73 is initialized via the fourth reset path 4B (see ST27 in FIG. 27), and the data transfer circuit 72 is initialized via the fourth reset path 4B (see ST27 in FIG. 22 and FIG. 27).

Furthermore, in the case where an underrun abnormality continues, in which the generation of display data does not keep up with the display timing every 1/60 seconds, the display circuit 74 is individually initialized via the fourth reset path 4A or the fourth reset path 4B (see ST10c in FIG. 20). Note that these individual reset operations will be described further below in relation to the program processing described in FIG. 20 and subsequent figures.

The above describes the reset mechanism characteristic of this embodiment. When any of the reset paths 1 to 4 function and the internal circuit of the composite chip 50 is reset, the setting value of the VDP register RGij corresponding to that internal circuit returns to the same default value as after power is turned on.

Next, we will return to the internal configuration of the CPU circuit 51 and continue explaining the characteristic circuit configuration. Figure 8 is a block diagram showing the internal configuration of the CPU circuit 51 in some detail. The CPU circuit 51 is configured to include many characteristic circuits in addition to the internal RAM 59, DMAC circuit 60, SIO 61, PIO 62, and WDT described above.

Firstly, the CPU circuit 51 has a separate CPU fetch bus for instructions and a CPU memory access bus for data, realizing a Harvard architecture. Therefore, there is no contention between the fetch operation by the CPU core (performance control CPU) 63 to read instructions from memory and the memory access operation, and high-speed processing is achieved by making the fetch operation continuous.

The CPU core 63 is also configured with multiple (e.g., 15) register banks RB0 to RB14, and is configured to allow the selection of whether to use them or not. In an operating state in which the use of register bank RBi is permitted, the register values (each 32 bits long) of the CPU's built-in registers (e.g., 19 registers) are automatically saved to an empty register bank RBi when interrupt processing begins.

In addition, when a specified restore command is executed at the end of interrupt processing, for example, 19 pieces of saved data are automatically restored to the corresponding built-in registers. This eliminates the need to execute the PUSH command 19 times at the start of interrupt processing and the POP command 19 times at the end of interrupt processing, as in the normal configuration, and achieves high-speed processing.

The CPU circuit 51 of the embodiment also provides an instruction cache memory 67, an operand cache memory 89, and a cache controller 69 to realize Harvard cache operation, and when accessing the same address, cached data is utilized to further speed up program processing. The bus bridge 65, a controller for peripheral bus (1), a controller for peripheral bus (2), and a controller for peripheral bus (3) are provided to appropriately connect the internal bus to peripheral bus (1), peripheral bus (2), and peripheral bus (3).

Next, in the circuit configuration of FIG. 8, the bus state controller 66 is a part that operates based on appropriate settings in the operation control register REG to optimize memory READ and memory WRITE operations with various memory devices connected to the CPU circuit 51. The memory READ and memory WRITE operations are executed, for example, at the operation timing illustrated in FIG. 38, but the operation timing of the address data output from the address bus (28 bits), the READ data read to the READ data bus (32 bits), the WRITE data written to the WRITE data bus (32 bits), and control signals such as the chip select signals CS0 to CS7 are appropriately specified according to the characteristics of each memory device based on the settings in the operation control register REG.

The separate READ and WRITE data buses allow for high-speed operation using the Harvard architecture described above. In this specification, the address bus (28 bits), READ data bus (32 bits), and WRITE data bus (32 bits) are sometimes collectively referred to as external buses to distinguish them from the internal bus shown in Figure 8 and peripheral buses (1) to (3).

Figure 9 illustrates the address spaces CS0 to CS7 selected by the chip select signals CS0 to CS7, and illustrates the address map for the performance control CPU 63 accessed via the bus state controller 66. First, each address space CS0 to CS7 is defined as a maximum of 64 MB (= 0x4000000H = 67108864).

As explained above, the address spaces CS0 to CS7 refer to external memories for the CPU circuit 51, which can specify the memory type (including whether it is volatile or not) and the data bus width (8/16/32 bits). In this embodiment, as shown in Figures 8(b) and 9, the control memory (PROM) 53 is located in address space CS0, the audio control register SRG of the audio processor 27 is located in address space CS3, the internal register of the clock circuit 38 and the SRAM 39 are located in address space CS4, the external DRAM (DDR) 54 is located in address space CS5, the work memory 57 is located in address space CS6, and the VDP register RGij is located in address space CS7. Note that the description of address spaces CS1 and CS2 will be omitted.

As can be seen from Figure 9, the address space CS0 to CS7 is reserved not only for address values 0x00000000 to 0x1FFFFFFF (cache-enabled space), but also for address values 0x20000000 to 0x3FFFFFFF (cache-disabled space). This allows the use of the cache function to be selected at will, by disabling the cache based on the internal operation of the CPU circuit 51 when address bit A29 = 1, and enabling the cache when address bit A29 = 0.

Therefore, in this embodiment, out of the total 32-bit address information (bits A31 to A0), even if the value of bit A29 is either 1 or 0, if the values of the remaining 31 bits (bits A31 to A30 and bits A28 to A0) are the same, it will point to the same address in the same memory. For example, whether address 0x18000000 is accessed for READ or address 0x38000000 is accessed for READ, the same data will be read from address zero of work memory 57. Note that when address 0x18000000 is accessed for READ, the read data is stored in the cache, and Figure 8(b) illustrates the access operation with the cache enabled/disabled.

However, it is also possible to disable cache operation for the instruction cache and/or operand cache based on the setting value of a specified operation control register REG. However, in this embodiment, after power is turned on, cache operation is enabled for the instruction cache and operand cache, and cache operation is disabled by accessing the cache-disabled space as necessary.

Continuing with the explanation of the memory map in Figure 9, addresses 0x40000000 and onwards are internal memory space in which the bus state controller 66 does not function, and addresses 0xF0000000 to 0xFF3FFFFF are allocated to the cache address array space. Additionally, addresses 0xFF400000 to 0xFFF7FFFF and 0xFFFC0000 to 0xFFFFFFFF are allocated to built-in peripheral modules, specifically to the operation control register REG of the CPU circuit. The address range of the built-in RAM 59 is 0xFFF80000 to 0xFFFBFFFF.

Continuing with the explanation of the internal configuration of the CPU circuit 51, the compare match timer CMT and the multifunction timer unit MTU are circuits that count external signals supplied to the CPU circuit 51, or count a counting clock that is a multiplied or divided internal clock, and generate an interrupt signal or the like when the count result reaches a predetermined value. Although not limited to this, in this embodiment, the multifunction timer unit MTU is used to generate a 1 ms interrupt signal and a 20 μS interrupt signal.

Next, the interrupt controller INTC is a circuit that receives internal interrupts from the VDP circuit 52, DMAC circuit 60, multifunction timer unit MTU, etc., and external interrupts such as IRQ_CMD, IRQ_SND, and IRQ_RCT, and starts the interrupt process (interrupt handler) based on a predefined priority order. Here, IRQ_CMD is a command reception interrupt signal that should receive the control command CMD, IRQ_SND is an end interrupt signal that indicates that the audio processor 27 has completed the initialization sequence, and IRQ_RCT is an alarm interrupt signal.

In this embodiment, the command reception interrupt IRQ_CMD has the highest interrupt priority, followed by the 20 μS interrupt → 1 ms interrupt → interrupts from the VDP circuit (IRQ0, IRQ1, IRQ2, IRQ3) → DMAC interrupt → IRQ_SND → IRQ_RCT (see FIG. 17(d)). Note that all of these are maskable interrupts, and the non-maskable interrupt NMI is output to the performance control CPU 63 when the reference clock is not being output from the oscillator OSC2, as explained above.

In any interrupt processing, the register values (each 32 bits long) of the CPU's multiple built-in registers are automatically saved to one of the free register banks RBi. Then, when a specified restore command is executed at the end of the interrupt processing, the saved data is automatically restored to the corresponding built-in register.

Next, the DMAC circuit 60 will be described. The DMAC circuit 60 of the embodiment is a circuit that repeats data transfers from the source (Source) to the destination (Destination) in a specified DMA transfer mode for each specified data transfer unit a specified number of times based on the setting value of a specified operation control register REG. Note that multiple channels DMAC0 to DMACn with the same internal configuration are provided, and can operate in parallel. However, a priority is set (channel 0>...>channel n), and during parallel operation in the channel arbitration operation mode, the operation of the DMACi with the higher priority is prioritized by channel arbitration at a specified timing.

In one embodiment where the DMAC circuit 60 is used, for example, in which the serial output port SO functions (see the dashed line in Figure 9(a)), the operation control register REG of the CPU circuit 51 is specified with the top address of the lamp/motor drive table (top value of the source address), the address of the input register of the serial output port SO (fixed value of the destination address), the data transfer unit (8 bits), and the number of transfers. Then, when a specific operation control register REG receives an instruction to start operation, the DMAC circuit 60 DMA transfers the drive data to the specific destination address while updating the source address. Then, when all DMA transfers have been completed, a DMAC interrupt (operation end interrupt) is generated.

This is almost the same in the embodiment (Fig. 23, Fig. 27(c)) in which the DMAC circuit 60 issues the display list DL. That is, the performance control CPU 63 sets the start address of the transfer source (DL buffer BUF), the address of the transfer destination (transfer port TR_PORT), the DMA transfer mode, the data transfer unit, the number of transfers, and other conditions in a specified operation control register REG of the CPU circuit 51. These points will be discussed further below in relation to Fig. 23.

Generally, DMA transfer modes include cycle steal transfer mode, in which the DMA operation does not occupy the memory bus, for example by releasing bus control during a unit operation (R operation/W operation) of the DMA transfer; burst transfer (pipeline transfer) mode, in which the bus control is not released until a specified number of transfers are completed, for example by performing multiple R operations or W operations in succession; and demand transfer mode, in which the DMA operation continues while a DMA transfer request (demand) from another device is active. However, the DMAC circuit 60 of this embodiment functions in cycle steal transfer mode, which provides at least one cycle of memory release period between read access activation (R operation) and write access activation (W operation) during DMA transfer, to prevent any disruption to the operation of the performance control CPU 63.

Figure 10 is a diagram explaining cycle steal transfer operation (a1) and pipeline transfer (a2). As shown in Figure 10 (a1), the DMAC circuit 60 functioning in cycle steal transfer mode operates with at least one cycle between the read access activation (R) and write access activation (W) of one data transfer, and during this free cycle, the performance control CPU 63 can use the bus. As is clear from the comparison between Figure 10 (a1) and Figure 10 (a2), in pipeline transfer, the bus is not released to the CPU until one cycle (one operand transfer) is completed, whereas in cycle steal transfer mode, the bus is released to the CPU for each read access, so the operation of the CPU is not significantly delayed.

For example, in an embodiment using the DMAC circuit 60 when issuing a display list DL to the VDP circuit 52, the data transfer unit (one operand) for one cycle is set to 32 x 2 bits, and the source address of the internal RAM 59 in which the display list DL is stored is appropriately increased (+8 for each operand transfer), while a DMA transfer operation is performed for the transfer port register TR_PORT (see FIG. 12) of the data transfer circuit 72 specified by a fixed address.

As will be described later, in the embodiment, the total data size is adjusted to a fixed value (for example, 4 x 64 = 256 bytes, or an integer multiple thereof) by adding the required number of NOP (no operation) commands to the display list DL, and the issuance of the display list DL is completed by repeating one operand transfer of 32 bits x 2 times 32 times (or an integer multiple thereof). Note that even if the drawing circuit 76 executes a NOP command, no change actually occurs.

Furthermore, when classifying operating modes with respect to DMA transfer conditions, generally, there are single operand transfer (see FIG. 10(b1)), consecutive operand transfer (see FIG. 10(b2)), and non-stop transfer (see FIG. 10(b3)).

Here, single operand transfer means an operation mode in which, as shown in FIG. 10(b1), the transfer of one operand is repeated each time a DMA transfer request is given, and a DMA interrupt request occurs when the byte count, which counts the number of transferred bytes, reaches zero. Next, continuous operand transfer means an operation mode in which, as shown in FIG. 10(b2), DMA transfer is repeated with one DMA request until the byte count reaches zero.

In these continuous operand transfers (b2) and single operand transfers (b1), channel arbitration is performed each time one operand transfer is completed, and the current channel transfer continues on the condition that there is no DMA request for a channel with a higher priority (channel arbitration operation mode). Therefore, in this embodiment, the single operand transfer method is used for issuing the display list DL to the VDP circuit and for DMA transfer of lamp drive data and motor drive data. During parallel operation, the DMACi of the optimal channel is used so that channel arbitration is performed with the priority of motor data > display list DL > lamp data, for example.

On the other hand, non-stop transfer is an operating mode in which channel arbitration is not performed, and as shown in FIG. 10 (b3), DMA transfer is repeated continuously until the byte count reaches zero in response to a single DMA request. In this embodiment, in the memory section initialization process at power-on (SP8 in FIG. 15), programs and data are DMA transferred using non-stop transfer.

Having explained the CPU circuit 51 above, we will now explain the VDP circuit 52. Connected to the VDP circuit 52 are a CGROM 55 that stores compressed data that is a component of the still and moving images that make up the image presentation, an external DRAM (Dynamic Random Access Memory) 54 with a storage capacity of about 4 Gbit, a main display device DS1, and a sub-display device DS2. The DRAM 54 is preferably configured with a DDR3 (Double-Data-Rate3 SDRAM).

In this embodiment, the CGROM 55 is configured as a flash SSD (solid state drive) made up of a NAND type flash memory with a storage capacity of about 62 Gbits, and is configured to obtain the necessary compressed data by serial transmission. This eliminates the problem of skew (difference in transmission speed for each bit of data) that inevitably occurs in parallel transmission, enabling extremely high-speed transmission operations. In this embodiment, the CGROM 55 is accessed at high speed using a HSS (High Speed Serial) method that complies with Serial ATA, although this is not particularly limited.

Whether or not it uses the HSS method compliant with SerialATA, NAND-type flash memory is more mechanically stable than a hard disk and allows high-speed access, but since it is a sequential access memory, it has problems with random access compared to DRAM and SRAM (Static Random Access Memory). Therefore, in this embodiment, a preload operation is performed in which a group of compressed data (CG data) is read into DRAM 54 prior to the drawing operation, thereby realizing smooth random access of CG data during drawing operations. Incidentally, the access speed is slower in the following order: built-in VRAM > external DRAM > CG ROM.

In detail, the VDP circuit 52 comprises a control register group 70 in which various operating parameters that define the operation of the VDP (Video Display Processor) can be set by the performance control CPU 63, an internal VRAM (video RAM) 71 of about 48 MB that is used when generating image data to be displayed on the display devices DS1 and DS2, a data transfer circuit 72 that transmits and receives data between each section within the chip and with the outside of the chip, and a source and destination bus for the internal VRAM 71. a preloader 73 capable of executing a preload operation for accessing the CGROM 55 for reading prior to a drawing operation; a graphics decoder (GDEC) 75 for decoding (decoding and expanding/expanding) compressed data read from the CGROM 55; a drawing circuit 76 for generating image data for one frame of each of the display devices DS1 and DS2 by appropriately combining still image data and moving image data after decoding (expanding); a geometry engine 77 for generating a three-dimensional image by appropriate coordinate conversion as part of the operation of the drawing circuit 76; The display circuit 74A-74C has three systems (A/B/C) capable of executing appropriate image processing in parallel, an output selection unit 79 that appropriately selects and outputs the output of the display circuit 74 of the three systems (A/B/C), an LVDS unit 80 that converts the image data output by the output selection unit 79 into an LVDS signal, an SMC unit 78 that can transmit and receive serial data, a CPUIF unit 81 that relays data transmission and reception with the CPUIF circuit 56, a CG bus IF unit 82 that relays data reception from the CGROM 55, a DRAMIF unit 83 that relays data transmission and reception with the external DRAM 54, and a VRAMIF unit 84 that relays data transmission and reception with the built-in VRAM 71 (see FIG. 7(a)). An audio circuit SND is also built in.

Figure 7 (b) illustrates the relationship between the CPUIF unit 81, CG bus IF unit 82, DRAMIF unit 83, and VRAMIF unit 84 and the control register group 70, CGROM 55, DRAM 54, and built-in VRAM 71. As shown in the figure, the CG data acquired from the CGROM 55 is transferred, for example, as preload data, via the data transfer circuit 72 and the DRAMIF unit 83 to the preload area of the external DRAM 54.

However, the above-mentioned preload operation is not a required operation, and the data transfer destination is not limited to the external DRAM 54, but may be the built-in VRAM 71. Therefore, for example, in an embodiment in which the preload operation is not performed, the CG data is transferred to the built-in VRAM 71 via the data transfer circuit 72 and the VRAM IF unit 84 (FIG. 7(b)).

In this embodiment, the built-in VRAM 71 requires a decompression area for the compressed data read from the CGROM 55, a frame buffer area for storing image data specifying the ARGB information (32 bits = 8 x 4) for each of the W x H display pixels of the display device, and a Z buffer area for storing depth information for each display pixel. In the ARGB information, A means 8-bit alpha plane data, and RGB means 8-bit data for the three primary colors.

The above-mentioned areas of the built-in VRAM 71 are indirectly accessed by the performance control CPU 63 based on various instruction commands (such as the textures and sprites mentioned above) written in the display list DL, but it would be cumbersome to specify the destination address and source address of the built-in VRAM 71 for each READ/WRITE access. Therefore, in this embodiment, in the initial processing after the CPU is reset, a one-dimensional or two-dimensional logical address space (hereinafter referred to as index space) required for drawing operations is secured, and an index number is assigned to each index space, making it possible to access based on the index number.

Specifically, after the CPU is reset, the built-in VRAM 71 is roughly divided into three types of memory areas, and the required number of index spaces are secured in each memory area. Then, an index table IDXTBL (see FIG. 11(a)) is constructed that associates and stores the index spaces with index numbers, thereby enabling subsequent operations based on the index numbers.

This index space needs to be added after (1) initial processing, or conversely, to be released (2). Therefore, a flag area FG is provided in the index table IDXTBL, which can determine whether the timing for adding/opening processing is possible or not, and whether the processing such as adding/opening has actually been completed or not, during the operation of the performance control CPU 63 for adding/opening. The built-in VRAM 71 is roughly divided into three types of memory areas, namely, two AAC areas (a1, a2), a page area (b), and an arbitrary area (c), which will be described below, and the index table IDXTBL is divided into three areas corresponding to the three types of memory areas (a1, a2) (b) and (c) (FIG. 11(a)). As shown in the figure, in this embodiment, the first AAC area (a1) and the second AAC area (a2) are secured as the AAC area (a), but this is not particularly limited, and only one of them may be used. In the following description, the first and second AAC regions (a1, a2) may be collectively referred to as AAC region (a).

In this embodiment, the built-in VRAM 71 is configured to be divisible into (a) an AAC area in which the index space and its index number are automatically assigned by internal processing and which has a memory cache function, (b) a page area in which the index space can be secured within an integer multiple of a two-dimensional space of, for example, 4096 bits x 128 lines, and (c) an arbitrary area in which the start address (space start address) STx and horizontal size Hx can be set arbitrarily (see FIG. 11(b)). However, in order to facilitate the internal operation of the VDP circuit 52, the space start address STx of the index space arbitrarily set in the arbitrary area (c) must have the lowest 11 bits 0 and be in units of a predetermined number of bits (2048 bits = 256 bytes).

After the CPU is reset, the maximum address space required for each area and the area start address (lowest 11 bits = 0) are specified, and the AAC area (a1), second AAC area (a2), and page area (b) are secured, and the remaining memory area becomes the arbitrary area (c). To facilitate the internal operation of the VDP circuit 52, the maximum address space of the AAC area is specified in units of 2048 bits, and the maximum address space of the page area is an integer multiple of the unit space of 4096 bits x 128 lines described above.

Next, the required number of index spaces are set in each of the areas (a1, a2), (b), and (c) thus secured. When using the arbitrary area (c), in order to facilitate the internal operation of the VDP circuit 52, the horizontal size Hx of the index space that handles two-dimensional data can be arbitrarily set as a multiple of 256 bits, while its vertical size is a fixed value (for example, 2048 lines).

In any case, the first and second AAC areas (a1, a2) are automatically assigned index spaces and index numbers by the VDP circuit 52. For example, if the decoding destination is specified as AAC area (a) by the SETINDEX command, which is a texture setting command, then the TXLOAD (texture load) command that reads CG data from CGROM 55 only needs to specify the source address of CGROM 55 and the horizontal and vertical size after expansion (decoding). Therefore, in this embodiment, the decoding destination for still images (textures) such as characters that appear temporarily during preview performances, and I-stream video, is set to AAC area (a).

Since each of these AAC areas (a) has a memory cache function, for example, if the same texture from CGROM 55 is read into AAC area (a) multiple times, the decoded data cached in AAC area (a) can be used from the second time onwards, making it possible to suppress unnecessary read accesses and decode processes. However, since old data is automatically destroyed when AAC area (a) is used up, in this embodiment, when using AAC area (a), the first AAC area (a1) is used as a general rule, and only specific textures that are used repeatedly are acquired in the second AAC area (a2).

Examples of textures that are used repeatedly include characters that appear repeatedly during a specified preview performance, and background images when the background screen is constructed with still images. In such cases, the SETINDEX command, which is a texture setting command, sets the decoding destination to the second AAC area (a2), and after the TXLOAD command decodes the texture of the characters, background images, etc. into the second AAC area (a2), the second AAC area (a2) is not used to protect the decoded results.

Then, after that, if the SETINDEX command is used to specify the second AAC area (a2) as the decoding destination and the same TXLOAD command is executed to reacquire the acquired texture, the acquired texture will be a cache hit, so it is possible to eliminate the need for a READ access to the CGROM 55 and the time required for the decoding process. As will be described later, this cache hit function is also exhibited by preload data pre-read into the preload area, but what is significant is that the preload data that hits the cache in the preload area is compressed data before decoding, whereas the data that hits the cache in the AAC area is expanded data after decoding.

The term "texture" generally refers to the feel and texture of an object's surface, but in this specification it is used to include not only sprite image data that makes up a still image, image data that makes up one frame of a video, and image data pasted onto drawing primitives such as triangles and rectangles, but also image data after decoding. When copying image data within the built-in VRAM 71 (hereafter referred to as moving for convenience), the source image data is set as texture using the SETINDEX texture setting command, and then the SPRITE command is executed.

When the SPRITE command is executed, the source Source image data is technically drawn in the virtual drawing space shown in Figure 11 (c); however, if the correspondence between the drawing area in the virtual drawing space that is actually drawn on the display device and the index space that serves as the frame buffer has been set in advance using environment setting commands (SETDAVR, SETDAVF) or texture setting commands (SETINDEX), then, for example, drawing in the virtual drawing space using the SPRITE command will result in the source Source image data being drawn in a specified index space (frame buffer) (see Figure 11 (c)).

In any case, in this embodiment, the built-in VRAM 71 is roughly divided into an AAC area (a1, a2), a page area (b), and an arbitrary area (c), and an appropriate number of index spaces can be secured for each area, and each index space is identified by an independent index number for each area (a), (b), and (c). The index number is, for example, 1 byte long, and for the page area (b) and arbitrary area (c) (excluding the AAC area (a) which is automatically assigned by the internal circuitry), the performance control CPU 63 can freely assign index numbers in the range of 0 to 255.

In this embodiment, as shown in FIG. 11(a), a pair of frame buffers FBa are reserved in the arbitrary area (c) for the display device DS1, and index numbers 255 and 254 are assigned to both of the double buffer structure. That is, index space 255 and index space 254 are reserved as frame buffer FBa for the main display device DS1, which are switched in a toggle manner. Although not limited to this, these index spaces 255 and 254 have a horizontal size of 1280, corresponding to the number of horizontal pixels of the display device DS1. Note that each pixel is specified by 32 bits of ARGB information, so the horizontal size 1280 means 32 x 1280 = 40960 bits (a multiple of 256 bits).

In addition, another pair of frame buffers FBb are reserved in the arbitrary area (c) for the display device DS2, and index numbers 252, 251 are assigned to both sides of the double buffer structure. That is, index space 252 and index space 251 are reserved as frame buffer FBb for the sub-display device DS2. These index spaces 252, 251 have a horizontal size of 480, corresponding to the number of horizontal pixels of the display device DS2. In this case, each pixel is specified by 32 bits of ARGB information, so the horizontal size of 480 means 32 x 480 = 15,360 bits (a multiple of 256 bits).

The reason why frame buffers FBa and FBb are reserved in arbitrary area (c) is that arbitrary area (c) can be set to any horizontal size as a multiple of 32 bytes (= 256 bits = 8 pixels), and as mentioned above, if it is set to match the number of horizontal pixels of display devices DS1 and DS2, no waste will occur in the reserved area. On the other hand, page area (b) can only be set to horizontal/vertical sizes that are integer multiples of the unit space of 128 pixels x 128 lines.

However, the two-dimensional index space secured in the arbitrary area (c) has a fixed vertical size (e.g., 2048 lines). Therefore, in the frame buffer FBa, only an area of horizontal size 1280 x vertical size 1024 becomes the valid data area for the main display device DS1. The same is true for the sub-display device DS2, and in the frame buffer FBb, only an area of horizontal size 480 x vertical size 800 becomes the valid data area for the sub-display device DS2 (see Figures 11(c) and 20(e)).

The above points will be discussed further below, but in any case, the frame buffers FBa and FBb are used alternately as the drawing area for the drawing circuit 76, with each double buffer (255/254, 252/251), and are used alternately as the display area for the display circuits 74A and 74B, with each double buffer (255/254, 252/251). In this embodiment, a missing number (253) occurs because a Z buffer that stores depth information of the display pixels is not used, but if a Z buffer is used, the index spaces 253 and 250 of index numbers 253 and 250 in the arbitrary area (c) become the Z buffers for the display devices DS1 and DS2.

In addition, in this embodiment, when an additional index space (memory area) is reserved in the arbitrary area (c) where frame buffers FBa and FBb are reserved, an index number starting from 0 is assigned. Although not limited in any way, in this embodiment, index space (0) is reserved in the arbitrary area (c) as a working area for preview effects in which performance images composed of characters and other still images are made to appear in a part of the display screen in an appropriate rotational position as necessary.

However, the use of a work area is not essential, and index space may be reserved as a work area in the page area (b) instead of the arbitrary area (c). If the page area (b) is used, an index space with dimensions that are a multiple of a square unit space of horizontal size 128 (= 4096 bits) x vertical size 128 can be reserved, making it ideal for handling small-sized performance images.

In this embodiment, the background images are also composed of moving images, and the image presentation is realized almost entirely with moving images. In particular, during a moving presentation, a large number of moving images (usually 10 or more) are simultaneously drawn. All of these moving images are stored in the CGROM 55 in a compressed state as a series of moving image frames, but are classified as I-stream moving images consisting of I-frames only, and IP-stream moving images consisting of I-frames and P-frames. Here, an I-frame (Intra coded frame) refers to a frame in which the input image is compressed as is, independent of other screens. On the other hand, a P-frame (Predictive coded frame) refers to a frame that performs forward predictive coding, and requires an I-frame or P-frame located in the past in time.

Therefore, in this embodiment, IP stream video is expanded in the page area (b) rather than in the AAC area (a) where there is a concern that old data may be destroyed. That is, a number of index spaces ( _IDX0 to _IDXN ) are secured in the page area (b) where an index space of a multiple of horizontal size 128 x vertical size 128 can be secured, and a series of video frames are decoded using the same index space IDXi corresponding to each video MVi at all times. That is, video MV1 is expanded in the index space IDX1, video MV2 is expanded in the index space IDX2, and so on.

To explain the video MVi more specifically, the SETINDEX command specifies in advance that the decode destination of the IP stream video MVi is the index space (i) of index number i in the page area (b), and then the TXLOAD command is executed to obtain one video frame of the IP stream video MVi.

Then, one frame of video (any of a series of video frames) on CGROM 55 specified by the TXLOAD command is first retrieved into the AAC area (a), and then the GDEC (graphics decoder) 75, which starts automatically, decodes and expands the retrieved one frame of video into the index space (i) of the page area (b).

On the other hand, in this embodiment, I stream video is treated the same as still images, and the SETINDEX command is used to specify that "the decoded destination of I stream video MVj is the first AAC area (a1)", and the TXLOAD command is executed. As a result, video frames are acquired in the first AAC area (a1), and then the GDEC 75, which starts automatically, expands the decoded data in the first ACC area (a1). As explained above, the index space for the AAC area (a) is automatically generated, so there is no need to specify an index number. The expansion volume required for the index space, that is, the horizontal and vertical sizes of the decoded texture (video frame), are specified by the TXLOAD command, regardless of whether the expansion destination is the AAC area (a) or the page area (b).

Meanwhile, IP stream video MVi and I stream video MVj are generally composed of N video frames (I frames and P frames). Therefore, the TXLOAD command specifies, for example, the source address of the CGROM 55 where the kth (1≦k≦N) video frame is stored, and the horizontal and vertical size after expansion. Although not limited in any way, in an embodiment where still images are hardly used, most of the 48 MB address space of the built-in VRAM 71 (about 30 MB) is assigned to the page area (b). And, in an embodiment where still images are hardly used, only the first AAC area (a1) is reserved as the AAC area, and the second AAC area (a2) is not reserved, and the cache hit function of the AAC area described above is not utilized.

In order to speed up the decoding process of compressed video data, it is also possible to provide a dedicated GDEC (graphics decoder) circuit. If a dedicated GDEC circuit is built into the VDP circuit 52, it will be sufficient to specify the start address of the video compression data to the GDEC circuit in the decoding process of compressed video data consisting of N compressed video frames, so there will be no need to specify the start address for each of the N compressed video frames.

However, if multiple dedicated GDEC circuits like this are built in for each compression algorithm, the internal configuration of the VDP circuit 52 becomes even more complicated. Therefore, in this embodiment, a software GDEC is used, and decoding is achieved for data such as IP stream video, I stream video, still images, and other alpha values through software processing corresponding to each compression algorithm. Note that the difference in processing time between hardware processing and software processing is not much of a problem; it is the access (READ) time from the CGROM 55 that is an issue in terms of processing time.

Returning to FIG. 7(a), the data transfer circuit 72 is a circuit that performs data transfer operations between a resource (storage medium) inside the VDP circuit and an external storage medium as a source port and a destination port in a DMA (Direct Memory Access) manner. FIG. 12 is a block diagram showing the internal configuration of the data transfer circuit 72 together with the related circuit configuration.

As shown in FIG. 12, the data transfer circuit 72 is configured to transmit and receive data to and from the CGROM 55, DRAM 54, and built-in VRAM 71 via an integrated connection bus ICM with a router function. The CGROM 55 and DRAM 54 are accessed via the CG bus IF unit 82 and the DMAMIF unit 83.

Meanwhile, the CPU circuit 51 issues a display list DL to the drawing circuit 76 and preloader 73 via the transfer port register TR_PORT built into the data transfer circuit 72. The CPU circuit 51 and the data transfer circuit 72 are connected bidirectionally, and when a display list DL is issued, the transfer port register TR_PORT functions as a data write port that accepts one unit of data that constitutes the display list DL. The write unit (one unit data length) of the transfer port register TR_PORT is 32 bits, corresponding to the FIFO structure of the CPU bus control unit 72d.

As shown in the figure, the performance control CPU 63 can access the transfer port register TR_PORT for WRITE via the CPUIF unit 81, but when the DMAC circuit 60 is used, the DMAC circuit 60 directly accesses the transfer port register TR_PORT for WRITE. The series of instruction commands written to the transfer port register TR_PORT (i.e., the sequence of instruction commands that make up the display list DL) are automatically stored in 32-bit units in the CPU bus control unit 72d, which has a built-in FIFO buffer with a FIFO structure (32 bits x 130 stages).

The data transfer circuit 72 also performs data transmission and reception operations on the transmission paths of three channels ChA to ChC, and has a ChA control circuit 72a (N=130 stages) with a FIFO buffer of a FIFO structure (64 bits x N stages), a ChB control circuit 72b (N=1026 stages), and a ChC control circuit 72c (N=130 stages).

Then, the instruction command sequence (display list DL) stored in the CPU bus control unit 72d is transferred to the drawing circuit 76 or the preloader 73 based on the setting value of the data transfer register RGij (one type of various control registers 70) by the performance control CPU 63. As shown by the arrows, the display list DL is configured to be transferred from the CPU bus control unit 72d to the drawing circuit 76 via the FIFO buffer of the ChB control circuit 72b, and then to the preloader 73 via the FIFO buffer of the ChC control circuit 72c.

In this embodiment, the ChB control circuit 72b and the ChC control circuit 72b are specialized for the transfer operation of the display list DL, and the data stored in the FIFO buffer of the CPU bus control unit 72d is transferred as part of the display list DL to the drawing circuit 76 or the display list analyzer of the preloader 73 via the FIFO buffer of the ChB control circuit 72b or the ChC control circuit 72c, respectively.

Then, the drawing circuit 76 starts drawing operations based on the transferred display list DL. Meanwhile, the preloader 73 executes the necessary preload operations based on the transferred display list DL. The preload operation causes the CG data in the CGROM 55 to be pre-read into a preload area secured in the DRAM 54, and the display list DL with the texture source address changed for the TXLOAD command or the like (hereinafter referred to as the rewrite list DL') is saved in the DL buffer area BUF' secured in the DRAM 54.

On the other hand, the ChA control circuit 72a and the connection bus access arbitration circuit 72e function to transfer data between storage media such as the CGROM 55, the DRAM 54, and the built-in VRAM 71. The IDXTBL access arbitration circuit 72f functions when accessing the built-in VRAM 71, which requires address information from the index table IDXTBL. Specifically, the ChA control circuit 72a functions, for example, when (a) compressed data from the CGROM 55 is transferred to the built-in VRAM 71, (b) compressed data from the CGROM 55 is preloaded (read ahead) and transferred to the external DRAM 54, or (c) read-ahead data from the preload area is transferred to the built-in VRAM 71.

The ChA control circuit 72a is configured to be able to operate in parallel with the ChB control circuit 72b and the ChC control circuit 72c, and the above operations (a) to (c) can be executed in parallel with the issuance operation of the display list DL (ST8 in FIG. 20, PT11 in FIG. 25) and the transfer operation of the rewrite list DL' (PT10 in FIG. 25). The ChB control circuit 72b and the ChC control circuit 72c can also be executed simultaneously. For example, the process of step PT10 in FIG. 25 in which the ChB control circuit 72b functions and the process of step PT11 in which the ChC control circuit 72c functions can be executed in parallel. However, since there is only one transfer port register TR_PORT, when one of them (72b/72c) is using the transfer port register TR_PORT, the other (72c/72b) cannot access the transfer port register TR_PORT.

When the ChA control circuit 72a is in operation, the connection bus access arbitration circuit 72e arbitrates data transmission with each memory element (CGROM 55, DRAM 54) via the integrated connection bus ICM. On the other hand, the IDXTBL access arbitration circuit 72f arbitrates data communication with the built-in VRAM 71 by controlling the ChA control circuit 72a based on the index table IDXTBL. In the embodiment in which the preloader 73 is functioning, the rewrite list DL' stored in the DL buffer area BUF' of the DRAM 54 is transferred to the drawing circuit 76 via the connection bus access arbitration circuit 72e and the ChB control circuit 72b (see FIG. 26(b)).

As described above, the data transfer circuit 72 of this embodiment realizes high-speed data transfer between a data source arbitrarily selected from various storage resources (Resources) and a data destination arbitrarily selected from various storage resources (Resources). As can be seen from FIG. 12, the storage resources on which the data transfer circuit 72 functions include not only the built-in VRAM 71, but also external devices via the CPUIF unit 56, CG bus IF unit 82, and DRAMIF unit 83.

The amount of data transferred between the external device and the ChA control circuit 72a is huge compared to the amount of data transferred between the ChB control circuit 72b and the ChC control circuit 72c, such as the amount of data to be acquired from the CGROM 55 at one time (memory sequential READ), and the amounts of data transferred are significantly different.

It is conceivable to configure these various types of data transfer so that the unit data amount and total data transfer amount can be set in detail, but this would complicate the control operations within the VDP and hinder smooth transfer operations. Therefore, in this embodiment, a minimum data amount Dmin for data transfer is uniquely defined, and the total data transfer amount is limited to an integer multiple of the minimum data amount DTmin, thereby achieving high-speed, smooth data transfer operations. Although not particularly limited, in the data transfer circuit 72 of the embodiment, the minimum data amount Dmin (unit data amount) is set to 256 bytes, and the total data transfer amount is limited to an integer multiple of this amount.

Therefore, the display list DL instruction command sequence stored in the FIFO buffer of the CPU bus control unit 72d for each 32 bits is transferred to the ChB control circuit 72b and the ChC control circuit 72b when the total amount reaches the minimum data amount Dmin, and is stored in each FIFO buffer.

The display list DL is composed of a series of instruction commands, but in this embodiment, in accordance with the write unit (32 bits) of the transfer port register TR_PORT, the display list DL is composed only of instruction commands whose command length is an integer multiple of 32 bits (N>0). Therefore, the drawing circuit 76 and preloader 73 that receive the instruction commands of the display list DL via the data transfer circuit 72 can quickly and smoothly start the command analysis process (DL analyze). Note that the command length of an integer multiple of 32 bits does not necessarily mean that all bits are significant, but also includes don't care bits, meaning that it is an integer multiple of 32 bits.

Next, the preloader 73 will be described. As briefly explained above, the preloader 73 is a circuit that interprets the display list DL transferred from the data transfer circuit 72 (ChC control circuit 72b) and transfers the CG data in the CGROM 55 referenced by the TXLOAD command to the preload area of the DRAM 54 in advance. The preloader 73 also stores a rewrite list DL' in which the reference destination of the CG data for this TXLOAD command is rewritten to the address after transfer in the DL buffer BUF' of the DRAM 54. The DL buffer BUF' and the preload area are reserved in advance during the initial processing after the CPU is reset (ST3 in FIG. 20).

Then, when the drawing operation of the drawing circuit 76 starts, the rewrite list DL' is transferred to the display list analyzer (DL Analyzer) of the drawing circuit 76 via the connection bus access arbitration circuit 72e of the data transfer circuit 72 and the ChB control circuit 72b. The drawing circuit 76 then executes the drawing operation based on the rewrite list DL'. Therefore, based on the TXLOAD command, etc., the CG data that should originally be obtained from the CGROM 55 is obtained from the preload area of the DRAM 54 as preload data that has been preloaded into the preload area. In this case, the preload data can be used repeatedly unless it is overwritten and erased, and preload data that hits the cache in the preload area is repeatedly reused.

In this embodiment, the preload area is set in the external DRAM 54, which has sufficient storage capacity, so the above-mentioned cache hit function works effectively. In addition, since the storage capacity of the external DRAM 54 is large, multiple preloading, for example, in which multiple frames of CG data are preloaded at once, is also possible. In other words, multiple preloading is realized by appropriately setting the operating period of the preloader 73, which is a series of preloading operations including the CG data prefetching operation, within the range of an integer multiple of the operating cycle δ of the VDP circuit 52 during intermittent operation.

However, for the sake of convenience, the following description will be given of an embodiment without multiple preloading, so the preloader 73 of the embodiment will complete the preloading operation for one frame during one operation period (δ). As will be described later with reference to FIG. 20, in this embodiment, the operation period δ during intermittent operation of the VDP circuit 52 is 1/30 seconds, which is twice the period of the vertical synchronization signal of the display device DS1.

Next, the drawing circuit 76 sequentially analyzes the instruction command sequence of the display list DL and the rewrite list DL' transferred via the data transfer circuit 72, and works with the graphics decoder 75 and the geometry engine 77 to draw one frame's worth of images for each display device DS1, DS2 in the frame buffer formed in the VRAM 71.

As described above, in an embodiment where the preloader 73 is activated, the CG data in the rewrite list DL' is referenced not to the CGROM 55 but to the preload area set in the DRAM 54. This allows for rapid sequential access to CG data that occurs while the drawing circuit 76 is drawing, and allows for fast-moving, high-resolution video to be drawn without any problems. In other words, according to this embodiment, complex and highly advanced image presentation can be achieved while utilizing an inexpensive SATA module as the CGROM 55.

However, regardless of whether the preloader 73 is enabled or disabled, even if data corruption occurs during the transfer of the display list DL or rewrite list DL', the drawing circuit 76 cannot detect this. In addition, the drawing circuit 76 may freeze due to noise or other factors, causing READ/WRITE access to the built-in VRAM 71 to stop abnormally. Therefore, in this embodiment, if the drawing circuit 76 detects an irrational instruction command (a bit sequence that cannot be analyzed) or if there is no READ/WRITE access to the built-in VRAM 71 for a certain period of time, a drawing abnormality interrupt is generated (drawing abnormality interrupt is enabled). This point will be described later with reference to FIG. 20(d).

Next, as explained with reference to FIG. 11, the frame buffer FB secured in the arbitrary area (c) of the VRAM 71 is a double buffer divided into a drawing area and a read area, and the two areas are used alternately. In this embodiment, since two display devices DS1 and DS2 are connected, two frame buffers FBa/FBb are secured as shown in FIG. 11. Therefore, the drawing circuit 76 draws one frame of image data in the drawing area (write area) of the frame buffer FBa for the display device DS1, and also draws one frame of image data in the drawing area (write area) of the frame buffer FBa for the display device DS2. When image data is written in the drawing area, the display circuit 74 reads out the image data from the other read area (display area) and outputs it to each display device DS1 and DS2.

The display circuit 74 is a circuit that reads image data from the frame buffers FBa and FBb, performs final image processing, and outputs the result (see FIG. 13(a)). The final image processing includes, for example, a scaling process using a scaler that enlarges or reduces the image, subtle color correction processing, and dithering processing that minimizes quantization errors in the entire image. The digital RGB signal (total of 24 bits) that has undergone these image processes is then normally output together with a horizontal synchronization signal HS and a vertical synchronization signal VS.

As shown in FIG. 13(a), in this embodiment, three display circuits A/B/C are provided that perform the above operations in parallel, and each display circuit 74A-74C reads image data from its corresponding frame buffer FBa/FBb/FBc and performs the above final image processing. However, since there are only two display devices in this embodiment, frame buffer FBc is not reserved and display circuit 74C does not function.

Now, looking at the specifications of the main display device DS1, the main display device DS1 needs to receive the odd pixels (ODD) and even pixels (EVEN) adjacent to the left and right in the receiver RV (RVa + RVb) through separate LVDS (Low Voltage Differential Signaling) transmission paths. In addition, the frequency of the operating clock CK of the main display device DS1 needs to be around 40 to 70 MHz (typical value 54 MHz), and the horizontal/vertical waiting times WTh/WTv need to be set so that (WTh + 640) x (WTv + 1024)/54 MHz ≒ 1/60 seconds. Furthermore, at the timing when image data (ODD/EVEN signal) is output to the main display device DS1, an active level data enable signal ENAB needs to be output.

Therefore, the display circuit 74A needs to output a signal that satisfies all of the above specifications. Figures 14(a) to 14(e) show various signals output from the display circuit 74A. First, the frequency of the dot clock (LVDS clock) DCK needs to be determined. In this embodiment, the main display device DS1 is operated by an operating clock CK with a typical value of 54 MHz, so the designed dot clock DCK (in the VDP circuit 52) is set to 108 MHz (= 54 x 2) accordingly.

This is because in a display panel LCD (1280 dots horizontally and 1024 lines vertically) (see Figure 14(f)), two adjacent pixels on the left and right are processed at once in synchronization with a 54 MHz operating clock CK, which is essentially equivalent to operating with a 108 MHz dot clock DCK.

The various operating parameters that define the operation of the display circuit 74A are determined based on a dot clock DCK with a frequency of 108 MHz. First, the horizontal and vertical waiting times WTh/WTv must be set so that (WT+640) x (WTv+1024)/54 MHz ≒ 1/60 seconds, but the operating parameters WTh and WTv for the display circuit 74A must satisfy (WT+1280) x (WTv+1024)/108 MHz ≒ 1/60 seconds.

Furthermore, the tolerance range of the display device DS1 specifications must be taken into consideration for the horizontal/vertical waiting times WTh/WTv. Therefore, in this embodiment, the horizontal waiting time WTh is counted using a 108 MHz dot clock DCK, and is set to 382 clocks, and the vertical waiting time WTv is set to 59 lines. Therefore, the time required to update one frame of image is (382 + 1280) x (59 + 1024) / 108 MHz = 16.666 mS, and the frame rate FR (Frame Rate) is 1/60 seconds.

This relationship defines the update period FR [seconds] of the display device DS1, and when using the frequency F _dot of the dot clock DCK described later, the number of horizontal synchronization cycles THc, and the number of vertical synchronization lines TVl, FR = THc x TVl/F _dot . If the update period FR is too long, there is a risk of abnormalities such as flickering, whereas if the update period FR is too short, the display device cannot perform normal update processing, so it should be defined in the range of 0.95/60 < FR [seconds] < 1.05/60.

Corresponding to this setting, the data valid signal ENAB is at L level during the waiting time WTh (=382/108 MHz) corresponding to 382 clocks in the image update operation of each line, and then becomes active level (H) during the active section (=1280/108 MHz) corresponding to 1280 clocks (FIG. 14(c)). As shown in FIG. 14(d) and FIG. 14(e), in the active section of the data valid signal ENAB, image data is output so that the image update operation is completed within a predetermined time (11.85 μS=1280/108 MHz) for the pixels of one line of 1280 dots. That is, 1280 pieces of pixel data (Pixel Data) are output in synchronization with 1280 dot clocks DCK. Since a full-color image with a gradation of 2 ⁸ × 2 ⁸ × 2 ⁸ is displayed on the display device DS1, the pixel data of one pixel is 3×8 bits long.

In this embodiment, the main display device DS1 outputs a vertical synchronizing signal VS and a horizontal synchronizing signal HS, although they are not required. The vertical synchronizing signal VS is output within the vertical waiting time WTv, and the horizontal synchronizing signal HS is output within the horizontal waiting time WTh. For ease of understanding, the operation cycles of each are shown in Fig. 14(a) and Fig. 14(b). Also, in Fig. 14(f), a circle is shown at the top left and bottom right vertices of a rectangular frame specified by TH x TV (= 1083 x 1662 clocks), and "Start of display operation" and "End of display operation" are written, but this circle signifies "V blank start" which specifies the operation cycle of the display circuit 74A which starts every 1/60 seconds. Since the 1083 x 1662 clocks which specify the display operation coincide with 1/60 seconds, the elapsed time from "Start of display operation" to "End of display operation" (operation cycle of the display circuit 74A) is 1/60 seconds. "V Blank Start" will be explained later with reference to Figure 20.

Returning to FIG. 13, the output selection unit 79 of the embodiment divides the output signal of the display circuit 74A into dual links that divide the 108 MHz dot clock DCK by two, and transmits them to the LVDS unit 80a and the LVDS unit 80b, respectively (see FIG. 13(a) and FIG. 5). Each LVDS unit 80a, 80b then converts the image data (a total of 24-bit digital RGB signal) into a first and second LVDS signal, adds a pair that transmits a clock signal (54 MHz = 108/2), and outputs a total of five pairs of differential signals LVDS1, LVDS2 via two paths to the main display device DS1 (see FIG. 13(a) and FIG. 4).

As explained above, in the main display device DS1, the ODD signal for one pixel and the EVEN signal for an adjacent pixel are processed at the same timing, so the actual frequency of the operating clock CK matches the 108 MHz dot clock DCK output by the display circuit 74A.

The above describes the display circuit 74A that generates the image to be transmitted to the main display device DS1, but the display circuit 74B generates image data to be transmitted to the sub-display device DS2. The digital RGB signal output by the display circuit 74B is supplied to the digital RGB section 80c via the output selection section 79, and is transmitted to the sub-display device DS2 together with the vertical synchronization signal VS and horizontal synchronization signal HS.

In addition to the synchronization signals VS and HS, the data valid signal ENAB is also transmitted via the digital RGB section 80c, but of course each of these signals is transmitted as a continuous signal, not as discrete values as in the case of an LVDS transmission line (see Figure 13(a)).

In this embodiment, each display circuit 74A-74B is provided with an underrun counter URCNTa-URCNTc that counts underrun abnormalities, which are when the generation of display data is delayed in time for the display timing (see FIG. 14). The counter values of these underrun counters URCNTa-URCNTc are configured to be automatically incremented for each VBLANK when an underrun abnormality occurs.

Next, the SMC section 78 (Serial Management Controller) is a composite controller incorporating an LED controller and a Motor controller. It outputs LED drive signals and motor drive signals in synchronization with a clock signal to an LED/Motor driver (a driver IC incorporating a shift register) mounted on an external board, while being configured to be able to output latch pulses at appropriate timing.

Regarding the internal circuitry and its operation of the VDP circuit 52 described above, the operation contents to be performed by the internal circuitry are specified by the operation parameters (setting values) set by the performance control CPU 63 in the control register group 70, and the execution state of the VDP circuit 52 can be determined by reading the operation status value of the control register group 70. The control register group 70 refers to a large number of VDP registers RGij mapped to an address space of about 1 MB (0 to FFFFFH) on the memory map of the performance control CPU 63, and the performance control CPU 63 executes the WRITE (setting) operation of the operation parameters and the READ operation of the operation status value via the CPUIF unit 81 (see FIG. 7(b)).

The control register group 70 (VDP register RGij) includes a "system control register" in which initial setting values related to system operations such as interrupt operations are written, an "index table register" that determines the AAC area (a) and page area (b) in the built-in VRAM and is used for constructing or changing the index table IDXTBL, a "data transfer register" in which setting values related to the data transfer process by the data transfer circuit 72 between the performance control CPU 63 and the internal circuitry of the VDP circuit 52 are written, a "GDEC register" that specifies the execution status of the graphics decoder 75, a "drawing register" in which instruction commands and setting values related to the drawing circuit 76 are written, a "preloader register" in which setting values related to the operation of the preloader 73 are written, a "display register" in which setting values related to the operation of the display circuit 74 are written, an "LED control register" in which setting values related to the LED controller (SMC unit 78) are written, a "motor control register" in which setting values related to the motor controller (SMC unit 78) are written, and an "audio control register SRG" in which setting values related to the audio circuit SND are written. However, in this embodiment, the audio circuit SND is not used.

In any case, in the following description, one or more registers RGij included in the control register group 70 may be referred to by the individual names described above, or may be referred to collectively as VDP registers RGij. In either case, the performance control CPU 63 controls the internal operation of the VDP circuit 52 by writing appropriate setting values to a specific VDP register RGij. Specifically, the performance control CPU 63 realizes a specific image performance based on a display list DL that is updated at appropriate time intervals and the setting values to a specific VDP register RGij. In this embodiment, the performance control CPU 63 is also responsible for lamp and motor performances, so the VDP register RGij also includes an LED control register and a motor control register.

Next, we will explain the unified control operation of image effects, sound effects, motor effects, and lamp effects that is realized by the composite chip 50 incorporating the above-mentioned CPU circuit 51 and VDP circuit 52.

In this embodiment, the operation of the composite chip 50 is started by a power-on reset operation (see FIG. 15(a)) caused by power-on or abnormal reset, and is configured to move through initial setting processing (SP1 to SP9) by the initial setting program (boot program) Pinit, and then to main control processing (SP10) by the performance control program Main and the interrupt processing program (vector handler) Vopt. With regard to the main control processing, the processing content of the introductory part is described in FIG. 17(a), and the processing content of the main part is described in FIG. 20(a). Note that the processing of step SP27 in FIG. 17 includes the processing of steps ST1 to ST3 in FIG. 20(a).

Based on the above, the power-on reset operation will be explained based on FIG. 15(a). When the system reset signal SYS maintains the L level for a predetermined period (assertion period), such as when the power is turned on, all operation control registers REG and all VDP registers RGij are automatically set to a predetermined default value. Then, when the system reset signal SYS subsequently changes to the H level (negate level), in this embodiment, first, 32-bit data from the top address of the address space CS0 is set in the program counter PC of the performance control CPU 63, and the following 32-bit data is set in the stack pointer SP. In addition, in FIG. 9 and FIG. 16(c), the top area of the memory that stores the initial values of the program counter PC and stack pointer SP is called the vector table VECT.

As shown in FIG. 15(b), this vector table VECT stores vector numbers that specify priority and interrupt causes, etc., in correspondence with address information. The smaller the vector number, the higher the priority. For example, vector number 11 is a non-maskable interrupt (NMI), and the address information stored therein is the start address of the interrupt processing program executed upon an NMI interrupt. Vector number 64 is an internal interrupt from the VDP (VDP_IRQ0), and the address information stored therein is the start address of the interrupt processing program executed upon a VDP_IRQ0 interrupt.

The interrupt priority is as shown in FIG. 17(d), so that the columns for vector numbers smaller than vector number 64 store the start addresses of the interrupt processing programs for the control command receive interrupt IRQ_CMD, the 20 μS timer interrupt, and the 1 ms timer interrupt. On the other hand, the columns for vector numbers larger than vector number 64 store the start addresses of the interrupt processing programs (IRQ_SND, IRQ_RTC, etc.) that have a lower priority than VDP_IRQ 1.

In addition, in the vector table VECT, vector number 0 and vector number 1 are stipulated as setting values that should be automatically set in the program counter and stack pointer of the CPU at power-on reset. As shown in FIG. 15(b), in this embodiment, as an internal operation at power-on reset (reset assert period), 4-byte data "****" is set in the program counter PC, and 4-byte data "++++" is set in the stack pointer SP. Note that "****" is the top address value of the initial setting program Pinit (SP1 to SP9 in FIG. 15) stored in a non-volatile manner in the address space CS0, and "++++" is the address value of the beginning or end of the stack area secured in the internal RAM 59 and functioning in a LIFO (Last-In First-Out) manner.

In this embodiment, the register bank RBi is effectively used, so the stack area is not consumed during interrupt processing, and so a large amount of memory capacity is not required. In other words, in this embodiment, the stack area is used exclusively for function processing and subroutine processing.

As a result of the above operations, the performance control CPU 63 will then execute the initial setting program Pinit described after the address value "****". However, the memory READ operation of the address space CS0 is executed based on the default value (initial value) of the operation control register REG, which specifies the operation of the bus state controller 66 (Figure 8). The initial value of this operation control register REG is a value that is automatically set during the reset assertion period (the period shown in Figure 6 (d) during which the system reset signal SYS maintains an L level), and is set to the slowest READ access operation (default access operation) so that no matter what memory device the address space CS0 is configured with, READ access can be performed without any problems.

Therefore, to change this default access operation to an optimal access operation, first an optimal value is set in a predetermined operation control register REG that specifies the operation of the bus state controller 66 (Figure 8) for the address space CS0 (SP1). That is, in order to optimize the memory READ operation when accessing the PROM 53 that stores the initial setting program Pinit (SP1-SP9), the performance control program MainB (SP10), constant data, etc., to match the memory device, the bus width and the presence or absence of page access are set, and the operation timing of the chip select signal CS0, the READ control signal, the WRITE control signal, and other signals are optimally set (see Figure 38).

As a result of the above settings, the processing from step SP2 onwards will be executed by optimally reading the program stored in address space CS0 from memory. Next, the performance control CPU 63 sets an optimal value in a specified operation control register REG that specifies the operation of the bus state controller 66 (Figure 8) for the VDP register RGij, in order to optimize the READ/WRITE access operation when accessing the VDP register RGij (SP2).

As explained above, in this embodiment, the VDP register RGij is located in the address space CS7 of the performance control CPU 63, so a specified value is written to a specified operation control register REG to optimally set the operation timing of the chip select signal CS7 and other control signals.

Next, the register value of a specific VDP register RGij is read, and it is determined whether or not the value is a predetermined value (device code) (SP3). This is a confirmation and determination that the system clock of the VDP circuit 52 has stabilized. In other words, the VDP circuit 52 operates based on the oscillation output of the oscillator OSC2 supplied to the PLLREF terminal, and this is a determination of whether or not this VDP circuit 52 can normally accept commands from the CPU circuit 51 (i.e., settings to the VDP register RGij, etc.).

If it is confirmed that the system clock has stabilized by the device code read process (SP3), normal operation of the VDP circuit 52 can be expected, and a setting process for a specific VDP register RGij is executed (SP4 to SP6). Specifically, first, the endian setting (big/little) and data bus width for when the performance control CPU 63 accesses the VDP register RGij are set (SP4).

In this embodiment, the most significant bit of the set value is set to big endian, which is stored in the most significant bit of the VDP register RGij, and the data 32 bus width is set to 32 bits, but if these set values are the same as the default values, these setting processes can be omitted (the same applies to the following processes).

Next, the interrupt significance level (H/L) is set for the internal interrupts (VDP_IRQ0, VDP_IRQ1, VDP_IRQ2, VDP_IRQ3) from the VDP circuit to the CPU circuit, and a setting is made to operate the DDR (DRAM54) based on the clock signal (reference clock) to the PLLREF terminal (see FIG. 7(a)) (SP4). As explained in FIG. 7(a), the reference clock of oscillator OSC2 is supplied to the PLLREF terminal.

Next, address spaces CS1 to CS6 are defined to realize the memory map shown in Figure 9 (SP5). As explained above, address space CS3 is assigned to the internal register of the audio processor 27, address space CS4 is assigned to the internal register of the RTC 38 and the address space of the SRAM 39, address space CS5 is assigned to the external DRAM (DDR) 54, and address space CS6 is assigned to the work memory 57 of the built-in CPU.

Note that since it is fixedly specified that the VDP register RGij is assigned to address space CS7, there is no need to define address space CS7. Also, it is fixedly specified in advance that address space CS0 is from address 0x000000000 onwards in the memory map of the CPU circuit 51. Based on this specification, whether address space CS0 is secured in CGROM 55 or assigned to another memory device is specified by the H/L level of the HBTSL terminal.

As explained above, in this embodiment, the HBTSL terminal is set to L, which indicates that the address space CS0 is defined in addition to the CGROM 55. The specific bus width and optimal access operation of the control memory 53, which is other than the CGROM 55, have already been set in step SP1, so the processing of step SP5 is not required for the address space CS0 either.

Next, for the address spaces CS1 to CS6 defined in the processing of step SP5, a predetermined value is written to a predetermined operation control register REG regarding the bus width and the presence or absence of page access when accessing each address space CSi (SP6). Also, in order to optimally set the chip select signal CSi and others, a predetermined value is written to a predetermined operation control register REG (SP6). These processes are similar to the processes of steps SP1 and SP2, and the chip select signal CSi, READ control signal, WRITE control signal, and other operation timings are optimally set by the write process to the operation control registers that define the operation of the bus state controller 66 (Figure 8).

Next, a clear signal is output to the WDT circuit 58 to avoid an abnormal reset (SP7). This is done to take into consideration that the WDT circuit 58 automatically starts operating after power is turned on, and similar processing is executed repeatedly thereafter. Note that the processing of step SP9 is stored in the control memory 53 as subroutine SP7, but until the end of step SP9, the subroutine SP7 in the control memory 53 is called, and after the end of step SP9, another subroutine SP7' transferred to the external DRAM 54 is called and executed.

Next, among the programs and data stored in address space CS0, the vector handler Vopt (interrupt processing program), error recovery processing program Piram, performance control program MainB, variables with initial values D, and constant data C shown in Figures 15(b) and 16(c) are transferred to the external DRAM 54 or the internal RAM 59 (SP8). Note that variables with initial values D refer to initial value data stored in a specified variable area. This memory section initialization process (SP8) is a process that transfers programs and data in order to speed up performance control processing, and is a process to avoid accessing ROM, which has a slower access speed.

Next, the register bank RBi is set to be used (SP9). As a result, from then on, register banks RB0 to RB14 will function during interrupt processing, speeding up interrupt processing and reducing stack area consumption.

The above processing is realized by executing the "initial setting program Pinit" stored in the control memory 53, which is the address space CS0 (see FIG. 16(c)). Then, once execution of this initial setting program Pinit is completed, the main control processing is executed by the performance control program Main (SP10). Here, execution of the main control processing means execution of the "performance control program Main" transferred from the control memory 53 to the external DRAM 54 by the transfer processing of step SP8 (see FIG. 15(b)).

The specific contents of the main control process (performance control program Main) will be explained based on Figures 17(a) and 20(a), but before that, the memory section initialization process (SP8) will be explained. As shown in Figure 16(a), the memory section initialization process (SP8) first initializes the DMACs of multiple channels to a stopped state. Note that this process is merely a formality just to be on the safe side.

When the above processing is completed, the DMACi of the specified channel is started, and the vector handler Vopt (interrupt processing program) stored in the control memory 53 is DMA transferred to the built-in RAM 59 using the non-stop transfer method (see FIG. 10(b3)). In this embodiment, since the interrupt processing program Vopt is transferred to the built-in RAM 59, appropriate abnormality response processing is possible even when an abnormality occurs in the external DRAM 54.

The subsequent processing is the same, and is executed in a non-stop transfer mode using the DMACi of a specified channel, and the error recovery processing program Piram is DMA transferred to the built-in RAM 59 (SP62). In this embodiment, since the error recovery processing program Piram is transferred to the built-in RAM 59, the peripheral circuits can be reliably reset during the error recovery processing. For example, if the error recovery processing program Piram is transferred to an external DRAM 54, for example, other than the built-in RAM 59, the external DRAM 54 cannot be reset during the error recovery processing.

Next, the performance control program Main is DMA-transferred to the external DRAM 54 (SP63), and the constant data C is DMA-transferred to the external DRAM 54 (SP64). The constant data includes the lottery data used in the performance lottery, and the lamp drive data and motor drive data in the various drive data tables shown in FIG. 20(b). In addition, the variable D, which has an initial value, is DMA-transferred to the external DRAM 54 (SP65), and all of these are executed by a non-stop transfer method using the DMACi of a specified channel.

Finally, clear data is written to the beginning of variable area B of the external DRAM (SP66). If this beginning address is assumed to be ADb, then in the subsequent DMA transfer process, the source address is initially set to ADb and the destination address is initially set to ADb+1, and then the clear data is diffused while the address values ADb and ADb+1 are incremented, thereby executing the clear process of variable area B (SP67).

The above-described steps SP61 to SP66 and step SP67 all perform similar operations, as shown in FIG. 16(b). That is, first, for the DMACi of a specified channel, the following DMA transfer conditions are set (1) cycle steal transfer mode, (2) non-stop transfer method, and (3) the address values of the source and destination are incremented (SP68).

Next, the initial values of the source address and destination address are set (SP69), the transfer size is set, and interrupts are disabled (SP70), and then the DMA transfer operation is started (SP71). Note that the settings in steps SP68 to SP71 are all realized by setting a specified operation control register REG.

In the initialization process for this memory section, interrupts upon completion of DMA transfer are prohibited (SP70), so after starting the DMA transfer operation, the status flag of a specified operation control register REG is repeatedly read and accessed to wait for the completion of the DMA transfer (SP72). However, taking into account the processing time until the operation ends, a clear signal is repeatedly output to the WDT circuit 58 (SP73). Then, when the DMA transfer ends, the DMACi is stopped based on the setting operation to the specified operation control register REG.

Next, the operation of the main control process will be described with reference to Figures 17 to 20. As explained above, the process contents of the introductory part (SP20 to SP27) of the main control process are shown in Figure 17(a), and the process contents of the main part (ST4 to ST14) are shown in Figure 20(a). Note that the process of step SP27 in Figure 17 includes the processes of steps ST1 to ST3 in Figure 20(a).

As shown in Figure 17(a), the main control process (introduction) first specifies the bus width and ROM device type for the CGROM 55 (SP20). Specifically, as shown in Figure 18(a), a specific VDP register RGij (e.g., the CG bus status register) that specifies the operating status of the CG bus that controls the interface with the CGROM 55 is accessed for READ (SP80), and it is determined whether the operation of the CG bus can be set (SP81).

If the value of the CG bus Status register is 1, it means that the internal circuitry of the CG bus is undergoing a reset operation, and the setting value for the VDP register RGij cannot be accepted. Therefore, after confirming that the value of the CG bus Status register has changed from 1 to 0 (SP81), the device sets operational parameters such as (1) the enable/disable status of each device section SPAi, (2) the type of ROM device, and (3) the data bus width in the specified VDP register RGij for each device section (SPA0 to SPAn) that can be defined corresponding to the memory devices that make up the CGROM (SP82).

As shown in FIG. 17(a), in this embodiment, the CGROM 55 can be divided into multiple areas (device sections), and for example, the memory device and data bus width can be selected for each device section (SPA0 to SPAn). Memory devices are broadly classified into, for example, (1) the SATA module (AHSI/F) used in this embodiment, (2) memory elements using a parallel I/F (Interface) format, and (3) memory elements using a sequential I/F format, and for each of the broadly classified memory devices, a specific memory device can be selected, and the data bus width, etc. can be specified arbitrarily.

Next, in order to optimize the memory READ operation with the memory device selected for each device section (SPA0 to SPAn), predetermined operating parameters are set in a predetermined VDP register RGij (SP83). The operating parameters include set values that stipulate the operation timing of the chip select signal and other control signals (such as the READ control signal). In addition, when a memory element that uses a sequential I/F format is selected, the output timing of the address latch and the number of read clocks are also specified to realize the operation shown in FIG. 18(b).

Therefore, it is possible to configure CGROM 55 by combining different types of memory devices. However, in this embodiment, CGROM 55 is configured using only SATA modules, and only the device section (SPA0) is enabled, while the other device sections (SPA1 to SPAn) are disabled.

In any case, once the setting process of steps SP82 to SP83 is complete, a specified value is written to a specified VDP register RGij in order to effectuate the setting process (SP84). This takes into consideration the fact that it takes a certain amount of time for the internal circuitry of the CG bus to be able to operate in response to the setting process of steps SP82 to SP83, and while the internal circuitry is operating, the value of the CG bus Status register (see SP80) mentioned above is 0.

Therefore, thereafter, the CG bus Status register is repeatedly accessed for a read (SP85), and the process ends after confirming that the value of the Status register has returned from 1 to 0 (SP86). Note that regardless of the predetermined number of determinations, if the value of the Status register has not returned from 1 to 0, the process of step SP66 may end. In that case, however, the game process will begin in a state in which the CGROM cannot be accessed normally, and the WDT circuit 58 will then start up at some point thereafter, causing the composite chip 50 to enter an abnormal reset state. In this case, the power-on reset operation will be executed again.

On the other hand, after the processing of step SP20 in FIG. 17 has been executed normally, the internal circuits of the CPU circuit 51, such as the interrupt controller INTC, the DMAC circuit 60, and the multifunction timer unit MTU, are individually initialized by software processing (SP21).

Next, the multifunction timer unit MTU starts a specified timer measurement operation (SP22), and then writes an enabled setting value to a specified operation control register REG for internal interrupts and internal interrupts to set the interrupt enabled state (SP23).

As a result, various interrupts as shown in FIG. 17(d) may occur. Normally, at this timing, the sound processor 27 has completed its initialization sequence, so the end interrupt signal IRQ_SND should have dropped to L level, as shown in FIG. 6(c). Therefore, the interrupt processing shown in FIG. 17(c) is started, and the performance control CPU 63 initializes the error flag ERR to 1, and performs READ access to address space CS3 (SP30), obtains the value of a specified sound register SRG of the sound processor 27, and determines whether the initialization sequence has ended normally (SP31).

If the initialization sequence does not end normally, the performance control CPU 63 writes a reset command to a specified sound register SRG of the sound processor 27 (SP32) and sets the error flag ERR, which is initially set to 1, to 2 (SP33). This error flag ERR determines whether or not to execute the sound processor initialization process (SP26), and the error flag ERR = 1 is the execution condition for step SP26.

Meanwhile, in response to receiving the reset command, the audio processor 27 restarts the initialization sequence with the end interrupt signal IRQ_SND at H level, and when the initialization sequence ends, the end interrupt signal IRQ_SND drops to L level. As a result, the process in FIG. 17(c) is executed again.

The above describes the exceptional case where the initialization sequence does not end normally, but normally, following step SP31, the processing of step SP32 is executed, and the performance control CPU 63 writes a predetermined value to a predetermined sound register SRG, thereby returning the end interrupt signal IRQ_SND from L level to H level (SP34).

Finally, a specified value is written to a specified audio register SRG, allowing READ/WRITE access to all audio registers SRG (SP35). As a result of this process, the necessary setting processes can be executed in the subsequent audio processor initialization process (SP26).

The above describes an example of a Maskable Interrupt that corresponds to the interrupt permission setting of step SP23, but a non-maskable interrupt based on the oscillation of oscillator OSC2 stopping can be activated at any time. As explained above, the operating clock (CPU system clock) of circuits other than the built-in CPU (performance control CPU 63) is generated by multiplying the frequency of the output clock of oscillator OSC2 using a PLL (Phase Locked Loop), and if the oscillation of oscillator OSC2 stops, normal operation of the VDP circuit 52 is impossible thereafter.

Meanwhile, the operating clock of the performance control CPU 63 is generated by multiplying the output clock of the oscillator OSC1 by a PLL, so program processing can continue. Moreover, the interrupt processing program is stored in the built-in RAM 59. The performance control CPU 63 then issues an abnormality notification by sound or lamp (SP28), and continues to output a clear signal to the WDT circuit 58 (SP29). The abnormality notification is, for example, an audio notification saying "An abnormality has occurred. Please contact a staff member immediately." The reason for continuing to output the clear signal to the WDT circuit 58 is to avoid an abnormal reset operation. In other words, in the event of a serious abnormality in which the oscillator OSC1 stops operating, it is considered that the device cannot be expected to return to normal even if the abnormality reset process is repeated.

As above, we have explained Figures 17(b) and 17(c), so we will return to Figure 17(a) and continue the explanation. In step SP24, in order to protect the program area of the external DRAM, necessary areas are set to be write-protected. Next, the clock circuit 38, which is battery-powered when the power is cut off, is checked for normal operation when the power is cut off, and the alarm interrupt is reset just to be sure (SP25).

Then, on condition that the error flag ERR = 1, the necessary setting values are written to the built-in register (audio register SRG) of the audio processor 27 to execute initialization processing (SP26). Note that if the error flag ERR = 0, a predetermined time is waited until the error flag ERR = 1, but if the time limit is exceeded, an infinite loop process is started to start the WDT circuit 58.

Next, the necessary setting values are written to the VDP register RGij to execute the initialization process for the VDP circuit 52 (SP27). Note that the process of step SP27 includes the processes of ST1 to ST3 in FIG. 20.

The above describes an embodiment in which the end interrupt signal IRQ_SND is received from the audio processor, but it is also preferable to omit the interrupt process in FIG. 17(c). FIG. 19 shows a modified embodiment in which a 1 ms timer interrupt signal generated by the multifunction timer unit MTU is used instead of the end interrupt signal IRQ_SND.

Figure 19 illustrates part of the 1 ms timer interrupt process, which realizes four stages of operation based on the value (0/1/2/3) of the operation management flag FLG, which is initially set to zero. Note that the IRQ_SND output terminal of the audio processor 27 is open, and the IRQ_SND input terminal of the CPU circuit 51 is fixed to the H level.

In the 1 ms timer interrupt process, first, if the operation management flag FLG = 0 is determined in the process of step SP42, it is confirmed that the initialization sequence of the audio processor 27 has ended normally (SP43). If it has ended normally, a predetermined value is written to a predetermined audio register SRG to clear the interrupt signal (IRQ_SND) (SP46), and the operation management flag FLG is set to 1 (SP47). Note that the processes of steps SP43 and SP46 are the same as the processes of steps SP31 and SP34 in FIG. 17(c).

On the other hand, if the initialization sequence has not ended normally, a reset command is written to a specific voice register SRG to cause the voice processor 27 to start the initialization sequence (SP44) and to reset the operation management flag FLG to zero (SP45). Note that the processing in step SP44 corresponds to the processing in step SP32 in FIG. 17(c).

Normally, the operation management flag FLG = 1 after the processing of step SP47, so at the next 1 ms timer interrupt, a specified value is written to a specified voice register to allow access to all voice registers (SP48), and the operation management flag FLG = 2 is set (SP49). The processing of step SP48 corresponds to the processing of step SP35 in FIG. 17(c).

Next, in the 1 ms timer interrupt with the operation management flag FLG = 2, similar to step SP26 in FIG. 17(a), the necessary setting values are written to the built-in register (audio register SRG) of the voice processor 27 to execute initialization processing (SP50), and the operation management flag FLG = 3 is set.

Operation management flag FLG = 3 indicates the normal voice control state, and voice control is progressed by setting the necessary operation parameters in the necessary voice registers SRG (SP52).

The above describes a method for checking whether the initialization sequence of the audio processor 27 has ended normally by using an interrupt process caused by an interrupt signal (IRQ_SND) (SP31 in FIG. 17(c)) and a method for checking using a 1 ms timer interrupt process (SP43 in FIG. 19), but the present invention is not limited to these methods. For example, it is also preferable to determine whether the initialization sequence of the audio processor 27 has ended normally as part of the process of step SP26 in FIG. 17.

The introductory part of the main control process (SP20 to SP27 in FIG. 17) has been explained above, so below, the operation of the main part of the main control process will be explained based on FIG. 20. As shown in FIG. 20, the operation of the performance control CPU 63 is composed of a main control process (a), a timer interrupt process (b) that starts every 1 ms, a reception interrupt process (not shown) that starts in response to a control command CMD, a VBLANK interrupt process (c) that starts in response to a VBLANK signal generated at the start of the V blank (vertical blanking period) of the display device DS1, and a drawing abnormality interrupt process (d) that occurs when the operation freezes or an irrational instruction command is detected. Note that an explanation of the 20 μS interrupt process will be omitted.

In the reception interrupt process, the control command CMD received from the main control unit 21 is stored in a specified reception buffer so that it can be referenced in the main control process (ST13), and the process ends. In addition, in the VBLANK interrupt process (FIG. 20(b)), the interrupt counter VCNT is incremented for each VBLANK interrupt (ST15), and at the start of the main control process, the interrupt counter VCNT is cleared to zero after determining the operation start timing of 1/30 seconds based on the value of the interrupt counter VCNT (ST4).

On the other hand, as shown in FIG. 20(b), the timer interrupt process includes a lamp performance and motor performance progress process (ST18), and a sensor signal acquisition process (ST19) that acquires the origin sensor signals SN0 to SNn and the chance button signal. The lamp performance and motor performance are controlled based on a performance scenario that centrally manages all performance operations, and when the performance start time managed by the performance counter EN is reached, the motor drive table and lamp drive table are identified in the performance scenario update process (ST11).

Then, the motor performance proceeds based on the identified motor drive table, and the lamp performance proceeds based on the identified motor drive table. As explained above, there are also embodiments in which the DMAC circuit (first and second DMA channels) 60 functions during the operation of step ST18. Note that the motor performance proceeds every 1 mS, but the lamp performance proceeds at appropriate timings longer than 1 mS.

On the other hand, as shown in FIG. 20(d), in the drawing abnormality interrupt process, the status register RGij, which indicates the operating state of the drawing circuit 76, is accessed for READ to identify the cause of the interrupt. Specifically, it is identified whether the drawing abnormality interrupt is due to (1) the detection of an abnormal command (bit corruption) or (2) the operation abnormality (freezing) of the drawing circuit 76 (ST16a). Then, if the drawing abnormality interrupt is due to the detection of an abnormal command, a predetermined value is written to a predetermined system control register RGij, thereby initializing the drawing circuit 76 (ST16b). This operation is nothing more than an individual reset operation of the reset path 4B shown in FIG. 6(b).

Next, after the normal end of the individual reset operation is confirmed by a specific status register RGij, a group of operating parameters that define the operation of the drawing circuit 76 are reset in the specific drawing register RGij, and the process is terminated (ST16c). Then, after adjusting the stack area that stores the return address (release process that erases the return address after the interrupt process), the process proceeds to step ST13 (ST16c).

On the other hand, in the case of a drawing abnormality interrupt based on an operational abnormality of the drawing circuit 76, the process transitions to an infinite loop process (ST16d), which activates the WDT circuit 58 and resets the entire composite chip 50. If it is not desired to reset the CPU circuit 51, a predetermined keyword string may be output to the pattern check circuit CHK and only the VDP circuit 52 may be reset by the reset signal RST (see FIG. 6(b)). In this case, after confirming that the reset operation of the VDP circuit 52 has been completed successfully, the process transitions to steps ST4 and ST13. In order to avoid overlooking the control command CMD as much as possible, it is better to transition to step ST13 from step ST4, including other cases.

When the entire composite chip 50 is reset, all previous effects are erased and the effect control is returned to the initial state (power-on state). However, when only the VDP circuit 52 is reset, the series of effect control can be continued, although there is a certain waiting time until the reset operation of the VDP circuit 52 is complete. Furthermore, since the effect control CPU 63 controls the image effect, lamp effect, and sound effect in a unified manner, there is no unnatural discrepancy between the effects.

Next, the main control process (a) will be described for an embodiment in which the preloader does not function. As shown in FIG. 20(a), the main control process is divided into introductory initial processing (ST1 to ST3) that is executed after the CPU is reset, and regular processing (ST4 to ST14) that is repeatedly executed every 1/30th of a second thereafter. Note that the initial processing (ST1 to ST3) is part of the introductory part of the main control process, and the regular processing represents the main body of the main control process.

The steady-state processing starts when the interrupt counter VCNT becomes VCNT≧2 (ST4), so the operating period δ of the steady-state processing is 1/30 seconds. This operating period δ is nothing but the actual operating period δ of the VDP circuit 52, which operates intermittently under the control of the performance control CPU 63. The reason for setting the judgment condition as VCNT≧2 is to take into consideration the possibility that the steady-state processing (ST4 to ST14) may be abnormally prolonged and the timing of VCNT=2 may be missed, but it is designed to prevent a situation in which VCNT=3 occurs.

Continuing with the explanation of the main control process (Figure 20 (a)) based on the above, in this embodiment, in the initial process, the built-in VRAM 71 with a storage capacity of 48 MB is appropriately divided into an ACC area (a) with appropriate storage capacity, a page area (b), and an arbitrary area (c) (ST1). Specifically, for the ACC area (a1, a2) and the page area (b), the start addresses of each area and the total required data size are set in a specified index table register RGij (ST1). Then, the secured ACC area (a1, a2) and the remaining area not included in the page area (b) become the arbitrary area (c).

Here, the lowest 11 bits of the area start addresses of the first and second ACC areas (a1, a2) and the page area (b) must each be 0, but can be selected arbitrarily in units of 2048 bits (1 address = 1 byte, selection in increments of 256 addresses). The total data size can also be selected arbitrarily within the range of an integer multiple of the unit size. Although not particularly limited, the unit size of the ACC area (a) is 2048 bits, and the unit size of the page area (b) is 512 kbits.

In this embodiment, certain conditions are set for the area settings of the ACC area (a1, a2) and the page area (b), in order to eliminate as much wasted area as possible from the built-in VRAM 71, which has a limited memory capacity, while facilitating the internal operation of the VDP circuit 52. In other words, while increasing the memory capacity of the built-in VRAM 71 unnecessarily raises concerns about rising manufacturing costs and increasing the chip area, allowing free area settings that completely eliminate wasted area complicates internal processing and makes it difficult to shorten the processing time for VRAM access. The same reason is also why certain restrictions are set for securing the index space, which will be explained below.

Continuing with the above, following the processing of step ST1, the necessary index space IDXi is secured for the page area (b) and the arbitrary area (c) (ST2). Specifically, the necessary information is set in a specified index table register RGij to secure the index space IDXi for each area (b) and (c).

For example, when an index space IDXi is provided in the page area (b), multiple information of an arbitrary horizontal size Hx and an arbitrary vertical size Wx (multiple information of length and width for the unit space) corresponding to an arbitrary index number i is set in a predetermined index table register RGij (ST2).

As explained above, the index space IDXi of the page area (b) has a unit space of 128 lines horizontally x 128 lines vertically, and one pixel is specified by 32 bits of information, so based on the horizontal size Hx and vertical size Wx settings, an index space IDXi with a data size (bit length) = 32 x 128 x Hx x 128 x Wx is secured. The top address (space top address) of the index space IDXi of the page area (b) is automatically assigned internally.

When an index space IDXi is provided in the arbitrary area (c), an arbitrary start address (space start address) STx and multiple information of an arbitrary horizontal size Hx are set in a predetermined index table register RGij corresponding to an arbitrary index number i (ST2). Here, "arbitrary" means that a predetermined condition is assumed, and the horizontal size Hx is arbitrarily determined in units of 256 bits, the lowest 11 bits of the start address STx are 0, and the horizontal size Hx is arbitrarily determined in units of 2048 bits. As explained above, the vertical size of the arbitrary area is fixed to 2048 lines, so that an index space of data size (bit length) = 2048 x Hx is secured after the start address STx based on the setting of the horizontal size Hx.

Specifically, as the frame buffer FBa of the main display device DS1, a pair of index spaces with a horizontal size of 1280 x vertical lines 2048 are set in one or more predetermined index table registers RGij with a specified index number for each, and as the frame buffer FBb of the sub display device DS2, a pair of index spaces with a horizontal size of 480 x vertical lines 2048 are set in one or more predetermined index table registers RGij with a specified index number for each. Note that if the number of horizontal pixels of the display device does not match an integer multiple of 256 bits/32 bits, the horizontal size of each index space is set to a value larger than the number of horizontal pixels of the display device and which is an integer multiple of 256/32=8, thereby minimizing the generation of wasted memory area.

As described above, the required size information and address information for the page area (b) and the arbitrary area (c) are set in the specified index table register RGij, respectively, to generate the required number of index spaces IDXi (ST2). Then, in response to this setting process (ST2), an index table IDXTBL that specifies the address information and size information of each index space IDXi is automatically constructed. As shown in FIG. 11(a), the index table IDXTBL stores the top address of each index space IDXi together with other necessary information, and is referenced when transferring data within the VDP circuit 52 or when acquiring data from an external storage resource (see FIG. 12). Note that the index space IDXi of the AAC area (a) is automatically generated and automatically deleted when necessary, so the setting process of step ST2 is not necessary.

As shown in Figures 11(a) and (b), a pair of frame buffers FBa and FBb are secured in the arbitrary area (c), and each is assigned an index number. In an embodiment that does not use a Z-buffer, a pair of index spaces 255 and 254, assigned with index numbers 255 and 254, are secured as the frame buffer FBa. Also, a pair of index spaces 252 and 251, assigned with index numbers 252 and 251, are secured as the frame buffer FBb. Note that in this embodiment, a working area with index number 0 (index space 0) is also secured in the arbitrary area (c).

In addition, in this embodiment, the required number of index spaces IDXi to be the decoded area of the IP stream video are secured in the page area (a), and the index number i is assigned. However, initially, only the index space _IDX0 for the background video (IP stream video) is secured. Then, depending on the necessity of the image performance (variation performance or notice performance), the index space IDXj of the page area (a) is increased based on the setting process to the index table register RGij and the instruction command of the display list DL, and then, when it becomes unnecessary, the index space IDXj is released. That is, FIG. 11 (a) shows the index table IDXTBL during normal operation.

The index space of the ACC area (a) is automatically generated when necessary based on the instruction command written in the display list DL, and the top address of the automatically generated index space IDXj and other necessary information are automatically set in the index table IDXTBL. In this embodiment, this AAC area (a) is used as a decoding area for still images and other textures.

The above operation of reserving index space is realized mainly by the setting operation to the index table register RGij included in the control register group 70, but by executing the necessary setting operation (ST3) to the other VDP register RGij following the processing of steps ST1 to ST2, steady operation (intermittent operation) of the VDP circuit 52 shown in Figures 28 to 29 is made possible.

In this embodiment, the necessary setting process (ST3) includes at least the processes (SS30 to SS43) shown in Table 1. Note that the order of the processes in steps SS30 to SS43 is not limited, and they can be executed in any order regardless of the order described below.

In this embodiment, first, a specific system control register RGij is set to construct a dual link transmission path for the main display device DS1 (SS30). As a result of this setting, the output of the display circuit 74A is supplied to the LVDS unit 80a and the LVDS unit 80b in a state in which the dot clock DCK is divided into an ODD signal and an EVEN signal, which are obtained by dividing the dot clock DCK by two.

Next, for display circuits 74A and 74B, a predetermined system control register RGij is set to generate dot clocks DCK _A and DCK _B based on the 40 MHz reference clock (output of oscillator OSC2) (SS31), and the multiplication ratio and division ratio for this reference clock are appropriately specified for each display circuit (SS32).

The dot clock DCK is set separately for the display circuits 74A and 74B, and the frequency of the dot clock DCK _A for the main display device DS1 applied to the display circuit 74A is set to 108 MHz as described above, while the frequency of the dot clock DCK _B for the sub-display device DS2 applied to the display circuit 74B is set to 27 MHz, corresponding to 480 horizontal x 800 vertical pixels.

In addition, a specific system control register RGij is set so that the start of operation of the display circuit 74B is synchronized with the start of operation of the display circuit 74A (SS33).

Next, the number of display lines and the number of horizontal pixels are set for each display device DS1, SD2 by writing predetermined operating parameters (number of lines and number of pixels) to a predetermined display register RGij that specifies the operation of the display circuit 74 (SS34). In this embodiment, the number of horizontal pixels of the main display device DS1 is 1280 dots, and the number of display lines is 1024 rows. The number of horizontal pixels of the sub-display device DS2 is 480 dots, and the number of display lines is 80 rows. As a result of the setting process of step SS34, the vertical and horizontal dimensions of the effective data area (dashed line area in FIG. 20(e)) to which the display circuits 74A, 74B should access for READ are specified in each frame buffer FBa, FBb.

Next, the number of cycles THc of the horizontal period TH and the horizontal waiting time WTh are set for each display device DS1, SD2 by writing predetermined operating parameters (THc, WTh) to a predetermined display register RGij that specifies the operation of the display circuit 74 (SS35). In addition, the number of lines TVl of the vertical period TV and the vertical waiting time WTv are set for each display device DS1, SD2 by writing predetermined operating parameters (TVl, WTv) to a predetermined display register RGij (SS36).

As explained with reference to FIG. 14, for the main display device DS1, the number of cycles of the horizontal period TH is set to THc = 1662, and the number of lines of the vertical period TV is set to TVl = 1083. In addition, the horizontal waiting time WTh is set to 382, and the vertical waiting time WTv is set to 59 lines. On the other hand, for the sub-display device DS2, for example, the number of cycles of the horizontal period TH is set to THc = 519, the number of lines of the vertical period TV is set to TVl = 867, and the horizontal waiting time WTh is set to 39, and the vertical waiting time WTv is set to 67 lines. Note that THc-WTh = 519-39 = 480, and TVl-WTv = 867-67 = 800, which matches the number of pixels of the sub-display device (480 horizontal x 800 vertical).

In any case, the frequency F _dot (=108 MHz) of the dot clock DCK is determined by the process of step SS32, and the number of cycles THc (=1662) of the horizontal period TH and the number of lines TVl (=1083) of the vertical period TV are specified for the main display device DS1 by the processes of steps SS35 to SS36, so that the display period of one frame is determined to be THc x TVl/F _dot . Specifically, the display period of one frame is determined to be 1083 x 1662/108 MHz = 16.667 mS, and the frame rate FR is determined to be 1/60 seconds.

For the sub-display device DS2, for example, the frequency F _dot of the dot clock DCK is determined to be 27 MHz, the number of cycles of the horizontal period THc is 519, and the number of lines of the vertical period TVl is 867, so that 519×867/27 MHz is determined to be 16.66 mS.

In this embodiment, in response to the above-mentioned confirmation process, the display circuit 74 enters a V blank start state every 1/60th of a second, and the display operation shown in FIG. 14 is repeated. Note that in FIG. 14, the start timing of the display operation and the end timing of the display operation indicated by circles indicate the V blank start timing.

Then, based on this V-blank start timing, the horizontal reference point TH0 (= horizontal reference time) and the vertical reference point (= vertical reference time) TV0 in the operation of the display circuit 74 are defined, and the display circuit 74 waits from the horizontal reference point TH0 until the horizontal waiting time WTh has elapsed without outputting image data corresponding to each pixel of the display device. Similarly, the display circuit 74 is configured to wait from the vertical reference point TV0 until the vertical waiting time WTv has elapsed without outputting image data corresponding to each pixel of the display device.

In addition, since the display circuit 74B operates in synchronization with the display device 74A (SS33), the start and end timing of the display operation for the sub-display device DS2 is also the same as that of the main display device DS1. Therefore, the frame period (519 x 867/27) for the sub-display device DS2 is set shorter than the frame period (1083 x 1662/108) for the sub-display device DS2, so that the update process for the sub-display device DS2 is set to be completed when the V blank starts.

Next, in this embodiment, for the sub-display device DS2, the pulse width of the horizontal cycle signal HS and the number of cycles from the V blank start timing of the pulse rising edge are set in a specific display register RGij (SS37). Also, for the sub-display device DS2, the pulse width of the vertical cycle signal VS and the number of cycles from the V blank start timing of the pulse rising edge are set (SS38).

As explained above, the main display device DS1 does not require a horizontal synchronization signal HS or a vertical synchronization signal VS, so the above processing (SS37 to SS38) for the main display device DS1 is not necessary. However, if the setting processing of steps SS37 to SS38 is omitted, the default values set at the time of power reset will function, so in reality, the display device 74A will also output a horizontal synchronization signal HS and a vertical synchronization signal VS.

According to the default value, for example, a horizontal synchronization signal HS with a pulse width of 40 clocks is output, which becomes active 16 clocks after the V blank start timing, and a vertical synchronization signal VS with a pulse width of 3 lines is output, which becomes active in synchronization with the V blank start timing.

This operation means that a horizontal synchronization signal HS with a horizontal front porch HPv = 16, pulse width PWh = 40, and horizontal back porch BPv = 326 is output to the main display device DS1 during the horizontal wait time WTh = 382 clocks, and a vertical synchronization signal VS with a vertical front porch HPv = 0, pulse width PWv = 3, and vertical back porch BPv = 56 is output during the vertical wait time WTv = 59 lines. However, as mentioned above, these synchronization signals are ignored in the main display device.

In order to prevent the synchronization signals HS and VS based on the default values from being output, a configuration may be adopted in which a specified system control register RGij is set so that the horizontal synchronization signal HS and the vertical synchronization signal VS are not output. When such a mask setting is provided, the output terminal of the horizontal synchronization signal HS and the output terminal of the vertical synchronization signal VS of the VDP circuit 52 can maintain a fixed value of H level or L level.

Next, a specific system control register RGij is set to allow V blank interrupts (SS39). As a result, in this embodiment, the VBLANK start interrupt shown in FIG. 20(c) occurs in response to the V blank start timing that occurs every 16.667 mS = 1/60 seconds. This V blank interrupt timing specifies the start timing of the regular processing (ST5 to ST14) of the performance control CPU 63, and also indicates the start timing of the display period for the display circuits 74A and 74B (the end timing of the previous display period).

Next, a predetermined operating parameter (address value) is written to a predetermined display register RGij to specify the vertical display start position and horizontal display start position for each frame buffer FBa, FBb (SS40). As a result, the effective data area whose vertical and horizontal dimensions were specified in the processing of step SS34 is determined on the frame buffers FBa, FBb. Here, the vertical display start position and horizontal display start position are relative address values in each index space, and in the example shown in Figure 20 (e), the display start position is (0, 0).

Here, "display area" refers to the index space (frame buffers FBa, FBb) from which the display circuits 74A, 74B should read image data to drive the display devices DS1, DS2, and refers to either of the double buffers in the frame buffers FBa, FBb, which each have a double buffer structure. However, the display circuits 74A, 74B actually read image data only from the "valid data area" in the display area (0) or display area (1) identified in steps SS34 and SS40.

Next, "display area (0)" and "display area (1)" are set in the display register RGij (DSPAINDEX) for the display circuit 74A that drives the main display device DS1 and in the display register RGij (DSPBINDEX) for the display circuit 74B that drives the sub-display device DS2, respectively, to define each display area (SS41).

Although not limited in any way, in this embodiment, for frame buffer FBa, index space 254 of index number 254 in VRAM arbitrary area (c) is defined as the "display area (0)," and index space 255 of index number 255 in VRAM arbitrary area (c) is defined as the "display area (1)" (SS41).

Furthermore, for frame buffer FBb, index space 251 of index number 251 in VRAM arbitrary area (c) is set as "display area (0)," and index space 252 of index number 252 in VRAM arbitrary area (c) is set as "display area (1)" (SS41). Note that there is no particular limitation on defining the "display area" in the initial processing (ST3), and the index space (display area) to which display circuit 74 should access image data for READ may be toggled for each operating cycle δ.

In this embodiment, once the initial settings including the above processes (SS30 to SS41) are completed, a predetermined prohibited value is set in the first type of prohibited setting register RGij so that the setting value in the predetermined system control register RGij is not subsequently changed due to the influence of noise or the like (first prohibited setting SS42).

The setting values that are prohibited from being written in the future include (1) setting values related to the display clock DCK of the display devices DS1 and DS2, (2) setting values related to the sampling clock of the LVDS, (3) setting values related to the selection operation of the output selection circuit 79, and (4) the synchronization relationship between the multiple display devices DS1 and DS2 (display circuit 74B being subordinate to the operating cycle of display circuit 74A). Note that although software processing exists to release the first prohibition setting, it is not used in this embodiment. However, it is preferable to use it as necessary.

Next, a predetermined prohibited value is set in the second type of prohibition setting register RGij, thereby prohibiting writing to the VDP register RGij of the initial setting system (second prohibition setting SS43). Here, the registers that are prohibited include the VDP register RGij related to steps SS30 to SS42.

On the other hand, by setting a specific prohibition value in the third type prohibition setting register RGij, it is also possible to set prohibitions on multiple VDP registers, including the VDP registers related to the setting processes of steps ST1 to ST3 (third prohibition setting). However, this is not used as a general rule in this embodiment. In any case, the second prohibition setting and the third prohibition setting can be released at will by writing a release value to a specific release register RGij, and it is also possible to change the setting value during normal operation.

The initial setting process of steps ST1 to ST3 described above is executed based on the initial value setting table SETTABLE (see FIG. 34), which associates the register address value of the VDP register RGij with the setting value for that register RGij. Having explained the initial setting process above, we will now provide a brief explanation of the steady-state operation (intermittent operation) of the VDP circuit 52 controlled by the performance control CPU 63 based on FIG. 28(a) and FIG. 29(b), before explaining the steady-state processing (ST4 to ST14).

The intermittent operation of the VDP circuit 52 is as shown in Figures 28 and 29. In an embodiment that does not use the preloader 73, as shown in Figure 28(a), the display list DLi completed by the performance control CPU 63 is issued to the drawing circuit 76 in its operation cycle (T1), and the drawing circuit 76 completes image data in the frame buffers FBa, FBb by drawing operations based on the display list DLi. Then, the image data completed in the frame buffers FBa, FBb is output by the display circuit 74 to the display devices DS1, DS2 in the next operation cycle T1+δ, and the display screen sensed by the player is created based on the subsequent drawing operations of the display devices DS1, DS2.

On the other hand, in an embodiment using a preloader 73, as shown in FIG. 29(a), the display list DLi completed by the performance control CPU 63 is issued to the preloader 73 in its operating cycle (T1), and the preloader 73 interprets the display list DLi and performs the necessary pre-reading operations while rewriting a portion of the display list DLi to complete the rewrite list DL'. The pre-read CG data and the rewrite list DL' are stored in the appropriate locations in the DRAM 54.

Next, in the next operating cycle (T1+δ), the drawing circuit 76 retrieves the rewrite list DL' from the DRAM 54, and completes the image data in the frame buffers FBa and FBb through drawing operations based on the rewrite list DL'. Then, in the next operating cycle (T1+2δ), the display circuit 74 outputs the completed image data in the frame buffers FBa and FBb to the display devices DS1 and DS2, and the display screen perceived by the player is created based on the subsequent drawing operations of the display devices DS1 and DS2.

The intermittent operation of the VDP circuit 52 has been briefly explained above, but to realize the operation shown in Figures 28 to 29, after the initial processing (ST1 to ST3), the performance control CPU 63 repeatedly refers to the value of the interrupt counter VCNT and waits for the operation start timing to be reached, and when the operation start timing (the start timing of the next V blank) is reached, the interrupt counter VCNT is cleared to zero (ST4).

After that, steady-state operation is started. In this embodiment, first, it is determined whether or not the operation start conditions for starting steady-state operation are met (ST5). Note that this determination timing is the timings T1, T1+δ, T1+2δ, ... shown in Figures 28 and 29, that is, the start timing of the vertical blanking period (VBLANK) of display device DS1. Note that the display timing of display device DS2 is set during initial setting (ST3) so that it is subordinate to the display timing of display device DS1.

The operation start condition determined at the start timing of the vertical blanking period (VBLANK) differs depending on whether or not the preloader 73 is used, so first, an embodiment (FIG. 20) that does not use the preloader 73 will be described. In this case, the circuit configuration and program are designed so that the internal operation of the VDP proceeds as shown in the time chart of FIG. 28(a). That is, based on the display list DL1 completed in the operation cycle (T1), the drawing circuit 76 should complete the drawing operation during that operation cycle (T1 to T1+δ). However, for example, as in the case of the display list DL3 completed in the operation cycle (T1+2δ) of FIG. 28(a), it cannot be said that there is no case where the drawing operation is not completed during that operation cycle (T1+2δ to T1+3δ). Also, there is a possibility that an underrun abnormality has occurred in the display circuit 74, in which the generation of display data does not keep up with the display timing.

The judgment process in step ST5 takes such a situation into consideration, and the performance control CPU 63 accesses the status register RGij (a type of control register group 70) that indicates the operating state of the drawing circuit 76, and judges at the timing of step ST5 whether the drawing circuit 76 has completed the necessary operations and whether there is an underrun abnormality. The presence or absence of an underrun abnormality is judged based on the underrun counters URCNTa to URCNTc. Also, in an embodiment that does not utilize the preloader 73, for example, at timing T1+δ in FIG. 28(a), the status information of the drawing register related to the drawing circuit 76 is read and accessed to confirm that the drawing operation based on the display list DL1 has ended.

If the operation start conditions are not met (abnormal/non-conformance), the abnormality flag ER, which counts the number of abnormalities, is incremented and steps ST6 to ST8 are skipped. The abnormality flag ER, along with other serious abnormality flags ABN, is determined in the processing of steps ST9 and ST10, and assuming that the serious abnormality flag ABN is in the reset state, if the number of consecutive abnormalities is not high (ER≦2), the performance command analysis processing is executed as in the normal case (ST13).

In the case of an underrun abnormality, steps ST6 to ST8 are similarly skipped. Then, a predetermined clear value is written to a predetermined system control register RGij to initialize the display clock DCK (frequency) and the display circuit 74 (ST10c). After confirming that this initialization process has ended normally, the frequency of the display clock DCK and the values of a group of system control registers RGij that define the operation of the display circuit 74 are reset to their specified values (ST10c), and the performance command analysis process is executed (ST13).

The performance command analysis process (ST13) determines whether a control command CMD has been received from the main control board 21, and if a control command CMD has been received, analyzes the control command CMD and executes the necessary processing (ST13). The necessary processing here includes preparation processing for the start of a new variable performance based on a control command CMD that instructs the start of a variable performance, and starting an error notification based on a control command CMD that indicates the occurrence of an error. Next, a clear pulse is output to the WDT circuit (ST14), and processing returns to step ST4.

The above describes the case where there is a minor underrun abnormality or where the operation start conditions are not met and the abnormality flag ER is ER≦2. In such cases, in that operating cycle, the process of toggling the display area read by the display circuit 74 (ST6) and the process of creating a display list (ST7) are skipped, and the performance scenario does not progress (see ST8 to ST12). This is to prevent the output of image data from the frame buffers FBa and FBb in an incomplete state. Therefore, for example, in the operating cycle (T1+3δ) in Figure 28(a), the image performance does not progress, and a frame drop occurs in which the original screen (screen based on DL2) is redisplayed.

To avoid dropping frames, it is also possible to configure the system to wait until the operation start conditions are met. However, since there are many control processes (ST6 to ST12) that the performance control CPU 63 must execute, and each process needs to have enough time, in this embodiment, frames are dropped when the operation start conditions are not met.

However, even if a frame is dropped, the image effects are only delayed by about 1/30 to 2/30 of a second compared to the lamp and motor effects that proceed through interrupt processing (Figure 20 (b)), and the player will not notice this. Furthermore, when a frame is dropped, the effect scenario processing (ST11), which includes the effect counter EN update processing, and the audio progression processing (ST12) are also skipped, so there is no risk of the start timing of the image effects, audio effects, lamp effects, and motor effects being shifted in the reach effects, preview effects, and gimmick effects that are started afterwards.

In other words, the performance scenario centrally manages the start timing of image performance, audio performance, lamp performance, and motor performance, as well as the performance content to be executed thereafter, and the start timing is controlled by the performance counter EN, which is updated only under normal circumstances, so that various performances will not become out of sync. For example, if there is a performance action that combines the sound of an explosion, an explosion image, the movement of a reel, and a lamp flash action, each of the above performance actions will start correctly and in sync, even after a frame drop occurs.

The above describes relatively minor abnormalities, but if the serious abnormality flag ABN is set, if there are many consecutive abnormalities (ER>2), or if an underrun abnormality occurs repeatedly, an infinite loop state is entered after the judgment in step ST10 (ST10b). As a result, the timing operation of the WDT circuit 58 progresses, and the composite chip 50 including the performance control CPU 63 is reset due to an abnormality, and then the initial processing (ST1-ST3) is re-executed, which is expected to eliminate the root cause of the abnormality.

This reset operation is performed by activating the WDT circuit 58, so the entire composite chip 50, including the CPU circuit 51, is reset (Figure 6 (b)). Therefore, in order to avoid resetting the CPU circuit 51, it is also preferable for the performance control CPU 63 to output a predetermined keyword string (e.g., three 1-byte data items) to the pattern check circuit CHK and output a reset signal RST to the VDP circuit 52 (see ST100 in Figure 34). In this case, too, after confirming that the reset operation of the VDP circuit 52 has been completed successfully (ST101), the process will move on to steps ST4 and ST13.

In any case, in the event of this abnormality, the sound circuit SND is also reset, so the image effects, sound effects, lamp effects, and motor effects are all returned to their initial states. However, these reset operations have no effect on the main control unit 21 or the payout control unit 25, so there is no risk of the jackpot state disappearing or the prize balls disappearing.

Although the above has been described as an abnormal situation, in reality, the above-mentioned abnormalities rarely occur, even if they are minor. After the processing of step ST5, the "display area" of frame buffers FBa and FBb that store image data to be read by display circuit 74A and display circuit 74B is toggled (ST6) based on the setting of a predetermined display register RGij (DSPACTL/DSPBCTL). As explained above, "display area (0)" and "display area (1)" are defined in advance in the initial processing (ST3), so in the processing of step ST6, it is determined whether the current "display area" for frame buffers FBa and FBb is display area (0) or display area (1).

By executing this step ST6, the display circuit 74A alternately reads out image data from the index space 254 (display area (0)) and the index space 255 (display area (1)) for each operation cycle δ to drive the display device DS1. Similarly, the display circuit 74B alternately reads out image data from the index space 251 (display area (0)) and the index space 252 (display area (1)) for each operation cycle δ to drive the sub-display device DS2. As explained above, the actual READ access by the display circuit 74 is limited to the valid data area in the display area (0)/display area (1).

In any case, in this embodiment, the "display area" switches for each operating cycle, so that the display circuits 74A and 74B start output processing to the display devices DS1 and DS2 for the image data that the drawing circuit 76 completed in the previous operating cycle. However, since the processing of step ST5 starts at the start of the vertical blanking period (V blank) of the main display device DS1, the output processing of the image data actually starts after the vertical blanking period is completed. In FIG. 28(a), the arrows shown in the display circuit column indicate the operating cycle of this output processing.

When the processing of step ST6, which has the above-mentioned significance, is completed, the performance control CPU 63 then completes a display list DL that specifies the image data that the display circuit 74 should output to the display device in the next operating cycle (ST7). Although not limited to this, in this embodiment, a list buffer area (DL buffer BUF) in RAM 59 is secured, and the display list DL is completed therein (see FIG. 12).

The display list DL is configured by listing a series of instruction commands in an appropriate order and is configured to end with an EODL (End Of DL) command. In this embodiment, in order to realize smooth operation of the data transfer circuit 72, the drawing circuit 76, and the preloader 73, all instruction commands including the EODL command are limited to only instruction commands whose command length is an integer multiple of 32 bits (N>0). As explained above, instruction commands consisting of an integer multiple of 32 bits may also include a don't care bit.

In this way, since the display list DL of the embodiment is composed only of instruction commands whose command length is an integer multiple of 32 bits (N>0), the data volume value (total amount of data) of the entire display list DL is always an integer multiple of the minimum unit of the command length (32 bits = 4 bytes). Furthermore, in this embodiment, taking into account the minimum data amount Dmin of the data transfer circuit 72, the data volume value of the display list DL is adjusted to be an integer multiple (1 or more) of the minimum data amount Dmin and also an integer multiple of the minimum unit of the instruction command (4 bytes). For example, if Dmin = 256 bytes, the data volume value of the display list DL is adjusted to one of the following values: 256 bytes, 512 bytes, etc.

It would be appropriate to adjust the value to 256 bytes or 512 bytes depending on the complexity of the presentation content, but in this embodiment, taking into consideration that there are two display devices and the sub-display device DS2 does not execute very complex image presentations, the data volume value of the display list DL is always adjusted to 256 bytes.

However, this method is not limited in any way, and in the case of three or more display devices, or in the case of a gaming machine that executes complex image effects including the sub-display device DS2, the data volume value is adjusted to 512 bytes or 768 bytes. Also, during normal effects, it is preferable to adjust the data volume value of the display list DL to 256 bytes, and only when a special effect is executed, to adjust the data volume value of the display list DL to 512 bytes or 768 bytes.

However, in this embodiment, the data volume value of the display list DL is adjusted to a predetermined byte length (256 bytes) in each operation cycle δ. The adjustment method can be a simple method (A) in which a 32-bit EODL command is followed by a 32-bit NOP (No Operation) command to fill in the missing area, or a standard method (B) in which the missing area is filled with a 32-bit NOP command and then a 32-bit EODL command is written at the end. In addition, a non-adjustment method (C) can be considered in which the data volume value (total amount of data) of the display list DL is terminated with an EODL command without any adjustment, and dummy data is additionally transferred during the operation of the data transfer circuit 72 to ensure a transfer amount that is an integer multiple of the minimum data amount Dmin.

If standard method (B) is adopted, the command counter CNT is initially set to a specified value (64-1 corresponding to 256 bytes), and the command counter CNT is appropriately decremented each time a significant command is written to the DL buffer area BUF. After a series of significant commands have been written, NOP commands are written until the command counter CNT reaches zero, and finally an EODL command is written. In this embodiment, the command length is limited to an integer multiple of 32 bits (N>0), so the above process is easy, and the decrement process of the command counter CNT corresponds to the integer N.

On the other hand, when the simplified method (A) is adopted, it is sufficient to fill the entire list buffer area (DL buffer BUF) with NOP commands at the beginning when creating the display list DL, so at first glance it appears to be superior to the standard method (B). Also, from the viewpoint of simplicity, the unadjusted method (C) also appears to be superior. However, this embodiment basically adopts the standard method (B), and adjusts so that the actual amount of data from the beginning of the display list DL to the EODL command, that is, the amount of data up to the EODL command, is always an integer multiple of the minimum data amount Dmin of the data transfer circuit 72.

This is because an embodiment utilizing the preloader 73 is taken into consideration, and if the simple method (A) or the adjustment-free method (C) is adopted, the actual data amount of the display list DL up to the EODL command becomes a random value, causing problems when the rewrite list DL' rewritten by the preloader 73 is transferred to the DRAM 54, and when the rewrite list DL' is transferred from the DRAM 54 to the drawing circuit 76. Note that when the rewrite list DL' is transferred to the DRAM 54, the ChA control circuit 72a of the data transfer circuit 72 functions, and when the rewrite list DL' is transferred to the drawing circuit 76, the ChB control circuit 72b functions (see FIG. 26), but in either case, only the rewrite list DL' up to the EODL command is transferred.

The above describes the advantages of the standard method (B) of adjusting the data volume value of the display list DL, but in an embodiment that does not use the preloader 73, the issued display list DL is simply processed by the drawing circuit 76, so there is no prohibition on using the simple method (A) or the adjustment-free method (C).

However, in the following explanation, we will assume that the standard method (B) is adopted in principle, regardless of whether or not the preloader 73 is used, and will explain the details of the display list DL based on Figure 21.

In this embodiment, although not limited to this, the display list DL first contains a sequence of instruction commands (L11-L16) for the main display device DS1, and then contains a sequence of instruction commands (L17-L20) for the sub-display device DS2. In addition, the standard method (B) is adopted to adjust the data volume value of the display list DL to a fixed length (256 bytes). Note that FIG. 21 also shows, in effect, the procedure by which the performance control CPU 63 writes instruction commands into the list buffer area of the RAM 59, and the operation of the drawing circuit 76 based on the display list DL.

As shown in FIG. 21, at the beginning of the display list DL, an environment setting command (SETDAVR) is written to specify the upper left base address (X, Y) in the index space IDX for the frame buffer FBa of the display device DS1 (L11). As explained with reference to FIG. 11(a), in this embodiment, a pair of frame buffers FBa is reserved in the arbitrary area (c) for the display device DS1. Then, normally, the base address (X, Y) = (0, 0) is set to correspond to the valid data area for the display circuit 74, and the frame buffer FBa is used by the drawing circuit 76 from its beginning position.

In Figure 11(c), the actual drawing area on the lower left is labeled L11, which means that the instruction command L11 has specified that the actual drawing area on frame buffer FBa begins at the base address (0,0) of frame buffer FBa. However, the vertical and horizontal dimensions of the actual drawing area and the index number that specifically specifies this actual drawing area have not yet been determined, and will be determined by instruction command (SETINDEX) L13, which will be described later. Note that instruction command L11 also specifies whether or not to use the Z buffer.

Next, the environment setting command (SETDAVF) is used to set the upper left base point coordinates (Xs, Ys) and the lower right diagonal point coordinates (Xe, Ye) in the virtual drawing space, defining a drawing area with dimensions W x H (L12). Here, the virtual drawing space is a virtual two-dimensional space of ±8192 in the X direction and ±8192 in the Y direction that can be drawn using drawing command commands (such as the SPRITE command) (see Figure 11(c)).

This instruction command L12 (SETDAVF) divides the virtual drawing space into a drawing area where the drawing contents are actually reflected on the display device DS1, and the other non-drawing area. Furthermore, instruction command L12 (SETDAVF) associates the actual drawing area, whose start position (base address) is specified by instruction command L11, with the drawing area in the virtual drawing space.

In other words, the instruction command L12 defines an actual drawing area of W x H starting from the base address in the frame buffer FBa (with the index space undefined), which corresponds to the drawing area in the virtual drawing space. Therefore, the drawing area specified by the instruction command L12 must be the same as or smaller than the horizontal size of the frame buffer FBa. Normally, the drawing area and actual drawing area are defined to be the same dimensions as the effective data area (Figure 20 (e)) for the display circuit 74.

After the drawing circuit 76 executes the instruction commands L11 and L12, only the drawing contents drawn in the virtual drawing space that are included in the drawing area are reflected in the actual drawing area of the frame buffer FBa. Therefore, the drawing contents that extend beyond the drawing area or the part marked as the working area in Figure 11 (c) are not reflected in the frame buffer as is. Note that when reserving a working area in the virtual drawing space, the non-drawing area of the virtual drawing space is used.

Next, in the current operation cycle, the drawing circuit 76 specifies where to draw the drawing contents based on the display list DL to be completed (L13). Specifically, for the frame buffer FBa of the display device DS1 with a double buffer configuration, the index space IDX that will be the "write area" of the drawing contents based on the current display list DL is specified (L13). Specifically, the SETINDEX command, which is a texture setting command, specifies (1) that the frame buffer FBa is secured in an arbitrary area, and (2) the index number N in the arbitrary area of the index space IDX _N that will be the "write area".

If, for example, N=255 is specified by this instruction command L13, the actual drawing area corresponding to the drawing area defined in the virtual drawing space is specifically defined as the index space IDX ₂₅₅ in the frame buffer FBa having a double buffer structure.

In this embodiment, the index number of the frame buffer FBa is 255 or 254 (FIG. 11(a)), and either one is designated by toggling (L13). Note that this index number is the index number of the display area other than (0)/(1) designated in step ST6 of the main control process. For example, in the process of step ST6, if display area (0) is designated for the display circuit 74, display area (1) becomes the "write area" for the drawing circuit 76.

As described above, the correspondence between the actual drawing area (logical space of W x H) and the drawing area (virtual space of W x H) is generally defined by instruction command L11 and instruction command L12, and then the virtual space of W x H is associated with the logical space of W x H in the specific index space IDX by instruction command L13 (SETINDEX), which specifically specifies the index space IDX.

In other words, from now on, the content that is virtually drawn in the W x H virtual space based on a series of instruction commands will become image data in the built-in VRAM 71 (frame buffer) based on a conversion table inside the VDP that defines the correspondence between the virtual space and the real addresses of the built-in VRAM 71.

Next, an instruction command is written to execute a frame buffer clear process that fills the specified index space IDX as the "write area" with, for example, black (L14, L15). This is nothing more than a process to erase the image data that was written to the frame buffer FBa two operation periods ago.

Specifically, the color black is selected using the SETFCOLOR command, which is a type of environment setting command, and the RECTANGLE command, which is a primitive drawing command, is used to specify that a rectangular area should be filled. Note that the RECTANGLE command specifies the XY coordinates of the upper left corner and lower right corner of the drawing area (the virtual space corresponding to the frame buffer FBa) set in the virtual drawing space (see Figure 11 (c)).

The above process completes the preparation for rendering, so next, command instructions are listed for rendering an appropriate texture, such as a still image or a single frame of video, in the virtual rendering space. Typically, the index space IDX into which the texture will be deployed is specified using a texture setting command, and then a texture load command, the TXLOAD command, is written to enter a specific texture read from CGROM 55 in the display list DL to be deployed in the specific index space IDX.

As explained above, in this embodiment, the background video is composed of IP stream video. Therefore, for example, the index space IDX into which the background video should be expanded is specified as index space IDX ₀ of page area (b) by the texture setting SETINDEX command, and then the texture load TXLOAD command is written. Note that the TXLOAD command needs to specify the top address of the CGROM 55 (texture source address) and the expanded data size (horizontal x vertical) for the video frame to be loaded this time.

When the VDP circuit 52 executes the TXLOAD command, one video frame (texture) of the background video is first acquired in the AAC area (a), and then the GDEC 75, which starts automatically, expands it into the index space IDX ₀ of the page area (b). Next, this one video frame is drawn in the virtual drawing space. In this case, the SETINDEX command (texture setting system) may be set so that "the index space IDX ₀ of the page area (b) is the texture to be processed thereafter," but if processing is to be performed immediately after the TXLOAD command, the description of this SETINDEX command may be omitted.

In any case, in the state where "index space IDX ₀ of page area (b) is specified as the texture to be processed thereafter," next, an appropriate inter-drawing calculation instruction command is written, such as setting parameters for alpha blending. Note that alpha blending is a process for making the image already written in the drawing area (frame buffer FBa) transparent/semi-transparent with the image to be overwritten. Therefore, in the first drawing operation, such as the video frame of the background video, it is not necessary to use an inter-drawing calculation instruction command.

Next, a SPRITE command, which is a primitive rendering instruction command, is written to render the "texture of index space IDX ₀ in page area (b) (one video frame of the background video)" in the appropriate location (rectangular destination area) in the virtual rendering space. Note that the SPRITE command requires that the upper left corner and lower right corner of the destination area in the virtual rendering space be specified.

This destination area is the entire drawing area (virtual space defined on the virtual drawing space) that has been associated in advance with the actual drawing area (FBa) by instruction commands L11 and L12, or a portion of it. However, since the background video is usually drawn on the entire display screen, the destination area in such a case is the entire drawing area or larger. Note that a destination area that is larger than the entire drawing area would be, for example, when the background video is zoomed in.

The above process has completed the drawing of the video frames of the background video, so next, command commands such as texture load, texture setting, inter-drawing calculation, and primitive drawing commands are listed in an appropriate order and overlaid on the background video to construct a display list DL for drawing various textures. As explained above, a large number of videos are required for variable effects, so in that case, an index table control command (NEWPIX) is written to increase the index space IDX for the page area (b) of the built-in VRAM 71.

For example, for the second IP stream video, an additional index space _IDX1 is reserved in the page area (b) by the NEWPIX command, and then this index space _IDX1 is specified (SETINDEX), a command is issued to render one frame of the second video (TXLOAD), and the rendered texture is placed in an appropriate location in the rendering area (SPRITE). Normally, the destination area in this case is part of the rendering area.

The same applies below, and after the index space IDX _k is secured one after another by the NEWPIX command, appropriate alpha blending is performed while drawing multiple IP streams in the drawing area, and the contents drawn in the drawing area are sequentially stored as image data in the frame buffer FBa, which is the actual drawing area. When multiple N IP stream videos are drawn, multiple N index spaces are functioning in the page area (b).

Then, when a series of variable presentations has ended, in order to release the index spaces IDX that are deemed unnecessary among the many index spaces IDX ₁ to IDX _k secured in the page area (b), the unnecessary index spaces IDX can be deleted by the DELPIX command.

When drawing still images or I-stream videos, if you specify with the SETINDEX command that the AAC area (a) is to be the decoded destination for these textures and then execute the TXLOAD command, the texture acquired in the AAC area (a) will then be expanded in the ACC area (a) by the automatically started GDEC75. The expanded texture can then be drawn in the appropriate location in the drawing area with the SPRITE command. Depending on whether or not the cache hit function is used, either the first AAC area (a1) or the second AAC area (a2) will be used.

In the explanation so far, each texture is drawn directly in the drawing area of the main display device DS1, but this is not necessarily the only way to do it. For example, if an appropriate drawing area is provided (Figure 11(c)) that does not overlap with the drawing area already reserved for the display device DS1, and this drawing area is associated with the working area of the built-in VRAM 71, an intermediate drawing area can be constructed and an appropriate performance image can be completed. The reason for not overlapping with the drawing area for the display device DS1 here is that for overlapping areas, the later association setting takes priority, and the drawing contents in that area are not reflected in the frame buffer FBa.

As shown in Fig. 11(c), the working area in this embodiment is the index space IDX ₀ in the arbitrary area (c). Then, at the performance timing when this working area is used, a command sequence (SETDAVR, SETDAVF, SETINDEX) is written in advance to associate the rendering area for the performance image (see Fig. 11(c)) with the working area (the actual rendering area of the index space IDX ₀ ). As shown in Fig. 11(c), the rendering area for the performance image is secured in an area not included in the rendering area for the main display device DS1.

Then, by listing command sequences similar to the command sequence L16 for the frame buffer FBa, an appropriate effect image can be completed in the index space IDX _0. In the case of this embodiment, since the effect image is composed of a still image, a command (SETINDEX) is written to cause the decoded data to be expanded in the first AAC area (a1), and then a primitive drawing command (SPRITE) is used with an appropriate location in the drawing area of the index space IDX ₀ as the Destination. This operation is repeated once or multiple times depending on the effect content.

Then, after positioning the index space IDX ₀ in which the performance image has been completed as a texture (SETINDEX), the performance image (texture) of the index space IDX ₀ can be drawn in an appropriate location in the drawing area of the main display device DS 1 by the SPRITE command. In such a case, it is conceivable that the performance image of the index space IDX ₀ is decomposed into triangular drawing primitives, rotated at an appropriate angle, and then drawn in the drawing area. The rotation angle of the texture is associated with, for example, the reliability of the preview performance.

The above describes the instruction command sequence (L11 to L16) for completing one frame on the main display device DS1, but the same is true for the instruction command sequence (L17 to L12) for completing one frame on the sub-display device DS2. That is, the starting XY coordinates of the frame buffer FBb are specified (L17) and defined (usually X=0, Y=0), and the drawing area for the sub-display device DS2 is defined in the virtual drawing space shown in FIG. 11(c) (L18).

In this embodiment, after the generation of image data for the main display device DS1 is completed, the process moves to the generation process for the sub-display device DS2. Therefore, even if the drawing area for the sub-display device DS2 overlaps with the drawing area for the main display device DS1, there is no problem and the drawing area can be set freely. Therefore, when developing a generation program for a display list DL, for example, when using a SPRITE command to paste an appropriate texture into a newly set drawing area, the settings of the operation parameters (Destination area) of the SPRITE command and other settings can be standardized to a certain extent.

Once this arbitrary drawing area has been defined (L18), the index space IDX that will be the "write area" for the drawing contents based on the current display list DL is identified for the frame buffer FBb of the double-buffered display device DS2 (L19). The index number of this index space IDX is the index number for the frame buffer FBb that does not correspond to the display area (0)/(1) specified in step ST6 of the main control process.

Then, the instruction command sequence L20 to L22 for the sub-display device DS2 is listed in the same manner as the instruction command sequence L14 to L16 for the main display device DS1. Also, the completed performance image can be used in the index space _IDX0 .

As described above, in this embodiment, the command lengths of all of the instruction commands L11 to L22 that make up the display list DL are limited to integer multiples of 32 bits. As explained above, the data volume value (total amount of data) of the display list DL in this embodiment is adjusted to a fixed length (256 bytes), and the necessary number of NOP commands (L23) are added as dummy commands, before terminating with the EODL command (L24). In other words, the embodiment in Figure 21 employs the standard method (B) described above.

However, even when standard method (B) is used, it is not necessarily required to fix the total amount of data in the display list DL to 256 bytes in all operation cycles. That is, in another embodiment, when the total amount of data in the display list DL excluding NOP commands exceeds 256 bytes (for example, during a special performance period), the total amount of data in the display list DL is adjusted to 512 bytes or more, that is, N x 256 bytes, by adding NOP commands. As explained above, when standard method (B) is used, the end of the N x 256 bytes is terminated with an EODL command.

The configuration of the display list DL has been explained in detail above, but the performance control CPU 63 issues the completed display list DL of fixed byte length to the VDP circuit (ST7 to ST8). Figure 22 is a flowchart explaining the DL issuing process (ST8 in Figure 20) in which the performance control CPU 63 directly WRITE accesses the transfer port register TR_PORT of the transfer circuit 72 and issues a display list DL to the drawing circuit 76. The transfer port register TR_PORT is a type of data transfer register RGij that specifies the operation content of the data transfer circuit 72.

To realize the DL issuing process, first, it is necessary to set the necessary setting values in the multiple data transfer registers RGij that define the operation contents of the data transfer circuit 72. Specifically, the transfer operation mode of the data transfer circuit 72 and the transmission route inside the data transfer circuit 72 are specified in a predetermined data transfer register RGij. The setting contents are not particularly limited, but here, it is set that the data is transferred from the CPUIF unit 56 via the ChB control circuit 72b, and that the data transfer operation is performed while checking the remaining capacity of the FIFO buffer of the CPU bus control unit 72d (ST20). In the following description, the ChB control circuit 72b may be abbreviated as "transfer circuit ChB" for convenience.

Next, the total transfer size is set in a specified data transfer register RGij. As explained above, in this embodiment, the total amount of data in the display list DL is adjusted to an integer multiple of 256 bytes, so that value is set. Note that the total amount of data = 256 x N is also an integer multiple N of the minimum data amount Dmin of the data transfer circuit 72. Normally, the multiple N is 1 or 2, but in the following explanation, N = 1 will be used.

Here, since the transfer port register TR_PORT (hereafter sometimes abbreviated as transfer port) is a 32-bit register, the performance control CPU 63 executes a register WRITE operation on the transfer port TR_PORT for every 32 bits. Therefore, the value of the management counter CN, which manages the number of register WRITEs, is initially set to 64 (ST21). Note that if the non-adjustment method (C) is adopted, at this timing, the data transfer amount that is an integer multiple of the minimum data amount Dmin is determined and the management counter CN is set.

The above process completes the initial settings, and next, data transfer operation via the transfer circuit ChB is set to the start state (ST22), and drawing operation is started based on the set value of a specific drawing register RGij that specifies the operation of the drawing circuit 76 (ST23). As a result, the performance control CPU 63 then ensures that the drawing circuit 76 (display list analyzer) can perform a quick and smooth analysis process on the instruction command sequence that the performance control CPU 63 writes to the transfer port TR_PORT.

Note that the fact that the command lengths listed in the display list DL are limited to those that are integer multiples of 32 bits also contributes effectively to a fast and smooth analyze process. Timings t1, t2, t3, and t4 in FIG. 28(a) indicate the operation timing of step ST23. Note that since the display list DL issuance process (ST8) is completed quickly, the time required for the issuance process is not shown in FIGS. 28 and 29.

Next, it is confirmed whether the settings in step ST22 have worked (ST24). This is because the initial settings of each part of the data transfer circuit 72 take longer to process than the register WRITE operation (setting operation) by the performance control CPU 63, so no further instructions are given to the data transfer circuit 72 in an incomplete state. Then, in the unlikely event that the circuit does not enter an operational start state even after waiting for a predetermined period of time, the serious abnormality flag ABN is set and the DL issuance process is terminated (ST25). As a result, the WDT circuit 58 then functions and the composite chip 50 is abnormally reset (ST10).

As mentioned above, the performance control CPU 63 may output a predetermined keyword sequence to the pattern check circuit CHK to abnormally reset only the VDP circuit 52 based on the reset signal RST in order to avoid resetting the CPU circuit 51.

However, since the setting in step ST22 is usually completed quickly, the CPU bus control unit 72d next checks to see if the FIFO buffer (32 bits x 130 stages) is full (ST26), and then writes instruction commands to the transfer port TR_PORT for each line in the display list DL, starting from the first line (ST28).

Then, while decrementing the management counter CN (ST29), the processing of steps ST26 to ST29 is repeated until the management counter CN becomes zero (ST30). In this embodiment, since a minimum data amount Dmin is specified for the data transfer circuit 72, the data transfer operation is executed when the minimum data amount Dmin is accumulated in the FIFO buffer, resulting in an intermittent transfer operation.

In any case, in this embodiment, the DL issuance process (ST28) is completed quickly, but in the unlikely event that the settings in the VDP register RGij become inconsistent due to the effects of noise or the like, it is possible that the FIFO buffer full state will not be resolved even after waiting for a specified time in the judgment of step ST26. In such a case, initialization data is set in a specified VDP register RGij, the drawing circuit 76 and data transfer circuit 72 are initialized, and the serious abnormality flag ABN is set to end the DL issuance process (ST27).

By the way, at this timing, the data transfer circuit 72 and the drawing circuit 76 have already started operating and completed a certain amount of processing, so the initialization process of the drawing circuit 76 includes (1) setting all internal parameters that may be set by the display list DL to their initial values, (2) setting all internal control circuits to their initial states, (3) initializing the GDEC 75, and (4) initializing the cache state of the AAC area, while maintaining the contents of the drawing register RGij. Similarly, the initialization process of the data transfer circuit 72 includes initialization of the entire data transfer up to that point, such as clearing the FIFO buffer. As a result, the status information indicating the operating state of the data transfer circuit 72 changes to a predetermined value (a value indicating that the entire data transfer is being initialized).

In the initialization process of step ST27 described above, the contents of the drawing register RGij are maintained, but the contents of certain drawing registers may be initialized. The certain drawing registers that are cleared to their initial values include (a) an execution control register (see ST23 in FIG. 22) that sets the start of drawing execution, (b) a status register that indicates the execution status of the drawing circuit 76, and (c) a status register that specifies the position of the display list currently being processed.

In any case, as a result of setting the serious abnormality flag ABN, the WDT circuit 58 and the performance control CPU 63 then function and the composite chip 50 or the VDP circuit 52 undergoes an abnormal reset (ST10a), so the process of initializing the drawing circuit 76 and the data transfer circuit 72 is not necessarily required. On the other hand, if the drawing circuit 76 and the data transfer circuit 72 are initialized, it is expected that the result will be a recovery from the abnormality, so it is also preferable to return to the process of step ST20 and re-execute the DL issuance process without setting the serious abnormality flag ABN.

The same applies to the processing of step ST25, and it is preferable to initialize the data transfer circuit 72 and drawing circuit 76, and then return to the processing of step ST20 without setting the serious abnormality flag ABN. In such a case, however, the number of times the DL issuance process is retried is counted, and if the number of retries exceeds a limit value, the serious abnormality flag ABN is set and the DL issuance process is terminated.

Figure 22 (b) is a confirmation diagram of a normal operating state. As shown in the figure, the issued display list DL is analyzed by the drawing circuit 76 (display list analyzer) in the order of the command commands listed, and operations based on each command are executed. This operation is executed in parallel with the process of issuing the display list DL and the data transfer operation (ST26 to ST30) of the data transfer circuit 72.

For example, when the instruction command (TXLOAD) is executed, the necessary texture is read from the CGROM 55 and acquired in the AAC area (a), after which the GDEC 75 is automatically started and a decoding operation is performed, and the decoded data is expanded in a specified index space. Also, depending on the instruction command, the geometry engine 77 and others function, but in any case, the various parts of the drawing circuit 76 work together to complete the image data corresponding to the display list DL in the frame buffers FBa and FBb.

Next, a case where a display list DL is issued via the DMAC circuit 60 will be described with reference to FIG. 23. Although not limited in any way, the third DMA channel will be used among the first to fourth DMA channels built into the DMAC circuit 60.

In the embodiment of FIG. 23, first, a clear value is set to a specific data transfer register RGij and a specific drawing register RGij, respectively, to initialize the data transfer circuit 72 and drawing circuit 76 (ST20). This process is the same as the error processing in step ST27 of FIG. 22, and the internal circuitry of the data transfer circuit 72 including the FIFO buffer is initialized, the status bit of the data transfer register indicating the progress of the data transfer is set to the initial value, and the bit indicating that the entire data transfer is being initialized is set to a specific value.

The same applies to the drawing circuit 76, and includes the above-mentioned (1) setting the internal parameters to initial values, (2) setting the internal control circuit to an initial state, (3) initializing the GDEC 75, and (4) initializing the cache state of the AAC area. Also, in the initialization process of the drawing circuit (ST20 in FIG. 23), the above-mentioned predetermined drawing register RGij may also be initialized. Note that such initialization process may be executed first in the process of FIG. 22.

In the process of FIG. 23, the system then reads a specific status register RGij that specifies the operating state of the data transfer circuit 72 and the drawing circuit 76 to confirm that the initialization process has been completed successfully (ST21). If the initialization is not successful, the system sets a serious abnormality flag ABN and ends the process (ST22). However, this situation almost never actually occurs.

Next, the transfer operation mode of the data transfer circuit 72 and the transmission route within the data transfer circuit 72 are set in a specified data transfer register RGij. The setting contents are not particularly limited, but here, it is set to pass from the CPUIF unit 56 through the ChB control circuit 72b, and the transfer protocol to the CPU bus control unit 72d follows the setting in the DMAC circuit 60 (ST23).

Next, the total transfer size is set in a specified data transfer register RGij. As in the case of FIG. 22, the total amount of data = 256. If the non-adjustment method (C) is used, the total transfer size is determined and set at this timing as an integer multiple of the minimum data amount Dmin. Next, the drawing operation of the drawing circuit 76 is started based on the setting value in the specified drawing register RGij (ST25). The timings t1, t2, t3, and t4 in FIG. 28(a) are also the operation timings of step ST25. Next, the operation of the DMAC circuit 60 is started (ST26), and then the data transfer operation of the data transfer circuit 72 is started (ST27).

The process for starting the operation of the DMAC circuit 60 is as shown in FIG. 23(b), and first, with DMAC transfers prohibited, the process waits for the transfer of one cycle of data transfer units (one operand) to be completed (ST40). The detailed operation is the same as the process shown in FIG. 24, and is divided into a process for setting DMAC transfers to be prohibited (ST53) and a subsequent wait process (ST54).

The reason for providing such processing is that (1) in other embodiments, the DMAC circuit 60 (third DMA channel) may be used in the main control processing or timer interrupt processing (FIG. 20), and (2) in other embodiments that do not provide the processing of step ST5 in FIG. 20, the DMAC circuit 60 that has started issuing a display list DL may not be able to finish the DL issuing operation within its operating period (δ).

In the above-mentioned exceptional situation, if new setting values (such as contradictory setting values) are additionally set to the operating DMAC circuit 60, normal DMA operation is not guaranteed at all, and serious trouble is a concern, but by providing the processing of step ST40, normal operation based on the subsequent setting values is guaranteed. In other words, even in a modified embodiment that is a partial modification of this embodiment, normal subsequent DMA operation can be achieved regardless of the preceding trouble.

After executing the processing of step ST40 having the above significance, the operating conditions of the DMAC circuit 60 are set (ST41). Specifically, as shown in FIG. 8, the cycle steal transfer mode is selected, and one operand transfer is set to 32-bit transfer x 2 times. In addition, it is specified that the source address is an address of the list buffer area (DL buffer BUF) of RAM 59 and should be recognized as sequentially increasing, while the destination address is the transfer port TR_PORT and should be a fixed value.

Next, the top address of the DL buffer BUF in RAM 59 is set in a predetermined operation control register REG that specifies the operation of the DMAC circuit 60 (ST42), and the address of the transfer port TR_PORT, which is the transfer destination address, is set (ST43). In addition, the total transfer size, that is, the total amount of data in the display list DL, is set to 256 bytes (ST44), and the DMA operation of the DMAC circuit 60 is started (ST45).

The explanation so far has been based on the assumption that the effective bit length of the instruction commands is an integer multiple of 32 bits. However, the configuration of the display list DL and instruction commands is not necessarily limited, so the following explanation will focus on such a case.

For example, including the case where the non-adjustment method (C) described above is used, if the total data amount X of the display list DL is an arbitrary value X that is not an integer multiple of 32 bits, in the processing of step ST44, this arbitrary value X is adjusted to an appropriate transfer amount MOD, and then the processing for setting the total transfer size is executed. Here, the appropriate transfer amount MOD is determined based on the setting contents for one operand transfer and the minimum data amount Dmin (bytes) of the data transfer circuit 72.

Specifically, if the one-operand transfer setting is N bytes x M times, the transfer amount MOD is adjusted to a value that is an integer multiple of N x M (bytes) and also an integer multiple of Dmin (bytes). For example, if N x M = 8 x 4 and Dmin = 256, the arbitrary value X (= 300) bytes is adjusted to the transfer amount MOD (= 512) bytes.

As explained above, including general theory, the DMA operation of the DMAC circuit 60 starts with a cycle steal transfer operation as shown in FIG. 8, and the display list DL is transferred to the transfer port TR_PORT in units of 32 bits in this embodiment, without interfering with the operation of the CPU. The transferred data is then transferred to the drawing circuit 76 via the transfer circuit ChB.

To achieve this operation, in this embodiment, following the processing of step ST45, the data transfer circuit 72 starts its transfer operation and ends the processing (ST27). The data transfer circuit 72 then receives a series of instruction commands for the display list DL from the DMAC circuit 60, with the minimum data amount Dmin as one unit, and transfers this to the drawing circuit 76. The drawing circuit 76 then executes drawing operations based on the instruction commands in the display list DL. Therefore, after the processing of step ST27, the performance control CPU 63 can start the processing of step ST11 in FIG. 20, and can control sound performances, lamp performances, and motor performances in parallel with the drawing operation by the VDP circuit 52 (DL issuance processing by the DMAC circuit 60).

Figure 23(c) illustrates this operation. Prior to the DMA transfer, the drawing circuit starts operating (ST25), and the display list analyzer of the drawing circuit 76 performs the analysis process quickly and smoothly. Based on the operations of the GDEC 75 and the geometry engine 77, one frame's worth of image data is generated in the frame buffers FBa and FBb for each of the display devices DS1 and DS2.

However, the configuration of FIG. 23, in which the DL issuance process ends with the process of step ST27, is not necessarily limited. For example, as in FIG. 30 to FIG. 31, when the audio effects, lamp effects, and motor effects are controlled by another CPU, it is preferable to check the normal operation of the DMAC circuit 60 and data transfer circuit 72 after the process of step ST27. FIG. 24 is a flowchart explaining the process of checking normal operation, which is the operation following step ST27 in FIG. 23.

First, a specific status register is referenced to confirm that the transfer operation of the DMAC circuit 60 has been completed normally (ST50). Also, it is confirmed that the data transfer circuit 72 has completed the transfer operation (ST51). Normally, the DL issuance process in FIG. 23 is completed through this process.

On the other hand, if the operation of the DMAC circuit 60 is not completed even after waiting for a predetermined time, or if the data transfer circuit 72 has not completed its transfer operation, a clear value is set in a predetermined VDP register RGij for the drawing circuit 76 and the data transfer circuit 72, and the DL issuance process is initialized (ST52). This is an operation based on the fact that the display list DL issuance process has not ended normally, and specifically, it is the same as the error process in step ST27 in FIG. 22 and the initial process in step ST20 in FIG. 23.

In other words, in this case too, the drawing circuit 76 has already started operating and has already completed a certain amount of processing, so the initialization process of the drawing circuit 76 includes (1) setting all internal parameters that may be set by the display list DL to their initial values, (2) setting all internal control circuits to their initial states, (3) initializing the GDEC 75, and (4) initializing the cache state of the AAC area.

Next, new DMA transfer operations are prohibited (ST53), and the process waits for the transfer operation of one operand that is currently being performed to finish (ST54). As explained above, in this embodiment, one operand is a 32-bit transfer x 2 times, and this is to avoid abruptly initializing the DMAC circuit 60 that is currently in operation.

Once this preparation work is complete, a clear value is set in a specific operation control register REG that specifies the operation of the DMAC circuit 60, and the DMAC circuit 60 is initialized (ST52). The serious abnormality flag ABN is then set and the DL issuance process is terminated. In this case, since the abnormality can be expected to be recovered from by the processing of steps ST52 and ST55, it is also preferable to return to step ST20 in FIG. 23 and re-execute the DL issuance process without setting the serious abnormality flag ABN. However, it is necessary to count the number of re-executions of the DL issuance process (ST23 to ST27), and if the number of re-executions exceeds a limit value, to set the serious abnormality flag ABN and terminate the DL issuance process.

Next, the main control process when the preloader 73 is used will be described with reference to FIG. 25. The process in FIG. 25 is similar to the process in FIG. 20, but first the content of the start condition determination (ST5') is different. That is, in an embodiment using a preloader, at the start of each operation cycle, status information of the drawing circuit 76 and the preloader 73 is read and accessed to confirm that the drawing operation based on the display list DL1 has ended, and that the preload operation based on the display list DL2 has ended (ST5').

As shown in the time chart of FIG. 29(a), the preloader 76 should have completed the preload operation during an operation cycle (T1) (T1 to T1+δ) based on the display list DL1 issued during that operation cycle. The drawing circuit 76 should have completed the drawing operation during that operation cycle (T1+δ to T1+2δ) based on the operation start command issued during that operation cycle (T1+δ).

Therefore, in (ST5'), the status information of the VDP register RGij related to the drawing circuit 76 and the preloader 73 is read and accessed to confirm the above-mentioned normal operation. In FIG. 29(a), normal operation is confirmed at the judgment timings of the operation cycles T1, T1+δ, T1+2δ, and T1+4δ, but at the judgment timing of the operation cycle T1+3δ, the preload operation is not completed.

In the event of such an abnormality, the abnormality flag ER is incremented (ER = ER + 1) and the process proceeds to step ST9. Therefore, as in the embodiment of FIG. 20, a frame is dropped. In other words, the display area switching process (ST6) is skipped, and the same screen is redisplayed. The operating period (T1 + 3δ to T1 + 4δ) shown in FIG. 28(a) shows this operating state.

If the start condition is not satisfied in the determination of step ST5', the drawing circuit 76 is not instructed to start the drawing operation (PT10) based on the rewrite list DL', so the drawing circuit 76 is in a non-operating state and a new display list is not generated. In FIG. 29(a), timings t0, t2, and t4 indicate the operation timing of the drawing operation start instruction (PT10), or more precisely, the timing of step ST26 in FIG. 26.

The above describes the case where the judgment in step ST5' is non-compliant, but in the normal case, after toggling between the display areas of the frame buffers FBa and FBb (ST6), the drawing circuit 76 is made to start drawing operations based on the rewrite list DL' (PT10). The specific contents are as shown in FIG. 26, and under the control of the performance control CPU 63, the drawing circuit 76 obtains the rewrite list DL' from the DL buffer BUF' in the external DRAM 54 via the data transfer circuit 72 (transfer circuit ChB) and executes the drawing operation.

Prior to explaining the flowchart in Figure 26 which realizes this operation, let us check the operation of the preloader 73. The preloader 73 has completed the look-ahead operation (preload) of the CGROM 55 based on the display list DL acquired one operation cycle ago, and the look-ahead data has already been stored in the preload area secured in the external DRAM 54. In addition, for the texture load command (TXLOAD) written in the display list DL, its source address is rewritten to an address in the preload area, and is stored in the DL buffer BUF' of the external DRAM 54 as a rewrite list DL'.

In addition, in this rewrite process, the total amount of data in the display list DL does not change, and the total amount of data in the rewrite list DL' is the same as that of the display list DL. In addition, the display list DL is created using the standard method (B), and the end of the rewrite list DL' is an EODL command, just like in the case of the display list DL.

With the above in mind, referring to FIG. 26, the performance control CPU 63 first sets a clear value to a specified data transfer register RGij and a specified drawing register RGij, respectively, to initialize the data transfer circuit 72 and the drawing circuit 76 (ST20). This process is the same as the process of ST20 in FIG. 23. Next, it is confirmed that this initialization process has ended normally (ST21), and in the unlikely event that the initialization is not completed after a specified time has elapsed, the major abnormality flag ABN is set and the process ends (ST22).

Normally, the initialization of the data transfer circuit 72 and drawing circuit 76 ends normally, so the transmission route within the data transfer circuit 72 is then set to a specified data transfer register RGij (ST23). Specifically, it is set to transfer data from the external DRAM 54 to the drawing circuit 76 via the ChB control circuit 72b (ST23). Next, the top address of the DL buffer BUF' in the external DRAM 54, in which the rewrite list DL' is stored, is set to the specified data transfer register RGij (ST24).

The total transfer size of this rewrite list DL' is also set in a predetermined data transfer register RGij (ST25). As explained above, the total amount of data in the rewrite list DL' is the same as the total amount of data in the display list DL, and is, for example, 256 bytes.

Next, the drawing operation of the drawing circuit 76 is started based on the set value of a specified drawing register RGij (ST26). Timings t1, t2, t3, and t4 in FIG. 28(a) are also the operation timings of step ST26. Next, the operation of the data transfer circuit 60 is started based on the set value of a specified data transfer register RGij, and the process ends (ST27). After that, the performance control CPU 63 is not particularly involved in the operation of the data transfer circuit 72 or the drawing circuit, and proceeds to the process of generating a display list (ST7) that will be executed in the next operating cycle.

Meanwhile, the drawing circuit 76, which starts operating at the timing of step ST26, executes drawing operations based on the rewrite list DL' and generates image data based on the rewrite list DL' in the frame buffers FBa and FBb. Note that in this operation, the drawing circuit 76 does not perform a READ access to the CGROM 55, but only performs a READ access to the preload area, so that a series of drawing operations can be completed quickly.

Having explained the processing contents of step PT10 above, let us return to FIG. 25 to continue the explanation. After the processing of step PT11, in an embodiment that utilizes the preloader 73, a display list DL to be executed in the next cycle is created based on the standard method (B) (ST7). For example, in the operation cycle (T1) shown in FIG. 29(a), a display list DL to be referenced by the drawing circuit 76 is created in the operation cycle (T1+δ), which is the next cycle.

Next, the performance control CPU 63 issues the created display list DL to the preloader 73, not to the drawing circuit 76 (PT11). The specific operation is as shown in FIG. 27. Previously, in the embodiment (FIG. 20) in which the preloader 73 is not used, the performance control CPU 63 has been shown issuing the display list DL directly to the drawing circuit 76 (FIG. 22) and via the DMAC circuit 60 (FIG. 23). In FIG. 27, almost the same operation is shown in FIG. 27(b) and FIG. 27(c), except that the issuing destination is the preloader 73.

Figure 27(a) is a flowchart explaining the operation of Figure 27(b), and is almost the same as the flowchart of Figure 22. However, it is set so that data is transferred from the CPUIF unit 56 via the ChC control circuit 72c, and the data transfer operation is performed while checking the remaining capacity of the FIFO buffer of the CPU bus control unit 72d (ST20). In the following description, the ChC control circuit 72c may be abbreviated to "transfer circuit ChC" for convenience.

Next, the total transfer size (for example, 256 bytes adjusted using the standard method (B)) is set in a specified data transfer register RGij, and the management counter CN is initialized to 64 (ST21). Next, the data transfer operation via the transfer circuit ChC is set to a start state (ST22), and the preload operation is started based on the setting value in the preload register RGij that specifies the operation of the preloader 73 (ST23).

As a result, the preloader 73 subsequently executes the necessary analysis (Analyze) process for each instruction command that the performance control CPU 63 writes to the transfer port TR_PORT, and when it detects an instruction command (TXLOAD) that requires READ access to the CGROM 55, it preloads the texture and saves it in the preload area of the DRAM 54. It also saves the rewrite list DL' with the changed texture source address in the DL buffer area BUF' of the DRAM 54.

Note that timings t1, t3, and t5 in FIG. 29(a) actually indicate the operation timing of step ST23 in FIG. 27. However, even in this embodiment, if any abnormality occurs during the process of issuing the display list DL, the processes of steps ST25 and ST27 are executed. Specifically, the operation of the data transfer circuit 72 and the preloader 73 are initialized, and the process of issuing the display list DL (ST20 to ST30) is executed again to the extent possible. The initialization process of the preloader 73 includes erasing the incomplete rewrite list DL' and clearing the preload area in which new preload data has been stored.

The above provides a detailed explanation of the cases where the preloader 73 is used and where it is not used, but the specific operation is not particularly limited. Figure 28(b) shows an embodiment in which the display list generated by the performance control CPU 63 is issued to the drawing circuit 76 with a delay of one operation cycle δ, rather than the same operation cycle in which it was generated. In such an embodiment, the drawing circuit 76 can use almost the entire time of one operation cycle (δ), reducing the possibility of frame dropping.

Figure 29 (b) shows an example in which the display list generated by the performance control CPU 63 is issued to the preloader 73 one operation cycle later than the operation cycle in which it was generated. In this case, the preloader 73 can use almost the entire time of one operation cycle (δ) to perform the preloading operation, so the possibility of frame dropping is also reduced in this case.

In the explanation so far, it has been assumed that a composite chip 50 is used, but it is not necessary that the performance control CPU 63 and the VDP circuit 52 are integrated into a single element. Furthermore, in the above embodiment, the entire performance control is controlled by a single CPU (performance control CPU 63), but the upstream CPU and the downstream performance control CPU 63 may cooperate with each other to execute the performance control operation.

Figures 30 and 31 are block diagrams showing such an embodiment. As shown in the figures, in this embodiment, the upstream performance control CPU controls the audio performance, the lamp performance, and the motor performance. Meanwhile, the downstream CPU circuit 51 controls only the image performance based on the control command CMD' received from the performance control CPU.

When such a configuration is adopted, the CPU circuit 51 does not need to execute the process of step ST12 in FIG. 20(a) and the process of FIG. 20(b), and can take a sufficient amount of time to generate a complex display list DL, making it possible to realize more complex and advanced image presentations such as 3D (Dimension). In such a case, the display list becomes larger, but in that case, the total amount of data in the display list DL is adjusted to 512 bytes or more, N×256 bytes, by adding a dummy command.

In addition, since the operation of the downstream CPU circuit 51 is specialized for image presentation control, it is also possible to confirm that the drawing operation is completed after the display list DL is issued. The lower part of Figure 22 shows an example of operation control in this case, and if the drawing operation is not completed even after the limit time has elapsed, the major abnormality flag ABN is set and processing ends (ST32). Note that since the processing of the downstream CPU circuit 51 is limited to image presentation control, it is also possible to simply wait for the drawing operation to be completed in an infinite loop.

When this configuration is adopted, the start condition determination (ST5) in FIG. 20(a) can be repeated for a predetermined time. Even with this configuration, so long as the delay in completing the drawing operation is not too long, the only problem that occurs is a delay in switching between display area (0) and display area (1). In other words, as in the operation cycle T1+3δ shown in FIG. 32(a), in one operation cycle in which the display operation is repeated twice, only the first half experiences a frame drop state, and the second half displays normal frames.

This is also the case when a preloader is used, and the start condition determination (ST5') in FIG. 25(a) can be repeated for a predetermined time. If there is a slight delay, then only the first half of the operation cycle T1+3δ shown in FIG. 32(b) will experience frame drop, and normal frames will be displayed in the second half. However, if the completion of the drawing operation is significantly delayed, then complete frame drop will occur, as in the operation cycle T1+3δ in FIG. 28(a), and if this situation continues, the WDT circuit 58 will be activated. This is also the case when a preloader is not used.

Furthermore, when the control operation of the CPU circuit 51 is specialized for image rendering control, in an embodiment employing DMA transfer, as shown at the bottom of FIG. 24, the completion of the drawing operation of the drawing circuit 76, the completion of the operation of the data transfer circuit 72, and the completion of the operation of the DMAC circuit 60 are determined (ST50'-ST52'). If any of the operations does not end normally, the operation of the data transfer circuit 72 and the drawing circuit 76 is initialized, and processing similar to the processing of steps ST53-ST55 (ST55'-ST57') is executed. Note that in this case as well, it is preferable to re-execute the DL issuance process a predetermined number of times.

The above describes an embodiment in which an index space with a horizontal size that perfectly matches the number of horizontal pixels of each display device is constructed as the frame buffers FBa and FBb of the main display device DS1 and the sub display device DS2. Figure 33(a) clearly illustrates this relationship, showing a case in which the drawing area (W x H) in the virtual drawing space and the effective data area (actual drawing area W x H) in the index space both match the number of horizontal/vertical pixels of the display devices.

In such a correspondence relationship, the drawing operation into the virtual drawing space by the display list DL is not necessarily limited to the drawing area (W x H). For example, as shown by the left sloping line at the top of Figure 33(a), by moving the drawing position in time for a drawing image (W' x H') that exceeds the drawing area (W x H), it is possible to appropriately move the drawing contents into the actual drawing area W x H, shown by the right sloping line at the bottom of Figure 33(a), vertically/horizontally/diagonally.

To achieve this kind of effect, for example, an index space with a horizontal size W larger than the number of horizontal pixels of the display device may be provided, as shown in Figure 33(b). In this case, the drawing area WxH in the virtual drawing space defined by instruction command L12 (SETDAVF) in the display list DL is set to be larger than the actual drawing area wxh corresponding to the number of horizontal/vertical pixels of the display device. Note that the actual drawing area wxh is indicated by a right-sloping line at the bottom of Figure 33(b).

The vertical and horizontal dimensions of the actual drawing area w×h are then specified as the number of display lines and the number of horizontal pixels of the display device in step SS30 of FIG. 20, and the upper left corner point of the actual drawing area w×h is set in a specified display register as the vertical/horizontal display start position in step SS31 of FIG. 20.

Meanwhile, the base address (X, Y) in the index space is set in a specified drawing register by the display list instruction command L11. As explained above, specifically, the top left base address in the index space IDX is specified as (0, 0), for example, by the environment setting instruction command L11 (SETDAVR). Then, if the top left corner point of the actual drawing area w×h is moved appropriately during normal processing, the drawing contents of the actual drawing area W×H, indicated by the right sloping line at the bottom of Figure 33(b), will move vertically/horizontally/diagonally as appropriate.

As explained with reference to FIG. 20, the VDP register RGij related to steps SS30 to SS32 is write-prohibited after initial setting (second prohibition setting SS34), but at the timing of executing the above-mentioned performance, this prohibition is released by writing a release value to a specific VDP register RGij.

In the above embodiment, the first and second type of inhibit setting registers are utilized to uniformly set the specified system control register RGij and the specified VDP register RGij of the initial setting system to a write inhibit state (see SS33 and SS34 in FIG. 20 and FIG. 25), so that the set values of these registers are not subsequently changed due to the influence of noise, etc. However, it is also preferable to repeat the setting process for the set values of important system control registers RGij at predetermined time intervals without setting them to such a write inhibit state.

Figure 34 is a diagram explaining the processing in such a case, where the setting values to be set in the initial setting processing (ST3) are collected in a setting value table SETTABLE stored in the control memory 53 (PROGMROM). Note that although explanation is omitted for step ST3 in Figure 20, the embodiment in Figure 20 is substantially the same as that explained below with regard to (a) executing the initial setting processing based on the initial value setting table SETTABLE, and (b) the contents of the initial value setting table SETTABLE.

In any embodiment, the setting value table SETTABLE is composed of multiple sets (N sets), each set being the register address value of the VDP register RGij and the setting value for that register RGij. Although not particularly limited, the register address value is fixed to 16 bits in length, and the setting value is fixed to 32 bits in length, and since each is a fixed length, the data capacity of the initial value setting table SETTABLE is 6 x N bytes (= 48t x N bits) in length, and there are N VDP registers RGij.

However, in the embodiment of FIG. 20, the initial value setting table SETTABLE is accessed for READ only once, and all N VDP registers RGij are initialized only once, whereas in the embodiment of FIG. 34, all N VDP registers RGij are divided into N1 VDP registers RGij that are initialized only once, and N2 VDP registers RGij that are repeatedly initialized every 1/30 seconds after the first initialization.

In the embodiment of FIG. 34, the setting values that are repeatedly initialized include (1) setting values for DMA transfer operations, (2) setting values for the VRAM, (3) setting values for interrupts, (4) setting values for the display circuit 74, and (5) setting values for the drawing circuit 76.

(1) The setting values for DMA transfer operation are, for example, setting values that are prerequisites for the operating conditions specified in step ST41, and are basic setting values that are fixedly applied regardless of differences in the operating conditions in FIG. 23(c) and FIG. 27(c). Specifically, they include setting values such as (a) a threshold value for how much of the FIFO buffer (N stages) built into the DMA transfer circuit 60 must be released before a transfer request is made to the transfer source (e.g., 1/2 of the total stages), and (b) whether or not to perform a handshake operation with the transfer destination and transfer source (e.g., No).

(2) The VRAM setting value includes the refresh cycle of the refresh operation. The built-in VRAM 71 operates at this refresh cycle to prevent natural discharge of stored data. Next, (3) the interrupt setting value is a value that specifies the type of error that causes an interrupt request and the output terminal of the interrupt signal (internal terminal of the built-in CPU), and includes, for example, setting values such as (a) that if the drawing circuit 76 freezes, a drawing abnormality interrupt is generated for the CPU circuit 51 (interrupt enabled state, see FIG. 20(d)), and (b) that when VBLANK starts on the display device DS1, a VBLANK start interrupt is generated for the CPU circuit 51 (see FIG. 20(c)).

In this embodiment, a composite chip 50 is used in which the CPU circuit 51 and the VDP circuit 52 are integrated, but if they are separate chips, the output terminal from which the VDP circuit 52 outputs an interrupt signal is connected to the external interrupt input terminal of the CPU circuit 51.

In addition, (4) the display circuit settings include (a) the horizontal/vertical start position of each frame buffer (see SS31), (b) the horizontal sync signal settings of each display device, (c) the vertical sync signal settings of each display device, (d) the scaler settings, and (e) the number of horizontal pixels and the number of display lines settings of each display device (SS30).

(5) The settings for the drawing circuit 76 include a setting value for the freeze time until a drawing abnormality interrupt occurs. This setting value is set, for example, as an integer multiple of the period of the vertical synchronization signal. As explained in FIG. 20(d), if the drawing circuit 76 does not access the VRAM during the freeze period specified here, the drawing circuit 76 is individually reset (ST16b), and the operating parameters for the drawing circuit 76 are reconfigured (ST16c).

As described above, in this embodiment, important setting values are repeatedly reset at predetermined time intervals, so that even if the setting values are corrupted due to noise or other factors, the abnormality is immediately corrected. Also, in this embodiment, unlike the embodiment in FIG. 20, the first and second type inhibition setting registers RGij are not set to a write-prohibited state, so rewriting can be performed freely without going through the somewhat complicated inhibition release process.

So far, in the embodiment, a configuration has been described in which a drawing abnormality interrupt is generated from the drawing circuit 76 of the VDP circuit 52 to the CPU circuit 51 when (1a) the operation of the drawing circuit 76 freezes after a predetermined freeze time has elapsed, or (1b) the drawing circuit 76 detects an irrational instruction command in the display list DL (see FIG. 20(d)). When a drawing abnormality interrupt occurs, the cause of the interrupt is determined (ST16a in FIG. 20(d)), and processing is executed according to the determination result (ST16c to ST16d).

However, according to the inventor's experiments, even under harsh operating conditions with a lot of noise, drawing abnormality interrupts rarely occur. Therefore, in order to reduce the control burden, it is preferable to either move to an infinite loop process (see FIG. 25(b)) without providing an interrupt cause determination process (ST16a), or to activate the pattern check circuit CHK (see FIG. 6(b)) (see ST17a in FIG. 25(c)).

In this case, the WDT circuit 58 will then be activated after a predetermined time, and the entire composite chip 50 will be reset, or just the VDP circuit 52 will be reset immediately thereafter (see FIG. 6(b)). If the VDP circuit 52 is reset based on the reset keyword output process (ST17a), the normal completion of the reset operation will be confirmed and the stack area that stores the return address will be organized (ST17b), after which the process will proceed to, for example, step ST4 or ST13.

In addition, in this embodiment, since the abnormality determination process (ST5 in FIG. 20 and FIG. 25) is provided to determine the completion of the operation of the drawing circuit 76 every 1/30 seconds, a drawing abnormality interrupt process (FIG. 25(d)) that essentially does nothing may be provided to further reduce the control burden. As shown in FIG. 25(d), in this configuration, when a drawing abnormality interrupt occurs, an IRET (Interrupt Return) command is immediately executed to return to the main control process, so the frozen state of the drawing circuit 76 will continue as is. However, in this embodiment, the number of frame drops is counted by the abnormality flag ER in the process of step ST5 in FIG. 20 and FIG. 25, and either the WDT circuit 58 or the pattern check circuit CHK will be activated at any time, so the configuration of FIG. 25(d) is essentially the same as the configuration of FIG. 25(b) and FIG. 25(c).

In addition, in order to further reduce the control burden, it is also preferable to set the VDP circuit 52 to a drawing abnormality interruption disabled state during initialization (see step ST3 in FIG. 20 and FIG. 25). If the default state at power-on is a drawing abnormality interruption disabled state, (a) a specific system control register RGij in which a permission/prohibition value that specifies whether an abnormality interrupt is permitted/prohibited should be set is set to a write-prohibited state, or (b) a prohibition value is repeatedly written to the system control register RGij at predetermined time intervals.

At first glance, this configuration seems superior to the configurations in Fig. 25(b) and Fig. 25(b). However, from the perspective of versatility of the control program, it is better to (b) set the drawing abnormality interrupt to a uniformly permitted state for all models of gaming machines of this type, rather than (a) setting it to a uniformly prohibited state for all models of gaming machines of this type, and then select for each model whether to adopt the configuration in Fig. 20(d) or one of the configurations in Fig. 25(b) to (d). Note that with the former configuration (a), it becomes necessary (complexity) to change the initial setting routine (see step ST3 in Fig. 20 and Fig. 25) for each model.

As a further modified embodiment, it is also preferable to utilize the audio circuit SND built into the combined chip 50. FIG. 35 is a block diagram showing such an embodiment. As is clear from comparing FIG. 35 with FIG. 6, in this embodiment, the audio processor 27 and audio memory 28 are not required, and external wiring to the audio circuit is not required for the data bus (8 bits) and address bus (2 bits) of the CPU circuit 51. In addition, since there is no transmission line for the underflow signal UF, the risk of the combined chip being erroneously reset due to noise superimposed on this UF transmission line is also avoided.

In addition, in this embodiment, in response to the elimination of the audio memory 28, the audio data to be stored in the audio memory 28 is stored in the CGROM 53. Figure 36(d) illustrates the storage contents of the CGROM 53, which permanently stores sound ROM header information, phrase header information HD, a large number of phrase data PH compressed from a group of audio data, and a large number of sound commands SCMD that dictate the operation of the audio circuit SND.

As shown in the figure, sound ROM header information is stored from the starting address SNDst, followed by phrase header information HD of data size HDvl stored from the starting address HDst. In addition, phrase data PH of data size PHvl is stored from the starting address PHst, and sound command SCMD of data size SCMDvl is stored from the starting address SCMDst.

Here, the sound ROM header information specifically means the start address HDst of the phrase header HD area, the data size HDvl of the phrase header HD area, the start address PHst of the phrase data area PH, the data size PHvl of the phrase data area PH, the start address SCMDst of the sound command area SCM, and the data size SCMDvl of the sound command area SCMD. This information is acquired by the internal circuitry of the sound circuit SND when the power is turned on (see step SD4).

The phrase header information HD and phrase data PH are also transferred to the external DRAM 54 when the power is turned on, thereby speeding up subsequent READ access (step SD6). In this way, in this embodiment, the voice processor 27 and voice memory 28 are eliminated, thereby reducing size and manufacturing costs, and overcoming the weakness of the CGROM 53, which is cheap and easy to increase in capacity, but has a slow access speed.

Based on the above, the initial setting process at power-on will be explained with reference to FIG. 36(a). Note that this process is executed as part of the process of step ST3 in FIG. 20 or FIG. 25.

As explained with respect to FIG. 6(b), when the power is turned on or when an abnormal reset occurs in which the WDT 58 is activated, the audio circuit SND is hardware reset via the reset path 2 (step SD1). Also, if the performance control CPU 63 detects an abnormality in the audio circuit SND, the audio circuit SND is hardware reset via the reset path 4B or 4C (step SD1). Note that the performance control CPU 63 may activate the pattern check circuit CHK, which may result in a hardware reset of the audio circuit SND together with the other circuits (72, 73, 74, etc.) (step SD1).

In either of these cases, the performance control CPU 63 then confirms that the reset operation has been completed normally (step SD2), and first sets the top address SNDst of the sound data area to the system control register RGij of the audio circuit SND (step SD3). Next, a predetermined value is set in a predetermined system control register, causing the sound ROM header information HD to be stored in the internal circuit. The sound ROM header information HD is the six elements mentioned above (HDst, HDvl, PHst, PHvl, SCMDst, SCMDvl), as shown in Figure 36 (c).

Then, it is confirmed that the processing up to this point has been normal, and if it has not ended normally, the audio circuits are individually reset via reset path 4B or 4C. However, since normal end can usually be confirmed, the phrase header information HD and phrase data PH are then transferred to the external DRAM 54 using the data transfer circuit 72 (step SD6). Note that the destination start address BGN, the source start address HDst, the total amount of data to be transferred HDvl+FDvl, etc. are appropriately specified in the data transfer circuit 72.

Next, the phrase header information HD and phrase data PH are stored in the external DRAM 54, not in the CGROM 55, by setting a specific system control register RGij (step SD7), and the start address BGN (sound RAM start address) of the group of data transferred to the external DRAM 54 is set in a specific system control register (step SD8). After that, other initial setting processes are completed (step SD9), enabling voice control operation.

As explained above, the sound ROM header information, i.e., the six pieces of information (HDst, HDvl, PHst, PHvl, SCMDst, SCMDvl), are stored in the internal circuitry of the sound circuit SND (step SD4), so the performance control CPU 63 can then specify the necessary information such as phrase data as a relative value to the sound RAM start address BGN, and the sound circuit SND, upon receiving this instruction, will convert the relative address value into an absolute address value and execute the necessary sound processing. Since sound data such as phrase data is accessed for reading from the external DRAM 54 rather than from the CGROM 55, even complex and advanced sound performances can be smoothly realized.

Although various embodiments have been described in detail above, the present invention is not limited to pinball machines or reel machines, and the specific description does not limit the present invention in any way. For example, the power-on reset operation shown in FIG. 15 is started based on the information in the vector table VECT secured at address 0x00000000 in the control memory 53, but it is also preferable to set the HBTSL terminal to the H level and to place the vector table VECT in the leading area of the CGROM 55. FIG. 37(a) and FIG. 37(b) show address maps in such a case, and the address space CS0 of the performance control CPU 63 is secured in a part (leading area) of the CGROM 55.

The main body of CGROM 55 is not accessed (cannot be accessed) by the performance control CPU 63, but is accessed exclusively by the VDP circuit 52, and is therefore not positioned in the address space CSi. As explained above, the main body of CGROM 55 can be configured with multiple memory devices, and in such a case, by dividing it into device sections SPA0 to SPA1 by the processing of step SP20 in Figure 17(a), optimal READ access suited to the characteristics of the memory devices becomes possible.

In any case, when the HBTSL terminal is set to the H level, the memory type and bus width (64/32/16 bits) of the CGROM 55 must be specified in advance based on the fixed input values to the 2-bit HBTBWD terminal and the 4-bit HBTRMSL terminal.

In this embodiment, following the vector table VECT, bus parameters for optimizing READ access from CGROM 55 must be stored in the leading area of CGROM 55. Although not essential, it is also preferable to store obfuscation parameters for deciphering the performance control program if it has been obfuscated to make illegal analysis of the program difficult.

When this configuration is adopted, after the power is reset, during the reset assertion period, the following operations 1 to 4 are automatically executed without going through program processing. First, the bus width of the address space CS0 is specified based on the input value to the HBTRMSL terminal, and the memory type is automatically specified based on the input value to the BTBWD terminal, and each is set in a predetermined VDP register RGij (operation 1). In this case, the memory type is broadly divided into memory elements that use a parallel I/F (Interface) format and memory elements that use a sequential I/F format.

Next, the obfuscation parameters stored in CGROM 55 are loaded, and the information required to remove the obfuscation is automatically set in the internal circuit (operation 2). In addition, the bus parameters stored in CGROM 55 are automatically acquired in the VDP register RGij (operation 3). Note that this operation 3 corresponds to the program processing of step SP63 in FIG. 18, and is automatically executed by the internal circuit.

Finally, to put into effect the bus parameters set in operations 1 to 3, an operation corresponding to the program processing in step SP64 in FIG. 18 is automatically executed by the internal circuit (operation 4). Then, when the bus parameter settings are put into effect, the values of the program counter PC and stack pointer SP are automatically set based on the information in the vector table, and execution of the boot program (initial setting program) begins.

With the configuration shown in FIG. 37(a), the program processing in step SP1 in FIG. 15(a) is also unnecessary, and operations 1 to 4 are executed automatically, greatly reducing the program processing burden. Also in this case, programs and data following the vector handler Vopt are transferred to an appropriate RAM area based on the operation of the initial setting program Pinit.

The programs and data following the vector handler Vopt do not necessarily need to be stored in the head area of the CGROM 55, and may be stored in the control memory 53, for example (Figure 37 (b)). Also, the programs and data following the vector handler Vopt do not necessarily need to be transferred to the RAM area, and if they are not transferred, the memory section initialization process (SP8 in Figure 15) in the initialization setting program is not necessary.

Furthermore, it is not necessary to match the V blank timing with the timing at which the transmission of significant image data ends. In other words, there is no need to end the transmission of image data at the timing of the lower left corner (circle) of the display area shown in FIG. 14(f). In short, it is sufficient to satisfy the specifications of the waiting time WTh/WRv and the horizontal/vertical synchronization signals HS/Vs required by the display device.

Fig. 39(a) is a diagram for explaining such an embodiment, and shows, for example, the operation of the display circuit 74A. In this embodiment, the frequency F _dot of the dot clock DCK is specified as 108 MHz in accordance with the specifications of the main display device DS1. In addition, in order to make the frame rate FR equal to 1/60 seconds, it is necessary to make THc x TVl / F _dot = 1/60, and here, as in the case of Fig. 14(f), the number of cycles THc of horizontal synchronization is set to 1662 clocks, and the number of lines TVl of vertical synchronization is set to 1083 lines.

In the illustrated embodiment, the horizontal synchronization signal HS and vertical synchronization signal VS are output in accordance with the display device specifications so as to be compatible with general display devices. In the illustrated example, the pulse width of the horizontal synchronization signal HS is 100 clocks, the horizontal front porch FPh is designed to be 110 (=10+100) clocks, and the horizontal back porch BPh is designed to be 172 clocks. In addition, the pulse width of the vertical synchronization signal VS is 10 lines, the vertical front porch FPv is designed to be 20 (=10+10) lines, and the vertical back porch BPv is designed to be 291 lines.

However, in the embodiment shown in Figures 39(a) and (b), the vertical wait time WTv is set to 49 lines and the horizontal wait time WTh is set to 372 clocks in order to complete the output operation before the V blank start timing indicated by the circle. Therefore, according to this embodiment, after the image update process for one frame is completed, the V blank start timing arrives after a time equivalent to 10 lines (154 μS), ensuring image update process under any operating conditions (see Figure 39(b)).

This type of operation works particularly well in display circuits that operate in synchronization with other display circuits, such as display circuits 74B and 74C that accompany the operation of display circuit 74A. Figures 39(c) to 39(e) are diagrams that explain this point, and show a case where the V blank period T2 in display circuit 74B is longer than the V blank period T1 in display circuit 74A (T1<T2).

In such a case, if the V blank period T1 in the display circuit 74A is operated in conjunction with the display circuit 74A, the V blank will start before the output of image data in the display circuit 74B is completed, which may result in image loss or unnatural display behavior (Figure 39 (d)). On the other hand, if the display circuit 74B is operated independently, it will not be possible to maintain consistency with the operation timing of the drawing circuit, which is synchronized with the operation of the display circuit 74A.

Therefore, if the V blank period T2 of display circuit 74B accompanying the operation of display circuit 74A is longer than the V blank period T1 of display circuit 74A, the wait time (vertical blank period) should be set short so that there is sufficient margin of time after the output of image data in display device B, as in the case of Figures 39(a) and (b). In this case, unless the wait time is set extremely short, a normal liquid crystal display device will be able to achieve display operation without any problems.

For example, even if the V blank period T3 of the display circuit 74B accompanying the operation of the display circuit 74A is shorter than the V blank period T1 of the display circuit 74A, an extra waiting period occurs after the V blank period T3, but the display operation is realized without any problem as long as the overall waiting time is not extremely long.

Although the embodiments of the present invention have been described in detail above, the specific description does not limit the present invention in any way. For example, the embodiments have been described primarily with respect to dual link transmission paths, but in order to simplify the device configuration, it is also preferable to employ a single link transmission path.

In the case of a single-link transmission line, if the frequency of the dot clock DCK is 108 MHz, the frequency of the LVDS clock CLK will also be 108 MHz. In this case, too, it is preferable that the dot clock DCK and the LVDS clock CLK share a common supply source, the oscillator OSC2, and are generated by the same generation process.

Also, unlike the above embodiment, it is preferable to use a single oscillator OSC2 as the common source for the system clock of the VDP circuit 52 and the CPU operating clock of the CPU circuit 51 in order to simplify the circuit configuration. If the multiplication ratio of the PLL circuit is commonly set based on the setting value of a common setting terminal (3-bit PLLMD terminal), frequency setting processing becomes unnecessary, which is even more effective.

In this case, although it somewhat contradicts the desire to speed up the CPU operating clock, it is preferable to adopt a system clock with the highest frequency allowed by the internal circuitry of the VDP circuit 52 and set the CPU operating clock to the same frequency.

For example, if the oscillation frequency of oscillator OSC2 is 40 MHz, the system clock and CPU operating clock can be set to a common 200 MHz (= 40 MHz x 5) by setting the setting terminal (3-bit PLLMD terminal) to 5. With this configuration, oscillator OSC1 is not required, and not only can the circuit configuration be simplified, but the somewhat complicated setting process for the VDP register is also unnecessary. Another advantage is that the operating cycles of VDP circuit 52 and CPU circuit 51 are the same.

GM gaming machines DS1, DS2 display device 52 image generating means 51 performance control means DL drawing list 76 drawing circuit 74 display circuit DCK display clock F _dot display clock frequency SS33 first means SS35 second means SS36 third means TH line operation time THc horizontal cycle number TVl vertical line number TV0 vertical reference point WTv between a predetermined number of lines

Claims (1)

a performance control means for issuing a display list that specifies the display contents to be displayed on the screen of the display device and controlling the operation of the image generating means;
A game machine having an image generating means for generating image data for realizing the display contents based on an instruction command written in a display list issued by the effect control means, and realizing an image effect by the display device having a number of vertical pixels V x a number of horizontal pixels H,
the image generating means is configured to have a data transfer circuit that transfers the configuration data of the display list received from the performance control means in a predetermined acquisition bit unit to a downstream circuit in a predetermined transfer bit unit, and the performance control means is configured to create the display list so that the total bit length is an integer N times (N≧1) the predetermined transfer bit unit,
A first means for defining a frequency Fdot of a display clock that defines an internal operation of a display circuit built into the image generating means;
a second means for defining a line operation time of the display circuit corresponding to one horizontal line of the display device by a horizontal cycle number THc of the display clock;
a third means for defining a vertical line number TVl, which is the number of times the line operation time is repeated;
A gaming machine characterized in that the display circuit is configured not to output image data corresponding to pixels of the display device for a predetermined number of lines starting from a vertical reference point of a display operating period defined based on the horizontal cycle number THc, the vertical line number TVl, and the value of the frequency Fdot of the display clock.

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