JP2005087334A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To avoid a rise in the cost of a game machine without the use of a high-performance processor while achieving an increase in the capacity of performance data used for performance. <P>SOLUTION: A CPU (central processing unit) 101 for performance control selects a CG (overglass) ROM (B) 83 or a CGROM (B') 84 for validifying the reading of the data by a chip select (1) signal in reference to the address information on each image. VDP 81 selects a CGROM (A) 82 or CGROMs 83 and 84 for validifying the reading of the data by the chip select (2) signal based on a control signal. The VDP 81 outputs the address signal to the CGROMs 82-84 and reads out the image data from one CGROM selected by the chip select (1) or (2) signal. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention enables a player to execute a predetermined game, and when a specific result is obtained as a result of the predetermined game, such as a pachinko gaming machine or a slot machine that controls to a specific game state advantageous to the player. It relates to gaming machines.

  In a pachinko gaming machine, the fact that the display result of the variable display means for displaying a special symbol as identification information is a combination of specific display modes determined in advance is generally called “hit”. When the big hit occurs, for example, the big winning opening is opened a predetermined number of times, and the game shifts to a big hit gaming state where the hit ball is easy to win. In addition, in the variable display means, a symbol other than the symbol that becomes the final stop symbol continues for a predetermined time and is stopped, rocked, enlarged, reduced, or deformed in a state that matches a specific display result, or The situation where multiple symbols are fluctuating synchronously in the same symbol, or the position of the display symbol is switched, and the possibility of a big hit continuing before the final result is displayed (hereinafter referred to as these states) Is referred to as a reach state).

  By the way, the pachinko gaming machine is provided with a ROM for storing various data. In general, when data stored in a ROM is read, data stored in an address specified by the address signal is read by outputting an address signal specifying an address from the processor to the ROM. A signal line for transmitting the address signal is an address bus. As the number of buses, that is, the number of digits of addresses that can be specified increases, more addresses can be directly specified. The range of addresses that can be specified by the address bus is called an address space.

  For example, in the conventional pachinko gaming machine described in Patent Document 1, a chip select signal (CS00 to CS15) for enabling 16 types of latch ICs from a 16-bit address signal (ADR00 to ADR15) is generated, Data is read by outputting the generated chip select signal.

Japanese Patent Laid-Open No. 11-76565 (paragraphs 0016, 0017, FIG. 1)

  Today, in pachinko gaming machines, the volume of data used for gaming effects is increasing. For example, by using a high-resolution image typified by a live-action photograph for game effects, the capacity of image data is increased as the resolution of the image is increased. However, as the data capacity increases, it is necessary to increase the capacity of the ROM for storing data, and it is necessary to increase the address space. On the other hand, when a high-performance processor that can access a wide address space (for example, a VDP that performs image processing of image data) is used, there is a problem that the cost of the gaming machine increases.

  In the conventional gaming machine described in Patent Document 1, chip select signals (CS00 to CS15) for enabling 16 types of latch ICs are used, but 16 types or more of latch ICs are enabled. In order to widen the address space, it is necessary to increase the number of signal lines, resulting in an increase in cost.

  Therefore, an object of the present invention is to provide a gaming machine that can increase the capacity of readable data and can avoid an increase in cost.

  In the gaming machine according to the present invention, when a player can execute a predetermined game and a specific result is obtained as a result of the predetermined game (for example, a display result of identification information variably displayed on the variable display device 9 is displayed). A gaming machine that controls a specific gaming state (for example, a big hit gaming state) advantageous to a player when a specific display result (a big hit symbol) is obtained, and an electrical component (for example, variable display) provided in the gaming machine A plurality of data storage means (for example, CGROMs 82 to 84 and sound data ROMs 702 to 704) for storing effect data (for example, image data and sound data) used for causing the device 9 and the speaker 27 to execute effects; A control command signal (for example, a control signal or a command signal) for instructing to read out the production data stored in the data storage means. ) For outputting an effect control microcomputer (for example, the effect control microcomputer 100 including the effect control CPU 101) and the address (for example, “shown in FIG. 5” assigned to the data storage means when the control command signal is input. 0000000h "to" 1FFFFFFh "), the address indicated by the control command signal (for example, the top address of the data storage area within the range of" 0000000h "to" 1FFFFFFh ") is specified to the data storage means A controller IC (for example, a VDP 81 or a voice synthesis IC 701) that reads the effect data stored at the address and causes the electrical component to execute the effect using the read effect data. One address indicated by the signal On the other hand, a plurality of data storage means (for example, CGROM (B) 83 and CGROM (B ′) 84 to which the same addresses “1000000h” to “1FFFFFFh” are assigned redundantly, audio data ROM (B) 703 and The production data can be read out from the audio data ROM (B ′) 704), and the production control microcomputer uses the production data stored in the plurality of data storage means to execute the production. In addition, data storage means (eg, for example, storing effect data used for execution of the current effect among a plurality of data storage means from before the control command signal is output to the controller IC (eg, before executing step S205). CGROM (B) 83 or CGROM (B ′) 84, voice data ROM (B) 703, Activation signal output means (for example, step select signal) that outputs an activation signal (for example, chip select (1) signal) for validating reading of data from the data storage means to the audio data ROM (B ′) 704). The controller IC includes data storage means to which an enable signal is input (for example, CGROM or audio data in which the CE input terminal for inputting the chip select (1) signal is at a low level) The effect data stored in the address assigned to the ROM) is read (for example, step S224 is executed). In the present invention described above, three CGROMs 82 to 84 and three audio data ROMs 702 to 704 are given as specific examples of the plurality of data storage means, but the CGROM (A) 82 and the like are included in the plurality of data storage means. Even if the audio data ROM (A) 702 is not included, the present invention can be realized.

  A plurality of performance data read continuously by the controller IC when the performance control microcomputer causes the electrical component to perform a continuous performance (for example, a super reach production after reach production or a jackpot game production after reach production). Are collectively stored in one of the plurality of data storage means (for example, as shown in FIG. 5, the plurality of movie image data (1) to (3) are CGROM (B) 83). The plurality of movie image data (4) to (6) are preferably stored together in the CGROM (B ′) 84).

  The production control microcomputer does not enable the input state (for example, ON state) for enabling the reading of the data of the enabling signal and the reading of the data depending on the signal level (for example, the high level and the low level) on the single signal line. The non-input state (for example, off state) is switched, and the plurality of data storage means include a first data storage means (for example, CGROM (B) 83 and voice data ROM (B) 703) and a second data storage means (for example, CGROM (B ′) 84 and audio data ROM (B ′) 704), and the first and second data storage means branch off a single signal line from the production control microcomputer. Are connected to each other, and one branch line is provided with an inverting circuit (for example, an inverter) for inverting the signal level (see FIG. 4). When either one of the second data storage means is in the input state of the enabling signal (for example, a low level signal in which the chip select (1) signal is on and the polarity is inverted by the inverter is input) When the chip select (1) signal is off and a high level signal whose polarity has been inverted by the inverter is input), the other is in the non-input state of the enabling signal ( For example, the chip select (1) signal is on and a high level signal is input without going through an inverter, and the chip select (1) signal is off and a low level signal is inputted without going through an inverter May be configured.

  In addition to a plurality of data storage means, presentation data that is read more frequently than the presentation data stored in the data storage means (for example, image data such as special symbols, warning characters, backgrounds, hold display, special Audio data used during normal effects or notice effects during fluctuations in symbols: Note that the data is read relative to data for effects stored in the data storage means (for example, movie image data used for reach effects, etc.). If the data is frequently used, all of the image data and audio data shown above may not be stored, and other image data and audio data may be stored. The high-frequency data storage means (for example, CGROM (A) 82 and voice data ROM (A) 702) may be provided.

  The electrical component includes an image display device (for example, a variable display device 9) that can display an image (for example, an image such as a special symbol) including a plurality of types of identification information that can identify each of the electrical components. Image data as effect data used for displaying an image on the display device is stored (for example, CGROMs 82 to 84 store image data), and the controller IC reads and reads the image data from a plurality of data storage means. It may be configured to be a microcontroller (for example, VDP 81 that executes the image reading and developing process shown in FIG. 10) that displays an image on the image display device using the image data.

  As described above, in the first aspect of the invention, the controller IC can read out the production data for a plurality of data storage means for one address indicated by the control command signal. When the control microcomputer executes an effect using the effect data stored in the plurality of data storage means, the current effect of the plurality of data storage means before the control command signal is output to the controller IC. Including an enabling signal output means for outputting an enabling signal for enabling the reading of data from the data storing means to the data storing means storing the production data used for execution of the controller IC, It is configured to read production data stored at the address assigned to the data storage means to which the validation signal is input. Therefore, the capacity of the presentation data stored in the data storage means that can be read by the controller IC can be increased, and since it is not necessary to widen the address space, it is necessary to use a high-performance controller IC. Therefore, it is possible to avoid an increase in the cost of the gaming machine.

  According to the second aspect of the present invention, when the production control microcomputer causes the electrical component to execute a continuous production, the plurality of production data that the controller IC continuously reads are one of the plurality of data storage means. Since they are stored together in the data storage means, it is not necessary to switch the activation signal to the data storage means when performing the performance continuously based on different performance data, and there is an error in reading the performance data (miss ) Can be reduced as much as possible.

  In the invention according to claim 3, the production control microcomputer has an input state in which the reading of the data of the enabling signal is enabled and a non-input state in which the reading of the data is not enabled, depending on the signal level in the single signal line. The plurality of data storage means are two of the first data storage means and the second data storage means, and the first and second data storage means are a single unit from the production control microcomputer. The signal lines are branched in the middle and connected to each other, and one of the branch lines is provided with an inverting circuit for inverting the signal level, and either one of the first and second data storage means is an enabling signal. Since the other is in the non-input state of the activation signal, the production control microcomputer and the first and second data are It is possible to reduce wiring costs for connecting the pay means.

  In the invention according to claim 4, apart from the plurality of data storage means, a configuration including high-frequency data storage means for storing effect data that is read more frequently than the effect data stored in the data storage means; Therefore, it is possible to prevent the production data from being erroneously read out as much as possible by not storing the production data that is frequently read out in two or more data storage means that are selectively used according to the content of the production data. Can be reduced.

  According to a fifth aspect of the present invention, the electrical component includes an image display device capable of displaying an image including a plurality of types of identification information that can identify each of the electrical components, and the plurality of data storage means cause the image display device to display an image. Since the controller IC reads image data from a plurality of data storage means and displays the image on the image display device using the read image data, the image data as the effect data used for the purpose is stored. The amount of image data used for image display can be increased, and high resolution of the image can be easily realized.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. First, the configuration of the gaming board of the first type pachinko gaming machine that is an example of the gaming machine will be described. FIG. 1 is a front view showing a front surface of a game board in a pachinko gaming machine.

  As shown in FIG. 1, a game board 6 is detachably attached to a pachinko gaming machine. The game board 6 is a structure including a plate-like body constituting the game board 6 and various components attached to the plate-like body. A game area 7 is formed on the front surface of the game board 6.

  Near the center of the game area 7 is provided a variable display device (special variable display section) 9 including a plurality of variable display sections that variably display symbols as identification information that can be identified. The variable display device 9 has, for example, three variable display portions (symbol display areas) of “left”, “middle”, and “right”. The variable display unit may be a fixed area, but may move or change in size in the display area of the variable display device 9 while the game is in progress.

  In addition to the special symbol, the variable display device 9 displays a background image, a character image, and the like other than the special symbol. In that case, sprite images and movie images are used as those images. The sprite image is an image having a predetermined shape (for example, a rectangle) for displaying a static image. The sprite image is mainly used when a background image is displayed or when a simple moving image is displayed such that a special symbol or character appears or changes. A movie image is an image that displays a moving image (video) within a predetermined shape (for example, within a rectangle). The movie image is mainly used when displaying a realistic moving image by a multicolor image typified by a live-action image. In this embodiment, a group of images displayed on a part of a display screen such as a character or a pattern realized by a sprite image or a movie image is referred to as a component image. A plurality of types of component images are combined and displayed on the variable display device 9. For example, a sprite image of a background image, a sprite image of a special symbol that is variably displayed, and a movie image of a special character are combined and displayed on the variable display device 9.

  The variable display device 9 also has a special symbol start memory display area (start memory display) for displaying a start winning memory indicating that a game ball has won the start winning opening 14, that is, the variable display execution condition is satisfied. Area) 18 is provided. The start memory display area 18 individually displays a plurality of start winning memories so that the number of effective winning balls that have entered the start winning opening 14, that is, the start winning memory number can be specified. Specifically, the start memory display area 18 individually displays a maximum of four start prize memories in order from the left every time there is a prize at the start prize opening 14. That is, every time there is a valid start prize (start prize when the start prize memory number is less than 4), the start prize memory number displayed in the start memory display area 18 is increased by one. Then, every time the variable symbol special display is started, the number of start winning memories displayed in the start memory display area 18 is reduced by one. The player is notified of the number of start winning memories for which the special symbol variable display is not started by the start winning memory displayed in the start memory display area 18. The display of the start winning memory displayed in the start memory display area 18 of the variable display device 9 is referred to as a hold display. In this embodiment, the hold display is realized by a sprite image.

  In addition, since the symbol display area and the start memory display area 18 are provided separately, the start winning memory number can be displayed even during variable display. The start memory display area 18 may be provided in a part of the symbol display area. In this case, the display of the start winning memory number may be interrupted during variable display. In this embodiment, the start memory display area 18 is provided in the variable display device 9. However, the variable display device 9 is a display (special symbol start memory display) for displaying the start winning memory number. It may be provided separately.

  Below the variable display device 9, a variable winning ball device 15 is provided as a start winning port 14. The winning ball that has entered the start winning opening 14 is guided to the back of the game board 6 and detected by the start opening switch 14a. A variable winning ball device 15 that opens and closes is provided below the start winning opening 14. The variable winning ball device 15 is opened by a solenoid 16.

  An opening / closing plate 20 that is opened by a solenoid 21 in a specific gaming state (big hit state) is provided below the variable winning ball device 15. The opening / closing plate 20 is a means for opening and closing the special winning opening. Of the winning balls guided from the opening / closing plate 20 to the back of the game board 6, the winning ball entering one (V winning area) is detected by the V winning switch 22, and the winning ball from the opening / closing plate 20 is detected by the count switch 23. Is done. On the back of the game board 6, a solenoid 21A for switching the route in the special winning opening is also provided.

  When a game ball wins the gate 32 and is detected by the gate switch 32a, a predetermined random number value is extracted if the normal symbol start winning memory has not reached the upper limit. And if it is a state which can start the variable display in which a display state changes in the normal symbol display 10, the variable display of the display of the normal symbol display 10 will be started. If the normal symbol display 10 is not in a state where variable display in which the display state changes can be started, the value of the normal symbol start winning memory is incremented by one. In the vicinity of the normal symbol display 10, there is provided a normal symbol start memory display 41 having a display unit with four LEDs for displaying the number of normal symbol start winning memorized numbers. Each time there is a prize at the gate 32, the normal symbol start memory display 41 increments the LED to be turned on by one. Then, every time variable display on the normal symbol display 10 is started, the number of LEDs to be lit is reduced by one. The special symbol and the normal symbol can be variably displayed on one variable display device. In that case, the special variable display unit and the normal variable display unit are realized by one variable display device.

  In this embodiment, the left and right lamps (the symbols can be visually recognized at the time of lighting) are alternately turned on, whereby the normal symbols are variably displayed, and the variable display continues for a predetermined time (for example, 29.2 seconds). Then, if the left lamp is turned on at the end of the variable display, it is a win. Whether or not to win is determined by whether or not the value of the random number extracted when the game ball wins the gate 32 matches a predetermined hit determination value. When the display result of the variable display on the normal symbol display 10 is a win, the variable winning ball apparatus 15 is opened for a predetermined number of times for a predetermined time so that the game ball is likely to win. That is, the state of the variable winning ball device 15 changes from a disadvantageous state to a player's advantageous state when the normal symbol is a winning symbol.

  Furthermore, in the probability variation state as the special game state, the probability that the stop symbol in the normal symbol display 10 becomes a winning symbol is increased, and one or both of the opening time and the number of times of opening of the variable winning ball device 15 are increased. And more advantageous for the player. Further, in a predetermined state such as a probability change state, the variable display period (fluctuation time) in the normal symbol display 10 may be shortened, which may be more advantageous for the player.

  The gaming board 6 is provided with a plurality of winning holes 29, 30, 33, 39, and winning of the game balls to the winning holes 29, 30, 33 is detected by winning hole switches 29a, 30a, 33a, 39a, respectively. The Around the left and right sides of the game area 7, there are provided decorative lamps 25 that are blinked and displayed during the game, and at the bottom there is an out mouth 26 that absorbs the hit ball that has not won.

  Although not shown in FIG. 1, speakers and various lamps that emit sound effects and sounds are provided on the outer periphery of the game area 7. The pachinko gaming machine has a glass door frame formed in a frame shape, and a hitting ball supply tray (upper plate) is provided on the lower surface of the glass door frame. Under the hitting ball supply tray, an extra ball receiving tray for storing game balls that cannot be accommodated in the hitting ball supply tray and a hitting operation handle (operation knob) for firing the hitting ball are provided.

  The game balls launched from the hit ball launching device enter the game area 7 through the hit ball rail, and then descend the game area 7. When the hit ball enters the start winning opening 14 and is detected by the start opening switch 14a, the variable display device 9 starts variable display (variation) if the variable display of the symbol can be started. If it is not in a state where the variable display of symbols can be started, the start winning memory number is increased by one.

  The variable display of the special symbol on the variable display device 9 stops when a certain time has elapsed. If the combination of the special symbols at the time of the stop is a jackpot symbol (specific display mode), the game shifts to a jackpot gaming state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or a predetermined number (for example, 10) of hit balls wins. When the hit ball enters the V winning area while the opening / closing plate 20 is opened and is detected by the V winning switch 22, a continuation right is generated and the opening / closing plate 20 is opened again. The generation of the continuation right is allowed a predetermined number of times (for example, 15 rounds).

  When the combination of special symbols in the variable display device 9 at the time of stoppage is a combination of jackpot symbols (probability variation symbols) with probability fluctuations, the probability of the next jackpot increases. That is, it becomes a more advantageous state (special game state) for the player, which is a probable change state.

  FIG. 2 is a block diagram illustrating a configuration example of the game control board and the effect control board. As shown in FIG. 2, a main board (game control board) 31 and an effect control board 80 are installed in the pachinko gaming machine. Although not shown in FIG. 2, in the pachinko gaming machine, in addition to the main board 31 and the effect control board 80, a payout control board, a lamp driver board, an audio output board, and a power supply board are installed. A game control means for controlling the progress of the game is mounted on the game control board. As will be described below, the game control means is realized by a game control microcomputer 50 mounted on the main board 31 and various circuits.

  As shown in FIG. 2, the main board 31 has a game control microcomputer (basic circuit) 50 for controlling the pachinko gaming machine according to a program, and a switch for giving a signal from the start port switch 14a to the game control microcomputer 50. A circuit 58 is mounted. Although not shown in FIG. 2, the switch circuit 58 also receives signals from the gate switch 32a other than the start port switch 14a, the V winning switch 22, the count switch 23, and the winning port switches 29a, 30a, 33a, and 39a. This is given to the game control microcomputer 50.

  Although not shown in FIG. 2, the main board 31 includes a solenoid 16 for opening / closing the variable winning ball apparatus 15, a solenoid 21 for opening / closing the opening / closing plate 20, and a solenoid 21A for switching a path in the special winning opening. A solenoid circuit that is driven in accordance with a command from the game control microcomputer 50 is also mounted. Further, the main board 31 has a jackpot information indicating the occurrence of a jackpot according to data given from the game control microcomputer 50, and an effective number indicating the number of starting winning balls used to start variable display of symbols in the variable display device 9. Also equipped with an information output circuit that outputs information output signals such as start information and probability change information indicating that probability fluctuation has occurred to an external device such as a hall computer via an information terminal board installed on the back of the gaming machine Has been.

  The switch such as the start port switch 14a may be a sensor. That is, the name of the game medium detection means (game ball detection means in this example) that can detect a game ball is not limited.

  The game control microcomputer 50 includes a ROM 54 for storing a game (game) control program and the like, a RAM 55 as storage means (means for storing variation data) used as a work memory, a CPU 56 for performing a control operation according to the program, and An I / O port unit 57 is included. In this embodiment, the ROM 54 and RAM 55 are built in the CPU 56. That is, the CPU 56 is a one-chip microcomputer. The one-chip microcomputer only needs to incorporate at least the RAM 55, and the ROM 54 and the I / O port unit 57 may be externally attached or built-in. Since the CPU 56 executes control according to the program stored in the ROM 54, the CPU 56 executes (or performs processing) hereinafter, specifically, the CPU 56 executes control according to the program. is there. The same applies to CPUs mounted on control means other than the game control means.

  Further, a part or all of the RAM (may be a CPU built-in RAM) 55 is a backup RAM backed up by a backup power source created on the power supply board. That is, even if the power supply to the gaming machine is stopped, a part or all of the contents of the RAM 55 is saved for a predetermined period.

  The game control microcomputer 50 is provided with a counter 56A for generating various random numbers used for jackpot determination or the like. The counter 56A updates the count value used as the random number value within a predetermined numerical range. The counter 56A is built in the game control microcomputer 50, but may be provided as an external counter outside the game control microcomputer 50. The random number extraction storage means 56B extracts various count values updated by the counter 56A based on the occurrence of the start winning (input of the detection signal from the start port switch 14a), and uses the extracted count value as the start winning memory. The data is stored in the storage area 55A corresponding to the start winning memory number in the RAM 55.

  The determination unit 56C at the start time is a big hit in the start winning memory that starts the variation stored in the storage area 55A when the variation of the special symbol can be started (when the variable display start condition is satisfied). The count value used for determination and reach determination is read. Then, the start time determination unit 56C determines whether or not to make a big hit (probability change big hit or non-probability change big hit) or reach based on the read count value.

  The variation pattern determining means 56D reads the count value used for determining the variation pattern of the special symbol in the start winning memory that starts the variation stored in the storage area 55A. Then, the variation pattern determination unit 56D determines a variation pattern of the special symbol according to the determination result of the start time determination unit 56C based on the read count value.

  The command transmission means 56E transmits an effect control command for executing control of a plurality of types of effect means (variable display device 9, speaker, lamp, LED, etc.) to the effect control means mounted on the effect control board. As the effect control command, there are an effect control command for designating the start winning memory number and an effect control command for designating the variation pattern determined by the variation pattern determination means 56D. In addition, there is an effect control command for designating a special symbol stop symbol displayed on the variable display device 9.

  The random number extraction / storage means 56B, the start time determination means 56C, the variation pattern determination means 56D, and the command transmission means 56E are realized as processing executed by the CPU 56 according to a program. A storage area 55 </ b> A corresponding to the start winning memory number is provided in a predetermined area in the RAM 55.

  The game control means transmits a payout control command (command indicating the number of prize balls) for executing the payout control of prize balls to the payout control means mounted on the payout control board in accordance with the winning of the game ball. The process to perform is also executed.

  The effect control board 80 is equipped with effect control means for controlling a plurality of types of effect means. The effect control means is realized by the effect control microcomputer 100, the VDP 81, the CGROMs 82 to 84, the VRAM 85, the drivers 105, 110 and the like mounted on the effect control board 80 as described below. The effect control means performs display control of a variable display device (LCD) 9 that performs variable display of special symbols, display of a start winning memory, and the like. In this embodiment, although not shown in FIG. 2, the effect control means also performs display control of the normal symbol display 10 that variably displays normal symbols. Further, the production control means includes display control (lighting / lighting-off control) of the normal symbol start memory display 41 and the decoration lamp 25 provided on the game board 6 and display control (lighting / lighting-off control) of various lamps / LEDs. Also do. Furthermore, the effect control means also controls the sound output of the speaker.

  As shown in FIG. 2, the effect control board 80 displays images on the display screen of the effect display microcomputer 100 that controls a plurality of types of effect means (such as the variable display device 9) according to the program. VDP (Video Display Processor; also referred to as GCL (Graphics Controller LSI)) 81 that performs drawing processing (image processing) of image data (CG data) used for image processing, image data such as frequently used symbols and characters, etc. A character ROM (hereinafter referred to as CGROM) 82 to 84 for storing image data and a VRAM (video RAM) 84 which is an image memory for storing image data to be displayed on the display screen of the variable display device 9 are mounted. Has been. The effect control board 80 further includes a driver 105 that outputs lighting instruction information output from the effect control microcomputer 100 to the lamp driver board, and sound number data output from the effect control microcomputer 100 as an audio output board. And a driver 110 for outputting to the driver.

  The effect control microcomputer 100 includes an effect control CPU 101 that performs a control operation in accordance with an effect control program, a ROM 102 that stores an effect control program, etc., a RAM 103 that serves as a work memory, and an I / O port. Part 104 is included. In this embodiment, the ROM 102 and the RAM 103 are built in the CPU 101 for effect control. That is, the effect control CPU 101 is a one-chip microcomputer.

  In the effect control microcomputer 100, the command receiving means 101A receives the effect control command transmitted from the game control means, and stores the received effect control command in the reception command buffer. The command analysis means 101B reads the effect control command stored in the reception command buffer, and analyzes (determines) the content of the read effect control command.

  The V blank interrupt process execution means 101C executes the V blank interrupt process according to the V blank interrupt based on the interrupt signal output from the VDP 81 at a predetermined timing. In the V blank interrupt processing, for example, processing for selecting a CGROM storing predetermined image data for image display from a plurality of CGROMs 82 to 84, reading predetermined image data from the selected CGROM to the VDP 81, and VRAM 85 And a process of selecting an audio data ROM storing predetermined audio data to be output from a plurality of audio data ROMs (see FIG. 3). The specific contents of the V blank interrupt process will be described in detail later with reference to FIG.

  The effect control process execution means 101D confirms whether or not the effect control command analyzed by the command analysis means 101B is an effect control command for designating a variation pattern. If the effect control command is an effect control command with a change pattern specified, the effect control process execution means 101D performs a notice effect that informs the player that the game will be a big hit or reach (that is likely). Whether or not it is supposed to be performed and the effect mode of the notice effect when it is performed are determined, the effect means used for the notice effect is selected, and the effect mode is determined. Then, the production control process execution means 101D selects the process data 102A corresponding to the variation pattern. In the process data 102A, in order to cause a plurality of types of rendering means (variable display device 9 or the like) to perform a certain aspect of rendering in each period divided into a plurality of periods in a variation time of a predetermined variation pattern. Is set (see FIG. 8).

  The effect control process execution means 101D executes control of a plurality of types of effect means before, during and after the change of the special symbol according to the contents of the process data 102A selected according to the change pattern. For example, control is performed to display an image during the change of the special symbol corresponding to the change pattern on the display screen of the variable display device 9. At this time, a command signal for displaying an image on the display screen of the variable display device 9 (including the display of the start winning memory) is output to the VDP 81. In addition, for example, control is performed to perform audio output from a speaker during the change of a special symbol corresponding to the change pattern. At this time, a command signal for outputting sound from the speaker is output to the speech synthesis IC (see FIG. 3) on the speech output board via the driver 110. The effect control process execution means 101D displays a big hit on the variable display device 9 when the big win is reached after the end of the variation time, and performs control during the big hit game (for example, display control of the number of rounds, etc.).

  Command receiving means 101A, command analyzing means 101B, V blank interruption process executing means 101C and effect control process executing means 101D are realized as processes executed by effect control CPU 101 in accordance with a program or the like. The process data 102A is stored in the ROM 102.

  The VDP 81 reads image data stored in any of the three CGROMs 82 to 84 based on a command signal from the effect control CPU 101, transfers the read image data to the VRAM 85, and displays the image data in the display area in the VRAM 85. Expand to a predetermined area outside. Based on the command signal from the effect control CPU 101, the VDP 81 develops the image data developed in a predetermined area in the VRAM 85 in the display area and displays the image on the display screen of the variable display device 9. The term “development” refers to writing image data at a designated position in the VRAM 85, which is also called drawing. The display area is an area corresponding to the display screen of the variable display device 9 secured in the two-dimensional space area in the VRAM 85, and is also referred to as a drawing area. The image data developed in the display area in the VRAM 85 is output to the variable display device 9, and an image corresponding to the image data is displayed on the display screen.

  Of the three CGROMs 82 to 84, the CGROM (A) 82 stores a plurality of types of image data such as special symbols, characters, and backgrounds that are frequently used. As the character, for example, a person, an animal, or a character, a figure, a symbol, or the like is used. In this embodiment, sprite images are used for special symbols, characters, and backgrounds that are frequently used. The CGROM (B) 83 and the CGROM (B ′) 84 store image data of a plurality of types of movie images (videos). Image data of a movie image (hereinafter referred to as movie image data) is used for special effects such as a reach effect or a big hit effect. In this embodiment, CGROM (B) 83 and CGROM (B ′) are distinguished for each effect used, such as movie image data used at the reach effect and movie image data used at the jackpot game effect. 84 is stored in the storage area.

  The VRAM 85 is realized using, for example, an SDRAM. The VRAM 85 stores data relating to a display image such as a frame buffer, image source data, palette data used for specifying or changing display colors, and the like. The source data is image data, and is expressed as source data in the sense of original image data.

  FIG. 3 is a block diagram illustrating a configuration example of an effect control board, a lamp driver board, and an audio output board. In the effect control means, as described above, the effect control microcomputer 100 receives an effect control command for designating a variation pattern or the like transmitted from the game control means. Further, the production control microcomputer 100 outputs sound number data to the sound output board 70 via the driver 110 in accordance with the contents of the process data 102A selected according to the variation pattern. Further, the production control microcomputer 100 outputs lighting instruction information to the lamp driver board 35 via the driver 105 in accordance with the content of the process data 102A selected according to the variation pattern.

  As shown in FIG. 3, the lamp driver substrate 35 includes a lamp driver 351 and an LED drive circuit 352. When the lamp / LED lighting instruction information corresponding to the content of the process data 102A output from the driver 105 of the effect control board 80 is input to the lamp driver board 35, the lamp driver 351 selects each lamp based on the lighting instruction information. A signal for driving is supplied to each lamp, and the LED drive circuit 352 supplies a signal for driving each LED to each LED based on the lighting instruction information. As described above, in this embodiment, lighting / extinguishing of the lamps / LEDs provided in the gaming machine is such that the production control means outputs lighting instruction information to the lamp driver board 35 in accordance with the contents of the process data 102A. Controlled by.

  As shown in FIG. 3, the audio output board 70 includes an audio synthesis IC (for example, a digital signal processor) 701, three audio data ROMs 702 to 704, an amplifier circuit 705, and a volume 706. In the voice output board 70, the sound number data corresponding to the contents of the process data 102A output from the driver 110 of the effect control board 80 is input to the voice synthesis IC 701. The voice synthesis IC 701 reads voice data corresponding to the sound number data from any of the three voice data ROMs 702 to 704, generates a voice or sound effect corresponding to the read voice data, and outputs it to the amplifier circuit 705. The amplification circuit 705 outputs an audio signal obtained by amplifying the output level of the voice synthesis IC 701 to a level corresponding to the volume set by the volume 706 to the speaker 27. Thus, in this embodiment, the sound output from the speaker 27 is controlled by the effect control means outputting the sound number data to the sound output board 70 in accordance with the contents of the process data 102A.

  The sound data corresponding to the sound number data stored in the three sound data ROMs 702 to 704 is a collection of data indicating the sound effect or sound output mode in a predetermined period (for example, a special symbol fluctuation period) in a time series. is there. When voice number data is input, the voice synthesis IC 701 performs sound output control according to the voice data corresponding to the voice number data stored in one of the three voice data ROMs 702 to 704. The sound output control according to the sound data corresponding to the sound number data is continued until the next sound number data is input. When the next sound number data is input, the speech synthesis IC 701 performs sound output control according to the sound data in the sound data ROMs 702 to 704 corresponding to the newly input sound number data.

  The three sound data ROMs 702 to 704 store a large number of sound data for realizing sounds and sound effects that may appear as the game progresses, and these sound data are associated with sound number data. . Therefore, the production control means can realize the audio output control only by outputting the sound number data to the audio output board 70. Note that the sound number data is, for example, 1-byte data and is transferred to the audio output board 70 via a serial signal line or a parallel signal line.

  Of the three audio data ROMs 702 to 704, the audio data ROM (A) 702 is, for example, a normal effect during a special symbol change (an effect other than a reach effect executed during a special symbol change) or a notice effect (a special symbol). Before the derivation display, a plurality of types of frequently used voice data such as voices and sound effects used at the time of presentation or the like for notifying the player of the occurrence of a big hit or reach are stored. In this embodiment, audio data used during normal production, audio data used during announcement production, and the like are distinguished for each production used and stored in the audio data ROM (A) 702. Also, the voice data (B) 703 and the voice data (B ′) 704 are not used frequently such as voices and sound effects used at the time of a reach effect or a big hit game effect during a special symbol change. Stores multiple types of special audio data. In this embodiment, the voice data ROM (B) 703 and the voice data ROM (B) are distinguished for each used effect, such as the audio data used during the reach effect and the audio data used during the jackpot game effect. ') Is stored in 704.

  It should be noted that the temporary stop timing and variation time of the special symbol displayed on the variable display device 9 are uniquely determined according to the effect control command for designating the variation pattern from the game control means. In other words, the effect control means, from the timing of receiving the effect control command specified by the variation pattern until the time of change corresponding to the received effect control command specified by the variation pattern has elapsed, The control is executed so that the sound output from 27 and the lamp / LED blinking display are performed in conjunction with each other.

  FIG. 4 is a wiring diagram showing the connection relationship of signal lines among the three CGROMs, CPUs and VDPs. As shown in FIG. 4, the VDP 81 is connected to a CPU bus (external bus) to which the presentation control CPU 101 is connected. The effect control CPU 101 outputs a control signal (command signal) to the VDP 81 via the CPU bus. The control signal instructs to read out the image data (image source data) stored in any of the three CGROMs 82 to 84 and expand it to a predetermined area outside the drawing area (display area) in the VRAM 85. Information, information for instructing development of image data developed in a predetermined area outside the drawing area in the VRAM 85 to the drawing area, and the like. As a signal line for connecting the effect control CPU 101 and the VDP 81, there is a signal line for transmitting an interrupt signal for the VDP 81 to cause the effect control CPU 101 to execute the V blank interrupt process. Is not shown.

  Three CGROMs 82 to 84 and the VDP 81 are connected by an address bus. The address bus transmits an address signal for designating the head address of the storage area in the CGROMs 82 to 84 for the image data read by the VDP 81. In this embodiment, the address bus has a 25-bit bus width (25 signal lines). Therefore, the address range (address space) that can be specified by the address bus is 32 M (33554432 = 25th power of “2”) bytes, that is, 256 Mbits, when an address is assigned for each byte. However, in this embodiment, the signal line of the most significant bit (25th bit) of the address bus is a signal line for transmitting a chip select (2) signal for selecting the CGROM accessed by the VDP 81. Therefore, in practice, the address bus for transmitting the address signal to each CGROM has a bus width of 24 bits.

  As shown in FIG. 4, the 25th bit signal line branches off at two points along the way. One branch line from the first branch point viewed from the VDP 81 side is connected to the CE ￣ terminal (CE: Chip enable input) and the OE ￣ terminal (OE: Output enable input) of the CGROM (A) 82. Has been. The other signal line from the first branch point (that is, between the first branch point and the second branch point) has an inverter (inverting circuit) that reverses the polarity of the signal. It is connected. Both branch lines from the second branch point are connected to the OE terminal of CGROM (B) 83 and CGROM (B ') 84, respectively. Here, when both signals output to the CEＣ terminal and the OE￣ terminal of the CGROM are at a low level, the CGROM is in an accessible state of the VDP 81, that is, a state in which image data can be read out.

  Therefore, when the chip select (2) signal from the VDP 81 is at a low level, the low level signal is output to the CE￣ terminal and the OE￣ terminal of the CGROM (A) 82. (A) 82 is selected. At this time, since the chip select (2) signal output to the OE terminal of CGROM (B) 83 and CGROM (B ′) 84 is a high level signal whose polarity is inverted by the inverter, CGROM (B) 83 Neither CGROM (B ′) 84 was selected. Conversely, when the chip select (2) signal from the VDP 81 is at a high level, a low level signal whose polarity is inverted by the inverter is output to the OE terminal of the CGROM (B) 83 and CGROM (B ′) 84. Therefore, CGROM (B) 83 and CGROM (B ′) 84 are selected as CGROMs to be accessed by the VDP 81. At this time, since the chip select (2) signal output to the CE￣ and OE￣ terminals of the CGROM (A) 82 is a high level signal, the CGROM (A) 82 is not selected.

  The signal line connecting the CPU 101 for effect control and the CGROM (B) 83 and CGROM (B ′) 84 selects either CGROM (B) 83 or CGROM (B ′) 84 as the CGROM accessed by the VDP 81. This is a signal line for transmitting a chip select (1) signal for the purpose. This signal line branches off in the middle. One branch line from the branch point is connected to the CE terminal of CGROM (B) 83 via an inverter that inverts the polarity of the signal, and the other branch line is connected to CGROM (B ′) 84 without going through the inverter. Connected to the CE terminal.

  Therefore, when the chip select (1) signal from the CPU 101 for effect control is at a high level, a low level signal whose polarity is inverted by the inverter is output to the CE terminal of the CGROM (B) 83. If the chip select (2) signal output to the OE terminal of the CGROM (B) 83 is at a low level, the CGROM (B) 83 is selected as the CGROM accessed by the VDP 81. At this time, since the chip select (1) signal output to the CE terminal of the CGROM (B ') 84 is at a high level, the CGROM (B') 84 is not selected. On the contrary, when the chip select (1) signal from the CPU 101 for effect control is low level, the low level signal is output to the CEＣ terminal of the CGROM (B ′) 84. At this time, CGROM (B ′ ) If the chip select (2) signal output to the OE terminal of 84 is at a low level, CGROM (B ′) 84 is selected as the CGROM to be accessed by the VDP 81. At this time, since the polarity of the chip select (1) signal output to the CE terminal of the CGROM (B) 83 is inverted by the inverter and becomes high level, the CGROM (B) 83 is not selected. Become.

  Further, the three CGROMs 82 to 84 and the VDP 81 are connected by a data bus. The data bus transmits image data read from any of the three CGROMs 82 to 83. In this embodiment, the data bus has an 8-bit bus width (eight signal lines).

  As described above, the CGROM accessed by the VDP 81 is selected depending on the signal level (high level and low level) of the chip select (1) signal and the chip select (2) signal, and image data is read from the selected CGROM. Becomes valid (possible). That is, whether the CGROM to be accessed is CGROM (A) 82, CGROM (B) 83, or CGROM (B ') 84 is selected according to the state of the chip select (2) signal. If the selected CGROM is CGROM (B) 83 or CGROM (B ′) 84, the CGROM to be accessed is CGROM (B) 83 or CGROM (B) depending on the state of the chip select (1) signal. ') Is selected as 84. When the CGGROM selected by the state of the chip select (2) signal is CGROM (A) 82, CGROM (B) 83 and CGROM (B ') 84 are used regardless of the state of the chip select (1) signal. Is not selected.

  Since the chip select (1) signal and the chip select (2) signal are binary signals of a high level and a low level, the states of the high level and the low level are the same as the digital data “1” and “0”. .

  Further, as a signal line between the VDP 81 and the three CGROMs 82 to 84, in addition to the signal line shown in FIG. 4, a signal line for transmitting a write enable signal from the VDP 81 and a read enable signal from the VDP 81 are transmitted. Although not shown in FIG.

  4 shows the signal line connection relationship among the three CGROMs 82 to 84, the production control CPU 101 and the VDP 81, the three audio data ROMs 702 to 704, the production control CPU 101 and the voice synthesis IC 701 are connected. The signal lines between each other are also connected in the same connection relationship as shown in FIG. Accordingly, as in the above case, the audio data ROM accessed by the speech synthesis IC 701 is selected according to the signal level state of the chip select (1) signal and the chip select (2) signal, and the selected audio data ROM is selected. The audio data can be read (enabled). Incidentally, since image data and audio data have different data capacities, the maximum data capacity of the audio data ROM is generally different from the maximum data capacity of the CGROM. Therefore, the bus width (number of signal lines) of the address bus or data bus may be different from the bus width shown in FIG.

  FIG. 5 is an explanatory diagram showing address maps of three CGROMs and image data storage areas in the three CGROMs. As shown in FIG. 5, the CGROM (A) 82 is assigned an address in the range of “0000000h” to “0FFFFFFh”. The same address in the range of “1000000h” to “1FFFFFFh” is assigned to CGROM (B) 83 and CGROM (B ′) 84. Note that “h” at the end of the number indicates that the numerical notation is a hexadecimal number having a value of “0” to “F” (that is, one number is 4 bits).

  The numerical value of the lower six digits (“000000h” to “FFFFFFh”) out of the seven digits indicating the address corresponds to an address space (16 Mbytes) that can be specified by a 24-bit address bus. The numerical value of “0” or “1” in the most significant digit (seventh digit) is the data of the chip select (2) signal that can be specified by the signal line of the most significant bit (25th bit) of the address bus. Equivalent to. As described with reference to FIG. 4, when the chip select (2) signal is low level (ie, “0”), CGROM (A) 82 is selected, and the chip select (2) signal is high level (ie, “1”). At that time, CGROM (B) 83 or CGROM (B ′) 84 was selected. This means that when the address specified by the 25-bit address signal is within the range of “0000000h” to “0FFFFFFh”, the address specifies the data storage area in the CGROM (A) 82 and the address is “1000000h”. When it is within the range of “1FFFFFFh”, the address is the same as specifying the data storage area in CGROM (B) 83 or CGROM (B ′) 84.

  In the three CGROMs 82 to 84 as a whole, the allocated address range is “0000000h” to “1FFFFFFh”, which corresponds to an address space of 32 Mbytes (that is, 256 Mbits) that can be specified by a 25-bit address bus. To do. However, as described in FIG. 4, either CGROM (B) 83 or CGROM (B ′) 84 is selected by the chip select (1) signal from the CPU 101 for effect control, as shown in FIG. In addition, the same address is assigned to CGROM (B) 83 and CGROM (B ′) 84. Therefore, as described above, the address space that can be originally specified by the 25-bit address bus is 32 Mbytes, and the maximum data capacity of the entire three CGROMs 82 to 84 should be 32 Mbytes. The maximum data capacity in the entire CGROMs 82 to 84 is 48 Mbytes (16M × 3 bytes). That is, the data capacity is 3/2 times (1.5 times) of 32 Mbytes. With such a configuration, the data capacity of image data that can be read by the VDP 81 is increased without using a high-performance VDP 81 that can access a wide address space.

  As described above, the CGROM (A) 82 stores a plurality of types of image data (1) to (n) that are frequently used. As the frequently used image data (1) to (n), for example, as shown in FIG. 6, for example, special symbols that are always used in effects during symbol variation (“7”, “2”, “8” in FIG. 6) , Image data of a character that frequently appears in the notice effect ("UFO" notice character in FIG. 6), image data of the background ("cloud" in FIG. 6), and start memory display area 18 Image data of a hold display (circular figure in FIG. 6). As shown in FIG. 5, the image data (1) to (n) is distinguished for each image and stored in a storage area in the CGROM (A) 82. Since sprite images are used for the image data (1) to (n), the capacity of one image data is relatively small (compared to movie image data). The image data (1) to (n) stored in the CGROM (A) 82 may or may not be compressed, and the image data (1) to (n) ) May be compressed. Image data (1) to (n) of such frequently used images is referred to as high frequency data.

  As described above, the CGROM (B) 83 and the CGROM (B ′) 84 store a plurality of types of movie image data (1) to (6). Movie image data (1) to (6) are used for special effects such as a reach effect or a big hit effect. As shown in FIG. 5, the movie image data (1) to (3) are stored in the storage area in the CGROM (B) 83 while being distinguished for each different effect. Also, the movie image data (4) to (6) are stored in the storage area in the CGROM (B ′) 84 by being distinguished for each different effect.

  The movie image data (1) to (3) stored in the CGROM (B) 83 is immediately after the movie image data (4) to (6) stored in the CGROM (B ′) 84 is used for production. The movie image data (4) to (6) stored in the CGROM (B ′) 84 is not used for the movie image data (1) to (6) stored in the CGROM (B) 83. Each movie image data (1) to (6) is distributed and stored in CGROM (B) 83 and CGROM (B ′) 84 so that (3) is not used immediately after the production is used. Yes.

  For example, when the movie image data (1) is data used for reach production and the movie image data (4) is data used for super reach production, the movie image data (1) is used for reach production. Immediately after that, the movie image data (4) is prevented from being used in the super reach effect in the same variable display. As another example, when the movie image data (1) is data used for a reach effect and the movie image data (4) is data used for a jackpot effect, the movie image data (1) is used for a reach effect. Immediately after being received, the movie image data (4) is prevented from being used in the big hit effect. If the movie image data (4) is read immediately after the movie image data (1) is read, the CGROM accessed by the chip select (1) signal must be switched as described above. There is a high possibility that a read error will occur. Therefore, the reading error is prevented as much as possible by preventing the reading of the movie image data (4) immediately after reading the movie image data (1).

  The movie image data (2) may be used for the production immediately after the movie image data (1) is used for the production. Since the movie image data (1) and (2) are stored in the same CGROM (B) 83, it is not necessary to switch the CGROM by the chip select (1) signal, and the possibility of erroneous reading is low. It is.

  An example of a movie image used for reach production is shown in FIG. The display example shown in FIG. 7 is a case where the final stop symbol (middle symbol) that is variably displayed after the left and right symbols are all aligned at “7” is displayed as a movie image in the special symbol reach production. Show. As shown in FIG. 7, when “6” approaches the stop position of the middle symbol (A), the reach effect by the movie image is started. As the first image in the movie image, a character image imitating “6” as shown in FIG. Then, a character imitating “7” as shown in (C) appears, and a moving image is reproduced in which the character imitating “6” is expelled from the display area of the movie image. Then, the character imitating “6” has completely disappeared from the display area of the movie image, and the character imitating “7” that has expelled the character imitating “6” is the center position of the movie image display area (for example, The video that moves to the symbol stop position is played back. Finally, as shown in (D), an image is displayed in which the character imitating “7” faces the front at the center position of the display area of the movie image. When the final image (D) of the movie images is displayed, the reach effect by the movie image ends. In the example shown in FIG. 7, it is a big hit because it stops at the symbol “7”.

  Although FIG. 5 shows the address map of the three CGROMs 82 to 84 and the storage area of the image data in the three CGROMs 82 to 84, the address map of the three audio data ROMs 702 to 704 and the address map of the three audio data ROMs 702 to 704 are shown. The storage area of the audio data can also be realized with the same configuration as that shown in FIG. Incidentally, since image data and audio data have different data capacities, the maximum data capacity of the audio data ROM is generally different from the maximum data capacity of the CGROM. Therefore, the range of addresses assigned to the audio data ROMs 702 to 704 may be different from the range of addresses assigned to the CGROMs 82 to 84 shown in FIG.

  FIG. 8 is an explanatory diagram showing a configuration example of process data. The process data 102A is composed of data in which a plurality of combinations of process timer set values and effect control execution tables are collected. In each effect control execution table, display control execution data in which data indicating the contents of display effects on the display screen of the variable display device 9 is set, and data indicating the contents of effects by lamps / LEDs, etc. are set. Lamp control execution data, and sound control execution data in which data indicating the content of audio output control of the speaker 27 is set. In addition, the process timer set value is set with a time period during which presentation control is performed based on display control execution data, lamp control execution data, and sound control execution data that immediately follow. The time obtained by adding the process timer set values of the process data 1 to n is the variation time in the variation pattern.

  The effect control CPU 101 refers to the process data, and displays the design depending on the effect set in the display control execution data, lamp control execution data, and sound control execution data immediately following the time set in the process timer set value. Is controlled to be displayed in a variable manner, the light emitter is turned on / off, and the sound is output from the speaker 27.

  Specifically, the display control execution data includes data (address information of the image data in the CGROM) indicating the start address of the storage area in the CGROMs 82 to 84 of the source data of the image transferred outside the drawing area of the VRAM 85. ing. Here, in the description of FIG. 5 described above, the same address is assigned to the CGROM (B) 83 and the CGROM (B ′) 84 as the addresses specified by the VDP 81 using the address signal. That is, the address space of the CGROM (B) 83 and the address space of the CGROM (B ′) 84 coincided. However, in the address information set in the display control execution data, it is assumed that consecutive addresses different from CGROM (B) 83 and CGROM (B ′) 84 are assigned. For example, CGROM (B) 83 is assigned an address in the range of “1000000h” to “1FFFFFFh”, and CGROM (B ′) 84 is assigned an address in the range of “2000000h” to “2FFFFFFh”. Yes. Therefore, the effect control CPU 101 can recognize whether the predetermined movie image data is stored in the CGROM (B) 83 or the CGROM (B ′) 84 based on the address information. In the address information of the display control execution data, the address assigned to the CGROM (A) 82 is, for example, in the range of “0000000h” to “0FFFFFFh” as in the case shown in FIG.

  In addition, the display control execution data includes the types of component images (sprites) such as backgrounds, symbols, characters, etc. constituting each frame variably displayed on the variable display device 9 (one image as a unit constituting a moving image). Image, movie image), position, and size data are included. In addition, when a predetermined part image is displayed in a deformed manner, data (a reduction / enlargement rate, a rotation rate) indicating the deformation mode (for example, reduction, enlargement, or rotation) is also included. When a movie image is included in the frame, the data indicating the position, size, and deformation mode of the image is data indicating the position, size, and deformation mode of the movie image display area in which the movie image is displayed as a moving image.

  For example, data indicating a light emission pattern of a lamp / LED is set in the lamp control execution data. For example, data indicating a sound output pattern from the speaker 27 is set in the sound control execution data. The sound control execution data also includes data (address information in the sound data ROM of the sound data) indicating the start address of the storage area in the sound data ROMs 702 to 704 of the sound data. Also in the address information set in the sound control execution data, different continuous addresses are assigned to the voice data ROM (B) 703 and the voice data ROM (B ′) 704.

  The process timer setting value in the process data 102A illustrated in FIG. 8 is set to a multiple of 33.3 ms when the frame frequency of the image displayed on the variable display device 9 is 30 Hz. When the frequency is 60 Hz, a value that is a multiple of 16.7 ms is set. In other words, the CPU 101 for effect control uses 33.3 ms or 16.7 ms as a unit for drawing control to the VRAM 85, lamp / LED light emission pattern switching control (control to turn on / off), and sound from the speaker 27. Execute output control.

  The process data 102A shown in FIG. 8 is stored in the ROM 102 in the effect control means. The process data 102A is prepared for each variation pattern. As described above, the effect control process execution means 101D in the effect control microcomputer 100 selects the process data 102A in accordance with the effect control command specifying the variation pattern transmitted from the game control means, and the selected process data 10A. Control of the variable display device 9, the lamp / LED and the speaker 27 is started based on each control execution data. And in V blank interruption, control according to each control execution data is performed sequentially.

  FIG. 9 is a flowchart showing the V blank interrupt process executed by the effect control CPU 101 in response to the V blank interrupt from the VDP 81. The V blank interrupt is an interrupt generated by the VDP 81 in the same cycle as that of the vertical synchronizing signal supplied to the variable display device 9. For example, when the screen change frequency (frame frequency) of the variable display device 9 is 30 Hz, the generation period of the V blank interrupt is 33.3 ms, and when the frame frequency is 60 Hz, the occurrence of the V blank interrupt is generated. The period is 16.7 ms.

  In the V blank interrupt process, the V blank interrupt process execution means 101C (that is, the effect control CPU 101) determines whether or not the necessary part image source data is in the VRAM 85 (the transfer destination area outside the drawing area) ( Step S201). The necessary component image source data is the component image source data handled in step S214.

  If the required part image is not in the VRAM 85, the V blank interrupt process execution means 101C refers to the address information of the display control execution data and confirms the CGROM in which the source data of the required part image is stored ( Step S202). Specifically, the V blank interrupt process execution unit 101C determines that the value of the address “n” when the address of the necessary part image source data in the address information of the display control execution data is “nXXXXXXXh”. Confirm. If the value of “n” is “0”, the V blank interrupt process execution unit 101C determines that the source data is stored in the CGROM (A) 82, and the value of “n” is “1”. If it is, it is determined that the source data is stored in the CGROM (B) 83, and if the value of “n” is “2”, it is determined that the source data is stored in the CGROM (B ′) 84.

  The V blank interrupt process execution means 101C determines whether or not the necessary part image source data is stored in the CGROM (B) 83 (step S203). When the necessary part image source data is stored in the CGROM (B) 83 (specifically, when the address information of the part image source data is within the range of “1000000h” to “1FFFFFFh”), V The blank interrupt processing execution means 101C turns on the chip select (1) signal (sets it to high level) (step S204), reads the necessary source data of the component image from the CGROM (B) 83, and reads the read source. Control is performed to transfer the data to the VRAM 85 and develop it in the transfer destination area outside the drawing area in the VRAM 85 (step S205).

  In addition, when the source data of the necessary component image is stored in the CGROM (B ′) 84 (specifically, when the address information of the source data of the component image is within the range of “2000000h” to “2FFFFFFh”) The V blank interrupt processing execution means 101C reads the necessary component image source data from the CGROM (B ′) 84 without turning on the chip select (1) signal (as a low level), and reads the read source data. Control is performed to transfer the data to the VRAM 85 and develop it in the transfer destination area outside the drawing area in the VRAM 85 (step S205).

  Further, when necessary source images of component images are not stored in the CGROM (B) 83 and the CGROM (B ′) 84 but are stored in the CGROM (A) 82 (specifically, the source data of the component images) Similarly, when the address information is in the range of “0000000h” to “0FFFFFFh”, the V blank interrupt processing execution means 101C is necessary without turning on the chip select (1) signal (as a low level). The source data of the component image is read from the CGROM (A) 82, the read source data is transferred to the VRAM 85, and control is performed to develop it in the transfer destination area outside the drawing area in the VRAM 85 (step S205).

  As a specific process of step S205, the V blank interruption process execution means 101C (production control CPU 101) outputs the address information of the source data of the component image set in the display control execution data and out of the drawing area of the VRAM 85 from the CGROM. Information for instructing transfer of source data to the VDP 81 is output to the VDP 81.

  Note that the address information output to the VDP 81 by the V blank interrupt process execution unit 101C is an address within a range that the VDP 81 can specify with a 25-bit address bus. That is, when the V blank interrupt process execution means 101C designates the address of the storage area in the CGROM (A) 82 and CGROM (B) 83 for the VDP 81, the address information (“ “0000000h” to “0FFFFFFh” and “1000000h” to “1FFFFFFh”) may be specified as they are, but when specifying the address of the storage area in the CGROM (B ′) 84, address information (“2000000h” to “2FFFFFFh”) ), It is impossible for the VDP 81 to specify such an address with a 25-bit address bus (a 26-bit address bus is required). Therefore, when the address of the storage area in the CGROM (B ′) 84 is designated, the V blank interrupt process execution unit 101C corresponds the address information (“2000000h” to “2FFFFFFh”) to the CGROM (B) 83. Address information ("1000000h" to "1FFFFFFh") to be specified. At this time, the lower 6 digits (24 bits) indicating the address are not changed.

  In step S205, when the source data of the component image read from the CGROM is encoded (in the case of movie image data), the V blank interrupt process execution unit 101C instructs execution of decoding of the source data. Information is output to the VDP 81.

  Next, the V blank interrupt process execution means 101C refers to the address information of the display control execution data, and confirms the audio data ROM in which necessary audio data is stored (step S206). Note that the necessary audio data is the audio data handled in step S216. As a specific process, as described above, when the V blank interrupt process execution unit 101C determines that the address of the source data of the necessary component image in the address information of the display control execution data is “nXXXXh” Is performed by confirming the value of the address “n”.

  The V blank interrupt process execution means 101C determines whether or not necessary audio data is stored in the audio data ROM (B) 703 (step S207). If the necessary audio data is stored in the audio data ROM (B) 703, the V blank interrupt processing execution means 101C turns on the chip select (1) signal (sets it to the high level) (step S208). .

  If the necessary audio data is not stored in the audio data ROM (B) 703 but is stored in the audio data ROM (B ′) 704 or the audio data ROM (A) 702, the V blank interrupt process is executed. The means 101C does not turn on the chip select (1) signal (leave it at the low level).

  Next, when the process data valid flag (flag indicating that the presentation control based on the process data 102A is performed) is set (step S209), the V blank interrupt process execution unit 101C sets the process timer. The value is decremented by -1 (step S210). When the value of the process timer becomes 0, that is, when the process timer times out (step S211), the control execution data in the process data 102A is switched (step S212). Specifically, the value of the process data pointer is incremented by +4. Therefore, the process data pointer points to the next process timer set value (see FIG. 8). It should be noted that the value of the process timer is not decremented by 1 since the process timer has not yet started at the start of the special symbol fluctuation. Further, in the control execution data switching, the value of the process data pointer is set to an initial value (a value indicating the first process timer set value). Next, the V blank interrupt process execution unit 101C sets the process timer set value pointed to by the process data pointer in the process timer, and starts the process timer (step S213).

  The V blank interrupt processing execution means 101C loads the contents of the display control execution data set in the area next to the area pointed to by the process data pointer (the area where the process timer set value is set), and displays the display control. In accordance with the contents of the execution data, image development instruction information is set in a register in the CPU (step S214). More specifically, when data for instructing drawing of a component image, that is, development into a drawing area of the VRAM 85 is set as display control execution data, the V blank interrupt process execution means 101C relates to the component image. Data of predetermined parameters such as a development position, a size, and a deformation mode are set in a register in the CPU, and information for instructing drawing in the drawing area of the VRAM 85 is set in a register in the CPU.

  Next, the V blank interrupt processing execution means 101C loads the content of the lamp control execution data set in the area next to the area pointed to by the process data pointer (area where the display control execution data is set), According to the content of the lamp control execution data, lamp / LED lighting instruction information is set in a register in the CPU (step S215). Specifically, when data for instructing lighting / extinguishing of various lamps / LEDs is set as the lamp control execution data, the V blank interrupt process execution means 101C selects the lamps / LEDs to be turned on / off, Information related to the timing of turning on / off is set in a register in the CPU.

  Next, the V blank interrupt process execution means 101C loads the content of the sound control execution data set in the area next to the area pointed to by the process data pointer (area where the lamp control execution data is set), In accordance with the contents of the sound control execution data, the sound output instruction information is set in a register inside the CPU (step S216). Specifically, when data for instructing voice output is set as the sound control execution data, the V blank interrupt processing execution means 101C performs a voice output instruction for designating sound number data according to the variation pattern. Information is set in a register in the CPU.

  Thereafter, each instruction information (image development instruction information, lamp / LED lighting instruction information, audio output instruction information) is already set in the internal register of the CPU by the above-described steps S214 to S216. Check if it exists. When each instruction information (at least one of them) is set, the effect control process execution means 101D outputs each instruction information to a predetermined effect means.

  Specifically, when image expansion instruction information is set, the expansion instruction information is output to the VDP 81. When the lamp / LED lighting instruction information is set, the lighting instruction information is output to the lamp driver board 35 via the driver 105. When the voice output instruction information is set, the sound number data corresponding to the variation pattern designated by the voice output instruction information is output to the voice output board 70 via the driver 110.

  FIG. 10 is a flowchart showing the image reading and developing process executed by the VDP 81. First, in step S205, the VDP 81 checks whether or not there has been an instruction to develop image data (source data) into the VRAM 85 from the V blank interrupt process execution unit 101C (step S221). If there is an instruction for expansion, the VDP 81 is designated by whether or not the image data of the component image is stored in the CGROM (A) 82, that is, by the address information from the V blank interrupt processing execution means 101C. It is determined whether or not the address is in the range of “0000000h” to “0FFFFFFFh” (step S222).

  When the image data of the component image is stored in the CGROM (A) 82, the VDP 81 does not turn on the chip select (2) signal (leave it at the low level). On the other hand, when the image data of the component image is not stored in the CGROM (A) 82, it is stored in either the CGROM (B) 83 or the CGROM (B ′) 84. ) The signal is turned on (high level) (step S223). At this time, if the image data is stored in the CGROM (B) 83, the chip select (1) signal is already turned on, and the image data is stored in the CGROM (B ′) 84. For example, the chip select (1) signal is turned off (see steps S203 and S204).

  Next, the VDP 81 outputs one of the CGROMs 82 to 84 by outputting an address signal designating the address designated by the address information from the V blank interrupt process execution means 101C to the CGROMs 82 to 84 via the address bus. Then, the image data of the component image is read out (step S224). At this time, image data is read from the CGROM in which both the CE￣ terminal and the OE￣ terminal are at the low level.

  The CGROM in which both the CE￣ terminal and the OE￣ terminal are at the low level, when the address signal is input, confirms that the CE￣ terminal is at the low level, and then the OE￣ terminal is at the low level. Confirm. Then, the image data stored in the storage area of the address specified by the address signal is output from the output terminal (DATA) via the data bus.

  Next, the VDP 81 checks whether or not the read image data is compressed (encoded), that is, whether or not a decoding execution instruction is output from the V blank interrupt processing execution unit 101C (step S225). . If the image data is compressed, the image data expansion process is executed (step S226). The VDP 81 expands the image data outside the drawing area of the VRAM 85 to the drawing area, creates an image signal based on the image data in the drawing area, outputs the image signal to the variable display device (LCD) 9, and outputs the image signal. Is displayed on the display screen of the variable display device 9 (step S227). Note that the processing for deforming (enlarging, reducing, rotating, etc.) the image is executed when the image data is expanded in the drawing area.

  The sound output control process executed by the speech synthesis IC will be described. When the voice synthesis IC 701 inputs the sound number data corresponding to the variation pattern, the voice data corresponding to the sound number data is read from the voice data ROM (A) by referring to the address information from the V blank interrupt processing execution means 101C. Whether it is stored in 702 or not is determined. When voice data corresponding to the sound number data is stored in the voice data ROM (A) 702, the voice synthesis IC 701 does not turn on the chip select (2) signal (leave it at the low level), and the voice data. Is not stored in the voice data ROM (A) 702, the voice synthesis IC 701 turns on the chip select (2) signal (sets it to high level). At this time, if the audio data is stored in the audio data ROM (B) 703, the chip select (1) signal has already been turned on, and the audio data is stored in the audio data ROM (B ′) 704. If so, the chip select (1) signal is off (see steps S207 and S208).

  The voice synthesis IC 701 outputs an address signal for designating an address designated by the address information from the V blank interrupt processing execution means 101C to the voice data ROMs 702 to 704 via the address bus, whereby the voice data ROM 702 is output. The audio data corresponding to the sound number data is read from any one of .about.704. At this time, audio data is read from the audio data ROM in which both the CE￣ terminal and the OE￣ terminal are at the low level.

  The audio data ROM in which both the CE￣ terminal and the OE￣ terminal are at the low level, when the address signal is input, confirms that the CE￣ terminal is at the low level, and then the OE 次 に terminal becomes the low level. Make sure. Then, the audio data stored in the storage area of the address specified by the address signal is output from the output terminal (DATA) via the data bus.

  The voice synthesis IC 701 generates voice and sound effects according to the voice data read from the voice data ROM, and outputs the voice and sound effects to the amplifier circuit 705. The amplification circuit 705 outputs an audio signal obtained by amplifying the output level of the voice synthesis IC 701 to a level corresponding to the volume set by the volume 706 to the speaker 27. In this way, sound is output from the speaker 27.

  As described above, in this embodiment, the production control CPU 101 (V blank interrupt processing execution means 101C) refers to the address information of the display control execution data and effectively reads out the image data by the chip select (1) signal. CGROM (B) 83 or CGROM (B ′) 84 to be selected, and VDP 81 outputs an address signal to CGROM (B) 83 and CGROM (B ′) 84 via an address bus having a predetermined bit width. Thus, the image data is read out from the storage area of the address designated by the address signal in the CGROM (B) 83 or CGROM (B ′) 84 validated by the chip select (1) signal. According to such a configuration, the capacity of image data that can be read by the VDP 81 can be doubled, and a high-performance VDP 81 is used because there is no need to increase the bit width (address space) of the address bus. There is no need to do so, and it is possible to avoid an increase in cost.

  Further, as shown in FIG. 5, in CGROM (B) 83 and CGROM (B ′) 84, images that are not used for presentation immediately after the image data stored in the other CGROM is used for presentation. Since each data is stored, it is possible to reduce the possibility of image data read errors.

  As shown in FIG. 4, the effect control CPU 101 and the CGROMs 83 and 84 are connected to a single signal line branched in the middle, and one branch line has an inverter that inverts the polarity of the signal. Provided, when one of the CGROMs 83 and 84 is in the input state of the chip select (1) signal, the other is wired so as to be in the non-input state of the chip select (1) signal. Wiring costs for connecting the control CPU 101 and the CGROMs 83 and 84 can be reduced.

  In addition to the CGROM (B) 83 and the CGROM (B ′) 84, a CGROM (A) 82 for storing high-frequency data, which is frequently used image data, is provided, which is designated by a control signal from the effect control CPU 101. When the read image data to be read is high-frequency data stored in the CGROM (A) 82, the VDP 81 selects the CGROM (A) 82 by the chip select (2) signal, and the CGROM (A) 82 On the other hand, by outputting an address signal via the address bus, the high frequency data is read from the storage area of the address designated by the address signal in the CGROM (A) 82, so that the content of the image data is CGROM can be used properly depending on whether it is used frequently. Further, by not storing the high frequency data in the CGROMs 83 and 84, it is possible to reduce the occurrence of a high frequency data read error.

  Further, as shown in FIG. 5, in the CGROM (B) 83 and the CGROM (B ′) 84, a plurality of types of movie image data corresponding to the effect are stored as image data separately for each effect. The use of movie image data according to the mode is facilitated and the capacity of the movie image data can be increased, and the entertainment of the game can be improved by performing effects using high-resolution images. it can.

  Note that the characteristic configuration as described above is not limited to the relationship among the effect control CPU 101, the VDP 81, and the CGROMs 82 to 84, but also applies to the relationship between the effect control CPU 101, the speech synthesis IC 701, and the sound data ROMs 702 to 704. Has been. Therefore, the above effects are also achieved in the relationship among the output control CPU 101, the speech synthesis IC 701, and the speech data ROMs 702 to 704.

  In the above embodiment, the two CGROMs 83 and 84 are provided as the data storage means. However, three or more CGROMs may be provided. By providing three or more CGROMs in this way, the maximum data capacity for storing movie image data can be further increased without expanding the address space. Also in this case, one of three or more CGROMs is selected by the chip select (1) signal.

  Further, although one CGROM (A) 82 is provided as the high frequency data storage means, two or more CGROMs may be provided. By providing two or more CGROMs in this way, the maximum data capacity for storing high frequency data can be further increased without expanding the address space. In order to realize this, for example, high frequency data may be stored in CGROM (B) 83 and CGROM (B ′) 84, and movie image data may be stored in CGROM (A) 82. (A) CGROM (A ′) may be provided separately from 82. However, in the latter case, CGROM (A) and CGROM (A ′) are selected by the chip select signal (signal different from the chip select (1) signal and the chip select (2) signal) from the CPU 101 for effect control. There is a need to.

  In FIG. 4, the signal line for transmitting the chip select (2) signal is connected to the CE terminal and the OE terminal of the CGROM (A) 82, but the signal line is connected only to the OE terminal. The CE terminal may be connected to a signal line connected to the ground (that is, the CE terminal may be grounded). Even with such wiring, the same operation as in the above embodiment can be performed.

  In FIG. 10, when the VDP 81 determines that the source data of the component image is not stored in the CGROM (A) 82 (N in step S222), the VDP 81 turns on the chip select (2) signal (step S222). In step S223, the address signal is output to the CGROM (B) 83 or CGROM (B ′) 84 (step S224). However, since the chip select (2) signal actually corresponds to the address signal transmitted through the 25th bit signal line of the address bus, the chip select (2) signal and the address signal are output to the CGROM at the same timing. The As shown in FIG. 10, the chip select (2) signal and the address signal may be output to the CGROM at different timings.

  Also, the bus width (number of signal lines) of the address bus is 25 bits (note that the most significant bit is the signal line for transmitting the chip select (2) signal), but is not limited to 25 bits. Further, the maximum data capacity of each CGROM 82 to 84 is not limited to 16 Mbytes. Furthermore, although the bus width of the data bus is 8 bits, it is not limited to 8 bits.

  Further, the CGROM is valid when the chip select (1) signal and the chip select (2) signal are low level, but the CGROM may be valid when it is high level.

  In addition, the production control CPU 101 stores the source data of each component image with reference to the address information (specifically, “n” in “nXXXXXXXh”) of each component image in the display control execution data of the process data 102A. However, the CGROM may be recognized based on other information (for example, information specifying the CGROM in which the part image is stored).

  The above-described modified example of the present invention is not limited to the relationship among the production control CPU 101, the VDP 81, and the CGROMs 82 to 84, but also in the relationship between the production control CPU 101, the voice synthesis IC 701, and the audio data ROMs 702 to 704. Applied.

  In the present invention, the “specific game state” means a state advantageous to a player who is given a predetermined game value. Specifically, the specific gaming state is, for example, a state in which the state of the variable winning ball apparatus is advantageous for a player who is easy to win a ball (a big hit gaming state), or a state in which a right to be advantageous for a player has occurred. A state in which a predetermined game value is given, such as a state where conditions for paying out premium game media are easily established.

  Further, in the present invention, the “continuous production” that the production control microcomputer causes the electrical component to execute is a plurality of special symbols from the start to the end (when the big hit, the big hit game ends). This refers to a series of effects continuously executed in a plurality of arbitrary periods among the periods divided into periods. In the above-described embodiment, as the “continuous production”, the super reach production after the reach production, the jackpot game production after the reach production, and the like are given. However, the present invention is not limited to such cases. Also included are reach production after the notice production. In addition, when the period for executing the reach effect or the big hit game effect can be divided into a plurality of periods, the effects executed in each divided period are also included. Data used for effects executed in each period divided in this way corresponds to “data for effects” in the present invention. In the embodiment described above, movie image data (1) to (6) is shown in FIG. 5 as an example of “production data”, but is not limited to movie image data. Data etc. are also included.

  The pachinko gaming machine 1 of the above embodiment can give a predetermined game value to a player when the special symbol stop symbol variably displayed on the special symbol display 9 based on the start winning prize becomes a predetermined symbol. The second type pachinko gaming machine that becomes a predetermined game value can be given to a player when there is a winning in a predetermined area of the electric game that is released based on the start winning Or a third type pachinko gaming machine in which a predetermined right is generated or continued when there is a prize for a predetermined electric accessory that is released when a stop symbol of the symbol variably displayed based on the start winning is a combination of the predetermined symbols Even so, the present invention can be applied. Further, the present invention is not limited to pachinko gaming machines in which the game medium is a game ball, and the present invention can also be applied to slot machines and the like.

  The present invention is applicable to a game such as a pachinko gaming machine, and in particular, it is necessary to use a processor that can increase the data capacity of a ROM provided in the gaming machine and can access a wide address space. This is useful for avoiding an increase in the cost of the gaming machine.

It is a front view which shows the front surface of the game board in a pachinko gaming machine. It is a block diagram which shows the structural example of a game control board and an effect control board. FIG. 4 is a block diagram illustrating a configuration example of an effect control board, a lamp driver board, and an audio output board. It is a wiring diagram which shows the connection relation of the signal line among three CGROM, CPU, and VDP. It is explanatory drawing which shows the storage area of the image map in the address map of three CGROMs, and three CGROMs. It is explanatory drawing which shows the example of a display of the image by a variable display apparatus. It is explanatory drawing which shows the example of a display of a movie image. It is explanatory drawing which shows the example of 1 structure of process data. It is a flowchart which shows V blank interruption processing. It is a flowchart which shows an image reading expansion | deployment process.

Explanation of symbols

9 Variable display devices (electric parts, variable display means, image display devices)
27 Speaker (electric parts)
31 Main board (game control means)
50 Microcomputer for game control 56 CPU
70 Audio output board 80 Production control board (production control means)
81 VDP (controller IC)
82-84 CGROM
85 VRAM (SDRAM)
100 effect control microcomputer 101 effect control CPU
701 IC for voice synthesis (controller IC)
702-704 Audio data ROM

Claims (5)

A gaming machine that controls a specific gaming state that is advantageous to the player when the player can execute a predetermined game and a specific result is obtained as a result of the predetermined game,
A plurality of data storage means for storing presentation data used to cause the electrical parts provided in the gaming machine to perform the presentation;
An effect control microcomputer that outputs a control command signal instructing to read out the effect data stored in the data storage means when the electric component is caused to produce an effect;
When the control command signal is input, the effect data stored in the address indicated by the control command signal among the addresses assigned to the data storage means is read, and the read effect data is used to read the effect data. A controller IC that causes the electrical component to perform a production,
The controller IC can read the production data for the plurality of data storage means for one address indicated by the control command signal,
The production control microcomputer, when the production data is executed using the production data stored in the plurality of data storage means, before outputting the control command signal to the controller IC. An enabling signal output for outputting an enabling signal for enabling reading of data from the data storing means to the data storing means storing the effect data used for execution of the present effect among the storing means Including means,
The gaming machine, wherein the controller IC reads out the effect data stored at an address assigned to data storage means to which the validation signal is input. When the effect control microcomputer causes the electrical component to execute a continuous effect, the plurality of effect data that the controller IC continuously reads are collectively stored in one data storage means among the plurality of data storage means. The gaming machine according to claim 1. The production control microcomputer switches between an input state in which the reading of the data of the enabling signal is enabled and a non-input state in which the reading of the data is not enabled, depending on the signal level in the single signal line
The plurality of data storage means are two of the first data storage means and the second data storage means,
In the first and second data storage means, a single signal line from the effect control microcomputer branches in the middle and is connected to each other, and one branch line inverts the signal level. Is provided,
The gaming machine according to claim 1 or 2, wherein when one of the first and second data storage means is in an input state of an enabling signal, the other is in an input state of an enabling signal. . The high-frequency data storage means for storing the production data that is read more frequently than the production data stored in the data storage means is provided separately from the plurality of data storage means. A gaming machine according to any of the above. The electrical component includes an image display device capable of displaying an image including a plurality of types of identification information that can identify each of the electrical components,
A plurality of data storage means store image data as effect data used for displaying an image on the image display device,
5. The controller IC is a microcontroller that reads out the image data from the plurality of data storage means and displays an image on the image display device using the read-out image data. 6. The gaming machine described in 1.

Images