JP2000021165A5 - - Google Patents

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Publication number
JP2000021165A5
JP2000021165A5 JP1998184483A JP18448398A JP2000021165A5 JP 2000021165 A5 JP2000021165 A5 JP 2000021165A5 JP 1998184483 A JP1998184483 A JP 1998184483A JP 18448398 A JP18448398 A JP 18448398A JP 2000021165 A5 JP2000021165 A5 JP 2000021165A5
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JP
Japan
Prior art keywords
clock signal
circuit
internal
signal
delayed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1998184483A
Other languages
English (en)
Japanese (ja)
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JP2000021165A (ja
JP4178225B2 (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP18448398A priority Critical patent/JP4178225B2/ja
Priority claimed from JP18448398A external-priority patent/JP4178225B2/ja
Priority to US09/304,516 priority patent/US6266294B1/en
Priority to KR1019990017075A priority patent/KR100329243B1/ko
Publication of JP2000021165A publication Critical patent/JP2000021165A/ja
Publication of JP2000021165A5 publication Critical patent/JP2000021165A5/ja
Application granted granted Critical
Publication of JP4178225B2 publication Critical patent/JP4178225B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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JP18448398A 1998-06-30 1998-06-30 集積回路装置 Expired - Lifetime JP4178225B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP18448398A JP4178225B2 (ja) 1998-06-30 1998-06-30 集積回路装置
US09/304,516 US6266294B1 (en) 1998-06-30 1999-05-04 Integrated circuit device
KR1019990017075A KR100329243B1 (ko) 1998-06-30 1999-05-13 집적 회로 장치

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18448398A JP4178225B2 (ja) 1998-06-30 1998-06-30 集積回路装置

Publications (3)

Publication Number Publication Date
JP2000021165A JP2000021165A (ja) 2000-01-21
JP2000021165A5 true JP2000021165A5 (enExample) 2004-12-16
JP4178225B2 JP4178225B2 (ja) 2008-11-12

Family

ID=16153974

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18448398A Expired - Lifetime JP4178225B2 (ja) 1998-06-30 1998-06-30 集積回路装置

Country Status (3)

Country Link
US (1) US6266294B1 (enExample)
JP (1) JP4178225B2 (enExample)
KR (1) KR100329243B1 (enExample)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4489231B2 (ja) * 2000-02-23 2010-06-23 富士通マイクロエレクトロニクス株式会社 遅延時間調整方法と遅延時間調整回路
JP4649081B2 (ja) * 2000-10-02 2011-03-09 キヤノン株式会社 周辺機器、その制御方法、プログラムおよび記憶媒体
US6480439B2 (en) * 2000-10-03 2002-11-12 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US6898683B2 (en) * 2000-12-19 2005-05-24 Fujitsu Limited Clock synchronized dynamic memory and clock synchronized integrated circuit
KR100413758B1 (ko) * 2001-03-26 2003-12-31 삼성전자주식회사 지연 동기 루프를 구비하는 반도체 메모리 장치
KR100422572B1 (ko) * 2001-06-30 2004-03-12 주식회사 하이닉스반도체 레지스터 제어 지연고정루프 및 그를 구비한 반도체 소자
US6832327B1 (en) * 2001-10-02 2004-12-14 Advanced Micro Devices, Inc. Apparatus and method for providing an external clock from a circuit in sleep mode in a processor-based system
US6678205B2 (en) * 2001-12-26 2004-01-13 Micron Technology, Inc. Multi-mode synchronous memory device and method of operating and testing same
JP2003228982A (ja) 2002-01-29 2003-08-15 Hitachi Ltd 半導体集積回路装置
KR100470995B1 (ko) * 2002-04-23 2005-03-08 삼성전자주식회사 클럭수신 동기회로를 갖는 멀티클럭 도메인 데이터 입력처리장치 및 그에 따른 클럭신호 인가방법
US6765433B1 (en) * 2003-03-20 2004-07-20 Atmel Corporation Low power implementation for input signals of integrated circuits
KR100560297B1 (ko) * 2003-10-29 2006-03-10 주식회사 하이닉스반도체 지연고정루프용 전원 공급 회로를 구비한 반도체 소자
KR100540487B1 (ko) * 2003-10-31 2006-01-10 주식회사 하이닉스반도체 데이터 출력제어회로
KR100571651B1 (ko) * 2003-12-29 2006-04-17 주식회사 하이닉스반도체 파워다운 모드의 안정적인 탈출을 위한 제어회로
KR100808052B1 (ko) * 2005-09-28 2008-03-07 주식회사 하이닉스반도체 반도체 메모리 장치
US7429871B2 (en) * 2005-09-29 2008-09-30 Hynix Semiconductor Inc. Device for controlling on die termination
JP4524662B2 (ja) * 2005-10-21 2010-08-18 エルピーダメモリ株式会社 半導体メモリチップ
KR100702766B1 (ko) * 2005-12-07 2007-04-03 주식회사 하이닉스반도체 안정적인 ｄｌｌ용 내부 전압을 생성하는 내부 전압발생기와 이를 포함하는 내부 클록 발생기 및 그 내부 전압발생 방법
KR100680975B1 (ko) * 2006-01-13 2007-02-09 주식회사 하이닉스반도체 파워다운 모드 제어 회로
KR100776906B1 (ko) 2006-02-16 2007-11-19 주식회사 하이닉스반도체 파워다운 모드 동안 주기적으로 락킹 동작을 실행하는기능을 가지는 ｄｌｌ 및 그 락킹 동작 방법
US7613064B1 (en) * 2006-12-19 2009-11-03 Nvidia Corporation Power management modes for memory devices
KR100896182B1 (ko) * 2007-02-22 2009-05-12 삼성전자주식회사 지연 동기 회로의 파워 다운 모드를 제어하는 장치 및 그제어 방법
US20080228950A1 (en) * 2007-03-14 2008-09-18 Qimonda North America Corp. Memory power down mode exit method and system
JP2009140322A (ja) * 2007-12-07 2009-06-25 Elpida Memory Inc タイミング制御回路および半導体記憶装置
KR100902058B1 (ko) * 2008-01-07 2009-06-09 주식회사 하이닉스반도체 반도체 집적 회로 및 그의 제어 방법
US7728638B2 (en) * 2008-04-25 2010-06-01 Qimonda North America Corp. Electronic system that adjusts DLL lock state acquisition time
JP5654196B2 (ja) * 2008-05-22 2015-01-14 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． Ｄｌｌ回路ユニット及び半導体メモリ
KR100996176B1 (ko) 2008-12-09 2010-11-24 주식회사 하이닉스반도체 반도체 메모리 장치 및 그에 구비되는 지연 고정 루프의 제어 방법
KR101497777B1 (ko) 2009-12-30 2015-03-02 마이크론 테크놀로지, 인크. 클록 입력 버퍼 제어
KR101175244B1 (ko) 2010-04-29 2012-08-22 에스케이하이닉스 주식회사 반도체장치 및 이의 동작방법, 메모리 시스템
KR101136985B1 (ko) 2010-08-18 2012-04-19 에스케이하이닉스 주식회사 반도체 메모리 장치의 데이터 출력 회로
US20140115358A1 (en) * 2011-05-27 2014-04-24 Freescale Semiconductor, Inc. Integrated circuit device and method for controlling an operating mode of an on-die memory
JP2015035241A (ja) * 2013-08-09 2015-02-19 マイクロン テクノロジー， インク． 半導体装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3429977B2 (ja) * 1997-05-16 2003-07-28 富士通株式会社 スキュー低減回路及び半導体装置
JP3832932B2 (ja) * 1997-07-11 2006-10-11 富士通株式会社 半導体集積回路および半導体集積回路システム
JP4031859B2 (ja) * 1998-02-03 2008-01-09 富士通株式会社 半導体装置

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