ITMI20050963A1 - Memoria tampone di ingresso di equalizzazione a retroazione di decisione - Google Patents

Memoria tampone di ingresso di equalizzazione a retroazione di decisione

Info

Publication number
ITMI20050963A1
ITMI20050963A1 IT000963A ITMI20050963A ITMI20050963A1 IT MI20050963 A1 ITMI20050963 A1 IT MI20050963A1 IT 000963 A IT000963 A IT 000963A IT MI20050963 A ITMI20050963 A IT MI20050963A IT MI20050963 A1 ITMI20050963 A1 IT MI20050963A1
Authority
IT
Italy
Prior art keywords
memory
input buffer
decision feedback
feedback input
decision
Prior art date
Application number
IT000963A
Other languages
English (en)
Inventor
Young-Soo Sohn
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of ITMI20050963A1 publication Critical patent/ITMI20050963A1/it

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H04L25/03057—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0087—Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Amplifiers (AREA)
IT000963A 2004-05-27 2005-05-25 Memoria tampone di ingresso di equalizzazione a retroazione di decisione ITMI20050963A1 (it)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020040037966A KR100615597B1 (ko) 2004-05-27 2004-05-27 데이터 입력회로 및 방법
US11/040,808 US7542507B2 (en) 2004-05-27 2005-01-21 Decision feedback equalization input buffer

Publications (1)

Publication Number Publication Date
ITMI20050963A1 true ITMI20050963A1 (it) 2005-11-28

Family

ID=35425223

Family Applications (1)

Application Number Title Priority Date Filing Date
IT000963A ITMI20050963A1 (it) 2004-05-27 2005-05-25 Memoria tampone di ingresso di equalizzazione a retroazione di decisione

Country Status (4)

Country Link
US (1) US7542507B2 (it)
KR (1) KR100615597B1 (it)
CN (1) CN100401269C (it)
IT (1) ITMI20050963A1 (it)

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US7804892B1 (en) * 2006-02-03 2010-09-28 Altera Corporation Circuitry for providing programmable decision feedback equalization
JP4773294B2 (ja) * 2006-07-14 2011-09-14 ルネサスエレクトロニクス株式会社 適応等化装置及び受信装置
JP2008066879A (ja) * 2006-09-05 2008-03-21 Ricoh Co Ltd オーバーサンプリング回路及びオーバーサンプリング方法
US7599461B2 (en) * 2006-09-29 2009-10-06 Agere Systems Inc. Method and apparatus for generating one or more clock signals for a decision-feedback equalizer using DFE detected data in the presence of an adverse pattern
US7646658B2 (en) * 2007-05-31 2010-01-12 Qualcomm Incorporated Memory device with delay tracking for improved timing margin
KR101412071B1 (ko) 2007-10-30 2014-06-26 삼성전자주식회사 Ｉｓｉ 제어 방법 및 그 방법을 이용하는 반도체 메모리장치
WO2010031417A1 (en) 2008-09-19 2010-03-25 Verigy (Singapore) Pte. Ltd. A data processing unit and a method of processing data
KR100951668B1 (ko) * 2008-10-14 2010-04-07 주식회사 하이닉스반도체 반도체 메모리 장치의 버퍼
KR100995658B1 (ko) * 2008-11-13 2010-11-19 주식회사 하이닉스반도체 반도체 메모리 장치의 버퍼
US8149907B2 (en) * 2009-01-07 2012-04-03 Mediatek Inc. Adaptive equalization apparatus with equalization parameter setting adaptively adjusted according to edges of equalizer output monitored in real-time manner and related method thereof
EP2267902B1 (en) * 2009-01-26 2013-03-13 Fujitsu Semiconductor Limited Sampling
KR101053524B1 (ko) * 2009-06-08 2011-08-03 주식회사 하이닉스반도체 반도체 버퍼 회로
CN102054060B (zh) * 2009-11-04 2013-02-20 普诚科技股份有限公司 周期信号平衡电路与芯片布局时平衡周期信号的方法
JP2011113450A (ja) * 2009-11-30 2011-06-09 Toshiba Corp メモリインターフェース回路
KR101034379B1 (ko) * 2010-04-30 2011-05-16 전자부품연구원 클록없이 동작하는 등화기를 이용한 데이터 복원장치
KR101421909B1 (ko) 2010-08-12 2014-07-22 어드밴테스트 (싱가포르) 피티이. 엘티디. 기준 스캔 체인 테스트 데이터를 생성하는 테스트 장치 및 테스트 시스템
US8391350B2 (en) 2010-09-03 2013-03-05 Altera Corporation Adaptation circuitry and methods for decision feedback equalizers
JP2012244537A (ja) * 2011-05-23 2012-12-10 Ricoh Co Ltd データリカバリ方法およびデータリカバリ装置
US8879616B2 (en) * 2011-10-31 2014-11-04 Hewlett-Packard Development Company, L.P. Receiver with decision feedback equalizer
KR101931223B1 (ko) * 2011-12-29 2018-12-21 에스케이하이닉스 주식회사 데이터 이퀄라이징 회로 및 데이터 이퀄라이징 방법
US9165597B2 (en) * 2013-06-28 2015-10-20 Seagate Technology Llc Time-multiplexed single input single output (SISO) data recovery channel
US20160277220A1 (en) * 2013-12-05 2016-09-22 Yahuan Liu Pattern-based coefficient adaptation operation for decision feedback equalization
JP6703364B2 (ja) * 2014-04-10 2020-06-03 ザインエレクトロニクス株式会社 受信装置
US9369267B2 (en) * 2014-05-07 2016-06-14 Texas Instruments Incorporated Communication reception with compensation for relative variation between transmit bit interval and receiver sampling interval
KR102222449B1 (ko) * 2015-02-16 2021-03-03 삼성전자주식회사 탭이 내장된 데이터 수신기 및 이를 포함하는 데이터 전송 시스템
JP2017135506A (ja) * 2016-01-26 2017-08-03 株式会社日立製作所 スキュー調整回路、半導体装置およびスキューキャリブレーション方法
JP6769317B2 (ja) 2017-01-31 2020-10-14 富士通株式会社 判定帰還型等化器及びインターコネクト回路
KR102438991B1 (ko) * 2017-11-28 2022-09-02 삼성전자주식회사 메모리 장치 및 그것의 동작 방법
US10607671B2 (en) * 2018-02-17 2020-03-31 Micron Technology, Inc. Timing circuit for command path in a memory device
TWI754303B (zh) * 2020-06-17 2022-02-01 群聯電子股份有限公司 等化器電路、記憶體儲存裝置及訊號調整方法
KR20230000322A (ko) * 2021-06-24 2023-01-02 에스케이하이닉스 주식회사 데이터정렬동작을 수행하기 위한 전자장치

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FI90705C (fi) * 1992-06-12 1994-03-10 Nokia Oy Ab Adaptiivinen ilmaisumenetelmä ja ilmaisin kvantittuneille signaaleille
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JP2001256728A (ja) 2000-03-10 2001-09-21 Fujitsu Ltd 半導体装置
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FR2826810A1 (fr) * 2001-06-29 2003-01-03 St Microelectronics Sa Dispositif de synchronisation et d'egalisation pour un recepteur de systeme de transmission numerique
CN1659780B (zh) * 2002-04-16 2011-06-22 汤姆森许可公司 判决反馈均衡器
KR100518029B1 (ko) * 2002-06-11 2005-10-04 한국전자통신연구원 블라인드 판정궤환등화 장치 및 그 방법
US7161980B2 (en) 2002-08-19 2007-01-09 Lucent Technologies Inc. Receiver for high rate digital communication system
US7463681B2 (en) * 2004-05-13 2008-12-09 Ittiam Systems (P) Ltd. Architecture for feedback loops in decision feedback equalizers

Also Published As

Publication number Publication date
CN1716214A (zh) 2006-01-04
CN100401269C (zh) 2008-07-09
US7542507B2 (en) 2009-06-02
KR100615597B1 (ko) 2006-08-25
US20050265440A1 (en) 2005-12-01
KR20050113362A (ko) 2005-12-02

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