ITMI20021185A1 - Dispositivo e metodo di lettura per memorie non volatili dotate di almeno un'interfaccia di comunicazione pseudo parallela - Google Patents

Dispositivo e metodo di lettura per memorie non volatili dotate di almeno un'interfaccia di comunicazione pseudo parallela

Info

Publication number
ITMI20021185A1
ITMI20021185A1 IT2002MI001185A ITMI20021185A ITMI20021185A1 IT MI20021185 A1 ITMI20021185 A1 IT MI20021185A1 IT 2002MI001185 A IT2002MI001185 A IT 2002MI001185A IT MI20021185 A ITMI20021185 A IT MI20021185A IT MI20021185 A1 ITMI20021185 A1 IT MI20021185A1
Authority
IT
Italy
Prior art keywords
communication interface
reading method
volatile memories
pseudo communication
parallel pseudo
Prior art date
Application number
IT2002MI001185A
Other languages
English (en)
Inventor
Salvatore Polizzi
Maurizio Perroni
Salvatore Poli
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT2002MI001185A priority Critical patent/ITMI20021185A1/it
Publication of ITMI20021185A0 publication Critical patent/ITMI20021185A0/it
Priority to US10/452,762 priority patent/US6975559B2/en
Publication of ITMI20021185A1 publication Critical patent/ITMI20021185A1/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G11C2029/2602—Concurrent test
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/06—Sense amplifier related aspects
    • G11C2207/061—Sense amplifier enabled by a address transition detection related control signal
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/108—Wide data ports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2281—Timing of a read operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
  • Tests Of Electronic Circuits (AREA)
IT2002MI001185A 2002-05-31 2002-05-31 Dispositivo e metodo di lettura per memorie non volatili dotate di almeno un'interfaccia di comunicazione pseudo parallela ITMI20021185A1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT2002MI001185A ITMI20021185A1 (it) 2002-05-31 2002-05-31 Dispositivo e metodo di lettura per memorie non volatili dotate di almeno un'interfaccia di comunicazione pseudo parallela
US10/452,762 US6975559B2 (en) 2002-05-31 2003-05-30 Device and method for reading non-volatile memories having at least one pseudo-parallel communication interface

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT2002MI001185A ITMI20021185A1 (it) 2002-05-31 2002-05-31 Dispositivo e metodo di lettura per memorie non volatili dotate di almeno un'interfaccia di comunicazione pseudo parallela

Publications (2)

Publication Number Publication Date
ITMI20021185A0 ITMI20021185A0 (it) 2002-05-31
ITMI20021185A1 true ITMI20021185A1 (it) 2003-12-01

Family

ID=11450016

Family Applications (1)

Application Number Title Priority Date Filing Date
IT2002MI001185A ITMI20021185A1 (it) 2002-05-31 2002-05-31 Dispositivo e metodo di lettura per memorie non volatili dotate di almeno un'interfaccia di comunicazione pseudo parallela

Country Status (2)

Country Link
US (1) US6975559B2 (it)
IT (1) ITMI20021185A1 (it)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3959270B2 (ja) * 2001-12-26 2007-08-15 株式会社東芝 半導体集積回路装置及びその読み出し開始トリガ信号発生方法
KR100546418B1 (ko) 2004-07-27 2006-01-26 삼성전자주식회사 데이터 출력시 ｄｄｒ 동작을 수행하는 비휘발성 메모리장치 및 데이터 출력 방법
KR101255325B1 (ko) * 2007-08-23 2013-04-16 삼성전자주식회사 강유전체 메모리 장치 및 강유전체 메모리 장치의 구동방법
JP2010108550A (ja) * 2008-10-30 2010-05-13 Elpida Memory Inc 半導体記憶装置
US9502920B2 (en) * 2011-11-16 2016-11-22 Semiconductor Energy Laboratory Co., Ltd. Power receiving device, power transmission device, and power feeding system

Family Cites Families (24)

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EP0206743A3 (en) * 1985-06-20 1990-04-25 Texas Instruments Incorporated Zero fall-through time asynchronous fifo buffer with nonambiguous empty/full resolution
US4839866A (en) * 1987-05-29 1989-06-13 Texas Instruments Incorporated Cascadable first-in, first-out memory
US5306963A (en) * 1992-06-19 1994-04-26 Intel Corporation Address transition detection noise filter in pulse summation circuit for nonvolatile semiconductor memory
JPH0729375A (ja) * 1993-07-14 1995-01-31 Seiko Epson Corp 半導体記憶装置
US5543975A (en) * 1993-11-12 1996-08-06 Hewlett-Packard Company Removal of precompensation in a write data signal from a flexible disk controller
DE69421266T2 (de) * 1994-02-18 2000-05-18 St Microelectronics Srl Lesetaktsteuerungsverfahren und Schaltung für nichtflüchtige Speicher
EP0700001B1 (en) * 1994-08-31 1999-11-03 Motorola, Inc. Method for synchronously accessing memory
US5548560A (en) * 1995-04-19 1996-08-20 Alliance Semiconductor Corporation Synchronous static random access memory having asynchronous test mode
JPH08293198A (ja) * 1995-04-21 1996-11-05 Nec Ic Microcomput Syst Ltd 半導体記憶装置
JPH09147598A (ja) * 1995-11-28 1997-06-06 Mitsubishi Electric Corp 半導体記憶装置およびアドレス変化検出回路
US6711648B1 (en) * 1997-03-28 2004-03-23 Siemens Aktiengesellschaft Kabushiki Kaisha Toshiba Methods and apparatus for increasing data bandwidth in a dynamic memory device by generating a delayed address transition detection signal in response to a column address strobe signal
US6125051A (en) * 1997-12-12 2000-09-26 Hyundai Electronics Industries Co., Ltd. Circuit for driving nonvolatile ferroelectric memory
US6069839A (en) * 1998-03-20 2000-05-30 Cypress Semiconductor Corp. Circuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the method
JP4107716B2 (ja) * 1998-06-16 2008-06-25 株式会社ルネサステクノロジ Ｆｉｆｏ型記憶装置
KR100290286B1 (ko) * 1999-02-05 2001-05-15 윤종용 빠른 입출력 라인 프리차지 스킴을 구비한 반도체 메모리 장치
KR100291897B1 (ko) * 1999-03-11 2001-06-01 윤종용 버스트 모드 액세스를 구비한 반도체 메모리 장치
US6111787A (en) * 1999-10-19 2000-08-29 Advanced Micro Devices, Inc. Address transistion detect timing architecture for a simultaneous operation flash memory device
TW535161B (en) * 1999-12-03 2003-06-01 Nec Electronics Corp Semiconductor memory device and its testing method
JP2001357670A (ja) * 2000-04-14 2001-12-26 Mitsubishi Electric Corp 半導体記憶装置
US6285627B1 (en) * 2000-04-25 2001-09-04 Advanced Micro Devices, Inc. Address transition detector architecture for a high density flash memory device
US6339541B1 (en) * 2000-06-16 2002-01-15 United Memories, Inc. Architecture for high speed memory circuit having a relatively large number of internal data lines
JP3959270B2 (ja) * 2001-12-26 2007-08-15 株式会社東芝 半導体集積回路装置及びその読み出し開始トリガ信号発生方法
US6741515B2 (en) * 2002-06-18 2004-05-25 Nanoamp Solutions, Inc. DRAM with total self refresh and control circuit
JP4088227B2 (ja) * 2003-09-29 2008-05-21 株式会社東芝 半導体集積回路装置

Also Published As

Publication number Publication date
US6975559B2 (en) 2005-12-13
ITMI20021185A0 (it) 2002-05-31
US20040001366A1 (en) 2004-01-01

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