IT9019589A0 - Memoria a carico variabile di marginarura - Google Patents

Memoria a carico variabile di marginarura

Info

Publication number
IT9019589A0
IT9019589A0 IT9019589A IT1958990A IT9019589A0 IT 9019589 A0 IT9019589 A0 IT 9019589A0 IT 9019589 A IT9019589 A IT 9019589A IT 1958990 A IT1958990 A IT 1958990A IT 9019589 A0 IT9019589 A0 IT 9019589A0
Authority
IT
Italy
Prior art keywords
marginarura
variable load
load memory
memory
variable
Prior art date
Application number
IT9019589A
Other languages
English (en)
Other versions
IT1241661B (it
IT9019589A1 (it
Inventor
George R Canepa
Original Assignee
Intel
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel filed Critical Intel
Publication of IT9019589A0 publication Critical patent/IT9019589A0/it
Publication of IT9019589A1 publication Critical patent/IT9019589A1/it
Application granted granted Critical
Publication of IT1241661B publication Critical patent/IT1241661B/it

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/26Sensing or reading circuits; Data output circuits
    • G11C16/28Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
IT19589A 1989-03-10 1990-03-07 Memoria a carico variabile di marginatura IT1241661B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/321,887 US5142495A (en) 1989-03-10 1989-03-10 Variable load for margin mode

Publications (3)

Publication Number Publication Date
IT9019589A0 true IT9019589A0 (it) 1990-03-07
IT9019589A1 IT9019589A1 (it) 1991-09-07
IT1241661B IT1241661B (it) 1994-01-26

Family

ID=23252467

Family Applications (1)

Application Number Title Priority Date Filing Date
IT19589A IT1241661B (it) 1989-03-10 1990-03-07 Memoria a carico variabile di marginatura

Country Status (3)

Country Link
US (1) US5142495A (it)
JP (1) JPH02254700A (it)
IT (1) IT1241661B (it)

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JP3080743B2 (ja) * 1991-12-27 2000-08-28 日本電気株式会社 不揮発性半導体記憶装置
JP2848117B2 (ja) * 1992-05-27 1999-01-20 日本電気株式会社 半導体記憶回路
US5561635A (en) * 1992-10-13 1996-10-01 Rohm Co., Ltd. PROM IC enabling a stricter memory cell margin test
JP3236105B2 (ja) * 1993-03-17 2001-12-10 富士通株式会社 不揮発性半導体記憶装置及びその動作試験方法
US5424991A (en) * 1993-04-01 1995-06-13 Cypress Semiconductor Corporation Floating gate nonvolatile memory with uniformly erased threshold voltage
US5463586A (en) * 1993-05-28 1995-10-31 Macronix International Co., Ltd. Erase and program verification circuit for non-volatile memory
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EP0933821B1 (en) * 1994-03-03 2003-04-23 Rohm Corporation Low voltage one transistor flash eeprom cell using fowler-nordheim programming and erase
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US6584017B2 (en) 2001-04-05 2003-06-24 Saifun Semiconductors Ltd. Method for programming a reference cell
US6535434B2 (en) * 2001-04-05 2003-03-18 Saifun Semiconductors Ltd. Architecture and scheme for a non-strobed read sequence
JP3734726B2 (ja) * 2001-07-17 2006-01-11 松下電器産業株式会社 読み出し専用メモリ
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US6791396B2 (en) * 2001-10-24 2004-09-14 Saifun Semiconductors Ltd. Stack element circuit
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US6700818B2 (en) 2002-01-31 2004-03-02 Saifun Semiconductors Ltd. Method for operating a memory device
US6917544B2 (en) 2002-07-10 2005-07-12 Saifun Semiconductors Ltd. Multiple use memory chip
US6538940B1 (en) * 2002-09-26 2003-03-25 Motorola, Inc. Method and circuitry for identifying weak bits in an MRAM
US7136304B2 (en) 2002-10-29 2006-11-14 Saifun Semiconductor Ltd Method, system and circuit for programming a non-volatile memory array
US20040151032A1 (en) * 2003-01-30 2004-08-05 Yan Polansky High speed and low noise output buffer
US7178004B2 (en) 2003-01-31 2007-02-13 Yan Polansky Memory array programming circuit and a method for using the circuit
US7076377B2 (en) * 2003-02-11 2006-07-11 Rambus Inc. Circuit, apparatus and method for capturing a representation of a waveform from a clock-data recovery (CDR) unit
US6885244B2 (en) 2003-03-24 2005-04-26 Saifun Semiconductors Ltd. Operational amplifier with fast rise time
US7142464B2 (en) 2003-04-29 2006-11-28 Saifun Semiconductors Ltd. Apparatus and methods for multi-level sensing in a memory array
US6906966B2 (en) 2003-06-16 2005-06-14 Saifun Semiconductors Ltd. Fast discharge for program and verification
US7123532B2 (en) 2003-09-16 2006-10-17 Saifun Semiconductors Ltd. Operating array cells with matched reference cells
US7050319B2 (en) * 2003-12-03 2006-05-23 Micron Technology, Inc. Memory architecture and method of manufacture and operation thereof
JP2005209311A (ja) * 2004-01-26 2005-08-04 Matsushita Electric Ind Co Ltd 半導体記憶装置
US7176728B2 (en) * 2004-02-10 2007-02-13 Saifun Semiconductors Ltd High voltage low power driver
US8339102B2 (en) * 2004-02-10 2012-12-25 Spansion Israel Ltd System and method for regulating loading on an integrated circuit power supply
TWI247311B (en) * 2004-03-25 2006-01-11 Elite Semiconductor Esmt Circuit and method for preventing nonvolatile memory from over erasure
US7652930B2 (en) 2004-04-01 2010-01-26 Saifun Semiconductors Ltd. Method, circuit and system for erasing one or more non-volatile memory cells
US7187595B2 (en) * 2004-06-08 2007-03-06 Saifun Semiconductors Ltd. Replenishment for internal voltage
US7256438B2 (en) * 2004-06-08 2007-08-14 Saifun Semiconductors Ltd MOS capacitor with reduced parasitic capacitance
US7190212B2 (en) * 2004-06-08 2007-03-13 Saifun Semiconductors Ltd Power-up and BGREF circuitry
US7317633B2 (en) 2004-07-06 2008-01-08 Saifun Semiconductors Ltd Protection of NROM devices from charge damage
JP4554613B2 (ja) * 2004-07-30 2010-09-29 Spansion Japan株式会社 半導体装置および半導体装置にデータを書き込む方法
US7095655B2 (en) 2004-08-12 2006-08-22 Saifun Semiconductors Ltd. Dynamic matching of signal path and reference path for sensing
US7638850B2 (en) 2004-10-14 2009-12-29 Saifun Semiconductors Ltd. Non-volatile memory structure and method of fabrication
US8094493B2 (en) * 2004-11-12 2012-01-10 Macronix International Co., Ltd. Memory devices and methods using improved reference cell trimming algorithms for accurate read operation window control
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US7239537B2 (en) * 2005-01-12 2007-07-03 International Business Machines Corporation Method and apparatus for current sense amplifier calibration in MRAM devices
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US8053812B2 (en) 2005-03-17 2011-11-08 Spansion Israel Ltd Contact in planar NROM technology
US20060218455A1 (en) * 2005-03-23 2006-09-28 Silicon Design Solution, Inc. Integrated circuit margin stress test system
US8400841B2 (en) 2005-06-15 2013-03-19 Spansion Israel Ltd. Device to program adjacent storage cells of different NROM cells
US7786512B2 (en) 2005-07-18 2010-08-31 Saifun Semiconductors Ltd. Dense non-volatile memory array and method of fabrication
US7668017B2 (en) 2005-08-17 2010-02-23 Saifun Semiconductors Ltd. Method of erasing non-volatile memory cells
US7221138B2 (en) 2005-09-27 2007-05-22 Saifun Semiconductors Ltd Method and apparatus for measuring charge pump output current
US7352627B2 (en) 2006-01-03 2008-04-01 Saifon Semiconductors Ltd. Method, system, and circuit for operating a non-volatile memory array
US7808818B2 (en) 2006-01-12 2010-10-05 Saifun Semiconductors Ltd. Secondary injection for NROM
US7692961B2 (en) 2006-02-21 2010-04-06 Saifun Semiconductors Ltd. Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection
US7760554B2 (en) 2006-02-21 2010-07-20 Saifun Semiconductors Ltd. NROM non-volatile memory and mode of operation
US8253452B2 (en) 2006-02-21 2012-08-28 Spansion Israel Ltd Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same
US7638835B2 (en) 2006-02-28 2009-12-29 Saifun Semiconductors Ltd. Double density NROM with nitride strips (DDNS)
US7701779B2 (en) 2006-04-27 2010-04-20 Sajfun Semiconductors Ltd. Method for programming a reference cell
US7605579B2 (en) 2006-09-18 2009-10-20 Saifun Semiconductors Ltd. Measuring and controlling current consumption and output current of charge pumps
JP2010079977A (ja) * 2008-09-25 2010-04-08 Toppan Printing Co Ltd 定電流型電源回路を有する不揮発性半導体メモリ装置
JP2011159355A (ja) * 2010-02-01 2011-08-18 Sanyo Electric Co Ltd 半導体記憶装置
US8345483B2 (en) * 2011-01-21 2013-01-01 Spansion Llc System and method for addressing threshold voltage shifts of memory cells in an electronic product
JP6496742B2 (ja) * 2014-02-11 2019-04-03 アイメック・ヴェーゼットウェーImec Vzw 薄膜電子回路をカスタマイズするための方法
GB2575508B (en) * 2018-07-13 2020-07-15 X Fab Semiconductor Foundries Gmbh Improvements in and relating to flash memory

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JPS56148792A (en) * 1980-04-21 1981-11-18 Nec Corp Testing method for margin voltage of memory cell
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US4903265A (en) * 1987-11-12 1990-02-20 Motorola, Inc. Method and apparatus for post-packaging testing of one-time programmable memories
US4841482A (en) * 1988-02-17 1989-06-20 Intel Corporation Leakage verification for flash EPROM

Also Published As

Publication number Publication date
IT1241661B (it) 1994-01-26
IT9019589A1 (it) 1991-09-07
US5142495A (en) 1992-08-25
JPH02254700A (ja) 1990-10-15

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Effective date: 19980327