JPS56148792A - Testing method for margin voltage of memory cell - Google Patents

Testing method for margin voltage of memory cell

Info

Publication number
JPS56148792A
JPS56148792A JP5246180A JP5246180A JPS56148792A JP S56148792 A JPS56148792 A JP S56148792A JP 5246180 A JP5246180 A JP 5246180A JP 5246180 A JP5246180 A JP 5246180A JP S56148792 A JPS56148792 A JP S56148792A
Authority
JP
Japan
Prior art keywords
potential
node
memory cell
digit line
cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5246180A
Other languages
Japanese (ja)
Other versions
JPS6126154B2 (en
Inventor
Hajime Shirato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5246180A priority Critical patent/JPS56148792A/en
Publication of JPS56148792A publication Critical patent/JPS56148792A/en
Publication of JPS6126154B2 publication Critical patent/JPS6126154B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/81—Threshold
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5004—Voltage

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To test a margin voltage accurately by taking the test with holding a write potential constant through grounding the counter electrode of the capacitor of a memory cell. CONSTITUTION:The counter electrode of capacitor CS' of one-transistor type memory cell 11 is grounded with low impedance and held at the ground voltage. At this constant potential, logic ''1'' or ''0'' is written at node S' of cell 11 via digit line D' and even when potential VDD at digit line D' is changed to VDD1 or VDD2 during a precharging period, write potential at node S' is not changed. Even if the node is read after power source VDD is charged during the precharging period or even when power source VDD in writing operation is made different from that in reading operation, the margin voltage is decreased or increased externally and forcibly as a result of variance in critical voltage in the reading operation where the difference signal potential between digit line D' and the digit line of reference cell 13 is zero without varying the potential at node S' of cell 11, so that the test wherein the internal margin voltage and blind sector width of the memory cell are measured accurately will be taken.
JP5246180A 1980-04-21 1980-04-21 Testing method for margin voltage of memory cell Granted JPS56148792A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5246180A JPS56148792A (en) 1980-04-21 1980-04-21 Testing method for margin voltage of memory cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5246180A JPS56148792A (en) 1980-04-21 1980-04-21 Testing method for margin voltage of memory cell

Publications (2)

Publication Number Publication Date
JPS56148792A true JPS56148792A (en) 1981-11-18
JPS6126154B2 JPS6126154B2 (en) 1986-06-19

Family

ID=12915352

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5246180A Granted JPS56148792A (en) 1980-04-21 1980-04-21 Testing method for margin voltage of memory cell

Country Status (1)

Country Link
JP (1) JPS56148792A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0076124A2 (en) * 1981-09-26 1983-04-06 Fujitsu Limited Method of testing IC memories
JPS5891594A (en) * 1981-11-27 1983-05-31 Fujitsu Ltd Dynamic semiconductor storage device
US4612630A (en) * 1984-07-27 1986-09-16 Harris Corporation EEPROM margin testing design
US5142495A (en) * 1989-03-10 1992-08-25 Intel Corporation Variable load for margin mode
US5559739A (en) * 1995-09-28 1996-09-24 International Business Machines Corporation Dynamic random access memory with a simple test arrangement
US5610867A (en) * 1995-09-28 1997-03-11 International Business Machines Corporation DRAM signal margin test method

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0076124A2 (en) * 1981-09-26 1983-04-06 Fujitsu Limited Method of testing IC memories
JPS5891594A (en) * 1981-11-27 1983-05-31 Fujitsu Ltd Dynamic semiconductor storage device
EP0080935A2 (en) * 1981-11-27 1983-06-08 Fujitsu Limited Dynamic semiconductor memory device
JPH0222470B2 (en) * 1981-11-27 1990-05-18 Fujitsu Ltd
US4612630A (en) * 1984-07-27 1986-09-16 Harris Corporation EEPROM margin testing design
US5142495A (en) * 1989-03-10 1992-08-25 Intel Corporation Variable load for margin mode
US5559739A (en) * 1995-09-28 1996-09-24 International Business Machines Corporation Dynamic random access memory with a simple test arrangement
US5610867A (en) * 1995-09-28 1997-03-11 International Business Machines Corporation DRAM signal margin test method

Also Published As

Publication number Publication date
JPS6126154B2 (en) 1986-06-19

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