JPS6126154B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for testing an integrated circuit using an insulated gate field effect device, and more particularly to a method for testing a margin voltage of a one-transistor type memory cell.

One-transistor memory cells use a small number of elements per cell and are suitable for large-capacity memory integrated circuits, but because the memory cell output signal is small, they are used in the memory cell section or small signal amplification circuit (hereinafter referred to as S.A.
) manufacturing variations reduce operating margin margins. Therefore, measuring the operating margin of a memory cell or S/A system is an effective means of knowing the manufacturing process capability, and if it is possible to go further and guarantee the operating margin of a memory cell or S/A system. , it also becomes possible to select memory circuits that are resistant to external physical noise factors (eg alpha particles).

Conventionally, as a test method of this type, there is a method called a bump test in which an external power supply is vibrated to test the operating margin of the entire memory circuit. The purpose of this method is to test the resistance of the entire memory circuit to power fluctuations.

FIG. 1 is a circuit diagram for explaining a bump test method as an example of a conventional one-transistor type memory circuit testing method, and FIG. 2 is a voltage waveform diagram used in the conventional bump test.

The operation of the one-transistor type memory cell 1 is that of a MOS type transistor (hereinafter referred to as
(referred to as MOST) Q ₁₁ and Q ₁₂ are made conductive, and the girder lines D,
Equilibrate the potentials of both to V _M . Activation period-
(MOST: Q ₁₁ , Q ₁₂ , Q ₂₂ are off) When the memory cell word line WL(S) is activated by the AND of timing φ ₁ and decoder DEC, the charge accumulated in the memory capacitor Cs becomes MOST : It is transferred to the digit line D through Q ₃₀ , and the potential level of the digit line D is slightly changed from _VM . On the other hand, at timing φ ₁ , the reference cell word line WL(R) is also activated, and the capacitance C ₂ of the reference cell 3 (the potential of the node R is set to the ground potential by MOSU: Q ₃₂ during the precharge period) ) through MOST:Q ₃₁ , which lowers the potential level of the digit line slightly. The minute potential difference between both digit lines D and MOST: Cross-coupled MOST amplifier 2 consisting of Q ₂₁ and Q ₂₂ is connected at timing φ ₂ .
MOST: By making Q ₂₃ conductive, it is activated and the potential difference between D and D is amplified. The opposite electrodes of the capacitors C _s and C _B of the memory mole 1 and the referens cell 3 are normally connected to a node A and then connected to an external power supply V _DD via a resistor R. Since the resistor R is originally inserted to make it strong against bump tests that change _VDD , the time constant due to the load capacitance of the node A and the resistor R is considerably large.

When a bump test is performed by varying V _DD by ±△V _DD , the precharge potential V _P shows an oscillation of approximately ±△V _DD , and the V _M that gives the digit line equilibrium potential level is ±α
It vibrates at ×△V _DD (α1). In addition, the potential C _S of the memory cell node S also has a large time constant.
It will vibrate as β×△V _DD (β1).
A bump test is a test to determine how much of these vibrations a memory circuit system can withstand.

However, when trying to measure the margin of a memory cell, the voltage inside the memory cell is not fixed, and this vibration causes the measurement to be inaccurate.

The present invention eliminates the above-mentioned drawbacks and provides a method for accurately testing the memory cell margin voltage by setting the counter electrode of the capacitor of the memory cell to ground potential and keeping the write potential of the memory cell constant.

The memory cell margin voltage testing method of the present invention includes a process of fixing the counter electrode of a capacitor of a memory circuit including a one-transistor type memory cell, a cross-coupled MOS transistor small signal amplifier, and a reference cell to a ground potential, and A process of setting two external power supply potentials constant when writing logic "1" and logic "0" to the memory cell, and setting the external power supply potential when reading from the memory cell to a different potential from the external power supply potential at the time of writing. The method includes a process of reducing or expanding the margin voltage of the memory cell by changing a critical potential between the two external power supply potentials at the time of writing.

The present invention will be explained by examples.

FIG. 3 is a circuit diagram for explaining a test method according to an embodiment of the present invention, and FIG. 4 is a diagram for explaining an external potential and a critical potential used in the test method of the present invention.

As shown in the figure, one transistor type memory cell 1
The opposite electrode of capacitor C _S ' of No. 1 is set to ground potential with low impedance. In the test method of the present invention, as shown in FIG. 4, the external power supply potential V _DD is clearly changed during the write cycle period T _W and the read cycle period _TR . The memory cell capacitance is represented by C _S ', the reference cell capacitance is represented by C _R ', the column line capacitance is expressed by C _D ', the memory cell node potential is expressed by V _S ', and the column line potential is set to the equilibrium potential V _M '.

The minute potential change that causes the memory cell 11 to change the digit line cannot make the activation time of the S・A (minimal signal amplification circuit) 12 much later than the WL'(S) activation time (so as not to delay the access time). Therefore, it is less than 100% of the capacity of normal cells.
Assume that K (K1) times the capacity of the cell is output to the digit line by the time S.A12 is activated. The difference signal potential level △V _S . _A between both digit lines is (signal output from memory cell 11) - (reference cell 1
_{3 ) , so △ V S} .
) −C _R ′/C _D ′+C _R ′V _M ′. _{Here ,} if _{V S ' where △} V _{S .}
C _R '/C _S '×1/K), that is, V _C is proportional to V _M '. C _D ′≫C
Considering _S ′, C _S ′〓2C _R ′K〓1, it becomes V _c 〓0.5×V _M ′ ……(1).

In the write cycle, a logic "1" level or a logic "0" level is further written to the node S' of the memory cell 11 on the digit line D'. Even if the digit line potential V _DD is changed to V _DD1 (or V _DD2 ) during the precharge period, since the opposite electrode of the memory cell capacitor C _S ' is at the ground potential, the potential of the node S', that is, the write potential to the memory cell 11 is It does not change. After changing the power supply during the precharge period, a read cycle is performed. When the power supply is changed, V _M ' is a function of V _DD (the potential V _M ' is a divided potential between V _DD and the ground potential in circuit terms), so based on the above equation (1), , the critical potential Vc changes. That is, by setting V _DD during writing and V _DD during reading to different values, it is possible to change the critical potential V _C without changing the memory cell potential V _S '.

In particular, if V _M ' is set to V _DD , the change in critical potential V _C △V _C (V _C1 - V _C or V _C2 - V _C )
is △V _C 〓0.5 (V _DD1 −V _DD ) or △V _C 〓
0.5 (V _DD2 −V _DD ), which is easy to quantify.

As is clear from the above explanation, according to the method of the present invention, the critical voltage during reading can be changed without changing the logic "1" level and "0" level in the memory cell determined by the power supply during writing. By forcefully reducing the margin voltage of the memory cell (logic "1" level - critical voltage or critical voltage - logic "0" level) from the outside,
It can be expanded.

A pair of cross-cut pulls that generally constitute an SA
MOSTs do not have perfectly aligned threshold voltages or current amplification factors. Therefore, logic “1”
The critical potential V _C1 for the level does not match the critical potential V _C0 for the logic “0” level.

The above calculated critical potential V _C and these V _C
1 , the difference with V _C0 is called the dead zone, and the logic is “1”.
Assuming a dead zone Vus ₁ for the level and a dead zone Vus ₀ for the logic "0" level, Vus ₁ =V _C1 -V _C and V _US0 = Vc - V _C0 .

FIG. 5 is a diagram illustrating the potential level inside the memory cell set by the above method.

According to the method of the present invention, the margin voltage and dead zone inside the memory can be estimated. This is Vc=
The case where it is set to 0.5×V _DD will be explained.

FIGS. 6a and 6b are diagrams for explaining changes in external power supply potential used in the test method of the present invention.

FIG. 6a shows that after a logic "0" potential V _W0 is written into the memory cell during the write period T _W , the external power supply potential V _DD is decreased by ΔT _DD with a transition time T _T , and the read period T Indicates the voltage when reading and testing in _R.

-△V _DD when the value of -△V _DD is changed and logic “0” can no longer be read during the T _R period
If , is -△V _DDL , Vc ₀ in Fig. 5 is changed by -△Vc ₀ due to this -△V _DDL , and it becomes exactly V _W
This means that it matches ₀ .

That is, since the margin voltage V _NMO of logic "0" is equal to △V _CO due to △V _DDL , it is given by V _NMO = 0.5 x △V _DDL .

Further, the dead band width V _US0 is determined from FIG. 5 as Vus ₀ =Vc-V _NMO -V _W =0.5×V _DD −0.5-×△V _DDL −V _W . Normally, logic “0” potential V during writing
Since _W is the ground potential, V _US0 =0.5×V _DD −0.5×△V _DDL .

FIG. 6b shows a logic "1" potential V _W applied to the memory cell.
After writing ₁ during the write period T _W , the external power supply V _D
The voltage is shown when _D is increased by +ΔV _DD with the transition time T _T and read and tested during the read period T _R .

By changing the value of +△V _DD , the +△V _DD when the logic “1” cannot be read during the T _R period is +
If ΔV _DDH is used, Vc ₁ in FIG. 5 is changed by +ΔVc due to +ΔV _DDH and becomes equal to V _W1 .

The logic "1" potential V _W1 during writing is either the normal write power supply V _DDW potential or a potential lower than the V _DDW potential by the threshold potential V _T of the MOST source follower. That is, V _W1 = V _DDW or V _W1 = V _DDW - V _T .

If the power supply during the read period T _R is set to V _DD as shown in FIG. 6b, then V _W1 =V _DD -△V _DDH or V _W1 =V _DD -△V _DDH -V _T . In either case, the margin voltage V _NM1 of logic "1" is given by the sum of the change in V _C1 ΔV _C1 and the difference ΔV _DDH between the power supply V _DDW and the read power supply V _DD during writing. That is, V _NM1 = △V _C1 + △V _DDH = 1.5 x △V _DDH . Since the dead band width V _US1 is given by V _W1 −V _NM1 −V _C , V _US1 =0.5×V _DD −1.5×ΔV _DDH or V _US1 =0.5×V _DD −1.5×ΔV _DDH −V _T .

As explained in detail above, according to the present invention,
Set the opposite electrode of the memory cell capacitor to ground potential,
By using a method that does not change the write potential to the memory cell, the margin voltage and dead zone width inside the memory cell can be quantitatively and accurately measured from the outside, which is extremely effective.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram for explaining a bump test method as an example of a conventional memory circuit testing method, Fig. 2 is a voltage waveform diagram used in the conventional bump test, and Fig. 3 is an embodiment of the present invention. A circuit diagram for explaining the example test method, FIG. 4 is a diagram for explaining the external potential and critical potential used in the test method of the present invention,
FIG. 5 is a diagram explaining the potential level inside the memory cell set by the test method of the present invention, FIG. 6a,
b is a diagram for explaining the state of change in the external power supply potential used in the test method of the present invention. 1, 11... memory cell, 2, 12... minute signal amplifier, 3, 13... reference cell.

Claims (1)

[Claims] 1 Transistor type memory cell and cross-coupled
A process of fixing the opposite electrode of a capacitor of the memory cell of a memory circuit including a MOS transistor small signal amplifier, a reference cell, and a memory cell to a ground potential, and applying logic "1" and logic "0" to the memory cell.
The two external power supply potentials at the time of writing are set constant, and the external power supply potential at the time of reading from the memory cell is set to a different potential from the external power supply at the time of writing. A memory cell margin voltage testing method comprising: a process of reducing or expanding the margin voltage of a memory cell by changing a critical potential located between an external power supply potential.