JP3238806B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a dynamic random access memory (hereinafter referred to as DRAM) having a test mode for finding a defect in a memory cell comprising a transistor and a capacitor. Related to the device.

[0002]

FIG. 19 is a block diagram showing a conventional semiconductor memory device having a plurality of memory blocks. FIG.
, An input terminal 1 receives an address signal, which is applied to an operation block selection circuit 2, a column address buffer 3, and a row address buffer 4. The operation block selection circuit 2 outputs a block selection signal for selecting one of the memory blocks. That is,
The semiconductor memory device includes a plurality of memory blocks 11, 12,.
, 1n, and one of the memory blocks is selected by a block selection signal from the operation block selection circuit 2. The memory block 11 includes a column decoder 11
1, an I / O gate 112, an input / output circuit 113, a row decoder 114, a drive circuit 115, and a memory cell array 116. The other memory blocks 12,..., 1n are similarly configured.

The operation block selection circuit 2 activates a column decoder 111 and a row decoder 114 when, for example, the memory block 11 is selected. The column address buffer 3 converts the input column address signal into a column decoder 11.
1, 121,..., 1n1. The row address buffer 4 converts the input row address signal into row decoders 114, 1
24, ..., 1n4. Row decoder 114 activates a word line in response to a block selection signal of memory block 11 and a row address signal. Thereafter, column decoder 111 activates a column address in response to a block selection signal and a column address signal. specify. Data input from the input / output circuit 113 via the I / O gate 112 is written to the memory cell at the designated address, and data amplified by the sense amplifier from the memory cell at the designated address is read. Then, data is output from the I / O gate 112 to the outside via the input / output circuit 113.

FIG. 20 is a block diagram showing an example of the row decoder shown in FIG. 20, the row decoder includes an inverter 201 for inverting a row address signal, and an AND circuit 202 for receiving the row address signal and the inverted row address signal and outputting a word line activation signal Xi.

FIG. 21 is a diagram showing an example of the memory cell array shown in FIG. In FIG. 21, the memory cell array includes word lines WL1, WL2, WL3 and a pair of bit lines BL1, / BL1, BL2, / BL2 orthogonal to these, and transistors Q1 to Q6 forming a memory cell and capacitors at respective intersections. C1 to C6 are connected.
A sense amplifier for precharging and equalizing to 1/2 Vcc before reading data from the memory cell and amplifying a minute potential difference after reading data is provided to bit line pair BL1, / BL1, BL2, / BL2. Equalizer 3
01 and 302 are connected.

FIG. 22 is a circuit diagram for explaining an operation until data read from a memory cell is transmitted to an I / O line. Row decode signal Xi from row decoder 114 shown in FIG. 20 is applied to word line drive circuit 115, and word line drive circuit 115
The word line WLi is driven. Memory cell transistor Q
Data read from the memory cell array 116 composed of i and the capacitance Ci to the bit line pair BLi, / BLi is amplified by the sense amplifier 303. Sense amplifier 303 includes n-channel transistors 311 and 312 and p-channel transistors 313 and 314, and memory cell array 1 according to sense amplifier drive signals / S2N and S2P.
The data read from 16 to the bit line pair BLi, / BLi is amplified. Equalizing circuit 304 includes n-channel transistors 315, 316 and 317, and equalizes bit line pair BLi, / BLi with constant voltage V _BL (= １ ／ · Vcc) and bit line equalizing signal BLEQ. I / O gate circuit 305 includes n-channel transistors 318 and 319 for transmitting the potential of bit line pair BLi and / BLi to input / output lines I / O and / I / O lines based on column decode signal Yi. . I / O line pairs I / O and / I / O are n-channel transistors 320 and 3
21 to Vcc-Vth level.

FIG. 23 is a time chart for explaining the operation of FIG. Next, the operation of FIG. 22 will be described with reference to FIG. When the row decode signal Xi goes to the “L” level as shown in FIG. 23A and the word line drive signal φ goes to the “H” level as shown in FIG. Word line WLi is activated to "H" level. At this time, equalizing signal BLEQ is already at the "L" level as shown in FIG. 23 (d) to precharge the bit line to 1/2 Vcc, and data is read out to bit line pair BLi and / BLi. As shown in FIGS. 23 (g) and 23 (h), a small potential difference occurs between the bit line pairs. At this time, FIGS.
As shown in the figure, the sense amplifier drive signals / S2N, S2P
Is activated, the potential difference between the pair of bit lines BLi and / BLi is changed by the sense amplifier 303 as shown in FIG.
Amplified as shown in (h), Vcc and Vs respectively
s level (GND). After that, the column decode signal Y
i becomes “H” level as shown in FIG. 23 (i), and the data amplified by the sense amplifier 303 is
As shown in (k), the data is output to the input / output line pair I / O, / I / O.

FIG. 24 is a diagram showing a part of the memory cell array shown in FIG. In FIG. 24, bit line BL
At each intersection of i and the word lines WLi, WLi _{+ 1} , the memory cell transistors Qi, Qi _{+ 1} and the memory cell capacitance C
i, Ci _{+ 1} are connected and the memory cell capacitances Ci, C
A constant voltage V _cp (= １ ／ · Vcc) is applied to one electrode of i ₊ 1.
Is given.

FIG. 25 shows information ("L" level) of memory cell capacitance Ci connected to word line WLi shown in FIG.
5 is a time chart showing the operation when reading out the data. FIG.
As shown in FIG. 5A, when the word line WLi becomes “H” level, the memory cell transistor Qi is turned on, and the “L” level information stored in the memory cell capacitance Ci is shown in FIG.
As shown in FIG. 5C, the data is read out to the bit line BLi via the memory cell transistor Qi and amplified by a sense amplifier (not shown).

[0010]

If the threshold voltage Vth _{+ 1} of the memory cell transistor Qi _{+ 1} adjacent to the memory cell transistor Qi is lower than the design value for some reason, FIG. As shown, the "H" level information stored in the memory cell capacitance Ci _{+ 1} gradually leaks to the bit line BLi. For example, 16M
In the case of manufacturing a bit DRAM or the like, the threshold voltage of a memory cell transistor of several bits may be lowered due to the attachment of minute dust and the like.

Conventionally, a test called a disturb refresh test is performed except for a semiconductor integrated circuit including a memory cell transistor having a low threshold voltage of several bits. That is, for example, threshold voltage Vt of memory cell transistor Qi _{+ 1} in FIG.
Assuming that h _{+ 1} is low, the memory cell capacity Ci is set to “L”.
Is written, "H" level data is written into memory cell capacitance Ci _{+ 1,} and data of memory cell capacitance Ci is repeatedly read. Since the potential of the bit line BLi to which the memory cell transistor Qi _{+ 1} is connected is "L", a voltage between the drain and the source is generated in the memory cell transistor Qi _{+ 1} , and a subthreshold current flows. If the threshold voltage Vthi ₊₁ is low, the sub-threshold current is large and data is lost. Therefore, data of the memory cell capacitance Ci _{+ 1} is read, and it is determined whether or not the data matches the written data. If not, it can be determined that the threshold voltage of the memory cell transistor Qi _{+ 1} is lower than the design value. .

FIG. 19 is a block diagram of a DRAM.
In the case of performing a disturb refresh test, the operation block selection circuit 2 selects, for example, the memory block 11 and the same predetermined data is written to all the memory cells of the memory cell array 116. Next, one word line in memory cell array 116 is kept activated, and data of a memory cell connected to a word line adjacent to the word line is read to determine whether or not the data matches the written data. You. If they do not match, it can be determined that the threshold voltage of the transistor of the memory cell is lower than the design value. Next, a word line other than the above-mentioned activated word line is activated for a certain period of time, data of a memory cell connected to a word line adjacent to the activated word line is read, and it is determined whether the data matches the written data. Is done. This operation is performed for all the memory cells in memory cell array 116.

However, in the conventional disturb refresh test, only one word line is activated. Therefore, when a specific word line is continuously activated for a certain period of time,
When verifying the data retention time of a cell other than the memory cell connected to the word line adjacent to the word line, generally, the data retention compensation time of the memory cell is sufficiently longer than the time for reading and writing data in the cell. The time required for the disturb refresh test can be expressed by ignoring the time required to read / write from / to the memory cell: (number of word lines)
X (time for activating a word line) x (number of blocks operating simultaneously). For example, in the case of a 16 MDRAM, the number of word lines is 16384, and it takes 64 msec to activate a word line and operates simultaneously. Since the number of blocks to be performed is 4, a test time of about 262 sec is required, and there is a problem that the test time becomes longer.

Therefore, a main object of the present invention is to provide a semiconductor memory device having a built-in test circuit capable of reducing the time required for a disturb refresh test.

[0015]

The invention according to claim 1 is
A plurality of word lines, a plurality of bit lines intersecting each word line, and a plurality of memory cell transistors each connected to one of the plurality of word lines and one of the plurality of bit lines, A semiconductor memory device having a built-in test circuit for determining in a test mode a memory cell transistor having a threshold voltage lower than a predetermined threshold voltage among a plurality of memory cell transistors,
Test mode detection means for detecting a test mode; and activation for collectively activating memory cell transistors in every other row among a plurality of memory cell transistors in response to detection of the test mode. It comprises means.

[0016]

[0017]

According to a second aspect of the present invention, a plurality of word lines are divided into a plurality of blocks, and a test mode detecting means for detecting a test mode, and for writing data or reading written data. Block selecting means for selecting a specified one of a plurality of blocks in a write / read mode, and selecting the plurality of blocks collectively in response to detection of a test mode; Activating means for collectively activating the memory cell transistors in a predetermined row among the plurality of memory cell transistors in the plurality of blocks.

[0019] In the invention according to claim 3, the activation means of Claim 2, collectively activate the memory transistor of every other row.

According to a fourth aspect of the present invention, the activating means of the second aspect activates the memory cell transistors in every other row collectively.

According to a fifth aspect of the present invention, there is provided a test mode detecting means for detecting a test mode, and a small-scale signal having a variable amplitude for increasing the potential of a word line in response to the detection of the test mode. It is provided with a small signal generating means for giving a signal.

In the invention according to claim 6 , word line driving means for driving a word line is provided, and the minute signal generating means according to claim 5 includes pulse signal generating means for generating a repetitive pulse signal, and pulse signal generating means for generating a pulse signal. And a capacitor for transmitting the pulse signal to the word line driving means.

According to the seventh aspect of the present invention, a test word line provided in parallel with a word line, intersecting a plurality of bit lines and coupled to each bit line by a parasitic capacitance, and a test mode are detected. Mode detecting means for detecting the test mode, and a small signal generating means for applying a small signal with a variable amplitude for increasing the potential to the test word line in response to the detection of the test mode.

[0024] In the invention according to claim 8 is connected between the bit line crossing the test word line according to claim 7, a plurality of bit lines connected to the memory cell transistors, the write / read mode , A switching element which is turned off and turned on according to the test mode is provided.

According to the ninth aspect of the present invention, a test mode detecting means for detecting a test mode, and a drive signal of a negative potential is supplied to a sense amplifier in response to the detection of the test mode, thereby providing a threshold voltage. A negative potential signal generating means for facilitating conduction of a low voltage memory cell transistor is provided.

[0026]

According to the first aspect of the present invention, in the test mode, the memory cells in every other row are collectively activated to collectively read and write the data in the memory cells in those rows. It can be compared with data, and a memory cell transistor having a threshold voltage lower than a predetermined threshold voltage can be determined in a short time.

According to the second aspect of the present invention, when a memory cell block is divided into a plurality of memory cells, each memory cell block is selected collectively, and memory cells in a predetermined row of each memory block are collectively selected. Since activation can be performed, a memory cell transistor having a lower threshold voltage can be determined in a shorter time.

According to the fifth aspect of the present invention, in response to the detection of the test mode, a small signal having a variable amplitude for raising the potential is applied to the word line, so that a predetermined threshold voltage can be obtained. easier to conduct the memory cell transistors also low threshold voltage, as possible leaves the determination of such a memory cell transistor between Mijikatoki.

According to the seventh aspect of the present invention, in the test mode, a small signal having a variable amplitude for raising the potential is applied to the test word line, so that the memory cell transistor having a low threshold voltage can be operated for a short time. Can be determined.

According to the ninth aspect of the present invention, a drive signal of a negative potential is applied to the sense amplifier in response to the detection of the test mode to facilitate conduction of the memory cell transistor having a low threshold voltage. Since the data held in such a memory cell transistor leaks faster, the memory cell transistor having a low threshold voltage can be determined in a short time.

[0031]

FIG. 1 is a block diagram showing an entire configuration of an embodiment of the present invention. In FIG. 1, the configuration is the same as that of the conventional example shown in FIG. 19, except that a mode detection circuit 5 for detecting a disturb refresh mode is newly provided and this detection signal is applied to row decoder control circuit 6. Is done. Row address strobe signal / RAS in the mode detection circuit 5, a column address strobe signal / CAS, 0-th bit A ₀ of the write enable signal / WE and address signals are input. In response to the detection of the disturb refresh mode by the mode detection circuit 5, the row decoder control circuit 6 physically activates the word lines of the memory cell arrays 116, 126,... Reduce the time required.

FIG. 2 is a specific block diagram of the mode detection circuit shown in FIG. 2, a row address strobe signal / RAS, a column address strobe signal / CAS, and a write enable signal / WE are applied to timing detection circuits 51, 52 and 53. The timing detection circuit 51 is formed by a logical product. The write enable signal / WE is set to the "L" level, the column address strobe signal / CAS is set to the "L" level, and then the row address strobe signal / RAS is set to the falling timing. (/ WE / CAS before / RAS cycle), and outputs an "H" level signal. The output of the timing detection circuit 51 is provided to one input terminal of an AND circuit 55. Address signal A ₀ is applied to the other input terminal of AND circuit 55 via high threshold buffer 54. If the address signal A ₀ is equal to or higher than a predetermined voltage higher than the normal “H” level, the high threshold buffer 54 supplies an “H” level signal to the other input terminal of the AND circuit 55. When the two inputs become “H” level, the AND circuit 55 sets the flip-flop 56. Depending on,
Flip-flop 56 outputs an “H” level mode detection signal.

The timing detection circuit 52 detects the timing (/ RAS only refresh) at which the row address strobe signal / RAS falls to the "L" level while the column address strobe signal / CAS is at the "H" level. A second reset signal that goes to “H” level is applied to flip-flop 56 via OR circuit 57 to reset the mode detection signal.

FIGS. 3 and 4 are time charts for explaining the operation of the mode detection circuit of FIG. FIG.
As shown in (a), (b), and (c), / WE / CA
When the row address strobe signal / RAS, the column address strobe signal / CAS, and the write enable signal / WE become "L" level in the Sbefore / RAS cycle, the timing detection circuit 51 outputs "H" as shown in FIG. And outputs it to one input terminal of the AND circuit 55. When the address signal A ₀ becomes equal to or higher than a predetermined voltage higher than the power supply voltage as shown in FIG. 3D, the high threshold value buffer 54 becomes “H” shown in FIG.
A level signal is applied to the other input terminal of the AND circuit 55. In response, the AND circuit 55 changes as shown in FIG.
An "H" level signal is output, and flip-flop 56 is set. Then, from the flip-flop 56, FIG.
As shown in (k), an "H" level disturb refresh mode signal is output. Then, as shown in (h) of FIG. 4A, after the row address strobe signal / RAS falls to "L" level, the timing detection circuit 52 generates the signal at the timing of rising to "H" level. The "H" level signal is output, or the column address strobe signal / CAS is first raised to "H" level, and then the row address strobe signal / RAS is set to "L".
, The flip-flop 56 is reset.

FIG. 5 is a circuit diagram of the row decoder control circuit shown in FIG. Row decoder control circuit 6 shown in FIG.
Activates every other word line during a disturb refresh test, and normally activates a word line corresponding to a row address signal. That is, the row decoder control circuit 6 includes an inverter 61 to which a mode detection signal is input, AND circuits 62 and 64, and an inverter 63 for inverting a row address signal.
And Inverter 61 inverts the mode detection signal and outputs row decoder control signal 1. AND circuit 62 calculates the logical product of the mode detection signal and the row address signal, and outputs row decode control signal 2. AND circuit 64 outputs a row decode control signal 3 according to the mode detection signal and the row address signal inverted by inverter 63.

FIG. 6 is a block diagram showing an example of the row decoder 117 shown in FIG. Row decoder 1 shown in FIG.
17 receives a 3-bit row address signal and also receives row decode control signals 1 to 3 from the row decoder control circuit 6 shown in FIG. Then, the row decoder 1
17 is an inverter 201 for inverting the row address signal.
And a 4-input AND circuit 203 receiving a row address signal or an inverted row address signal and a row decode control signal 1, an output of the AND circuit 203, and an OR circuit 204 receiving the row decode control signal 2 or 3. .

Next, a specific operation of the embodiment of the present invention will be described with reference to FIGS. In FIG. 1, when an address signal is input to input terminal 1, operation block selection circuit 2 outputs a block selection signal for activating only a block in which a memory cell array specified by the address signal exists, For example, the column decoder 111 and the row decoder 117 are activated. Further, row address buffer 4 takes in a row address specified by the address signal, and outputs a row address signal to row decoder control circuit 6. In the normal write or read mode, the mode detection circuit 5 does not detect the disturb refresh mode, and therefore outputs an “L” level signal. This “L” level mode detection signal is inverted by inverter 61 in FIG. 5 and output as “H” level row decode control signal 1. The AND circuit 62,
64 is closed by the “L” level mode detection signal, so that the row decode control signals 2 and 3 are both “L”.
Level. Therefore, the AND circuit 203 of FIG. 5 outputs a signal in accordance with the input row address signal and the inverted row address signal. At this time, since all of the row decode control signals 2 and 3 output an “L” level signal, the OR circuit 204 derives the output of the AND circuit 203 as it is. Therefore, the row decoder 11
7 decodes only the row address signal and specifies the row address of the memory cell array 116 via the drive circuit 115 in the same manner as the conventional row decoder 114 shown in FIG. The row decoder 111 changes the column address of the memory cell array 116 via the I / O gate 112 according to the column address signal taken into the column address buffer 3 in the same manner as in the conventional example described with reference to FIG. specify.

Next, as described with reference to FIGS. 2 to 4, when the mode detection circuit 5 detects the disturb refresh mode, the mode detection signal is activated to "H" level. The "H" level mode detection signal is inverted by the inverter 61 in FIG. 5, and the row decode control signal 1 becomes "L" level, and the AND circuits 62 and 64 are opened. Then, the row address signal is output as the row decode control signal 2 via the AND circuit 62, and the row address signal is inverted by the inverter 63,
It is output as a row decode control signal 3 via the D circuit 64. That is, the row decode control signals 2 and 3 are output as contradictory row address signals.

In the row decoder 117 shown in FIG. 6, since the row decode control signal 1 is at "L" level, the AND circuit 203 outputs an "L" level signal to the OR circuit 204, and the OR circuit 204 Conflicting row decode control signals 2,
3 outputs a word line activation signal every other word.

In the disturb refresh test, when data of a memory cell that raises a word line is read out, the bit line connected to a memory cell that does not raise the word line goes to "L" level. Such data is written, and "H" level data is written into a memory cell which does not raise a word line. As described above, the disturb refresh mode is set, the memory block is selected by the operation block selecting circuit 2 by the address input, and the row decode control signal is set to the "H" level by the row address signal, for example. Row decode control signal 3 is set to “L” level, and every other word line of memory cell array 116 is activated by row decoder 117.

Next, the mode is returned from the disturb refresh mode to the normal mode, and the data in the memory cell array 116 is read in order to confirm whether the data in the memory cells connected to other than the activated word line has not been destroyed. It is checked whether the data matches the written data.

Next, predetermined data is again written into the memory cell array 116, the disturb refresh mode is entered, and the row address control signal causes the row decode control signal 2 of the row decoder control circuit 6 to attain the "L" level. And the row decode control signal 3 is set to "H" level. As a result, every other word line, which is the opposite of the previous word line, is activated for a certain period of time and then returned to the normal mode, the data of the memory cell array 116 is read, and the memory cells connected to other than the activated word line are read. It is checked whether the data of the file has been destroyed. Thus, by activating every other word line of the memory cell array 116 at the same time, the disturb refresh test of one block is completed. Then, the same test may be performed by selecting the memory cell array 126 as the next block.

As described above, according to this embodiment, for example, assuming that there are 1024 word lines in one block, it is necessary to check that the data retention time is 64 msec or more in the embodiment shown in FIG. For example, considering the case where every other word line is activated at the same time, (time for continuing activation of word line) × (number of word lines in block) / (number of word lines to be activated simultaneously) ×
(Number of blocks) = 64 msec × 1024/512 × 4
= 0.51 sec. However, a time for writing data in advance for each memory cell or reading data from a memory cell to make a determination is omitted. On the other hand, the test time when the disturb refresh test mode according to this embodiment is not used requires a time of 64 msec × 1024/1 × 4 ≒ 262 sec in the above-described example, and it is apparent that this embodiment can reduce the test time. is there.

FIG. 7 is a block diagram showing another embodiment of the present invention. In the embodiment shown in FIG. 1 described above, the disturb refresh test is performed by the operation block selection circuit 2 for each block, that is, each of the blocks 11, 12,.
In the embodiment shown in FIG. 7, the operation block selection circuit 2
., 1n are simultaneously activated by 0, and a disturb refresh test is performed in the same manner as in the prior art. For this purpose, the mode detection signal detected by the mode detection circuit 5 is supplied to the operation block selection circuit 20.

FIG. 8 is a specific block diagram of the operation block selection circuit 20 shown in FIG. In FIG. 8, in addition to a conventional operation block selection circuit 2, an OR for obtaining a logical sum of an output of the operation block selection circuit 2 and a mode detection signal is obtained.
, 2n are provided. When the mode detection signal attains the “H” level during the disturb refresh, the “H” level signal is output to the OR circuits 21, 22 and 22.
, 2n are supplied as block selection signals to the blocks 11, 12,..., 1n. In this way, by applying a block selection signal to each of the blocks 11, 12,..., 1n, these blocks are simultaneously activated,
A disturb refresh test is performed in the same manner as in the description of FIG.

The time required for the disturb refresh test according to this embodiment is calculated in the same manner as in the embodiment of FIG. 1, and is 64 msec × (1024/1) × 1 ≒ 65.5 sec. This is １ ／ of the conventional example, and the time required for the disturb refresh test can be reduced as compared with the conventional example.

In the embodiment shown in FIG. 1, every other word line is activated in the same operation block, but two or more word lines in the same block are activated. It may be. In this case, assuming that n word lines in the same operation block are activated, the result is 64 msec × (1024 / n) × 4, and the disturb refresh test can be performed in 1 / n of the conventional example.

FIG. 9 is a block diagram showing another embodiment of the present invention. The embodiment shown in FIG. 9 is a combination of the embodiments shown in FIGS. 1 and 7. That is, the mode detection signal detected by the mode detection circuit 5 is supplied to the row decoder control circuit 6 and the operation block selection circuit 20. The row decoder control circuit 6 uses the one shown in FIG. 5, and the operation block selection circuit 20 uses the one shown in FIG. Therefore, in this embodiment, FIG.
In the case of the disturb refresh, all the blocks 11, 12,.
n are selected and, as in the embodiment shown in FIG. 1, the memory cells 116, 12 of each of the blocks 11, 12,.
Every other word line of 6,..., 1n6 is activated,
A disturb refresh test is performed. In this embodiment, the time required for the disturb refresh test is 64 msec × (1024/512) × 1 = 0.128
sec, and the time required for the disturb refresh test can be reduced.

FIG. 10 is a block diagram showing still another embodiment of the present invention. In the embodiment shown in FIG. 10, in the disturb refresh mode, a small signal is applied to a word line, and the transistor having a low threshold value is easily turned on by the small signal. Do. For this,
The mode detection signal detected by the mode detection circuit 5 is supplied to the small signal generation circuit 7, and the small signal generation circuit 7 generates a small signal.
, 1n5, the memory cell array 1
16, 126,..., 1n6.

FIG. 11 shows the embodiment shown in FIG.
FIG. 12 is a block diagram showing a main part of performing a disturb refresh test by a small signal, and FIG. 12 is a block diagram of the oscillation circuit shown in FIG.

In FIG. 11, small signal generation circuit 7 includes an oscillation circuit 71, an n-channel transistor 72, and a capacitor 73. Oscillation circuit 71 includes inverters 710-714 and NAND circuit 715 as shown in FIG. . When the “H” level disturb refresh mode detection signal is applied to one input terminal of NAND circuit 715 from mode detection circuit 5, the output of NAND circuit 715 is output to NAND circuit 715 via inverters 711 to 713.
To start the oscillation. This oscillation output is inverted by inverter 714 and applied to one electrode of n-channel transistor 72. An “H” level mode detection signal is applied from the mode detection circuit 5 to the gate of the n-channel transistor 72. The other electrode of the n-channel transistor 72 is connected to the Vss line of the drive circuit 115 via the capacitor 73. Drive circuit 115
Includes a series circuit of a p-channel transistor 211 and an n-channel transistor 212, a decode signal Xi is given to each gate from the row decoder 114, and a drain of the p-channel transistor 211 and a drain of the n-channel transistor 212 are connected to a word line WLi. It is connected. A word line drive signal is applied to the source of the p-channel transistor 211. FIG. 13 is a time chart for explaining the operation of FIG. Next, FIG.
13 to 13 will be described. In the normal mode, the detection signal of the mode detection circuit 5 is at the "L" level as shown in FIG. 13A, so that the small signal generation circuit 7 does not generate a small signal. Therefore, the memory cell arrays 116 and 12 shown in FIG.
, 1n6 are respectively selected by the operation block selection circuit 2, and accessed by the address signal in the same manner as in the conventional example. In the disturb refresh test, for example, block 11 shown in FIG. 10 is selected by operation block selection circuit 2, and then, / WE / CAS
When a signal at the timing of before / RAS cycle is input to mode detection circuit 5 and an address signal A ₀ higher than the “H” level input in normal mode is input, it is connected to a word line to be activated. "L" level data is written to the memory cell, and "H" level data is written to the memory cell connected to the inactive word line. As shown in FIG. 13E, when the mode detection signal of the “H” level is output from the mode detection circuit 5, the oscillation circuit 71 generates a pulse signal that repeats the “H” and “L” levels. At this time, n-channel transistor 72 is turned on in response to the mode detection signal at the “H” level, and a clock signal from oscillation circuit 71 is applied to Vss line of word line drive circuit 115 via n-channel transistor 72 and capacitor 73. Signal, a small signal is applied to the non-selected word line WLi, and in the memory cells of the memory cell array 116 connected to the non-selected word line, the potential of the word line slightly increases, so that the threshold voltage is increased. The subthreshold leakage current is much larger than that of a non-defective memory cell even if the transistor of the defective defective memory cell is turned on or off, and data at "H" level is lost. Then, data is sequentially read from the memory cells corresponding to the non-selected word lines, and it is determined whether the written data matches the read data.

As described above, in the disturb refresh mode, as compared with the normal mode, the transistor connected to the unselected word line WLi and having a threshold lower than the design value leaks from the memory cell capacitance to the bit line BLi. Is more likely to occur, and defects can be detected in a short test time.

Note that, for example, 16MDRAM 4K R
In the case of performing the refresh refresh test of the efresh product, it took 260 sec. In this embodiment, however, the time for continuing the activation of the word line described in the embodiment of FIG. 26 sec
Testing can be performed to a degree.

Incidentally, the capacitor 73 shown in FIG. 11 may have a capacitance of about several hundred pF, and is preferably arranged in the vicinity of the row decoders 114, 124,..., 1n4 away from the pad of Vss. That is, if the capacitor 73 is arranged at a position close to the pad of Vss, the potential of Vss is rapidly increased even if an attempt is made to output a pulse, and no pulse is output.
It is preferable to arrange them so that the distance up to 15 is shorter.

FIG. 14 is a view showing still another embodiment of the present invention. In this embodiment, a dedicated word line WLj for applying a small signal to the bit lines BLi and / BLi is provided in addition to the conventional word line WLi. Parasitic capacitances 225 and 226 exist between the word line WLj and the bit lines BLj and / BLj. Bit line BLi, /
N-channel transistors 223 and 224 are connected between BLi and BLj and / BLj, and these n-channel transistors 223 and 224 are connected to mode detection circuit 5.
When the disturb refresh mode is detected.

The small signal generation circuit 72 includes an oscillation circuit 71, n-channel transistors 231 and 232, and an inverter 2
33. The detection signal of mode detection circuit 5 is inverted and applied to the gate of n-channel transistor 231 by inverter 233, and the detection signal of mode detection circuit 5 is applied to the gate of n-channel transistor 232.
The oscillation output of the oscillation circuit 71 is given to the drain of the n-channel transistor 232,
The word line WLj is connected to the source of the N. 32 and the drain of the n-channel transistor 231, and the potential of Vss is applied to the source of the n-channel transistor 231.

FIG. 15 is a time chart for explaining the operation of the embodiment shown in FIG. In the normal mode shown in FIG. 15A, the detection signal φ _T of the mode detection circuit 5 becomes “L” level as shown in FIG. 15D, the n-channel transistor 231 is turned on, and the other n-channel transistors 232 and 232 are turned on. 223 and 224 are turned off. Therefore, the bit lines BLj and / BLj are connected to the bit lines BLi and / B
15 (A) and becomes high impedance as shown in FIG. 15 (f), and the word line WLj becomes
Since it is connected to the Vss potential as shown in (e) of (A), the memory cell array is accessed by the address signal in the same manner as in the prior art.

Next, as shown in FIG. 15B, the mode detection circuit 5 outputs / WE / CAS before / RA
When it is detected that the S cycle and the address signal A ₀ have become equal to or higher than a predetermined voltage higher than the normal “H” level, the mode detection signal φ _T changes to “H” as shown in (e) of FIG. ”Level and the n-channel transistor 2
31 is turned off, and the other n-channel transistors 232, 223 and 224 conduct. Therefore, the oscillating circuit 71 starts oscillating according to the detection output of the mode detecting circuit 5. The oscillation output of the oscillation circuit 71 is transmitted to the word line WLj via the n-channel transistor 232, and further transmitted to the bit line B via the parasitic capacitances 225 and 226.
Lj and / BLj are transmitted to bit lines BLi and / BLi. As a result, the bit lines BLi and / BLi instantaneously have a negative potential as compared with the normal mode, so that a transistor having a threshold lower than the designed value does not need to be turned on or turned on at that moment. Since the sub-threshold leakage current is much larger than that of the threshold value transistor, the data at the “H” level is damaged.
Therefore, the time required to keep the word line activated as described with reference to FIG. 1 can be shortened, and the test time of the disturb refresh test can be shortened. Note that the bit lines BLj, /
Although BLj has a negative potential, a negative potential V _BB is applied to the substrate, and the bit lines BLj and / BLj do not become lower than this, so that no current flows between the substrate and the substrate. I have.

FIG. 16 is a diagram showing still another embodiment of the present invention, and FIG. 17 is a diagram showing the negative potential generating circuit of FIG.

In this embodiment, a negative voltage is transmitted for a certain period to the drive signal of the sense amplifier 251 only when the disturb refresh mode is set, and the memory cell transistor having a threshold lower than the design value is turned on. It was made easier. That is, a negative potential generating circuit 75 is provided instead of the small signal generating circuit 7 shown in FIG. This negative potential generation circuit 75 includes an oscillation circuit including inverters 751 to 755 and a NAND gate 756, and n-channel transistors 758 and 758, as shown in FIG.
59, capacitor 757 and n-channel transistor 76
0, and a capacitor 761 for charging a charge. Capacitor 761 is charged to a potential of the negative potential - [Delta] V, "H" level signal phi _T from the mode detection circuit 5 when applied to NAND gate 756, the oscillation circuit starts oscillation operation. When the oscillation circuit outputs a signal that rises from the “L” level to the “H” level to one electrode of capacitor 757, the potential of node 762 becomes 2 Vth or more due to capacitive coupling of capacitor 757. (Vth is the threshold voltage of the n-channel transistors 758 and 759). Then, n-channel transistors 758 and 759 conduct, and node 7
62, a discharge current flows to the ground node via these transistors 758 and 759, and the potential of node 762 becomes 2
When the voltage drops to Vth, the n-channel transistor 758,
759 becomes non-conductive. At this time, since the potential of the node 763 is lower than the drain of the node 762, the n-channel transistor 760 remains off. Then, when the oscillation circuit outputs a signal that falls from the “H” level to the “L” level, the potential of the node 762 falls from 2 Vth to a negative potential due to capacitive coupling of the capacitor 757. Then, since the potential of the node 763 is higher than the potential of the node 762, the n-channel transistor 760 is turned on, charge is drawn from the node 763 to the node 762, and the potential of the node 763 becomes higher than the potential of the node 762 by Vth. Then, the n-channel transistor 760 is turned off. By repeating this operation, a negative potential is generated.

The detection signal of mode detection circuit 5 is applied to the gate of n-channel transistor 232 and is inverted by inverter 233 to be
31 gates. n-channel transistor 2
The source of 32 is supplied with the negative potential −ΔV generated by the negative potential generating circuit 75, and the drain and the source of the n-channel transistor 231 are supplied to the source of the n-channel transistor 242 of the drive circuit 115. The potential of Vss is applied to the drain of the n-channel transistor 231. Further, a sense amplifier drive signal φ _S is applied to the gate of n-channel transistor 242, and this sense amplifier drive signal φ _S
It is also given to one gate. The power supply voltage + Vcc is applied to the source of the p-channel transistor 241, and its drain is connected to the drain of the n-channel transistor 242 and to the sense amplifier 251. −ΔV is 0 <| −ΔV | <| Vth (221)
|, For example, about -0.5V. As a method of adjusting ΔV, the transistor 7
Change the threshold of 59,758. Inverter 75
The power supply voltage supplied to 5 is reduced, and the output amplitude is reduced. Further, a transistor is connected in series with the transistors 759 and 758. And so on.

FIG. 18 is a time chart for explaining the operation of the embodiment shown in FIG. In the normal mode, as shown in (b) of FIG. 18A, since the detection signal φ _T of the mode detection circuit 5 is at the “L” level, the n-channel transistor 231 turns on and the n-channel transistor 232 Is off. Therefore, when sense amplifier drive signal φ _S at “H” level is applied to the gate of n-channel transistor 242, n-channel transistor 242 is turned on and sense amplifier 25
1 is supplied with a potential S ₂ N of Vss as shown in FIG. Therefore, bit lines BLi, / B
Either of Li is reduced from 1/2 Vcc to Vss by the sense amplifier as shown in FIG.

On the other hand, in the disturb refresh mode, since the detection signal of mode detection circuit 5 attains the "H" level, a potential of -.DELTA.V is generated from negative potential generation circuit 75, and "H" level mode detection signal .phi. _In response to _T , n-channel transistor 232 is turned on, and n-channel transistor 242 is also turned on in response to sense amplifier drive signal φ _S , so that sense amplifier 251 has-as shown in (d) of FIG. A negative potential of ΔV is provided. For this reason, one of the bit lines BLi and / BLi is switched to the state shown in FIG.
As shown in (e) of (B), −ΔV from Ｖ Vcc.
Since the sub-threshold leakage current becomes much larger than that of a transistor having a normal threshold even if a memory transistor having a threshold lower than the designed value is turned on or off, the stored “H” data is Be impaired.

[0064]

As described above, according to the first aspect of the present invention, every other row of the plurality of memory cells is activated collectively in response to the detection of the test mode. By reading the stored data and comparing it with the written data, it is possible to easily and quickly determine a memory cell transistor having a threshold voltage lower than a predetermined threshold voltage.

According to the second aspect of the present invention, a plurality of memory blocks are collectively selected, and among a plurality of memory cell transistors in each block, memory cell transistors in a predetermined row are collectively activated to store data. By reading the stored data and comparing it with the written data,
A memory cell transistor having a threshold voltage lower than a predetermined threshold can be determined in a shorter time.

According to the third aspect of the present invention, in response to the detection of the test mode, a small signal whose amplitude changes to increase the potential of the word line is applied to the word line, thereby providing a memory cell having a low threshold value. The transistor can be determined in a short time.

In the invention according to claim 5 , a test mode word line is provided separately from the plurality of word lines, and the amplitude is increased to increase the potential of the test word line in response to the detection of the test mode. By giving a changing small signal, a memory cell transistor having a low threshold voltage can be determined in a short time.

According to the seventh aspect of the present invention, since the drive signal for instantaneously setting the bit line to a negative potential is applied in response to the detection of the test mode, the memory cell transistor having a low threshold value is provided. Can be determined in a short time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention.

FIG. 2 is a specific block diagram of the mode detection circuit shown in FIG.

FIG. 3 is a time chart for explaining an operation of the mode detection circuit shown in FIG. 2;

FIG. 4 is a time chart for explaining an operation of the mode detection circuit in a normal mode and a test mode.

FIG. 5 is a block diagram of a row decoder control circuit shown in FIG. 1;

FIG. 6 is a block diagram illustrating an example of a row decoder illustrated in FIG. 1;

FIG. 7 is a block diagram of another embodiment of the present invention.

8 is a specific block diagram of the operation block selection circuit shown in FIG.

FIG. 9 is a block diagram of another embodiment of the present invention.

FIG. 10 is a block diagram showing still another embodiment of the present invention.

FIG. 11 is a block diagram showing a main part for performing a disturb refresh test by a minute signal in the embodiment shown in FIG. 10;

FIG. 12 is a block diagram of the oscillation circuit shown in FIG. 11;

FIG. 13 is a time chart for explaining operations in a normal mode and a test mode of the embodiment shown in FIG. 1;

FIG. 14 is a block diagram showing a main part of still another embodiment of the present invention.

FIG. 15 is a time chart in the normal mode and the test mode of the embodiment shown in FIG. 14;

FIG. 16 is a diagram showing still another embodiment of the present invention.

FIG. 17 is a circuit diagram showing a negative potential generating circuit shown in FIG. 16;

FIG. 18 is a time chart for explaining operations in a normal mode and a test mode of the embodiment shown in FIG. 16;

FIG. 19 is a block diagram of a conventional semiconductor memory device divided into a plurality.

20 is a block diagram illustrating an example of a row decoder illustrated in FIG.

FIG. 21 is a circuit diagram showing an example of the memory cell array shown in FIG.

FIG. 22 is a circuit diagram for describing an operation until data read from a memory cell is transmitted to an I / O line.

FIG. 23 is a time chart for explaining the operation of FIG. 22;

FIG. 24 is a diagram showing a part of the memory cell array shown in FIG. 21;

FIG. 25 is a time chart showing an operation when reading information of a memory cell capacitance Ci connected to a word line WLi of FIG. 24;

[Explanation of symbols]

 2, 20 operation block selection circuit 3 column address buffer 4 row address buffer 5 mode detection circuit 6 row decoder control circuit 7 small signal generation circuit 11, 12,... 1n operation blocks 51, 52, 53 timing detection circuit 54 high threshold buffer 55, 62, 64, 203 AND circuit 56 Flip-flop 57, 204 OR circuit 111, 121... 1n1 Column decoder 112, 122... 1n2 I / O gate 113, 123. 126 ... 1n6 Memory cell array 117,127 ... 1n7 Row decoder 71 Oscillator circuit 75 Negative potential generation circuit

Continuation of front page (56) References JP-A-6-176598 (JP, A) JP-A-4-159688 (JP, A) JP-A-5-144294 (JP, A) JP-A-6-119777 (JP) , A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 29/00 G11C 11/40-11/419

Claims (9)

(57) [Claims] 1. A plurality of word lines, a plurality of bit lines intersecting each word line, each connected to one of the plurality of word lines and one of the plurality of bit lines. Having a built-in test circuit for determining, in a test mode, a memory cell transistor having a threshold voltage lower than a predetermined threshold voltage among the plurality of memory cell transistors. A memory device, comprising: a test mode detecting means for detecting the test mode; and a test mode detecting means for detecting every other row of the plurality of memory cell transistors in response to the test mode being detected by the test mode detecting means. A semiconductor memory device comprising activation means for activating memory cell transistors collectively. 2. A plurality of word lines, a plurality of bit lines intersecting each word line, each connected to one of the plurality of word lines and one of the plurality of bit lines, and A plurality of memory cell transistors divided into a plurality of blocks; and a test for determining, in a test mode, a memory cell transistor having a threshold voltage lower than a predetermined threshold among the plurality of memory transistors. A semiconductor memory device having a built-in circuit, comprising: a test mode detecting means for detecting the test mode; and a write for writing data to any of the plurality of memory cell transistors or reading the written data. In the read mode, a designated block is selected from the plurality of blocks, and the test mode A block selecting means for collectively selecting the plurality of blocks in response to detection of a mode; and a memory of a predetermined row among a plurality of memory cell transistors of the plurality of blocks selected collectively. A semiconductor memory device comprising activation means for activating cell transistors collectively. 3. The semiconductor memory device according to claim 2 , wherein said activating means simultaneously activates memory transistors in every other row. 4. The semiconductor memory device according to claim 2 , wherein said activating means activates the memory cell transistors every several rows at a time. 5. A plurality of word lines, a plurality of bit lines intersecting each word line, each connected to one of the plurality of word lines and one of the plurality of bit lines. Having a built-in test circuit for determining, in a test mode, a memory cell transistor having a threshold voltage lower than a predetermined threshold voltage among the plurality of memory cell transistors. A memory device, comprising: a test mode detecting means for detecting the test mode; and an amplitude for increasing a potential of the word line in response to a test mode being detected by the test mode detecting means. A semiconductor memory device including a minute signal generating means for giving a changing minute signal. 6. The apparatus according to claim 6, further comprising word line driving means for driving said word line, wherein said small signal generating means is a pulse signal generating means for generating a repetitive pulse signal, and said small signal generating means is generated by said pulse signal generating means. 6. The semiconductor memory device according to claim 5 , further comprising a capacitor for transmitting a pulse signal to said word line driving means. 7. A plurality of word lines, a plurality of bit lines intersecting each word line, each connected to one of the plurality of word lines and one of the plurality of bit lines. Having a built-in test circuit for determining, in a test mode, a memory cell transistor having a threshold voltage lower than a predetermined threshold voltage among the plurality of memory cell transistors. A storage device, comprising: a test word line provided in parallel with the plurality of word lines, intersecting with the plurality of bit lines, and coupled to each bit line by a parasitic capacitance, for detecting the test mode. A test mode detecting means and, in response to the test mode being detected by the test mode detecting means, raise the potential of the test word line. Because the amplitude with a precise signal generating means for providing a small signal changes, the semiconductor memory device. 8. A memory cell transistor connected between a bit line intersecting the test word line and a plurality of bit lines connected to each of the memory cell transistors. 8. The semiconductor memory device according to claim 7 , further comprising a switching element which is turned off in a write / read mode for writing or reading data written therein, and turned on in accordance with said test mode. 9. A plurality of word lines, a plurality of bit lines intersecting each word line, each connected to one of the plurality of word lines and one of the plurality of bit lines. A plurality of memory cell transistors, and a plurality of sense amplifiers connected to the plurality of bit lines, and among the plurality of memory cell transistors, a memory cell having a threshold voltage lower than a predetermined threshold voltage. A semiconductor memory device having a built-in test circuit for determining a transistor in a test mode, the test mode detection means for detecting the test mode, and the test mode detection means detecting a test mode by the test mode detection means. A drive signal of a negative potential is applied to the sense amplifier to facilitate conduction of the memory cell transistor having a low threshold voltage. With a negative potential signal generating means, the semiconductor memory device.