WO2004079745A1

WO2004079745A1 - Semiconductor memory and method for accumulating charge in dynamic memory cell

Info

Publication number: WO2004079745A1
Application number: PCT/JP2003/002638
Authority: WO
Inventors: Yoshimasa Yagishita; Toshiya Uchida
Original assignee: Fujitsu Limited
Priority date: 2003-03-06
Filing date: 2003-03-06
Publication date: 2004-09-16
Also published as: JPWO2004079745A1; JP4137060B2

Abstract

A predetermined number of first word lines are multiply selected during a first selection period to activate sense amplifiers, so that a predetermined quantity of charge is accumulated in memory cells connected to the first word lines. The sense amplifiers are de-activated while the first word lines are selected, and a predetermined number of second word lines are multiply selected. Thus, the accumulated charge in the memory cells and bit lines connected to the first word lines are redistributed to the memory cells connected to the second word lines. Thereafter, the selection of the first and second word lines are undone to read data from the memory cells after a predetermined time to clarify the relation between the quantity of charge accumulated in the memory cells and the data holding characteristic. Therefore, the charge holding characteristic of the memory cells is accurately evaluated in a semiconductor memory having dynamic memory cells. A special voltage generating circuit and a capacitor for charge accumulation are unnecessary to accumulate a desired quantity of charge in the memory cells. Therefore, the chip size of a semiconductor memory is prevented from increasing.

Description

TECHNICAL FIELD The charge storage method of a semiconductor memory and a dynamic memory cell

The present invention relates to a technology for equalizing data retention characteristics of a semiconductor memory having dynamic memory cells. Background art

Memory cells of semiconductor memories such as DRAMs and pseudo SRAMs have a capacity to hold data as electric charges. Since the charge stored in the memory cell gradually escapes, the data written in the memory cell disappears after a predetermined time. Therefore, a refresh operation for writing back the data in the memory cell is required.

The ability of the memory cell to hold the charge affects the refresh cycle. The refresh cycle needs to be increased as the amount of charge leakage increases. For this reason, the charge retention capability (data retention characteristics) directly affects power consumption. Therefore, in the development and mass production of this type of semiconductor memory, detailed evaluation of the data retention characteristics (refresh characteristics) is important.

One of the evaluations of the data holding characteristics is to set the amount of charge held in the memory cell capacity to a predetermined value and measure the data holding time for each amount of charge. The amount of charge held in the memory cell capacitance can be set depending on the voltage of the bit line connected to the memory cell.

As one method of accumulating a desired amount of charge in a memory cell capacitance, a power supply voltage of a sense amplifier connected to a bit line is adjusted (for example, Patent Document 1). The bit line is set to a predetermined voltage by adjusting the sense amplifier power supply, and a desired amount of charge is stored in the memory cell capacitance. However, when the sense amplifier power supply changes, the bit line precharge voltage and the memory cell plate voltage also change. For this reason, after accumulating charges in the memory cell capacity, it is necessary to wait for a long time until the precharge voltage and the plate voltage stabilize, which increases the evaluation time. There is.

Another method of storing a desired amount of charge in the memory cell capacitance is to adjust the selection period of the word line connected to the gate of the transfer transistor of the memory cell and adjust the connection time between the bit line and the memory cell capacitance. Has been done. However, the word line selection period varies depending on transistor manufacturing errors. For this reason, the amount of charge held in the memory cell capacity differs for each semiconductor memory chip. That is, quantitative evaluation is not possible.

Further, there is a method of forming a test circuit for directly applying a predetermined voltage to a bit line in a semiconductor memory. However, test circuits increase chip size and increase the manufacturing cost of semiconductor memory. Also, the extra load associated with the test circuit is added to the bit line.

Hereinafter, prior art documents related to the present invention are listed.

(Patent Document)

(1) Japanese Patent Application Laid-Open No. 7-192455 discloses the invention

An object of the present invention is to store a desired amount of electric charge in the capacity of a dynamic memory cell. In particular, it is to store a desired amount of charge in the memory cell capacity without increasing the chip size.

It is another object of the present invention to store a desired amount of electric charge in the capacity of a dynamic memory cell in the same environment as when normally accessing a semiconductor memory.

Another object of the present invention is to quantitatively and quickly evaluate the data retention characteristics of a dynamic memory cell.

In one embodiment of the present invention, a predetermined number of first read lines are multiplex-selected in the first selection period, and a signal amount corresponding to data held in a plurality of dynamic memory cells is read out to a bit line. Thereafter, the sense amplifier is activated, and the signal amount on the bit line is amplified. The sense amplifier is deactivated after amplifying the signal amount. Next, a predetermined number of second word lines are multi-selected with the first word line selected. The amplified signal amount is written to a dynamic memory cell connected to the second word line. The stored charges of the memory cells connected to the first word line and the stored charges of the bit lines are redistributed to the memory cells connected to the second word line. Therefore, a desired amount of charge can be stored in the memory cell according to the number of selected first word lines and the number of subsequently selected second word lines. By distributing the amount of charge stored in the bit line and the plurality of memory cells, a desired amount of charge can be stored in the memory cell, so that a special voltage generation circuit and a capacitor for charge storage are not required. Therefore, it is possible to prevent the chip size of the semiconductor memory from increasing.

It is not necessary to connect a special circuit for supplying electric charge to the bit line, etc., so that the load on the bit line can be the same as before. As a result, for example, it is possible to prevent the access time from becoming longer due to an increase in load.

For example, the first and second selection periods are set during a test mode for evaluating data retention characteristics of a memory cell. After the charge is redistributed, the first and second lead lines are deselected, and after a predetermined time, data is read from the memory cell, revealing the relationship between the amount of charge stored in the memory cell and the data retention characteristics. become. For this reason, by repeating the evaluation while changing the number of the first lead lines to be selected and the number of the second lead lines to be selected thereafter, in the semiconductor memory having the dynamic memory cells, the data retention characteristics of the memory cells can be accurately determined. Can be evaluated.

Unlike the conventional method in which the voltage of the bit line is adjusted by controlling the voltage generation circuit such as the power supply of the sense amplifier, other voltage generation circuits in the semiconductor memory are not affected when the charge is stored in the memory cell. Therefore, there is no need to wait until the other voltage generation circuits are stabilized after storing the desired charge in the memory cell. As a result, the refresh characteristics of the dynamic memory cell can be evaluated in a short time.

In another embodiment of the present invention, the sense amplifier mask circuit masks the reception of the access end signal in an access cycle other than the last access cycle in the first selection period. This mask inhibits the inactivation of the sense amplifier activation signal. Therefore, the sense amplifier mask circuit allows the sense amplifier to continue operating during a predetermined period of the first selection period.

In another embodiment of the present invention, the plurality of decode circuits of the word line control circuit are addressable for generating a decode signal for selecting one of the word lines. Decode the signal. The latch circuit of each decode circuit latches the decode signal in the first and second selection periods to keep outputting the decode signal. Since a once generated decode signal can be held with a simple circuit, multiple lines can be selected by simply supplying addresses sequentially as in normal access.

In another embodiment of the present invention, the precharge circuit precharges the bit line to a predetermined voltage. The precharge control circuit stops the operation of the precharge circuit during the first and second selection periods. Therefore, the bit line can be reliably floated during the first and second selection periods, and a desired amount of charge can be accurately stored in the memory cell.

In another embodiment of the present invention, the precharge signal generation circuit of the precharge circuit operates during activation of the precharge control signal. The precharge control circuit activates the precharge control signal in response to an access start signal that starts access to a memory cell, and deactivates the precharge control signal in response to an access end signal that ends access to a memory cell. I do. The precharge mask circuit of the precharge circuit masks the reception of the access end signal during the first selection period. This mask inhibits the deactivation of the precharge control signal. For this reason, the precharge mask circuit allows the precharge operation of the bit line to be stopped during the first selection period.

In another embodiment of the present invention, the word line control circuit selects one of the first word lines first, and selects the rest of the first word line after the activation of the sense amplifier. For example, among the memory cells accessed in the first selection period, at least a memory cell connected to one of the first-selected first code lines has a first logic level written in advance. The memory cell accessed in the second selection period is written with the second logic level in advance. Since the number of memory cells to which the first logic level is previously written can be minimized, the write operation time can be shortened. Therefore, the period for accumulating charges in the memory cell can be shortened, and the evaluation time of the data retention characteristics of the memory cell can be shortened.

In another embodiment of the present invention, the word line control circuit selects the first word line simultaneously. For example, a first logic level is written in advance to a memory cell accessed during the first selection period. The memory cells accessed during the second selection period are stored in the second logic level in advance. The bell is written. Since the first word lines are simultaneously selected, the first selection period can be minimized, and the period for accumulating charges in the memory cells can be shortened. As a result, the time for evaluating the charge retention characteristics of the memory cell can be reduced. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram showing a first embodiment of the semiconductor memory of the present invention. FIG. 2 is a circuit diagram showing details of a test control circuit, a sense amplifier control circuit, a precharge control circuit, and a code decoder shown in FIG.

FIG. 3 is a circuit diagram showing details of the memory array, precharge circuit, and sense amplifier array shown in FIG.

FIG. 4 is a waveform diagram showing an operation of the memory array during the test mode of the FCRAM in the first embodiment.

FIG. 5 is a waveform chart showing the operation of the memory array during the normal operation mode in the first embodiment.

FIG. 6 is a timing chart showing the operation of the control circuit during the test mode of the FCRAM in the first embodiment.

FIG. 7 is an explanatory diagram showing the amount of charge stored in the memory cell corresponding to the number of selected word lines in the first embodiment.

FIG. 8 is a waveform diagram showing the operation of the memory array during the test mode in the second embodiment of the semiconductor memory of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the drawings. Double circles in the figure indicate external terminals. In the figure, the signal lines indicated by bold lines are composed of a plurality of lines. Some of the blocks to which the bold lines are connected are composed of a plurality of circuits. Signals supplied via external terminals use the same symbols as the terminal names. Signals ending with ^ "indicate positive logic. Signals ending with 〃 X" indicate negative logic.

FIG. 1 shows a first embodiment of the semiconductor memory of the present invention. This semiconductor memory is formed on a silicon substrate as a fast asynchronous RAM (FCRAM) using a CMOS process. The FCRAM is a pseudo SRAM having a DRAM memory and an SRAM interface. The FCRAM periodically performs a refresh operation inside the chip without receiving a refresh command from the outside, and retains the data written to the memory cells. This FCRAM is used, for example, as a work memory mounted on a mobile phone.

FCRAM has two operation modes: a normal operation mode for executing a read operation, a write operation, and a refresh operation, and a test mode for evaluating the refresh characteristics of a memory cell.

Read and write operations are performed in response to command signals CMD (read command and write command) supplied via external terminals. The refresh operation is performed in response to a refresh request generated inside the FCRAM without being recognized by an external system.

FCRAM consists of command control circuit 10, mode register 12, refresh timer 14, refresh control circuit 16, refresh address counter 18, address input circuit 20, data input / output circuit 22, and end address switching circuit 2. 4. It has a core control circuit 26 and a memory core 28. The core control circuit 26 has a test control circuit 30 (part of a lead line control circuit), a sense amplifier control circuit 32 and a precharge control circuit 34. FIG. 1 shows only the main signals necessary for explaining the present invention.

The command control circuit 10 receives a command signal CMD (for example, a chip enable signal / CE, a write enable signal / WE, an output enable signal / 0E, etc.) supplied from an external terminal. The command control circuit 10 outputs a read control signal RDZ for executing a read operation and a write control signal WRZ for executing a write operation in response to the received command signal CMD. The command control circuit 10 outputs a test mode signal DSRZ when receiving a command signal CMD of a predetermined combination prohibited in the normal operation mode. The FCRAM transitions from the normal operation mode to the test mode by the output of the test mode signal DSRZ.

The mode register 12 is a register for setting an operation mode of the FCRAM. The mode register 12 is set according to the logic level of the data signal supplied to the data terminal DQ when the mode register setting command MRS is supplied via the command terminal CMD.

The refresh timer 14 outputs a refresh request signal RQ at a predetermined cycle. The refresh address counter 18 operates in response to a refresh request signal RQ, and outputs a refresh address signal RFA composed of a plurality of bits. The refresh address signal RFA is a row address signal for selecting a read line WL described later.

The address input circuit 20 receives the address signal ADD supplied from the address terminal ADD, and outputs the received signal as a row address signal RA and a column address signal CA. The row address signal RA is used to select a word line WL described later. The column address signal CA is used to select a bit line BL (or / BL) described later.

The data input / output circuit 22 outputs read data transferred from the memory core 28 via the common data bus CDB to the data terminal DQ during a read operation. The data input / output circuit 22 receives write data via the data terminal DQ during a write operation, and transfers the received data to the memory core 28 via the common data bus CDB.

When receiving the low-level refresh signal REFZ (read cycle or write cycle), the address switching circuit 24 outputs the row address signal RA as the internal row address signal IRA. When receiving the high-level refresh signal REFZ (refresh cycle), the address switching circuit 24 outputs the refresh address signal RFA as the internal low address signal IRA. That is, in a read operation and a write operation, an externally supplied address signal RA is selected, and in a refresh operation, an internally generated refresh address signal FRA is selected.

The core control circuit 26 outputs a plurality of control signals for controlling the operation of the memory core 28 when receiving one of the read control signal RDZ, the write control signal WRZ, and the refresh start signal RSZ. . The core control circuit 26 reads externally supplied It also has the function of an arbiter that determines which of the read command and write command (command signal CMD) or the internally generated refresh command (refresh request signal RQ) has priority. The core control circuit 26 activates the refresh signal REFZ (high level) when performing a refresh operation in response to the refresh command.

The test control circuit 30 of the core control circuit 26 is a basic timing signal for operating the memory core 28 according to the read control signal RDZ, write control signal WRZ and refresh start signal RSZ during the normal operation mode. (Such as the mouth timing signal RASZ ヽ latch enable pulse signal LEPZ and precharge signal SPRDX described in Fig. 6 described later). When receiving the test mode signal DSRZ during the test mode, the test control circuit 30 outputs the bit line control signal DSRBTZ and the read line control signal DSRWLX to start the refresh test.

The sense amplifier control circuit 32 of the core control circuit 26 operates the sense amplifier at normal timing according to the read control signal RDZ, the write control signal WRZ, and the refresh start signal RSZ during the normal operation mode. The latch enable signal LEX is output. The sense amplifier control circuit 32 outputs the latch enable signal LEX at the test timing according to the bit line control signal DSRBTZ during the test mode.The precharge control circuit 34 of the core control circuit 26 normally operates During the operation mode, the bit line short signal BRSX for precharging the bit line is output at normal timing according to the read control signal RDZ, the write control signal WRZ, and the refresh start signal RSZ. The precharge control circuit 34 outputs the bit line short signal BRSX at a test timing according to the bit line control signal DSRBTZ during the test mode.

The memory core 28 has a sense amplifier array SAA, a precharge circuit PRE, a memory array ARY, a word decoder TOEC (another part of the word line control circuit), a column decoder CDEC :, a sense buffer SB, and a write amplifier WA. ing. Details of the sense amplifier array SAA and the precharge circuit PRE will be described later with reference to FIG. The memory array ARY is composed of a plurality of volatile memory cells arranged in a matrix. It has an MC (dynamic memory cell), a plurality of lead lines WL and a plurality of bit line pairs BLZ and BLX connected to the memory cell MC.

The memory cell MC is the same as a general DRAM memory cell, and has a capacitor for holding data as electric charges and a transfer transistor disposed between the capacitor and the bit line BL. The gate of the transfer transistor is connected to the word line WL.

The mode decoder WDEC selects one of the word lines WL according to the internal row address signal IRA, and changes the selected word line WL to a high level in synchronization with the timing signal.

The column decoder CDEC outputs a column line signal for turning on a column switch connecting each of the bit lines BL, / BL and the data bus DB according to the column address signal CAD.

The sense buffer unit SB amplifies the signal amount of read data on the data bus DB during a read operation and outputs the amplified signal to the common data bus CDB. The write amplifier WA amplifies the signal amount of write data on the common data bus CDB during a write operation and outputs the amplified signal to the data bus DB.

FIG. 2 shows details of the test control circuit 30, the sense amplifier control circuit 32, the precharge control circuit 34 and the read decoder TOEC shown in FIG.

The test control circuit 30 is activated in response to the shift register 30a operating in synchronization with the read pulse signal WLPZ and the high-level test mode signal DSRZ, and outputs the bit line control signal DSRBTZ and the word line control signal DSRWLX. It has a signal generating circuit 30b for generating.

The latch LT1 at the first stage of the shift register 30a latches the high level (internal power supply voltage VII) and outputs the low level in synchronization with the rising edge of the first read pulse signal WLPZ. The next-stage latch LT2 receives the output of the latch LT1 and outputs a high level in synchronization with the falling edge of the first word pulse signal WLPZ. The third-stage latch LT3 receives the output of the latch LT2 in synchronization with the second rising edge of the read pulse signal WLPZ, and outputs a low level to the signal generation circuit 30b.

The signal generation circuit 30b operates while the test mode signal DSRZ is at a low level (normal operation mode). ), The bit line control signal DSRBTZ is held low and the word line control signal DSRWLX is held high. The signal generation circuit 30b changes the bit line control signal DSRBTZ to a high level and the word line control signal DSRWLX to a low level in response to the change of the test mode signal DSRZ to a high level. The signal generation circuit 30b changes the bit line control signal DSRBTZ to low level in response to the change of the output of the latch LT3 to low level during the high level period of the test mode signal DSRZ. Further, after the bit line control signal DSRBTZ changes to low level, the signal generation circuit 30b changes the level of the mouth timing signal RASZ, which is a basic timing signal for operating the memory core 28, to low level. In response to the change, the line control signal DSRWLX is changed to a high level.

The sense amplifier control circuit 32 has logic gates for controlling the flip-flops FF1 and FF2 and the flip-flops FF1 and FF2.

The flip-flop FF1 is set in synchronization with the rising edge of the code pulse signal WLPZ, and is reset in synchronization with the starter signal STTX which changes to a low level for a predetermined period when the FCRAM is turned on. The flip-flop FF1 is reset in synchronization with the reset pulse signal RSTPZ output at the end of the refresh test.

The NOR gate N0R1 connected to the output of the flip-flop FF1 holds the test latch enable signal DSRLEZ low while the test mode signal DSRZ is low (during normal operation mode). NOR gate N0R1 changes test latch enable signal DSRLEZ to high in response to the change of test mode signal DSRZ to high. That is, the test latch enable signal DSRLEZ is activated in synchronization with the transition from the normal operation mode to the test mode. After that, the NOR gate N0R1 deactivates (low level) the test latch enable signal DSRLEZ in synchronization with the read pulse signal WLPZ.

The flip-flop FF2 changes the latch enable signal LEX (sense amplifier activation signal) to a low level in synchronization with the latch enable pulse signal LEPZ (access start signal) during the normal operation mode. When the latch enable signal LEX changes to low level, the sense amplifier activation signals PSA and NSA shown in FIG. 3 described later change to high level and low level, respectively, and the sense amplifier SA of the sense amplifier array SAA is activated. Be converted to At this time, the bit line control signal DSRBTZ, the refresh test signal TREFZ, the precharge signal SPRDX, and the test latch enable signal DSRLEZ are flip-flops for low level, low level, high level, and low level, respectively. All inputs to the FF2 3-input NOR gate are low.

After the sense amplifier SA amplifies the voltage on the bit line and the precharge signal SPRDX (access end signal) changes to low level for a predetermined period, one of the inputs of the 3-input NOR gate changes to high level and latch enable. The signal LEX goes high. When the latch enable signal LEX changes to a high level, the sense amplifier activation signals PSA and NSA change to a low level and a high level, respectively, and the sense amplifier SA of the sense amplifier array SAA is deactivated. That is, the amplification operation is completed.

As described above, the flip-flop FF2 activates the latch enable signal LEX in response to the latch enable pulse signal LEPZ for starting access to the memory cell MC, and terminates the access to the memory cell MC. Operates as a sense amplifier signal generation circuit that deactivates the latch enable signal LEX in response to SPRDX. In the test mode, the precharge signal SPRDX is masked while the test latch enable signal DSRLEZ is at a high level. Therefore, the latch enable signal LEX once activated is not deactivated even if the precharge signal SPRDX is output. After the test latch enable signal DSRLEZ changes from the high level to the low level, the latch enable signal LEX changes to the high level and is deactivated due to the change of the precharge signal SPRDX to the low level.

As described above, the NOR gate connected to the input of the flip-flop FF2 operates as a sense amplifier mask circuit that masks the reception of the precharge signal SPRDX to inhibit the inactivation of the latch enable signal LEX.

Thereafter, the bit line control signal DSRBTZ changes to low level during the high level period of the refresh test signal TREFZ, thereby masking the setting function of the flip-flop FF2. That is, the flip-flop FF2 does not activate the latch enable signal LEX even when receiving the latch enable pulse signal LEPZ. After the operation of the refresh test, the refresh test signal TREFZ is changed to low level, and the mask of the set function of the flip-flop FF2 is released. The precharge control circuit 34 has a flip-flop FF3 and a logic gate for controlling the flip-flop FF3.

During the normal operation mode, the flip-flop FF3 is set in synchronization with the command pulse signal CMDPZ (access start signal), and changes the bit line short signal BRSX to a low level. The command pulse signal CMDPZ is generated in response to the read control signal RDZ, the write control signal WRZ, and the refresh start signal RSZ. When the bit line short signal BRSX changes to a low level, the switch circuit pair of the precharge circuit PRE shown in FIG. 3 described later is turned off, the equalization of the bit lines BLZ and BLX is released, and the bit lines BLZ and BLX and the precharge The connection with the voltage line VPR is released. That is, the bit lines BLZ and BLX are in a floating state. Thereafter, the flip-flop FF3 is reset in synchronization with the precharge signal SPRDX (access end signal), and changes the bit line short signal BRSX to a high level.

As described above, the flip-flop FF3 activates the bit line short signal BRSX in response to the command pulse signal CMDPZ for starting the access to the memory cell MC, and outputs the precharge signal SPRDX for ending the access to the memory cell MC. In response, it operates as a precharge signal generation circuit that deactivates the bit line short signal BRSX.

On the other hand, during the test mode, while the bit line control signal DSRBTZ is at the high level, the reset function of the flip-flop FF3 is masked by the NAND gate connected to the input of the flip-flop FF3. That is, even if the precharge signal SPRDX is output during this period, the bit line short signal BRSX does not change to high level.

As described above, the NAND gate connected to the input of the flip-flop FF3 serves as a precharge mask circuit that masks the reception of the precharge signal SPRDX in order to inhibit the deactivation of the bit line short signal BRSX. Operate.

The word decoder TOEC consists of a decoder (NAND gate) that decodes the complementary address signal RANY0-2 generated from the address signal ADD (row address), and a NOR gate that controls the operation of the NAND gate and the output voltage of the NAND gate. And During the normal operation mode, the NOR gate outputs a low level because the lead line control signal DSRWLX is at a high level. Therefore, the NAND gate is activated. Then, the predecode signal PRAAX changes to a low level according to the address signals RANY0-2. Step When the decoded signal PRAAX changes to a low level, the corresponding read line WL is selected and changes to a low level.

On the other hand, during the test mode, the word line control signal DSRWLX is at a low level. Therefore, when the predecode signal PRAAX changes to a low level, the NOR gate outputs a high level. The NAND gate is deactivated in response to the high level output from the NOR gate. The output of the NAND gate is connected to the ground line VSS by turning on the nMOS transistor. That is, the predecode signal PRAAX which has changed to the low level during the test mode does not return to the high level until the test mode ends.

As described above, the read decoder WDEC operates as a latch circuit that latches the predecode signal PRAAX to continuously output the predecode signal PRAAX during the test mode.

FIG. 3 shows details of the memory array ARY, the precharge circuit PRE, and the sense amplifier array SAA shown in FIG.

The memory array ARY includes a plurality of memory cells MC arranged in a matrix, a plurality of word lines WL (WL0, WL1,...) Arranged in the vertical direction in the figure, and a plurality of memory cells MC arranged in the horizontal direction in the figure. Bit line pairs BLZ and BLX. The memory cells MC connected to the even-numbered word lines WL0, WL2,... Are connected to the bit line BLZ. The memory cells MC connected to odd-numbered lead lines WL1, WL3,... Are connected to the bit line BLX.

The symbols Ί-Ι ”and '” displayed on the memory cell MC connected to the even-numbered word lines WL0, WL2,... Indicate the data held by the memory cell MC at the start of the test mode. The symbol “H” (first logic level) indicates that high-level data is held in the memory cell MC, and the symbol '! / (Second logic level) indicates that low-level data is stored in the memory cell MC. Is held.

The precharge circuit PRE has a plurality of switch circuits SW respectively corresponding to the bit line pairs BLZ and BLX. The switch circuit SW has two nMOS transistors connected in series between the bit lines BLZ and BLX. The connection node of the nMOS transistor is connected to the precharge line VPR. The precharge line VPR is set to, for example, an intermediate voltage (1/2 of VII) between the internal power supply voltage VII and the ground voltage VSS. The gates of the nMOS transistors both receive the bit line short signal BRSX. The sense amplifier array SAA has a plurality of sense amplifiers SA corresponding to the bit line pairs BLZ and BLX, respectively. Each sense amplifier SA is composed of a pair of CMOS inverters whose inputs and outputs are connected to each other. The inputs of the CMOS inverters are connected to bit lines BLZ and BLX, respectively. The source of the pMOS transistor of the CMOS inverter is connected to the sense amplifier activation signal line PSA. The source of the nMOS transistor of the CMOS inverter is connected to the sense amplifier activation signal line NSA. The sense amplifier SA is activated when the sense amplifier activation signals PSA and NSA are at high level and low level, respectively, and amplifies the voltage difference between the bit lines BLZ and BLX and latches the amplified logic level. That is, the sense amplifier SA increases the signal amount on the bit line BLZ (or BLX). The data amplified by the sense amplifier SA is transmitted to the data bus DB (Fig. 1) via the column switch during the read operation, and is written to the memory cell MC via the bit / line BLZ (or BLX) during the write operation. .

FIG. 4 shows the operation of the memory array ARY during the test mode of the FCRAM.

Before entering the test mode, as shown in Fig. 3, the memory connected to a predetermined number of word lines (for example, three of WL0, WL2, and WL4; the first word line) among the even-numbered word lines. High level data is written to cell MC. Also, low-level data is written into the memory cells MC connected to another predetermined number of word lines (for example, two of WL10 and WL12; the second word line) among the even-numbered word lines.

The operation in the test mode is divided into a first selection period and a second selection period. In the first selection period, the word lines connected to the memory cell MC in which the high-level data is written are sequentially selected, and a plurality of word lines WL are multiplex-selected for a predetermined period. In the second selection period, the word line WL connected to the memory cell MC in which the low level data has been written is multi-selected together with the word line WL selected in the first selection period.

In the first selection period, first, the bit line short signal BRSX changes to a low level, and the precharge operation of the bit lines BLZ and BLX stops. Next, the read line WL0 is selected, and high-level data is read from the memory cell MC to the bit line BLZ. Depending on the selection of the lead line WL0, a voltage difference occurs between the bit lines BLZ and BLX.

Thereafter, the latch enable signal LEX changes to a low level, and the sense amplifier SA is activated. It is done. The activation of the sense amplifier SA amplifies the voltage difference between the bit lines BLZ and BLX. The voltages of the bit lines BLZ and BLX change to the power supply voltage VII and the ground voltage VSS, respectively. The cell voltage STR of the memory cell MC connected to the word line WL0 temporarily decreases when the memory cell MC is connected to the bit line BLZ, but increases to the power supply voltage VII due to the amplification operation of the sense amplifier SA.

Next, while the lead line WL0 is selected, the lead line WL2 is selected, and another memory cell MC holding high-level data is connected to the bit line BLZ. At this time, the voltage of the bit line BLZ has changed to the power supply voltage VII due to the amplification operation of the sense amplifier SA. Therefore, high-level data is written back to the memory cell MC connected to the word line WL2.

Next, with the word lines WL0 and WL2 selected, the word line WL4 is selected, and another memory cell MC holding high level data is connected to the bit line BLZ.髙 level data is written back to the memory cell MC connected to the line WL2. In this manner, a predetermined number of memory cells MC connected to the bit line BLZ are connected to each other via the bit line BLZ, and high-level data is written.

Note that low-level data may be held in the memory cells MC connected to the word lines WL2 and WL4 in advance. This is because when the word lines WL2 and WL4 are selected, the sense amplifier SA operates sufficiently, and the voltages of the bit lines BLZ and BLX change to the power supply voltage VII and the ground voltage VSS.

Next, in the second selection period, while the read lines WL0, WL2, and WL4 are selected, the latch enable signal LEX changes to a high level, and the sense amplifier SA stops the amplification operation. Thereafter, the word lines WL10 and WL12 are simultaneously selected, and the plurality of memory cells MC holding low-level data are connected to the bit line BLZ. The memory cell capacity of the memory cell MC connected to the word lines WL1-WL4 and the charge stored in the bit line BLZ are redistributed to the memory cell capacity of the memory cell MC connected to the word lines WL10 and WL12. The voltage of the memory cell MC and the voltage of the bit line BLZ change. The memory cell voltage STR is determined depending on the number of memory cells MC holding high-level data and the number of memory cells MC holding low-level data, which are simultaneously connected to the bit line BLZ. In the example shown in FIG. 4, three word lines WL0, WL2, and WL4 are selected during the first selection period. Starting, by starting the selection of the two word lines WL10 and WL12 during the second selection period, the memory cell voltage STR is set to 81% of the power supply voltage VII.

Next, the bit line short signal BRSX changes to high level, the bit lines BLZ and BLX are precharged, and the test mode ends.

Thereafter, in the normal operation mode, the standby state is continued for a predetermined period. Then, the word line WL0 is selected again, and data is read from the memory cell MC. Based on the logical value of the read data, the data holding characteristic of the memory cell MC storing a predetermined amount of charge is evaluated.

FIG. 5 shows the operation of the memory array ARY during the normal operation mode. This waveform is the same as the waveform of the conventional read operation. This example shows a waveform of a read operation after a lapse of 3 Oms from the second selection period shown in FIG.

First, the bit line short signal BRSX changes to low level, and the precharge operation of the bit lines BLZ and BLX stops. Next, the word line W is selected and 0 is selected, and high-level data is read out from the memory cell MC to the bit line BLZ. The memory cell voltage STR is 81% of the power supply voltage VII at the end of the test mode, but is lower than 81% because the charge gradually leaks during the subsequent standby period.

Next, the latch enable signal LEX changes to low level, and the sense amplifier SA is activated. The activation of the sense amplifier SA amplifies the voltage difference between the bit lines BLZ and BLX. The voltages of the bit lines BLZ and BLX change to the power supply voltage VII and the ground voltage VSS, respectively. The amplified data is output from the data terminal DQ as read data. In this example, the voltage of the bit line BLZ rises to the power supply voltage VII. In other words, it can be seen that when the memory cell voltage STR is 81% of the power supply voltage VII, data can be read correctly after a pause of 3 ms.

Thereafter, the lead line WLO is deselected. The latch enable signal LEX changes to high level, and the sense amplifier SA stops the amplification operation. Next, the bit line short signal BRSX changes to high level, the bit lines BLZ and BLX are precharged, and the read operation ends.

FIG. 6 shows the operation of the control circuit during the test mode of the FCRAM. The basic timing is the same as in FIG. 4 described above. That is, in the first selection period, the word lines WL0, WL2, and WL4 are sequentially selected, and the word lines WL0, WL2, and WL4 are multiplex-selected (FIG. 6 (a)). In the second selection period, the word lines WL10 and WL12 are simultaneously selected, and the word lines WL0, WL2, WL4, WL10, and WL12 are multi-selected (FIG. 6 (b)).

One test consists of the first to fourth cycles, and the fifth cycle after a predetermined period has elapsed from the fourth cycle. The first to fourth cycles are executed during the test mode, and the fifth cycle is executed during the normal operation mode. Each cycle is a basic cycle for the memory array ARY to execute one read operation, and is executed in response to a read command RD supplied from outside the FCRAM.

First, upon receiving the test mode signal DSRZ, the test control circuit 30 shifts the FCRAM from the normal operation mode to the test mode. The test control circuit 30 changes the word line control signal DSRWLX to low level and the bit line control signal DSRBTZ to high level in response to the test mode signal DSRZ (Fig. 6 (c)). The control circuit 32 changes the test latch enable signal DSRLEZ to a high level in response to the test mode signal DSRZ (FIG. 6 (d)).

In the first cycle, the core control circuit 26 outputs a command pulse signal CMDPZ and a low timing signal RASZ in response to the read command RD (read control signal RDZ) (FIG. 6 (e)). In response to the row timing signal RASZ, the read line WL0 corresponding to the address signal ADD is selected, and data is read from the memory cell MC to the bit line BLZ (FIG. 6 (f)). The row timing signal RASZ is reset after a predetermined period. Further, the core control circuit 26 outputs a latch enable pulse signal LEPZ in response to the read command RD (FIG. 6 (g)). The precharge control circuit 34 changes the bit line short signal BRSX to a low level in response to the command pulse signal CMDPZ (FIG. 6 (h)). The sense amplifier control circuit 32 changes the latch enable signal LEX to a low level in response to the latch enable pulse signal LEPZ (FIG. 6 (i)). The activation of the latch enable signal LEX activates the sense amplifier SA to amplify the data on the bit line BLZ. The core control circuit 26 outputs the precharge signal SPRDX after a predetermined period from the output of the row timing signal RASZ (FIG. 6 (j)). The precharge control circuit 3 4 Since it receives the high-level bit line control signal DSRBTZ, it keeps outputting the low-level bit line short signal BRSX. The precharge control circuit 34 masks the precharge signal SPRDX with the high-level test latch enable signal DSRLEZ, and continues to output the low-level latch enable signal LEX (FIG. 6 (k)). Data read by selecting word line WL0 continues to be amplified by sense amplifier SA. In the second cycle, the core control circuit 26 outputs a command pulse signal CMDPZ and a row timing signal RASZ in response to the read command RD (read control signal RDZ) (FIG. 6 (1)). In response to the row timing signal RASZ, the code line WL2 corresponding to the address signal ADD is selected (FIG. 6 (m)). The word decoder WDEC does not reset the predecode signal PRAAX because it receives the low-level lead line control signal DSRWLX. Therefore, the word lines WL0 and WL2 are multi-selected. The high level data amplified on the bit lines B and Z is written to the memory cell MC connected to the read line W2.

The core control circuit 26 outputs a latch-ine pull pulse signal LEPZ in response to the read command RD (FIG. 6 (n)). However, since the latch-line pull signal LEX has already been activated, the sense amplifier SA continues to be activated.

Thereafter, the precharge signal SPRDX is output (FIG. 6 (o)). However, as described above, the bit 1, the line short signal BRSX, and the latch enable signal LEX do not change due to the masking of the high-level bit line control signal DSRBTZ. Therefore, the data read by selecting the word line WL0 continues to be amplified by the sense amplifier SA.

In the third cycle, the test control circuit 30 sequentially changes the refresh test signal TREFZ and the read pulse signal WLPZ to a high level (FIG. 6 (p)). The test latch enable signal DSRLEZ changes to low level in response to the high-level word pulse signal WLPZ (Fig. 6 (q)).

The core control circuit 26 outputs a command pulse signal CMDPZ and a mouth timing signal RASZ in response to the read command RD (read control signal RDZ) (FIG. 6 (r)). In response to the row timing signal RASZ, the word line WL4 corresponding to the address signal ADD is selected (FIG. 6 (s)). The word decoder WDEC has a low level The predecode signal PRAAX is not reset because it receives the single line control signal DSRWLX. Therefore, the word lines WL0, WL2, WL4 are multi-selected. The high level data amplified on the bit line BLZ is written to the memory cell MC connected to the word line WL4.

The core control circuit 26 outputs the latch enable pulse signal LEPZ in response to the read command RD (FIG. 6 (t)). However, since the latch enable signal LEX has already been activated, the sense amplifier SA continues to be activated.

Thereafter, a precharge signal SPRDX is output (FIG. 6 (u)). Since the test latch enable signal DSRLEZ has changed to low level, the sense amplifier control circuit 32 changes the latch enable signal LEX to high level in response to the precharge signal SPRDX. Therefore, the sense amplifier SA is inactivated, and the operation of amplifying data on the bit line BLZ is stopped. However, since the word lines WL0, WL2, and WL4 continue to be selected, the memory cells MC connected to the word lines WL0, WL2, and W4 continue to be connected to the bit line BLZ.

In the fourth cycle, the test control circuit 30 changes the read pulse signal WLPZ to a high level (FIG. 6 (V)). The bit line control signal DSRBTZ changes to low level in response to the high level word pulse signal WLPZ (Fig. 6 (w)). At this time, the masking operation for prohibiting the precharge control circuit 34 from changing the bit line short signal BRSX to high level is released.

The core control circuit 26 outputs a command pulse signal CMDPZ and a row timing signal RASZ in response to the read command RD (read control signal RDZ) (FIG. 6 (X)). In response to the row timing signal RASZ, the input lines WL10 and WL12 corresponding to the address signal ADD are multiplex-selected (FIG. 6 (y)).

The read decoder WDEC does not reset the predecode signal PRAAX because it receives the low level read line control signal DSRWLX. Therefore, the word lines WL0, WL2, WL4, WL10, WL12 are multi-selected. Therefore, as shown in FIG. 4, the charge stored in the memory cell capacitance connected to the word lines WL0, WL2, WL4 and the charge stored on the bit line BLZ are It is redistributed to the memory cell capacity connected to lines WL10 and WL12. That is, a predetermined amount of charge is stored in the memory cell MC. It is.

Since the bit line control signal DSRBTZ is deactivated, the test control circuit 30 deactivates the read line control signal DSRWLX in response to the deactivation of the mouth timing signal RASZ (see FIG. 6 ( zl))). The word decoder WDEC stops the latch operation in response to the deactivation of the word line control signal DSRWLX. Therefore, the word lines WL0 to WL12 are deselected (FIG. 6 (z2)).

Further, since the bit line control signal DSRBTZ is inactivated, the precharge control circuit 34 changes the bit line short signal BRSX to a high level in response to the precharge signal SPRDX (see FIG. 6 (z 3 )). Therefore, the bit lines BLZ and BLX are precharged.

Thereafter, a command to exit the test mode is input via the command terminal CMD, and the FCRAM transitions from the test mode to the normal operation mode.

In the normal operation mode, the standby state is continued for a predetermined period. Then, similarly to FIG. 5, the word line WL0 is selected again, and data is read from the memory cell MC. Based on the logical value of the read data, the data retention characteristic of the memory cell C in which a predetermined amount of charge is stored is evaluated.

FIG. 7 shows the relative value of the accumulated charge amount (calculated value) of the memory cell corresponding to the number of selected word lines.

Let X be the number of lead lines WL selected in the first selection period and Y be the number of lead lines WL to be newly multiplex-selected in the second selection period. The amount of charge stored in the X memory cells MC and the bit lines BLZ (or BLX) during the first selection period, and then the X + Y memory cells MC and the bit lines BLZ (or BLX) during the second selection period ) Are equal. Therefore, equation (1) holds.

Viic-(Cbl + X-Cs) = Vst-(Cbl + (X + Y)-Cs) (1)

Here, Cs is the capacitance of the memory cell MC, Cbl is the capacitance of the bit line BLZ (or BLX) including the parasitic capacitance of the sense amplifier SA, Vst is the voltage of the memory cell MC (cell storage voltage), and Viic is the sense amplifier. Power supply voltage supplied to SA.

Each value in the figure is obtained from Expression (2) obtained by modifying Expression (1).

Vst / Vi ic = (Cbl + X. Cs) / (Cbl + (X + Y) ■ Cs) (2) In FIG. 7, the capacitance Cs of the memory cell MC is 30 fF, and the capacitance Cbl of the bit line BLZ (or BLX) is 160 fF.

As shown in FIG. 7, by changing the number X of word lines WL to be multi-selected in the first selection period and the number Y of word lines WL to be newly multi-selected in the second selection period, they are accumulated in the memory cell MC. The charge amount is set to various values. By setting the number of word lines WL to be multi-selected in the first and second selection periods to 1 to 8 respectively, the amount of electric charge accumulated in the memory cell MC is reduced to 44 ° / ₀ to the internal power supply voltage VII. Can be set to 93%. The capacities Cs and Cbl vary due to fluctuations in manufacturing conditions and the like. However, as is clear from the above equations (1) and (2), the influence of variations in the capacitances Cs and Cbl can be reduced by increasing the number X and Y of the word lines WL.

As described above, in the present embodiment, the amount of charge stored in the memory cell MC is determined according to the number of words WL selected in the first selection period and the number of word lines WL selected in the second selection period. Can be set freely. Therefore, by repeating the evaluation while changing the number of selected word lines WL, the data retention characteristics of the memory cell MC can be accurately evaluated in the semiconductor memory having the dynamic memory cell MC.

By distributing the amount of charge stored in the bit line BLZ and the plurality of memory cells MC, a desired amount of charge can be stored in the memory cell MC, so that a special voltage generation circuit and a capacitor for charge storage are not required. Therefore, it is possible to prevent the chip size of the FCRAM from increasing.

There is no need to connect a special voltage generation circuit for setting the bit line BLZ to a predetermined voltage to the bit line BLZ. Therefore, the load on the bit line BLZ can be made the same as before. As a result, for example, it is possible to prevent the access time from becoming longer due to an increase in load.

Unlike the conventional method in which the voltage of the bit line is adjusted by controlling the voltage generation circuit such as the sense amplifier power supply, other voltage generation circuits in the FCRAM (such as a precharge voltage generation circuit) transfer electric charges to the memory cell MC. Unaffected by accumulation. Therefore, there is no need to wait until the other voltage generation circuits have stabilized after storing the desired charge in the memory cell MC. As a result, the refresh characteristics of the dynamic memory cell MC can be evaluated in a short time. A mask circuit (NOR gate) for inhibiting the deactivation of the latch enable signal LEX is formed in the sense amplifier control circuit 32. Therefore, the sense amplifier SA can easily continue to operate during the first and second cycles of the first selection period.

Mask circuit (NAND gate) that inhibits reset of the bit line short signal BRSX is formed in the precharge control circuit 34. Therefore, the precharge operation of the bit line BLZ can be easily stopped during the first and second selection periods. Therefore, the bit line BLZ can be reliably floated, and the desired amount of charge can be accurately stored in the memory cell.

A latch for continuously outputting the predecode signal PRAAX during the first and second selection periods is formed in the word decoder WDEC. For this reason, a plurality of read lines WL can be selected multiple times only by sequentially supplying the address signal ADD in the test mode as in the normal access.

During the first selection period of the test mode, one of the gate lines WL connected to the memory cell MC to which high-level data is to be written in advance is selected first, and another word line WL is activated after the activation of the sense amplifier SA. Selected. Therefore, the number of memory cells to which the first logic level is previously written can be minimized, and the write operation time can be shortened. Therefore, the period for accumulating charges in the memory cell can be shortened, and the evaluation time of the data retention characteristics of the memory cell can be shortened.

FIG. 8 shows the operation of the memory array in the test mode in the second embodiment of the semiconductor memory of the present invention. The same elements as those described in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

In this embodiment, during the first selection period, the word lines WL0, WL2, WL4 are simultaneously selected. High-level data is written in the memory cells MC connected to the word lines WL0, WL2, WL4 in advance. Other waveforms are the same as in the first embodiment (FIG. 4). In this embodiment, the core control circuit 26 of the first embodiment is modified to obtain the waveform shown in FIG. Other configurations are the same as those of the first embodiment.

In this embodiment, the same effects as in the first embodiment can be obtained. In addition, the word line WL0, WL2, WL4 selects simultaneously, the first selection The period can be shortened. As a result, the evaluation time of the data holding characteristic of the memory cell MC can be shortened as compared with the first embodiment.

In the above-described embodiment, the example in which the present invention is applied to the FCRAM has been described. The present invention is not limited to such an embodiment. For example, the present invention may be applied to a DRAM.

As described above, the present invention has been described in detail. However, the above-described embodiment and its modifications are merely examples of the present invention, and the present invention is not limited thereto. Obviously, modifications can be made without departing from the present invention. Industrial potential

According to the charge storage method of a semiconductor memory and a dynamic memory cell of the present invention, a desired amount of charge can be stored in a memory cell according to the number of selected first word lines and the number of second word lines selected thereafter. Since a desired amount of charge can be stored in the memory cell without preparing a special voltage generation circuit and a capacitor for charge storage, an increase in the chip size of the semiconductor memory can be prevented.

Since there is no need to connect a special circuit for supplying charges to the bit line, the load on the bit line can be the same as before. As a result, for example, it is possible to prevent the access time from becoming longer due to an increase in the load.

By repeating the evaluation while changing the number of the first lead lines to be selected and then the number of the second lead lines to be selected, the data retention characteristics of the memory cells in the semiconductor memory having the dynamic memory cells are improved. Can be evaluated accurately.

In the semiconductor memory of the present invention, the sense amplifier can be continuously operated during the predetermined period of the first selection period by the sense amplifier mask circuit.

In the semiconductor memory of the present invention, since a once-generated decode signal can be held by a simple circuit, word lines can be multiple-selected simply by sequentially supplying addresses as in normal access.

In the semiconductor memory of the present invention, the precharge mask circuit allows the precharge operation of the bit line to be continuously stopped during the first selection period.

In the semiconductor memory of the present invention, one of the first word lines is selected first, By selecting the rest of the first code line after the activation of the loop, the number of memory cells to which the first logic level is previously written can be minimized. Therefore, the write operation time can be shortened. As a result, the period for accumulating charges in the memory cell can be shortened, and the evaluation time of the data retention characteristics of the memory cell can be shortened.

In the semiconductor memory of the present invention, by simultaneously selecting the first word lines, the first selection period can be minimized, and the period for accumulating charges in the memory cells can be shortened. As a result, the time for evaluating the charge retention characteristics of the memory cell can be reduced.

Claims

The scope of the claims

(1) a memory array having a plurality of dynamic memory cells, a plurality of word lines respectively connected to the memory cells, and a bit line connected to the memory cells;

A sense amplifier for amplifying a signal amount on the bit line;

In a first selection period, a predetermined number of first word lines are multiplex-selected to connect a part of the memory cells to the bit lines, and in a second selection period after the first selection period, the first word A line control circuit for multiplexing a predetermined number of second lines in order to connect another part of the memory cells to the bit lines while the lines are multi-selected; and A semiconductor memory, comprising: a sense amplifier control circuit that activates an amplifier and deactivates the sense amplifier during the second selection period.

(2) In the semiconductor memory of Claim 1,

The sense amplifier control circuit includes:

Activate a sense amplifier activation signal in response to an access start signal for starting access to the memory cell, and deactivate the sense amplifier activation signal in response to an access end signal for ending access to the memory cell. A sense pump signal generation circuit;

A sense amplifier mask circuit for masking reception of the access end signal in order to inhibit inactivation of the sense amplifier activation signal in an access cycle other than a last access cycle in the first selection period,

The semiconductor memory, wherein the sense amplifier operates during activation of the sense amplifier activation signal.

(3) In the semiconductor memory of Claim 1,

The word line control circuit includes:

A plurality of decode circuits for decoding an address signal to generate a decode signal for selecting one of the word lines, respectively;

Each of the decoding circuits outputs the decode signal during the first and second selection periods. A semiconductor memory comprising: a latch circuit for latching the decode signal so as to keep outputting.

(4) In the semiconductor memory of Claim 1,

A precharge circuit for precharging the bit line to a predetermined voltage;

A semiconductor memory, comprising: a precharge control circuit for stopping the operation of the precharge circuit in the first and second selection periods.

(5) In the semiconductor memory according to claim 4,

The precharge control circuit includes:

A precharge control signal is activated in response to an access start signal for starting access to the memory cell, and a precharge control signal is deactivated in response to an access end signal for ending access to the memory cell. A charge signal generation circuit;

A precharge mask circuit for masking reception of the access end signal in order to prohibit deactivation of the precharge control signal in the first selection period; and wherein the precharge circuit comprises: A semiconductor memory which operates during activation of a signal.

(6) In the semiconductor memory of Claim 1,

The semiconductor memory according to claim 1, wherein the word line control circuit selects one of the first word lines first, and selects the rest of the first word line after activation of the sense amplifier.

(7) In the semiconductor memory according to claim 6,

Of the memory cells accessed in the first selection period, at least a memory cell connected to one of the first gate lines selected first has a first logic level written therein in advance, and A semiconductor memory, wherein a memory cell accessed during a selection period is pre-programmed with a second logic level.

(8) In the semiconductor memory of claim 1,

2. The semiconductor memory according to claim 1, wherein said word line control circuit simultaneously selects said first word line.

(9) In the semiconductor memory according to claim 8, A semiconductor cell, wherein a memory cell accessed in the first selection period is written with a first logic level in advance, and a memory cell accessed in the second selection period is written with a second logic level in advance. memory.

(10) In the semiconductor memory of Claim 1,

The semiconductor memory according to claim 1, wherein the first and second selection periods are set during a test mode for evaluating data retention characteristics of the memory cells.

(11) In a first selection period, a predetermined number of first lead lines respectively connected to a plurality of dynamic memory cells are multi-selected,

Activating a sense amplifier to amplify a signal amount on a bit line connected to the memory cell;

Deactivating the sense amplifier after amplification of the signal amount,

While the first hood line is selected, a predetermined number of second lead lines respectively connected to the plurality of dynamic memory cells are multi-selected,

Redistributing the accumulated charge of the memory cell connected to the first word line and the accumulated charge of the bit line to the memory cell connected to the second word line. Accumulation method.

(1 2) The charge storage method for a dynamic memory cell according to claim 1, wherein after the charge is redistributed, the first and second lead lines are deselected,

A method for storing charges in a dynamic memory cell, comprising reading data from at least one of the memory cells after a predetermined time.

(13) The method according to claim 11, wherein one of the first lead lines is selected first, and the remaining first lead line is activated after the activation of the sense amplifier. A method for storing electric charge in a dynamic memory cell, characterized by selecting:

(14) The charge storage method for a dynamic memory cell according to claim 13, wherein the memory cell is connected to at least one of the first word lines selected first among the memory cells accessed in the first selection period. A memory cell to which a first logic level is written in advance, and a memory cell accessed in the second selection period is written in advance to a second logic level. (15) The charge storage method for a dynamic memory cell according to claim 11, wherein the first line is simultaneously selected.

(16) In the charge storage method for a dynamic memory cell according to claim 15, in the memory cell accessed in the first selection period, a first logic level is written in advance and the memory cell is accessed in the second selection period. A method of storing charge in a dynamic memory cell, wherein a second logic level is previously written in the memory cell.

(17) The charge storage method for a dynamic memory cell according to claim 11, wherein the first and second selection periods are set during a test mode for evaluating data retention characteristics of the memory cell. Characteristic charge storage method for dynamic memory cells.