JP2009245497A - Semiconductor memory device and its defect detection method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device which can efficiently detect a defect due to shortage of an accumulated charge amount of a memory cell, and to provide its defect detection method. <P>SOLUTION: While a word line, to which a memory cell of a test target is connected, is driven in a defect detection test, driving of a word line to which a memory cell for applying active noise is connected is made possible, wherein data inverse to data written in the memory cell of the test target is written into the memory cell for applying active noise. By this means, noise is directly applied to a data line from which data from the memory cell of the test target is read. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device with improved defect detection accuracy and a defect detection method thereof.

  Conventionally, a passive noise application method is generally used for a defect detection test of a highly integrated semiconductor memory represented by a dynamic ram (DRAM) or a static ram (SRAM). Hereinafter, a passive noise application method will be described.

  In a defect detection test of a semiconductor memory device, data is written to and read from each memory cell to check whether data can be read correctly. At this time, the data read from the memory cell to be inspected (the potential of the data line to which the memory cell to be inspected is connected, hereinafter referred to as the data potential) is amplified by the sense amplifier, and the amplified potential represents the correct data. A pass / fail judgment is made depending on whether or not there is. Here, if the data potential is a value near the boundary of whether or not the data potential is correctly amplified, there is a possibility that it is determined as a non-defective product or a defective product. Therefore, a passive noise application method is used to reliably determine such a memory cell as a defective product and improve inspection accuracy.

  In the passive noise application method, a write / read operation is also performed on a data line adjacent to a data line (hereinafter referred to as a target data line) to which a memory cell to be inspected is connected. Since there is a stray capacitance inherent in the wiring arrangement between the adjacent data lines, the potential of the data line of interest changes according to the change in the potential of the adjacent data line (because of coupling noise). In this way, inducing the potential change of the data line of interest by changing the potential of the adjacent data line is called passive noise application. In order to more effectively apply the passive noise, the on-timing of the sense amplifier connected to the data line of interest and the on-timing of the sense amplifier connected to the adjacent data line are also shifted. .

  FIG. 9 shows a schematic configuration diagram of a semiconductor memory device capable of performing a defect detection test by a passive noise application method.

  The apparatus of FIG. 9 has a plurality of memory banks 91 in which a large number of memory cells are arranged in a matrix, and a sense amplifier array 92 arranged between these memory banks 91. Each sense amplifier of the sense amplifier array 92 is connected to each data line provided in a memory bank located on both sides.

  In the above configuration, a stray capacitance is formed between each data line in the memory bank and the adjacent data line. When a defect detection test is performed on the memory cell connected to the target data line, writing and reading are also performed on the adjacent data lines. At this time, the on-timing of the sense amplifiers on the adjacent data lines can be shifted by shifting the on-timing of the sense amplifier rows 92 located on both sides of each memory bank.

  FIGS. 10A and 10B show potential changes in the data line of interest and the adjacent data lines at the time of the defect detection test. FIG. 10A shows a case where data “High” is written and read, and FIG. 10B shows a case where data “Low” is written and read.

  As shown in FIGS. 10A and 10B, before starting writing / reading of the data line of interest, writing / reading of the adjacent data lines is started. Next, writing / reading of the target data line is started, and the potential of the target data line is increased or decreased. At this time, the potential change of the data line of interest is suppressed by the influence of the stray capacitance formed between the adjacent data lines. Next, when the sense amplifier connected to both adjacent data lines is turned on and the potential of both adjacent data lines is amplified, the potential of the data line of interest is opposite to the direction in which it should be amplified due to the effect of stray capacitance. Change (decrease or increase). Thereafter, the sense amplifier connected to the target data line is turned on, and the potential of the target data line is amplified.

  As described above, in the defect detection test by the conventional passive noise application method, a defective product that may be judged as a non-defective product can be obtained by suppressing the potential change of the data line of interest and changing it in the direction opposite to the amplification direction. It can detect reliably and can improve a defect detection rate.

  As another conventional defect detection method, a technique for simultaneously selecting a plurality of word lines and shortening a test time is known (see, for example, Patent Document 1).

JP 2002-304899 A

  The conventional defect detection test using the passive noise application method requires not only the sense amplifier connected to the data line of interest but also the sense amplifier connected to the adjacent data lines. For this reason, the conventional defect detection method has problems that the control is complicated, the defect detection takes time, and the efficiency is poor.

  In addition, the method described in Patent Document 1 has a problem in that no consideration is given to a defect due to a shortage of accumulated charge in a memory cell that can be detected by a passive noise application method.

  In view of the above, an object of the present invention is to provide a semiconductor memory device and a defect detection method thereof that can efficiently detect a defect due to a shortage of accumulated charge in a memory cell.

  The present invention is characterized in that the semiconductor memory device includes active noise applying means for directly applying noise to a data line to which a memory cell to be inspected is connected in a defect detection test.

  Specifically, the active noise applying means is connected to the data line to which the test target memory cell is connected during the period of driving the first word line connected to the test target memory cell. Drive means for driving a second word line connected to another memory cell is provided.

  According to another aspect of the present invention, in the defect detection method for a semiconductor memory device, a data read operation is performed from a memory cell to be tested, and noise is directly applied to a data line to which the memory cell to be tested is connected. .

  Specifically, in the semiconductor memory device defect detection method, data opposite to the data written in the test target memory is applied to another memory cell connected to the data line to which the test target memory cell is connected. The data is written in advance, and when performing the data read operation from the memory cell to be inspected, the noise is applied to the data line by performing the data read operation from the other memory cells.

  According to the present invention, since noise is directly applied to the data line to which the memory cell to be inspected is connected, the defect detection efficiency can be improved, the test time can be shortened, and the cost can be reduced.

  Hereinafter, a semiconductor memory device and a defect detection method thereof according to an embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows a schematic configuration diagram of a semiconductor memory device according to an embodiment of the present invention.

  The illustrated semiconductor memory device includes a memory cell array 11, a sense amplifier group 12, a column decoder 13, a row decoder 14, a clock generator 15, a command decoder 16, a mode register 17, a control circuit 18, a column address buffer and burst counter 19, a row An address buffer / refresh counter 20, a data control circuit 21, a latch circuit 22, a DLL 23, and an input / output buffer 24 are provided.

  FIG. 2 shows a peripheral circuit configuration diagram centered on the memory cell array 11. Here, an example in which the memory cell array 11 has four memory cells 111 to 114 is shown.

  Memory cell 111 is connected to data line memory cell level transmission line 201 and X address 0 sub-word line 202. Memory cell 112 is connected to data line memory cell level transmission line 201 and X address 1 sub-word line 203. Memory cell 113 is connected to data line memory cell level transmission line 204 and X address 0 sub-word line 202. Memory cell 114 is connected to data line memory cell level transmission line 204 and X address 1 sub-word line 203.

  Sense amplifiers 121 and 122 are connected to the data memory cell level transmission lines 201 and 204, respectively. These sense amplifiers 121 and 122 are further connected to data line memory cell level opposite transmission lines 205 and 206, respectively, and a data line high level amplification signal level input line 207 and a data line low level amplification signal level input. Line 208 is connected in common.

  The data line memory cell level transmission lines 201 and 204 and the data line memory cell level opposite transmission lines 205 and 206 are connected to the data line precharge level input line 211 via the switches 209 and 210. The switches 209 and 210 are connected to the data line precharge signal line 212.

  Data line memory cell level transmission lines 201 and 204 are further connected to one 217 of the main I / O sense amplifier amplification level transmission line pair via switches 213 and 214. The data line memory cell level opposite transmission lines 205 and 206 are connected to the other 218 of the main I / O sense amplifier amplification level transmission line pair via switches 215 and 216. The switches 213 and 215 are connected to the Y address 0 column selection switch signal line 219, and the switches 214 and 216 are connected to the Y address 1 column selection switch signal line 220, respectively.

  Data reading from the memory cells 111 to 114 is performed as follows.

  First, the switches 209 and 210 are turned on by the data line precharge signal, and the potentials of the data line memory cell level transmission lines 201 and 204 and the data line memory cell level opposite transmission lines 205 and 206 are set to the data line precharge level. . After that, when the switches 209 and 210 are turned off and any one of the sub word lines 202 or 203 is driven, the charge ("" stored in the memory cells 111 and 113 or 112 and 114 connected to the sub word line 202 or 203 is displayed. In response to “High” or “Low”), the potentials of the data line memory cell level transmission lines 201 and 204 change from the precharge level. The sense amplifiers 121 and 122 amplify this potential change to the level amplification signal level. By driving the column selection switch signal line 217 or 218 for Y address 0 or Y address 1 and turning on the switches 213 and 215 or 214 and 216, the amplified level (read data) is main. Output to I / O line sense amplifier amplification level transmission lines 217 and 218.

  Next, the row decoder 14 for driving the sub word line will be described with reference to FIG. Here, it is assumed that the sub-word line for X address 1 is for data main signal, and the sub-word line for X address 0 is for data disturb (for applying active noise).

  The row decoder 14 of FIG. 3 includes a driver (inverter) 31 and a switch 32 connected to the X-address 1 sub-word line 203, and a driver (inverter) 33 and a switch 34 connected to the X-address 0 sub-word line 200. Yes. Also, the NAND circuit 35 connected to the sub-word line selection signal line 301 for X address 1 for driving the switch 32 and the word line multiple selection control signal input line 302, and the multiplexing for delaying the output of the NAND circuit 35. A selected word line selection time delay circuit 36 is provided. Furthermore, it has a NOT circuit that logically inverts the signal as necessary.

  The drivers 31 and 33 include PMOSs 31a and 33a and NMOSs 31b and 33b, and are connected between the word line voltage supply line 303 and the ground. The drivers 31 and 33 turn on the PMOSs 31a and 33a or the NMOSs 31b and 33b according to the potentials of the signal input lines 304 and 305 from the main word line, and use the potential of the word line voltage supply line 303 or the ground potential for sub word line selection. The signal lines 301 and 302 are supplied. Thus, the drivers 31 and 33 function as level supply means.

  In normal operation, the PMOS 31a and 33a are not turned on simultaneously. However, in the present embodiment, the PMOSs 31a and 33a are simultaneously turned on in the defect detection mode. A known technique for simultaneously driving a plurality of word lines can be used to generate an input signal from the main word line for simultaneously turning on the PMOSs 31a and 33a.

  In the present embodiment, the potentials of the sub word lines 203 and 200 depend on the states of the switches 32 and 34 as well as the states of the drivers 31 and 33.

  When the X-address 1 sub-word line selection signal line 301 is “Low”, the switch 32 is on, and the potential of the sub-word line 203 becomes the ground potential (GND level) regardless of the operation of the driver 31. When the X-address 1 sub-word line selection signal line 301 is “High”, the switch 32 is off, and the potential of the sub-word line 203 is set to the word line voltage supply level or the GND level according to the operation of the driver 31. It becomes. In this way, the switch 32 serves as a first level maintaining means for maintaining the voltage level supplied from the driver 31 or forcibly reducing it to the GND level.

  On the other hand, the switch 34 depends on the potentials of the sub-word line selection signal line 301 for X address 1 and the word line multiple selection control signal input line 302. That is, the switch 34 is turned off when both of these signals are “High”, and turned on at other times. However, the ON / OFF change of the switch 34 is affected by the multiple selection word line selection time delay circuit 36, and from the potential change of the sub-word line selection signal line 301 for X address 1 and the word line multiple selection control signal input line 302. Be late. By changing the number of delay stages of the delay circuit 36, the delay time can be arbitrarily changed. In this way, the switch 34 functions as a second level maintaining means for maintaining the voltage level supplied from the driver 33 or forcibly reducing it to the GND level.

  With the above configuration, the row decoder 14 functions as a driving unit that can drive the X address 0 subword 200 within a period during which the X address 1 subword 203 is driven. The row decoder 14 functions as an active noise applying unit in combination with a known technique for simultaneously selecting a plurality of word lines.

  The operation of the circuit of FIG. 3 will be described below with reference to FIGS.

  First, the operation during normal operation will be described with reference to FIGS.

  During normal operation, the signal E of the word line multiple selection control signal input line 302 is fixed to “Low”. As a result, the switch 34 is turned on, and the X word 0 sub-word line 200 is maintained at the GND level regardless of the state of the driver 33.

  In this state, when the signal A of the signal input lines 304 and 305 from the main word line changes to “High”, the PMOSs 31 a and 33 a of the drivers 31 and 33 are turned on, and the word line voltage supply 303 is supplied to the sub word lines 203 and 200. A voltage is supplied. At this time, by setting the signal C of the X-address 1 sub-word line selection signal line to “High”, the X-address 1 sub-word line 203 is driven. The X address 0 sub-word line 200 is maintained at the GND level as described above.

  When the potential G of the X address 1 sub-word line 203 reaches a predetermined potential, the memory cells connected to the X address 1 sub-word line 203 can be written and read.

  Next, the operation in the defect detection mode will be described with reference to FIGS. In the defect detection mode, the signal E of the word line multiple selection control signal input line 302 is fixed to “High”.

  In this state, when the signal A of the signal input lines 304 and 305 from the main word line changes to “High”, the PMOSs 31 a and 33 a of the drivers 31 and 33 are turned on, and the word line voltage supply 303 is supplied to the sub word lines 203 and 200. A voltage is supplied. At this time, by setting the signal C of the X-address 1 sub-word line selection signal line to “High”, the X-address 1 sub-word line 203 is driven.

  Since the signal C of the sub-word line selection signal line for X address 1 changes to “High”, the output of the NAND circuit 302 also changes to “High”. This change is delayed by the multiple selection word selection time delay circuit 36 and appears as a change in the signal F. Thus, after the X-address 1 sub-word line 203 is driven, the X-address 0 sub-word line 200 is also driven after a predetermined time has elapsed.

  Thus, the data read from the memory cell connected to the X address 0 sub-word line 200 can be directly applied as noise to the data read from the memory cell connected to the X address 1 sub-word line 203. it can.

  Thus, in this embodiment, it is not necessary to turn on a plurality of sense amplifiers in order to inspect one memory cell to be inspected. Therefore, control is easy and the inspection time can be shortened.

  In the above embodiment, a case where a 4-bit memory is taken as an example and one of the two sub word lines is used for the data main signal and the other is used for the data disturb is described. However, in an actual memory, a large number of word lines are used. For example, one of the plurality of defect relief word lines can be used for data disturb.

  A first embodiment of the present invention will be described with reference to FIGS.

  In FIG. 6A, all of the memory cells 61 to 64 have the same configuration. That is, no special memory cell is prepared as an active noise application cell. As the active noise application cell, for example, a defect relief cell can be used.

  In this configuration, the capacitor of the defect detection inspection target cell and the capacitor of the active noise application cell have substantially the same capacitance. In the active noise application cell, data opposite to the data written in the memory cell to be inspected (logically inverted) is written.

  The defect detection test is performed as follows. Here, the memory cell 62 is an inspection target memory cell, and the memory cell 64 is an active noise application cell.

  First, the word line (selected word line) 65 to which the memory cell 62 to be inspected is connected is activated (driven). Next, simultaneously with turning on the sense amplifier 66, the word line (test mode use word line) connected to the active noise application cell 64 is activated (multiple sense). The time change of the potential of the data line 68 at this time is shown in the lower left diagram and the right diagram in FIG.

  The lower left diagram and the right diagram in FIG. 6B are those when “High” is written as data in the memory cell 62 to be inspected. In this case, “Low” is written in the active noise application cell 64.

  The upper left diagram in FIG. 6B shows the potential change of the data line 68 in the normal read operation. As is apparent from the comparison between this figure and the lower left and right figures of FIG. 6B, the potential of the data line 68 raised by driving the selected word line 65 to which the memory cell 62 to be inspected is connected is the sense amplifier. The voltage decreases when 66 is turned on, that is, when the test mode use word line 67 is driven. As shown in the lower left diagram of FIG. 6B, if the sense amplifier 66 can be correctly amplified by the influence of this potential drop, it is determined that the memory cell 62 to be inspected is normal. On the other hand, as shown in the right diagram of FIG. 6B, if the sense amplifier 66 cannot be correctly amplified by the influence of the potential drop, it is determined that the memory cell 62 to be tested is normal. Is done.

  In this way, in this embodiment, it is possible to detect a defect of the memory cell itself such as an insufficient capacity of the capacitor.

  It should be noted that the same defect detection test can be performed on the active noise application cell 64 by making another memory cell play a role as an active noise application cell.

  In the above description, the multiple sense is performed at the same time as the sense amplifier 66 is turned on. However, it may be performed at a timing adjusted before and after starting the sense amplifier, if necessary.

  Next, Embodiment 2 of the present invention will be described with reference to FIGS. 7 (a), (b) and (c).

  In this embodiment, a dedicated cell 71 is prepared as an active noise application cell. The dedicated cell 71 has a larger capacitance than that of a normal memory cell. Alternatively, a resistor may be used instead of the capacitor. Further, the drive timing of the test mode use word line 72 to which the dedicated cell 71 is connected is set later than the on timing of the sense amplifier 73.

  The time change of the potential of the data line 74 according to the present embodiment is shown in the lower left diagram and the right diagram in FIG. The upper left diagram in FIG. 7B shows the potential change of the data line 74 in the normal read operation.

  In the present embodiment, noise is applied to the data line 74 after the differential amplification of the potential of the data line 74 by the sense amplifier 73 is started. If the sense amplifier 73 has a predetermined amplification capability, sufficient amplification is performed before the noise is applied, so that it can be correctly amplified even after the noise is applied. On the other hand, if the sense amplifier 73 does not have a predetermined amplification capability, noise cannot be applied and correct amplification cannot be performed.

  Thus, in this embodiment, it is possible to detect a failure of the transistor included in the sense amplifier 73 shown in FIG.

  Next, Embodiment 3 of the present invention will be described with reference to FIGS.

  In this embodiment, a dedicated cell 81 is prepared as an active noise application cell. The dedicated cell 81 has a capacitor having a smaller capacitance than that of a normal memory cell. Alternatively, a resistor (having a larger resistance value than in the second embodiment) may be used instead of the capacitor.

  The time change of the potential of the data line 82 according to the present embodiment is shown in the lower left diagram and the right diagram in FIG. The upper left diagram in FIG. 8B shows the potential change of the data line 82 in the normal read operation.

  In this embodiment, by reducing the capacitance of the capacitor of the active noise application cell, the noise application timing can be set irrespective of the on-timing of the sense amplifier. FIG. 8B shows the potential change of the data line 82 when the test mode use word line 85 is driven simultaneously with the driving of the selected word line 84 to which the memory cell 83 to be inspected is connected.

  Thus, in this embodiment, it is possible to stably detect a defect that depends on the activation timing of the sense amplifier.

1 is a block diagram showing a schematic configuration of a semiconductor memory device according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing a peripheral circuit configuration of a memory cell array in the semiconductor memory device of FIG. 1. FIG. 2 is a circuit diagram showing a configuration of a row decoder used in the semiconductor memory device of FIG. 1. FIG. 4 is a waveform diagram for explaining a normal read operation of the circuit of FIG. 3. FIG. 4 is a waveform diagram for explaining an operation when a defect detection test of the circuit of FIG. 3 is performed. BRIEF DESCRIPTION OF THE DRAWINGS It is a figure for demonstrating Example 1 of this invention, Comprising: (a) is a circuit diagram which shows schematic structure, (b) is a wave form diagram which shows the electrical potential change of the data line contained in the circuit of (a). . 5A and 5B are diagrams for explaining a second embodiment of the present invention, in which FIG. 5A is a circuit diagram showing a schematic configuration, FIG. 5B is a waveform diagram showing potential changes of data lines included in the circuit of FIG. c) is a circuit diagram showing an internal configuration of the sense amplifier. 4A and 4B are diagrams for explaining a third embodiment of the present invention, where FIG. 5A is a circuit diagram showing a schematic configuration, and FIG. 5B is a waveform diagram showing potential changes of data lines included in the circuit of FIG. . It is a schematic block diagram of the conventional semiconductor memory device. It is a wave form diagram which shows the electric potential change of the data line in the defect detection test by the conventional passive noise application method.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Memory cell array 12 Sense amplifier group 13 Column decoder 14 Row decoder 15 Clock generator 16 Command decoder 17 Mode register 18 Control circuit 19 Column address buffer and burst counter 20 Row address buffer and refresh counter 21 Data control circuit 22 Latch circuit 23 DLL
24 I / O buffer 31, 33 Driver 31a, 33a PMOS
31b, 33b NMOS
32, 34 Switch 35 NAND circuit 36 Multiple selection word line selection time delay circuit 36
61 to 64 Memory cells 65 and 84 Selected word line 66 and 73 Sense amplifier 67 and 85 Test mode use word line 71 and 81 Active noise application cell 72 Test mode use word line 74 and 82 Data line 83 Test target cells 111 to 114 Memory cell 121, 122 Sense amplifier 201 Data line memory cell level transmission line 202 Sub word line for X address 0 203 Sub word line for X address 1 204 Data line memory cell level transmission line 205, 206 Data line memory cell level opposite transmission line 207 Data line high level amplification signal level input line 208 Data line low level amplification signal level input line 209, 210, 213, 214 Switch 211 Data line precharge level input line 212 Data line precharge signal line 217, 2 18 Main I / O Sense Amplifier Amplification Level Transmission Line Pair 219 Y Address 0 Column Selection Switch Signal Line 220 Y Address 1 Column Selection Switch Signal Line 301 X Address 1 Sub Word Line Selection Signal Signal Line 302 Word Line Multiple Selection Control Signal input line 303 Word line voltage supply line 304, 305 Signal input line from main word line

Claims (13)

  A semiconductor memory device comprising active noise applying means for directly applying noise to a data line to which a memory cell to be inspected is connected in a defect detection test.   The active noise applying means is connected to another memory cell connected to the data line to which the test target memory cell is connected during a period in which the first word line connected to the test target memory cell is driven. 2. The semiconductor memory device according to claim 1, further comprising driving means for driving the connected second word line. The drive means
Level supply means for supplying a high level or a low level to each of the first word line and the second word line in response to a common input signal;
First level maintaining means for maintaining the level of the first word line or forcing it to a low level in response to a word line selection signal for selecting the memory cell to be inspected;
Second level maintaining means for maintaining or forcibly setting the level of the second word line to a low level according to the word line selection signal and the multiple selection signal;
3. The semiconductor memory device according to claim 2, further comprising: The other memory cell has a capacitance equal to or greater than a capacitance of the memory cell to be inspected;
The second level maintaining means delays the response of the second level maintaining means to the change of the word line selection signal from the response of the first level maintaining means to the change of the word line selection signal. 4. The semiconductor memory device according to claim 3, further comprising:   4. The semiconductor memory device according to claim 2, wherein a capacitance of the other memory cell is smaller than a capacitance of the memory cell to be inspected.   6. The semiconductor memory device according to claim 3, wherein said level supply means includes a CMOS inverter.   The first level maintaining means includes a first switch connected between the first word line and ground, and the second level maintaining means includes the second word line and the installation. 6. The semiconductor memory device according to claim 3, further comprising a second switch connected therebetween.   8. The semiconductor memory device according to claim 7, wherein the second level maintaining means includes a NAND circuit for obtaining a negative logical product of the word line selection signal and the multiple selection signal. In the semiconductor memory device defect detection method,
A defect detection method for a semiconductor memory device, wherein a data read operation is performed from a memory cell to be tested, and noise is directly applied to a data line to which the memory cell to be tested is connected.   A data read operation from the inspection target memory cell is performed by previously writing data opposite to the data written in the inspection target memory in another memory cell connected to the data line to which the inspection target memory cell is connected. 10. The method of detecting a defect in a semiconductor memory device according to claim 9, wherein the noise is applied to the data line by performing a data read operation also from the other memory cells when performing the operation. As the other memory cell, a memory cell having a capacitance equal to the capacitance of the memory cell to be inspected is used,
Driving a first word line connected to the memory cell to be tested;
11. The semiconductor memory device according to claim 10, wherein the second word line connected to the other memory cell is driven simultaneously with activation of the sense amplifier or at timing adjusted before and after activation of the sense amplifier. Defect detection method. As the other memory cell, a memory cell having a capacitance smaller than the capacitance of the memory cell to be inspected is used,
11. The semiconductor memory device according to claim 10, wherein the second word line connected to the other memory cell is driven simultaneously with driving the first word line connected to the memory cell to be inspected. Defect detection method. As the other memory cell, a memory cell having a capacitance larger than that of the memory cell to be inspected is used,
Driving a first word line connected to the memory cell to be tested;
Start the sense amplifier,
11. The defect detection method for a semiconductor memory device according to claim 10, wherein the second word line connected to the other memory cell is driven after that.

Images