JP4771610B2 - Memory circuit and test method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a memory circuit in which complementary memory cell pairs to which contents opposite to each other are written are connected to a bit line pair and these are selected by the same word line, and a test method thereof.
[0002]
[Prior art]
In this type of memory circuit, the bit line pair potential difference that occurs after activation of the word line is approximately twice that of a normal memory circuit that reads the stored contents of a single cell to the bit line. In addition to being highly resistant to changes and noise during reading, the reliability is high and the refresh cycle can be extended.
[0003]
[Problems to be solved by the invention]
However, since the read potential difference is “about twice”, failure detection becomes difficult, and cell characteristic evaluation cannot be performed based on the same standard as a normal memory circuit. Tests had to be doubled, and the failure analysis time during memory development was particularly long.
[0004]
In view of such problems, the object of the present invention is to evaluate the cell characteristics of a memory circuit that reads the stored contents of a complementary cell pair to a bit line pair on the same basis as the memory circuit that reads the stored contents of a single cell to a bit line. It is an object of the present invention to provide a memory circuit and a test method thereof.
[0005]
[Means for solving the problems and their effects]
In one aspect of the memory circuit testing method according to the present invention, a sense amplifier circuit and a precharge circuit are connected between the intermediate bit line pair, and one end and the other end of the intermediate bit line pair are respectively separated from the first and second bit lines. The first bit line pair is connected to the first bit line pair via the switch pair, and one and the other of the pair of complementary memory cells selected by the first word line are connected to each of the first bit line pair. The memory contents of the memory circuit in which one and the other of the pair of complementary memory cells selected by the second word line are connected to each of the line pairs are tested. In this test,
Only one of four bit line isolation switches constituting the first and second bit line isolation switch pairs is turned on,
Selectively activating one of the first and second word lines related to the on-state bit line isolation switch while the precharge circuit is off;
Next, the turned on bit line isolation switch is turned off,
Next, the sense amplifier circuit is activated,
Next, based on the potential difference of the intermediate bit line pair, the stored contents of the memory cell corresponding to the turned-on bit line isolation switch in the complementary memory cell pair connected to the activated word line are confirmed.
[0006]
According to this configuration, although a potential difference is caused by charge transfer between the first or second bit line pair and the selected complementary memory cell pair, the four bits constituting the first and second bit line isolation switch pairs Since only one of the line separation switches is turned on, the potential difference between the pair of intermediate bit lines becomes a value corresponding to only the stored contents of the memory cell corresponding to the turned on bit line separation switch. Since the turned-on bit line isolation switch is turned off and the sense amplifier circuit is activated in a state where the sense amplifier circuit is isolated from the first and second bit line pairs, any one of the complementary memory cell pairs is activated. Can be tested. That is, although the bit line pair read potential difference is determined by the capacitor potential of the complementary memory cell pair, a read operation that depends only on any one capacitor potential of the complementary memory cell pair can be performed. Therefore, the cell characteristics of the memory circuit that reads the storage contents of the complementary cell pair to the bit line pair can be evaluated on the same basis as the normal memory circuit that reads the storage contents of the single cell to the bit line. In another aspect of the method for testing a memory circuit according to the present invention,
Turning on the first and second bit line isolation switch pairs;
Selectively activating one of the first and second word lines with the precharge circuit off;
Next, the sense amplifier circuit is activated,
Next, based on the potential difference of the intermediate bit line pair, the stored contents of the complementary memory cell pair connected to the activated word line are confirmed.
[0007]
According to this configuration, the bit line capacitance at the time of the test is about twice that in normal use, so that the bit line pair read potential difference is generated in the same degree as in a normal memory circuit. Therefore, it is possible to roughly evaluate the memory circuit that reads the stored contents of the complementary cell pair to the bit line pair on the same basis as that of a normal memory circuit.
[0008]
In addition, the test time for all the memory cells is about half that in the case of the above embodiment.
[0009]
Other objects, configurations and effects of the present invention will become apparent from the following description.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In general, an inverted signal of the signal SZ is represented by SX, and the endings Z and X indicate that they are active high and active low signals, respectively.
[0011]
[First Embodiment]
FIG. 1 is a schematic block diagram showing a part of the memory circuit according to the first embodiment of the present invention.
[0012]
This memory circuit includes cell arrays of blocks BLK0 to BLK3. Sense amplifier rows 10 to 14 are formed so as to sandwich both sides of each block.
[0013]
FIG. 3 shows a schematic configuration of a part of these blocks and sense amplifier arrays. In FIG. 3, black rectangles indicate memory cells connected to the intersections of the bit lines and the word lines. For simplification, FIG. 3 shows a case where only two pairs of complementary memory cells are connected to one bit line pair.
[0014]
For each of the blocks BLK0 to BLK3, the value of the row address least significant bit signal RA00Z is “0”, “1”, “1”, “0” from the left side with respect to the word line. Thereby, for example, when activating the word line in the blocks BLK0 and BLK1 corresponding to RA00Z = '0', for example, the word line WL0 or WL1, the sense amplifier circuit in the sense amplifier row 11 is used. Thus, the sense amplifier circuits in the sense amplifier arrays 10 and 12 maintain the inactive state. Similarly, when the word line corresponding to RA00Z = '1' is activated, the sense amplifier circuit in the sense amplifier row 10 is used for the block BLK0, and the sense amplifier in the sense amplifier row 12 for the block BLK1. A circuit is used, and the sense amplifier circuit in the sense amplifier array 11 maintains an inactive state.
[0015]
FIG. 4 is a circuit diagram showing the sense amplifier unit 20 in FIG. 3 and part of both sides thereof.
[0016]
The sense amplifier unit 20 includes a sense amplifier circuit 21 and a precharge circuit 22 connected between the intermediate bit lines ML0 and * ML0, and one end of the intermediate bit lines ML0 and * ML0 and the bit lines BL0 and * BL0. Bit line isolation NMOS transistors 23 and 24 respectively connected to the other bit lines, and bit line isolation NMOS transistors 25 and 26 connected between the other ends of the intermediate bit lines ML0 and * ML0 and the bit lines BL1 and * BL1, respectively. And have.
[0017]
The sense amplifier circuit 21 has two CMOS inverters connected between drive signal lines to which the sense amplifier activation signals PSA and NSA are supplied, and these are mutually connected in a flip-flop type. The sense amplifier circuit 21 is used when RA00Z = “0” as described above.
[0018]
The precharge circuit 22 includes an NMOS transistor connected between the power supply potential Vpr, for example, VDD / 2 and the intermediate bit line ML0, and between the power supply potential Vpr and the intermediate bit line * ML0, and the intermediate bit lines ML0 and * 0. An NMOS transistor for equalization connected between ML0 and a bit line reset signal BRSX is supplied to these gates. Wiring lines ISO01, ISO00, ISO11, and ISO10 are connected to the gates of the bit line isolation NMOS transistors 23 to 26, respectively.
[0019]
The bit line isolation NMOS transistors 23 to 26 are for sharing the sense amplifier circuit 21 and the precharge circuit 22 with the adjacent blocks BLK0 and BLK1, and when the block BLK0 is active, the bit line isolation NMOS transistor When the transistors 25 and 26 are turned off and the block BLK1 is active, the bit line isolation NMOS transistors 23 and 24 are turned off.
[0020]
Memory cells M0 and * M0 (complementary memory cell pairs) are connected to the intersections of the bit lines BL0 and * BL0 and the word line WL0, respectively, and these NMOS transistor switches are turned on by activation of the word line WL0. The charge moves so that the potential is equal to the potential of the bit line connected thereto, and the bit line potential changes, for example, by 100 mV. The same applies to the memory cells M1 and * M1 (complementary memory cell pairs) connected to the intersections of the bit lines BL1 and * BL1 and the word line WL1, respectively. The complementary memory cell pair is charged with voltages of opposite logic values at the time of writing.
[0021]
The potential difference between the intermediate bit lines ML0 and * ML0 is transmitted to the read circuit 29, the logical value is determined, and read out to the outside. The read circuit 29 includes, for example, a column switch that is selectively turned on by the output of the column decoder, and a direct sense circuit.
[0022]
FIG. 5 shows an example of the layout in the vicinity of the wirings ISO00 and ISO01 in FIG.
[0023]
In FIG. 5, the gate lines GL0 and GL1 are common to the bit line isolation NMOS transistors in the same column, and the gate lines GL0 and GL1 include the gates of the bit line isolation NMOS transistors 24 and 23 of FIG. Yes. 4 has N-type regions 231 and 232 and a part of the upper gate line GL1 between them, and the NMOS transistor 24 has N-type regions 241 and 242 and an upper portion between them. Part of the gate line GL0. In the gate lines GL0 and GL1, the ends of branch lines from the center are connected to the upper metal wirings ISO00 and ISO01 via interlayer contacts.
[0024]
Next, the operation of the circuit of FIG. 4 will be described.
[0025]
FIG. 7 is a timing chart showing an operation when reading the stored contents of the memory cell * M0 of FIG. 4 during a test.
[0026]
The cell storage values of the memory cells M0 and * M0 are opposite to each other, and these cell charging voltages are 0 V and VDD, respectively. Initially, the word line WL0 is low and the NMOS transistor switches of the memory cells M0 and * M0 are off. Further, the sense amplifier activation signals PSA and NSA are at the potential of VDD / 2 and the sense amplifier circuit 21 is inactive. Further, the wirings ISO00, ISO01, ISO10 and ISO11 are at a high level, the NMOS transistors 23 to 26 for bit line isolation are turned on, the bit line reset signal BRSX is at a high level and the precharge circuit 22 is turned on, and the bit lines ML0, BL0, BL1, * ML0, * BL0 and * BL1 are precharged and their potential is VDD / 2.
[0027]
Each of the time points t1 to t4 in FIG. 7 is determined by, for example, an elapsed time after the row address strobe signal BRASZ transits to a high level.
[0028]
(T0) The bit line reset signal BRSX transits to a low level and the precharge circuit 22 is turned off. At this timing, the wirings ISO01, ISO10 and ISO11 transit to a low level and the NMOS transistors 23 and 25 for bit line isolation 26 is turned off.
[0029]
(T1) The word line WL0 changes to high level, and the NMOS transistor switches of the memory cells M0 and * M0 are turned on. As a result, the potentials of the bit lines * BL0 and * ML0 increase by ΔV1, and the potential of the bit line BL0 decreases by ΔV2. Since the bit line isolation NMOS transistor 23 is off, the potential of the bit line ML0 is maintained at VDD / 2.
[0030]
(T2) The wiring ISO00 transits to a low level to turn off the bit line isolation NMOS transistor 24, and the potentials of the sense amplifier activation signals PSA and NSA transit to VDD and 0 V, respectively, to activate the sense amplifier circuit 21. The potential difference ΔV1 between the bit lines * ML0 and ML0 is amplified, and the potentials of the bit lines ML0 and * ML0 change to 0 V and VDD, respectively.
[0031]
(T3) The wirings ISO00 and ISO01 transit to a high level, the bit line isolation NMOS transistors 23 and 24 are turned on, and the potentials of the bit lines BL0 and * BL0 change to 0 V and VDD, respectively. As a result, the restore operation is started for the memory cells M0 and * M0. Further, the read circuit 29 starts reading data corresponding to the potential difference between the bit lines ML0 and * ML0 to the outside.
[0032]
(T4) The word line WL0 transitions to a low level, the NMOS transistor switches of the memory cells M0 and * M0 are turned off, and the restore operation is completed.
[0033]
(T5) The bit line reset signal BRSX transits to a high level and the precharge circuit 22 is turned on. At the timing of this transition, both the sense amplifier activation signals PSA and NSA change to the potential VDD / 2 and the sense amplifier The circuit 21 becomes inactive, and the bit lines BL0, * BL0, ML0, and * ML0 become the precharge potential VDD / 2.
[0034]
(T6) Almost the same as the bit line reset signal BRSX transits to the high level, or the interconnects ISO10 and ISO11 transit to the high level at the time t6 after a predetermined time has elapsed since the transition to the high level, and the NMOS for bit line isolation Transistors 25 and 26 are turned on and return to the initial state.
[0035]
FIG. 8 is a timing chart showing an operation when reading the stored contents of the memory cell M0 of FIG. 4 during a test.
[0036]
In this case, the signal waveforms of the wirings ISO00 and ISO01 are the same as those of the wirings ISO01 and ISO00 of FIG. 7, respectively, and the other signal waveforms are the same as those of FIG.
[0037]
Conventionally, the bit line pair potential difference (ΔV1 + ΔV2) at the time of reading is amplified by the sense amplifier circuit 21 to determine the stored contents. Therefore, the amplified voltage is affected by the change in the holding voltage due to cell charge leakage and the noise at the time of reading. When the logical value is opposite to the stored content, it is difficult to determine which memory cell is defective and which memory cell characteristic is bad.
[0038]
However, according to the first embodiment, when the bit line pair potential difference (ΔV1 + ΔV2) occurs, one of the bit line isolation NMOS transistors 23 and 24 is off, so the potential difference between the intermediate bit lines ML0 and * ML0 is ΔV1 when the NMOS transistor 23 is off, ΔV2 when the NMOS transistor 24 is off, and the potential difference is amplified by the sense amplifier circuit 21 after the bit line isolation NMOS transistor 23 is turned off. One of the memory cell pairs can be tested. After that, both the bit line isolation NMOS transistors 23 are turned on and the restore operation is performed on the memory cell pair, so that the test can be similarly performed on the other of the complementary memory cell pair.
[0039]
That is, although the bit line pair potential difference is (ΔV1 + ΔV2), the stored contents of each of the complementary memory cell pair can be read independently, so that the cell is based on the same standard as a normal DRAM circuit having a single cell array. Properties can be evaluated. For example, when the refresh characteristic is poor at the time of memory development, it becomes possible to measure and evaluate conventionally in pursuit of the problem.
[0040]
FIG. 9 is a timing chart showing an operation when reading the stored contents of the memory cells M0 and * M0 of FIG. 4 during normal use.
[0041]
During normal use, the wirings ISO00 and ISO01 are maintained at a high level, that is, the bit line isolation NMOS transistors 23 and 24 are maintained on. Other signal waveforms are the same as those in FIG. 7 except for the waveforms of the intermediate bit line pair M0 and M0.
[0042]
By such an operation, the absolute value (ΔV1 + ΔV2) of the bit line pair potential difference before amplification when the word line WL0 is activated is about twice that in the test, so that the refresh characteristics are improved.
[0043]
In general, (ΔV1 + ΔV2) depends on the capacitance Ccell of each cell, the capacitance Cbit of each bit line, and the difference VS between the high-level and low-level cell voltages,
ΔV1 + ΔV2 = Ccell · VS / (Ccell + Cbit) (1)
It is expressed. VS is VDD immediately after restoration, but changes with time due to leakage.
[0044]
Next, a circuit for performing the above-described test operation and normal operation will be described.
[0045]
FIG. 2 shows an example of a signal generation unit supplied to the circuit of FIG.
[0046]
The row address RA is latched in the row address register 31 by a latch signal from the control circuit 30. Two bits of the row address register 31 are decoded by the predecoder 32 to generate block selection signals BLK0Z to BLK3Z that are selectively activated. The block selection signal BLK0Z is supplied to the bit line isolation switch control circuits 40 to 42 in FIG. 1, the block selection signal BLK1Z is supplied to the bit line isolation switch control circuits 41 to 44, and the block selection signal BLK2Z is the bit line isolation switch control circuit. The block selection signal BLK3Z is supplied to the bit line isolation switch control circuits 45 to 47.
[0047]
Bits other than 2 bits for block selection in the row address register 31 are supplied to the predecoder 33 and decoded, and the result and block selection signals BLK0Z to BLK3Z are supplied to the word decoders 50 to 53 of FIG. The selected word line of the selected block is activated.
[0048]
Regarding the least significant bit RA00Z of the row address register 31, in addition to being used for word line selection, it is inverted by the inverter 34 to generate a bit RA00X. These row address least significant bit signals RA00Z and RA00X are supplied to the bit line isolation switch control circuits 40 to 47 shown in FIG.
[0049]
The test signal TES supplied from the outside is amplified by the buffer gate 35 to become the test signal TESZ, and is supplied to each of the bit line isolation switch control circuits 40 to 47 in FIG.
[0050]
The control circuit 30 generates various control signals based on an externally supplied clock CLK, chip select signal CSX, row address strobe signal RASX, column address strobe signal CASX, write enable signal WEX, and internal signals. That is, for example, the control circuit 30 generates a row address strobe signal BRASZ in which the retimed signal of the row address strobe signal RASX is in reverse phase, and the bit line reset signal BRSX and the sense are detected from this signal BRASZX and the block selection signals BLK0Z to BLK3Z. Amplifier activation signals PSA and NSA are generated. The row address strobe signal BRASZ is supplied to each of the bit line isolation switch control circuits 40 to 47 of FIG. 1 as a reference signal for the timing of activation and inactivation of the isolation switch control wiring. The sense amplifier activation signals PSA and NSA and the bit line reset signal BRSX are supplied to each of the sense amplifier rows 10 to 14.
[0051]
In FIG. 1, bit line isolation switch control circuits 40 to 47 have the same configuration, and signal input / output positions correspond to each other. The output ends of the bit line isolation switch control circuits 40, 42, 44 and 46 correspond to a pair of isolation switch control wirings (corresponding to the wirings ISO10 and ISO11 in FIG. 7) arranged on the right side of the sense amplifier rows 10 to 13, respectively. And the output ends of the bit line isolation switch control circuits 41, 43, 45 and 47 are respectively connected to a pair of isolation switch control wirings (wirings in FIG. 7) arranged on the left side of the sense amplifier rows 11-14. One corresponding to ISO00 and ISO01). For the bit line isolation switch control circuits 40 and 47 at both ends, the input signal corresponding to the non-existent block is fixed to the high level “H”.
[0052]
The word decoders 50 to 53 are provided corresponding to the blocks BLK0 to BLK3, respectively.
[0053]
FIG. 6 is a detailed circuit diagram of the bit line isolation switch control circuit 41 in FIG.
[0054]
(1) Circuits related to normal use
The NOR gate 60 and the NAND gate 61 are circuits related to normal use. One input terminal of the NOR gate 60 is supplied with a test signal TESZ, and the other input terminal is supplied with a block selection signal BLK1Z and a row address strobe signal BRASZ. 61 is supplied. The output of the NOR gate 60 is supplied to one input terminal of each of the OR gates 62 and 63. The outputs of the OR gates 62 and 63 are respectively supplied to level shift circuits (or buffer circuits) 64 and 65 having the same configuration. The voltage amplitude of the outputs of the level shift circuits 64 and 65 is higher than that of the input (the same voltage amplitude in the case of a buffer circuit). Outputs of the level shift circuits 64 and 65 are supplied to wirings ISO00 and ISO01 via inverters 66 and 67, respectively.
[0055]
(1-1) Since the test signal TESZ is at a low level during normal use, the output of the NOR gate 60 is at a high level only when both the block selection signal BLK1Z and the row address strobe signal BRASZ are at a high level. When the block BLK0 is selected, since the block selection signal BLK1Z is at a low level, the wirings ISO00 and ISO01 maintain a high level as shown in FIG. When the block BLK1 is selected, since the block selection signal BLK1Z is at a high level, the lines ISO00 and ISO01 fall in response to the rise of the row address strobe signal BRASZ. This corresponds to the falling of the wirings ISO10 and ISO11 in FIG. Next, when the row address strobe signal BRASZ falls, the wirings ISO00 and ISO01 rise. This corresponds to the rise of the wirings ISO10 and ISO11 in FIG.
[0056]
(1-2) Since the test signal TESZ is at a high level during the test, the output of the NOR gate 60 is at a low level regardless of the output value of the NAND gate 61, and the outputs of the OR gates 62 and 63 are signals at the other input terminal. Determined.
[0057]
(2) Circuits related to the test
Components 68-76 are circuits involved during testing. The test signal TESZ is supplied to one input terminal of the NOR gate 69 via the inverter 68, and the block input signal BLK0Z and the row address strobe signal BRASZ are supplied to the other input terminal of the NOR gate 69 via the NAND gate 70. . The output of the NOR gate 69 is supplied to pulse generation circuits 71 and 72.
[0058]
(2-1) Since the test signal TESZ is at a low level during normal use, the output of the NOR gate 69 is maintained at a low level regardless of the output value of the NAND gate 70, and the outputs of the OR gates 62 and 63 are determined by the output of the NOR gate 60. .
[0059]
(2-2) Since the test signal TESZ is high during the test, the output of the NOR gate 69 is high only when both the block selection signal BLK0Z and the row address strobe signal BRASZ are high.
[0060]
When the block BLK0 is selected, since the block selection signal BLK0Z is at a high level, the output of the NOR gate 69 rises at the rising edge of the row address strobe signal BRASZ, and in response to this, the pulse generation circuits 71 and 72 respectively output the circuit shown in FIG. Pulses of the indicated signals S1 and S2 are generated.
[0061]
When the row address least significant bit signals RA00Z and RA00X are at a high level and a low level, respectively, the outputs of the pulse generation circuits 71 and 72 are connected to the other of the OR gates 62 and 63 via the positively connected NMOS transistors 73 and 74, respectively. Supplied to the input end. Therefore, the potentials of the wirings ISO00 and ISO01 have waveforms as shown in FIG.
[0062]
When the row address least significant bit signals RA00Z and RA00X are at a low level and a high level, respectively, the outputs of the pulse generation circuits 71 and 72 are connected to the OR gate 63 and the OR gate 62 via the reversely connected NMOS transistors 75 and 76, respectively. It is supplied to the other input end. Therefore, the potentials of the wirings ISO00 and ISO01 have waveforms as shown in FIG.
[0063]
When the block BLK1 is selected, since the block selection signal BLK0Z is at a low level, the output of the NOR gate 69 is maintained at a low level regardless of the output value of the NAND gate 70, and the wirings ISO00 and ISO01 are maintained at a low level.
[0064]
With the circuit as described above, the signal waveforms of the separation switch control wirings correspond to FIGS.
[0065]
The NMOS transistors 73 to 76 as switches may use CMOS transfer gates in which a PMOS transistor and an NMOS transistor are connected in parallel.
[0066]
[Second Embodiment]
FIG. 10 is a schematic block diagram showing a part of the memory circuit according to the second embodiment of the present invention.
[0067]
FIG. 11 is a circuit diagram showing a part of the sense amplifier row 11A of FIG. 10 and a part of the blocks BLK0 and BLK1 on both sides thereof.
[0068]
The circuit itself of FIG. 11 that is the control target is the same as the conventional one, the gates of the bit line isolation NMOS transistors 23 and 24 are connected to the wiring ISO0, and the gates of the bit line isolation NMOS transistors 25 and 26 are connected to the wiring ISO1. Has been. The other points are the same as those in FIG.
[0069]
FIG. 12 shows the layout of the separation switch control wiring ISO0 and its vicinity in FIG.
[0070]
The gate line GL0 is common to the transistor rows including the bit line isolation NMOS transistors 23 and 24 of FIG. In the gate line GL0, the end of the branch line from the center thereof is connected to the upper wiring ISO0 via an interlayer contact.
[0071]
Next, the operation of the circuit of FIG. 11 will be described.
[0072]
FIG. 13 is a timing chart showing an operation when reading the stored contents of the memory cells M0 and * M0 of FIG. 11 during the test.
[0073]
The first state before time t0 is the same as in the case of the first embodiment.
[0074]
Each of the time points t1, t2, and t4 in FIG. 13 is determined by, for example, an elapsed time after the bit line reset signal BRSX transitions to a low level.
[0075]
The feature of the second embodiment is that when the block BLK0 is selected, not only the isolation switch control wiring ISO0 on the block BLK0 side but also the isolation switch control wiring ISO1 on the adjacent non-selected block BLK1 side is maintained at a high level. Thus, the bit line isolation NMOS transistors 23 to 26 are turned on.
[0076]
(T0) The bit line reset signal BRSX transitions to a low level and the precharge circuit 22 is turned off.
[0077]
(T1) The word line WL0 changes to high level, and the NMOS transistor switches of the memory cells M0 and * M0 are turned on. Since the bit line capacitance is about twice that in the first embodiment, the potentials of the bit lines * BL0 and * ML0 are increased by approximately ΔV1 / 2, and the potential of the bit line BL0 is decreased by approximately ΔV2 / 2. To do. That is, the read potential difference between the bit line pair is
Ccell / VS / (Ccell + 2Cbit) (2)
It becomes. The value of equation (2) is approximately half that of equation (1) (ΔV1 + ΔV2) / 2.
[0078]
(T2) The sense amplifier activation signals PSA and NSA transition to VDD and 0 V, respectively, to activate the sense amplifier circuit 21, and the potential difference between the bit lines ML0 and * ML0 is approximately − (ΔV1 + ΔV2) / 2 and the bit is amplified. The potentials of the lines ML0 and * ML0 change to 0V and VDD, respectively.
[0079]
In addition, a restore operation for the memory cells M0 and * M0 is started, and reading of data corresponding to the potential difference between the intermediate bit lines ML0 and * ML0 is started by the read circuit 29.
[0080]
The operation from time t4 to t6 is the same as that in FIG.
[0081]
The operation for reading the stored contents of the memory cells M1 and * M1 in FIG. 11 during the test is the same as that in the timing chart of FIG.
[0082]
According to the second embodiment, such a read operation during a test causes a read potential difference of the same level as that of a normal DRAM circuit having a single cell array between bit line pairs. The memory circuit can be roughly evaluated.
[0083]
In addition, since the refresh cycle can be halved during testing, the test time for all memory cells is approximately half that of the conventional method. For example, in the development of the memory circuit, it took a day in the past to examine the outline of the storage retention characteristics of all the memory cells of several hundred chips formed on one wafer. According to, it will take about half a day.
[0084]
The operation when reading the stored contents of the memory cells M0 and * M0 in FIG. 11 during normal use is such that the signal waveform of the wiring ISO1 is shown by a dotted line in FIG. 13, and the other signal waveforms are the same as in the test. is there. In this case, the potential of the wiring ISO1 falls at the falling timing of the bit line reset signal BRSX, and then at the time t6 almost at the same time as the bit line reset signal BRSX rises at the time t5 or after a predetermined time elapses. Thus, the potential of the wiring ISO1 rises.
[0085]
Next, a circuit for performing the above-described test operation and normal operation will be described.
[0086]
10, bit line isolation switch control circuits 80 to 89 have the same configuration, and signal input positions correspond to each other.
[0087]
The output ends of the bit line isolation switch control circuits 81, 83, 85, 87 and 89 are for controlling the isolation switches arranged on the right side of the sense amplifier arrays 10A to 14A via inverters 91, 93, 95, 97 and 99, respectively. Connected to the wiring (corresponding to the wiring ISO1 in FIG. 11), the output ends of the bit line isolation switch control circuits 80, 82, 84, 86 and 88 are connected to inverters 90, 92, 94, 96 and 98, respectively. Are connected to separation switch control wirings (corresponding to the wirings ISO0 and ISO1 in FIG. 11) arranged on the left side of the sense amplifier arrays 10A to 14A.
[0088]
For each of the bit line isolation switch control circuits 81 and 88 corresponding to the nonexistent block, all three inputs are always at a high level so that the output is always at a low level 'L'.
[0089]
A row address strobe signal BRASZ as a reference signal for determining output activation and deactivation timing is supplied to each of the bit line isolation switch control circuits 80, 82 to 87 and 89. As is clear from the above description regarding FIG. 3, the row address least significant bit signal RA00Z is supplied to the bit line isolation switch control circuits 80, 84, 85 and 89 corresponding to the odd-numbered sense amplifier columns, and the row address least significant bit signal RA00Z is supplied. The lower bit signal RA00X is supplied to the bit line isolation switch control circuits 82, 83, 86 and 87 corresponding to the even-numbered sense amplifier columns. The test signal TESZ is supplied to the input terminal of one of the OR gates 100 to 109. The other input terminals of the odd-numbered OR gates 100, 102, 104, 106 and 108 to 109 are supplied with signals BLK0Z to BLK3Z and 'H' for selecting the right block, respectively, and the even-numbered OR gates 101 and 103 are selected. , 105, 107 and 109 are supplied with a signal 'H' and BK0Z to BLK3Z for selecting the left block, respectively. A fixed low level 'H' corresponds to a non-existent block.
[0090]
Next, the operation of the bit line isolation switch control circuits 82 and 83 during normal use will be described.
[0091]
When a word line corresponding to RA00Z = '0' in the block BLK0 is selected during normal use, the output of the bit line isolation switch control circuit 82 is that the row address least significant bit signal RA00X is at a high level and the block selection signal Since BLK1Z is at a low level, the low level is maintained. Therefore, the potential of the wiring ISO0 is maintained at a high level as shown in FIG. In contrast, the output of the bit line isolation switch control circuit 83 changes to high level at the timing when the row address strobe signal BRASZ changes to high level, that is, the wiring ISO1 changes to low level. Next, at the time t5, the row address strobe signal BRASZ transitions to a low level, and immediately after or after (t6-t5), the output of the bit line isolation switch control circuit 83 transitions to a low level, that is, the wiring ISO1 is Transition to high level. Therefore, the signal waveform of the wiring ISO1 is as shown by the dotted line in FIG.
[0092]
Next, the operation of the bit line isolation switch control circuits 82 and 83 during the test will be described.
[0093]
During the test, since the test signal TESZ is at a high level and the outputs of the OR gates 100 to 109 are all at a high level, the outputs of the bit line isolation switch control circuits 81 to 87 are irrelevant to the selected block. When the word line corresponding to RA00Z = '0' in the block BLK0 is selected, the outputs of the bit line isolation switch control circuits 82 and 83 are both kept at a low level, and the potentials of the wirings ISO0 and ISO1 are at a high level. maintain. Therefore, the signal waveform of the wiring ISO1 is as shown by the solid line in FIG.
[0094]
Next, a modification of the second embodiment will be described.
[0095]
In FIG. 10, there is no cell array outside the sense amplifier arrays 10A and 14A. However, in order to enable testing on both sides of the blocks BLK0 and BLK3 in the same manner as the blocks BLK1 and BLK2, FIG. In this manner, a cell array that can be used during testing may be arranged outside the sense amplifier arrays 10A and 14A. Note that the memory cells connected to the word lines indicated by dotted lines are not used.
[0096]
Further, in order to use the cell arrays on both sides in FIG. 14 more effectively, as shown in FIG. 15, a sense amplifier row is further arranged for the cell arrays on both sides, and the sense amplifier rows and cell arrays on both sides are used for redundancy. And a region including a defective cell may be replaced with a corresponding redundant region. The region is, for example, a word line unit or a sense amplifier unit corresponding to a bit line. In FIG. 15, the word lines, bit lines and sense amplifiers indicated by dotted lines are for redundancy, and the cells connected to the word lines and bit lines indicated by dotted lines are redundant cells.
[0097]
Note that the present invention includes various other modifications.
[0098]
For example, the present invention is not limited to a DRAM circuit, but can be applied to various memory circuits having complementary memory cell pair arrays.
[0099]
In addition, a memory circuit combining the first embodiment and the second embodiment is configured, and the test of the first embodiment and the second embodiment can be selected according to the supplied test mode signal. First, a test is performed in the test mode of the second embodiment to detect a complementary memory cell pair in which a read error has occurred, and then only the error complementary memory cell pair is tested in the test mode of the first embodiment. Thus, the error cell may be evaluated in more detail. In this case, the test time can be shortened and detailed evaluation can be performed.
[0100]
The present invention includes the following supplementary notes.
[0101]
(Supplementary Note 1) A sense amplifier circuit and a precharge circuit are connected between the intermediate bit line pair, and one end and the other end of the intermediate bit line pair are connected to the first and second bit lines via the first and second bit line isolation switch pairs, respectively. One pair of complementary memory cell pairs selected by the first word line is connected to each of the first bit line pairs, and the second word line is connected to each of the second bit line pairs. In the test method of the memory circuit for testing the storage contents of the memory circuit to which one and the other of the pair of complementary memory cells selected by
Only one of four bit line isolation switches constituting the first and second bit line isolation switch pairs is turned on,
Selectively activating one of the first and second word lines related to the on-state bit line isolation switch while the precharge circuit is off;
Next, the turned on bit line isolation switch is turned off,
Next, the sense amplifier circuit is activated,
Next, based on the potential difference of the intermediate bit line pair, the stored contents of the memory cell corresponding to the turned-on bit line isolation switch in the complementary memory cell pair connected to the activated word line are confirmed.
A test method for a memory circuit. (1)
(Appendix 2) After the sense amplifier circuit is activated, the bit line isolation switch turned off from the on state and the bit line isolation switch paired therewith are turned on and connected to the activated word line. Restore operation for the pair of complementary memory cells
Next, the activated word line is deactivated and the restore operation is terminated.
The method of testing a memory circuit according to appendix 1, wherein:
[0102]
(Supplementary Note 3) A sense amplifier circuit and a precharge circuit are connected between the intermediate bit line pair, and one end and the other end of the intermediate bit line pair are connected to the first and second bit lines via the first and second bit line isolation switch pairs, respectively. One pair of complementary memory cell pairs selected by the first word line is connected to each of the first bit line pairs, and the second word line is connected to each of the second bit line pairs. In the memory circuit to which one and the other of the pair of complementary memory cells selected by
Only one of the four bit line isolation switches constituting the first and second bit line isolation switch pairs is turned on according to the value of the supplied row address, and then the precharge circuit is in an off state, The turned-on bit line isolation switch is turned off, and when the test signal is inactive, one of the first and second bit line isolation switch pairs is selectively turned on according to the supplied row address value. A bit line isolation switch control circuit to
In response to the row address, a row decoder that selectively activates one of the first and second word lines with the precharge circuit turned off;
A control circuit for activating the sense amplifier circuit in a state where the turned-on bit line isolation switch is turned off;
A read circuit that reads out the stored contents of the memory cell based on the potential difference between the pair of intermediate bit lines;
A memory circuit comprising: (2)
(Supplementary Note 4) After the sense amplifier circuit is activated, the bit line isolation switch control circuit turns on the bit line isolation switch that is turned off from the on state and the bit line isolation switch that is paired with the bit line isolation switch. The memory circuit according to appendix 3, characterized by:
[0103]
(Supplementary Note 5) A sense amplifier circuit and a precharge circuit are connected between the intermediate bit line pair, and one end and the other end of the intermediate bit line pair are connected to the first and second bit lines via the first and second bit line isolation switch pairs, respectively. One pair of complementary memory cell pairs selected by the first word line is connected to each of the first bit line pairs, and the second word line is connected to each of the second bit line pairs. In the test method of the memory circuit for testing the storage contents of the memory circuit to which one and the other of the pair of complementary memory cells selected by
Turning on the first and second bit line isolation switch pairs;
Selectively activating one of the first and second word lines with the precharge circuit off;
Next, the sense amplifier circuit is activated,
Next, based on the potential difference of the intermediate bit line pair, the stored contents of the complementary memory cell pair connected to the activated word line are confirmed.
A test method for a memory circuit. (3)
(Supplementary Note 6) A sense amplifier circuit and a precharge circuit are connected between the intermediate bit line pair, and one end and the other end of the intermediate bit line pair are connected to the first and second bit lines via the first and second bit line isolation switch pairs, respectively. One pair of complementary memory cell pairs selected by the first word line is connected to each of the first bit line pairs, and the second word line is connected to each of the second bit line pairs. In the memory circuit to which one and the other of the pair of complementary memory cells selected by
When the supplied test signal is active, the first and second bit line isolation switch pairs are turned on, and when the test signal is inactive, the first and second bit lines are supplied according to the value of the row address supplied. A bit line isolation switch control circuit for selectively turning on one of the bit line isolation switch pair;
A row decoder that selectively activates one of the first and second word lines related to the bit line isolation switch that is in an on state in response to the row address when the precharge circuit is off;
A control circuit that activates the sense amplifier circuit after the word line is activated; a read circuit that reads out the stored contents of the memory cell based on a potential difference between the pair of intermediate bit lines;
A memory circuit comprising: (4)
(Supplementary Note 7) By performing the method described in Supplementary Note 5, a complementary memory cell pair in which a read error has occurred is detected.
By performing the method according to appendix 1 on the complementary memory cell in which the read error has occurred, each cell characteristic of the pair of complementary memory cells in which the read error has occurred is evaluated.
A test method for a memory circuit. (5)
(Supplementary Note 8) By performing the method described in Supplementary Note 5, a complementary memory cell pair in which a read error has occurred is detected.
Performing the method described in Appendix 2 on the complementary memory cell in which the read error has occurred, thereby evaluating the cell characteristics of each of the complementary memory cell pair in which the read error has occurred.
A test method for a memory circuit.
[Brief description of the drawings]
FIG. 1 is a schematic block diagram showing a part of a memory circuit according to a first embodiment of the present invention.
FIG. 2 is a schematic block diagram showing a generation unit of a signal supplied to the circuit of FIG.
FIG. 3 is a diagram showing a schematic configuration of a part of the memory circuit in FIG. 1;
4 is a circuit diagram showing details of a sense amplifier unit 20 in FIG. 3 and a part of both sides thereof, and a read circuit block; FIG.
FIG. 5 is a diagram showing a layout in the vicinity of separation switch control wirings ISO00 and ISO01 in FIG. 1;
6 is a detailed circuit diagram of the bit line isolation switch control circuit 41 in FIG. 1. FIG.
7 is a timing chart showing an operation when reading the stored contents of the memory cell * M0 of FIG. 4 during a test.
8 is a timing chart showing an operation when reading the stored contents of the memory cell M0 of FIG. 4 during a test.
9 is a timing chart showing an operation when reading the stored contents of the complementary memory cell pair M0, * M0 of FIG. 4 during normal use.
FIG. 10 is a schematic block diagram showing a part of a memory circuit according to a second embodiment of the present invention.
11 is a circuit diagram showing details of a part of the sense amplifier row 11A in FIG. 10 and parts of blocks BLK0 and BLK1 on both sides and a read circuit block.
12 is a diagram showing a layout of an isolation switch control wiring ISO0 and its vicinity in FIG. 10;
13 is a timing chart showing an operation when reading the stored contents of the complementary memory cell pair M0, * M0 of FIG. 11 during a test.
FIG. 14 is a layout diagram showing a part of a memory circuit, showing a modification of the second embodiment of the present invention.
FIG. 15 is a layout diagram showing a part of a memory circuit, showing another modification of the second embodiment of the present invention;
[Explanation of symbols]
10-14, 10A-14A sense amplifier train
20, 20A sense amplifier unit
21 sense amplifier circuit
22 Precharge circuit
23-26 NMOS transistor for bit line isolation
231,232,241,242 N-type region
29 Lead circuit
30 Control circuit
31 Row address register
32, 33 predecoder
40-47, 80-89 Bit line isolation switch control circuit
50-53 word decoder
71, 72 pulse generation circuit
BLK0 to BLK3 blocks
ISO00, ISO01, ISO10, ISO11, ISO0, ISO1 Bit line isolation switch control wiring
TES, TESZ test signal
RA00Z, RA00X Row address least significant bit signal
BLK0Z, BLK1Z, BLK2Z, BLK3Z Block selection signal
BRASZ Row address strobe signal
BRSX Bit line reset signal
BL0, * BL0, BL1, * BL1 bit lines
WL0, WL1 Word line
ML0, * ML0 Intermediate bit line
PSA, NSA sense amplifier activation signal
M0, * M0, M1, * M1 memory cells
GL0, GL1 gate line

Claims (3)

A sense amplifier circuit and a precharge circuit are connected between the intermediate bit line pair, and one end and the other end of the intermediate bit line pair are connected to the first and second bit line pairs via the first and second bit line isolation switch pairs, respectively. And one and the other of the pair of complementary memory cells selected by the first word line are connected to each of the first bit line pair and selected by the second word line to each of the second bit line pair In a test method for a memory circuit for testing the storage contents of a memory circuit to which one and the other of a pair of complementary memory cells are connected,
Four bit line isolation switches constituting the first and second bit line isolation switch pairs and the precharge circuit are turned on so that the intermediate bit line pair, the first bit line pair, and the second bit line are turned on. In a state where the pair is precharged, only one of the four bit line isolation switches is kept on and the other three bit line isolation switches are turned off to turn off the precharge circuit. ,
Next, selectively activate one of the first and second word lines related to the bit line isolation switch maintained on,
Next, the bit line isolation switch maintained on is turned off,
Next, the sense amplifier circuit is activated,
Then, based on the potential difference between the bit line pair between intermediate, evaluate cell characteristics and read out the stored content of the memory cell corresponding to the bit line isolation switch off after maintained at the on of the complementary memory cell pair To
A test method for a memory circuit. A sense amplifier circuit and a precharge circuit are connected between the intermediate bit line pair, and one end and the other end of the intermediate bit line pair are connected to the first and second bit line pairs via the first and second bit line isolation switch pairs, respectively. And one and the other of the pair of complementary memory cells selected by the first word line are connected to each of the first bit line pair and selected by the second word line to each of the second bit line pair In a memory circuit in which one and the other of a pair of complementary memory cells are connected,
During the test, the four bit line isolation switches constituting the first and second bit line isolation switch pairs and the precharge circuit are turned on, and the intermediate bit line pair, the first bit line pair, and the first bit line pair are turned on. In a state where the two bit line pairs are precharged, only one of the four bit line isolation switches is kept on and the other three bit line isolation switches are turned off, and the precharge circuit And then selectively activating one of the first and second word lines associated with the bit line isolation switch maintained on, and then turning off the bit line isolation switch maintained on. A control circuit for activating the sense amplifier circuit;
A read circuit that reads out the stored contents of the memory cell corresponding to the bit line isolation switch that is turned on and then turned off based on the potential difference between the pair of intermediate bit lines while the sense amplifier circuit is active ; Have
A memory circuit having a memory cell test function, wherein cell characteristics of a memory cell from which the stored contents are read are evaluated . A sense amplifier circuit and a precharge circuit are connected between the intermediate bit line pair, and one end and the other end of the intermediate bit line pair are connected to the first and second bit line pairs via the first and second bit line isolation switch pairs, respectively. And one and the other of the pair of complementary memory cells selected by the first word line are connected to each of the first bit line pair and selected by the second word line to each of the second bit line pair In a test method for a memory circuit for testing the storage contents of a memory circuit to which one and the other of a pair of complementary memory cells are connected,
Four bit line isolation switches constituting the first and second bit line isolation switch pairs and the precharge circuit are turned on so that the intermediate bit line pair, the first bit line pair, and the second bit line are turned on. With the pair precharged, the precharge circuit is turned off, one of the first and second word lines is selectively activated, then the sense amplifier circuit is activated, and then the intermediate bit line Based on the potential difference of the pair, the stored contents of the pair of complementary memory cells connected to the activated word line are read out,
If the read storage content is an error, the method of claim 1 is performed on each memory cell of the complementary memory cell pair associated with the error;
A test method for a memory circuit.

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