JP3043992B2 - Ferroelectric memory device and inspection method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a ferroelectric memory device using a ferroelectric capacitor and a method of testing the same.

[0002]

2. Description of the Related Art Recently, a ferroelectric memory device which realizes non-volatility of stored data by using a ferroelectric material for a capacitor of a memory cell has been devised. The ferroelectric capacitor has a hysteresis characteristic, and even when the electric field is zero, remnant polarization having different polarities according to the history remains. By expressing the stored data by the remanent polarization of the ferroelectric capacitor, a nonvolatile memory device can be realized.

[0003] US Patent No. 4,873,664 discloses two types of ferroelectric memory devices. First
Is a type in which a memory cell is constituted by one transistor and one capacitor (1T1C) per bit. For example, one dummy memory cell (ie, reference cell) is provided for every 256 main body memory cells (ie, normal cells).

In the second type, a memory cell is constituted by two transistors and two capacitors (2T2C) per bit without providing a dummy memory cell. A pair of complementary data is stored in a pair of ferroelectric capacitors.

As a ferroelectric material constituting a capacitor, KNO ₃ , PbLa ₂ O ₃ —ZrO ₂ —TiO ₂ , PbTiO ₃ —PbZrO _{3 and the} like are known. PCT
International Patent Publication No. WO93 / 12542 also discloses a ferroelectric material suitable for a ferroelectric memory device and having extremely small fatigue as compared with PbTiO ₃ -PbZrO ₃ .

[0006]

According to the 1T1C type ferroelectric memory device described above, the reference memory cell capacitor (ie, the dummy memory cell capacitor) is
It has, for example, twice the capacity of the main body memory cell capacitor, that is, twice the area. Moreover, the size of the reference memory cell capacitor is different from that of the main memory cell capacitor, and it is necessary to determine the size according to the characteristics of the ferroelectric capacitor.

In the conventional 1T1C type ferroelectric memory device, it is necessary to set the size of the reference memory cell capacitor to a size different from that of the main memory cell capacitor. As a result, the operating margin is reduced particularly at a low voltage. The 2T2C type ferroelectric memory device operates stably, but the memory cell area per bit is about twice as large as that of the 1T1C type.

Further, the conventional 2T2C type or 1T1
Since a margin test of the characteristics of the ferroelectric capacitor cannot be performed with a device of only the C type, there is a problem that a ferroelectric capacitor having poor characteristics cannot be removed by screening.

Although the 1T1C type device has a higher degree of integration than the 2T2C type device, it cannot be remedied when it becomes defective. Therefore, the yield decreases. On the other hand, the 2T2C type device has a low degree of integration, so that the product cost increases.

An object of the present invention is to solve the above-mentioned conventional problems and to provide a dielectric memory device having stable operation at a low voltage and high integration at a high voltage, and an inspection method thereof. Aim.

[0011]

According to the present invention, there is provided a ferroelectric memory device comprising a first bit line and a first bit line via a first memory cell transistor constituting a main memory cell. A first ferroelectric capacitor connected to the first bit line, a second ferroelectric capacitor connected to the second bit line via a second memory cell transistor forming a main memory cell, A third ferroelectric capacitor connected to the second bit line via a third memory cell transistor forming a reference memory cell, and a fourth memory cell transistor forming a second reference memory cell A fourth ferroelectric capacitor connected to the first bit line via the first bit line; and a control circuit for controlling gates of the first to fourth memory cell transistors.

The control circuit has a control function of first and second operation modes, and includes the first and third memory cell transistors in the first operation mode (ie, 1T1C mode). The gate of each transistor in one of the group and the group including the second and fourth memory cell transistors is controlled. The second mode of operation (ie, 2T
In the 2C mode), only one of the gates of the first and second memory cell transistors is controlled.

According to the above configuration, 1T1C mode and 2T1C mode
By switching the operation in the T2C mode, a ferroelectric memory device having stable operation at a low voltage and high integration at a high voltage is provided. Preferably, the first memory cell transistor and the second memory cell transistor are arranged adjacent to each other. Further, it is preferable that the ferroelectric memory device has a voltage detection circuit, and the switching between the first operation mode and the second operation mode is performed by a detection signal from the voltage detection circuit.

According to one feature of the method for testing a ferroelectric memory device of the present invention, the second operation mode, ie,
After the inspection in the T2C mode, an inspection in the first operation mode, that is, the 1T1C mode, is performed on a product that has passed the inspection. According to this method, a 1T1C type device can be inspected in a short time by the 2T2C mode inspection.

According to another characteristic of the inspection method of the present invention, writing is performed in the 1T1C mode using two different power supply voltages (ie, the first and second power supply voltages).
By reading in the C mode, a margin inspection of the ferroelectric memory capacitor is performed. According to this method, for example, a ferroelectric capacitor having poor characteristics is removed by screening, and only a highly reliable device can be supplied.

In addition, since switching between the 1T1C type and the 2T2C type can be performed, even if a 1T1C type device becomes defective, it can be commercialized as a non-defective product using the 2T2C type device, and an improvement in yield can be expected. .

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a circuit of the ferroelectric memory device according to the first embodiment of the present invention. FIG. 2 shows a circuit for generating the control signal MD. This ferroelectric memory cell can be operated in one of an operation mode in which one transistor and one ferroelectric capacitor constitute one-bit data, and an operation mode in which two transistors and two ferroelectric capacitors constitute one-bit data. You can choose.

In FIG. 1, WL0 to WL255 are word lines, DWL0 and DWL1 are reference word lines,
L and / BL are bit lines, CP is a cell plate electrode, DC
P is a reference cell plate electrode, BP is a bit line precharge control signal, SAE is a sense amplifier control signal,
VSS is a ground voltage, and SA is a sense amplifier. C0
C255 is a main body memory cell capacitor, DC0, DC1
Are reference memory cell capacitors, Qn0 to Qn2
55, QnD0, QnD1, QnBP0, and QnBP1 are N-channel MOS transistors. Hereinafter, Qn0
To Qn255 are called main body memory cell transistors.
nD0 and QnD1 are referred to as reference memory cell transistors.

First, the configuration of the ferroelectric memory device will be described. The bit lines BL and / B are connected to the sense amplifier SA.
L is connected. The sense amplifier SA is controlled by a sense amplifier control signal SAE. The first electrode of the reference memory cell capacitor DC0 is connected to the bit line / B via a reference memory cell transistor QnD0 whose gate electrode is connected to the reference word line DWL0.
L. The second electrode of the reference memory cell capacitor DC0 is connected to the reference cell plate electrode DCP.

Reference memory cell capacitor DC1
The first electrode has a gate electrode connected to the reference word line D
It is connected to the bit line BL via a reference memory cell transistor QnD1 connected to WL1. The second electrode of the reference memory cell capacitor DC1 is connected to the reference cell plate electrode DCP.

On the other hand, the first electrode of the main memory cell capacitor C0 is connected to the bit line B via the main memory cell transistor Qn0 whose gate electrode is connected to the word line WL0.
L. The second electrode of the main body memory cell capacitor C0 is connected to the cell plate electrode CP.

The first electrode of the main memory cell capacitor C1 is connected to the bit line / BL via the main memory cell transistor Qn1 whose gate electrode is connected to the word line WL1. Second of main body memory cell capacitor C1
Are connected to the cell plate electrode CP.

NOR gates NOR0 to NOR255 are connected to word lines WL0 to WL255, and NOR gates NOR0 to reference word lines DWL0 and DWL1.
D and NOR1D are connected. These NOR gates include NOR gates NOR0L, NOR1L, and NAN.
D gates NAND1 to NAND255 are connected. These gates constitute a control circuit for selecting an operation mode according to the control signal MD.

As shown in FIG. 2, the circuit for generating the control signal MD for switching the operation mode includes a fuse F, an N-channel MOS transistor Qn, and a NOT circuit INV. The control signal MD is at the logic voltage “L” when the fuse F is not blown,
When the fuse F is cut, the logic voltage becomes “H”.

When the control signal MD is at the logic voltage "L",
For example, word line WL0 and reference word line DWL
0 is selected and the device operates as the 1T1C mode. When the control signal MD is at the logic voltage "H", for example, the word line W
L0 and the word line WL1 are selected, and the reference word lines DWL0 and DWL1 are not selected, and operate in the 2T2C mode.

In the ferroelectric memory device of the present embodiment, when the operation margin is reduced and stable operation is difficult in 1T1C mode, stable operation can be obtained by switching to 2T2C mode. In other words, even if the device is not normal in the 1T1C mode, it can be regarded as a non-defective device in the 2T2C mode. Therefore, an improvement in yield can be expected, and a reduction in product cost can be achieved.

Next, a ferroelectric memory device according to a second embodiment of the present invention will be described. In this device, the circuit for generating the control signal MD of the ferroelectric memory device of the first embodiment is replaced with a circuit using a voltage detection signal. FIG. 3 shows an example of the configuration of the voltage detection circuit. Power supply voltage VDD
Is high, the control signal MD becomes the logic voltage “L”, and V
When DD is low, the control signal MD becomes the logic voltage “H”.

In the 1T1C mode, the operation margin is reduced particularly at a low voltage. The ferroelectric memory device according to the present embodiment includes:
When the power supply voltage is high, the high integration operation is performed in the 1T1C mode, and when the power supply voltage is low, the operation automatically shifts to the 2T2C mode to perform the stable operation. In addition, by performing an inspection (for example, a pattern function inspection) in a short time by the 2T2C mode inspection, and performing a characteristic margin inspection of the ferroelectric memory capacitor, a highly reliable device is supplied.

Next, a method of testing a ferroelectric memory device according to a third embodiment of the present invention and a ferroelectric memory device having the test function will be described. FIG. 4 shows a flowchart of this inspection method. FIG. 5 shows a hysteresis characteristic of the 2T2C mode operation of the ferroelectric capacitor in this inspection method. First, as shown in FIG.
An inspection is performed in the 2T2C mode, and a failure (FAI
The device of L) is excluded as a defective product. If the test is passed (PASS), the test is continuously performed in the 1T1C mode.
It is regarded as a good C-mode product. A device that has passed (PASS) the inspection in the 1T1C mode is considered as a non-defective product in the 1T1C mode.

As described above, by adopting the inspection flow using the 2T2C mode in which the inspection time is shorter (approximately ２) than the 1T1C mode, defective products can be removed at an early stage, so that the entire wafer can be inspected. Time can be reduced.

FIG. 5 shows the hysteresis characteristic of the electric field (horizontal axis) and the electric charge (vertical axis) applied to the ferroelectric capacitor of the memory cell. In the ferroelectric material, even when the electric field becomes zero, the remanent polarization indicated by the points H51 and L51 exists. Therefore, a non-volatile semiconductor memory is realized by using the residual polarization remaining in the ferroelectric capacitor as non-volatile data even when power supply is stopped.

In the 2T2C mode, if the data of the memory cell is "1", one ferroelectric capacitor of the memory cell is in the state of H51 and the other ferroelectric capacitor is in the state of L51. Conversely, if the data in the memory cell is "0", one ferroelectric capacitor of the memory cell is in the state of L51 and the other ferroelectric capacitor is in the state of H
It is in the state of 51. The line L has a slope determined by the capacitance value of the bit line.

When data "1" is read, the data is read from the capacitor to the bit line, and one ferroelectric capacitor of the memory cell changes from the state of H51 to H5.
The state changes to 2. The other ferroelectric capacitor of the memory cell changes from the state of L51 to the state of L52. Thus, the potential difference ΔV5 between the state of H52 and the state of L52 is obtained. After that, H by a sense amplifier or the like.
The potential in the state 52 is amplified to the potential in the state H53,
The potential in the state of L52 is amplified to the potential in the state of L53. Next, as a rewrite (rewrite) operation, H53
Is returned to the potential of the state H54, and the potential of the state L53
Is returned to the potential of the state L54. This L54 is equal to L51. Next, the potential in the state of H54 is reset to the potential in the state of H51.

In the 1T1C mode inspection, 2T
Since the 2C mode write operation is performed, it is also possible to perform an inspection of only the read operation without performing the write operation. In this case, the time required for the write operation in the 1T1C mode is not required, so that the inspection time is further reduced. In FIG. 4, pass / fail is first determined by inspection in the 2T2C mode.
An inspection flow in which only the write operation is performed in the T2C mode and only the read operation is performed in the 1T1C mode may be employed.
In this case, the inspection time is reduced to about 75% as compared with the case where the writing operation and the reading operation are performed in the 1T1C mode.

Further, the self-inspection function by this inspection method can be provided in the ferroelectric memory device. For example, first, a self-inspection is performed in the 2T2C mode, and if it is a non-defective product, the inspection is switched to the 1T1C mode. Conversely, the inspection is first performed in the 1T1C mode, and if it is defective, the inspection is performed in the 2T2
Switch to C mode and perform inspection, and pass the 2T2
A non-defective product in the C mode can also be obtained.

Next, a method for testing a ferroelectric memory device according to a fourth embodiment of the present invention will be described. FIG. 6 shows a flowchart of this inspection method, and FIG. 7 shows the operation hysteresis characteristics of the ferroelectric capacitor.

As shown in FIG. 6, first, the power supply voltage V
DD = 5V, H data is written to the memory cell C0 of FIG. 1 in the 1T1C mode. As a result, in the hysteresis curve of FIG. 7, the ferroelectric capacitor changes from the state of H64 to the state of H61. Next, the power supply voltage VDD = 3
H data is written to the memory cell C1 in the V, 1T1C mode. As a result, in the hysteresis curve of FIG. 7, the ferroelectric capacitor changes from the state of L60 to the state of L61. Next, a read operation is performed in the 2T2C mode. Because H data is written with different power supply voltage,
The states of H61 and L61 are the initial states of H data and L data. These states have the same polarization direction. When a read operation is performed in the 2T2C mode from this state, Δ in FIG.
A read potential difference of V6 is obtained. This is smaller than the read potential difference ΔV5 of the third embodiment. For example, a ferroelectric capacitor having poor characteristics is removed by screening, and only a highly reliable device can be supplied.

The inspection method of this embodiment can be used not only for screening a ferroelectric capacitor having poor characteristics using an external inspection device, but also for providing a ferroelectric memory device with a self-inspection function. Can be applied. For example, if the mode shifts to the screening mode, the step-down power supply circuit is automatically activated to lower the internal power supply voltage,
Alternatively, the ferroelectric memory device may have a function of inspecting the memory cell with the cell plate voltage being lower than the power supply voltage.

Next, a method for testing a ferroelectric memory device according to a fifth embodiment of the present invention will be described. The fourth mentioned earlier
In the embodiment of FIG.
Data is written, but in this embodiment, L data is written. FIG. 8 shows the hysteresis characteristics of the ferroelectric capacitor in the inspection method according to the present embodiment. H81 and L
81 indicates an initial state, and these states have the same L-side polarization direction.

In this embodiment, a read potential difference ΔV8 different from that of the fourth embodiment is obtained, and inspection can be performed with an inspection margin suitable for each device. It should be noted that the self-test function according to the test method of this embodiment can be provided in the ferroelectric memory device. In addition, by combining this inspection method with the inspection method of the fourth embodiment, it is possible to screen the ferroelectric capacitor under a plurality of conditions.

Next, a method for testing a ferroelectric memory device according to a sixth embodiment of the present invention will be described. 4th and 5th
In this embodiment, both H data and L data are written by different voltages in the 1T1C mode, but in this embodiment, H data and L data are written by different voltages. FIG. 9 shows the hysteresis characteristics of the ferroelectric capacitor in the inspection method according to the present embodiment.

In this embodiment, unlike the fourth or fifth embodiment, the inspection can be performed with a margin of the read potential difference by a read method close to the normal operation of 2T2C.
H91 and L91 show the initial state, and these states have different polarization directions and different polarization magnitudes. ΔV in FIG.
9 is the read potential difference in this case. It should be noted that the self-test function according to the test method of this embodiment can be provided in the ferroelectric memory device.

[0043]

As described above, according to the present invention,
By switching the operation between the 1T1C type and the 2T2C type, it is possible to provide a ferroelectric memory device having both a stable operation at a low voltage and a high integration at a high voltage. In addition to performing the inspection in a short time, a highly reliable device can be supplied by the margin inspection of the ferroelectric memory capacitor.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a ferroelectric memory device according to a first embodiment of the present invention;

FIG. 2 is a circuit diagram of a control signal generation circuit of the ferroelectric memory device of FIG. 1;

FIG. 3 is a circuit diagram of a control signal generation circuit of a ferroelectric memory device according to a second embodiment of the present invention.

FIG. 4 is a flowchart of an inspection method for a ferroelectric memory device according to a third embodiment of the present invention;

FIG. 5 is a diagram showing hysteresis characteristics of a ferroelectric capacitor in the inspection method of FIG.

FIG. 6 is a flowchart of a method for testing a ferroelectric memory device according to a fourth embodiment of the present invention;

FIG. 7 is a hysteresis characteristic diagram of the ferroelectric capacitor in the inspection method of FIG.

FIG. 8 is a diagram showing a hysteresis characteristic of a ferroelectric capacitor in a method for testing a ferroelectric memory device according to a fifth embodiment of the present invention;

FIG. 9 is a diagram showing a hysteresis characteristic of a ferroelectric capacitor in a method for testing a ferroelectric memory device according to a sixth embodiment of the present invention;

[Explanation of symbols]

WL0-WL255 Word line DWL0, DWL1 Reference word line BL, / BL Bit line and its signal CP Cell plate electrode and its signal DCP Reference cell plate electrode and its signal BP Bit line precharge control signal SAE Sense amplifier control signal A7, / A7 Address signal MD Control signal VSS Ground voltage VDD Power supply voltage SA Sense amplifier C0 to C255 Main body memory cell capacitor DC0, DC1 Reference memory cell capacitor Qn0 to Qn255, QnD0, QnD1, QnBP
0, QnBP1, QnN channel type MOS transistor INV negation circuit F fuse

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Toshiyuki Honda 1-1, Kochi-cho, Takatsuki-shi, Osaka Prefecture Inside Matsushita Electronics Corporation (72) Inventor Joji Nakane 1-1, Kochi-cho, Takatsuki-shi, Osaka Matsushita (58) Field surveyed (Int.Cl. ⁷ , DB name) G11C 11/22 G11C 11/401 G11C 29/00

Claims (17)

(57) [Claims] A first ferroelectric capacitor connected to the first and second bit lines, the first ferroelectric capacitor being connected to the first bit line via a first memory cell transistor forming a main memory cell; A second ferroelectric capacitor connected to the second bit line through a second memory cell transistor forming a memory cell, and a third memory cell transistor forming a first reference memory cell A third ferroelectric capacitor connected to the second bit line, and a fourth ferroelectric capacitor connected to the first bit line via a fourth memory cell transistor forming a second reference memory cell. And a control circuit for controlling the gates of the first to fourth memory cell transistors, wherein the control circuit controls the first and second operation modes. Having a function, in the first operation mode, any one of a group including the first and third memory cell transistors and a group including the second and fourth memory cell transistors Controlling the gates of the respective transistors, and in the second operation mode,
A ferroelectric memory device that controls only one of the gates of the first and second memory cell transistors. 2. The ferroelectric memory device according to claim 1, wherein said first and second memory cells are arranged adjacent to each other. 3. The ferroelectric memory device according to claim 1, further comprising a voltage detection circuit, wherein switching between the first and second operation modes is performed by a detection signal from the voltage detection circuit. 4. The ferroelectric memory device according to claim 1, further comprising a function of performing a test in the first operation mode after performing a test in the second operation mode. 5. The ferroelectric memory device according to claim 4, further comprising a function of performing a read operation in said first operation mode after performing a write operation in said second operation mode. 6. The ferroelectric memory device according to claim 1, further comprising a function of performing an inspection in the first operation mode after the inspection in the second operation mode and passing the inspection. 7. Writing data to a first ferroelectric capacitor in the first operation mode using a first power supply voltage,
5. The ferroelectric device according to claim 4, having a function of writing data to a second ferroelectric capacitor in the first operation mode using a second power supply voltage, and thereafter reading data in the second operation mode. Memory device. 8. Writing H data to a first ferroelectric capacitor in the first operation mode using a first power supply voltage, and writing second data in the first operation mode using a second power supply voltage. 5. The ferroelectric memory device according to claim 4, having a function of writing H data to a ferroelectric capacitor and thereafter reading data in the second operation mode. 9. An L data is written to a first ferroelectric capacitor in the first operation mode using a first power supply voltage, and a second data is written in the first operation mode using a second power supply voltage. 5. The ferroelectric memory device according to claim 4, having a function of writing L data to a ferroelectric capacitor and subsequently reading data in the second operation mode. 10. H data is written to a first ferroelectric capacitor in the first operation mode using a first power supply voltage, and second data is written in the first operation mode using a second power supply voltage. 5. The ferroelectric memory device according to claim 4, having a function of writing L data to a ferroelectric capacitor and subsequently reading data in the second operation mode. 11. The inspection method according to claim 1, wherein the inspection is performed in the first operation mode after the inspection is performed in the second operation mode. 12. The inspection method according to claim 11, wherein a write operation is performed in the second operation mode, and then a read operation is performed in the first operation mode. 13. The inspection method for a ferroelectric memory device according to claim 1, wherein after inspecting in the second operation mode, an inspection in the first operation mode is performed on a pass product by the inspection. Inspection method. 14. The method for testing a ferroelectric memory device according to claim 1, wherein data is written to a first ferroelectric capacitor in the first operation mode using a first power supply voltage. An inspection method for writing data in a second ferroelectric capacitor in the first operation mode using the second power supply voltage, and thereafter reading data in the second operation mode. 15. The method for testing a ferroelectric memory device according to claim 1, wherein H data is written to the first ferroelectric capacitor in the first operation mode using a first power supply voltage. Writing H data to a second ferroelectric capacitor in the first operation mode using a second power supply voltage;
Then, an inspection method for reading data in the second operation mode. 16. The method for testing a ferroelectric memory device according to claim 1, wherein L data is stored in a first ferroelectric capacitor in an operation of the first operation mode using a first power supply voltage. And writing L data to the second ferroelectric capacitor in the first operation mode using the second power supply voltage, and then reading data in the second operation mode. 17. The method for testing a ferroelectric memory device according to claim 1, wherein H data is written to the first ferroelectric capacitor in the first operation mode using a first power supply voltage. Writing L data to a second ferroelectric capacitor in the first operation mode using a second power supply voltage;
Then, an inspection method for reading data in the second operation mode.