JP2005092978A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device which can perform a test for performing both read or write operation and refresh operation on each cycle by cycle basis. <P>SOLUTION: In a normal mode, this pseud SRAM performs the refresh operation in accordance with an output address signal RX for an address counter 16 in synchronization with an output clock signal REF of an oscillator 15. In a test mode, the device performs the refresh operation in accordance with an output address signal X of a row address buffer 3 responding to a rising edge of an external control signal/OE. A severe test can be, therefore, performed in which both the read or the write operation and the refresh operation are performed on the each cycle by cycle basis. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that requires data refresh.

  Conventionally, there are SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory) as semiconductor memories capable of rewriting data. In SRAM, data in the memory cell is not destroyed even if the standby state is kept for a long time, but in DRAM, data in the memory cell is destroyed unless the data in the memory cell is refreshed every predetermined time. However, the area of the SRAM memory cell is larger than the area of the DRAM memory cell, and the DRAM is superior to the SRAM for high integration at low cost. Therefore, the input / output of signals is the same as that of SRAM, and a semiconductor memory that uses DRAM memory cells and automatically performs a refresh operation instead of externally has been put into practical use. Such a semiconductor memory is called a pseudo SRAM.

In the conventional pseudo SRAM, the data in each memory cell is refreshed at a predetermined period in synchronization with the output clock signal of the internal oscillator. There is also a method of refreshing data each time a read / write operation is performed (see, for example, Patent Document 1).
JP 2002-150794 A

  In the conventional pseudo SRAM, the most severe condition is when both the read or write operation and the refresh operation are performed within one cycle. However, since the refresh operation is performed at the cycle of the output clock signal of the internal oscillator, It was not possible to conduct a rigorous test that performed both the read or write operation and the refresh operation every time.

  Therefore, a main object of the present invention is to provide a semiconductor memory device capable of performing a test for performing both a read or write operation and a refresh operation every cycle.

  In the semiconductor memory device according to the present invention, any one of the first and second clock signals having a predetermined first period is selectively input and responds to the first clock signal. A semiconductor memory device that performs a read operation and performs a write operation in response to a second clock signal, the memory array including a plurality of memory cells, and leading edges of each of the first and second clock signals In response to the first latch circuit, a first latch circuit that latches a first address signal applied from the outside, and a third clock having a predetermined second period longer than the predetermined first period An oscillator that generates a signal, a pulse counter of a third clock signal generated by the oscillator, an address counter that generates a second address signal based on the count value, and a first clock signal In response to the leading edge of the second clock signal, a reading circuit for reading data of the memory cell corresponding to the first address signal latched in the first latch circuit, and in response to the leading edge of the second clock signal, A write circuit for writing data in the memory cell corresponding to the first address signal latched in the first latch circuit, and an address counter in response to the leading edge of the third clock signal in the normal mode The memory cell data corresponding to the second address signal generated by the first address signal is refreshed, and in the test mode, the first clock signal and / or the second clock signal And a refresh circuit for refreshing data in the memory cell corresponding to the address signal No. 3.

  In the semiconductor memory device according to the present invention, in the normal mode, the refresh operation is performed in synchronization with the third clock signal generated by the oscillator, and in the test mode, the trailing edge of the first clock signal for reading and A refresh operation is performed in response to the trailing edge of the second clock signal for writing. Therefore, it is possible to perform a strict test that performs both the read or write operation and the refresh operation for each cycle.

[Embodiment 1]
FIG. 1 is a block diagram showing a configuration of a pseudo SRAM according to the first embodiment of the present invention. In FIG. 1, this pseudo SRAM includes a control clock generation circuit 1, a column address buffer 2, a row address buffer 3, a row decoder 4, a column decoder 5, a memory array 6, a sense amplifier + input / output control circuit 7, and 16 pieces. An input / output buffer 8 is provided.

  The control clock generation circuit 1 selects a predetermined operation mode based on control signals / CE, / OE, / WE, / LB, / UB given from the outside, and controls the entire pseudo SRAM. Column address buffer 2 latches externally applied address signals A0 to A6 at a predetermined timing, and supplies the latched address signals A0 to A6 to column decoder 5. Row address buffer 3 latches externally applied address signals A7 to A19 at a predetermined timing, and supplies the latched address signals A7 to A19 to row decoder 4.

  Memory array 6 includes a plurality of memory cells arranged in a matrix. Each memory cell stores 1-bit data. The plurality of memory cells are divided into a plurality of memory cell groups each including 16 memory cells. Each memory cell group is arranged at a predetermined address determined by a row address and a column address. Row decoder 4 designates the row address of memory array 6 in accordance with row address signals A 7 to A 19 provided from row address buffer 3. Column decoder 5 designates a column address of memory array 6 in accordance with column address signals A0 to A6 applied from column address buffer 2. Sense amplifier + input / output control circuit 7 reads, writes, and refreshes data in each memory cell in the address group specified by row decoder 4 and column decoder 5.

  Of the 16 input / output buffers 8, the eight input / output buffers 8 corresponding to the lower bit data signals DQ0 to DQ7 are activated by the signal LC, and the eight input / output buffers corresponding to the upper bit data signals DQ8 to DQ15 are activated. The buffer 8 is activated by the signal UC. Input / output buffer 8 supplies data D input from the outside to the selected memory cell via sense amplifier + input / output control circuit 7 in response to a control signal / OE supplied from the outside during a write operation. Input / output buffer 8 outputs data Q read out from the selected memory cell by sense amplifier + input / output control circuit 7 in response to a control signal / OE input from the outside during a read operation. .

  FIG. 2 is a circuit block diagram showing a main part of the pseudo SRAM shown in FIG. In FIG. 2, only the portion corresponding to the 1-bit data signal DQ is shown. In FIG. 2, the memory array 6 includes a plurality of memory cells MC arranged in a matrix, word lines WL provided corresponding to each row, and bit line pairs BL, / provided corresponding to each column. BL. Each memory cell MC is a well-known one including an N channel MOS transistor for access and a capacitor for information storage. The word line WL transmits the output of the row decoder 4 and activates the memory cell MC in the selected row. Bit line pair BL, / BL inputs / outputs a data signal to / from selected memory cell MC.

  Sense amplifier + input / output control circuit 7 includes a data input / output line pair IO, / IO, a column selection gate 11, a sense amplifier 12 and an equalizer 13 provided corresponding to each column. The data input / output line pair IO, / IO is connected to one input / output buffer 8. Column select gate 11 includes a pair of N channel MOS transistors connected between bit line pair BL, / BL and data input / output line pair IO, / IO. The gates of a pair of N channel MOS transistors of each column selection gate 11 are connected to the column decoder 5 via a column selection line CSL. When column select line CSL is raised to "H" level of the selection level by column decoder 5, a pair of N channel MOS transistors are turned on, and bit line pair BL, / BL and data input / output line pair IO, / IO Are combined.

  Sense amplifier 12 amplifies a minute potential difference between bit line pair BL and / BL to power supply voltage VCC in response to sense amplifier activation signals SE and / SE being set to “H” level and “L” level, respectively. To do. The equalizer 13 equalizes the potential of the bit line pair BL, / BL to the bit line potential VBL (= VCC / 2) in response to the bit equalize signal BLEQ being set to the activation level “H” level.

  Next, the operation of the pseudo SRAM shown in FIGS. 1 and 2 will be described. During the write operation, the column decoder 5 raises the column selection line CSL of the column corresponding to the column address signals A0 to A6 to the “H” level of the selection level, and the column selection gate 11 of that column is turned on.

  In response to signal / WE, input / output buffer 8 applies external write data D to selected bit line pair BL, / BL via data input / output line pair IO, / IO. Write data D is given as a potential difference between bit line pair BL, / BL. Next, the row decoder 4 raises the word line WL of the row corresponding to the row address signals A7 to A19 to the “H” level of the selection level, and the N channel MOS transistor of the memory cell MC of that row is turned on. The capacitor of the selected memory cell MC stores an amount of charge corresponding to the potential of the bit line BL or / BL. Since the electric charge of the capacitor gradually leaks, it is necessary to rewrite (refresh) data in a predetermined cycle.

  In the refresh operation, first, the bit line equalize signal BLEQ falls to the “L” level, and the equalization of the bit line pair BL, / BL is stopped. Next, the row decoder 4 raises the word line WL of the row corresponding to the refresh address signals A7 to A19 (which will be described later) to the “H” level of the selection level, and the N channel MOS transistor of the memory cell MC of that row Is conducted. As a result, the potential of the bit line pair BL, / BL changes by a minute amount according to the charge amount of the capacitor of the activated memory cell MC.

  Then, sense amplifier activation signals SE and / SE are set to “H” level and “L” level, respectively, and sense amplifier 12 is activated. When the potential of the bit line BL is slightly higher than the potential of the bit line / BL, the potential of the bit line BL is pulled up to the “H” level (power supply potential VCC), and the potential of the bit line / BL is set to the “L” level. Pulled down to (ground potential GND). Conversely, when the potential of the bit line / BL is slightly higher than the potential of the bit line BL, the potential of the bit line / BL is pulled up to the “H” level and the potential of the bit line BL is pulled down to the “L” level. It is done. As a result, the data in each memory cell MC in the row corresponding to the refresh address signals A7 to A19 is refreshed.

  In a read operation, first, bit line equalize signal BLEQ is lowered to "L" level, and equalization of bit line pair BL, / BL is stopped. Next, the row decoder 4 raises the word line WL in the row corresponding to the row address signals A7 to A19 to the "H" level of the selection level, and the N channel MOS transistor of the memory cell MC in that row is turned on. As a result, the potential of the bit line pair BL, / BL changes by a minute amount according to the charge amount of the capacitor of the activated memory cell MC.

  Then, sense amplifier activation signals SE and / SE are set to “H” level and “L” level, respectively, and sense amplifier 12 is activated. When the potential of the bit line BL is higher by a minute amount than the potential of the bit line / BL, the potential of the bit line BL is raised to the “H” level and the potential of the bit line / BL is lowered to the “L” level. Conversely, when the potential of the bit line / BL is slightly higher than the potential of the bit line BL, the potential of the bit line / BL is pulled up to the “H” level and the potential of the bit line BL is pulled down to the “L” level. It is done. Next, the column selection line CSL of the column corresponding to the column address signals A0 to A6 is raised to the “H” level of the selection level by the column decoder 5, and the column selection gate 11 of that column is turned on. Data of the bit line pair BL, / BL of the selected column is applied to the input / output buffer 8 via the column selection gate 11 and the data input / output line pair IO, / IO. Input / output buffer 8 outputs read data Q to the outside in response to signal / OE.

  Hereinafter, the refresh operation which is a feature of the pseudo SRAM will be described in more detail. FIG. 3 is a block diagram showing a portion related to generation of the refresh address signal RX = A7 to A19. In FIG. 3, the pseudo SRAM includes an oscillator 15, an address counter 16, and a selector 17 in addition to the row address buffer 3 and the row decoder 4. The oscillator 15 outputs a clock signal REF having a predetermined period. The address counter 16 counts the number of pulses of the clock signal REF and outputs the count value as the refresh address signal RX = A7 to A16.

  The selector 17 receives the refresh address signal RX = A7 to A16 output from the address counter 16 and the row address signal X = A7 to A16 output from the row address buffer 3, and receives the internal control signal φS and the test signal TE. Be controlled. Internal control signal φS is set to “H” level during a refresh operation, and is set to “L” level during a read operation and a write operation. Test signal TE is set to “H” level in the test mode, and is set to “L” level in the normal mode. Selector 17 provides refresh address signal RX to row decoder 4 when signals φS and TE are at “H” level and “L” level, respectively, and row address signal X when signals φS and TE are both at “L” level. Is supplied to the row decoder 4, and when the signal TE is at "H" level, the row address signal X is supplied to the row decoder 4 regardless of the signal φS. The row decoder 4 selects any one of the plurality of word lines WL according to the address signals A7 to A16 supplied through the selector 17, and selects the selected word line WL as the “H” level of the selection level. To.

  FIG. 4 is a circuit block diagram showing a part related to control of the refresh operation. 4, the pseudo SRAM includes a word driver control circuit 20, a one-shot pulse generation circuit 21, a flip-flop 22, a TREFE generation circuit 23, a selector 24, an AND gate 25, a refresh control, in addition to the oscillator 15 shown in FIG. A circuit 26 and a delay circuit 27 are provided.

  The word driver control circuit 20 sets the word line activation signal WLE to the “H” level of the activation level in response to the external control signals / OE, / WE being set to the “L” level of the activation level. The one-shot pulse generation circuit 21 generates the signal PWLE in a pulse-like manner as “H” in response to the word line activation signal falling from the activation level “H” level to the deactivation level “L” level. To the level. Signal PWLE is applied to one input node of AND gate 25.

  The oscillator 15 is the same as that shown in FIG. 3, and outputs a clock signal REF having a predetermined period. The flip-flop 22 is set in response to the clock signal REF being raised to the “L” level or the “H” level to raise the signal REFE from the “L” level to the “H” level, and the signal REFTGD is “ In response to the rise from the “L” level to the “H” level, the signal REFE is lowered from the “H” level to the “L” level. The REFE generation circuit 23 outputs a signal TREFE. TREFE generating circuit 23 includes an output node 23a receiving power supply potential VCC as shown in FIG. Therefore, signal TREFE is fixed at “H” level (power supply potential VCC).

  The selector 24 receives the output signal REFE of the flip-flop 22 and the output signal TREFE of the TREFE generating circuit 23, and is controlled by the test signal TE. Test signal TE is a signal which is set to “L” level in the normal mode and is set to “H” level in the test mode. Selector 24 provides signal REFE to the other input node of AND gate 25 when test signal TE is at “L” level, and signal TREFE to the other input node of AND gate 25 when test signal TE is at “H” level. give.

  A refresh trigger signal REFTG, which is an output signal of the AND gate 25, is delayed by a delay circuit 27 to become a signal REFTGD and is given to the refresh control circuit 26. The refresh control circuit 26 controls the entire pseudo SRAM in response to the refresh trigger signal REFTG being pulsed to the “H” level to refresh the data in the memory cells.

  FIG. 6 is a time chart showing a read operation and a refresh operation in the normal mode of the pseudo SRAM. In FIG. 6, an output enable signal / OE is a clock signal that is lowered to the “L” level of the activation level by a predetermined time in a predetermined cycle. The output clock signal REF of the oscillator 15 is raised to the “H” level in a pulse manner at a predetermined refresh cycle. The refresh cycle is longer than the cycle of signal / OE.

  When signal / OE falls from "H" level to "L" level at time t0, address signal X0 is latched by row address buffer 3 and address signals A0 to A6 are latched by column address buffer 2 and read. Operation is performed. At this time, the output address signal X0 of the row address buffer 3 is supplied to the row decoder 4 via the selector 17. In addition, the word line activation signal WLE is raised to the activation level “H” level by the word driver control circuit 20, and the word line WL in the row corresponding to the address signal X0 is selected by the word driver in the row decoder 4. To “H” level.

  When clock signal REF is raised to "H" level in a pulse manner, flip-flop 22 is set and signal REFE is raised to "H" level. At this time, since the test signal TE is at the “L” level, the signal REFE is applied to the other input node of the AND gate 25 via the selector 24.

  When signal / OE rises from “L” level to “H” level at time t1, signal WLE falls from “H” level to “L” level, and signal PWLE is pulsed to “H” level. The refresh trigger signal TEFTG is raised to “H” level in a pulsed manner. When signal TEFTG is raised to "H" level in a pulse manner, delay circuit 27 raises signal TEFTGD to "H" level in a pulse manner, flip-flop 22 is reset, and signal REFE is changed from "H" level. Lowered to “L” level.

  When refresh trigger signal REFTG is pulsedly raised to “H” level, refresh operation is performed by refresh control circuit 26. At this time, the output address signal RX0 of the address counter 16 is applied to the row decoder 4 via the selector 17, and the data in each memory cell MC in the row corresponding to the address signal RX0 is refreshed.

  Next, when external control signal / OE falls from "H" level to "L" level at time t2, a read operation is performed following the refresh operation. At this time, the output address signal X1 of the row address buffer 3 is applied to the row decoder 4 via the selector 17. In this read cycle, the signal REF remains unchanged at the “L” level. The same applies hereinafter. During this time, the chip enable signal / CE is set to the activation level “L” to activate the pseudo SRAM, and both the lower bit selection signal / LB and the upper bit selection signal / UB are at the activation level “L”. The 16 data signals Q0 to Q16 are read out and the write enable signal / WE is fixed to the "H" level of the inactivation level.

  FIG. 7 is a time chart showing a write operation and a refresh operation in the normal mode of the pseudo SRAM. Referring to FIG. 7, FIG. 7 is different from FIG. 6 in that the signal / WE and the signal / OE are interchanged, and a write operation is performed instead of the read operation. The write enable signal / WE is a clock signal that is lowered to the “L” level of the activation level by a predetermined time at a predetermined cycle. The output clock signal REF of the oscillator 15 is raised to the “H” level in a pulse manner at a predetermined refresh cycle. The refresh cycle is longer than the cycle of the signal / WE.

  Write operation is performed when signal / WE falls from "H" level to "L" level at time t0, and refresh operation is performed when signal / WE is raised from "L" level to "H" level at time t1. When signal / WE falls from "H" level to "L" level at time t2, a write operation is performed.

  FIG. 8 is a time chart showing the operation of the pseudo SRAM in the test mode. In FIG. 8, the output enable signal / OE is lowered to the “L” level of the activation level by a predetermined time in a predetermined cycle. When the test mode is set, the test signal TE is set to the “H” level, the selector 17 in FIG. 3 applies the output address signal X of the row address buffer 3 to the row decoder 4 regardless of the signal φS, and the selector 24 in FIG. Supplies the output signal TREFE of the TREFE generating circuit 23 to the other input node of the AND gate 25. Since the signal TREFE is fixed at the “H” level, the output signal PWLE of the one-shot pulse generation circuit 21 passes through the AND gate 25 and becomes the refresh trigger signal REFTG.

  When signal / OE falls from "H" level to "L" level at time t0, row signal buffer 3 latches address signal X0, and a read operation is performed based on address signal X0. Next, when signal / OE rises from "L" level to "H" level at time t1, refresh trigger signal REFTG shown in FIGS. 4 to 7 is pulsed to "H" level, and row address buffer 3 A refresh operation is performed on the basis of the address signal X0 latched at the same time.

  Next, when signal / OE falls from "H" level to "L" level at time t2, address signal X1 is latched by row address buffer 3, and a read operation is performed based on address signal X1. Next, when the signal / OE is raised from the “L” level to the “H” level at time t3, the output signal of the selector 24 is fixed to the “H” level, so that the refresh trigger signal REFTG is “H” in a pulsed manner. The refresh operation is performed based on the address signal X1 which is set to the level and latched in the row address buffer 3.

  As described above, in the pseudo SRAM, the refresh operation and the read operation are performed every read cycle in the test mode. As shown in FIG. 9, when the signal / OE is fixed at the “H” level and the signal / WE is set at the “L” level for a predetermined time in a predetermined cycle, the refresh operation and the write operation are performed every write cycle. Done. As shown in FIG. 10, when the signals / OE and / WE are alternately lowered to the “L” level of the activation level one cycle at a time, the refresh operation and the read operation are performed every read cycle. A refresh operation and a write operation are performed every write cycle. Pseudo SRAMs that operate normally even if read, write, and refresh are performed under such severe conditions are shipped as products, and pseudo SRAMs that do not operate normally are discarded as defective products.

  In the first embodiment, both the refresh operation and the read operation can be performed for each read cycle in the test mode, and both the refresh operation and the write operation can be performed for each write cycle. Can be tested. Therefore, it is possible to efficiently test whether the pseudo SRAM is normal in a short time.

  In the test mode, since the read operation is performed based on the output address signal X of the row address buffer 3 instead of the output address signal RX of the address counter 16, an address signal for refresh operation and an address signal for read or write operation are generated. Any combination can be used. Therefore, it is possible to test under the most severe conditions from this point.

[Embodiment 2]
FIG. 11 is a circuit block diagram showing a main part of the pseudo SRAM according to the second embodiment of the present invention. Referring to FIG. 11, this pseudo SRAM is different from the pseudo SRAM of the first embodiment in that TREFE generation circuit 23 is replaced with TREFE generation circuit 30. TREFE generation circuit 30 includes one-shot pulse generation circuits 31 and 32 and a flip-flop 33.

  One shot pulse generation circuit 31 raises signal φ31 to “H” level in a pulse manner in response to signal / OE being raised from “H” level to “L” level. One shot pulse generation circuit 32 raises signal φ32 to “H” level in a pulse manner in response to signal / WE falling from “H” level to “L” level. The flip-flop 33 is set in response to the signal φ31 being pulsed to the “H” level to raise the signal TREFE from the “L” level to the “H” level, and the signal φ32 is pulsed to the “H” level. The signal TREFE is reset from the “H” level to the “L” level by being reset in response to the change to the level.

  FIG. 12 is a time chart showing the operation of the pseudo SRAM in the test mode. In FIG. 12, when signal / OE falls from "H" level to "L" level at time t0, flip-flop 33 is set and signal TREFE is raised from "L" level to "H" level. The address signal X0 is latched by the row address buffer 3, and a read operation is performed based on the address signal X0. Next, when the signal / OE is raised from the “L” level to the “H” level at time t1, the output signal of the selector 24 is set to the “H” level, so that the refresh trigger signal REFTG is pulsed to the “H” level. The refresh operation is performed based on the address signal X0 latched in the row address buffer 3.

  Next, when signal / OE falls from "H" level to "L" level at time t2, address signal X1 is latched by row address buffer 3, and a read operation is performed based on address signal X1. Next, when the signal / OE rises from the “L” level to the “H” level at the time t3, the output signal of the selector 24, that is, the signal TREFE is set to the “H” level, so the refresh trigger signal REFTG is “ The refresh operation is performed based on the address signal X 1 which is set to the “H” level and latched in the row address buffer 3.

  Next, at time t4, when signal / WE falls from "H" level to "L" level, flip-flop 33 is reset and signal TREFE falls from "H" level to "L" level. Address signal X2 is latched in address buffer 3, and a write operation is performed based on address signal X2. Next, when signal / WE is raised from "L" level to "H" level at time t5, output signal PWLE of one-shot pulse generation circuit 21 in FIG. 4 is pulsed to "H" level. Since the output signal of the selector 24 is at the “L” level, the refresh trigger signal REFTG remains at the “L” level and no refresh operation is performed.

  Next, at time t6, when signal / OE falls from "H" level to "L" level, flip-flop 33 is set and signal TREFE is raised from "L" level to "H" level. Address signal X3 is latched by address buffer 3, and a read operation is performed based on address signal X3.

  In the second embodiment, both the refresh operation and the read operation can be performed for each read cycle in the test mode, and the pseudo SRAM can be tested under severe conditions.

  FIG. 13 is a circuit block diagram showing a modification of the second embodiment. In FIG. 13, the TREFE generating circuit 34 is different from the TREFE generating circuit 30 in FIG. 11 in that signals / WE and / OE are input to the one-shot pulse generating circuits 31 and 32, respectively. When signal / WE falls from "H" level to "L" level, flip-flop 33 is set and signal TREFE is raised from "L" level to "H" level. When signal / OE rises from “H” level to “L” level, flip-flop 33 is reset and signal TREFE falls from “H” level to “L” level.

  FIG. 14 is a time chart showing an operation in the test mode of the pseudo SRAM including the TREFE generation circuit 34 shown in FIG. When signal / WE falls to "L" level at time t0, flip-flop 33 is set, signal TREFE is raised to "H" level, and a write operation is performed. When signal / WE rises to "H" level at time t1, refresh operation is performed because signal TREFE is set to "H" level. Write operation is performed when signal / WE falls to "L" level at time t2, and signal TREFE is set to "H" level when signal / WE is raised to "H" level at time t3. A refresh operation is performed. When signal / OE falls to "L" level at time t4, flip-flop 33 is reset, signal TREFE falls to "L" level, and a read operation is performed. Even if signal / OE rises to "H" level at time t5, refresh operation is not performed because signal TREFE is set to "L" level.

  In this modified example, both the refresh operation and the write operation can be performed for each write cycle in the test mode, and the pseudo SRAM can be tested under severe conditions.

[Embodiment 3]
FIG. 15 is a circuit block diagram showing a main part of the pseudo SRAM according to the third embodiment of the present invention. Referring to FIG. 15, this pseudo SRAM is different from the pseudo SRAM of the first embodiment in that TREFE generating circuit 23 is replaced with TREFE generating circuit 35 and that a switch 38 is added. .

  An output node 35a of the TREFE generation circuit 35 is connected to a signal input terminal 36 for chip enable signal / CE. Input buffer 37 transmits a signal / CE supplied from the outside via signal input terminal 36 to control clock generation circuit 1. One switching terminal 38a of switch 38 receives the output signal of input buffer 37, the other switching terminal 38b receives ground potential GND, and its common terminal 38c is connected to control clock generating circuit 1. The signal appearing at the common terminal 38c of the switch 38 becomes the internal chip enable signal ZCE. When the signal ZCE is set to the “L” level of the activation level, the pseudo SRAM is activated.

  In the normal mode, the terminals 38a and 38c of the switch 38 become conductive, and the signal / CE is applied to the control clock generation circuit 1 through the input buffer 37 and the switch 38. In the test mode, the terminals 38b and 38c of the switch 38 become conductive, the signal ZCE is set to the “L” level (ground potential GND), and the pseudo SRAM is fixed to the activated state.

  FIG. 16 is a time chart showing the operation of the pseudo SRAM described in FIG. 15 in the test mode. In this pseudo SRAM, the logic level of the signal TREFE can be arbitrarily set from the signal input terminal 36 for the signal / CE. FIG. 16 shows a case where the signal TREFE is set to “H” level at times t0 to t4 and is set to “L” level at times t4 to t6. At time t1 and t3, since signal TREFE is at "H" level, a refresh operation is performed in response to the rising edge of signal / OE. At time t5, since signal TREFE is at "L" level, no refresh operation is performed in response to the rising edge of signal / OE.

[Embodiment 4]
FIG. 17 is a block diagram showing the main part of the pseudo SRAM according to the fourth embodiment of the present invention, which is compared with FIG. Referring to FIG. 17, this pseudo SRAM is different from the pseudo SRAM of the first embodiment in that an address generation circuit 40 is added and selector 17 is replaced with selector 41.

  The address generation circuit 40 outputs an address signal X + n obtained by shifting the output address signal X = A7 to A19 of the row address buffer 3 by a predetermined value n. n is a 13-bit number in binary.

  The selector 41 receives the output address signal RX of the address counter 16, the output address signal X of the row address buffer 3, and the output address signal X + n of the address generation circuit 40, and is controlled by signals φS and TE. Signal φS is set to “H” level during a refresh operation, and is set to “L” level during a read operation and a write operation. Test signal TE is set to “H” level in the test mode, and is set to “L” level in the normal mode.

  Selector 41 provides address signal X to row decoder 4 when both signals φS and TE are at “L” level, and row address signal RX when signals φS and TE are at “H” level and “L” level, respectively. When the signals φS and TE are at “L” level and “H” level, respectively, the address signal X is applied to the row decoder 4. When the signals φS and TE are both at “H” level, the address signal x + n is applied. This is given to the row decoder 4.

  FIG. 18 is a time chart showing the operation of the pseudo SRAM described in FIG. 17 in the test mode. In the test mode, the output signal of the selector 24 in FIG. 4, that is, the signal TREFE is fixed at the “H” level. When signal / OE falls to "L" level at time t0, address signal X0 is latched by row address buffer 3, a read operation is performed based on address signal X0, and address signal is sent from address generating circuit 40. X0 + n is output. When signal / OE rises to “H” level at time t1, refresh operation is performed based on output address signal X0 + n of address generation circuit 40.

  In the fourth embodiment, refresh can be performed with an address different from the previous read address or write address.

  A plurality of address generation circuits having different shift amounts n may be provided, and an output address signal from any one of these address generation circuits may be selected and supplied to the row decoder 4.

[Embodiment 5]
FIG. 19 is a block diagram showing the main part of the pseudo SRAM according to the fifth embodiment of the present invention, which is compared with FIG. Referring to FIG. 17, this pseudo SRAM is different from the pseudo SRAM of the fifth embodiment in that address generation circuit 40 is replaced with a row address buffer 42.

  Address buffer 42 latches address signals TRX = A7 to A19 in response to rising edges of signals / OE and / WE, and provides latched address signal TRX to selector 41. The selector 41 receives the output address signal RX of the address counter 16, the output address signal X of the row address buffer 3, and the output address signal TRX of the row address buffer 42, and is controlled by signals φS and TE.

  Selector 41 provides address signal X to row decoder 4 when both signals φS and TE are at “L” level, and row address signal RX when signals φS and TE are at “H” level and “L” level, respectively. When the signals φS and TE are at “L” level and “H” level, respectively, the address signal X is applied to the row decoder 4. When the signals φS and TE are both at “H” level, the address signal TRX is applied. This is given to the row decoder 4.

  FIG. 20 is a time chart showing the operation of the pseudo SRAM described in FIG. 19 in the test mode. In the test mode, the output signal of the selector 24 in FIG. 4, that is, the signal TREFE is fixed at the “H” level. When signal / OE falls to "L" level at time t0, address signal X0 is latched by row address buffer 3, and a read operation is performed based on address signal X0. When signal / OE rises to "H" level at time t1, address signal TRX0 is latched by row address buffer 42, and a refresh operation is performed based on address signal TRX0.

  In the fifth embodiment, refresh can be performed with an address unrelated to the previous read address or write address.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a block diagram showing an overall configuration of a pseudo SRAM according to a first embodiment of the present invention. FIG. 2 is a circuit block diagram showing a configuration of a memory array and a sense amplifier + input / output control circuit shown in FIG. 1. FIG. 2 is a block diagram showing a configuration of a portion related to a refresh operation of the pseudo SRAM shown in FIG. 1. FIG. 10 is another circuit block diagram showing a portion related to the refresh operation of the pseudo SRAM shown in FIG. 1. FIG. 5 is a circuit diagram showing a configuration of a TREFE generation circuit shown in FIG. 4. 6 is a time chart showing a read operation and a refresh operation in the normal mode of the pseudo SRAM shown in FIGS. 6 is a time chart showing a write operation and a refresh operation in the normal mode of the pseudo SRAM shown in FIGS. 6 is a time chart showing a read operation and a refresh operation in the test mode of the pseudo SRAM shown in FIGS. 6 is a time chart showing a write operation and a refresh operation in the test mode of the pseudo SRAM shown in FIGS. 6 is a time chart showing a read operation, a write operation, and a refresh operation in the test mode of the pseudo SRAM shown in FIGS. It is a circuit block diagram which shows the structure of the TREFE generating circuit of pseudo SRAM by Embodiment 2 of this invention. 12 is a time chart showing a read operation, a write operation, and a refresh operation in the test mode of the pseudo SRAM described in FIG. FIG. 10 is a circuit block diagram showing a modification of the second embodiment. 14 is a time chart showing a write operation, a read operation, and a refresh operation in the test mode of the pseudo SRAM described in FIG. It is a circuit block diagram which shows the principal part of pseudo SRAM by Embodiment 3 of this invention. 16 is a time chart showing a read operation and a refresh operation in the test mode of the pseudo SRAM described in FIG. It is a block diagram which shows the principal part of pseudo SRAM by Embodiment 4 of this invention. 18 is a time chart showing a read operation and a refresh operation in the test mode of the pseudo SRAM described with reference to FIG. It is a block diagram which shows the principal part of pseudo SRAM by Embodiment 5 of this invention. 20 is a time chart showing a read operation and a refresh operation in the test mode of the pseudo SRAM described in FIG.

Explanation of symbols

  1 control clock generation circuit, 2 column address buffer, 3, 42 row address buffer, 4 row decoder, 5 column decoder, 6 memory array, 7 sense amplifier + input / output control circuit, 8 input / output buffer, 11 column select gate, 12 Sense amplifier, 13 equalizer, MC memory cell, WL word line, BL, / BL bit line pair, 15 oscillator, 16 address counter, 17, 24, 41 selector, 20 word driver control circuit, 21, 31, 32 one-shot pulse Generating circuit, 22, 33 flip-flop, 23, 30, 34, 35 TREFE generating circuit, 25 AND gate, 26 refresh control circuit, 36 signal input terminal, 37 input buffer, 38 switch, 40 address generating circuit.

Claims (9)

One of the first and second clock signals having a predetermined first period is selectively input, and a read operation is performed in response to the first clock signal. A semiconductor memory device that performs a write operation in response to a clock signal of 2,
A memory array including a plurality of memory cells;
A first latch circuit for latching a first address signal applied from the outside in response to a leading edge of each of the first and second clock signals;
An oscillator for generating a third clock signal having a predetermined second period longer than the predetermined first period;
An address counter that counts the number of pulses of the third clock signal generated by the oscillator and generates a second address signal based on the count value;
A read circuit for reading data of a memory cell corresponding to a first address signal latched in the first latch circuit in response to a leading edge of the first clock signal;
A write circuit for writing data of a memory cell corresponding to the first address signal latched in the first latch circuit in response to the leading edge of the second clock signal; In response to the leading edge of the third clock signal, the memory cell data corresponding to the second address signal generated by the address counter is refreshed. In the test mode, after the first clock signal A semiconductor memory device comprising: a refresh circuit for refreshing data of a memory cell corresponding to a third address signal in response to an edge and / or a trailing edge of the second clock signal. The refresh circuit includes:
A flip-flop that is set by the leading edge of the third clock signal generated by the oscillator and whose output signal changes from a first potential to a second potential;
A first signal generating circuit for outputting a signal of the second potential;
A first selector that selects an output signal of the flip-flop in the normal mode, and an output signal of the first signal generation circuit in the test mode;
A second signal that is activated when the signal selected by the first selector is the second potential and outputs a refresh trigger signal in response to the trailing edge of each of the first and second clock signals. And a refresh execution circuit for refreshing data in the memory cell in response to the refresh trigger signal,
The semiconductor memory device according to claim 1, wherein the flip-flop is reset by the refresh trigger signal, and an output signal thereof changes from the second potential to the first potential. The refresh circuit includes:
A first flip-flop that is set by a leading edge of a third clock signal generated by the oscillator and whose output signal changes from a first potential to a second potential;
Set by the leading edge of the first clock signal to change its output signal from the first potential to the second potential and reset by the leading edge of the second clock signal to A second flip-flop that changes from a second potential to the first potential;
A first selector that selects an output signal of the first flip-flop in the normal mode, and an output signal of the second flip-flop in the test mode;
Signal generation that is activated when the signal selected by the first selector is the second potential and outputs a refresh trigger signal in response to the trailing edge of each of the first and second clock signals A refresh execution circuit for refreshing data in the memory cell in response to the refresh trigger signal,
2. The semiconductor memory device according to claim 1, wherein the first flip-flop is reset by the refresh trigger signal, and its output signal changes from the second potential to the first potential. The refresh circuit includes:
A first flip-flop that is set by a leading edge of a third clock signal generated by the oscillator and whose output signal changes from a first potential to a second potential;
Set by the leading edge of the second clock signal and its output signal changes from the first potential to the second potential and reset by the leading edge of the first clock signal and the output signal becomes A second flip-flop that changes from a second potential to the first potential;
A first selector that selects an output signal of the first flip-flop in the normal mode, and an output signal of the second flip-flop in the test mode;
Signal generation that is activated when the signal selected by the first selector is the second potential and outputs a refresh trigger signal in response to the trailing edge of each of the first and second clock signals A refresh execution circuit for refreshing data in the memory cell in response to the refresh trigger signal,
2. The semiconductor memory device according to claim 1, wherein the first flip-flop is reset by the refresh trigger signal, and its output signal changes from the second potential to the first potential. The refresh circuit includes:
A flip-flop that is set by the leading edge of the third clock signal generated by the oscillator and whose output signal changes from a first potential to a second potential;
An external terminal to which one of the signal of the first potential and the signal of the second potential is selectively given in the test mode;
A first selector that selects an output signal of the flip-flop in the normal mode and a signal applied to the external terminal in the test mode;
Signal generation that is activated when the signal selected by the first selector is the second potential and outputs a refresh trigger signal in response to the trailing edge of each of the first and second clock signals A refresh execution circuit for refreshing data in the memory cell in response to the refresh trigger signal,
The semiconductor memory device according to claim 1, wherein the flip-flop is reset by the refresh trigger signal, and an output signal thereof changes from the second potential to the first potential. The external terminal receives an external control signal in the normal mode,
The semiconductor memory device
The apparatus further comprises: an input buffer that generates an internal control signal in response to an external control signal given through the external terminal; and a switch that sets the internal control signal to a predetermined level during the test mode. The semiconductor memory device described. The third address signal is a first address signal latched in the first latch circuit;
The semiconductor memory device
Further, the first address signal latched in the first latch circuit is selected in response to the leading edge of each of the first and second clock signals, and the third clock signal is selected in the normal mode. The second address signal generated by the address counter is selected in response to the leading edge of the first clock signal and / or the trailing edge of the second clock signal in the test mode. In response to the second selector, a second selector that selects the first address signal latched by the first latch circuit, and the plurality of the first address signal selected by the second selector A decoder for selecting any one of the memory cells;
The read circuit reads data from a memory cell selected by the decoder,
The write circuit writes data in a memory cell selected by the decoder;
The semiconductor memory device according to claim 1, wherein the refresh circuit refreshes data of a memory cell selected by the decoder. An address generation circuit configured to generate the third address signal different from the first address signal based on the first address signal latched by the first latch circuit;
In response to the leading edge of each of the first and second clock signals, the first address signal latched in the first latch circuit is selected, and the front of the third clock signal is selected in the normal mode. In response to an edge, selects a second address signal generated by the address counter and responds to the trailing edge of the first clock signal and / or the trailing edge of the second clock signal during the test mode. A second selector for selecting the third address signal generated by the address generation circuit; and the plurality of the plurality of the first address signal selected by the second selector according to the first, second and third address signals. A decoder for selecting any one of the memory cells;
The read circuit reads data from a memory cell selected by the decoder,
The write circuit writes data in a memory cell selected by the decoder;
The semiconductor memory device according to claim 1, wherein the refresh circuit refreshes data of a memory cell selected by the decoder. A second latch circuit for latching the third address signal applied from the outside in response to a trailing edge of each of the first and second clock signals;
In response to the leading edge of each of the first and second clock signals, the first address signal latched in the first latch circuit is selected, and the front of the third clock signal is selected in the normal mode. In response to an edge, selects a second address signal generated by the address counter and responds to the trailing edge of the first clock signal and / or the trailing edge of the second clock signal during the test mode. And a second selector for selecting the third address signal latched by the second latch circuit, and the first, second and third address signals selected by the second selector. A decoder for selecting any one of the plurality of memory cells;
The read circuit reads data from a memory cell selected by the decoder,
The write circuit writes data in a memory cell selected by the decoder;
The semiconductor memory device according to claim 1, wherein the refresh circuit refreshes data of a memory cell selected by the decoder.

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