DE69424771T2 - Anordnung zum Lesen einer Speicherzellenmatrix - Google Patents

Anordnung zum Lesen einer Speicherzellenmatrix

Info

Publication number
DE69424771T2
DE69424771T2 DE69424771T DE69424771T DE69424771T2 DE 69424771 T2 DE69424771 T2 DE 69424771T2 DE 69424771 T DE69424771 T DE 69424771T DE 69424771 T DE69424771 T DE 69424771T DE 69424771 T2 DE69424771 T2 DE 69424771T2
Authority
DE
Germany
Prior art keywords
reading
arrangement
memory cell
cell matrix
matrix
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69424771T
Other languages
English (en)
Other versions
DE69424771D1 (de
Inventor
Carla Maria Golla
Marco Olivo
Silvia Padoan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Publication of DE69424771D1 publication Critical patent/DE69424771D1/de
Application granted granted Critical
Publication of DE69424771T2 publication Critical patent/DE69424771T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/14—Dummy cell management; Sense reference voltage generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
DE69424771T 1994-03-22 1994-03-22 Anordnung zum Lesen einer Speicherzellenmatrix Expired - Fee Related DE69424771T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP94830124A EP0678871B1 (de) 1994-03-22 1994-03-22 Anordnung zum Lesen einer Speicherzellenmatrix

Publications (2)

Publication Number Publication Date
DE69424771D1 DE69424771D1 (de) 2000-07-06
DE69424771T2 true DE69424771T2 (de) 2000-10-26

Family

ID=8218402

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69424771T Expired - Fee Related DE69424771T2 (de) 1994-03-22 1994-03-22 Anordnung zum Lesen einer Speicherzellenmatrix

Country Status (4)

Country Link
US (1) US5627790A (de)
EP (1) EP0678871B1 (de)
JP (1) JP3198027B2 (de)
DE (1) DE69424771T2 (de)

Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0726578A1 (de) * 1995-02-09 1996-08-14 International Business Machines Corporation Leseverstärker mit mehreren Referenzen
US5650966A (en) * 1995-11-01 1997-07-22 Advanced Micro Devices, Inc. Temperature compensated reference for overerase correction circuitry in a flash memory
KR970051285A (ko) * 1995-12-30 1997-07-29 김주용 센스 증폭기의 차동 전압 증가 장치
EP0805454A1 (de) * 1996-04-30 1997-11-05 STMicroelectronics S.r.l. Abtastschaltung zum Lesen und Nachprüfen eines Speicherzelleninhalts
EP0814480B1 (de) * 1996-06-18 2003-12-17 STMicroelectronics S.r.l. Verfahren und Schaltung zum Lesen von nichtflüchtigen Speicherzellen mit niedriger Versorgungsspannung
EP0814484B1 (de) * 1996-06-18 2003-09-17 STMicroelectronics S.r.l. Nichtflüchtiger Speicher mit Einzelzellenreferenzsignalgeneratorschaltung zum Auslesen von Speicherzellen
DE69627152T2 (de) * 1996-09-30 2004-03-04 Stmicroelectronics S.R.L., Agrate Brianza Leseschaltung für Halbleiter-Speicherzellen
US5798967A (en) * 1997-02-22 1998-08-25 Programmable Microelectronics Corporation Sensing scheme for non-volatile memories
DE69827109D1 (de) * 1998-02-13 2004-11-25 St Microelectronics Srl Abfühlverstärker für nichtflüchtigen Speicher mit niedriger Spannung
US6038194A (en) * 1998-12-28 2000-03-14 Philips Electronics North America Corporation Memory decoder with zero static power
EP1063654B1 (de) * 1999-06-21 2003-03-05 STMicroelectronics S.r.l. Lesevorgang für nichtflüchtige Speicher mit einem mit der Lesespannung variablen Abtaststrom, und Anordnung zur Verwirkligung dieses Vorgangs
KR100308195B1 (ko) * 1999-09-30 2001-11-02 윤종용 반도체 메모리 장치의 감지 증폭기 회로
FR2807562B1 (fr) * 2000-04-10 2005-03-25 Dolphin Integration Sa Dispositif de lecture d'une memoire
DE60041056D1 (de) * 2000-08-16 2009-01-22 St Microelectronics Srl Sofortvergleichleseschaltung für einen nichtflüchtigen Speicher
US6584017B2 (en) 2001-04-05 2003-06-24 Saifun Semiconductors Ltd. Method for programming a reference cell
US6535434B2 (en) * 2001-04-05 2003-03-18 Saifun Semiconductors Ltd. Architecture and scheme for a non-strobed read sequence
US6567330B2 (en) * 2001-08-17 2003-05-20 Kabushiki Kaisha Toshiba Semiconductor memory device
US6917544B2 (en) 2002-07-10 2005-07-12 Saifun Semiconductors Ltd. Multiple use memory chip
US7136304B2 (en) 2002-10-29 2006-11-14 Saifun Semiconductor Ltd Method, system and circuit for programming a non-volatile memory array
US6963505B2 (en) 2002-10-29 2005-11-08 Aifun Semiconductors Ltd. Method circuit and system for determining a reference voltage
US6992932B2 (en) 2002-10-29 2006-01-31 Saifun Semiconductors Ltd Method circuit and system for read error detection in a non-volatile memory array
US6967896B2 (en) * 2003-01-30 2005-11-22 Saifun Semiconductors Ltd Address scramble
US7178004B2 (en) 2003-01-31 2007-02-13 Yan Polansky Memory array programming circuit and a method for using the circuit
US7142464B2 (en) * 2003-04-29 2006-11-28 Saifun Semiconductors Ltd. Apparatus and methods for multi-level sensing in a memory array
US7652930B2 (en) * 2004-04-01 2010-01-26 Saifun Semiconductors Ltd. Method, circuit and system for erasing one or more non-volatile memory cells
US7755938B2 (en) * 2004-04-19 2010-07-13 Saifun Semiconductors Ltd. Method for reading a memory array with neighbor effect cancellation
US7095655B2 (en) * 2004-08-12 2006-08-22 Saifun Semiconductors Ltd. Dynamic matching of signal path and reference path for sensing
US7638850B2 (en) 2004-10-14 2009-12-29 Saifun Semiconductors Ltd. Non-volatile memory structure and method of fabrication
US7257025B2 (en) * 2004-12-09 2007-08-14 Saifun Semiconductors Ltd Method for reading non-volatile memory cells
US8053812B2 (en) 2005-03-17 2011-11-08 Spansion Israel Ltd Contact in planar NROM technology
US8400841B2 (en) * 2005-06-15 2013-03-19 Spansion Israel Ltd. Device to program adjacent storage cells of different NROM cells
US7184313B2 (en) * 2005-06-17 2007-02-27 Saifun Semiconductors Ltd. Method circuit and system for compensating for temperature induced margin loss in non-volatile memory cells
EP1746645A3 (de) 2005-07-18 2009-01-21 Saifun Semiconductors Ltd. Speicherzellenanordnung mit sub-minimalem Wortleitungsabstand und Verfahren zu deren Herstellung
US20070036007A1 (en) * 2005-08-09 2007-02-15 Saifun Semiconductors, Ltd. Sticky bit buffer
US7668017B2 (en) 2005-08-17 2010-02-23 Saifun Semiconductors Ltd. Method of erasing non-volatile memory cells
US7808818B2 (en) 2006-01-12 2010-10-05 Saifun Semiconductors Ltd. Secondary injection for NROM
US7760554B2 (en) 2006-02-21 2010-07-20 Saifun Semiconductors Ltd. NROM non-volatile memory and mode of operation
US7692961B2 (en) 2006-02-21 2010-04-06 Saifun Semiconductors Ltd. Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection
US8253452B2 (en) 2006-02-21 2012-08-28 Spansion Israel Ltd Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same
US20070255889A1 (en) * 2006-03-22 2007-11-01 Yoav Yogev Non-volatile memory device and method of operating the device
US7701779B2 (en) 2006-04-27 2010-04-20 Sajfun Semiconductors Ltd. Method for programming a reference cell
US7590001B2 (en) 2007-12-18 2009-09-15 Saifun Semiconductors Ltd. Flash memory with optimized write sector spares

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5693363A (en) * 1979-12-04 1981-07-28 Fujitsu Ltd Semiconductor memory
JPS60167198A (ja) * 1984-02-09 1985-08-30 Toshiba Corp 半導体記憶回路
US5040148A (en) * 1988-06-24 1991-08-13 Kabushiki Kaisha Toshiba Semiconductor memory device with address transition actuated dummy cell
US5142495A (en) * 1989-03-10 1992-08-25 Intel Corporation Variable load for margin mode
US5293345A (en) * 1989-06-12 1994-03-08 Kabushiki Kaisha Toshiba Semiconductor memory device having a data detection circuit with two reference potentials

Also Published As

Publication number Publication date
EP0678871B1 (de) 2000-05-31
JP3198027B2 (ja) 2001-08-13
DE69424771D1 (de) 2000-07-06
EP0678871A1 (de) 1995-10-25
JPH0836884A (ja) 1996-02-06
US5627790A (en) 1997-05-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee