IT8621126A0 - Processo per l'ottenimento di circuiti passivi a strato sottile con linee resistive a differenti resistenze di strato e circuito passivo realizzato con il processo suddetto. - Google Patents

Processo per l'ottenimento di circuiti passivi a strato sottile con linee resistive a differenti resistenze di strato e circuito passivo realizzato con il processo suddetto.

Info

Publication number
IT8621126A0
IT8621126A0 IT8621126A IT2112686A IT8621126A0 IT 8621126 A0 IT8621126 A0 IT 8621126A0 IT 8621126 A IT8621126 A IT 8621126A IT 2112686 A IT2112686 A IT 2112686A IT 8621126 A0 IT8621126 A0 IT 8621126A0
Authority
IT
Italy
Prior art keywords
passive
circuit made
thin layer
resistances
obtaining thin
Prior art date
Application number
IT8621126A
Other languages
English (en)
Other versions
IT1197776B (it
IT8621126A1 (it
Inventor
Giampiero Ferraris
Antonio Tersalvi
Original Assignee
Gte Telecom Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gte Telecom Spa filed Critical Gte Telecom Spa
Priority to IT21126/86A priority Critical patent/IT1197776B/it
Publication of IT8621126A0 publication Critical patent/IT8621126A0/it
Priority to DE8787201179T priority patent/DE3772900D1/de
Priority to EP87201179A priority patent/EP0256568B1/en
Priority to JP62173102A priority patent/JPH07101730B2/ja
Priority to NO872916A priority patent/NO173037C/no
Publication of IT8621126A1 publication Critical patent/IT8621126A1/it
Application granted granted Critical
Publication of IT1197776B publication Critical patent/IT1197776B/it
Priority to US07/627,568 priority patent/US5152869A/en
Priority to GR91401653T priority patent/GR3003237T3/el

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/702—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof
    • H01L21/707—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof of thin-film circuits or parts thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49082—Resistor making
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49082—Resistor making
    • Y10T29/49099—Coating resistive material on a base

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Non-Adjustable Resistors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Microwave Amplifiers (AREA)
  • Control Of Motors That Do Not Use Commutators (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)
IT21126/86A 1986-07-15 1986-07-15 Processo per l'ottenimento di circuiti passivi a strato sottile con linee resistive a differenti resistenze di strato e circuito passivo realizzato con il processo suddetto IT1197776B (it)

Priority Applications (7)

Application Number Priority Date Filing Date Title
IT21126/86A IT1197776B (it) 1986-07-15 1986-07-15 Processo per l'ottenimento di circuiti passivi a strato sottile con linee resistive a differenti resistenze di strato e circuito passivo realizzato con il processo suddetto
DE8787201179T DE3772900D1 (de) 1986-07-15 1987-06-19 Verfahren zum herstellen einer duennschichtschaltung und nach diesem verfahren hergestellte passive schaltung.
EP87201179A EP0256568B1 (en) 1986-07-15 1987-06-19 Process for obtaining thin-film circuits and passive circuit made by said process
JP62173102A JPH07101730B2 (ja) 1986-07-15 1987-07-13 薄膜受動回路の製造方法とその方法によって製造される薄膜受動回路
NO872916A NO173037C (no) 1986-07-15 1987-07-13 Fremgangsmaate for aa tilveiebringe passive tynnsjikt-kretser, og en passiv krets fremstilt ved fremgangsmaaten
US07/627,568 US5152869A (en) 1986-07-15 1990-12-11 Process for obtaining passive thin-layer circuits with resistive lines having different layer resistances and passive circuit made by said process
GR91401653T GR3003237T3 (en) 1986-07-15 1991-11-29 Process for obtaining thin-film circuits and passive circuit made by said process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT21126/86A IT1197776B (it) 1986-07-15 1986-07-15 Processo per l'ottenimento di circuiti passivi a strato sottile con linee resistive a differenti resistenze di strato e circuito passivo realizzato con il processo suddetto

Publications (3)

Publication Number Publication Date
IT8621126A0 true IT8621126A0 (it) 1986-07-15
IT8621126A1 IT8621126A1 (it) 1988-01-15
IT1197776B IT1197776B (it) 1988-12-06

Family

ID=11177117

Family Applications (1)

Application Number Title Priority Date Filing Date
IT21126/86A IT1197776B (it) 1986-07-15 1986-07-15 Processo per l'ottenimento di circuiti passivi a strato sottile con linee resistive a differenti resistenze di strato e circuito passivo realizzato con il processo suddetto

Country Status (7)

Country Link
US (1) US5152869A (it)
EP (1) EP0256568B1 (it)
JP (1) JPH07101730B2 (it)
DE (1) DE3772900D1 (it)
GR (1) GR3003237T3 (it)
IT (1) IT1197776B (it)
NO (1) NO173037C (it)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1197776B (it) * 1986-07-15 1988-12-06 Gte Telecom Spa Processo per l'ottenimento di circuiti passivi a strato sottile con linee resistive a differenti resistenze di strato e circuito passivo realizzato con il processo suddetto
IT1216135B (it) * 1988-03-18 1990-02-22 Sits Soc It Telecom Siemens Dielettrico mediante deposizioni in processo per la realizzazione di vuoto di metalli, e relativo fori metallizzati in un substrato prodotto ottenuto.
US5310965A (en) * 1991-08-28 1994-05-10 Nec Corporation Multi-level wiring structure having an organic interlayer insulating film
US5288951A (en) * 1992-10-30 1994-02-22 At&T Bell Laboratories Copper-based metallizations for hybrid integrated circuits
US5352331A (en) * 1993-12-07 1994-10-04 Trw Inc. Cermet etch technique for integrated circuits
EP0697723A3 (en) * 1994-08-15 1997-04-16 Ibm Method of metallizing an insulating layer
US6498385B1 (en) 1999-09-01 2002-12-24 International Business Machines Corporation Post-fuse blow corrosion prevention structure for copper fuses
DE10039710B4 (de) * 2000-08-14 2017-06-22 United Monolithic Semiconductors Gmbh Verfahren zur Herstellung passiver Bauelemente auf einem Halbleitersubstrat
US6475400B2 (en) 2001-02-26 2002-11-05 Trw Inc. Method for controlling the sheet resistance of thin film resistors
DE10213940A1 (de) * 2002-03-28 2003-10-30 Bosch Gmbh Robert Verfahren zur Herstellung einer auf einem Substrat aufgebauten Dünnschichtanordnung, insbesondere Sensoranordnung sowie eine Dünnschichtanordnung
TWI266568B (en) * 2004-03-08 2006-11-11 Brain Power Co Method for manufacturing embedded thin film resistor on printed circuit board
US7199016B2 (en) * 2004-08-13 2007-04-03 Raytheon Company Integrated circuit resistor
JP2009295346A (ja) * 2008-06-03 2009-12-17 Hitachi Cable Ltd 電気接点層付金属材及びその製造方法
US8242876B2 (en) 2008-09-17 2012-08-14 Stmicroelectronics, Inc. Dual thin film precision resistance trimming
US8659085B2 (en) 2010-08-24 2014-02-25 Stmicroelectronics Pte Ltd. Lateral connection for a via-less thin film resistor
US8436426B2 (en) * 2010-08-24 2013-05-07 Stmicroelectronics Pte Ltd. Multi-layer via-less thin film resistor
US8400257B2 (en) 2010-08-24 2013-03-19 Stmicroelectronics Pte Ltd Via-less thin film resistor with a dielectric cap
US8927909B2 (en) 2010-10-11 2015-01-06 Stmicroelectronics, Inc. Closed loop temperature controlled circuit to improve device stability
US8809861B2 (en) 2010-12-29 2014-08-19 Stmicroelectronics Pte Ltd. Thin film metal-dielectric-metal transistor
US9159413B2 (en) 2010-12-29 2015-10-13 Stmicroelectronics Pte Ltd. Thermo programmable resistor based ROM
US8981527B2 (en) * 2011-08-23 2015-03-17 United Microelectronics Corp. Resistor and manufacturing method thereof
US8526214B2 (en) 2011-11-15 2013-09-03 Stmicroelectronics Pte Ltd. Resistor thin film MTP memory
US9140735B2 (en) 2013-05-03 2015-09-22 Infineon Technologies Ag Integration of current measurement in wiring structure of an electronic circuit

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3423821A (en) * 1965-03-18 1969-01-28 Hitachi Ltd Method of producing thin film integrated circuits
US4112196A (en) * 1977-01-24 1978-09-05 National Micronetics, Inc. Beam lead arrangement for microelectronic devices
JPS55162254A (en) * 1979-06-05 1980-12-17 Nec Corp Composite integrated circuit
US4226932A (en) * 1979-07-05 1980-10-07 Gte Automatic Electric Laboratories Incorporated Titanium nitride as one layer of a multi-layered coating intended to be etched
JPS57113264A (en) * 1980-12-29 1982-07-14 Fujitsu Ltd Manufacture of mis type capacitor
DE3200983A1 (de) * 1982-01-14 1983-07-21 Siemens AG, 1000 Berlin und 8000 München Elektrisches netzwerk
IT1197776B (it) * 1986-07-15 1988-12-06 Gte Telecom Spa Processo per l'ottenimento di circuiti passivi a strato sottile con linee resistive a differenti resistenze di strato e circuito passivo realizzato con il processo suddetto
US4801469A (en) * 1986-08-07 1989-01-31 The United States Of America As Represented By The Department Of Energy Process for obtaining multiple sheet resistances for thin film hybrid microcircuit resistors

Also Published As

Publication number Publication date
NO872916L (no) 1988-01-18
JPH07101730B2 (ja) 1995-11-01
GR3003237T3 (en) 1993-02-17
IT1197776B (it) 1988-12-06
NO872916D0 (no) 1987-07-13
NO173037C (no) 1993-10-13
NO173037B (no) 1993-07-05
US5152869A (en) 1992-10-06
EP0256568B1 (en) 1991-09-11
IT8621126A1 (it) 1988-01-15
EP0256568A3 (en) 1988-08-10
JPS6329961A (ja) 1988-02-08
DE3772900D1 (de) 1991-10-17
EP0256568A2 (en) 1988-02-24

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Legal Events

Date Code Title Description
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19960710