DE68925656D1 - Integrierte Schaltung mit einer Verbindungsverdrahtung - Google Patents

Integrierte Schaltung mit einer Verbindungsverdrahtung

Info

Publication number
DE68925656D1
DE68925656D1 DE68925656T DE68925656T DE68925656D1 DE 68925656 D1 DE68925656 D1 DE 68925656D1 DE 68925656 T DE68925656 T DE 68925656T DE 68925656 T DE68925656 T DE 68925656T DE 68925656 D1 DE68925656 D1 DE 68925656D1
Authority
DE
Germany
Prior art keywords
integrated circuit
connection wiring
wiring
connection
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68925656T
Other languages
English (en)
Other versions
DE68925656T2 (de
Inventor
Shigeru C O Patent Divi Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE68925656D1 publication Critical patent/DE68925656D1/de
Application granted granted Critical
Publication of DE68925656T2 publication Critical patent/DE68925656T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE68925656T 1988-03-29 1989-03-29 Integrierte Schaltung mit einer Verbindungsverdrahtung Expired - Fee Related DE68925656T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63073286A JPH077809B2 (ja) 1988-03-29 1988-03-29 集積回路

Publications (2)

Publication Number Publication Date
DE68925656D1 true DE68925656D1 (de) 1996-03-28
DE68925656T2 DE68925656T2 (de) 1996-08-01

Family

ID=13513753

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68925656T Expired - Fee Related DE68925656T2 (de) 1988-03-29 1989-03-29 Integrierte Schaltung mit einer Verbindungsverdrahtung

Country Status (5)

Country Link
US (1) US4906872A (de)
EP (1) EP0335697B1 (de)
JP (1) JPH077809B2 (de)
KR (1) KR950010871B1 (de)
DE (1) DE68925656T2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5012427A (en) * 1988-01-30 1991-04-30 Kabushiki Kaisha Toshiba Semiconductor integrated circuit and method of manufacturing the same
US5233235A (en) * 1988-08-16 1993-08-03 Siemens Aktiengesellschaft On-chip intermediate driver for discrete WSI systems
JP2622612B2 (ja) * 1989-11-14 1997-06-18 三菱電機株式会社 集積回路
US5079442A (en) * 1990-03-28 1992-01-07 Advanced Micro Devices, Inc. Apparatus adaptable for use as a replacement output driver in a signal generating circuit
JP3017789B2 (ja) * 1990-10-18 2000-03-13 三菱電機株式会社 半導体集積回路装置のレイアウト設計方法
KR930008310B1 (ko) * 1991-02-05 1993-08-27 삼성전자 주식회사 반도체 메모리장치의 워드라인드라이버단 배치방법
KR940008722B1 (ko) * 1991-12-04 1994-09-26 삼성전자 주식회사 반도체 메모리 장치의 워드라인 드라이버 배열방법
JP2826446B2 (ja) * 1992-12-18 1998-11-18 三菱電機株式会社 半導体集積回路装置及びその設計方法
DE4422456B4 (de) * 1993-06-30 2004-07-01 Intel Corporation, Santa Clara Taktverteilungssystem für einen Mikroprozessor
JP3112784B2 (ja) * 1993-09-24 2000-11-27 日本電気株式会社 クロック信号分配回路
US5416431A (en) * 1994-03-21 1995-05-16 At&T Corp. Integrated circuit clock driver having improved layout
US5663677A (en) * 1995-03-30 1997-09-02 Lucent Technologies Inc. Integrated circuit multi-level interconnection technique
US5751650A (en) * 1995-10-02 1998-05-12 Matsushita Electronics Corporation Electric signal supply circuit and semiconductor memory device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55115352A (en) * 1979-02-27 1980-09-05 Fujitsu Ltd Clock distributing circuit of ic device
US4577276A (en) * 1983-09-12 1986-03-18 At&T Bell Laboratories Placement of components on circuit substrates
JPS6182525A (ja) * 1984-09-29 1986-04-26 Toshiba Corp 半導体集積回路装置
JPS6341048A (ja) * 1986-08-06 1988-02-22 Mitsubishi Electric Corp 標準セル方式大規模集積回路

Also Published As

Publication number Publication date
KR950010871B1 (ko) 1995-09-25
JPH077809B2 (ja) 1995-01-30
US4906872A (en) 1990-03-06
JPH01246845A (ja) 1989-10-02
EP0335697A3 (en) 1990-05-23
EP0335697A2 (de) 1989-10-04
DE68925656T2 (de) 1996-08-01
KR890015409A (ko) 1989-10-30
EP0335697B1 (de) 1996-02-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee