IT201700079201A1 - Metodo di allineamento di maschere fotolitografiche e relativo procedimento di fabbricazione di circuiti integrati in una fetta di materiale semiconduttore - Google Patents

Metodo di allineamento di maschere fotolitografiche e relativo procedimento di fabbricazione di circuiti integrati in una fetta di materiale semiconduttore

Info

Publication number
IT201700079201A1
IT201700079201A1 IT102017000079201A IT201700079201A IT201700079201A1 IT 201700079201 A1 IT201700079201 A1 IT 201700079201A1 IT 102017000079201 A IT102017000079201 A IT 102017000079201A IT 201700079201 A IT201700079201 A IT 201700079201A IT 201700079201 A1 IT201700079201 A1 IT 201700079201A1
Authority
IT
Italy
Prior art keywords
photolitographic
masks
slice
alignment
manufacture
Prior art date
Application number
IT102017000079201A
Other languages
English (en)
Inventor
Gianluca Eugeni
Original Assignee
Lfoundry Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lfoundry Srl filed Critical Lfoundry Srl
Priority to IT102017000079201A priority Critical patent/IT201700079201A1/it
Priority to EP18747019.0A priority patent/EP3652588B1/en
Priority to CN201880046713.8A priority patent/CN110892331B/zh
Priority to US16/630,129 priority patent/US10895809B2/en
Priority to KR1020207004215A priority patent/KR102633183B1/ko
Priority to JP2020501339A priority patent/JP7249994B2/ja
Priority to PCT/IB2018/055208 priority patent/WO2019012499A1/en
Publication of IT201700079201A1 publication Critical patent/IT201700079201A1/it

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/7084—Position of mark on substrate, i.e. position in (x, y, z) of mark, e.g. buried or resist covered mark, mark on rearside, at the substrate edge, in the circuit area, latent image mark, marks in plural levels
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70475—Stitching, i.e. connecting image fields to produce a device field, the field occupied by a device such as a memory chip, processor chip, CCD, flat panel display

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
IT102017000079201A 2017-07-13 2017-07-13 Metodo di allineamento di maschere fotolitografiche e relativo procedimento di fabbricazione di circuiti integrati in una fetta di materiale semiconduttore IT201700079201A1 (it)

Priority Applications (7)

Application Number Priority Date Filing Date Title
IT102017000079201A IT201700079201A1 (it) 2017-07-13 2017-07-13 Metodo di allineamento di maschere fotolitografiche e relativo procedimento di fabbricazione di circuiti integrati in una fetta di materiale semiconduttore
EP18747019.0A EP3652588B1 (en) 2017-07-13 2018-07-13 Method for the alignment of photolithographic masks, corresponding process for manufacturing integrated circuits in a wafer of semiconductor material and corresponding optical photolithography system
CN201880046713.8A CN110892331B (zh) 2017-07-13 2018-07-13 对准光刻掩膜板的方法和在半导体材料的晶圆中制造集成电路的相应工艺
US16/630,129 US10895809B2 (en) 2017-07-13 2018-07-13 Method for the alignment of photolithographic masks and corresponding process for manufacturing integrated circuits in a wafer of semiconductor material
KR1020207004215A KR102633183B1 (ko) 2017-07-13 2018-07-13 포토리소그래피 마스크의 정렬 방법 및 반도체 재료의 웨이퍼에서 집적 회로를 제조하기 위한 대응 공정 방법
JP2020501339A JP7249994B2 (ja) 2017-07-13 2018-07-13 フォトリソグラフィマスクを整列させる方法及び半導体材料のウェファの集積回路を製造する対応する工程
PCT/IB2018/055208 WO2019012499A1 (en) 2017-07-13 2018-07-13 METHOD FOR ALIGNING PHOTOLITHOGRAPHIC MASKS AND CORRESPONDING METHOD FOR MANUFACTURING INTEGRATED CIRCUITS IN A SEMICONDUCTOR MATERIAL WAFER

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT102017000079201A IT201700079201A1 (it) 2017-07-13 2017-07-13 Metodo di allineamento di maschere fotolitografiche e relativo procedimento di fabbricazione di circuiti integrati in una fetta di materiale semiconduttore

Publications (1)

Publication Number Publication Date
IT201700079201A1 true IT201700079201A1 (it) 2019-01-13

Family

ID=60202369

Family Applications (1)

Application Number Title Priority Date Filing Date
IT102017000079201A IT201700079201A1 (it) 2017-07-13 2017-07-13 Metodo di allineamento di maschere fotolitografiche e relativo procedimento di fabbricazione di circuiti integrati in una fetta di materiale semiconduttore

Country Status (7)

Country Link
US (1) US10895809B2 (it)
EP (1) EP3652588B1 (it)
JP (1) JP7249994B2 (it)
KR (1) KR102633183B1 (it)
CN (1) CN110892331B (it)
IT (1) IT201700079201A1 (it)
WO (1) WO2019012499A1 (it)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102020126211A1 (de) * 2020-05-28 2021-12-02 Taiwan Semiconductor Manufacturing Co. Ltd. Photolithographie-Ausrichtungsprozess für gebondete Wafer
KR20220044016A (ko) 2020-09-29 2022-04-06 삼성전자주식회사 극자외선(euv) 포토마스크 및 이를 이용한 반도체 장치 제조 방법
CN113219797B (zh) * 2021-03-25 2023-11-17 北海惠科半导体科技有限公司 晶圆半导体产品及其制作方法
CN113219799B (zh) * 2021-03-25 2024-03-19 北海惠科半导体科技有限公司 晶圆半导体产品、掩膜版以及光刻机
TWI779874B (zh) * 2021-10-12 2022-10-01 鴻海精密工業股份有限公司 光刻量測機及其操作方法
CN114089608B (zh) * 2021-11-30 2024-01-23 上海华力集成电路制造有限公司 拼接工艺中的修正方法
US20230281779A1 (en) * 2022-03-03 2023-09-07 Kla Corporation Measurement of stitching error using split targets

Citations (5)

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Publication number Priority date Publication date Assignee Title
US5440138A (en) * 1993-01-06 1995-08-08 Nikon Corporation Exposure method
US6104471A (en) * 1995-06-26 2000-08-15 Nikon Corporation Exposure apparatus and method wherein the magnification of the projection optical system compensates for physical changes in the substrate
US20040156027A1 (en) * 2002-12-19 2004-08-12 Asml Netherlands B.V. Lithographic projection mask, device manufacturing method, and device manufactured thereby
US20080032203A1 (en) * 2006-08-04 2008-02-07 Asml Netherlands B.V. Lithographic method and patterning device
US20120202138A1 (en) * 2011-02-03 2012-08-09 Micrel, Inc. Single Field Zero Mask For Increased Alignment Accuracy in Field Stitching

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Publication number Priority date Publication date Assignee Title
JP3617046B2 (ja) * 1995-05-29 2005-02-02 株式会社ニコン 露光方法
US6455211B1 (en) * 1998-02-09 2002-09-24 Canon Kabushiki Kaisha Pattern transfer method and apparatus, and device manufacturing method
JP2002229215A (ja) * 2001-01-30 2002-08-14 Nikon Corp 露光方法及び露光装置
JP2003249640A (ja) * 2002-02-22 2003-09-05 Sony Corp 固体撮像素子の製造方法
JP2003248329A (ja) * 2002-02-26 2003-09-05 Canon Inc 半導体装置及びその製造方法
JP4976210B2 (ja) * 2007-06-20 2012-07-18 三菱電機株式会社 露光方法およびイメージセンサの製造方法
JP2013033870A (ja) * 2011-08-02 2013-02-14 Canon Inc 半導体デバイスおよびその製造方法
US9703214B2 (en) * 2013-07-19 2017-07-11 Canon Kabushiki Kaisha Lithography apparatus, lithography method, and article manufacturing method
JP6271922B2 (ja) * 2013-09-10 2018-01-31 キヤノン株式会社 位置を求める方法、露光方法、露光装置、および物品の製造方法
CN104808451B (zh) * 2015-05-15 2017-07-18 合肥京东方光电科技有限公司 一种对位曝光方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5440138A (en) * 1993-01-06 1995-08-08 Nikon Corporation Exposure method
US6104471A (en) * 1995-06-26 2000-08-15 Nikon Corporation Exposure apparatus and method wherein the magnification of the projection optical system compensates for physical changes in the substrate
US20040156027A1 (en) * 2002-12-19 2004-08-12 Asml Netherlands B.V. Lithographic projection mask, device manufacturing method, and device manufactured thereby
US20080032203A1 (en) * 2006-08-04 2008-02-07 Asml Netherlands B.V. Lithographic method and patterning device
US20120202138A1 (en) * 2011-02-03 2012-08-09 Micrel, Inc. Single Field Zero Mask For Increased Alignment Accuracy in Field Stitching

Also Published As

Publication number Publication date
US10895809B2 (en) 2021-01-19
US20200166853A1 (en) 2020-05-28
JP2020527254A (ja) 2020-09-03
JP7249994B2 (ja) 2023-03-31
EP3652588A1 (en) 2020-05-20
CN110892331A (zh) 2020-03-17
WO2019012499A1 (en) 2019-01-17
CN110892331B (zh) 2022-11-01
KR20200029008A (ko) 2020-03-17
WO2019012499A8 (en) 2019-04-04
EP3652588B1 (en) 2023-07-05
KR102633183B1 (ko) 2024-02-01

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